TMCS1100A2QDRQ1

TMCS1100-Q1 ZHCSM20 – JUNE 2021 TMCS1100-Q1 具有 ±600V 工作电压的 AEC-Q100 1% 高精度、基本型隔离、霍 尔效应电流传感器 1 特性 3 说明 • 符合面向汽车应用的 AEC-Q100 标准 – 温度等级 1：– 40 ° C 至 125 ° C、 T A • 提供功能安全 – 可帮助进行功能安全系统设计的文档 • 总体误差：典型值 ±0.4%，最大值 ±0.9%，–40°C 至 85°C – 灵敏度误差：±0.4% – 失调电压误差：7mA – 温漂：0.04mA/°C – 线性误差：0.05% • 使用寿命和环境漂移：400 V Material group II Rated mains voltage ≤ 150 VRMS I-IV Rated mains voltage ≤ 300 VRMS I-III Maximum repetitive peak isolation voltage AC voltage (bipolar) 600 VPK Maximum working isolation voltage AC voltage (sine wave); Time Dependent Dielectric Breakdown test, see Insulation Lifetime. 424 VRMS DC voltage 600 VDC 4242 VPK VPK Overvoltage category VIORM VIOWM VIOTM Maximum transient isolation voltage VTEST = VIOTM = 4242VPK, t = 60 s (qualification); VTEST = 1.2 × VIOTM = 5090VPK, t = 1 s (100% production) VIOSM Maximum surge isolation voltage(2) Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 1.3 × VIOSM = 7800VPK (qualification) 6000 Method a: After I/O safety test subgroup 2/3, Vini = VIOTM = 4242VPK, tini = 60 s; Vpd(m) = 1.2 × VIORM = 700VPK, tm = 10 s ≤5 Method a: After environmental tests subgroup 1, Vini = VIOTM = 4242VPK, tini = 60 s; Vpd(m) = 1.2 × VIORM = 700VPK, tm = 10 s ≤5 Method b3: At routine test (100% production) and preconditioning (type test) Vini = 1.2 × VIOTM = 5090VPK, tini = 1 s; Vpd(m) = 1.2 × VIOTM = 5090VPK, tm = 1 s ≤5 VIO = 0.4 sin (2πft), f = 1 MHz 0.6 pF VIO = 500 V, TA = 25°C >1012 Ω VIO = 500 V, 100°C ≤ TA ≤ 125°C >1011 Ω VIO = 500 V at TS = 150°C >109 Ω qpd Apparent charge(3) Barrier capacitance, input to output(4) CIO RIO Isolation resistance, input to output(4) Pollution degree pC 2 UL 1577 VISO (1) (2) Withstand isolation voltage VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 × VISO, t = 1 s (100% production) 3000 VRMS Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Take care to maintain the creepage and clearance distance of the board design to make sure that the mounting pads of the isolator on the printedcircuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications. Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 5 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 (3) (4) Apparent charge is electrical discharge caused by a partial discharge (pd). All pins on each side of the barrier tied together creating a two-terminal device 7.7 Safety-Related Certifications UL UL 1577 Component Recognition Program Certified according to IEC 62368-1 CB File number: E181974 Certificate number: US-36733-UL 7.8 Safety Limiting Values Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. PARAMETER MIN IS Safety input current (side 1)(1) IS Safety input, output, or supply current (side 2)(1) RθJA = 36.6°C/W, VI = 5 V, TJ = 150°C, TA = 25°C, see Thermal Derating Curve, Side 2. PS Safety input, output, or total power(1) RθJA = 36.6°C/W, TJ = 150°C, TA = 25°C, see Thermal Derating Curve, Both Sides. TS Safety temperature(1) (1) 6 TEST CONDITIONS RθJA = 36.6°C/W, TJ = 150°C, TA = 25°C, see Thermal Derating Curve, Side 1. TYP MAX UNIT 30 A 0.68 3.4 W 150 ℃ The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be exceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on the TMCS1100EVM . Use these equations to calculate the value for each parameter: TJ = TA + RθJA × P, where P is the power dissipated in the device. TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature. PS = IS × VI, where VI is the maximum input voltage. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 7.9 Electrical Characteristics at TA = 25°C, VS = 5 V, VREF = 2.5 V (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT OUTPUT Sensitivity(7) mV/A TMCS1100A3-Q1 200 mV/A TMCS1100A4-Q1 400 mV/A 0.05 V ≤ VOUT ≤ VS – 0.2 V, TA= 25ºC ±0.2% ±0.7% 0.05 V ≤ VOUT ≤ VS – 0.2 V, TA= 25ºC -0.47% ±1.02% 0.05 V ≤ VOUT ≤ VS – 0.2 V, TA= –40º C to +85ºC ±0.4% ±0.85% 0.05 V ≤ VOUT ≤ VS – 0.2 V, TA= –40º C to +125ºC ±0.5% ±1.15% Output voltage offset error(1) Output voltage offset drift Offset error, RTI(1) (3) Offset error temperature drift, RTI(3) PSRR mV/A 100 Sensitivity error, including lifetime and environmental drift (5) Nonlinearity error IOS 50 TMCS1100A2-Q1 Sensitivity error Sensitivity error VOE TMCS1100A1-Q1 Power-supply rejection ratio CMTI Common mode transient immunity CMRR Common mode rejection ratio, RTI(3) RVRR Reference voltage rejection ratio, output referred Noise density, RTI(3) VOUT = 0.5 V to VS – 0.5 V ±0.05% TMCS1100A1-Q1 ±0.4 ±3 mV TMCS1100A2-Q1 ±0.6 ±5 mV TMCS1100A3-Q1 ±0.8 ±8 mV TMCS1100A4-Q1 ±2.2 ±19 mV TMCS1100A1-Q1, TA= –40ºC to +125ºC ±3.7 ±12 µV/℃ TMCS1100A2-Q1, TA= –40ºC to +125ºC ±4 ±19 µV/℃ TMCS1100A3-Q1, TA= –40ºC to +125ºC ±8.2 ±35 µV/℃ TMCS1100A4-Q1, TA= –40ºC to +125ºC ±26 ±138 µV/℃ TMCS1100A1-Q1 ±8 ±60 mA TMCS1100A2-Q1 ±6 ±50 mA TMCS1100A3-Q1 ±4 ±40 mA TMCS1100A4-Q1 ±5.5 ±47.5 mA TMCS1100A1-Q1, TA= –40ºC to +125ºC ±74 ±240 µA/°C TMCS1100A2-Q1, TA= –40ºC to +125ºC ±40 ±190 µA/°C TMCS1100A3-Q1, TA= –40ºC to +125ºC ±41 ±175 µA/°C TMCS1100A4-Q1, TA= –40ºC to +125ºC ±65 ±345 µA/°C TMCS1100A1-Q1-A3-Q1, VS = 3 V to 5.5 V, VREF = VS/2, TA= –40ºC to +125ºC ±1 ±2 mV/V TMCS1100A4-Q1, VS = 4.5 V to 5.5 V, VREF = VS/2, TA= –40ºC to +125ºC ±1 ±3 mV/V 50 kV/µs DC to 60Hz 5 uA/V VREF = 0.5 V to 4.5 V, TMCS1100A1-Q1A3-Q1 1 3.5 VREF = 0.5 V to 4.5 V, TMCS1100A4-Q1 1.5 8 TMCS1100A1-Q1 380 μA/√Hz TMCS1100A2-Q1 330 μA/√Hz TMCS1100A3-Q1 300 μA/√Hz TMCS1100A4-Q1 225 μA/√Hz IN+ to IN– 1.8 mΩ mV/V mV/V INPUT RIN Input conductor resistance Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 7 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 at TA = 25°C, VS = 5 V, VREF = 2.5 V (unless otherwise noted) PARAMETERS G TEST CONDITIONS MIN TYP MAX UNIT Input conductor resistance temperature drift TA= –40ºC to +125ºC 4.4 μΩ/°C Magnetic coupling factor TA= 25ºC 1.1 mT/A TA= 25ºC 30 A 25 A 22.5 A IIN,max Allowable continuous RMS current (4) VREF Reference input voltage TA= 85ºC TA= 105ºC TA= 125ºC 16 VGND VREF input current VREF = GND, VS VREF external source impedance Maximum source impedance of external circuit driving VREF ±1 A VS V ±5 µA 5 kΩ VOLTAGE OUTPUT ZOUT Closed loop output impedance f = 1 Hz to 1 kHz f = 10 kHz 0.2 Ω 2 Ω Maximum capacitive load No sustained oscillation Short circuit output current VOUT short to ground, short to VS Swing to VS power-supply rail RL = 10 kΩ to GND, TA= –40ºC to +125º C Swing to GND, current driven RL = 10 kΩ to GND, TA= –40ºC to +125º C VGND + 5 VGND + 10 mV TMCS1100A1-Q1-A3-Q1, RL = 10 kΩ to GND, TA= –40ºC to +125ºC, VREF = GND, IIN = 0 A VGND + 5 VGND + 20 mV TMCS1100A4-Q1, RL = 10 kΩ to GND, TA= –40ºC to +125ºC, VREF = GND, IIN =0A VGND + 20 VGND + 55 mV Swing to GND, zero current 1 nF 90 mA VS – V – 0.1 0.02 S V FREQUENCY RESPONSE BW SR tr tp tr,SC tp,SC Bandwidth(6) –3-dB Bandwidth 80 kHz Slew rate(6) Slew rate of output amplifier during single transient step. 1.5 V/µs Time between the input current step reaching 90% of final value to the sensor output reaching 90% of its final value, for a 1V output transition. 6.5 µs delay(6) Time between the input current step reaching 10% of final value to the sensor output reaching 10% of its final value, for a 1V output transition. 4 µs Current overload response time(6) Time between the input current step reaching 90% of final value to the sensor output reaching 90% of its final value. Input current step amplitude is twice full scale output range. 5 µs Current overload propagation delay(6) Time between the input current step reaching 10% of final value to the sensor output reaching 10% of its final value. Input current step amplitude is twice full scale output range. 3 µs Current overload recovery time Time from end of current causing output saturation condition to valid output 15 µs Response time(6) Propagation POWER SUPPLY 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 at TA = 25°C, VS = 5 V, VREF = 2.5 V (unless otherwise noted) PARAMETERS IQ Quiescent current Power on time (1) (2) (3) (4) (5) (6) (7) TEST CONDITIONS TA = 25ºC MIN TYP MAX 4.5 5.5 mA 6 mA TA = –40ºC to +125ºC Time from VS > 3 V to valid output 25 UNIT ms Excludes effect of external magnetic fields. See the Accuracy Parameters section for details to calculate error due to external magnetic fields. Excluding magnetic coupling from layout deviation from recommended layout. See the Layout section for more information. RTI = referred-to-input. Output voltage is divided by device sensitivity to refer signal to input current. See the Parameter Measurement Information section. Thermally limited by junction temperature. Applies when device mounted on TMCS1100EVM . For more details, see the Safe Operating Area section. Lifetime and environmental drift specifications based on three lot AEC-Q100 qualification stress test results. Typical values are population mean+1σ from worst case stress test condition. Min/max are tested device population mean±6σ; devices tested in AECQ100 qualification stayed within min/max limits for all stress conditions. See Lifetime and Environmental Stability section for more details. Refer to the Transient Response section for details of frequency and transient response of the device. Centered parameter based on TMCS1100EVM PCB layout. See Layout section. Device must be operated below maximum junction temperature. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 9 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 7.10 Typical Characteristics 0.8 80 0.6 Sensitivity Error (%) 0.4 0.2 0 -0.2 -0.4 A1 A2 A3 A4 60 Input Current Offset (mA) A1 A2 A3 A4 -0.6 40 20 0 -20 -40 -60 -0.8 -50 -25 0 25 50 75 Temperature (°C) 100 125 -80 -50 150 图 7-1. Sensitivity Error vs. Temperature -25 0 25 50 75 Temperature (°C) 100 125 150 图 7-2. Input Offset Current vs. Temperature 0.25 A1 A2 A3 A4 Population Non-linearity (%) 0.2 0.15 Sensitivity Error (%) 0 -50 -25 0 25 50 75 Temperature (°C) 100 125 0.7 0.6 0.5 0.4 0.3 0.2 0 0.1 -0.1 -0.2 -0.3 -0.4 -0.5 -0.7 0.05 -0.6 0.1 D023 All sensitivities 150 图 7-4. Sensitivity Error Production Distribution IOS (mA) -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 60 52 44 36 28 20 4 12 -4 -12 -20 -28 -36 -44 -52 -60 Population Population 图 7-3. Non-Linearity vs. Temperature D024 TMCS1100A1-Q1 IOS (mA) D025 TMCS1100A2-Q1 图 7-5. Input Offset Current Production Distribution 图 7-6. Input Offset Current Production Distribution 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn -47.5 -42.5 -37.5 -32.5 -27.5 -22.5 -17.5 -12.5 -7.5 -2.5 2.5 7.5 12.5 17.5 22.5 27.5 32.5 37.5 42.5 47.5 Population -40 -36 -32 -28 -24 -20 -16 -12 -8 -4 0 4 8 12 16 20 24 28 32 36 40 Population ZHCSM20 – JUNE 2021 D026 IOS (mA) IOS (mA) TMCS1100A3-Q1 D027 TMCS1100A4-Q1 图 7-7. Input Offset Current Production Distribution 图 7-8. Input Offset Current Production Distribution 4 30 3 0 2 -30 0 Phase (°) Gain (dB) 1 -1 -2 -3 -90 -120 -4 All gains 80kHz -3dB -150 -5 -6 10 100 1k 10k Frequency (Hz) 100k -180 10 1M 图 7-9. Sensitivity vs. Frequency, All Gains Normalized to 1 Hz 100 1k Frequency (Hz) 10k 100k 图 7-10. Phase vs. Frequency, All Gains Output Voltage Swing (V) 10k 1k PSRR (mV/V) -60 100 10 1 VS (VS) – 0.5 (VS) – 1 (VS) – 1.5 (VS) – 2 (VS) – 2.5 (VS) – 3 GND + 3 GND + 2.5 GND + 2 GND + 1.5 GND + 1 GND + 0.5 GND 0 20 40 60 80 100 120 140 160 Output Current (mA) 100m 1 10 100 1k 10k Frequency (Hz) 100k 图 7-11. PSRR vs. Frequency 1M 图 7-12. Output Swing vs. Output Current Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 11 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 5.2 10 1 4.6 1k 10k Frequency (Hz) 100k 4.2 -50 1M 5 0 -5 -10 0.5 1 1.5 2 2.5 3 VREF (V) 3.5 4 4.5 125 250 200 A1 A2 150 10 A3 A4 100 1k Frequency (Hz) 10k 100k 图 7-16. Input-Referred Noise vs. Frequency 90 75 3.5 75 60 3 60 3 45 2.5 45 2.5 30 2 30 2 15 1.5 1.5 IIN V1 1 V2 0.5 0 -15 Input Current (A) 4 Output Voltage (V) 90 15 150 300 5 图 7-15. Output Voltage Offset vs. VREF Input Current (A) 100 350 -15 0 25 50 75 Temperature (°C) 400 Referred-to-Input Current Noise (uA/—Hz) A1 A2 A3 A4 10 0 图 7-14. Quiescent Current vs. Temperature 20 15 -25 4 IIN V1 3.5 V2 0 Output Voltage (V) 100 图 7-13. Output Impedance vs. Frequency VOE (mV) 4.8 4.4 0.1 10 12 A1 A2 A3 A4 5 Quiescent Current (mA) Closed-loop Output Impedance (:) 100 1 -15 0.5 Time (4Ps/div) Time (4Ps/div) 图 7-17. Voltage Output Step, Rising 图 7-18. Voltage Output Step, Falling Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 60 6 IIN VOUT 5 50 4 40 3 30 2 20 1 10 0 0 -1 -10 Output Voltage (V) Input Current (A) 70 -2 Time (4Ps/div) 图 7-20. Startup Transient Response 图 7-19. Current Overload Response 2.4 2.3 2.2 RIN (m:) 2.1 2 1.9 1.8 1.7 1.6 1.5 1.4 -50 -25 0 25 50 75 Temperature (°C) 100 125 150 图 7-21. Input Conductor Resistance vs. Temperature 35 0.8 30 0.7 Safety Limiting Current (A) Safety Limiting Current (A) 7.10.1 Insulation Characteristics Curves 25 20 15 10 5 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0 20 40 60 80 100 120 Ambient Temperature (°C) 140 160 0 20 40 60 80 100 120 Ambient Temperature (°C) 140 160 图 7-22. Thermal Derating Curve for Safety-Limiting 图 7-23. Thermal Derating Curve for Safety-Limiting Current, Side 1 Current, Side 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 13 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 4 Saftey Limiting Power (W) 3.5 3 2.5 2 1.5 1 0.5 0 0 20 40 60 80 100 120 Ambient Temperature (°C) 140 160 图 7-24. Thermal Derating Curve for Safety-Limiting Power 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 8 Parameter Measurement Information 8.1 Accuracy Parameters The ideal first-order transfer function of the TMCS1100-Q1 is given by 方程式 1, where the output voltage is a linear function of input current. The accuracy of the device is quantified both by the error terms in the transfer function parameters, as well as by nonidealities that introduce additional error terms not in the simplified linear model. See Total Error Calculation Examples for example calculations of total error, including all device error terms. VOUT = S × IIN + VREF (1) where • • • • VOUT is the analog output voltage. S is the ideal sensitivity of the device. IIN is the isolated input current. VREF is the voltage applied to the reference voltage input. where • • • • VOUT is the analog output voltage. S is the ideal sensitivity of the device. IIN is the isolated input current. VOUT,0A is the zero current output voltage for the device variant. 8.1.1 Sensitivity Error Sensitivity is the proportional change in the sensor output voltage due to a change in the input conductor current. This sensitivity is the slope of the first-order transfer function of the sensor, as shown in 图 8-1. The sensitivity of the TMCS1100-Q1 is tested and calibrated at the factory for high accuracy. VOUT (V) VREF + VFS+ VNL S = Slope (V/A) best fit linear VREF VOUT, 0 A VOE VREF VREF ± VFS± IFS± IIN (A) IFS+ 图 8-1. Sensitivity, Offset, and Nonlinearity Error Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 15 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 Deviation from ideal sensitivity is quantified by sensitivity error, defined as the percent variation of the best-fit measured sensitivity from the ideal sensitivity. When specified over a temperature range, this is the worst-case sensitivity error at any temperature within the range. eS = [(Sfit – Sideal) / Sideal] × 100% (2) where • eS is the sensitivity error. • Sfit is the best fit sensitivity. • SIdeal is the ideal sensitivity. 8.1.2 Offset Error and Offset Error Drift Offset error is the deviation from the ideal output voltage with zero input current through the device. Offset error can be referred to the output as a voltage error VOE or referred to the input as a current offset error IOS. Offset error is a single error source, however, and must only be included once in error calculations. The output voltage offset error of the TMCS1100-Q1 is the error in the zero current output voltage from the VREF pin voltage as in 方程式 3. VOE VOUT,0A VREF (3) where • VOUT,0A is the device output voltage with zero input current. The offset error includes the magnetic offset of the Hall sensor and any offset voltage errors of the signal chain. The input referred (RTI) offset error is the output voltage offset error divided by the sensitivity of the device, shown in 方程式 4. Refer the offset error to the input of the device to allow for easier total error calculations and direct comparison to input current levels. No matter how the calculations are done, the error sources quantified by VOE and IOS are the same, and should only be included once for error calculations. IOS VOE / S (4) Offset error drift is the change in the input-referred offset error per degree Celsius change in ambient temperature. This parameter is reported in µA/°C. To convert offset drift to an absolute offset for a given change in temperature, multiply the drift by the change in temperature and convert to percentage, as in 方程式 5. IOS,25qC eIOS ,'T % § PA · IOS,drift ¨ ¸ u 'T © qC ¹ IIN (5) where • IOS,drift is the specified input-referred device offset drift. • ΔT is the temperature range from 25°C. 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 8.1.3 Nonlinearity Error Nonlinearity is the deviation of the output voltage from a linear relationship to the input current. Nonlinearity voltage, as shown in 图 8-1, is the maximum voltage deviation from the best-fit line based on measured parameters, calculated by 方程式 6. VNL = VOUT,MEAS – (IMEAS × Sfit + VOUT,0A) (6) where • • • • VOUT,MEAS is the voltage output at maximum deviation from best fit. IMEAS is the input current at maximum deviation from best fit. Sfit is the best-fit sensitivity of the device. VOUT,0A is the device zero current output voltage. Nonlinearity error (eNL) for the TMCS1100-Q1 is the nonlinearity voltage specified as a percentage of the fullscale output range (VFS), as shown in 方程式 7. eNL 100% * VNL VFS (7) 8.1.4 Power Supply Rejection Ratio Power supply rejection ratio (PSRR) is the change in device offset due to variation of supply voltage from the nominal 5 V. The error contribution at the input current of interest can be calculated by 方程式 8. ePSRR (%) PSRR * (VS S IIN 5) (8) where • VS is the operational supply voltage. • S is the device sensitivity. 8.1.5 Common-Mode Rejection Ratio Common-mode rejection ratio (CMRR) quantifies the effective input current error due to a varying voltage on the isolated input of the device. Due to magnetic coupling and galvanic isolation of the current signal, the TMCS1100-Q1 has very high rejection of input common-mode voltage. Percent error contribution from input common-mode variation can be calculated by 方程式 9. eCMRR (%) CMRR * VCM IIN (9) where • VCM is the maximum operational AC or DC voltage on the input of the device. 8.1.6 Reference Voltage Rejection Ratio The voltage applied to the VREF pin sets the zero current output voltage for the TMCS1100-Q1. Ideally, the zero current output voltage directly tracks VREF. Light internal mismatch can cause minor errors, however. When the reference voltage deviates from half of the supply, an additional effective output offset error is introduced into the device transfer function. The reference voltage rejection ratio (RVRR) is the effective change in output offset voltage due to this deviation. Error due to reference rejection can be calculated by 方程式 10. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 17 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 RVRR * (VREF VS ) 2 S e VREF (%) IIN (10) 8.1.7 External Magnetic Field Errors The TMCS1100-Q1 does not have stray field-rejection capabilities, so external magnetic fields from adjacent high-current traces or nearby magnets can impact the output measurement. The total sensitivity (S) of the device is comprised of the initial transformation of input current to magnetic field quantified as the magnetic coupling factor (G), as well as the sensitivity of the Hall element and the analog circuitry that is factory calibrated to provide a final sensitivity. The output voltage is proportional to the input current by the device sensitivity, as defined in 方程式 11. S G * SHall * A V (11) where • • • • S is the TMCS1100-Q1 sensitivity in mV/A. G is the magnetic coupling factor in mT/A. SHall is the sensitivity of the Hall plate in mV/mT. AV is the calibrated analog circuitry gain in V/V. An external field, BEXT, is measured by the Hall sensor and signal chain, in addition to the field generated by the leadframe current, and is added as an extra input term in the total output voltage function: VOUT BEXT * SHall * A V IIN * G * SHall * A V VOUT,0A (12) Observable from 方程式 12 is that the impact of an external field is an additional equivalent input current signal, IBEXT, shown in 方程式 13. This effective additional input current has no dependence on Hall or analog circuitry sensitivity, so all gain variants have equivalent input-referred current error due to external magnetic fields. IBEXT BEXT G (13) This additional current error generates a percentage error defined by 方程式 14. eBEXT (%) BEXT G IIN (14) 8.2 Transient Response Parameters The transient response of the TMCS1100-Q1 is impacted by the 250 kHz sampling rate as defined in Transient Response. 图 8-2 shows the TMCS1100-Q1 response to an input current step sufficient to generate a 1V output change. The typical 4us sampling window can be observed as a periodic step. This sampling window dominates the response of the device, and the response will have some probabilistic nature due to alignment of the input step and the sampling window interval. 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn 90 4 75 3.5 60 3 45 2.5 30 2 15 1.5 Output Voltage (V) Input Current (A) ZHCSM20 – JUNE 2021 IIN V1 1 V2 0.5 0 -15 Time (4Ps/div) 图 8-2. Transient Step Response 8.2.1 Slew Rate Slew rate (SR) is defined as the VOUT rate of change for a single integration step’s output transition, as shown in 图 8-3. Because the device often requires two sampling windows to reach a full 90% settling of its final value, this slew rate is not equal to the 10%-90% transition time for the full output swing. Input Current Input Current Input Current tr 90% 4 s Sample Window 1V SR tr 90% 4 s Sample Window SR tr 90% 4 s Sample Window 1V VOUT response 1V VOUT response SR VOUT response 10% tp 10% tp 10% tp 图 8-3. Small Current Input Step Transient Response 8.2.2 Propagation Delay and Response Time Propagation delay is the time period between the input current waveform reaching 10% of its final value and VOUT reaching 10% of its final value. This propagation delay is heavily dependent upon the alignment of the input current step and the sampling period of the TMCS1100-Q1, as shown for several different sampling window cases in 图 8-3. Response time is the time period between the input current reaching 90% of its final value and the output reaching 90% of its final value, for an input current step sufficient to cause a 1-V transition on the output. 图 8-3 shows the response time of the TMCS1100-Q1 under three different time cases. Unless a step input occurs directly during the beginning of one sampling window the response time will include two sampling intervals. 8.2.3 Current Overload Parameters Current overload response parameters are the transient behavior of the TMCS1100-Q1 to an input current step consistent with a short circuit or fault event. Tested amplitude is twice the full scale range of the device, or 10V / Sensitivity in V/A. Under these conditions, the TMCS1100-Q1 output will respond faster than in the case of a small input current step due to the higher input amplitude signal. Response time and propagation delay are measured in a similar manner to the case of a small input current step, as shown in 图 8-4. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 19 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 Input Current tr 90% û IIN = 10 V / S VOUT response SR 10% tp 图 8-4. Current Overload Transient Response Current overload recovery time is the required time for the device output to exit a saturated condition and return to normal operation. The transient response of the device during this recovery period from a current overload is shown in 图 7-19. 8.2.4 CMTI, Common-Mode Transient Immunity CMTI is the capability of the device to tolerate a rising/falling voltage step on the input without disturbance on the output signal. The device is specified for the maximum common-mode transition rate under which the output signal will not experience a greater than 200-mV disturbance that lasts longer than 1 µs. Higher edge rates than the specified CMTI can be supported with sufficient filtering or blanking time after common-mode transitions. 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 8.3 Safe Operating Area The isolated input current safe operating area (SOA) of the TMCS1100-Q1 is constrained by self-heating due to power dissipation in the input conductor. Depending upon the use case, the SOA is constrained by multiple conditions, including exceeding maximum junction temperature, Joule heating in the leadframe, or leadframe fusing under extremely high currents. These mechanisms depend on pulse duration, amplitude, and device thermal states. Current SOA strongly depends on the thermal environment and design of the system-level board. Multiple thermal variables control the transfer of heat from the device to the surrounding environment, including air flow, ambient temperature, and printed-circuit board (PCB) construction and design. All ratings are for a single TMCS1100-Q1 device on the TMCS1100EVM, with no air flow in the specified ambient temperature conditions. Device use profiles must satisfy both continuous conduction and short-duration transient SOA capabilities for the thermal environment under which the system will be operated. 8.3.1 Continuous DC or Sinusoidal AC Current The longest thermal time constants of device packaging and PCBs are in the order of seconds; therefore, any continuous DC or sinusoidal AC periodic waveform with a frequency higher than 1 Hz can be evaluated based on the RMS continuous-current level. The continuous-current capability has a strong dependence upon the operating ambient temperature range expected in operation. 图 8-5 shows the maximum continuous currenthandling capability of the device on the TMCS1100EVM. Current capability falls off at higher ambient temperatures because of the reduced thermal transfer from junction-to-ambient and increased power dissipation in the leadframe. By improving the thermal design of an application, the SOA can be extended to higher currents at elevated temperatures. Using larger and heavier copper power planes, providing air flow over the board, or adding heat sinking structures to the area of the device can all improve thermal performance. Maximum Continuous RMS Current (A) 35 30 25 20 15 10 -55 -35 -15 5 25 45 65 Ambient Temperature (qC) 85 105 125 D012 图 8-5. Maximum Continuous RMS Current vs. Ambient Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 21 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 8.3.2 Repetitive Pulsed Current SOA For applications where current is pulsed between a high current and no current, the allowable capabilities are limited by short-duration heating in the leadframe. The TMCS1100-Q1 can tolerate higher current ranges under some conditions, however, for repetitive pulsed events, the current levels must satisfy both the pulsed current SOA and the RMS continuous current constraint. Pulse duration, duty cycle, and ambient temperate all impact the SOA for repetitive pulsed events. 图 8-6, 图 8-7, 图 8-8, and 图 8-9 illustrate repetitive stress levels based on test results from the TMCS1100EVM under which parametric performance and isolation integrity was not impacted post-stress for multiple ambient temperatures. At high duty cycles or long pulse durations, this limit approaches the continuous current SOA for a RMS value defined by 方程式 15. IIN,RMS IIN,P * D (15) where • IIN,RMS is the RMS input current level • IIN,P is the pulse peak input current • D is the pulse duty cycle 160 250 1% 5% 10% 25% 50% 75% 150 Allowable Current (A) Allowable Current (A) 200 1% 5% 10% 25% 50% 75% 140 100 120 100 80 60 40 50 20 0 0.001 0.01 0.1 1 Current Pulse Duration (s) 0 0.001 10 0.01 D016 TA = 25°C 120 1% 5% 10% 25% 50% 75% 100 1% 5% 10% 25% 50% 75% 100 Allowable Current (A) 120 Allowable Current (A) D017 图 8-7. Maximum Repetitive Pulsed Current vs. Pulse Duration 140 80 60 40 80 60 40 20 20 0.01 0.1 1 Current Pulse Duration (s) 10 0 0.001 D018 TA = 105°C 0.01 0.1 1 Current Pulse Duration (s) 10 D019 TA = 125°C 图 8-8. Maximum Repetitive Pulsed Current vs. Pulse Duration 22 10 TA = 85°C 图 8-6. Maximum Repetitive Pulsed Current vs. Pulse Duration 0 0.001 0.1 1 Current Pulse Duration (s) 图 8-9. Maximum Repetitive Pulsed Current vs. Pulse Duration Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 8.3.3 Single Event Current Capability Single higher-current events that are shorter duration can be tolerated by the TMCS1100-Q1, because the junction temperature does not reach thermal equilibrium within the pulse duration. 图 8-10 shows the short-circuit duration curve for the device for single current-pulse events, where the leadframe resistance changes after stress. This level is reached before a leadframe fusing event, but should be considered an upper limit for short duration SOA. For long-duration pulses, the current capability approaches the continuous RMS limit at the given ambient temperature. Fuse Current (A) 1000 100 TA = 25°C TA = 125°C 10 0.001 0.01 0.1 Pulse Duration (s) 1 10 D004 图 8-10. Single-Pulse Leadframe Capability Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 23 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 9 Detailed Description 9.1 Overview The TMCS1100-Q1 is a precision Hall-effect current sensor, featuring a 600-V basic isolation working voltage, < 1% full-scale error across temperature, and an external reference voltage enabling unidirectional or bidirectional current sensing Input current flows through a conductor between the isolated input current pins. The conductor has a 1.8-mΩ resistance at room temperature for low power dissipation and a 20-A RMS continuous current handling capability up to 105°C ambient temperature on the TMCS1100EVM. The low-ohmic leadframe path reduces power dissipation compared to alternative current measurement methodologies, and does not require any external passive components, isolated supplies, or control signals on the high-voltage side. The magnetic field generated by the input current is sensed by a Hall sensor and amplified by a precision signal chain. The device can be used for both AC and DC current measurements and has a bandwidth of 80 kHz. There are multiple fixed-sensitivity device variants for a wide option of linear sensing ranges, and the TMCS1100-Q1 can operate with a low voltage supply from 3 V to 5.5 V. The TMCS1100-Q1 is optimized for high accuracy and temperature stability, with both offset and sensitivity compensated across the entire operating temperature range. 9.2 Functional Block Diagram Isolation Barrier VS Hall Element Bias Temperature Compensation ---------------------Offset Cancellation IN+ Precision Amplifier Output Amplifier VOUT IN± Reference Sampling VREF GND 9.3 Feature Description 9.3.1 Current Input Input current to the TMCS1100-Q1 passes through the isolated side of the package leadframe through the IN+ and IN– pins. The current flow through the package generates a magnetic field that is proportional to the input current, and measured by a galvanically isolated, precision, Hall sensor IC. As a result of the electrostatic shielding on the Hall sensor die, only the magnetic field generated by the input current is measured, thus limiting input voltage switching pass-through to the circuitry. This configuration allows for direct measurement of currents with high-voltage transients without signal distortion on the current-sensor output. The leadframe conductor has a nominal resistance of 1.8 mΩ at 25°C, and has a typical positive temperature coefficient as defined in the Electrical Characteristics table. 9.3.2 Input Isolation The separation between the input conductor and the Hall sensor die due to the TMCS1100-Q1 construction provides inherent galvanic isolation between package pins 1-4 and pins 5-8. Insulation capability is defined according to certification agency definitions and using industry-standard test methods as defined in the Insulation Specifications table. Assessment of device lifetime working voltages follow the VDE 0884-11 standard for basic insulation, requiring time-dependent dielectric breakdown (TDDB) data-projection failure rates of less than 1000 part per million (ppm), and a minimum insulation lifetime of 20 years. The VDE standard also requires an additional safety margin of 20% for working voltage, and a 30% margin for insulation lifetime, translating into a minimum required lifetime of 26 years at 509 VRMS for the TMCS1100-Q1. 24 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 图 9-1 shows the intrinsic capability of the isolation barrier to withstand high-voltage stress over the lifetime of the device. Based on the TDDB data, the intrinsic capability of these devices is 424 VRMS with a lifetime of > 100 years. Other factors such as operating environment and pollution degree can further limit the working voltage of the component in an end system. 图 9-1. Insulation Lifetime 9.3.3 High-Precision Signal Chain The TMCS1100-Q1 uses a precision, low-drift signal chain with proprietary sensor linearization techniques to provide a highly accurate and stable current measurement across the full temperature range of the device. The device is fully tested and calibrated at the factory to account for any variations in either silicon or packaging process variations. The full signal chain provides a fixed sensitivity voltage output that is proportional to the current through the leadframe of the isolated input. 9.3.3.1 Temperature Stability The TMCS1100-Q1 includes a proprietary temperature compensation technique which results in significantly improved parametric drift across the full temperature range. This compensation technique accounts for changes in ambient temperature, self-heating, and package stress. A zero-drift signal chain architecture and Hall sensor temperature stabilization methods enable stable sensitivity and minimize offset errors across temperature, and drastically improves system-level performance across the required operating conditions. 图 9-2 shows the offset error across the full device ambient temperature range. 图 9-3 shows the typical sensitivity. There are no other external components introducing errors sources; therefore, the high intrinsic accuracy and stability over temperature directly translates to system-level performance. As a result of this high precision, even a system with no calibration can reach < 1% of total error current-sensing capability. 80 0.8 A1 A2 A3 A4 40 20 0 -20 -40 -60 -80 -50 A1 A2 A3 A4 0.6 Sensitivity Error (%) Input Current Offset (mA) 60 0.4 0.2 0 -0.2 -0.4 -0.6 -25 0 25 50 75 Temperature (°C) 100 125 150 图 9-2. Offset Error Drift Across Temperature -0.8 -50 -25 0 25 50 75 Temperature (°C) 100 125 150 图 9-3. Sensitivity Drift Across Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 25 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 9.3.3.2 Lifetime and Environmental Stability The same compensation techniques used in the TMCS1100-Q1 to reduce temperature drift also greatly reduce lifetime drift due to aging, stress, and environmental conditions. Typical magnetic sensors suffer from up to 2% to 3% of sensitivity drift due to aging at high operating temperatures. The TMCS1100-Q1 has greatly improved lifetime drift, as defined in the Electrical Characteristics for total sensitivity error measured after the worst case stress test during a three lot AEC-Q100 qualification. All other stress tests prescribed by an AEC-Q100 qualification caused lower than the specified sensitivity error, and were within the bounds specified within the Electrical Characteristics table. 图 9-4 shows the total sensitivity error after the worst-case stress test, a Highly Accelerated Stress Test (HAST) at 130°C and 85% relative humidity (RH), while 图 9-5 and 图 9-6 show the sensitivity and offset error drift after a 1000 hour, 125°C high temperature operating life stress test as specified by AEC-Q100. This test mimics typical device lifetime operation, and shows the likely device performance variation due to aging is vastly improved compared to typical magnetic sensors. 160 200 140 180 160 120 Unit Count Unit Count 140 100 80 60 120 100 80 60 40 40 20 20 0 -1% -.8% -.6% -.4% -.2% 0% .2% .4% .6% .8% Sensitivity Drift (%) 0 -1% -.8% -.6% -.4% -.2% 0% 1% .2% Sensitivity Drift (%) D020 图 9-4. Sensitivity Error After 130°C, 85% RH HAST .4% .6% .8% 1% D021 图 9-5. Sensitivity Error Drift After AEC-Q100 High Temperature Operating Life Stress Test 120 100 Unit Count 80 60 40 20 0 -50 -40 -30 -20 -10 0 10 20 30 IOS Drift (mA) 40 50 D022 图 9-6. Input-Referred Offset Drift After AEC-Q100 High Temperature Operating Life Stress Test 9.3.3.3 Frequency Response The TMCS1100-Q1 signal chain has a spectral response atypical of a linear analog system due to its discrete time sampling. The 250-kHz sampling interval implies an effective Nyquist frequency of 125 kHz, which limits spectral response to below this frequency. Higher frequency content than this frequency will be aliased down to lower spectrums. The TMCS1100-Q1 bandwidth is defined by the –3-dB spectral response of the entire signal chain which is constrained by the sampling frequency. Normalized gain and phase plots across frequency are shown below in 图 9-7 and 图 9-8, all variants have the same bandwidth and phase response. Signal content beyond the 3-dB bandwidth level will still have significant fundamental frequency transmission through the signal chain, but at increasing distortion levels 26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 4 30 3 0 2 -30 0 Phase (°) Gain (dB) 1 -1 -2 -3 -60 -90 -120 -4 All gains 80kHz -3dB -150 -5 -6 10 100 1k 10k Frequency (Hz) 100k 1M -180 10 图 9-7. Normalized Gain, All Variants 100 1k Frequency (Hz) 10k 100k 图 9-8. Normalized Phase, All Variants 9.3.3.4 Transient Response The TMCS1100-Q1 signal chain includes a precision analog front end followed by a sampled integrator. At the end of each integration cycle, the signal propagates to the output. Depending on the alignment of a change in input current relative to the sampling window, the output might not settle to the final signal until the second integration cycle. 图 9-9 shows a typical output waveform response to a 10-kHz sine wave input current. For a slowly varying input current signal, the output is a discrete time representation with a phase delay of the integration sampling window. Adding a first order filter of 100 kHz effectively smooths the output waveform with minimal impact to phase response. 5.5 6 VOUT Input Current 5 VOUT, 100 kHz Filter 5 4 4 3 3.5 2 3 1 2.5 0 2 -1 1.5 -2 1 -3 0.5 -4 0 0 .00005 .0001 .00015 Time (s) .0002 Input Current (A) Output Voltage (V) 4.5 -5 .00025 D015 图 9-9. Response Behavior to 10-kHz Sine Wave Input Current 图 9-10 shows two transient waveforms to an input-current step event, but occurring at different times during the sampling interval. In both cases, the full transition of the output takes two sampling intervals to reach the final output value. The timing of the current event relative to the sampling window determines the proportional amplitude of the first and second sampling intervals. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 27 TMCS1100-Q1 www.ti.com.cn 90 4 75 3.5 60 3 45 2.5 30 2 15 1.5 Output Voltage (V) Input Current (A) ZHCSM20 – JUNE 2021 IIN V1 1 V2 0.5 0 -15 Time (4Ps/div) 图 9-10. Transient Response to Input-Current Step Sufficient for 1-V Output Swing 70 6 60 5 50 4 40 3 30 2 20 1 10 Output Voltage (V) Input Current (A) The output value is effectively an average over the sampling window; therefore, a large-enough current transient can drive the output voltage to near the full scale range in the first sample response. This condition is likely to be true in the case of a short-circuit or fault event. 图 9-11 shows an input-current step twice the full scale measurable range with two output voltage responses illustrating the effect of the sampling window. The relative timing and size of the input current transition determines both the time and amplitude of the first output transition. In either case, the total response time is slightly longer than one integration period. 0 IIN V1 -1 V2 -2 0 -10 Time (4Ps/div) 图 9-11. Transient Response to a Large Input Current Step 9.3.4 External Reference Voltage Input The reference voltage provided externally to the TMCS1100-Q1 on the VREF pin determines the zero current output voltage, VOUT,0A. This zero-current output level along with sensitivity determine the measurable input current range of the device, and allows for unidirectional or bidirectional sensing, as described in the Absolute Maximum Ratings table. 图 9-12 illustrates the transfer function of the TMCS1100A2-Q1 with varying VREF voltages of 0 V, 1.25 V, and 2.5 V. By shifting the zero current output voltage of the device, the dynamic range of measurable input current can be modified. 28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 5 4.5 Output Voltage (V) 4 3.5 3 2.5 2 1.5 1 VREF = 0 V VREF = 1.25 V VREF = 2.5 V 0.5 0 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 Input Current (A) D002 图 9-12. Output Voltage Relationship to Input Current With Varying VREF Voltages The input voltage on this pin can be provided by any external voltage source or potential, such as a discrete precision reference, a voltage divider, ADC reference, or ground. The VREF pin is sampled by the internal circuitry at approximately 1 MHz, then buffered and provided to the signal chain of the device. An apparent DC load of approximately 1 µA will be observed by the external reference. To prevent errors due to sampling settling, keep the source impedance below the level specified in the Electrical Characteristics table. 9.3.5 Current-Sensing Measurable Ranges The TMCS1100-Q1 can be configured to allow for bidirectional or unidirectional measurable current ranges based on the external voltage on the VREF pin. The output voltage is limited by VOUT swing to either supply or ground. Linear output swing range to both VS and GND is calculated by equations 方程式 16 and 方程式 17. VOUT,max = VS – SwingVS (16) VOUT,min = SwingGND (17) Rearranging the transfer function of the device to solve for input current, and substituting VOUT,max and VOUT,min yields the maximum and minimum measurable input current ranges as shown in 方程式 18 and 方程式 19. IIN,MAX+ = (VOUT,max – VREF) / S (18) IIN,MAX- = (VREF – VOUT,min) / S (19) where • IIN,MAX+ is the maximum linear measurable positive input current. • IIN,MAX- is the maximum linear measurable negative input current. • S is the sensitivity of the device variant. Setting VREF to the middle of the output swing range provides bidirectional measurement capability, whereas setting VREF close to the ground provides a unidirectional measurement. Custom ranges with nonuniform positive and negative input current ranges can be achieved by appropriately scaling the VREF potential relative to the full output voltage range. 9.4 Device Functional Modes 9.4.1 Power-Down Behavior As a result of the inherent galvanic isolation of the device, very little consideration must be paid to powering down the device, as long as the limits in the Absolute Maximum Ratings table are not exceeded on any pins. The isolated current input and the low-voltage signal chain can be decoupled in operational behavior, as either can be energized with the other shut down, as long as the isolation barrier capabilities are not exceeded. The lowvoltage power supply can be powered down while the isolated input is still connected to an active high-voltage signal or system. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 29 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 10 Application and Implementation 备注 以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定 器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。 10.1 Application Information The key feature sets of the TMCS1100-Q1 provide significant advantages in any application where an isolated current measurement is required. • Galvanic isolation provides a high isolated working voltage and excellent immunity to input voltage transients. • Hall based measurement simplifies system level solution without the need for a power supply on the high voltage (HV) side. • An input current path through the low impedance conductor minimizes power dissipation. • Excellent accuracy and low temperature drift eliminate the need for multipoint calibrations without sacrificing system performance. • An external reference input maximizes flexibility for unidirectional or bidirectional measurement with custom dynamic ranges, and improves accuracy at the system level. • A wide operating supply range enables a single device to function across a wide range of voltage levels. These advantages increase system-level performance while minimizing complexity for any application where precision current measurements must be made on isolated currents. Specific examples and design requirements are detailed in the following section. 10.1.1 Total Error Calculation Examples Total error can be calculated for any arbitrary device condition and current level. Error sources considered should include input-referred offset current, power-supply rejection, input common-mode rejection, sensitivity error, nonlinearity, VREF to VOUT gain error, and the error caused by any external fields. Compare each of these error sources in percentage terms, as some are significant drivers of error and some have inconsequential impact to current error. Offset (方程式 20), CMRR (方程式 22), PSRR (方程式 21), VREF gain error (方程式 23), and external field error (方程式 24) are all referred to the input, and so, are divided by the actual input current IIN to calculate percentage errors. For calculations of sensitivity error and nonlinearity error, the percentage limits explicitly specified in the Electrical Characteristics table can be used. eIOS (%) IOS IIN ePSRR (%) (20) PSRR * (VS S IIN 5) (21) eCMRR (%) CMRR * VCM IIN RVRR * (VREF (22) VS ) 2 S e VREF (%) 30 IIN (23) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn eBEXT (%) ZHCSM20 – JUNE 2021 BEXT G IIN (24) When calculating error contributions across temperature, only the input offset current and sensitivity error contributions vary significantly. For determining offset error over a given temperature range (ΔT), use 方程式 25 to calculate total offset error current. Sensitivity error is specified for both –40°C to 85°C and –40°C to 125°C. The appropriate specification should be used based on application operating ambient temperature range. IOS,25qC eIOS ,'T % § PA · IOS,drift ¨ ¸ u 'T © qC ¹ IIN (25) To accurately calculate the total expected error of the device, the contributions from each of the individual components above must be understood in reference to operating conditions. To account for the individual error sources that are statistically uncorrelated, a root sum square (RSS) error calculation should be used to calculate total error. For the TMCS1100-Q1, only the input referred offset current (IOS), CMRR, and PSRR are statistically correlated. These error terms are lumped in an RSS calculation to reflect this nature, as shown in 方程式 26 for room temperature and 方程式 27 for across a given temperature range. The same methodology can be applied for calculating typical total error by using the appropriate error term specification. eRSS (%) eRSS,'T (%) eIOS ePSRR eIOS,'T eCMRR ePSRR 2 e VREF 2 eCMRR 2 eBEXT 2 e VREF 2 eS2 eBEXT 2 eNL2 (26) eS,'T 2 eNL 2 (27) The total error calculation has a strong dependence on the actual input current; therefore, always calculate total error across the dynamic range that is required. These curves asymptotically approach the sensitivity and nonlinearity error at high current levels, and approach infinity at low current levels due to offset error terms with input current in the denominator. Key figures of merit for any current-measurement system include the total error percentage at full-scale current, as well as the dynamic range of input current over which the error remains below some key level. 图 10-1 illustrates the RSS maximum total error as a function of input current for a TMCS1100A2 at room temperature and across the full temperature range with VS of 5 V. 10 RSS Max Error, 25°C 566 0D[ (UURU ± ƒ& WR 566 0D[ (UURU ± ƒ& WR RSS Max Total Error (%) 9 8 ƒ& ƒ& 7 6 5 4 3 2 1 0 0 5 10 15 Input Current (A) 20 25 D007 图 10-1. RSS Error vs. Input Current Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 31 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 10.1.1.1 Room Temperature Error Calculations For room-temperature total-error calculations, specifications across temperature and drift are ignored. As an example, consider a TMCS1100-Q1 A1 with a supply voltage (VS) of 3.3 V, a VREF of 1.5 V, and a worst-case common-mode excursion of 600 V to calculate operating-point-specific parameters. Consider a measurement error due to an external magnetic field of 30 µT, roughly the Earth's magnetic field strength. The full-scale current range of the device in specified conditions is slightly greater than 28 A; therefore, calculate error at both 25 A and 12.5 A to highlight error dependence on the input-current level. 表 10-1 shows the individual error components and RSS maximum total error calculations at room temperature under the conditions specified. Relative to other errors, the additional error from CMRR is negligible, and can typically be ignored for total error calculations. 表 10-1. Total Error Calculation: Room Temperature Example ERROR COMPONENT SYMBOL Input offset error eIos EQUATION IOS IIN eIOS (%) PSRR error ePSRR CMRR error eCMRR PSRR * (VS S IIN ePSRR (%) eCMRR (%) VREF error e VREF (%) BEXT G IIN eBext Sensitivity error eS Specified in Electrical Characteristics Nonlinearity error eNL Specified in Electrical Characteristics eRSS eBEXT (%) eRSS (%) eIOS 0.48% 0.27% 0.54% 0.01% 0.02% 0.04% 0.08% 0.11% 0.22% 0.7% 0.7% 0.05% 0.05% 0.88% 1.28% IIN External Field error RSS total error 0.24% VS ) 2 S eVREF % MAX TOTAL ERROR AT IIN = 12.5 A 5) CMRR * VCM IIN RVRR * (VREF % MAX TOTAL ERROR AT IIN = 25 A ePSRR eCMRR 2 e VREF 2 eBEXT 2 eS 2 eNL 2 10.1.1.2 Full Temperature Range Error Calculations To calculate total error across any specific temperature range, 方程式 26 and 方程式 27 should be used for RSS maximum total errors, similar to the example for room temperatures. Conditions from the example in Room Temperature Error Calculations have been replaced with their respective equations and error components for a –40°C to 85°C temperature range below in 表 10-2. 表 10-2. Total Error Calculation: –40°C to 85°C Example ERROR COMPONENT SYMBOL Input offset error eIos,ΔT 32 EQUATION IOS,25qC eIOS ,'T % § PA · IOS,drift ¨ ¸ u 'T © qC ¹ IIN Submit Document Feedback % MAX TOTAL ERROR AT IIN = 25 A % MAX TOTAL ERROR AT IIN = 12.5 A 0.28% 0.56% Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 表 10-2. Total Error Calculation: –40°C to 85°C Example (continued) ERROR COMPONENT SYMBOL PSRR error ePSRR CMRR error eCMRR EQUATION PSRR * (VS S IIN ePSRR (%) eCMRR (%) VREF error e VREF (%) BEXT G IIN eBext Sensitivity error eS,ΔT Specified in Electrical Characteristics Nonlinearity error eNL Specified in Electrical Characteristics eRSS,ΔT eBEXT (%) eRSS,'T (%) eIOS,'T ePSRR 0.54% 0.01% 0.02% 0.04% 0.08% 0.11% 0.22% 0.85% 0.85% 0.05% 0.05% 1.03% 1.43% IIN External Field error RSS total error 0.27% VS ) 2 S eVREF % MAX TOTAL ERROR AT IIN = 12.5 A 5) CMRR * VCM IIN RVRR * (VREF % MAX TOTAL ERROR AT IIN = 25 A eCMRR 2 e VREF 2 eBEXT 2 eS,'T 2 eNL 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 33 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 10.2 Typical Application Inline sensing of inductive load currents, such as motor phases, provides significant benefits to the performance of a control systems, allowing advanced control algorithms and diagnostics with minimal postprocessing. A primary challenge to inline sensing is that the current sensor is subjected to full HV supply-level PWM transients driving the load. The inherent isolation of an in-package Hall-effect current sensor topology helps overcome this challenge, providing high common-mode immunity, as well as isolation between the high-voltage motor drive levels and the low-voltage control circuitry. 图 10-2 illustrates the use of the TMCS1100-Q1 in such an application, driving the inductive load presented by a three phase motor. 5V VS V+ VOUT IN+ TMCS1100-Q1 2.5 V VREF IN– GND TMCS1100-Q1 TMCS1100-Q1 V- 图 10-2. Inline Motor Phase Current Sensing 10.2.1 Design Requirements For current sensing of a three-phase motor application, make sure to provide linear sensing across the expected current range, and make sure that the device remains within working thermal constraints. A single TMCS1100Q1 for each phase can be used, or two phases can be measured, and the third phase calculated on the motorcontroller host processor. For this example, consider a nominal supply of 5 V but a minimum of 4.9 V to include for some supply variation. Maximum output swings are defined according to TMCS1100-Q1 specifications, and a full-scale current measurement of ±20 A is required. 表 10-3. Example Application Design Requirements DESIGN PARAMETER 34 EXAMPLE VALUE VS,nom 5V VS,min 4.9 V IIN,FS ±20 A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 10.2.2 Detailed Design Procedure The TMCS1100-Q1 application design procedure has two key design parameters: the sensitivity version chosen (A1-A4) and the reference voltage input. Further consideration of noise and integration with an ADC can be explored, but is beyond the scope of this application design example. The TMCS1100-Q1 transfer function is effectively a transimpedance with a variable offset set by VREF, defined by 方程式 28. VOUT IIN u S VREF (28) Design of the sensing solution first focuses on maximizing the sensitivity of the device while maintaining linear measurement over the expected current input range. The linear output voltage range is constrained by the TMCS1100-Q1 linear swing to ground, SwingGND, and swing to supply, SwingVS. With the previous parameters, the maximum linear output voltage range is the range between VOUT,max and VOUT,min, as defined by 方程式 29 and 方程式 30. VOUT,max VS,min SwingVS VOUT,min SwingGND (29) (30) For a bidirectional current-sensing application, a sufficient linear output voltage range is required from VREF to both ground and the power supply. Design parameters for this example application are shown in 表 10-4 along with the calculated output range. 表 10-4. Example Application Design Parameters DESIGN PARAMETER EXAMPLE VALUE SwingVS 0.2 V SwingGND 0.05 V VOUT,max 4.7 V VOUT,min 0.05 V VOUT,max - VOUT,min 4.65 V These design parameters result in a maximum linear output voltage swing of 4.65 V. To determine which sensitivity variant of the TMCS1100-Q1 most fully uses this linear range, calculate the maximum current range by 方程式 31 for a unidirectional current (IU,MAX), and 方程式 32 for a bidirectional current (IB,MAX). IU,MAX IB,MAX VOUT,max SA VOUT,min (31) x! VOUT,max VOUT,min 2 u SA (32) x! where • SA is the sensitivity of the relevant A1-A4 variant. 表 10-5 shows such calculation for each gain variant of the TMCS1100-Q1 with the appropriate sensitivities. 表 10-5. Maximum Full-Scale Current Ranges With 4.65-V Output Range SENSITIVITY VARIANT SENSITIVITY IU,MAX IB,MAX TMCS1100A1-Q1 50 mV/A 93 A ±46.5 A TMCS1100A2-Q1 100 mV/A 46.5 A ±23.2A TMCS1100A3-Q1 200 mV/A 23.2 A ±11.6A TMCS1100A4-Q1 400 mV/A 11.6 A ±5.8 A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 35 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 In general, select the highest sensitivity variant that provides for the desired full-scale current range. For the design parameters in this example, the TMCS1100A2-Q1 with a sensitivity of 0.1 V/A is the proper selection because the maximum-calculated ±23.2 A linear measurable range is sufficient for the desired ±20-A full-scale current. After selecting the appropriate sensitivity variant for the application, the zero-current reference voltage defined by the VREF input pin is defined. Manipulating 方程式 28 and using the linear range defined by VOUT,max, VOUT,min, and the full-scale input current, IIN,FS, calculate the maximum and minimum VREF voltages allowed to remain within the linear measurement range, shown in 方程式 33 and 方程式 34. VREF,max VOUT,max VREF,min VOUT,min IIN,FS u S (33) IIN,FS u S (34) Any value of V REF can be chosen between VREF,max and VREF,min to maintain the required linear sensing range. If the allowable VREF range is not wide enough or does not include a desired VREF voltage, the analysis must be repeated with a lower sensitivity variant of the TMCS1100-Q1. 方程式 28 can be manipulated to solve for the maximum allowable current in either direction by using the selected VREF voltage and the maximum linear voltage ranges as in 方程式 35 and 方程式 36. IMAX IMAX VOUT,max VREF (35) S VOUT,min VREF (36) S 表 10-6 shows the respective values for the example design parameters in 表 10-4. In this case, a VREF of 2.5 V has been selected such that the zero current output is half of the nominal power supply. This example VREF design value provides a linear input current-sensing range of –24.5 A to +22 A, with the positive current defined as current flowing into the IN+ pin. 表 10-6. Example VREF Limits and Associated Current Ranges 36 REFERENCE PARAMETER EXAMPLE VALUE VREF,min MAXIMUM LINEAR CURRENT SENSING RANGE IMAX+ IMAX– 2.05 V 26.5 A –20 A VREF,max 2.7 V 20 A –26.5 A Selected VREF 2.5 V 22 A –24.5 A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 After selecting a VREF for the application design, an appropriate source must be defined. Multiple implementations are possible, but could include: • Resistor divider from the supply voltage • Resistor divider from an ADC full-scale reference • Dedicated or preexisting voltage reference IC • DAC or reference voltage from a system microcontroller Each of these options has benefits, and the error terms, noise, simplicity, and cost of each implementation must be weighed. In the current design example, any of these options are potentially available as a 2.5-V VREF is midrail of the power supply, a common IC reference voltage, and might already be available in the system. If the primary consideration for the current application design is to maximize precision while minimizing temperature drift and noise, a dedicated voltage reference must be chosen. For this case, the LM4030C-2.5 can be chosen for to optimize system accuracy without significant cost addition. 图 10-3 depicts the current-sense system design as discussed. 5V IIN VS IN+ VOUT TMCS1100-Q1 0.1 μF To ADC / MCU 2.5 V VREF IN– GND LM4030C-2.5 0.15%, 30 ppm/
C 图 10-3. TMCS1100-Q1 Example Current-Sense System Design 11 Power Supply Recommendations The TMCS1100-Q1 only requires a power supply (VS) on the low-voltage isolated side, which powers the analog circuitry independent of the isolated current input. VS determines the full-scale output range of the analog output VOUT, and can be supplied with any voltage between 3 V and 5.5 V. To filter noise in the power-supply path, place a low-ESR decoupling capacitor of 0.1 µF between VS and GND pins as close as possible to the supply and ground pins of the device. To compensate for noisy or high-impedance power supplies, add more decoupling capacitance. The TMCS1100-Q1 power supply VS can be sequenced independently of current flowing through the input. However, there is a typical 25-ms delay between VS reaching the recommended operating voltage and the analog output being valid. Within this delay VOUT transfers from a high impedance state to the active drive state, during which time the output voltage could transition between GND and VS. If this behavior must be avoided, a stable supply voltage to VS should be provided for longer than 25 ms prior to applying input current. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 37 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 12 Layout 12.1 Layout Guidelines The TMCS1100-Q1 is specified for a continuous current handling capability on the TMCS1100EVM, which uses 3-oz copper pour planes. This current capability is fundamentally limited by the maximum device junction temperature and the thermal environment, primarily the PCB layout and design. To maximize current-handling capability and thermal stability of the device, take care with PCB layout and construction to optimize the thermal capability. Efforts to improve the thermal performance beyond the design and construction of the TMCS1100EVM can result in increased continuous-current capability due to higher heat transfer to the ambient environment. Keys to improving thermal performance of the PCB include: • • • • Use large copper planes for both input current path and isolated power planes and signals. Use heavier copper PCB construction. Place thermal via farms around the isolated current input. Provide airflow across the surface of the PCB. The TMCS1100-Q1 senses external magnetic fields, so make sure to minimize adjacent high-current traces in close proximity to the device. The input current trace can contribute additional magnetic field to the sensor if the input current traces are routed parallel to the vertical axis of the package. 图 12-1 illustrates the most optimal input current routing into the TMCS1100-Q1. As the angle that the current approaches the device deviates from 0° to the horizontal axis, the current trace contributes some additional magnetic field to the sensor, increasing the effective sensitivity of the device. If current must be routed parallel to the package vertical axis, move the routing away from the package to minimize the impact to the sensitivity of the device. Terminate the input current path directly underneath the package lead footprint, and use a merged copper input trace for both the IN+ and IN– inputs. IIN,} IIN,0 IIN,0 } } IN+ 1 8 VS IN+ 2 7 VOUT IN± 3 6 VREF IN± 4 5 GND IIN,} 图 12-1. Magnetic Field Generated by Input Current Trace In addition to thermal and magnetic optimization, make sure to consider the PCB design required creepage and clearance for system-level isolation requirements. Maintain required creepage between solder stencils, as shown in 图 12-2, if possible. If not possible to maintain required PCB creepage between the two isolated sides at board level, add additional slots or grooves to the board. If more creepage and clearance is required for system isolation levels than is provided by the package, the entire device and solder mask can be encapsulated with an overmold compound to meet system-level requirements. 38 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 Cu Plane Solder Mask Creepage VS Cu Plane IN+ VOUT VREF Cu Plane IN± GND Cu Plane 图 12-2. Layout for System Creepage Requirements 12.2 Layout Example An example layout, shown in 图 12-3, is from the TMCS1100EVM. Device performance is targeted for thermal and magnetic characteristics of this layout, which provides optimal current flow from the terminal connectors to the device input pins while large copper planes enhance thermal performance. 图 12-3. Recommended Board Top (Left) and Bottom (Right) Plane Layout Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 39 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 13 Device and Documentation Support 13.1 Device Support 13.1.1 Development Support For development tool support see the following: • TMCS1100EVM • TMCS1100 TI-TINA Model • TMCS1100 TINA-TI Reference Design 13.2 Documentation Support 13.2.1 Related Documentation For related documentation see the following: • Texas Instruments, TMCS1100EVM User's Guide • Texas Instruments, Enabling Precision Current Sensing Designs with Nonratiometric Magnetic Current Sensors • Texas Instruments, Low-Drift, Precision, In-Line Isolated Magnetic Motor Current Measurements • Texas Instruments, Isolation Glossary 13.3 接收文档更新通知 要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更 改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。 13.4 支持资源 TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解 答或提出自己的问题可获得所需的快速设计帮助。 链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。 13.5 Trademarks TI E2E™ is a trademark of Texas Instruments. 所有商标均为其各自所有者的财产。 13.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 13.7 术语表 TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 40 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 PACKAGE OUTLINE D0008B SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .150-.157 [3.81-3.98] NOTE 4 .010 [0.25] C A B .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A .041 [1.04] TYPICAL 4221445/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15], per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 41 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 EXAMPLE BOARD LAYOUT D0008B SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] 8X (.055) [1.4] SEE DETAILS SYMM SEE DETAILS SYMM 1 1 8 8X (.024) [0.6] 8 SYMM 5 4 6X (.050 ) [1.27] 8X (.024) [0.6] (R.002 ) TYP [0.05] SYMM 5 4 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) [0.05] TYP (.217) [5.5] HV / ISOLATION OPTION .162 [4.1] CLEARANCE / CREEPAGE IPC-7351 NOMINAL .150 [3.85] CLEARANCE / CREEPAGE LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:6X METAL SOLDER MASK OPENING EXPOSDE METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND .0028 MAX [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4221445/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com 42 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 TMCS1100-Q1 www.ti.com.cn ZHCSM20 – JUNE 2021 EXAMPLE STENCIL DESIGN D0008B SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] 8X (.055) [1.4] SYMM SYMM 1 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] 8 SYMM 5 4 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 6X (.050 ) [1.27] 5 4 (R.002 ) [0.05] TYP (.217) [5.5] (.213) [5.4] HV / ISOLATION OPTION .162 [4.1] CLEARANCE / CREEPAGE IPC-7351 NOMINAL .150 [3.85] CLEARANCE / CREEPAGE SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.127 MM] THICK STENCIL SCALE:6X 4221445/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TMCS1100-Q1 43 PACKAGE OPTION ADDENDUM www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number (1) Status Material type (1) (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material MSL rating/ Peak reflow (4) (5) Op temp (°C) Part marking (6) TMCS1100A1QDRQ1 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 Q100A1 TMCS1100A1QDRQ1.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 Q100A1 TMCS1100A2QDRQ1 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 Q100A2 TMCS1100A2QDRQ1.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 Q100A2 TMCS1100A3QDRQ1 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 Q100A3 TMCS1100A3QDRQ1.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 Q100A3 TMCS1100A4QDRQ1 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 Q100A4 TMCS1100A4QDRQ1.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 Q100A4 Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 23-May-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMCS1100-Q1 : • Catalog : TMCS1100 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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