TMDS251PAGR

TMDS251 SLLS852A – AUGUST 2007 – REVISED JULY 2011 www.ti.com 2.5 Gbps 2-TO-1 DVI/HDMI SWITCH Check for Samples: TMDS251 FEATURES 1 • • • • • • • Compatible with HDMI 1.3a Supports 2.5 Gbps Signaling Rate for 480i/p, 720i/p, and 1080i/p Resolutions up to 12-Bit Color Depth Integrated Switchable Receiver Termination Selectable Receiver Equalization to Accommodate to Different Input Cable Lengths Intra-Pair Skew < 40 ps Inter-Pair Skew < 65 ps HBM ESD Protection Exceeds 8 kV to TMDS Inputs • • • • • • • 3.3-V Fixed Supply to TMDS I/Os 5-V Fixed Supply to HPD, DDC, and Source Selection Circuits 64-Pin TQFP Package Footprint Compatible with 3-to-1 Switch TMDS351 with Port 3 Disabled ROHS Compatible and 260°C Reflow Rated TMDS250 is Available with Port 1 Disabled and Ports 2 and 3 Enabled Supports 5-V to 3.3-V Level Shifting on DDC Links APPLICATIONS • • Digital TV Digital Projector DESCRIPTION The TMDS251 is a 2-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to 2 DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to 2.5 Gbps to allow 1080p resolution in 12-bit color depth. The input port is enabled by configuring source selectors, S1 and S2. When an input port is selected, the TMDS inputs are connected to the TMDS outputs through a 2-to-1 multiplexer, the MOSFET between the input DDC channel and the output DDC channel is turned on, and the HPD output follows the state of the HPD_SINK. The other input port is inactive with disconnected input terminations, disconnected TMDS inputs to the outputs, disconnected DDC inputs to the outputs, and the HPD outputs are low state. Check the source selection look up table for the details of port selections. When S1 is high and S2 is low, all input terminations are disconnected, TMDS inputs are high impedance with standard TMDS terminations, all internal MOSFETs are turned off to disable the DDC links, and all HPD outputs are connected to the HPD_SINK. This allows the initiation of the HDMI physical address discovery process. Termination resistors (50-Ω), pulled up to VCC, are integrated at each TMDS receiver input. External terminations are not required. A precision resistor is connected externally from the VSADJ pin to ground for setting the differential output voltage to be compliant with the TMDS standard. Typical Application DVD Player STB Digital TV TMDS251 2-to-1 PHY SX 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2011, Texas Instruments Incorporated TMDS251 SLLS852A – AUGUST 2007 – REVISED JULY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION CONTINUED The TMDS251 provides two levels of receiver input equalization for different ranges of cable lengths. Each TMDS receiver owns frequency responsive equalization circuits. When EQ sets low, the receiver supports the input connection in short range HDMI cables. When EQ sets high, the receiver supports the input connection in long range HDMI cables. The TMDS251 supports power saving operation. When a system is under standby mode and there is no digital audio/visual content from a connected source, the 3.3-V supply voltage, VCC, can be powered off to minimize power consumption from the TMDS inputs, outputs, and internal switching circuits. The HPD, DDC, and source selection circuits are powered up by the 5-V supply voltage, VDD, to maintain the system hot plug detect response, the DDC link from the selected source to the sink under system standby operation. The device is characterized for operation from 0°C to 70°C. 2 Copyright © 2007–2011, Texas Instruments Incorporated TMDS251 SLLS852A – AUGUST 2007 – REVISED JULY 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM EQ Vcc RINT RINT A14 B14 TMDS Rx Vcc RINT Y3 Vcc TMDS Driver RINT A12 A11 Z4 TMDS Rx RINT B12 Y4 TMDS Driver RINT A13 B13 2-to-1 MUX Z3 TMDS Rx Vcc RINT Y2 RINT TMDS Driver TMDS Rx B11 Z2 Vcc A24 B24 RINT Y1 RINT TMDS Driver TMDS Rx Z1 Vcc RINT VSADJ RINT A23 B23 TMDS Rx Vcc RINT RINT A22 B22 TMDS Rx Vcc RINT RINT A21 B21 TMDS Rx HPD1 HPD2 S1 S2 Control Logic HPD_SINK SCL1 SDA1 SCL2 SDA2 Copyright © 2007–2011, Texas Instruments Incorporated SCL_SINK SDA_SINK HPD/DDC Power Supply VDD 3 TMDS251 SLLS852A – AUGUST 2007 – REVISED JULY 2011 www.ti.com 49 50 51 52 53 54 A14 47 3 46 4 45 5 44 B14 Vcc A13 B13 GND A12 6 43 TMDS251 7 42 8 41 64-pin TQFP 9 40 B11 SCL1 SDA1 HPD1 EQ S2 32 31 30 29 28 B12 Vcc A11 Y1 Z1 GND SCL_SINK SDA_SINK HPD_SINK S1 27 33 26 34 16 25 35 15 24 36 14 23 13 22 37 21 38 12 20 39 11 19 10 Y4 Z4 Vcc Y3 Z3 GND Y2 Z2 Vcc 4 55 56 57 58 59 60 61 62 48 2 17 NC Vcc NC NC GND VSADJ 1 18 NC NC GND NC NC Vcc NC NC GND NC 63 64 NC A24 B24 Vcc A23 B23 GND A22 B22 Vcc A21 B21 SCL2 SDA2 HPD2 VDD PAG PACKAGE (TOP VIEW) Copyright © 2007–2011, Texas Instruments Incorporated TMDS251 SLLS852A – AUGUST 2007 – REVISED JULY 2011 www.ti.com PIN FUNCTIONS PIN NAME I/O NO. DESCRIPTION A11, A12, A13, A14 39, 42, 45, 48 I Source port 1 TMDS positive inputs A21, A22, A23, A24 54, 57, 60, 63 I Source port 2 TMDS positive inputs B11, B12, B13, B14 38, 41, 44, 47 I Source port 1 TMDS negative inputs B21, B22, B23, B24 53, 56, 59, 62 I Source port 2 TMDS negative inputs Y1, Y2, Y3, Y4 26,23,20,17 O Sink port TMDS positive outputs Z1, Z2, Z3, Z4 27,24,21,18 O Sink port TMDS negative outputs SCL1 37 I/O Source port 1 DDC I2C clock line SDA1 36 I/O Source port 1 DDC I2C data line SCL2 52 I/O Source port 2 DDC I2C clock line SDA2 51 I/O Source port 2 DDC I2C data line SCL_SINK 29 I/O Sink port DDC I2C clock line SDA_SINK 30 I/O Sink port DDC I2C data line HPD1 35 O Source port 1 hot plug detector output (status pin) HPD2 50 O Source port 2 hot plug detector output (status pin) HPD_SINK 31 I Sink port hot plug detector input (status pin) 32, 33 I Source selector EQ 34 I TMDS Input equalization selector (control pin) EQ = Low – HDMI 1.3 compliant cable EQ = High – 10m 28 AWG HDMI cable VSADJ 16 I TMDS compliant voltage swing control (control pin) VDD 49 VCC 6, 12, 19, 25, 40, 46, 55, 61 Power supply GND 3, 9, 15, 22, 28, 43, 58 Ground S1, S2 HPD/DDC Power supply 1, 2, 4, 5, 7, 8, 10, 11, 13, 14, 64 NC No connect: these pins should be left floating Table 1. Source Selection Lookup (1) CONTROL BITS (1) I/O SELECTED HOT PLUG DETECT STATUS S2 S1 Y/Z SCL_SINK SDA_SINK H H A1/B1 Terminations of A2/B2 are disconnected SCL1 SDA1 HPD_SINK L H L A2/B2 Terminations of A1/B1 are disconnected SCL2 SDA2 L HPD_SINK L L Disallowed (indeterminate) State All terminations are disconnected L L L H None (Z) All terminations are disconnected HPD_SINK HPD_SINK None (Z) Are pulled HIGH by external pull-up termination HPD1 HPD2 H: Logic high; L: Logic low; X: Don't care; Z: High impedance Copyright © 2007–2011, Texas Instruments Incorporated 5 TMDS251 SLLS852A – AUGUST 2007 – REVISED JULY 2011 www.ti.com EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS TMDS Input Stage TMDS Output Stage VCC VCC Y Z 50 W 50 W A B 10 mA Control Input Stage Status and Source Selector VDD VCC HPD_SINK S1 S2 EQ DDC Pass Gate HPD Output Stage VDD VDD HPD1 HPD2 6 SCL/SDA Source SCL/SDA Sink Copyright © 2007–2011, Texas Instruments Incorporated TMDS251 SLLS852A – AUGUST 2007 – REVISED JULY 2011 www.ti.com ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PACKAGE TMDS251PAGR TMDS251 64-PIN TQFP Tape/Reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range (2) –0.5 V to 6 V VDD Anm Voltage range –0.5 V to 4 V VCC (3) , Bnm 2.5 V to 4 V Ym, Zm, VSADJ, EQ –0.5V to 4 V SCLn, SCL_SINK, SDAn, SDA_SINK, HPDn, HPD_SINK, S1, S2 –0.5 V to 6 V Human body model (4) Electrostatic discharge Anm, Bnm, Ym, Zm ±8000 V All pins ±4000 V Charged-device model (5) (all pins) ±1500 V (6) ±200 V Machine model (all pins) See Dissipation Rating Table Continuous power dissipation (1) (2) (3) (4) (5) (6) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. n = 1, 2; m = 1, 2, 3, 4 Tested in accordance with JEDEC Standard 22, Test Method A114-B Tested in accordance with JEDEC Standard 22, Test Method C101-A Tested in accordance with JEDEC Standard 22, Test Method A115-A DISSIPATION RATINGS PACKAGE TA ≤ 25°C Low-K 1111 mW 11.19 mW/°C 611 mW High-K 1492 mW 14.92 820 mW 64-TQFP PAG (1) DERATING FACTOR ABOVE TA = 25°C (1) PCB JEDEC STANDARD TA = 70°C POWER RATING This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX (1) UNIT RθJB Junction-to-board thermal resistance 33.4 °C/W RθJC Junction- to-case thermal resistance 15.6 °C/W PD Device power dissipation TJ Junction Temperature (1) VIH = VCC, VIL = VCC - 0.6 V, RT = 50 Ω, AVCC = 3.3V, Am/Bm(2:4) = 2.5-Gbps HDMI data pattern, Am/Bm(1) = 250-MHz clock 590 0 750 mW 125 °C The maximum rating is simulation under 3.6-V VCC, 5.5-V VDD, and 600 mV VID. Copyright © 2007–2011, Texas Instruments Incorporated 7 TMDS251 SLLS852A – AUGUST 2007 – REVISED JULY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS VCC Supply voltage VDD Standby supply voltage TA Operating free-air temperature MIN NOM MAX 3 3.3 3.6 UNIT 4.5 5 5.5 V 0 70 °C V TMDS DIFFERENTIAL PINS VIC Input common mode voltage VCC–0.4 VCC+0.01 VID Receiver peak-to-peak differential input voltage 150 1560 mVp-p RVSADJ Resistor for TMDS compliant voltage swing range 3.66 4.02 4.47 kΩ AVCC TMDS output termination voltage, see Figure 1 3 3.3 3.6 V RT Termination resistance, see Figure 1 45 50 55 Ω 0 2.5 Gbps Signaling rate V CONTROL PINS VIH LVTTL High-level input voltage 2 VCC V VIL LVTTL Low-level input voltage GND 0.8 V GND VDD V DDC I/O PINS VI(DDC) DDC Input voltage STATUS and SOURCE SELECTOR PINS VIH LVTTL High-level input voltage 2 VDD V VIL LVTTL Low-level input voltage GND 0.8 V ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER ICC Supply current IDD Power supply current, 5-V TYP (1) MAX S1/S2 = Low/Low, Low/High, High/High 176 200 S1/S2 = High/Low 8 20 2 5 mA TEST CONDITIONS VIH = VCC, VIL = V CC – 0.6 V, RT = 50 Ω, AVCC = 3.3 V Am/Bm(2:4) = 2.5 Gbps HDMI data pattern Am/Bm(1) = 250 MHz clock MIN UNIT mA VIH = VCC, VIL = V CC – 0.6 V, RT = 50 Ω, AVCC = 3.3 V Am/Bm(2:4) = 2.5 Gbps HDMI data pattern Am/Bm(1) = 250 MHz clock TMDS DIFFERENTIAL PINS VOH Single-ended high-level output voltage AVCC–10 AVCC+10 mV VOL Single-ended low-level output voltage AVCC–600 AVCC–400 mV Vswing Single-ended output swing voltage 400 600 mV VOD(O) Overshoot of output differential voltage VOD(U) Undershoot of output differential voltage ΔVOC(SS) Change in steady-state common-mode output voltage between logic states I(OS) Short circuit output current See Figure 3 VI(open) Single-ended input voltage under high impedance input or open input II = 10 µA RINT Input termination resistance VIN = 2.9 V See Figure 2, AVCC = 3.3 V, RT = 50 Ω 15% 2× Vswing 25% 2× Vswing 5 mV -12 12 mA VCC–10 VCC+10 mV 45 50 55 Ω CONTROL PINS IIH High-level digital input current (2) VIH = 2 V or VCC -10 10 µA IIL Low-level digital input current (2) VIL = GND or 0.8 V -10 10 µA (1) (2) 8 All typical values are at 25°C and with a 3.3-V supply. IIH and IIL specifications are not applicable to the VSADJ pin. Copyright © 2007–2011, Texas Instruments Incorporated TMDS251 SLLS852A – AUGUST 2007 – REVISED JULY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT DDC I/O PINS Ilkg Input leakage current VI = 0.1 VDD to 0.9 VDD to isolated DDC inputs CIO Input/output capacitance VI(pp) = 1 V, 100 kHz RON Switch resistance IO = 3 mA, VO = 0.4 V VPASS Switch output voltage VI = 5 V, IO = 100 µA 10 µA 10 pF 40 Ω 2.4 2.7 V -10 27 STATUS AND SOURCE SELECTOR PINS IIH High-level digital input current VIH = 2 V or VDD -10 10 µA IIL Low-level digital input current VIL = GND or 0.8 V -10 10 µA VOH TTL High-level output voltage IOH = –100 μA 2.4 VDD V VOL TTL Low-level output voltage IOL = 100 μA GND 0.4 V SWITCHING CHARACTERISTICS (1) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT TMDS DIFFERENTIAL PINS (Y/Z) tPLH Propagation delay time, low-to-high-level output 400 650 900 ps tPHL Propagation delay time, high-to-low-level output 400 650 900 ps tr Differential output signal rise time (20% - 80%) 60 80 140 ps tf Differential output signal fall time (20% - 80%) 60 80 140 ps tsk(p) Pulse skew (|tPHL – tPLH|) (3) 6 20 ps tsk(D) Intra-pair differential skew, see Figure 4 20 40 ps tsk(o) Inter-pair channel-to-channel output skew (4) 30 65 ps tsk(pp) Part-to-part skew  (5) 510 ps tjit(pp) Peak-to-peak output jitter from Yj/Zj(1) residual jitter 8 20 ps tjit(pp) Peak-to-peak output jitter from Yj/Zj(2:4) residual jitter 60 80 ps tSX Select to switch output 50 70 ns ten Enable time 170 200 ns tdis Disable time 9 15 ns tpd(DDC) Propagation delay from SCLn to SCL_SINK or SDAn to SDA_SINK or SDA_SINK to SDAn 8 15 ns tsx(DDC) Switch time from SCLn to SCL_SINK 8 15 ns tpd(HPD) Propagation delay (from HPD_SINK to the active port of HPD) 14 20 ns tsx(HPD) Switch time from port select to the latest valid status of HPD 33 50 ns (1) (2) (3) (4) (5) See Figure 2, AVCC = 3.3 V, RT = 50 Ω See Figure 5, Am/Bm(1) = 250 MHz clock, Am/Bm(2:4) = 2.5 Gbps HDMI pattern See Figure 6, 10-mA Current source to the input See Figure 7, CL = 10 pF Measurements are made with the Agilent 81250 ParBert System with a N4872A generator (600 fs tJIT(CLK), 13 ps tJIT(pp)) and a N4873A analyzer. All typical values are at 25°C and with a 3.3-V supply. tsk(p) is the magnitude of the time difference between tPLH and tPHL of a specified terminal. tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of a sink-port bank when inputs of the active source port are tied together. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same source, the same supply voltages, at the same temperature, and have identical packages and test circuits. Copyright © 2007–2011, Texas Instruments Incorporated 9 TMDS251 SLLS852A – AUGUST 2007 – REVISED JULY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION AVcc RT RT ZO = RT TMDS Driver TMDS Receiver ZO = RT Figure 1. Termination for TMDS Output Driver Vcc R R INT INT RT Y A VA TMDS Receiver VID TMDS Driver CL 0.5 pF B VB V AVcc RT VY Z ID = VA − VB Vswing = VY − VZ VZ VA VB DC Coupled Vcc AC Coupled Vcc+0.2 V Vcc−0.4 V Vcc−0.2 V 0.4 V VID V VID(pp) ID 0V −0.4 V t PHL t PLH 100% 80% Vswing V OD(O) 0V Differential VOD(pp) 20% 0% tf tr VOD(U) V OC nVOC(SS) NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf < 100 ps, 100 MHz from Agilent 81250. CL includes instrumentation and fixture capacitance within 0.06 m of the D.U.T. Measurement equipment provides a bandwidth of 20 GHz minimum. Figure 2. TMDS Input, Output, and Timing Definitions 10 Copyright © 2007–2011, Texas Instruments Incorporated TMDS251 SLLS852A – AUGUST 2007 – REVISED JULY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 50 W IOS TMDS Driver 50 W + _ 0 V or 3.6 V Figure 3. Short Circuit Output Current Test Circuit VOH VY 50% VZ VOL tsk(D) Figure 4. Definition of Intra-Pair Differential Skew AVcc RT Data + Data Video Patterm Generator Coax Coax SMA RX + SMA EQ HDMI Cables 1000 mVpp Differential M U X OUT