TMDS341APFC

TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 3-TO-1 DVI/HDMI SWITCH FEATURES • • • • • • • • • • • Compatible with HDMI 1.3a Supports 2.25 Gbps Signaling Rate for 480i/p, 720i/p, and 1080i/p Resolutions up to 12-Bit Color Depth Each Port Supports HDMI or DVI Inputs Isolated Digital Display Control (DDC) Bus for Unused Ports 5-V Tolerance to all DDC and HPD_SINK Inputs Integrated Receiver Termination Inter-Pair Output Skew < 100 ps Intra-Pair Skew < 50 ps 8-dB Receiver Equalization to Compensate for 5-m DVI Cable Losses High Impedance Outputs When Disabled TMDS Inputs HBM ESD Protection • • • Exceeds 5 kV 3.3-V Supply Operation 80-Pin TQFP Package ROHS Compatible and 260°C Reflow Rated APPLICATIONS • • • • Switching From Three Digital-Video (DVI) or Digital-Audio Visual (HDMI) Sources Digital TV Digital Projector Audio Video Receiver DESCRIPTION The TMDS341A is a 3-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to 3 DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot plug detector, and an I2C interface are supported on each port. Each TMDS channel allows signaling rates up to 2.25 Gbps. The active source is selected by configuring source selectors, S1, S2, and S3. The selected TMDS inputs from each port are switched through a 3-to-1 multiplexer. The I2C interface of the selected input port is linked to the I2C interface of the output port, and the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the unused ports, the I2C interfaces are isolated, and the HPD pins are kept low. Termination resistors (50-Ω), pulled up to VCC, are integrated at each receiver input pin. External terminations are not required. A precision resistor is connected externally from the VSADJ pin to ground for setting the differential output voltage to be compliant with the TMDS standard. When the output is connected to a standard TMDS termination and OE is high, the output is high impedance. The TMDS341A provides fixed 8-dB input equalization and selectable 3-dB output de-emphasis to optimize system performance through 5-meter or longer DVI compliant cables. The device is characterized for operation from 0°C to 70°C. Typical Application DVD Player Digital TV PC or Game Machine TMDS 341A STB Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2007, Texas Instruments Incorporated TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM A14 B14 A13 B13 A12 B12 A11 B11 VCC (3.3 V) RINT Rx w/ EQ RINT Rx w/ EQ RINT Rx w/ EQ RINT Rx w/ EQ PRE VSADJ VCC (3.3 V) RINT A24 B24 Y4 Rx w/ EQ VCC RINT 3−to−1 MUX TMDS Drive Z4 A23 B23 Rx w/ EQ Y3 VCC TMDS Drive RINT A22 B22 Z3 Rx w/ EQ VCC RINT Y2 A21 TMDS Drive Rx w/ EQ B21 Z2 VCC (3.3 V) RINT Y1 TMDS Drive A34 B34 Rx w/ EQ Z1 VCC RINT OE A33 B33 Rx w/ EQ VCC S1 RINT S2 A32 B32 Rx w/ EQ S3 VCC RINT A31 B31 Rx w/ EQ HPD1 HPD2 Control Logic HPD_SINK HPD3 SCL1 SCL_SINK SDA1 SDA_SINK SCL2 SDA2 SCL3 SDA3 2 Submit Documentation Feedback TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 NC V CC HP D3 SD A 3 S C L3 GN D B 31 A 31 B 32 VCC A 32 GN D B 33 A 33 B 34 OE 60 59 58 VCC A 34 GN D NC PFC PACKAGE (TOP VIEW) 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 GND GND 65 36 GND GND 66 35 Z1 B21 67 34 Y1 A21 68 33 V CC VCC 69 32 Z2 B22 70 31 Y2 A22 71 30 GND GND 72 29 Z3 B23 73 28 Y3 A23 74 27 V CC VCC 75 26 Z4 B24 76 25 Y4 A24 77 24 GND GND 78 23 S3 VCC 79 22 S2 HPD1 80 21 S1 Submit Documentation Feedback 20 NC 14 15 16 17 18 19 PR E 10 11 12 13 VSADJ 9 VC C 8 GND 7 A14 6 B1 4 5 VC C 4 A1 3 3 B1 3 2 C 1 GND 37 B1 2 64 A1 2 SCL_SINK SCL2 A1 1 38 VC 63 B1 1 SDA_SINK SDA2 GND HPD_SINK 39 SC L 1 40 62 NC 61 HPD2 SD A 1 VCC 3 TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 TERMINAL FUNCTIONS TERMINAL NAME I/O DESCRIPTION A11, A12, A13, A14 6, 9, 12, 15 I Port 1 TMDS positive inputs A21, A22, A23, A24 68, 71, 74, 77 I Port 2 TMDS positive inputs A31, A32, A33, A34 49, 52, 55, 58 I Port 3 TMDS positive inputs B11, B12, B13, B14 5, 8, 11, 14 I Port 1 TMDS negative inputs B21, B22, B23, B24 67, 70, 73, 76 I Port 2 TMDS negative inputs B31, B32, B33, B34 48, 51, 54, 57 I Port 3 TMDS negative inputs GND 4, 10, 16 24, 30, 36, 37, 47, 53, 59, 65, 66, 72, 78 HPD1 80 O Port 1 hot plug detector output HPD2 62 O Port 2 hot plug detector output HPD3 44 O Port 3 hot plug detector output HPD_SINK 40 I Sink side hot plug detector input High: 5-V power signal asserted from source to sink and EDID is ready Low: No 5-V power signal asserted from source to sink, or EDID is not ready Ground NC 1, 20, 41,60 OE 42 I Output enable, active low PRE 19 I Output de-emphasis adjustment High: 3 dB Low: 0 dB SCL1 3 I/O Port 1 DDC bus clock line SCL2 64 I/O Port 2 DDC bus clock line SCL3 46 I/O Port 3 DDC bus clock line SCL_SINK 38 I/O Sink side DDC bus clock line SDA1 2 I/O Port 1 DDC bus data line SDA2 63 I/O Port 2 DDC bus data line SDA3 45 I/O Port 3 DDC bus data line SDA_SINK 39 I/O Sink side DDC bus data line S1, S2, S3 21, 22, 23 I VCC VSADJ 4 NO. No connect 7, 13, 17 27, 33, 43, 50, 56 61, 69, 75, 79 Source selector input Power supply 18 I TMDS compliant voltage swing control Y1, Y2, Y3, Y4 34, 31, 28, 25 O TMDS positive outputs Z1, Z2, Z3, Z4 35, 32, 29, 26 O TMDS negative outputs Submit Documentation Feedback TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 Table 1. Source Selection Lookup CONTROL PINS (1) (1) I/O SELECTED HOT PLUG DETECT STATUS S1 S2 S3 Y/Z SCL_SINK SDA_SINK HPD1 HPD2 HPD3 H x x A1/B1 SCL1 SDA1 HPD_SINK L L L H x A2/B2 SCL2 SDA2 L HPD_SINK L L L H A3/B3 SCL3 SDA3 L L HPD_SINK L L L None (Z) None (Z) L L L H: Logic high; L: Logic low; X: Don't care; Z: High impedance Submit Documentation Feedback 5 TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS TMDS Input Stage TMDS Output Stage Vcc 25 Ω 25 Ω 50Ω Y Z 50Ω A B 10 mA Control Input Stage HPD output stage Vcc OE HPD_SINK PRE S1, S2, S3 Vcc HPD1 HPD2 HPD3 400Ω DDC pass gate Vcc SCL/SCA Source SCL/SCA Sink 8V 8V ORDERING INFORMATION (1) (1) 6 PART NUMBER PART MARKING PACKAGE TMDS341APFC TMDS341A 80-PIN TQFP TMDS341APFCR TMDS341A 80-PIN TQFP Tape/Reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Submit Documentation Feedback TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range, VCC (2) –0.5 V to 4 V Anm (3), Bnm Voltage range 2.5 V to 4 V Ym, Zm, VSADJ, PRE, Sn, OE, HPDn –0.5V to 4 V SCLn, SCL_SINK, SDAn, SDA_SINK, HPD_SINK –0.5 V to 6 V Anm, Bnm Human body model (4) Electrostatic discharge 5 kV All pins 4 kV Charged-device model (5) (all pins) 1000 V (6) 250 V Machine model (all pins) See Dissipation Rating Table Continuous power dissipation (1) (2) (3) (4) (5) (6) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. n = 1, 2, 3; m = 1, 2, 3, 4 Tested in accordance with JEDEC Standard 22, Test Method A114-B Tested in accordance with JEDEC Standard 22, Test Method C101-A Tested in accordance with JEDEC Standard 22, Test Method A115-A DISSIPATION RATINGS (1) PACKAGE TA ≤ 25°C 80-TQFP 1342 mW DERATING FACTOR ABOVE TA = 25°C (1) TA = 70°C POWER RATING 13.42 mW/°C 738 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX VCC Supply voltage 3 3.3 3.6 UNIT V TA Operating free-air temperature 0 70 °C TMDS DIFFERENTIAL PINS (A/B) VID Receiver peak-to-peak differential input voltage VIC Input common mode voltage RVSADJ Resistor for TMDS compliant voltage swing range AVCC TMDS output termination voltage, see Figure 1 RT Termination resistance, see Figure 1 Signaling rate 150 1560 VCC–0.4 VCC+0.01 mVp-p V 4.6 4.64 4.68 kΩ 3 3.3 3.6 V 45 50 55 Ω 0 2.25 Gbps CONTROL PINS (PRE; S, OE) VIH LVTTL High-level input voltage 2 VCC V VIL LVTTL Low-level input voltage GND 0.8 V GND 5.5 V DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK) VI(DDC) Input voltage STATUS PINS (HPD_SINK) VIH LVTTL High-level input voltage 2 5.3 V VIL LVTTL Low-level input voltage GND 0.8 V Submit Documentation Feedback 7 TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS ICC Supply current VIH = VCC, VIL = VCC – 0.4 V, RVSADJ = 4.64 kΩ, RT = 50 Ω, AVCC = 3.3 V Am/Bm = 1.65 Gbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 165 MHz clock PD Power dissipation VIH = VCC, VIL = VCC – 0.4 V, RVSADJ = 4.64 kΩ, RT = 50 Ω, AVCC = 3.3 V Am/Bm = 1.65 Gbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 165 MHz clock MIN TYP (1) MAX UNIT 190 230 mA 394 657 mW TMDS DIFFERENTIAL PINS (A/B; Y/Z) VOH Single-ended high-level output voltage AVCC–10 AVCC+10 mV VOL Single-ended low-level output voltage AVCC–600 AVCC–400 mV Vswing Single-ended output swing voltage 400 600 mV VOD(O) Overshoot of output differential voltage VOD(U) Undershoot of output differential voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states I(O)OFF Single-ended standby output current 0 V ≤ VCC ≤ 1.5 V, AVCC = 3.3 V, RT = 50 Ω |I(OS)| Short circuit output current See Figure 3 VODE(SS) Steady state output differential voltage with de-emphasis VODE(pp) Peak-to-peak output differential voltage See Figure 4, PRE = VCC, Am/Bm = 250 Mbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 25 MHz clock VI(open) Single-ended input voltage under high impedance input or open input II = 10 µA RINT Input termination resistance VIN = 2.9 V See Figure 2, AVCC = 3.3 V, RT = 50 Ω, PRE = 0 V 6% 15% 2× Vswing 12% 25% 2× Vswing 0.5 5 mV 10 µA 12 mA 560 840 mVp-p 800 1200 mVp-p VCC–10 VCC+10 –10 45 mV 50 55 Ω 2 µA DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK) |Ilkg| Input leakage current VI = 0.1 VCC to 0.9 VCC to isolated DDC ports 0.1 CIO Input/output capacitance VI = 0 V 7.5 RON Switch resistance IO = 3 mA, VO = 0.4 V VPASS Switch output voltage VI = 3.3 V, IO = 100 µA 1.5 (2) pF 25 50 Ω 2.0 2.5 (3) V STATUS PINS (HPD) VOH(TTL) TTL High-level output voltage IOH = –8 mA VOL(TTL) TTL Low-level output voltage IOL = 8 mA 2.4 V 0.4 V CONTROL PINS (PRE, S, OE) |IIH| High-level digital input current VIH = 2 V or VCC 0.1 2 µA |IIL| Low-level digital input current VIL = GND or 0.8 V 0.1 2 µA VIH = 5.3 V 23 100 VIH = 2 V or VCC 0.1 2 VIL = GND or 0.8 V 0.1 2 STATUS PINS (HPD_SINK) |IIH| High-level digital input current |IIL| Low-level digital input current (1) (2) (3) 8 All typical values are at 25°C and with a 3.3-V supply. The value is tested in full temperature range at 3.0 V. The value is tested in full temperature range at 3.6 V. Submit Documentation Feedback µA µA TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT TMDS DIFFERENTIAL PINS (Y/Z) tPLH Propagation delay time, low-to-high-level output 250 800 ps tPHL Propagation delay time, high-to-low-level output 250 800 ps tr Differential output signal rise time (20% - 80%) 75 240 ps tf Differential output signal fall time (20% - 80%) 75 240 ps tsk(p) Pulse skew (|tPHL– tPLH|) 7 50 ps tsk(D) Intra-pair differential skew, see Figure 5 23 50 ps tsk(o) Inter-pair channel-to-channel output skew (2) 100 ps tsk(pp) Part-to-part skew  (3) 200 ps tjit(pp) Peak-to-peak output jitter from Y/Z(1) residual jitter tjit(pp) Peak-to-peak output jitter from Y/Z(2:4) residual jitter tjit(pp) Peak-to-peak output jitter from Y/Z(1) residual jitter tjit(pp) Peak-to-peak output jitter from Y/Z(2:4) residual jitter tPRE De-emphasis duration tSX Select to switch output ten Enable time tdis Disable time See Figure 2, AVCC = 3.3 V, RT = 50 Ω, PRE = 0 V See Figure 8, PRE = 0 V Am/Bm = 1.65 Gbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 165 MHz clock 15 30 ps 18 50 ps See Figure 8, PRE = 0 V Am/Bm = 2.25 Gbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 225 MHz clock 20 22 ps 38 78 ps See Figure 4, PRE = VCC Am/Bm = 250 Mbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 25 MHz clock See Figure 6 240 (4) ps 6 10 ns 6 10 ns 6 10 ns 0.4 2.5 ns 2 6.0 ns 3 6.5 ns DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK) tpd(DDC) Propagation delay from SCLn to SCL_SINK or SDAn to SDA_SINK or SDA_SINK to SDAn See Figure 7, CL = 10 pF CONTROL AND STATUS PINS (S, HPD_SINK, HPD) tpd(HPD) Propagation delay (from HPD_SINK to the active port of HPD) tsx(HPD) Switch time (from port select to the latest valid status of HPD) (1) (2) (3) (4) See Figure 7, CL = 10 pF All typical values are at 25°C and with a 3.3-V supply. tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of a device when inputs are tied together. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of two devices, or between channel 1 of two devices, when both devices operate with the same source, the same supply voltages, at the same temperature, and have identical packages and test circuits. The typical value is ensured by simulation. Submit Documentation Feedback 9 TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION AVcc RT RT ZO = RT TMDS Driver TMDS Receiver ZO = RT Figure 1. Termination for TMDS Output Driver Vcc R R INT INT RT Y A VA TMDS Receiver VID TMDS Driver CL 0.5 pF B VB V ID VY AVcc RT Z = VA − VB Vswing = VY − VZ VZ VA VB DC Coupled Vcc AC Coupled Vcc+0.2 V Vcc−0.4 V Vcc−0.2 V 0.4 V VID V VID(pp) ID 0V −0.4 V t PHL t PLH 100% 80% V OD(O) 0V Differential VOD(pp) 20% 0% tf tr VOD(U) V OC nVOC(SS) NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf < 100 ps, 100 MHz from Agilent 81250. CL includes instrumentation and fixture capacitance within 0.06 m of the D.U.T. Measurement equipment provides a bandwidth of 20 GHz minimum. Figure 2. Timing Test Circuit and Definitions 10 Submit Documentation Feedback TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION (continued) 50 W IOS TMDS Driver 50 W + _ 0 V or 3.6 V Figure 3. Short Circuit Output Current Test Circuit 1 bit 1 to N bit VODE(SS) VOD(pp) 80% 20% t PRE Figure 4. De-Emphasis Output Voltage Waveforms and Duration Measurement Definitions VOH VY 50% VZ tsk(D) VOL Figure 5. Definition of Intra-Pair Differential Skew Submit Documentation Feedback 11 TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION (continued) Input−1 Kept High A B Input−2/Input−3 A Kept Low B 3.3 V VCC 2 0V S1 Clocking S2 or S3 Kept High tsx Output tsx Y 75 mV Z −75 mV Hi−Z 75 mV −75 mV 3.3 V VCC 2 0V OE tdis ten Figure 6. TMDS Outputs Control Timing Definitions VCC 2 HPD_SINK VCC 2 0.4 V HPD1 tsx(HPD) tpd(HPD) tpd(HPD) 2.4 V HPD2 HPD3 0V S1 VCC 2 S2 S3 0V SDA_SINK VCC 2 tpd(DDC) tpd(DDC) VCC 2 SDA1 SDA2 SDA3 Figure 7. HPD Timing Definitions 12 Submit Documentation Feedback TMDS341A www.ti.com SLLS702B – MAY 2006 – REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION (continued) AVcc RT Data + Data − Video Patterm Generator Coax Coax SMA RX SMA EQ 5m 28AWG HDMI Cable 1000 mVpp Differential M U X + OUT 0dB