TMDS442
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SLLS757A – AUGUST 2006 – REVISED MARCH 2007
4-TO-2 DVI/HDMI SWITCH
•
FEATURES
1
• A 4-to-2 Single-Link or 2-to-1 Dual-Link
DVI/HDMI Physical Layer Switch
• Compatible with HDMI 1.3a
• Supports 2.25 Gbps Signaling Rate for 480i/p,
720i/p, and 1080i/p Resolutions up to 12-Bit
Color Depth
• Integrated Receiver Terminations
• 8-dB Receiver Equalizer Compensates for
Losses From Standard HDMI Cables
• Selectable Output De-Emphasis Compensates
for Losses From Flat Cables
• High-Impedance Outputs When Disabled
2
•
•
•
•
I2C Repeater Isolates Bus Capacitance at Both
Ends
TMDS Inputs HBM ESD Protection Exceeds 6
kV
3.3-V Supply Operation
128-Pin TQFP Package
ROHS Compatible and 260°C Reflow Rated
APPLICATIONS
•
•
•
•
Digital TV
Digital Projector
Audio Video Receiver
DVI or HDMI Switch
DESCRIPTION
The TMDS442, 4-to-2 port DVI/HDMI switch, allows up to 4 digital video interface (DVI) or high-definition
multimedia interface (HDMI) ports to be switched to two independent display blocks. The essential requirement
of picture-in-picture display from two digital audiovisual sources is having two individual DVI or HDMI receivers in
a digital display system. TMDS442 supports two DVI or HDMI receivers to enable multiple-source selection
(picture-in-picture), as well as supports acting as a 4-input 1-output video switch.
Each input or output port contains one 5-V power indicator (5V_PWR), one hot plug detector (HPD), a pair of I2C
interface signals (SCL/SDA), and four TMDS channels supporting data rates up to 2.25 Gbps. The 5-V power
indicator and the hot plug detector are pulled down with internal resistors, forcing a low state on these pins until
receiving a valid high signal. The I2C interface is constructed by an I2C repeater circuit to isolate the capacitance
form both ends of the buses. TMDS receivers integrate 50-Ω termination resistors pulled up to VCC, which
eliminates the need for external terminations. An 8-dB input equalization cooperates to each TMDS receiver
inputs to optimize system performance through 5-meter or longer DVI or HDMI compliant cables.
TYPICAL APPLICATION
Game
Machine
Digital TV
STB
DVD Player or DVR
TMDS
442
High Definition DVD Player
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
TMDS442
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SLLS757A – AUGUST 2006 – REVISED MARCH 2007
A precision resistor is connected externally from the VSADJ pin to ground, for setting the differential output
voltage to be compliant with the TMDS standard for all TMDS driver outputs. The PRE pin controls the TMDS
output to be operated under either a standard TMDS mode or an AC de-emphasis mode. When PRE = high, a
3-dB AC de-emphasis TMDS output swing is selected to pre-condition the output signals to overcome signal
impairments that may exist between the output of the TMDS442 and the HDMI receiver placed at a remote
location.
Each sink output port can be configured with the SA, SB, OE, I2CEN, and PRE pins. SA1, SB1, OE1, I2CEN1,
and PRE1 regulate the behaviour of sink port 1; SA2, SB2, OE2, I2CEN2, and PRE2 regulate the behaviour of
sink port 2. These control signals are hard-wire controlled by GPIO interface, or through a local I2C interface.
When GE = low, the configurations are done through a local I2C interface, LC_SCL, LC_SDA, LC_A0, and
LC_A1 pins, and the 5V_EN can be programmed through the local I2C interface. It is default high after device
powered on. When GE = high, the configurations are done through GPIO pins regardless the value of the 5V_EN
in the internal I2C registers.
The two bit source selector pins, SA and SB, determine the source transferred to the sink port. The internal
multiplexer interconnects the TMDS channels and I2C interface from the selected source port to the sink port.
The HPD output of the selected source port follows the status of the HPD_SINK. Since two of the source ports
will always be unconnected to any output, the I2C interfaces of unselected ports are isolated and the HPD
outputs of an unselected port are pulled low.
The TMDS outputs of each of the sink ports are enabled based on the OE signal and 5V_PWR signal (from the
selected source port). When OE is low, for an output port, and the 5V_PWR signal from the selected source port
is high, the TMDS output signals are enabled; otherwise they are disabled, and high impedance.
The I2C driver at sink side, SCL_SINK and SDA_SINK, are enabled by setting I2CEN high. When I2CEN is low,
the I2C driver can not forward a low state to the I2C bus connected at the sink port. A hard wire output voltage
select pin, OVS, allows adjustable output voltage level to SCL_SINK and SDA_SINK to optimise noise margins
while interfacing to different HDMI receivers. The I2C driver of each source port, SCL and SDA, is controlled by
its 5V_PWR signal. A valid 5-V signal appearing at the input of 5V_PWR enables the I2C driver of the source
port.
The device is packaged in a 128-pin PowerPAD TQFP package and characterized for operation from 0°C to
70°C.
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
A14
B14
A13
B13
A12
B12
A11
B11
A24
B24
A23
B23
A22
B22
A21
B21
A34
B34
A33
B33
A32
B32
A31
B31
Quad
Terminated
TMDS Rx
with EQ
Quad
Terminated
TMDS Rx
with EQ
Quad
TMDS Tx
4-to-2
Dual
MUX
4-to-1
MUX
Y14
Z14
Y13
Z13
Y12
Z12
Y11
Z11
PRE1 OE1
VSADJ
Quad
Terminated
TMDS Rx
with EQ
Quad
TMDS Tx
Y24
Z24
Y23
Z23
Y22
Z22
Y21
Z21
PRE2 OE2
A44
B44
A43
B43
A42
B42
A41
B41
SA1
SB1
Quad
Terminated
TMDS Rx
with EQ
LC_SCL
LC_SDA
SA2
SB2
LC_A0
LC_A1
GE
HPD1
HPD2
HPD3
HPD4
5V_PWR1
5V_PWR2
5V_PWR3
5V_PWR4
x
x
x
PRE1 I CEN1 OE1
2
SB1
SA1
x
x
x
PRE2 I CEN2 OE2
2
SB2
SA2
x
x
SP
5V_
PWR4
5V_
PWR2
5V_
PWR1
5V_EN
5V_
PWR3
HPD_SINK1
HPD_SINK2
5V_SINK1
5V_SINK2
Control Logic
SCL1
SDA1
SCL2
SDA2
SCL_SINK1
SDA_SINK1
SCL3
SDA3
SCL_SINK2
SDA_SINK2
OVS
GPIO0 (SA1)
GPIO1 (SB1)
GPIO2 (/OE1)
GPIO3 (I2CEN1)
GPIO4 (PRE1)
GPIO5 (SA2)
GPIO6 (SB2)
GPIO7 (/OE2)
GPIO8 (I2CEN2)
GPIO9 (PRE2)
GPIO10 (SP)
SCL4
SDA4
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SLLS757A – AUGUST 2006 – REVISED MARCH 2007
B44
Vcc
A43
B43
GND
A42
B42
Vcc
A41
B41
GND
SCL4
SDA4
5V_PWR4
HPD4
Vcc
LC_SCL
LC_SDA
LC_A0
LC_A1
GND
Vcc
HPD_SINK1
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
SCL_SINK1
A44
91
65
Vcc
GND
5V_SINK1
SDA_SINK1
HPD3
93
92
66
5V_PWR3
94
SDA3
96
95
PNP PACKAGE
(TOP VIEW)
SCL3
97
98
64
63
GND
GND
B31
99
62
Y11
A31
Vcc
100
101
61
60
Vcc
Z12
B32
102
59
Y12
A32
GND
103
104
58
57
GND
Z13
B33
105
56
Y13
A33
106
55
Vcc
Vcc
107
54
Z14
B34
108
Y14
A34
109
53
52
GND
110
51
VSADJ
Vcc
HPD2
111
112
50
Vcc
HPD_SINK2
5V_PWR2
SDA2
113
114
48
SCL2
115
47
46
GND
116
45
GND
B21
117
44
Z21
A21
118
Y21
Vcc
119
43
42
B22
120
41
Z22
A22
GND
121
122
40
39
Y22
GND
B23
123
38
Z23
A23
124
37
Y23
Vcc
125
36
Vcc
B24
126
Z24
A24
127
35
34
GND
128
33
GND
5V_SINK2
SDA_SINK2
SCL_SINK2
Vcc
Y24
32
31
GE
GND
OVS
30
GPIO9 (PRE2)
GPIO (SP)
28
29
27
26
GPIO6 (SB2)
GPIO7 (/OE2)
GPIO8 (I2CEN2)
GPIO5 (SA2)
23
24
25
GPIO4 (PRE1)
GPIO3 (I2CEN1)
22
GPIO2 (/OE1)
21
GPIO1 (SB1)
19
20
GPIO0 (SA1)
18
17
A14
GND
Vcc
16
15
Vcc
B14
14
A13
13
12
GND
B13
A12
10
11
9
Vcc
B12
A11
6
7
8
B11
GND
5
SCL1
4
SDA1
3
5V_PWR1
2
Vcc
HPD1
1
49
Z11
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
A11, A12,
A21, A22,
A31, A32,
A41, A42,
A13, A14
A23, A24
A33, A34
A43, A44
8, 11, 14, 17
118, 121, 124,
127
100, 103, 106,
109
82, 85, 88, 91
I
Source
Source
Source
Source
port
port
port
port
1
2
3
4
TMDS
TMDS
TMDS
TMDS
positive
positive
positive
positive
B11, B12,
B21, B22,
B31, B32,
B41, B42,
B13, B14
B23, B24
B33, B34
B43, B44
7, 10, 13, 16
117, 120, 123,
126
99, 102, 105, 108
81, 84, 87, 90
I
Source
Source
Source
Source
port
port
port
port
1
2
3
4
TMDS
TMDS
TMDS
TMDS
negative
negative
negative
negative
4
inputs
inputs
inputs
inputs
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inputs
inputs
inputs
inputs
Copyright © 2006–2007, Texas Instruments Incorporated
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SLLS757A – AUGUST 2006 – REVISED MARCH 2007
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
Y11, Y12, Y13, Y14
Y21, Y22, Y23, Y24
62, 59, 56, 53
43, 40, 37, 34
O
Sink port 1 TMDS positive outputs
Sink port 2 TMDS positive outputs
Z11, Z12, Z13, Z14
Z21, Z22, Z23, Z24
63, 60, 57, 54
44, 41, 38, 35
O
Sink port 1 TMDS negative outputs
Sink port 2 TMDS negative outputs
SCL1
SDA1
54
IO
Source Port 1 DDC I2C clock line
Source Port 1 DDC I2C data line
SCL2
SDA2
115
114
IO
Source Port 2 DDC I2C clock line
Source Port 2 DDC I2C data line
SCL3
SDA3
97
96
IO
Source Port 3 DDC I2C clock line
Source Port 3 DDC I2C data line
SCL4
SDA4
79
78
IO
Source Port 4 DDC I2C clock line
Source Port 4 DDC I2C data line
SCL_SINK1
SDA_SINK1
65
66
IO
Sink port 1 DDC I2C clock line
Sink port 1 DDC I2C data line
SCL_SINK2
SDA_SINK2
46
47
IO
Sink port 2 DDC I2C clock line
Sink port 2 DDC I2C data line
HPD1
HPD2
HPD3
HPD4
2
112
94
76
O
Source
Source
Source
Source
HPD_SINK1
HPD_SINK2
68
49
I
Sink port 1 hot plug detector input
Sink port 2 hot plug detector input
5V_PWR1
5V_PWR 2
5V_PWR 3
5V_PWR 4
3
113
95
77
I
Source
Source
Source
Source
5V_SINK1
5V_SINK 2
67
48
O
Sink Port 1 5-V power indicator output
Sink Port 2 5-V power indicator output
LC_SCL
LC_SDA
74
73
IO
Local I2C clock line
Local I2C data line
LC_A0
LC_A1
72
71
I
Local I2C address bit 0
Local I2C address bit 1
GE
31
I
GPIO Enable
L: Local I2C pins are active, GPIO pins are high impedance
H: GPIO pins are active, local I2C pins are high impedance
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
20
21
22
23
24
I
SA1 – Sink port 1 source selector
SB1 – Sink port 1 source selector
OE1 – Sink port 1 TMDS output enable
I2CEN1 – Sink port 1 DDC I2C output enable
PRE1 – Sink port 1 TMDS AC de-emphasis mode selector
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
25
26
27
28
29
30
32
I
SA2 – Sink port 2 source selector
SB2 – Sink port 2 source selector
OE2 – Sink port 2 TMDS output enable
I2CEN2 – Sink port 2 DDC I2C output enable
PRE2 – Sink port 2 TMDS AC de-emphasis mode selector
SP – Sink priority selector
OVS – SCL_SINK/SDA_SINK output voltage select
51
I
TMDS compliant voltage swing control
VSADJ
Port 1
Port 2
Port 3
Port 4
Port 1
Port 2
Port 3
Port 4
Vcc
1, 9, 15, 19 36,
42, 50, 55, 61 69,
75, 83, 89, 93
101, 107, 111,
119, 125
Power supply
GND
6, 12, 18, 33, 39,
45, 52, 58, 64 70,
80, 86, 92 98,
104, 110, 116,
122, 128
Ground
hot
hot
hot
hot
5-V
5-V
5-V
5-V
plug
plug
plug
plug
detector output
detector output
detector output
detector output
power
power
power
power
signal input
signal input
signal input
signal input
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
TMDS Output Stage
TMDS Input Stage
Y
Vcc
25 W
Z
25 W
50 W
50 W
A
B
10mA
Source-Side I2C Input/Output Stage
Sink-Side I2C Input/Output Stage
Status Input Stage
Vcc
Vcc
Vcc
400 W
SCL
SDA
LC_SDA
Vcc
SINK_SCL
SINK_SDA
400 W
400 W
HPD_SINK
5V_PWR
60 kW
V OL
Control Input Stage
Control Input Stage
Vcc
GE
GPIO
LC_SCL
Vcc
400 W
Status Output Stage
Vcc
HPD
5V_SINK
400 W
OVS
ORDERING INFORMATION (1)
(1)
6
PART NUMBER
PART MARKING
PACKAGE
TMDS442PNP
TMDS442
128-PIN TQPF
TMDS442PNPR
TMDS442
128-PIN TQPF Tape/Reel
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VCC Supply voltage range
(2)
–0.5 V to 4 V
Aim*, Bim
Voltage range
2.5 V to 4 V
Yjm, Zjm, , Vsadjj, HPDi, 5V_SINKj, LC_SCL, LC_SDA, LC_A0, LC_A1, GE, GPIO
–0.5V to 4 V
SCLi, SCL_SINKj, SDAi, SDA_SINKj, HPD_SINKj, 5V_PWRi
–0.5 V to 6 V
Aim, Bim
Human body model (3)
Electrostatic discharge
±6 kV
All pins
±5 kV
Charged-device model (4) (all pins)
±1500 V
(5)
±200 V
Machine model
(all pins)
See Dissipation
Rating Table
Continuous power dissipation
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-B
Tested in accordance with JEDEC Standard 22, Test Method C101-A
Tested in accordance with JEDEC Standard 22, Test Method A115-A
DISSIPATION RATINGS
(1)
(2)
(3)
DERATING FACTOR
ABOVE TA = 25°C
(1)
TA = 70°C
POWER RATING
PACKAGE
PCB JEDEC STANDARD
TA ≤ 25°C
128-TQFP PNP
Low-K (2)
2129.47 mW
21.2947 mW/°C
1171.20 mW
128-TQFP PNP
High-K (3)
4308.48 mW
43.0848 mW/°C
2369.66 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
In accordance with the Low-K thermal metric definitions of EIA/JESD51-3
In accordance with the High-K thermal metric definitions of EIA/JESD51-7
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
RθJB
Junction-to-board thermal resistance
RθJC
Junction- to-case thermal resistance
PD
Device power dissipation
TEST CONDITIONS
MIN
VIH = VCC, VIL = VCC - 0.6 V, RT = 50 Ω, AVCC = 3.3 V,
VCC = 3.6 V, RVSADJ = 4.6 kΩ, PRE = Low or high
Ai/Bi(2:4)= 1.65 Gbps HDMI data pattern,
Ai/Bi(1) = 165 MHz clock
TYP MAX
UNIT
7.86
°C/W
19.5
°C/W
1431
mW
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
VCC
Supply voltage
3
3.3
3.6
UNIT
V
TA
Operating free-air temperature
0
70
°C
TMDS DIFFERENTIAL PINS (A/B)
VIC
Input common mode voltage
VCC–400
VCC+10
VID
Receiver peak-to-peak differential input voltage
150
1560
mVp-p
RVSADJ
Resistor for TMDS compliant voltage swing range
4.6
4.64
4.68
kΩ
AVCC
TMDS Output termination voltage, see Figure 3
3
3.3
3.6
V
RT
Termination resistance, see Figure 3
45
50
55
Ω
Signaling rate
mV
0
2.25
Gbps
2
VCC
V
CONTROL PINS (LC_A0, LC_A1, GE, GPIO)
VIH
LVTTL High-level input voltage
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RECOMMENDED OPERATING CONDITIONS (continued)
MIN
VIL
LVTTL Low-level input voltage
NOM
MAX
UNIT
GND
0.8
V
CONTROL PINS (OVS)
VIH
LVTTL High-level input voltage
3
3.6
V
VIL
LVTTL Low-level input voltage
-0.5
0.5
V
STATUS PINS (HPD_SINK, 5V_PWR)
VIH
High-level input voltage
2
5.3
V
VIL
Low-level input voltage
GND
0.8
V
DDC I/O PINS (SCL_SINK, SDA_SINK)
VIH
High-level input voltage
0.7VCC
5.5
V
VIL
Low-level input voltage
-0.5
0.3VCC
V
VILC
Low-level input voltage contention (1)
-0.5
0.4
V
DDC I/O PINS (SCL, SDA)
VIH
High-level input voltage
2.1
5.5
V
VIL
Low-level input voltage
-0.5
1.5
V
LOCAL I2C PINS (LC_SCL, LC_SDA)
VIH
High-level input voltage
0.7VCC
VCC
V
VIL
Low-level input voltage
-0.5
0.3VCC
V
(1)
VIL specification is for the first low level seen by the SCL_SINK/SDA_SINK lines. VILC is for the second and subsequent low levels seen
by the SCL_SINK/SDA_SINK lines.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ICC
Supply current
VIH = VCC, VIL = VCC – 0.4 V, RT = 50 Ω,
AVCC = 3.3 V,
Ai/Bi(2:4) = 1.65-Gbps HDMI data pattern,
Ai/Bi(1) = 165-MHz Pixel clock
PD
Power dissipation
VIH = VCC, VIL = VCC – 0.4 V, RT = 50 Ω,
AVCC = 3.3 V,
Ai/Bi(2:4) = 1.65-Gbps HDMI data pattern,
Ai/Bi(1) = 165-MHz Pixel clock
MIN
TYP (1)
MAX
UNIT
250
412 (2)
mA
640
1344 (2)
mW
TMDS DIFFERENTIAL PINS (A/B, Y/Z)
VOH
Single-ended high-level output voltage
AVCC–10
AVCC+10
mV
VOL
Single-ended low-level output voltage
AVCC–600
AVCC–400
mV
Vswing
Single-ended output swing voltage
400
600
mV
VOD(O)
Overshoot of output differential voltage
15%
2× Vswing
VOD(U)
Undershoot of output differential voltage
25%
2× Vswing
ΔVOC(SS)
Change in steady-state common-mode
output voltage between logic states
I(O)OFF
Single-ended standby output current
VOD(pp)
Peak-to-peak output differential voltage
VODE(SS)
Steady state output differential voltage
with de-emphasis
I(OS)
Short circuit output current
See Figure 6
VI(open)
Single-ended input voltage under high
impedance input or open input
II = 10 µA
RINT
Input termination resistance
VIN = 2.9 V
See Figure 4, AVCC = 3.3 V,
RT = 50 Ω
5
mV
–10
10
µA
800
1200
560
840
PRE = Low
-12
12
PRE = High
-15
15
VCC–10
VCC+10
0 V ≤ VCC ≤ 1.5 V,
AVCC = 3.3 V, RT = 50 Ω
See Figure 5, PRE = High,
AVCC = 3.3 V, RT = 50 Ω
45
50
55
mVp-p
mA
mV
Ω
STATUS PINS (HPD_SINK, 5V_PWR)
(1)
(2)
8
All typical values are at 25°C and with a 3.3-V supply.
The maximum rating is characterized under 3.6 V VCC.
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
IIH
High-level digital input current
IIL
Low-level digital input current
TEST CONDITIONS
VIH = 5.3 V
MIN
TYP (1)
MAX
UNIT
-150
150
VIH = 2 V or VCC
-85
85
VIL = GND or 0.8 V
-20
20
µA
µA
STATUS PINS (HPD, 5V_SINK)
VOH
High-level output voltage
IOH = -4 mA
VOL
Low-level output voltage
IOL = 4 mA
2.4
VCC
V
GND
0.4
V
CONTROL PINS (LC_A0, LC_A1, GE, GPIO)
IIH
High-level digital input current
VIH = 2 V or VCC
-10
10
µA
IIL
Low-level digital input current
VIL = GND or 0.8 V
-10
10
µA
CI
Input capacitance
VI = GND or VCC
10
pF
DDC I/O PINS (SCL_SINK, SDA_SINK)
VI = 5.5 V
-50
50
VI = VCC
-10
10
High-level output current
VO = 3.6 V
-10
10
µA
Low-level input current
VIL = GND
-40
40
µA
OVS = NC
470
620
OVS = GND
620
775
OVS = VCC
775
950
Ilkg
Input leakage current
IOH
IIL
VOL
Low-level output voltage
IOL = 400 μA or 4 mA
OVS = NC
VOL-VILC
CIO
Low-level input voltage below output
low-level voltage level
Input/output capacitance
Ensured by design
µA
V
70
OVS = GND
240
OVS = VCC
420
mV
VI = 5.0 V or 0 V, Freq = 100 kHz
25
VI = 3.0 V or 0 V, Freq = 100 kHz
10
pF
DDC I/O PINS (SCL, SDA) AND LOCAL I2C PINS (LC_SCL, LC_SDA)
VI = 5.5 V
-50
50
VI = VCC
-10
10
High-level output current
VO = 3.6 V
-10
10
µA
Low-level input current
VIL = GND
-10
10
µA
Low-level output voltage
IOL = 4 mA
0.2
V
VI = 5.0 V or 0 V, Freq = 100 kHz
25
VI = 3.0 V or 0 V, Freq = 100 kHz
10
Ilkg
Input leakage current
IOH
IIL
VOL
CI
Input capacitance
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SLLS757A – AUGUST 2006 – REVISED MARCH 2007
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
TMDS DIFFERENTIAL PINS (Y/Z)
tPLH
Propagation delay time, low-to-high-level output
250
800
ps
tPHL
Propagation delay time, high-to-low-level output
250
800
ps
tr
Differential output signal rise time (20% - 80%)
80
240
ps
tf
Differential output signal fall time (20% - 80%)
80
240
ps
tsk(p)
Pulse skew (|tPHL – tPLH|) (2)
50
ps
tsk(D)
Intra-pair differential skew, see Figure 7
75
ps
tsk(o)
Inter-pair channel-to-channel output skew (3)
150
ps
tsk(bb)
Bank-to-bank skew
300
ps
tsk(pp)
Part-to-part skew
1
ns
ten
Enable time
20
ns
tdis
Disable time
20
ns
tsx
TMDS Switch time
20
ns
tjit(pp)
Peak-to-peak output jitter from Y/Z(1), residual jitter
tjit(pp)
Peak-to-peak output jitter from Y/Z(2:4), residual jitter
tjit(pp)
Peak-to-peak output jitter from Y/Z(1), residual jitter
tjit(pp)
Peak-to-peak output jitter from Y/Z(2:4), residual jitter
See Figure 4, AVCC = 3.3 V,
RT = 50 Ω
(4)
See Figure 8
See Figure 9, Ai/Bi(1) = 165-MHz clock,
Ai/Bi(2:4) = 1.65-Gbps HDMI pattern,
PRE = low
Input: 5m 28AWG HDMI cable,
Output: 3-Inch 8-mil trace width
10
30
ps
48
74
ps
See Figure 9, Ai/Bi(1) = 225-MHz clock,
Ai/Bi(2:4) = 2.25-Gbps HDMI pattern,
PRE = low
Input: 5m 28AWG HDMI cable,
Output: 3-Inch 8-mil trace width
18
33
ps
56
71
ps
CONTROL AND STATUS PINS (HPD_SINK, HPD, 5V_PWR, 5V_SINK)
tpd(HPD)
Propagation delay time
15
ns
tpd(5V)
Propagation delay time
15
ns
15
ns
tsx(HPD)
HPD Switch time
tsx(5V)
5-V Power switch time
tsx
DDC Switch time
See Figure 8
CL= 10 pF, CL(DDC) = 100 pF
15
ns
1
μs
204
459
ns
35
140
ns
194
351
ns
35
140
ns
DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK)
tPLH
Propagation delay time, low-to-high-level output
SCL_SINK/SDA_SINK to SCL/SDA
tPHL
Propagation delay time, high-to-low-level
outputSCL_SINK/SDA_SINK to SCL/SDA
tPLH
Propagation delay time, low-to-high-level output SCL/SDA to
SCL_SINK/SDA_SINK
See Figure 11, OVS = NC
tPHL
Propagation delay time, high-to-low-level output SCL/SDA to
SCL_SINK/SDA_SINK
tr
Output signal rise time, SCL_SINK/SDA_SINK
500
800
ns
tf
Output signal fall time, SCL_SINK/SDA_SINK
20
72
ns
tr
Output signal rise time, SCL/SDA
796
999
ns
tf
Output signal fall time, SCL/SDA
20
72
ns
tset
Enable to start condition
thold
Enable after stop condition
(1)
(2)
(3)
(4)
10
See Figure 12
100
ns
100
ns
All typical values are at 25°C and with a 3.3-V supply.
tsk(p) is the magnitude of the time difference between tPLH and tPHL of a specified terminal.
tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of a device when
inputs are tied together.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of two devices, or
between channel 1 of two devices, when both devices operate with the same source, the same supply voltages, at the same
temperature, and have identical packages and test circuits.
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TIMING CHARACTERISTICS FOR LOCAL I2C INTERFACE (LC_SCL, LC_SDA, LC_AO, LC_A1)
STANDARD MODE
PARAMETER
MIN
MAX
FAST MODE
MIN
100
MAX
fSCL
Clock frequency, SCL
tw(L)
Clock low period, SCL low
tw(H)
Clock high period, SCL high
tr
Rise time, SCL and SDA
1000
300
μs
tf
Fall time, SCL and SDA
300
300
μs
tsu(1)
Setup time, SDA to SCL
th(1)
Hold time, SCL to SDA
t(buf)
4.7
400
UNIT
4
kHz
μs
1.3
μs
0.6
250
100
μs
0
0
μs
BUS Free time between a STOP and START condition
4.7
1.3
μs
tsu(2)
Setup time, SCL to start condition
4.7
0.6
μs
th(2)
Hold time, start condition to SCL
4
0.6
μs
tsu(3)
Setup time, SCL to stop condition
4
0.6
Cb (1)
Capacitive load for each bus line
(1)
400
μs
400
pF
Cb is the total capacitance of one bus line in pF.
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PARAMETER MEASUREMENT INFORMATION
t w(H)
t w(L)
tr
tf
SCL
t su(1)
t h(1)
SDA
A.
tr and tf are measured at 20% - 80% refered to VIHmin and VILmax levels.
Figure 1. SCL and SDA Timing
SCL
t su(2)
t h(2)
t su(3)
t (buf)
SDA
Start Condition
Stop Condition
Figure 2. Start and Stop Conditions
AVcc
RT
RT
ZO = RT
TMDS
Driver
ZO = RT
TMDS
Receiver
Figure 3. Typical Termination for TMDS Output Driver
12
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PARAMETER MEASUREMENT INFORMATION (continued)
Vcc
RINT
RINT
RT
Y
A
TMDS
Receiver
VID
VA
TMDS
Driver
CL
0.5 pF
VY
AVcc
RT
Z
B
VZ
VB
VID = VA − VB
Vswing = VY − VZ
VA
DC Coupled
Vcc
AC Coupled
Vcc+0.2 V
VB
Vcc−0.4 V
Vcc−0.2 V
VID
0.4 V
VID
VID(pp)
0V
−0.4 V
t PHL
t
PLH
100%
80%
Vswing
VOD(O)
0V Differential
VOD(pp)
20%
0%
tf
tr
VOD(U)
VOC
nVOC(SS)
NOTE: PRE = low. All input pulses are supplied by a generator having the following characteristics: tr or tf < 100 ps, 100 MHz
from Agilent 81250. CL includes instrumentation and fixture capacitance within 0.06 m of the D.U.T. Measurement
equipment provides a bandwidth of 20 GHz minimum.
Figure 4. TMDS Timing Test Circuit and Definitions
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PARAMETER MEASUREMENT INFORMATION (continued)
1 bit
VOD(PP)
1 to N bit
VODE(SS)
Figure 5. De-Emphasis Output Voltage Waveforms and Duration Measurement Definitions
50 W
IOS
TMDS
Driver
50 W
+
_
0 V or 3.6 V
Figure 6. Short Circuit Output Current Test Circuit
VOH
VY
50%
VZ
VOL
tsk(D)
Figure 7. Definition of Intra-Pair Differential Skew
14
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PARAMETER MEASUREMENT INFORMATION (continued)
Input-1
kept HIGH
A
Input-2
kept LOW
A
B
B
3.3V
Vcc
2
0V
SA
Clocking
SB
0V
kept LOW
tSX
Y
Output
tSX
75mV
-75mV
Z
75mV
-75mV
Hi-Z
3.3V
Vcc
2
0V
/OE
tdis
ten
Figure 8. TMDS Outputs Control Timing Definitions
AVcc
RT
Data +
Video
Data Patterm
Generator
800mVpp or
1200mVpp
Differential
Clk+
Clk-
Coax
Coax
SMA
SMA
RX
+EQ
SMA
28AWG
HDMI Cable
Coax
Coax
SMA
Coax
Jitter Test
Instrument
AVcc
RT
RT
Transmission media
HDMI cable
or
FR4 PCB trace
SMA
SMA
SMA
Coax
OUT
TMDS442
RX
+EQ
RT
Coax
OUT
SMA
Coax
Jitter Test
Instrument
TTP1
TTP2
TTP3
TTP4
-12
A.
All jitters are measured in BER of 10
B.
The residual jitter reflects the total jitter measured at the TMDS442 output, TP3, subtract the total jitter from the signal
generator, TP1
C.
The input cable length and the output transmission media are specified in the test conditions.
Figure 9. Jitter Test Circuit
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PARAMETER MEASUREMENT INFORMATION (continued)
Port 1 is the Source
Port 2 is the Source
SA
Vcc
2
SB
0V
5V_PWR1
1.5V
5V
5V_PWR2
5V_PWR3
5V
or
0V
5V_PWR4
5V
or
0V
5V_SINK
Vcc/2
tpd (5V)
tsx (5V)
tpd (5V)
HPD_SINK
1.5V
tsx (HPD)
HPD1
Vcc/2
tpd (HPD)
HPD2
tpd (HPD)
Vcc
Vcc/2
0V
tpd (HPD)
HPD3
0V
HPD4
0V
SDA1
SDA2
2.0V
SDA_SINK
0.6V
tsx (DDC)
Figure 10. Post Switch Timing Definitions
16
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PARAMETER MEASUREMENT INFORMATION (continued)
Vcc
VCC
3.3V + 10%
SCL/SDA
Input
Vcc/2
RL=4.7kW
PULSE
GENERATOR
0.1V
D.U.T.
RT
tPHL
C L=100pF
VIN
tPLH
80%
VOUT
SCL_SINK/
SDA_SINK
Output
80%
20%
1.5V
20%
tf
3.3V +
10%
tr
VOL
Vcc
VCC
5V + 10%
SCL_SINK/
SDA_SINK
Input
1.5V
RL=1.67kW
PULSE
GENERATOR
0.1V
D.U.T.
RT
tPHL
C L=400pF
VIN
80%
VOUT
SCL/SDA
Output
80%
20%
Vcc/2
20%
tf
5V +
10%
tr
VOL
Vcc
SCL_SINK/
SDA_SINK
Input
0.5V
tPLH
5V +
10%
SCL/SDA
Output
Vcc/2
Figure 11. I2C Timing Test Circuit and Definition
START
STOP
5V
SCL
0V
5V
VCC/2
SDA
0V
V CC
1.5V
5V_PWR
0V
t SET
t HOLD
V CC
I2CEN
0V
2
Figure 12. I C Setup and Hold Definition
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREQUENCY
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
320
325
319
317
ICC - Supply Current - mA
ICC - Supply Current - mA
318
VID(PP) = 1000 mV, PRE = High
316
315
VID(PP) = 1000 mV, PRE = Low
314
313
312
311
VCC = AVCC = 3.3 V, RT = 50 W,
RVSADJ = 4.64 kW, TA = 25°C,
SA1 = SB1 = Low, 5V_PWR1 = High,
SA2 = SB2 = High, 5V_PWR4 = High,
OE1 = OE2 = Low I2CEN1 = I2CEN2 = High,
HDMI Data Pattern
320
PRE = HIGH
315
PRE = LOW
310
VCC = AVCC = 3.3 V, RT = 50 W,
305
300
RVSADJ = 4.64 kW, TA = 25°C,
SA1 = SB1 = Low, 5V_PWR1 = High,
SA2 = SB2 = High, 5V_PWR4 = High,
OE1 = OE2 = Low I2CEN1 = I2CEN2 = High,
HDMI Data Pattern, 165-Mhz Pixel Clock,
VID(PP) = 1000 mV
310
0
20
30
40
50
60
70
Figure 13.
Figure 14.
RESIDUAL PEAK-TO-PEAK JITTER
vs
DATA RATE
(DC Coupled Input: 5m Cable, Output: 1m Cable)
RESIDUAL PEAK-TO-PEAK JITTER
vs
DATA RATE
(DC Coupled Input: 5m Cable, Output: 0m Cable)
20
20
18
18
16
PRE = High,
TTP1 1200 mVPP
14
PRE = High,
TTP1 800 mVPP
12
10
See Figure 9 Jitter Test Circuit,
VCC = AVCC = 3.3 V, RT = 50 W,
8
RVSADJ = 4.64 kW, TA = 25°C
SA1 = SB1 = Low , 5V_PWR1 = High,
SA2 = SB2 = High, 5V_PWR4 = High,
OE1 = OE2 = Low,
I2CEN1 = I2CEN2 = High,
HDMI Data Pattern
6
4
2
0
16
See Figure 9 Jitter Test Circuit,
VCC = AVCC = 3.3 V, RT = 50 W,
RVSADJ = 4.64 kW, TA = 25°C
PRE = Low, 1200 mVPP
14
PRE = Low, 800 mVPP
12
PRE = High, 1200 mVPP
10
8
PRE = High, 800 mVPP
6
SA1 = SB1 = Low, 5V_PWR1 = High,
SA2 = SB2 = High, 5V_PWR4 = High,
OE1 = OE2 = Low, I2CEN1 = I2CEN2 = High,
HDMI Data Pattern
4
2
0
750
1450
1650
1850
2250
750
Data Rate - Mbps
Figure 15.
18
10
TA - Free-Air Temperature - ºC
Residual Peak-Peak Jitter - % of Tbit
Residual Peak-Peak Jitter - % of Tbit
200 250 450 650 750 850 1050 1250 1450 1650
Signaling Rates - Mbps
1450
1650
1850
Data Rate - Mbps
2250
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
RESIDUAL PEAK-TO-PEAK JITTER
vs
DATA RATE
(AC Coupled Input: 3m Cable, Output: 1m Cable)
20
20
PRE = High, 800 mVPP
18
16
14
PRE = High, 1200 mVPP
12
10
8
6
2
See Figure 9 Jitter Test Circuit, VCC = AVCC = 3.3 V,
RT = 50 W, RVSADJ = 4.64 kW, TA = 25°C, SA1 = SB1 = Low,
5V_PWR1 = High, SA2 = SB2 = High, 5V_PWR4 = High,
OE1 = OE2 = Low, I2CEN1 = I2CEN2 = High,
HDMI Data Pattern
Residual Peak-Peak Jitter - % of Tbit
Residual Peak-Peak Jitter - % of Tbit
18
4
RESIDUAL PEAK-TO-PEAK JITTER
vs
DATA RATE
(AC Coupled Input: 3m Cable, Output: 0m Cable)
16
See Figure 9 Jitter Test Circuit, VCC = AVCC = 3.3 V,
RT = 50 W, RVSADJ = 4.64 kW, TA = 25°C, SA1 = SB1 = Low,
5V_PWR1 = High, SA2 = SB2 = High, 5V_PWR4 = High,
OE1 = OE2 = Low, I2CEN1 = I2CEN2 = High,
HDMI Data Pattern
14
PRE = High, 1200 mVPP
12
10
PRE = Low, 1200 mVPP
8
6
4
PRE = Low, 800 mVPP
PRE = High, 800 mVPP
2
0
0
750
1450
1650
1850
2250
750
Data Rate - Mbps
Figure 17.
RESIDUAL PEAK-TO-PEAK JITTER
vs
PEAK-TO-PEAK DIFFERENTIAL INPUT VOLTAGE
(at TTP1, DC Coupled: 5m Cable)
30
24
30
See Figure 9 Jitter Test Circuit, VCC = AVCC = 3.3 V,
RT = 50 W, RVSADJ = 4.64 kW, TA = 25°C,
SA1 = SB1 = Low, 5V_PWR1 = High,
SA2 = SB2 = High, 5V_WPR4 = High
OE1 = OE2 = Low, I2CEN1 = I2CEN2 = High,
1.65-Gbps HDMI Data Pattern,
165-MHz pixel Clock,VID(PP) at TTP1,
PRE = Low,
TTP1 1200 mVPP
Source Jitter < 0.3UI
22
20
18
PRE = High,
TTP1 1200 mVPP
16
PRE = Low,
TTP1 800 mVPP
14
12
PRE = High,
TTP1 800 mVPP
10
See Figure 9 Jitter Test Circuit, VCC = AVCC = 3.3 V, RT = 50 W,
RVSADJ = 4.64 kW, TA = 25°C, SA1 = SB1 = Low ,
5V_PWR1 = High, SA2 = SB2 = High, 5V_PWR4 = High,
OE1 = OE2 = Low, I2CEN1 = I2CEN2 = High
165-Mhz Pixel Clock HDMI Data Pattern,
VID(PP) at TTP1, Source Jitter < 0.3 UI
28
Residual Peak-Peak Jitter - % of Tbit
Residual Peak-Peak Jitter - % of Tbit
26
26
24
22
Output:1m HDMI Cable, PRE = High
20
18
16
14
12
10
8
Output:0m HDMI Cable, PRE = Low
6
8
4
2250
Figure 18.
RESIDUAL PEAK-TO-PEAK JITTER
vs
8-MIL FR4 TRACE OUTPUT
(DC Coupled Input: 5m Cable)
28
1450
1650
1850
Data Rate - Mbps
8
12
16
8-mil FR4 Trace Length - inch
Figure 19.
100 300 500 700 900 1100 1300 1500 1700
Peak-to-Peak Differential Input Voltage - mVp-p
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT INTRA-PAIR SKEW
vs
INPUT INTRA-PAIR SKEW
(DC Coupled Input: 0m, Output: 0m)
30
Output Intra-Pair Skew - ps
25
VCC = AVCC = 3.3 V, RT = 50 W,
RVSADJ = 4.64 kW, TA = 25°C,
tr/tf > 0.3Tbit From the Source
1080p (1.485Gbps), PRE = High
20
1080i (742.5Mbps), PRE = High
15
1080i (742.5Mbps), PRE = Low
10
1080p (1.485Gbps), PRE = Low
5
SA1 = SB1 = Low, 5V_PWR1 = High,
SA2 = SB2 = High, 5V_PWR4 = High,
OE1 = OE2 = Low, I2CEN1 = I2CEN2 = High,
HDMI Data Pattern, TTP2 VID(PP) = 800 mVPP
0
0.08
20
0.16
0.24 0.32 0.4 0.48 0.56
Input Intra-Pair Skew - Tbit
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
TP1
TP2
TP3
TP4
TMDS442 Test Board
Video
Format
Generator
HDMI Cable
A
TMDS
442
HDMI Cable
B
Eye Pattern
@ TP1
@ TP2
@TP3 PRE=LOW
@TP4 PRE=HIGH
Cable A
1m
Data
Cable B
1m
Clock
5m
1m
Data
Clock
Figure 22. Eye Patterns at 148.5-MHz Pixel Clock
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DESCRIPTION
SOURCE SELECTION LOOKUP
CONTROL REGISTER BITS
I/O SELECTED
HOT PLUG DETECT STATUS
SB
SA
OE
I2CEN
Y/Z
SCL_SINK
SDA_SINK
HPD1
HPD2
HPD3
HPD4
L
L
L
H
A1/B1
SCL1
SDA1
HPD_SINK
L
L
L
L
H
L
H
A2/B2
SCL2
SDA2
L
HPD_SINK
L
L
H
L
L
H
A3/B3
SCL3
SDA3
L
L
HPD_SINK
L
H
H
L
H
A4/B4
SCL4
SDA4
L
L
L
HPD_SINK
X
X
L
L
A/B
Z
HPD_SINK is transmitted to corresponding source port
X
X
H
H
Z
SCL
SDA
HPD_SINK is transmitted to corresponding source port
X
X
H
L
Z
Z
HPD_SINK is transmitted to corresponding source port
SINK PRIORITY CONTROL
(SA1 = SA2 = Low, SB1 = SB2 = Low, OE1 = OE2 = Low, I2CEN1 = I2CEN2 = High)
SINK PRIORITY
SINK PORT 1
SINK PORT 2
SP
Y1/Z1
SCL_SINK1/SDA_SINK1
Y2/Z2
SCL_SINK2/SDA_SINK2
HPD1
L
A1/B1
SCL1/SDA1
A1/B1
Z
HPD_SINK1
H
A1/B1
Z
A1/B1
SCL1/SDA1
HPD_SINK2
5V_PWR STATUS
(SA = Low, SB = Low, OE = Low, I2CEN = High)
CONTROL STATUS SOURCE
PLUG IN STATUS
I/O SELECTED
HOT PLUG DETECT STATUS
GE
5V_EN
5V_PWR1
Y/Z
SCL_SINK/SDA_SINK
HPD1
HPD2
HPD3
HPD4
L
H
H
A1/B1
SCL1/SDA1
HPD_SINK
L
L
L
L
H
L
Z
Z
L
L
L
L
L
L
X
A1/B1
SCL1/SDA1
HPD_SINK
L
L
L
H
X
H
A1/B1
SCL1/SDA1
HPD_SINK
L
L
L
H
X
L
Z
Z
L
L
L
L
I2C POINTER REGISTER
P7
P6
P5
P4
P3
P2
P1
P0
0
0
0
0
0
0
X
X
01, Sink port 1 configuration register
10, Sink port 2 configuration register
11, Source plug-in status register
Power up default is 0000 0011
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SINK PORT 1 CONFIGURATION REGISTER
C7
C6
C5
C4
C3
C2
C1
C0
0
0
0
PRE1
I2CEN1
OE1
SB1
SA1
Power up default is 0000 1000
SINK PORT 2 CONFIGURATION REGISTER
C7
C6
C5
C4
C3
C2
C1
C0
0
0
0
PRE2
I2CEN2
OE2
SB2
SA2
Power up default is 0000 1001
SOURCE PLUG-IN STATUS REGISTER
S7
S6
S5
S4
S3
S2
S1
S0
0
0
SP
5V_EN
5V_PWR4
5V_PWR3
5V_PWR2
5V_PWR1
Power up default is 0001 0000
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APPLICATION INFORMATION
I2C Interface Notes
The I2C interface is used to access the internal registers of the TMDS442. I2C is a two-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of
a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines
are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL.
A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus
under control of the master device. The TMDS442 works as a slave and supports the standard mode transfer
(100 kbps) and fast mode transfer (400 kbps) as defined in the I2C-Bus Specification. The TMDS442 has been
tested to be fully functional with the high-speed mode (3.4 Mbps) but is not ensured at this time.
The basic I2C start and stop access cycles are shown in Figure 23. The basic access cycle consists of the
following:
• A start condition
• A slave address cycle
• Any number of data cycles
• A stop condition
SDA
SCL
S
P
Start
Condition
Stop
Condition
Figure 23. I2C Start and Stop Conditions
General I2C Protocol
•
•
•
•
24
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 23. All I2C-compatible devices should
recognize a start condition.
The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 23). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 25) by pulling the SDA line low during
the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a
communication link with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from
the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So
an acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (see Figure 26).
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 23). This releases the bus and stops the communication link
with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.
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SDA
SCL
Data Line
Stable;
Data Valid
Change of Data Allowed
Figure 24. I2C Bit Transfer
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
8
2
9
S
Clock Pulse for
Acknowledgement
Start
Condition
Figure 25. I2C Acknowledge
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
Stop
MSB
Acknowledge
Slave Address
Acknowledge
Data
Figure 26. I2C Address and Data Cycles
During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle so
that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the
receiving device will pull the SDA line low for one SCL clock cycle. A stop condition will be initiated by the
transmitting device after the last byte is transferred. An example of a write cycle can be found in Figure 27 and
Figure 28. Note that the TMDS442 does not allow multiple write transfers to occur. See Example – Writing to the
TMDS442 section for more information.
During a read cycle, the slave receiver will acknowledge the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
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acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 29 and Figure 30.
Note that the TMDS442 does not allow multiple read transfers to occur. See Example – Reading from the
TMDS442 section for more information.
From Receiver
S
Slave Address
W
A
DATA
A
DATA
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
R = Read
P
A
From Transmitter
Figure 27. I2C Write Cycle
Acknowledge
(From Receiver)
Start
Condition
A6
A5
A1
A0
R/W ACK
D7
Acknowledge
(Transmitter)
Acknowledge
(Receiver)
D6
D0
D1
ACK
D7
D6
D1
D0
ACK
SDA
2
First Data
Byte
I C Device Address and
Read/Write Bit
Other
Data Bytes
Stop
Condition
Last Data Byte
Figure 28. Multiple Byte Write Transfer
S
Slave Address
R
A
DATA
A
DATA
A
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
R = Read
P
Transmitter
Receiver
Figure 29. I2C Read Cycle
Start
Condition
SDA
Acknowledge
(From
Receiver)
A6
A0
R/W
ACK
I 2 C Device Address and
Read/Write Bit
D7
Acknowledge
(From
Transmitter)
D0
First Data
Byte
ACK
Not
Acknowledge
(Transmitter)
D7
Other
Data Bytes
D6
D1
D0
Last Data Byte
ACK
Stop
Condition
Figure 30. Multiple Byte Read Transfer
Slave Address
Both SDA and SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors should
comply with the I2C specification that ranges from 2 kΩ to 19 kΩ. When the bus is free, both lines are high. The
address byte is the first byte received following the START condition from the master device. The first 5 Bits
(MSBs) of the address are factory preset to 01011. The next two bits of the TMDS442 address are controlled by
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the logic levels appearing on the I2C-A1 and I2C-A0 pins. The I2C-A1 and I2C-A0 address inputs can be
connected to VCC for logic 1, GND for logic 0, or can be actively driven by TTL/CMOS logic levels. The device
addresses are set by the state of these pins and are not latched. Thus a dynamic address control system could
be utilized to incorporate several devices on the same system. Up to four TMDS442 devices can be connected to
the same I2C-Bus without requiring additional glue logic. Table 1 lists the possible addresses for the TMDS442.
Table 1. TMDS442 Slave Addresses
FIXED ADDRESSES
SELECTABLE WITH ADDRESS PINS
READ/WRITE BIT
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2 (A1)
BIT 1 (A0)
BIT 0 (R/W)
0
1
0
1
1
0
0
0
0
1
0
1
1
0
0
1
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
0
0
1
0
1
1
1
0
1
0
1
0
1
1
1
1
0
0
1
0
1
1
1
1
1
Sink Port Selection Register and Source Plug-In Status Register Description (Sub-Address)
The TMDS442 operates using only a single byte transfer protocol similar to Figure 27 and Figure 29. The internal
sub-address registers and the functionality of each can be found in Table 2. When writing to the device, it is
required to send one byte of data to the corresponding internal sub-address. If control of two sink ports and
source plug-in status is desired, then the master will have to cycle through the sub-addresses (sink ports) one at
a time as illustrated in the Example – Writing to the TMDS442 section for the proper procedure of writing to the
TMDS442.
During a read cycle, the TMDS442 sends the data in its selected sub-address in a single transfer to the master
device requesting the information. See the Example – Reading from the TMDS442 section of this document for
the proper procedure on reading from the TMDS442. Upon power up, the TMDS442 registers are in a default
value, 0000 0011.
Table 2. TMDS442 Sink Port and Source Plug-In Status Registers Selection
REGISTER NAME
BIT ADDRESS (b7b6b5...b0)
Sink port 1
0000 0001
Sink port 2
0000 0010
Source plug-in status
0000 0011
Sink Port Register Bit Descriptions
Each bit of the first two sub-addresses, sink port 1 and port 2 control registers, allows the user to individually
control the functionality of the TMDS442. The benefit of this process allows the user to control the functionality of
each sink port independent of the other sink port. The bit description is decoded in Table 3.
Table 3. TMDS442 Sink Port Register Bit Decoder
BIT
FUNCTION
BIT VALUES
RESULT
7, 6, 5
Reserved
000
Default value
4
PRE
0
3dB De-emphasis off
3
I2CEN
2
OE
1
3dB De-emphasis on
0
Sink side I2C buffer is disabled (Hi-Z)
1
Sink side I2C buffer is enabled
0
Sink side TMDS on
1
Sink side TMDS off (Hi-Z)
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Table 3. TMDS442 Sink Port Register Bit Decoder (continued)
BIT
FUNCTION
1, 0
BIT VALUES
RESULT
00
Source port 1 select
01
Source port 2 select
10
Source port 3 select
11
Source port 4 select
SB SA
Bits 7 (MSB), 6 and 5 – Reserved bits without function.
Bit 4 – Controls the TMDS output differential voltage.
Bit 3 – Controls the status of DDC interface, SCL_SINK and
SDA_SINK.
Bit 2 – Controls the status of TMDS interface, Y/Z.
Bits 1, and 0 (LSB) – Selects the source input of the TMDS442.
The 5-V plug in status can be read through each bit of the sub-address (source plug-in status) status register.
Each bit of the third sub-address, source plug-in status registers, allows the user to read the cable plug-in status
based on the appearance of a valid +5-V power signal from each source input port. The bit description is
decoded in Table 4.
Table 4. TMDS442 Source Plug-In Status Register Bit Decoder
BIT
FUNCTION
BIT VALUES
7, 6
Reserved
00
5
SP
4
5V_EN
3
5V_PWR4
2
5V_PWR3
1
0
5V_PWR2
5V_PWR1
RESULT
Default value
0
Sink port1 is the main display when the same source is selected by both sinks
1
Sink port2 is the main display when the same source is selected by both sinks
0
TMDS output status is not controlled by the corresponding +5-V power signal
1
TMDS output status is controlled by the corresponding +5-V power signal
0
Source side I2C buffer is disabled (Hi-Z) When source port 4 is selected by sink,
TMDS is Hi-Z
1
Source side I2C buffer is enabled When source port 4 is selected by sink, TMDS is
under the control of OE
0
Source side I2C buffer is disabled (Hi-Z)
1
When source port 3 is selected by sink, TMDS is Hi-Z
0
Source side I2C buffer is disabled (Hi-Z) When source port 2 is selected by sink,
TMDS is Hi-Z
1
Source side I2C buffer is enabled When source port 2 is selected by sink, TMDS is
under the control of OE
0
Source side I2C buffer is disabled (Hi-Z) When source port 1 is selected by sink,
TMDS is Hi-Z
1
Source side I2C buffer is enabled When source port 1 is selected by sink, TMDS is
under the control of OE
Example - Writing to the TMDS442
The proper way to write to the TMDS442 is illustrated as follows:
An I2C master initiates a write operation to the TMDS442 by generating a start condition (S) followed by the
TMDS442 I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After
receiving an acknowledge from the TMDS442, the master presents the sub-address (sink port) it wants to write
consisting of one byte of data, MSB first. The TMDS442 acknowledges the byte after completion of the transfer.
Finally the master presents the data it wants to write to the register (sink port) and the TMDS442 acknowledges
the byte. The I2C master then terminates the write operation by generating a stop condition (P). Note that the
TMDS442 does not support multi-byte transfers. To write to both sink ports – or registers - this procedure must
be repeated for each register one series at a time (i.e. repeat steps 1 through 8 for each sink port).
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STEP 1
0
2
I C Start (Master)
STEP 2
2
I C General Address (Master)
S
7
6
5
4
3
2
1
0
0
1
0
1
1
X
X
0
Where each X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either Vs+ or GND.
STEP 3
9
2
I C Acknowledge (Slave)
A
STEP 4
7
6
5
4
3
2
1
0
I2C Write Sink Port Address (Master)
0
0
0
0
0
0
Addr
Addr
Where Addr is determined by the values shown in Table 2.
STEP 5
9
I2C Acknowledge (Slave)
A
STEP 6
I2C Write Data (Master)
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
Where Data is determined by the values shown in Table 3.
STEP 7
9
I2C Acknowledge (Slave)
A
STEP 8
0
I2C Stop (Master)
P
For step 4, an example of the proper bit control for selecting sink port 2 is 0000 0010.
For step 6, an example of the proper bit control for selecting source port B, enabling TMDS outputs and DDC link
of the sink port 2 without 3.5dB de-emphasis is 0000 1001.
Example - Reading From the TMDS442
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master
initiates a write operation to the TMDS442 by generating a start condition (S) followed by the TMDS442 I2C
address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the
TMDS442, the master presents the sub-address (sink port) of the register it wants to read. After the cycle is
acknowledged (A), the master terminates the cycle immediately by generating a stop condition (P).
The second phase is the data phase. In this phase, an I2C master initiates a read operation to the TMDS442 by
generating a start condition followed by the TMDS442 I2C address (as shown below for a read operation), in
MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the TMDS442, the I2C
master receives one byte of data from the TMDS442. After the data byte has been transferred from the
TMDS442 to the master, the master generates a NOT-acknowledge followed by a stop. Similar to the write
function, to read both sink ports steps 1 through 11 must be repeated for each and every sink port desired.
TMDS Read Phase 1:
STEP 1
0
I2C Start (Master)
S
STEP 2
7
6
5
4
3
2
1
0
I2C General Address (Master)
0
1
0
1
1
X
X
0
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Where each X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either Vs+ or GND.
STEP 3
9
I2C Acknowledge (Slave)
A
STEP 4
7
6
5
4
3
2
1
0
I2C Read Sink Port Address (Master)
0
0
0
0
0
0
Addr
Addr
Where Addr is determined by the values shown in Table 2.
STEP 5
9
I2C Acknowledge (Slave)
A
STEP 6
0
I2C Stop (Master)
P
TMDS442 Read Phase 2:
STEP 7
0
I2C Start (Master)
S
STEP 8
7
6
5
4
3
2
1
0
I2C General Address (Master)
0
1
0
1
1
X
X
1
Where X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either Vs+ or GND.
STEP 9
9
2
I C Acknowledge (Slave)
A
STEP 10
2
I C Read Data (Slave)
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
Where Data is determined by the logic values contained in the Sink Port Register.
STEP 11
9
I2C Not-Acknowledge (Master)
A
STEP 12
0
I2C Stop (Master)
P
Supply Voltage
All VCC pins can be tied to a single 3.3-V power source. A 0.01-μF capacitor is connected from each VCC pin
directly to ground to filter supply noise.
TMDS Inputs
Standard TMDS terminations are integrated on all TMDS inputs. External terminations are not required. Each
input channel contains an 8-dB equalization circuit to compensate for cable losses. The voltage at the TMDS
input pins must be limited per the absolute maximum ratings. An unused input should not be connected to
ground as this would result in excessive current flow damaging the device. TMDS input pins do not incorporate
failsafe circuits. An unused input channel can be externally biased to prevent output oscillation. The
complementary input pin is recommended to be grounded through a 1-kΩ resistor and the other pin left open.
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TMDS Outputs
A 1% precision resister, 4.64-kΩ, connected from VSADJ to ground is recommended to allow the differential
output swing to provide TMDS signal levels. The differential output driver provides a typical 10-mA current sink
capability, which provides a typical 500-mV voltage drop across a 50-Ω termination resistor. A 10% accuracy
resistor is allowed to be connected when the output swing is not strictly required to meet the TMDS signal levels.
A 10% resistor provides differential output voltages in the range of 438 mV and 532 mV.
AVCC
VCC
TMDS442
ZO = RT
TMDS
Driver
RT
RT
TMDS
Receiver
ZO = RT
GND
Figure 31. TMDS Driver and Termination Circuit
Referring to Figure 31, if both VCC (TMDS442 supply) and AVCC (sink termination supply) are both powered, the
TMDS output signals are high impedance when OE = high. Both supplies being active is the normal operating
condition.
Again refer to Figure 31, if VCC is on and AVCC is off, the TMDS outputs source a typical 5-mA current through
each termination resistor to ground. A total of 10-mW of power is consumed by the terminations independent of
the OE logical selection. When AVCC is powered on, normal operation (OE controls output impedance) is
resumed.
When the power source of the device is off and the power source to termination is on, the IO(off), output leakage
current, specification ensures the leakage current is limited 10-μA or less.
The PRE pin provides 3dB de-emphasis, allowing output signal pre-conditioning to offset interconnect losses
from the TMDS442 outputs to a TMDS receiver. PRE is recommended to be set low while connecting to a
receiver throw short PCB route.
HPD Pins
The HPD signals (HPD1, HPD2, HPD3) have an output impedance of 47-Ω typically. In certain applications, a
931-Ω resistor from the HPD output to the connector pin is recommended, to increase the output resistance to
1-KΩ +/- 20%.
DDC Channels
The DDC channels are designed using I2C drivers with 5-V signal tolerance, allowing direct connection to
standard I2C buses.
Dual-Link 2-to-1 Switch Configurations
TMDS442 can be simply configured to operate as a dual-link DVI/HDMI, 2-to-1 switch, by configuring the device
as follows, see Figure 32:
1. Set SA1 = low and SA2 = high
2. Set SB1 = SB2
3. When the 5V_SINK1, HPD_SINK1, SCL_SINK1, and SDA_SINK1 are selected as the control channels
from/to the SINK, connect the 5V_PWR1, HPD1, SCL1, and SDA1 to the dual-link source 1, and connect the
5V_PWR3, HPD3, SCL3, and SDA3 to the dual-link source 2.
4. When the 5V_SINK2, HPD_SINK2, SCL_SINK2, and SDA_SINK2 are selected as the control channels
from/to the SINK, connect the 5V_PWR2, HPD2, SCL2, and SDA2 to the dual-link source 1, and connect the
5V_PWR4, HPD4, SCL4, and SDA4 to the dual-link source 2.
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TMDS DATA 5
TMDS DATA 4
TMDS DATA 3
Quad
Terminated
TMDS Rx
with EQ
TMDS DATA 2
From source 1
TMDS DATA 1
TMDS DATA 0
TMDS CLOCK
TMDS DATA 5
Quad
Terminated
TMDS Rx
with EQ
TMDS DATA 4
Quad
TMDS Tx
TMDS DATA 3
Unused Input
TMDS DATA 2
MUX
TMDS DATA 5
TMDS DATA 4
TMDS DATA 3
To SINK
TMDS DATA 1
Quad
Terminated
TMDS Rx
with EQ
TMDS DATA 0
Quad
TMDS Tx
TMDS DATA 2
TMDS CLOCK
Unused Output
From source 2
TMDS DATA 1
TMDS DATA 0
TMDS CLOCK
Quad
Terminated
TMDS Rx
with EQ
Unused Input
To source 1
HPD1
To source 2
HPD3
HPD_SINK1
HPD2
From SINK
HPD_SINK2
HPD4
From source 1
5V_PWR1
From source 2
5V_PWR3
5V_PWR4
5V_SINK1
To SINK
5V_SINK2
SCL3
SDA3
SCL4
SDA4
GPIO5 (SA2)
GPIO6 (SB2)
SCL1
SDA1
SCL2
SDA2
From/To source
2
Control Logic
GPIO0 (SA1)
GPIO1 (SB1)
From/To source
1
5V_PWR2
SCL_SINK1
SDA_SINK1
From/To SINK
SCL_SINK2
SDA_SINK2
HIGH = source 1
LOW = source 2
Figure 32. Dual-Link 2-to-1 DVI/HDMI Switch Configuration
In a dual link application, the unused TMDS input should be configured as follows: the complementary input pin
is grounded through a 1-kΩ resistor, and the other pin left open.
Layout Considerations
The high-speed TMDS inputs are the most critical paths for the TMDS442. There are several considerations to
minimize discontinuities on these transmission lines between the connectors and the device:
• The TMDS differential inputs should be layout in the shortest stubs from connectors directly
• Maintain 100-Ω differential impedance into and out of the TMDS442
• Keep an uninterrupted ground plane beneath the high-speed I/Os
• Keep the ground-path vias to the device as close as possible to allow the shortest return current path
I2C Function Description
The SCL/SDA and SCL_SINK/SDA_SINK pins are 5-V tolerant when the device is powered off and high
impedance under low supply voltage, 1.5 V or below. If the device is powered up and the I2C circuits are
enabled, and EN = high, the driver T (see Figure 33) is turned on or off depending up on the corresponding R
side voltage level.
When the R side is pulled low below 1.5 V, the corresponding T side driver turns on and pulls the T side down to
a low level output voltage, VOL. The value of VOL depends on the input to the OVS pin. When OVS is left floating
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or not connected, VOL is typically 0.5 V. When OVS is connected to GND, VOL is typically 0.65 V. When OVS is
connected to VCC, VOL is typically 0.8 V. VOL is always higher than the driver R input threshold, VIL, which is
typically 0.4 V, preventing lockup of the repeater loop. The VOL value can be selected to improve or optimize
noise margins between VOL and the VIL of the repeater itself or the VIL of some external device connected on the
T side.
When the R side is pulled up, above 1.5 V, the T side driver turns off and the T side pin is high impedance.
OVS
T
SCL
SDA
SCL_SINK
SDA_SINK
EN
R
Figure 33. I2C Drivers in TMDS442
When the T side is pulled below 0.4 V by an external I2C driver, both drivers R and T are turned on. Driver R
pulls the R side to near 0 V, and driver T is on, but is overridden by the external I2C driver. If driver T is already
on, due to a low on the R side, driver R just turns on.
When the T side is released by the external I2C driver, driver T is still on, so the T side is only able to rise to the
VOL of driver T. Driver R turns off, since VOL is above its 0.4-V VIL threshold, releasing the R side. If no external
I2C driver is keeping the R side low, the R side rises, and driver T turns off once the R side rises above 1.5 V,
see Figure 34.
Vcc
SCL_SINK/
SDA_SINK
0.5V
tPLH
5V +
10%
SCL/SDA
Vcc/2
Figure 34. Waveform of Turning Driver T Off
It is important that any external I2C driver on the T side is able to pull the bus below 0.4 V to ensure full
operation. If the T side cannot be pulled below 0.4 V, driver R may not recognize and transmit the low value to
the R side.
I2C Enable
The I2C drivers are enabled with an internal EN signal. This EN signal is the AND gate result of the 5V_PWR
signal from the selected input port and the I2CEN signal for the output. This AND gate is turned on based on an
OR gate result of the GE and the 5V_EN settings.
GE
5V_EN
EN
5V_PWR
I2CEN
Figure 35. I2C Enable Equivalent Logic
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When GE sets high, or GE sets low and 5V_EN sets high, the EN signal is the AND result of the 5V_PWR and
the I2CEN. When GE sets low and 5V_EN sets low, the EN signals follows the status of I2CEN. See Table 5.
Table 5. Truth Table for the EN Signal of the I2C Driver
(1)
GE
5V_EN (1)
5V_PWR
I2CEN
EN
1
X
1
1
1
1
X
1
0
0
1
X
0
1
0
1
X
0
0
0
0
1
1
1
1
0
1
1
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
X is 1 or 0
The I2CEN pin is active-high with an internal pull-up to VCC. It can be used to isolate a badly behaved slave
during powering up. It should never change state during an I2C operation because disabling during a bus
operation may hang the bus and enabling part way through a bus cycle could confuse the I2C parts being
enabled.
I2C Behavior
The typical application of the TMDS442 is as a repeater in a TV connecting the HDMI input connector and an
internal HDMI Rx through flat cables. The I2C repeater is 5-V tolerant, and no additional circuitry is required to
translate between 3.3-V to 5-V bus voltages. In the following example, the system master is running on an R-side
I2C-bus while the slave is connected to a T-side bus. Both buses run at 100 kHz supporting standard-mode I2C
operation. Master devices can be placed on either bus.
VRdd
V Tdd
Driver T
RRup
RTup
Master
Slave
CSOURCE
CI
CO
Cslave
Driver R
Cmedium
CCABLE
Figure 36. Typical Application
Figure 37 illustrates the waveforms seen on the R-side I2C-bus when the master writes to the slave through the
I2C repeater circuit of the TMDS442. This looks like a normal I2C transmission, and the turn on and turn off of the
acknowledge signals are slightly delayed.
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9th Clock Pulse - Acknowledge From Slave
RSCL
RSDA
Figure 37. Bus R Waveform
Figure 38 illustrates the waveforms seen on the T-side I2C-bus under the same operation in Figure 37. On the
T-side of the I2C repeater, the clock and data lines would have a positive offset from ground equal to the VOL of
the driver T. After the 8th clock pulse, the data line is pulled to the VOL of the slave device which is very close to
ground in this example. At the end of the acknowledge, the slave device releases and the bus level rises back to
the VOL set by the driver until the R-side rises above VCC/2, after which it continues to high. It is important to note
that any arbitration or clock stretching events require that the low level on the T-side bus at the input of the
TMDS442 I2C repeater is below 0.4 V to be recognized by the device and then transmitted to the R-side I2C bus.
9th Clock Pulse - Acknowledge From Slave
TSCL
TSDA
VOL Of Driver T
V OL Of Slave
Figure 38. Bus T Waveform
The I2C circuitry inside the TMDS442 allows multiple stage operation as shown in Figure 39. I2C-Bus slave
devices can be connected to any of the bus segments. The number of devices that can be connected in series is
limited by repeater delay/time of flight considerations for the maximum bus speed requirements.
Source
3.3V
5V
5V
5V
Rup
5V
3.3V
Rup SOURCE
SOURCE
Rup 1
BUS
MASTER
Sink
Repeater
3.3V
Rup
Rup 2
Rup SINK
SINK
SDA
RSDA
TSDA
SDA
SDA_SINK
RSDA
TSDA
SDA
SCL
RSCL
TSCL
SCL
SCL_SINK
RSCL
TSCL
SCL
C1
TMDS141
C2
C3
C2
C2
TMDS442
C3
EN
EN
C2
TMDS141
C1
BUS
SLAVE
EN
Figure 39. Typical Series Application
I2C Pull-up Resistors
The pull-up resistor value is determined by two requirements:
1. The maximum sink current of the I2C buffer:
The maximum sink current is 3 mA or slightly higher for an I2C driver supporting standard-mode I2C
operation,.
R up(min) + VDDńlsink
(1)
2. The maximum transition time on the bus:
The maximum transition time, T, of an I2C bus is set by an RC time constant, where R is the pull-up resistor
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value, and C is the total load capacitance. The parameter, k, can be calculated from equation 3 by solving for
t, the times at which certain voltage thresholds are reached. Different input threshold combinations introduce
different values of t. Table 6 summarizes the possible values of k under different threshold combinations.
T + k RC
(2)
V(t) + V
(1 * e *tńRC)
DD
(3)
Table 6. Value K Upon Different Input Threshold Voltages
Vth-\Vth+
0.7VDD
0.65VDD
0.6VDD
0.55VDD
0.5VDD
0.45VDD
0.4VDD
0.35VDD
0.3VDD
0.1VDD
1.0986
0.9445
0.8109
0.6931
0.5878
0.4925
0.4055
0.3254
0.2513
0.15VDD
1.0415
0.8873
0.7538
0.6360
0.5306
0.4353
0.3483
0.2683
0.1942
0.2VDD
0.9808
0.8267
0.6931
0.5754
0.4700
0.3747
0.2877
0.2076
0.1335
0.25VDD
0.9163
0.7621
0.6286
0.5108
0.4055
0.3102
0.2231
0.1431
0.0690
0.3VDD
0.8473
0.6931
0.5596
0.4418
0.3365
0.2412
0.1542
0.0741
-
From equation 1, Rup(min) = 5.5V/3mA = 1.83 kΩ to operate the bus under a 5-V pull-up voltage and provide less
than 3 mA when the I2C device is driving the bus to a low state. If a higher sink current, for example 4 mA, is
allowed, Rup(min) can be as low as 1.375 kΩ.
Given a 5-V I2C device with input low and high threshold voltages at 0.3 Vdd and 0.7 Vdd, the valued of k is
0.8473 from Table 6. Taking into account the 1.83-kΩ pull-up resistor, the maximum total load capacitance is
C(total-5V) = 645 pF. Ccable(max) should be restricted to be less than 545 pF if Csource and Ci can be as heavy as 50
pF. Here the Ci is treated as Csink, the load capacitance of a sink device.
Fixing the maximum transition time from Table 6, T = 1 μs, and using the k values from Table 6, the
recommended maximum total resistance of the pull-up resistors on an I2C bus can be calculated for different
system setups.
To support the maximum load capacitance specified in the HDMI spec, Ccable(max) = 700pF/Csource = 50pF/Ci =
50pF, R(max) can be calculated as shown in Table 7.
Table 7. Pull-Up Resistor Upon Different Threshold Voltages and 800-pF Loads
Vth-\Vth+
0.7VDD
0.65VDD
0.6VDD
0.55VDD
0.5VDD
0.45VDD
0.4VDD
0.35VDD
0.3VDD
UNIT
0.1VDD
1.14
1.32
1.54
1.80
2.13
2.54
3.08
3.84
4.97
kΩ
0.15VDD
1.20
1.41
1.66
1.97
2.36
2.87
3.59
4.66
6.44
kΩ
0.2VDD
1.27
1.51
1.80
2.17
2.66
3.34
4.35
6.02
9.36
kΩ
0.25VDD
1.36
1.64
1.99
2.45
3.08
4.03
5.60
8.74
18.12
kΩ
0.3VDD
1.48
1.80
2.23
2.83
3.72
5.18
8.11
16.87
-
kΩ
Or, limiting the maximum load capacitance of each cable to be 400 pF to accommodate with I2C spec version
2.1. Ccable(max) = 400pF/Csource=50pF/Ci = 50pF, the maximum values of R are calculated as shown in Table 8.
Table 8. Pull-Up Resistor Upon Different Threshold Voltages and 500-pF Loads
Vth-\Vth+
0.7VDD
0.65VDD
0.6VDD
0.55VDD
0.5VDD
0.45VDD
0.4VDD
0.35VDD
0.3VDD
UNIT
0.1VDD
1.82
2.12
2.47
2.89
3.40
4.06
4.93
6.15
7.96
kΩ
0.15VDD
1.92
2.25
2.65
3.14
3.77
4.59
5.74
7.46
10.30
kΩ
0.2VDD
2.04
2.42
2.89
3.48
4.26
5.34
6.95
9.63
14.98
kΩ
0.25VDD
2.18
2.62
3.18
3.92
4.93
6.45
8.96
13.98
28.99
kΩ
0.3VDD
2.36
2.89
3.57
4.53
5.94
8.29
12.97
26.99
-
kΩ
Obviously, to accommodate the 3-mA drive current specification, a narrower threshold voltage range is required
to support a maximum 800-pF load capacitance for a standard-mode I2C bus.
When the input low and high level threshold voltages, Vth- and Vth+, are 0.7 V and 1.9 V, which is 0.15 VDD and
0.4 VDD approximately with VDD = 5 V, from Table 7, the maximum pull-up resistor is 3.59 kΩ. The allowable
pull-up resistor is in the range of 1.83 kΩ and 3.59 kΩ.
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Thermal Dissipation
High-K board – It is always recommended to solder the PowerPAD™ onto the thermal land. A thermal land is the
area of solder-tinned-copper underneath the PowerPAD package. Thermal simulation shows the θJA of the
TMDS442 is 23.2°C/W on a high-K board with a 4 x 4 thermal via array, or is 29.4°C/W under the same condition
without a via array. The maximum junction temperature is 103°C with via arrays and 112°C without via arrays
when the maximum power dissipation from the device is 1.43W. The maximum recommended junction
temperature is 125°C, allowing the TMDS442 to operate over the full temperature range (0°C - 70°C) when the
PowerPAD is soldered onto the thermal land.
Low-K board – Simulation also shows the θJA of the TMDS442 is 46.9°C/W on a low-K board with the
PowerPAD soldered and no thermal vias. To ensure the maximum junction temperature does not exceed 125°C
with a worst case power dissipation from the device of 1.43W, the ambient temperature needs to be lower than
58°C, when the device is placed on a low-K board.
A general PCB design guide to PowerPAD package is provided in slma002 - PowerPAD Thermally Enhanced
Package.
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PACKAGE OPTION ADDENDUM
PACKAGING INFORMATION 30-August-2006
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins
Package
Qty
Eco Plan (2)
Lead/Ball Finish
MSL Peak Temp (3)
TMDS442PNP
ACTIVE
HTQFP
PNP
128
90
Green (RoHS & no
Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TMDS442PNPG4
ACTIVE
HTQFP
PNP
128
90
Green (RoHS & no
Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
1. The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI
does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
2. Eco Plan -The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green
(RoHS & no Sb/Br) -please check http://www.ti.com/productcontent for the latest availability information and
additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with
the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by
weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products
are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder
bumps used between the die and package, or 2) lead-based die adhesive used between the die and
leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine
(Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous
material)
3. MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard
classifications, and peak solder temperature.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and
belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties,
and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better
integrate information from third parties. TI has taken and continues to take reasonable steps to provide
representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus
CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at
issue in this document sold by TI to Customer on an annual basis.
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Revision History
Changes from Original (August 2006) to Revision A ..................................................................................................... Page
•
•
•
•
•
•
•
•
•
•
Changed HDMI 1.3 to HDMI 1.3a.......................................................................................................................................... 1
Changed 1.65 Gbps to 2.25 Gbps and 8-Bit to 12-Bit........................................................................................................... 1
Changed 1.65 Gbps to 2.25 Gbps ......................................................................................................................................... 1
Changed 1.65 Gbps to 2.25 Gbps ......................................................................................................................................... 7
Added 2.25 Gbps Peak-to-peak output jitter from Y/Z(1), residual jitter.............................................................................. 10
Added 2.25 Gbps Peak-to-peak output jitter from Y/Z(2:4), residual jitter........................................................................... 10
Changed RESIDUAL PEAK-TO-PEAK JITTER vs DATA RATE curves............................................................................. 18
Changed RESIDUAL PEAK-TO-PEAK JITTER vs DATA RATE curves............................................................................. 18
Changed RESIDUAL PEAK-TO-PEAK JITTER vs DATA RATE curves............................................................................. 19
Added RESIDUAL PEAK-TO-PEAK JITTER vs DATA RATE curves ................................................................................. 19
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMDS442PNP
ACTIVE
HTQFP
PNP
128
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TMDS442
TMDS442PNPR
ACTIVE
HTQFP
PNP
128
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TMDS442
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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