TMS320F2807x Microcontrollers
Technical Reference Manual
Literature Number: SPRUHM9F
October 2014 – Revised September 2019
Contents
Preface....................................................................................................................................... 79
1
C2000 Software Support ...................................................................................................... 80
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2
Introduction ..................................................................................................................
Features .....................................................................................................................
Floating-Point Unit .........................................................................................................
Trigonometric Math Unit ..................................................................................................
84
84
84
84
System Control .................................................................................................................. 85
3.1
3.2
3.3
3.4
3.5
3.6
2
81
81
81
81
81
81
82
C28x Processor .................................................................................................................. 83
2.1
2.2
2.3
2.4
3
Introduction ..................................................................................................................
C2000Ware Structure ......................................................................................................
Documentation ..............................................................................................................
Devices ......................................................................................................................
Libraries .....................................................................................................................
Code Composer Studio ....................................................................................................
PinMUX Tool ................................................................................................................
Introduction .................................................................................................................. 86
System Control Functional Description .................................................................................. 86
3.2.1 Device Identification .............................................................................................. 86
3.2.2 Device Configuration Registers ................................................................................. 86
Resets ....................................................................................................................... 87
3.3.1 Reset Sources ..................................................................................................... 87
3.3.2 External Reset (XRS) ............................................................................................. 87
3.3.3 Power-On Reset (POR) .......................................................................................... 87
3.3.4 Debugger Reset (SYSRS) ....................................................................................... 88
3.3.5 Watchdog Reset (WDRS) ........................................................................................ 88
3.3.6 NMI Watchdog Reset (NMIWDRS) ............................................................................. 88
3.3.7 DCSM Safe Code Copy Reset (SCCRESET) ................................................................. 88
3.3.8 Hibernate Reset (HIBRESET) ................................................................................... 88
3.3.9 Hardware BIST Reset (HWBISTRS)............................................................................ 88
3.3.10 Test Reset (TRST) ............................................................................................... 89
Peripheral Interrupts ....................................................................................................... 89
3.4.1 Interrupt Concepts................................................................................................. 89
3.4.2 Interrupt Architecture.............................................................................................. 89
3.4.3 Interrupt Entry Sequence ......................................................................................... 90
3.4.4 Configuring and Using Interrupts ................................................................................ 91
3.4.5 PIE Channel Mapping ............................................................................................ 93
3.4.6 Vector Tables ...................................................................................................... 94
Exceptions and Non-Maskable Interrupts ............................................................................. 100
3.5.1 Configuring and Using NMIs ................................................................................... 100
3.5.2 Emulation Considerations ...................................................................................... 100
3.5.3 NMI Sources ...................................................................................................... 100
3.5.4 Illegal Instruction Trap (ITRAP) ................................................................................ 101
Safety Features ........................................................................................................... 101
3.6.1 Write Protection on Registers .................................................................................. 101
3.6.2 Missing Clock Detection Logic ................................................................................. 102
Contents
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.6.3 PLLSLIP Detection ..............................................................................................
3.6.4 CPU1 Vector Address Validity Check .........................................................................
3.6.5 NMIWDs ..........................................................................................................
3.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection ................................................
3.6.7 ECC Enabled Flash Memory ...................................................................................
3.6.8 ERRORSTS Pin..................................................................................................
Clocking ...................................................................................................................
3.7.1 Clock Sources ....................................................................................................
3.7.2 Derived Clocks ...................................................................................................
3.7.3 Device Clock Domains ..........................................................................................
3.7.4 XCLKOUT.........................................................................................................
3.7.5 Clock Connectivity ...............................................................................................
3.7.6 Clock Source and PLL Setup ..................................................................................
32-Bit CPU Timers 0/1/2 .................................................................................................
Watchdog Timers .........................................................................................................
3.9.1 Servicing the Watchdog Timer .................................................................................
3.9.2 Minimum Window Check .......................................................................................
3.9.3 Watchdog Reset or Watchdog Interrupt Mode ...............................................................
3.9.4 Watchdog Operation in Low Power Modes ..................................................................
3.9.5 Emulation Considerations ......................................................................................
Low Power Modes ........................................................................................................
3.10.1 IDLE ..............................................................................................................
3.10.2 STANDBY .......................................................................................................
3.10.3 HALT .............................................................................................................
3.10.4 HIB ................................................................................................................
Memory Controller Module ..............................................................................................
3.11.1 Functional Description .........................................................................................
Flash and OTP Memory .................................................................................................
3.12.1 Features..........................................................................................................
3.12.2 Flash Tools ......................................................................................................
3.12.3 Default Flash Configuration ...................................................................................
3.12.4 Flash Bank, OTP and Pump ..................................................................................
3.12.5 Flash Module Controller (FMC) ...............................................................................
3.12.6 Flash and OTP Power-Down Modes and Wakeup .........................................................
3.12.7 Flash and OTP Performance ..................................................................................
3.12.8 Flash Read Interface ...........................................................................................
3.12.9 Erase/Program Flash ...........................................................................................
3.12.10 Error Correction Code (ECC) Protection ...................................................................
3.12.11 Reserved Locations Within Flash and OTP ...............................................................
3.12.12 Procedure to Change the Flash Control Registers .......................................................
Dual Code Security Module (DCSM) ...................................................................................
3.13.1 Functional Description .........................................................................................
3.13.2 CSM Impact on Other On-Chip Resources .................................................................
3.13.3 Incorporating Code Security in User Applications ..........................................................
JTAG .......................................................................................................................
F2807x System Control Registers ......................................................................................
3.15.1 F2807x System Control Base Addresses ...................................................................
3.15.2 CPUTIMER_REGS Registers .................................................................................
3.15.3 PIE_CTRL_REGS Registers ..................................................................................
3.15.4 WD_REGS Registers ..........................................................................................
3.15.5 NMI_INTRUPT_REGS Registers .............................................................................
3.15.6 XINT_REGS Registers .........................................................................................
3.15.7 DMA_CLA_SRC_SEL_REGS Registers ....................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Contents
103
103
104
104
104
104
105
105
107
108
109
110
111
114
116
116
117
117
118
118
119
119
119
119
120
122
122
129
129
129
130
130
130
131
132
132
134
135
139
139
140
140
146
147
151
153
153
154
161
213
219
230
239
3
www.ti.com
3.15.8
3.15.9
3.15.10
3.15.11
3.15.12
3.15.13
3.15.14
3.15.15
3.15.16
3.15.17
3.15.18
3.15.19
3.15.20
3.15.21
3.15.22
3.15.23
3.15.24
4
4.9
4.10
Introduction ................................................................................................................
Boot ROM Registers .....................................................................................................
Device Boot Sequence ...................................................................................................
Device Boot Modes .......................................................................................................
Configuring Boot Mode Pins ............................................................................................
Configuring Get Boot Options ...........................................................................................
Configuring Emulation Boot Options ...................................................................................
Device Boot Flow Diagrams .............................................................................................
4.8.1 Emulation Boot Flow Diagrams ................................................................................
4.8.2 Standalone and Hibernate Boot Flow Diagrams .............................................................
Device Reset and Exception Handling .................................................................................
4.9.1 Reset Causes and Handling....................................................................................
4.9.2 Exceptions and Interrupts Handling ...........................................................................
Boot ROM Description ...................................................................................................
4.10.1 Entry Points......................................................................................................
4.10.2 Wait Points ......................................................................................................
4.10.3 Memory Maps ...................................................................................................
4.10.4 Boot Modes ......................................................................................................
4.10.5 Boot Data Stream Structure ...................................................................................
4.10.6 GPIO Assignments .............................................................................................
4.10.7 Secure ROM Function APIs ...................................................................................
4.10.8 Clock Initializations .............................................................................................
4.10.9 Wait State Configuration .......................................................................................
4.10.10 Boot Status information.......................................................................................
4.10.11 ROM Version ..................................................................................................
558
558
558
558
560
561
562
562
563
564
565
565
566
566
566
567
567
569
582
584
586
587
587
587
588
Direct Memory Access (DMA) ............................................................................................. 589
5.1
5.2
5.3
5.4
5.5
4
246
291
313
353
355
362
369
389
396
416
462
485
502
504
513
536
545
ROM Code and Peripheral Booting ..................................................................................... 557
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5
DEV_CFG_REGS Registers ..................................................................................
CLK_CFG_REGS Registers ..................................................................................
CPU_SYS_REGS Registers .................................................................................
ROM_PREFETCH_REGS Registers .......................................................................
DCSM_COMMON_REGS Registers .......................................................................
DCSM_Z1_OTP Registers ...................................................................................
DCSM_Z1_REGS Registers .................................................................................
DCSM_Z2_OTP Registers ...................................................................................
DCSM_Z2_REGS Registers .................................................................................
MEM_CFG_REGS Registers ................................................................................
ACCESS_PROTECTION_REGS Registers ...............................................................
MEMORY_ERROR_REGS Registers ......................................................................
ROM_WAIT_STATE_REGS Registers .....................................................................
FLASH_CTRL_REGS Registers ............................................................................
FLASH_ECC_REGS Registers .............................................................................
UID_REGS Registers .........................................................................................
Register to Driverlib Function Mapping.....................................................................
Introduction ................................................................................................................
Features ....................................................................................................................
Architecture ................................................................................................................
5.3.1 Block Diagram ....................................................................................................
5.3.2 Common Peripheral Architecture ..............................................................................
5.3.3 Peripheral Interrupt Event Trigger Sources ..................................................................
5.3.4 DMA Bus ..........................................................................................................
Address Pointer and Transfer Control .................................................................................
Pipeline Timing and Throughput ........................................................................................
Contents
590
590
591
591
591
592
597
597
602
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
5.6
5.7
5.8
5.9
6
603
604
604
605
605
606
606
607
612
641
Control Law Accelerator (CLA) ........................................................................................... 643
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
CPU and CLA Arbitration ................................................................................................
Channel Priority ...........................................................................................................
5.7.1 Round-Robin Mode ..............................................................................................
5.7.2 Channel 1 High Priority Mode ..................................................................................
Overrun Detection Feature ..............................................................................................
DMA Registers ............................................................................................................
5.9.1 DMA Base Addresses ...........................................................................................
5.9.2 DMA_REGS Registers ..........................................................................................
5.9.3 DMA_CH_REGS Registers.....................................................................................
5.9.4 Register to Driverlib Function Mapping .......................................................................
Introduction ................................................................................................................
Features ....................................................................................................................
CLA Interface ..............................................................................................................
6.3.1 CLA Memory .....................................................................................................
6.3.2 CLA Memory Bus ................................................................................................
6.3.3 Shared Peripherals and EALLOW Protection ................................................................
6.3.4 CLA Tasks and Interrupt Vectors ..............................................................................
6.3.5 CLA Software Interrupt to CPU ................................................................................
CLA and CPU Arbitration ................................................................................................
6.4.1 CLA Message RAM .............................................................................................
CLA Configuration and Debug ..........................................................................................
6.5.1 Building a CLA Application .....................................................................................
6.5.2 Typical CLA Initialization Sequence ...........................................................................
6.5.3 Debugging CLA Code ...........................................................................................
6.5.4 CLA Illegal Opcode Behavior ..................................................................................
6.5.5 Resetting the CLA ...............................................................................................
Pipeline .....................................................................................................................
6.6.1 Pipeline Overview ................................................................................................
6.6.2 CLA Pipeline Alignment .........................................................................................
6.6.3 Parallel Instructions ..............................................................................................
Instruction Set .............................................................................................................
6.7.1 Instruction Descriptions .........................................................................................
6.7.2 Addressing Modes and Encoding..............................................................................
6.7.3 Instructions .......................................................................................................
CLA Registers .............................................................................................................
6.8.1 CLA Base Addresses............................................................................................
6.8.2 CLA_REGS Registers ...........................................................................................
6.8.3 CLA_SOFTINT_REGS Registers ..............................................................................
644
644
646
646
647
647
648
650
650
650
652
652
652
653
654
654
656
656
656
660
661
661
663
665
776
776
777
818
General-Purpose Input/Output (GPIO) ................................................................................. 822
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Introduction ................................................................................................................
Configuration Overview ..................................................................................................
Digital General-Purpose I/O Control....................................................................................
Input Qualification .........................................................................................................
7.4.1 No Synchronization (Asynchronous Input) ...................................................................
7.4.2 Synchronization to SYSCLKOUT Only........................................................................
7.4.3 Qualification Using a Sampling Window ......................................................................
USB Signals ...............................................................................................................
SPI Signals ................................................................................................................
GPIO and Peripheral Muxing ............................................................................................
Internal Pullup Configuration Requirements...........................................................................
GPIO Registers ...........................................................................................................
7.9.1 GPIO Base Addresses ..........................................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Contents
823
824
824
826
826
826
826
829
829
830
835
836
836
5
www.ti.com
7.9.2
7.9.3
7.9.4
8
Crossbar (X-BAR)............................................................................................................ 1058
8.1
8.2
8.3
9
9.2
1059
1060
1060
1062
1065
1066
1068
1068
1069
1082
1099
1200
1293
1402
Introduction ...............................................................................................................
9.1.1 Features ........................................................................................................
9.1.2 Block Diagram ..................................................................................................
9.1.3 Lock Registers ..................................................................................................
Analog Subsystem Registers ..........................................................................................
9.2.1 Analog Subsystem Base Addresses .........................................................................
9.2.2 ANALOG_SUBSYS_REGS Registers .......................................................................
1408
1408
1408
1411
1412
1412
1413
Analog-to-Digital Converter (ADC)..................................................................................... 1422
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
6
Input X-BAR ..............................................................................................................
ePWM, CLB, and GPIO Output X-BAR ..............................................................................
8.2.1 ePWM X-BAR ...................................................................................................
8.2.2 CLB X-BAR .....................................................................................................
8.2.3 GPIO Output X-BAR ...........................................................................................
8.2.4 X-BAR Flags ....................................................................................................
XBAR Registers .........................................................................................................
8.3.1 XBAR Base Addresses ........................................................................................
8.3.2 XBAR_REGS Registers .......................................................................................
8.3.3 INPUT_XBAR_REGS Registers .............................................................................
8.3.4 OUTPUT_XBAR_REGS Registers ..........................................................................
8.3.5 EPWM_XBAR_REGS Registers .............................................................................
8.3.6 CLB_XBAR_REGS Registers ................................................................................
8.3.7 Register to Driverlib Function Mapping ......................................................................
Analog Subsystem .......................................................................................................... 1407
9.1
10
GPIO_CTRL_REGS Registers ................................................................................. 837
GPIO_DATA_REGS Registers ............................................................................... 1002
Register to Driverlib Function Mapping ...................................................................... 1052
Introduction ...............................................................................................................
ADC Features ............................................................................................................
ADC Block Diagram .....................................................................................................
ADC Configurability .....................................................................................................
10.4.1 Clock Configuration ...........................................................................................
10.4.2 Resolution ......................................................................................................
10.4.3 Voltage Reference ............................................................................................
10.4.4 Signal Mode ....................................................................................................
10.4.5 Expected Conversion Results ...............................................................................
10.4.6 Interpreting Conversion Results .............................................................................
SOC Principle of Operation ............................................................................................
10.5.1 SOC Configuration ............................................................................................
10.5.2 Trigger Operation .............................................................................................
10.5.3 ADC Acquisition (Sample and Hold) Window .............................................................
10.5.4 ADC Input Models .............................................................................................
10.5.5 Channel Selection .............................................................................................
SOC Configuration Examples .........................................................................................
10.6.1 Single Conversion from ePWM Trigger ....................................................................
10.6.2 Oversampled Conversion from ePWM Trigger ............................................................
10.6.3 Multiple Conversions from CPU Timer Trigger ............................................................
10.6.4 Software Triggering of SOCs ................................................................................
ADC Conversion Priority ...............................................................................................
Burst Mode ...............................................................................................................
10.8.1 Burst Mode Example..........................................................................................
10.8.2 Burst Mode Priority Example ................................................................................
EOC and Interrupt Operation ..........................................................................................
Contents
1423
1423
1424
1424
1425
1425
1425
1425
1425
1426
1427
1427
1427
1428
1428
1429
1430
1430
1430
1431
1432
1432
1435
1435
1435
1437
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
10.10
10.11
10.12
10.13
10.14
10.15
10.16
11
1437
1438
1438
1438
1439
1439
1440
1441
1442
1442
1442
1442
1443
1443
1443
1444
1447
1447
1450
1451
1451
1453
1454
1454
1455
1594
1615
Buffered Digital-to-Analog Converter (DAC) ....................................................................... 1619
11.1
11.2
11.3
11.4
12
10.9.1 Interrupt Overflow ............................................................................................
10.9.2 Continue to Interrupt Mode ..................................................................................
Post-Processing Blocks ................................................................................................
10.10.1 PPB Offset Correction.......................................................................................
10.10.2 PPB Error Calculation .......................................................................................
10.10.3 PPB Limit Detection and Zero-Crossing Detection ......................................................
10.10.4 PPB Sample Delay Capture ...............................................................................
Opens/Shorts Detection Circuit (OSDETECT) ......................................................................
10.11.1 Implementation ...............................................................................................
10.11.2 Detecting an Open Input Pin ...............................................................................
10.11.3 Detecting a Shorted Input Pin ..............................................................................
Power-Up Sequence ...................................................................................................
ADC Calibration .........................................................................................................
10.13.1 ADC Zero Offset Calibration ...............................................................................
ADC Timings ............................................................................................................
10.14.1 ADC Timing Diagrams ......................................................................................
Additional Information ..................................................................................................
10.15.1 Ensuring Synchronous Operation .........................................................................
10.15.2 Choosing an Acquisition Window Duration ...............................................................
10.15.3 Achieving Simultaneous Sampling ........................................................................
10.15.4 Designing an External Reference Circuit .................................................................
10.15.5 Internal Temperature Sensor...............................................................................
ADC Registers...........................................................................................................
10.16.1 ADC Base Addresses .......................................................................................
10.16.2 ADC_REGS Registers ......................................................................................
10.16.3 ADC_RESULT_REGS Registers ..........................................................................
10.16.4 Register to Driverlib Function Mapping ...................................................................
Introduction ...............................................................................................................
11.1.1 Features ........................................................................................................
11.1.2 Block Diagram .................................................................................................
Using the DAC ...........................................................................................................
11.2.1 Initialization Sequence ........................................................................................
11.2.2 DAC Offset Adjustment .......................................................................................
11.2.3 EPWMSYNCPER Signal .....................................................................................
Lock Registers ...........................................................................................................
DAC Registers ...........................................................................................................
11.4.1 DAC Base Addresses ........................................................................................
11.4.2 DAC_REGS Registers ........................................................................................
11.4.3 Register to Driverlib Function Mapping.....................................................................
1620
1620
1620
1620
1621
1621
1621
1621
1622
1622
1623
1631
Comparator Subsystem (CMPSS) ...................................................................................... 1632
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Introduction ...............................................................................................................
Features ..................................................................................................................
12.2.1 Block Diagram .................................................................................................
Comparator...............................................................................................................
Reference DAC ..........................................................................................................
Ramp Generator .........................................................................................................
12.5.1 Ramp Generator Overview ..................................................................................
12.5.2 Ramp Generator Behavior ...................................................................................
12.5.3 Ramp Generator Behavior at Corner Cases...............................................................
Digital Filter ..............................................................................................................
12.6.1 Filter Initialization Sequence .................................................................................
Using the CMPSS .......................................................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Contents
1633
1633
1633
1634
1634
1636
1636
1636
1637
1638
1639
1639
7
www.ti.com
12.8
13
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
Introduction ...............................................................................................................
13.1.1 SDFM Features ................................................................................................
13.1.2 Block Diagram .................................................................................................
Configuring Device Pins ................................................................................................
Input Control Unit ........................................................................................................
Sinc Filter .................................................................................................................
13.4.1 Data Rate and Latency of the Sinc Filter ..................................................................
Data (Primary) Filter Unit ...............................................................................................
13.5.1 32-bit or 16-bit Data Filter Output Representation ........................................................
13.5.2 SDSYNC Event ................................................................................................
Comparator (Secondary) Filter Unit ...................................................................................
13.6.1 Higher threshold (HLT) comparator .........................................................................
13.6.2 Lower Threshold (LLT) comparator .........................................................................
Interrupt Unit .............................................................................................................
13.7.1 SDFM (SDINT) Interrupt sources: ..........................................................................
Register Descriptions ...................................................................................................
SDFM Registers .........................................................................................................
13.9.1 SDFM Base Addesses .......................................................................................
13.9.2 SDFM_REGS Registers ......................................................................................
13.9.3 Register to Driverlib Function Mapping.....................................................................
1670
1670
1671
1672
1673
1675
1676
1677
1677
1678
1679
1680
1680
1681
1681
1683
1685
1685
1686
1722
Enhanced Pulse Width Modulator (ePWM) ......................................................................... 1724
14.1
14.2
14.3
14.4
14.5
14.6
8
1639
1639
1639
1640
1641
1641
1642
1667
Sigma Delta Filter Module (SDFM) ..................................................................................... 1669
13.1
14
12.7.1 LATCHCLR and EPWMSYNCPER Signals ...............................................................
12.7.2 Synchronizer, Digital Filter and Latch Delays .............................................................
12.7.3 Calibrating the CMPSS .......................................................................................
12.7.4 Enabling and Disabling the CMPSS Clock ................................................................
CMPSS Registers .......................................................................................................
12.8.1 CMPSS Base Addresses.....................................................................................
12.8.2 CMPSS_REGS Registers ....................................................................................
12.8.3 Register to Driverlib Function Mapping.....................................................................
Introduction ...............................................................................................................
14.1.1 Submodule Overview .........................................................................................
Configuring Device Pins ................................................................................................
ePWM Modules Overview ..............................................................................................
Time-Base (TB) Submodule ...........................................................................................
14.4.1 Purpose of the Time-Base Submodule .....................................................................
14.4.2 Controlling and Monitoring the Time-Base Submodule ..................................................
14.4.3 Calculating PWM Period and Frequency ..................................................................
14.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules.....................................
14.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules ....................
14.4.6 Time-Base Counter Modes and Timing Waveforms ......................................................
14.4.7 Global Load ....................................................................................................
Counter-Compare (CC) Submodule ..................................................................................
14.5.1 Purpose of the Counter-Compare Submodule ............................................................
14.5.2 Controlling and Monitoring the Counter-Compare Submodule ..........................................
14.5.3 Operational Highlights for the Counter-Compare Submodule ...........................................
14.5.4 Count Mode Timing Waveforms ............................................................................
Action-Qualifier (AQ) Submodule .....................................................................................
14.6.1 Purpose of the Action-Qualifier Submodule ...............................................................
14.6.2 Action-Qualifier Submodule Control and Status Register Definitions ..................................
14.6.3 Action-Qualifier Event Priority ...............................................................................
14.6.4 AQCTLA and AQCTLB Shadow Mode Operations .......................................................
14.6.5 Waveforms for Common Configurations ...................................................................
Contents
1725
1727
1732
1732
1734
1734
1735
1736
1740
1740
1740
1743
1745
1745
1745
1746
1748
1751
1752
1752
1755
1756
1758
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
14.7
14.8
14.9
14.10
14.11
14.12
14.13
14.14
14.15
15
Dead-Band Generator (DB) Submodule .............................................................................
14.7.1 Purpose of the Dead-Band Submodule ....................................................................
14.7.2 Dead-band Submodule Additional Operating Modes .....................................................
14.7.3 Operational Highlights for the Dead-Band Submodule ...................................................
PWM Chopper (PC) Submodule .....................................................................................
14.8.1 Purpose of the PWM Chopper Submodule ................................................................
14.8.2 Operational Highlights for the PWM Chopper Submodule...............................................
14.8.3 Waveforms .....................................................................................................
Trip-Zone (TZ) Submodule .............................................................................................
14.9.1 Purpose of the Trip-Zone Submodule ......................................................................
14.9.2 Operational Highlights for the Trip-Zone Submodule .....................................................
14.9.3 Generating Trip Event Interrupts ............................................................................
Event-Trigger (ET) Submodule........................................................................................
14.10.1 Operational Overview of the ePWM Type 4 Event-Trigger Submodule ..............................
Digital Compare (DC) Submodule ....................................................................................
14.11.1 Purpose of the Digital Compare Submodule .............................................................
14.11.2 Enhanced Trip Action Using CMPSS .....................................................................
14.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis .........................................
14.11.4 Operation Highlights of the Digital Compare Submodule ..............................................
ePWM X-BAR ...........................................................................................................
Applications to Power Topologies ....................................................................................
14.13.1 Overview of Multiple Modules .............................................................................
14.13.2 Key Configuration Capabilities .............................................................................
14.13.3 Controlling Multiple Buck Converters With Independent Frequencies ................................
14.13.4 Controlling Multiple Buck Converters With Same Frequencies ........................................
14.13.5 Controlling Multiple Half H-Bridge (HHB) Converters ...................................................
14.13.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) .....................................
14.13.7 Practical Applications Using Phase Control Between PWM Modules ................................
14.13.8 Controlling a 3-Phase Interleaved DC/DC Converter ...................................................
14.13.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter...................................
14.13.10 Controlling a Peak Current Mode Controlled Buck Module ...........................................
14.13.11 Controlling H-Bridge LLC Resonant Converter.........................................................
High-Resolution Pulse Width Modulator (HRPWM) ............................................................
14.14.1 Operational Description of HRPWM.......................................................................
14.14.2 Appendix A: SFO Library Software - SFO_TI_Build_V8.lib ............................................
ePWM Registers ........................................................................................................
14.15.1 ePWM Base Addresses.....................................................................................
14.15.2 EPWM_REGS Registers ...................................................................................
14.15.3 SYNC_SOC_REGS Registers .............................................................................
14.15.4 Register to Driverlib Function Mapping ...................................................................
1765
1765
1765
1767
1771
1771
1771
1772
1775
1775
1775
1778
1780
1781
1786
1787
1788
1788
1788
1794
1796
1796
1796
1797
1799
1801
1803
1806
1807
1810
1811
1812
1814
1816
1838
1841
1841
1842
1973
1981
Enhanced Capture (eCAP) ................................................................................................ 1989
15.1
15.2
15.3
15.4
15.5
15.6
Introduction ...............................................................................................................
Features ..................................................................................................................
Description ...............................................................................................................
Configuring Device Pins for the eCAP ...............................................................................
Capture and APWM Operating Mode ................................................................................
Capture Mode Description .............................................................................................
15.6.1 Event Prescaler ................................................................................................
15.6.2 Edge Polarity Select and Qualifier ..........................................................................
15.6.3 Continuous/One-Shot Control ...............................................................................
15.6.4 32-Bit Counter and Phase Control ..........................................................................
15.6.5 CAP1-CAP4 Registers .......................................................................................
15.6.6 eCAP Synchronization ........................................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Contents
1990
1990
1990
1990
1992
1993
1994
1995
1995
1996
1997
1997
9
www.ti.com
15.7
15.8
15.9
16
15.6.7 Interrupt Control ...............................................................................................
15.6.8 Shadow Load and Lockout Control .........................................................................
15.6.9 APWM Mode Operation ......................................................................................
Application of the eCAP Module ......................................................................................
15.7.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger ....................................
15.7.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger ......................
15.7.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger ..................................
15.7.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger ....................
Application of the APWM Mode .......................................................................................
15.8.1 Example 1 - Simple PWM Generation (Independent Channel/s) .......................................
eCAP Registers..........................................................................................................
15.9.1 eCAP Base Addresses .......................................................................................
15.9.2 ECAP_REGS Registers ......................................................................................
15.9.3 Register to Driverlib Function Mapping.....................................................................
Enhanced Quadrature Encoder Pulse (eQEP) ..................................................................... 2027
Introduction ...............................................................................................................
Configuring Device Pins ................................................................................................
Description ...............................................................................................................
16.3.1 EQEP Inputs ...................................................................................................
16.3.2 Functional Description ........................................................................................
16.3.3 eQEP Memory Map ...........................................................................................
16.4 Quadrature Decoder Unit (QDU) ......................................................................................
16.4.1 Position Counter Input Modes ...............................................................................
16.4.2 eQEP Input Polarity Selection ...............................................................................
16.4.3 Position-Compare Sync Output .............................................................................
16.5 Position Counter and Control Unit (PCCU) ..........................................................................
16.5.1 Position Counter Operating Modes .........................................................................
16.5.2 Position Counter Latch .......................................................................................
16.5.3 Position Counter Initialization ................................................................................
16.5.4 eQEP Position-compare Unit ................................................................................
16.6 eQEP Edge Capture Unit ..............................................................................................
16.7 eQEP Watchdog .........................................................................................................
16.8 Unit Timer Base .........................................................................................................
16.9 eQEP Interrupt Structure ...............................................................................................
16.10 eQEP Registers .........................................................................................................
16.10.1 eQEP Base Addresses .....................................................................................
16.10.2 EQEP_REGS Registers ....................................................................................
16.10.3 Register to Driverlib Function Mapping ...................................................................
16.1
16.2
16.3
17
2028
2030
2030
2030
2031
2032
2033
2033
2036
2036
2036
2036
2038
2040
2041
2042
2046
2046
2047
2048
2048
2049
2083
Serial Peripheral Interface (SPI) ........................................................................................ 2085
17.1
17.2
17.3
10
1999
2000
2000
2002
2002
2003
2004
2005
2006
2006
2007
2007
2008
2025
Introduction ...............................................................................................................
17.1.1 Features ........................................................................................................
17.1.2 Block Diagram ................................................................................................
System-Level Integration ...............................................................................................
17.2.1 SPI Module Signals ...........................................................................................
17.2.2 Configuring Device Pins ......................................................................................
17.2.3 SPI Interrupts ..................................................................................................
17.2.4 DMA Support ..................................................................................................
SPI Operation ............................................................................................................
17.3.1 Introduction to Operation .....................................................................................
17.3.2 Master Mode ...................................................................................................
17.3.3 Slave Mode ....................................................................................................
17.3.4 Data Format ....................................................................................................
17.3.5 Baud Rate Selection .........................................................................................
Contents
2086
2086
2086
2087
2087
2088
2088
2090
2090
2090
2091
2092
2093
2094
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
17.4
17.5
18
Serial Communications Interface (SCI)
18.1
18.2
18.3
18.4
18.5
18.6
18.7
18.8
18.9
18.10
18.11
18.12
18.13
18.14
19
17.3.6 SPI Clocking Schemes .......................................................................................
17.3.7 SPI FIFO Description .........................................................................................
17.3.8 SPI DMA Transfers ...........................................................................................
17.3.9 SPI High-Speed Mode ........................................................................................
17.3.10 SPI 3-Wire Mode Description ..............................................................................
Programming Procedure ...............................................................................................
17.4.1 Initialization Upon Reset .....................................................................................
17.4.2 Configuring the SPI ...........................................................................................
17.4.3 Configuring the SPI for High-Speed Mode .................................................................
17.4.4 Data Transfer Example .......................................................................................
17.4.5 SPI 3-Wire Mode Code Examples ..........................................................................
17.4.6 SPI STEINV Bit in Digital Audio Transfers .................................................................
SPI Registers ............................................................................................................
17.5.1 SPI Base Addresses ..........................................................................................
17.5.2 SPI_REGS Registers .........................................................................................
17.5.3 Register to Driverlib Function Mapping.....................................................................
2095
2096
2097
2098
2098
2100
2100
2100
2101
2101
2102
2103
2105
2105
2106
2125
.............................................................................. 2127
Introduction ...............................................................................................................
Architecture ..............................................................................................................
SCI Module Signal Summary ..........................................................................................
Configuring Device Pins ................................................................................................
Multiprocessor and Asynchronous Communication Modes........................................................
SCI Programmable Data Format ......................................................................................
SCI Multiprocessor Communication ..................................................................................
18.7.1 Recognizing the Address Byte ..............................................................................
18.7.2 Controlling the SCI TX and RX Features ..................................................................
18.7.3 Receipt Sequence.............................................................................................
Idle-Line Multiprocessor Mode.........................................................................................
18.8.1 Idle-Line Mode Steps .........................................................................................
18.8.2 Block Start Signal .............................................................................................
18.8.3 Wake-UP Temporary (WUT) Flag ..........................................................................
18.8.4 Receiver Operation ...........................................................................................
Address-Bit Multiprocessor Mode .....................................................................................
18.9.1 Sending an Address ..........................................................................................
SCI Communication Format ...........................................................................................
18.10.1 Receiver Signals in Communication Modes..............................................................
18.10.2 Transmitter Signals in Communication Modes...........................................................
SCI Port Interrupts ......................................................................................................
SCI Baud Rate Calculations ...........................................................................................
SCI Enhanced Features................................................................................................
18.13.1 SCI FIFO Description .......................................................................................
18.13.2 SCI Auto-Baud ...............................................................................................
18.13.3 Autobaud-Detect Sequence ................................................................................
SCI Registers ............................................................................................................
18.14.1 SCI Base Addresses ........................................................................................
18.14.2 SCI_REGS Registers .......................................................................................
18.14.3 Register to Driverlib Function Mapping ...................................................................
2128
2130
2130
2130
2130
2131
2131
2132
2132
2132
2132
2133
2134
2134
2134
2134
2134
2135
2136
2136
2137
2138
2138
2138
2140
2140
2141
2141
2142
2162
Inter-Integrated Circuit Module (I2C) .................................................................................. 2164
19.1
Introduction ...............................................................................................................
19.1.1 Features ........................................................................................................
19.1.2 Features Not Supported ......................................................................................
19.1.3 Functional Overview ..........................................................................................
19.1.4 Clock Generation ..............................................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Contents
2165
2165
2166
2166
2167
11
www.ti.com
19.2
19.3
19.4
19.5
19.6
20
2168
2168
2169
2169
2169
2169
2170
2171
2173
2174
2174
2175
2176
2176
2178
2179
2180
2180
2181
2205
Multichannel Buffered Serial Port (McBSP) ........................................................................ 2207
20.1
20.2
20.3
20.4
20.5
20.6
12
19.1.5 I2C Clock Divider Registers (I2CCLKL and I2CCLKH) ..................................................
Configuring Device Pins ................................................................................................
I2C Module Operational Details .......................................................................................
19.3.1 Input and Output Voltage Levels ............................................................................
19.3.2 Data Validity ...................................................................................................
19.3.3 Operating Modes ..............................................................................................
19.3.4 I2C Module START and STOP Conditions ................................................................
19.3.5 Serial Data Formats...........................................................................................
19.3.6 NACK Bit Generation .........................................................................................
19.3.7 Clock Synchronization ........................................................................................
19.3.8 Arbitration ......................................................................................................
19.3.9 Digital Loopback Mode .......................................................................................
Interrupt Requests Generated by the I2C Module ..................................................................
19.4.1 Basic I2C Interrupt Requests ................................................................................
19.4.2 I2C FIFO Interrupts ...........................................................................................
Resetting or Disabling the I2C Module ...............................................................................
I2C Registers ............................................................................................................
19.6.1 I2C Base Addresses ..........................................................................................
19.6.2 I2C_REGS Registers .........................................................................................
19.6.3 Register to Driverlib Function Mapping.....................................................................
Overview..................................................................................................................
20.1.1 Features of the McBSPs .....................................................................................
20.1.2 McBSP Pins/Signals ..........................................................................................
Configuring Device Pins ................................................................................................
McBSP Operation .......................................................................................................
20.3.1 Data Transfer Process of McBSPs .........................................................................
20.3.2 Companding (Compressing and Expanding) Data........................................................
20.3.3 Clocking and Framing Data ..................................................................................
20.3.4 Frame Phases .................................................................................................
20.3.5 McBSP Reception .............................................................................................
20.3.6 McBSP Transmission .........................................................................................
20.3.7 Interrupts and DMA Events Generated by a McBSP .....................................................
McBSP Sample Rate Generator ......................................................................................
20.4.1 Block Diagram .................................................................................................
20.4.2 Frame Synchronization Generation in the Sample Rate Generator ....................................
20.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock .................................
20.4.4 Reset and Initialization Procedure for the Sample Rate Generator ....................................
McBSP Exception/Error Conditions ...................................................................................
20.5.1 Types of Errors ................................................................................................
20.5.2 Overrun in the Receiver ......................................................................................
20.5.3 Unexpected Receive Frame-Synchronization Pulse .....................................................
20.5.4 Overwrite in the Transmitter .................................................................................
20.5.5 Underflow in the Transmitter .................................................................................
20.5.6 Unexpected Transmit Frame-Synchronization Pulse .....................................................
Multichannel Selection Modes .........................................................................................
20.6.1 Channels, Blocks, and Partitions ............................................................................
20.6.2 Multichannel Selection ........................................................................................
20.6.3 Configuring a Frame for Multichannel Selection ..........................................................
20.6.4 Using Two Partitions ..........................................................................................
20.6.5 Using Eight Partitions .........................................................................................
20.6.6 Receive Multichannel Selection Mode......................................................................
20.6.7 Transmit Multichannel Selection Modes ...................................................................
Contents
2208
2208
2209
2210
2210
2211
2212
2213
2216
2218
2219
2220
2220
2221
2224
2224
2226
2227
2227
2227
2229
2231
2232
2233
2235
2235
2236
2236
2236
2238
2239
2239
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
20.7
20.8
20.9
20.6.8 Using Interrupts Between Block Transfers .................................................................
SPI Operation Using the Clock Stop Mode ..........................................................................
20.7.1 SPI Protocol ....................................................................................................
20.7.2 Clock Stop Mode ..............................................................................................
20.7.3 Enable and Configure the Clock Stop Mode ..............................................................
20.7.4 Clock Stop Mode Timing Diagrams .........................................................................
20.7.5 Procedure for Configuring a McBSP for SPI Operation ..................................................
20.7.6 McBSP as the SPI Master ...................................................................................
20.7.7 McBSP as an SPI Slave......................................................................................
Receiver Configuration .................................................................................................
20.8.1 Programming the McBSP Registers for the Desired Receiver Operation .............................
20.8.2 Resetting and Enabling the Receiver .......................................................................
20.8.3 Set the Receiver Pins to Operate as McBSP Pins .......................................................
20.8.4 Digital Loopback Mode .......................................................................................
20.8.5 Clock Stop Mode ..............................................................................................
20.8.6 Receive Multichannel Selection Mode......................................................................
20.8.7 Receive Frame Phases.......................................................................................
20.8.8 Receive Word Length(s) .....................................................................................
20.8.9 Receive Frame Length .......................................................................................
20.8.10 Receive Frame-Synchronization Ignore Function .......................................................
20.8.11 Receive Companding Mode ................................................................................
20.8.12 Receive Data Delay .........................................................................................
20.8.13 Receive Sign-Extension and Justification Mode .........................................................
20.8.14 Receive Interrupt Mode .....................................................................................
20.8.15 Receive Frame-Synchronization Mode ...................................................................
20.8.16 Receive Frame-Synchronization Polarity .................................................................
20.8.17 Receive Clock Mode ........................................................................................
20.8.18 Receive Clock Polarity ......................................................................................
20.8.19 SRG Clock Divide-Down Value ............................................................................
20.8.20 SRG Clock Synchronization Mode ........................................................................
20.8.21 SRG Clock Mode (Choose an Input Clock) ..............................................................
20.8.22 SRG Input Clock Polarity ...................................................................................
Transmitter Configuration ..............................................................................................
20.9.1 Programming the McBSP Registers for the Desired Transmitter Operation ..........................
20.9.2 Resetting and Enabling the Transmitter ....................................................................
20.9.3 Set the Transmitter Pins to Operate as McBSP Pins ....................................................
20.9.4 Digital Loopback Mode .......................................................................................
20.9.5 Clock Stop Mode ..............................................................................................
20.9.6 Transmit Multichannel Selection Mode .....................................................................
20.9.7 XCERs Used in the Transmit Multichannel Selection Mode.............................................
20.9.8 Transmit Frame Phases ......................................................................................
20.9.9 Transmit Word Length(s) .....................................................................................
20.9.10 Transmit Frame Length .....................................................................................
20.9.11 Enable/Disable the Transmit Frame-Synchronization Ignore Function ...............................
20.9.12 Transmit Companding Mode ...............................................................................
20.9.13 Transmit Data Delay ........................................................................................
20.9.14 Transmit DXENA Mode .....................................................................................
20.9.15 Transmit Interrupt Mode ....................................................................................
20.9.16 Transmit Frame-Synchronization Mode ..................................................................
20.9.17 Transmit Frame-Synchronization Polarity ................................................................
20.9.18 SRG Frame-Synchronization Period and Pulse Width .................................................
20.9.19 Transmit Clock Mode ........................................................................................
20.9.20 Transmit Clock Polarity .....................................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Contents
2241
2242
2242
2243
2243
2244
2246
2246
2248
2249
2249
2250
2250
2251
2251
2252
2252
2253
2253
2254
2255
2256
2258
2259
2259
2261
2263
2264
2266
2266
2267
2268
2268
2268
2269
2270
2270
2270
2271
2272
2275
2275
2276
2277
2278
2279
2281
2281
2282
2283
2284
2285
2285
13
www.ti.com
20.10 Emulation and Reset Considerations ................................................................................
20.10.1 McBSP Emulation Mode ....................................................................................
20.10.2 Resetting and Initializing McBSPs .........................................................................
20.11 Data Packing Examples ................................................................................................
20.11.1 Data Packing Using Frame Length and Word Length ..................................................
20.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function ...............
20.12 Interrupt Generation ....................................................................................................
20.12.1 McBSP Receive Interrupt Generation .....................................................................
20.12.2 McBSP Transmit Interrupt Generation ....................................................................
20.12.3 Error Flags ...................................................................................................
20.13 McBSP Modes...........................................................................................................
20.14 Special Case: External Device is the Transmit Frame Master ....................................................
20.15 McBSP Registers ......................................................................................................
20.15.1 McBSP Base Addresses ....................................................................................
20.15.2 Data Receive Registers (DRR[1,2]) .......................................................................
20.15.3 Data Transmit Registers (DXR[1,2]) ......................................................................
20.15.4 Serial Port Control Registers (SPCR[1,2]) ...............................................................
20.15.5 Receive Control Registers (RCR[1, 2]) ..................................................................
20.15.6 Transmit Control Registers (XCR1 and XCR2) ..........................................................
20.15.7 Sample Rate Generator Registers (SRGR1 and SRGR2) .............................................
20.15.8 Multichannel Control Registers (MCR[1,2]) ..............................................................
20.15.9 Pin Control Register (PCR) .................................................................................
20.15.10 Receive Channel Enable Registers (RCERA, RCERB, RCERC, RCERD, RCERE, RCERF,
RCERG, RCERH) ..............................................................................................
20.15.11 Transmit Channel Enable Registers (XCERA, XCERB, XCERC, XCERD, XCERE, XCERF,
XCERG, XCERH) ..............................................................................................
20.15.12 XCERs Used in a Transmit Multichannel Selection Mode ............................................
20.15.13 McBSP Interrupt Enable Register ........................................................................
20.16 Register to Driverlib Function Mapping ..............................................................................
21
2317
2319
2320
2321
2322
Controller Area Network (CAN) ......................................................................................... 2325
Introduction ...............................................................................................................
21.1.1 Features .......................................................................................................
21.1.2 Functional Description .......................................................................................
21.1.3 Block Diagram ................................................................................................
21.2 Configuring Device Pins ................................................................................................
21.3 Address/Data Bus Bridge ..............................................................................................
21.4 Operating Modes ........................................................................................................
21.4.1 Initialization ....................................................................................................
21.4.2 CAN Message Transfer (Normal Operation) ..............................................................
21.4.3 Test Modes ....................................................................................................
21.5 Multiple Clock Source ..................................................................................................
21.6 Interrupt Functionality ..................................................................................................
21.6.1 Message Object Interrupts ..................................................................................
21.6.2 Status Change Interrupts ....................................................................................
21.6.3 Error Interrupts ................................................................................................
21.6.4 PIE Nomenclature for DCAN Interrupts ....................................................................
21.6.5 Interrupt Topologies ..........................................................................................
21.7 Parity Check Mechanism ..............................................................................................
21.7.1 Behavior on Parity Error .....................................................................................
21.8 Debug Mode ............................................................................................................
21.9 Module Initialization ....................................................................................................
21.10 Configuration of Message Objects ...................................................................................
21.10.1 Configuration of a Transmit Object for Data Frames ...................................................
21.10.2 Configuration of a Transmit Object for Remote Frames ...............................................
21.1
14
2286
2287
2287
2289
2289
2291
2291
2292
2292
2293
2293
2294
2296
2296
2297
2297
2298
2303
2305
2308
2310
2315
Contents
2326
2326
2326
2327
2328
2328
2330
2330
2330
2331
2334
2335
2335
2335
2335
2335
2336
2337
2337
2337
2338
2338
2338
2339
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
21.11
21.12
21.13
21.14
21.15
22
2339
2339
2340
2340
2340
2341
2341
2341
2342
2342
2342
2342
2343
2343
2343
2343
2345
2345
2350
2352
2353
2354
2354
2355
2357
2358
2359
2359
2360
2421
Universal Serial Bus (USB) Controller................................................................................ 2423
22.1
22.2
22.3
22.4
22.5
23
21.10.3 Configuration of a Single Receive Object for Data Frames ...........................................
21.10.4 Configuration of a Single Receive Object for Remote Frames .......................................
21.10.5 Configuration of a FIFO Buffer ............................................................................
Message Handling .....................................................................................................
21.11.1 Message Handler Overview ...............................................................................
21.11.2 Receive/Transmit Priority ..................................................................................
21.11.3 Transmission of Messages in Event Driven CAN Communication ...................................
21.11.4 Updating a Transmit Object ...............................................................................
21.11.5 Changing a Transmit Object ...............................................................................
21.11.6 Acceptance Filtering of Received Messages ............................................................
21.11.7 Reception of Data Frames .................................................................................
21.11.8 Reception of Remote Frames .............................................................................
21.11.9 Reading Received Messages .............................................................................
21.11.10 Requesting New Data for a Receive Object ...........................................................
21.11.11 Storing Received Messages in FIFO Buffers ..........................................................
21.11.12 Reading from a FIFO Buffer .............................................................................
CAN Bit Timing .........................................................................................................
21.12.1 Bit Time and Bit Rate .......................................................................................
21.12.2 Configuration of the CAN Bit Timing .....................................................................
Message Interface Register Sets ....................................................................................
21.13.1 Message Interface Register Sets 1 and 2 ...............................................................
21.13.2 IF3 Register Set .............................................................................................
Message RAM ..........................................................................................................
21.14.1 Structure of Message Objects .............................................................................
21.14.2 Addressing Message Objects in RAM ...................................................................
21.14.3 Message RAM Representation in Debug Mode ........................................................
CAN Registers...........................................................................................................
21.15.1 CAN Base Addresses .......................................................................................
21.15.2 CAN_REGS Registers ......................................................................................
21.15.3 Register to Driverlib Function Mapping ...................................................................
Introduction ...............................................................................................................
Features ..................................................................................................................
22.2.1 Block Diagram .................................................................................................
22.2.2 Signal Description .............................................................................................
22.2.3 VBus Recommendations .....................................................................................
Functional Description ..................................................................................................
22.3.1 Operation as a Device ........................................................................................
22.3.2 Operation as a Host...........................................................................................
22.3.3 DMA Operation ................................................................................................
22.3.4 Address/Data Bus Bridge ....................................................................................
Initialization and Configuration.........................................................................................
22.4.1 Pin Configuration ..............................................................................................
22.4.2 Endpoint Configuration .......................................................................................
USB Registers ...........................................................................................................
22.5.1 USB Base Address ...........................................................................................
22.5.2 USB Register Map ............................................................................................
22.5.3 USB Register Descriptions ...................................................................................
2424
2424
2424
2425
2425
2426
2426
2430
2433
2433
2435
2435
2435
2437
2437
2438
2448
External Memory Interface (EMIF) ..................................................................................... 2517
23.1
23.2
Introduction ...............................................................................................................
23.1.1 Purpose of the Peripheral ....................................................................................
Features ..................................................................................................................
23.2.1 Asynchronous Memory Support .............................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Contents
2518
2518
2518
2518
15
www.ti.com
23.3
23.4
23.5
23.6
23.7
24
2519
2519
2520
2520
2520
2520
2520
2522
2522
2534
2546
2546
2546
2547
2547
2547
2548
2549
2550
2550
2551
2551
2551
2559
2559
2560
2580
2584
Configurable Logic Block (CLB)........................................................................................ 2585
24.1
24.2
24.3
24.4
24.5
24.6
16
23.2.2 Synchronous DRAM Memory Support .....................................................................
Functional Block Diagram ..............................................................................................
Configuring Device Pins ................................................................................................
EMIF Module Architecture .............................................................................................
23.5.1 EMIF Clock Control ...........................................................................................
23.5.2 EMIF Requests ................................................................................................
23.5.3 EMIF Signal Descriptions ....................................................................................
23.5.4 EMIF Signal Multiplexing Control ...........................................................................
23.5.5 SDRAM Controller and Interface ............................................................................
23.5.6 Asynchronous Controller and Interface ....................................................................
23.5.7 Data Bus Parking..............................................................................................
23.5.8 Reset and Initialization Considerations .....................................................................
23.5.9 Interrupt Support ..............................................................................................
23.5.10 DMA Event Support .........................................................................................
23.5.11 EMIF Signal Multiplexing ...................................................................................
23.5.12 Memory Map .................................................................................................
23.5.13 Priority and Arbitration ......................................................................................
23.5.14 System Considerations .....................................................................................
23.5.15 Power Management .........................................................................................
23.5.16 Emulation Considerations ..................................................................................
Example Configuration .................................................................................................
23.6.1 Hardware Interface ............................................................................................
23.6.2 Software Configuration .......................................................................................
EMIF Registers ..........................................................................................................
23.7.1 EMIF Base Addresses ........................................................................................
23.7.2 EMIF_REGS Registers .......................................................................................
23.7.3 EMIF1_CONFIG_REGS Registers .........................................................................
23.7.4 Register to Driverlib Function Mapping.....................................................................
Introduction ...............................................................................................................
Features ..................................................................................................................
CLB Input/Output Connection .........................................................................................
24.3.1 Overview .......................................................................................................
24.3.2 CLB Input Selection ...........................................................................................
24.3.3 CLB Output Selection .........................................................................................
24.3.4 Peripheral Signal Multiplexer ...............................................................................
The CLB Tile .............................................................................................................
24.4.1 Static Switch Block ...........................................................................................
24.4.2 Counter Block ..................................................................................................
24.4.3 FSM Block ......................................................................................................
24.4.4 LUT4 Block .....................................................................................................
24.4.5 Output LUT Block .............................................................................................
24.4.6 High Level Controller (HLC) .................................................................................
CPU Interface ............................................................................................................
24.5.1 Register Description ..........................................................................................
24.5.2 Non-Memory Mapped Registers ............................................................................
CLB Registers ...........................................................................................................
24.6.1 CLB Base Addresses .........................................................................................
24.6.2 CLB_LOGIC_CONFIG_REGS Registers ..................................................................
24.6.3 CLB_LOGIC_CONTROL_REGS Registers................................................................
24.6.4 CLB_DATA_EXCHANGE_REGS Registers ...............................................................
24.6.5 CLB_DATA_EXCHANGE_REGS Registers ...............................................................
24.6.6 Register to Driverlib Function Mapping.....................................................................
Contents
2586
2586
2587
2587
2587
2591
2592
2594
2595
2597
2599
2600
2600
2601
2604
2604
2605
2606
2606
2607
2640
2667
2670
2673
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
Revision History ...................................................................................................................... 2676
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Contents
17
www.ti.com
List of Figures
Device Interrupt Architecture
3-2.
Interrupt Propagation Path ................................................................................................ 90
3-3.
Missing Clock Detection Logic .......................................................................................... 103
3-4.
ERRORSTS Pin Diagram
3-5.
Clocking System .......................................................................................................... 105
3-6.
Single-ended 3.3V External Clock ...................................................................................... 106
3-7.
External Crystal ........................................................................................................... 106
3-8.
External Resonator ....................................................................................................... 107
3-9.
AUXCLKIN ................................................................................................................. 107
3-10.
CPU-Timers
3-11.
3-12.
3-13.
3-14.
3-15.
3-16.
3-17.
3-18.
3-19.
3-20.
3-21.
3-22.
3-23.
3-24.
3-25.
3-26.
3-27.
3-28.
3-29.
3-30.
3-31.
3-32.
3-33.
3-34.
3-35.
3-36.
3-37.
3-38.
3-39.
3-40.
3-41.
3-42.
3-43.
3-44.
3-45.
3-46.
3-47.
18
.............................................................................................
3-1.
...............................................................................................
...............................................................................................................
CPU-Timer Interrupts Signals and Output Signal ....................................................................
CPU Watchdog Timer Module .........................................................................................
Memory Architecture .....................................................................................................
Arbitration Scheme on Global Shared Memories .....................................................................
Arbitration Scheme on Local Shared Memories ......................................................................
FMC Interface with Core, Bank and Pump ............................................................................
Flash Prefetch Mode .....................................................................................................
ECC Logic Inputs and Outputs..........................................................................................
Storage of Zone-Select Bits in OTP ...................................................................................
Location of Zone-Select Block Based on Link-Pointer ...............................................................
CSM Password Match Flow (PMF) .....................................................................................
ECSL Password Match Flow (PMF) ....................................................................................
TIM Register ...............................................................................................................
PRD Register ..............................................................................................................
TCR Register ..............................................................................................................
TPR Register ..............................................................................................................
TPRH Register ............................................................................................................
PIECTRL Register ........................................................................................................
PIEACK Register..........................................................................................................
PIEIER1 Register .........................................................................................................
PIEIFR1 Register .........................................................................................................
PIEIER2 Register .........................................................................................................
PIEIFR2 Register .........................................................................................................
PIEIER3 Register .........................................................................................................
PIEIFR3 Register .........................................................................................................
PIEIER4 Register .........................................................................................................
PIEIFR4 Register .........................................................................................................
PIEIER5 Register .........................................................................................................
PIEIFR5 Register .........................................................................................................
PIEIER6 Register .........................................................................................................
PIEIFR6 Register .........................................................................................................
PIEIER7 Register .........................................................................................................
PIEIFR7 Register .........................................................................................................
PIEIER8 Register .........................................................................................................
PIEIFR8 Register .........................................................................................................
PIEIER9 Register .........................................................................................................
PIEIFR9 Register .........................................................................................................
List of Figures
89
104
114
114
116
122
124
124
130
133
136
143
144
148
150
155
156
157
159
160
163
164
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
3-48.
PIEIER10 Register........................................................................................................ 201
3-49.
PIEIFR10 Register ........................................................................................................ 203
3-50.
PIEIER11 Register........................................................................................................ 205
3-51.
PIEIFR11 Register ........................................................................................................ 207
3-52.
PIEIER12 Register........................................................................................................ 209
3-53.
PIEIFR12 Register ........................................................................................................ 211
3-54.
SCSR Register ............................................................................................................ 214
3-55.
WDCNTR Register
3-56.
WDKEY Register.......................................................................................................... 216
3-57.
WDCR Register ........................................................................................................... 217
3-58.
WDWCR Register
3-59.
3-60.
3-61.
3-62.
3-63.
3-64.
3-65.
3-66.
3-67.
3-68.
3-69.
3-70.
3-71.
3-72.
3-73.
3-74.
3-75.
3-76.
3-77.
3-78.
3-79.
3-80.
3-81.
3-82.
3-83.
3-84.
3-85.
3-86.
3-87.
3-88.
3-89.
3-90.
3-91.
3-92.
3-93.
3-94.
3-95.
3-96.
.......................................................................................................
........................................................................................................
NMICFG Register .........................................................................................................
NMIFLG Register .........................................................................................................
NMIFLGCLR Register ....................................................................................................
NMIFLGFRC Register ....................................................................................................
NMIWDCNT Register ....................................................................................................
NMIWDPRD Register ....................................................................................................
NMISHDFLG Register....................................................................................................
XINT1CR Register ........................................................................................................
XINT2CR Register ........................................................................................................
XINT3CR Register ........................................................................................................
XINT4CR Register ........................................................................................................
XINT5CR Register ........................................................................................................
XINT1CTR Register ......................................................................................................
XINT2CTR Register ......................................................................................................
XINT3CTR Register ......................................................................................................
CLA1TASKSRCSELLOCK Register ...................................................................................
DMACHSRCSELLOCK Register .......................................................................................
CLA1TASKSRCSEL1 Register .........................................................................................
CLA1TASKSRCSEL2 Register .........................................................................................
DMACHSRCSEL1 Register .............................................................................................
DMACHSRCSEL2 Register .............................................................................................
PARTIDL Register ........................................................................................................
PARTIDH Register........................................................................................................
REVID Register ...........................................................................................................
DC0 Register ..............................................................................................................
DC1 Register ..............................................................................................................
DC2 Register ..............................................................................................................
DC3 Register ..............................................................................................................
DC4 Register ..............................................................................................................
DC5 Register ..............................................................................................................
DC6 Register ..............................................................................................................
DC7 Register ..............................................................................................................
DC8 Register ..............................................................................................................
DC9 Register ..............................................................................................................
DC10 Register.............................................................................................................
DC11 Register.............................................................................................................
DC12 Register.............................................................................................................
DC13 Register.............................................................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
215
218
220
221
223
225
226
227
228
231
232
233
234
235
236
237
238
240
241
242
243
244
245
248
250
251
252
253
254
255
257
258
259
260
261
262
263
264
265
266
19
www.ti.com
3-97.
DC14 Register............................................................................................................. 267
3-98.
DC15 Register............................................................................................................. 268
3-99.
DC17 Register............................................................................................................. 270
3-100. DC18 Register............................................................................................................. 271
3-101. DC20 Register............................................................................................................. 272
3-102. PERCNF1 Register ....................................................................................................... 274
3-103. FUSEERR Register....................................................................................................... 275
276
3-105. SOFTPRES1 Register
277
3-106.
278
3-107.
3-108.
3-109.
3-110.
3-111.
3-112.
3-113.
3-114.
3-115.
3-116.
3-117.
3-118.
3-119.
3-120.
3-121.
3-122.
3-123.
3-124.
3-125.
3-126.
3-127.
3-128.
3-129.
3-130.
3-131.
3-132.
3-133.
3-134.
3-135.
3-136.
3-137.
3-138.
3-139.
3-140.
3-141.
3-142.
3-143.
3-144.
3-145.
20
...................................................................................................
...................................................................................................
SOFTPRES2 Register ...................................................................................................
SOFTPRES3 Register ...................................................................................................
SOFTPRES4 Register ...................................................................................................
SOFTPRES6 Register ...................................................................................................
SOFTPRES7 Register ...................................................................................................
SOFTPRES8 Register ...................................................................................................
SOFTPRES9 Register ...................................................................................................
SOFTPRES11 Register ..................................................................................................
SOFTPRES13 Register ..................................................................................................
SOFTPRES14 Register ..................................................................................................
SOFTPRES16 Register ..................................................................................................
SYSDBGCTL Register ...................................................................................................
CLKCFGLOCK1 Register ................................................................................................
CLKSRCCTL1 Register ..................................................................................................
CLKSRCCTL2 Register ..................................................................................................
CLKSRCCTL3 Register ..................................................................................................
SYSPLLCTL1 Register ...................................................................................................
SYSPLLMULT Register ..................................................................................................
SYSPLLSTS Register ....................................................................................................
AUXPLLCTL1 Register ..................................................................................................
AUXPLLMULT Register ..................................................................................................
AUXPLLSTS Register ....................................................................................................
SYSCLKDIVSEL Register ...............................................................................................
AUXCLKDIVSEL Register ...............................................................................................
PERCLKDIVSEL Register ...............................................................................................
XCLKOUTDIVSEL Register .............................................................................................
LOSPCP Register ........................................................................................................
MCDCR Register .........................................................................................................
X1CNT Register...........................................................................................................
CPUSYSLOCK1 Register ...............................................................................................
HIBBOOTMODE Register ...............................................................................................
IORESTOREADDR Register ............................................................................................
PIEVERRADDR Register ................................................................................................
PCLKCR0 Register .......................................................................................................
PCLKCR1 Register .......................................................................................................
PCLKCR2 Register .......................................................................................................
PCLKCR3 Register .......................................................................................................
PCLKCR4 Register .......................................................................................................
PCLKCR6 Register .......................................................................................................
PCLKCR7 Register .......................................................................................................
3-104. SOFTPRES0 Register
List of Figures
280
281
282
283
284
285
286
287
288
289
290
293
295
297
299
300
301
302
303
304
305
306
307
308
309
310
311
312
315
318
319
320
321
323
324
326
328
329
330
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
3-146. PCLKCR8 Register ....................................................................................................... 331
3-147. PCLKCR9 Register ....................................................................................................... 332
.....................................................................................................
.....................................................................................................
PCLKCR12 Register .....................................................................................................
PCLKCR13 Register .....................................................................................................
PCLKCR14 Register .....................................................................................................
PCLKCR16 Register .....................................................................................................
SECMSEL Register.......................................................................................................
LPMCR Register ..........................................................................................................
GPIOLPMSEL0 Register.................................................................................................
GPIOLPMSEL1 Register.................................................................................................
TMR2CLKCTL Register ..................................................................................................
RESC Register ............................................................................................................
ROMPREFETCH Register...............................................................................................
FLSEM Register ..........................................................................................................
SECTSTAT Register .....................................................................................................
RAMSTAT Register.......................................................................................................
Z1OTP_LINKPOINTER1 Register ......................................................................................
Z1OTP_LINKPOINTER2 Register ......................................................................................
Z1OTP_LINKPOINTER3 Register ......................................................................................
Z1OTP_PSWDLOCK Register ..........................................................................................
Z1OTP_CRCLOCK Register ............................................................................................
Z1OTP_BOOTCTRL Register...........................................................................................
Z1_LINKPOINTER Register .............................................................................................
Z1_OTPSECLOCK Register ............................................................................................
Z1_BOOTCTRL Register ................................................................................................
Z1_LINKPOINTERERR Register .......................................................................................
Z1_CSMKEY0 Register ..................................................................................................
Z1_CSMKEY1 Register ..................................................................................................
Z1_CSMKEY2 Register ..................................................................................................
Z1_CSMKEY3 Register ..................................................................................................
Z1_CR Register ...........................................................................................................
Z1_GRABSECTR Register ..............................................................................................
Z1_GRABRAMR Register ...............................................................................................
Z1_EXEONLYSECTR Register .........................................................................................
Z1_EXEONLYRAMR Register ..........................................................................................
Z2OTP_LINKPOINTER1 Register ......................................................................................
Z2OTP_LINKPOINTER2 Register ......................................................................................
Z2OTP_LINKPOINTER3 Register ......................................................................................
Z2OTP_PSWDLOCK Register ..........................................................................................
Z2OTP_CRCLOCK Register ............................................................................................
Z2OTP_BOOTCTRL Register...........................................................................................
Z2_LINKPOINTER Register .............................................................................................
Z2_OTPSECLOCK Register ............................................................................................
Z2_BOOTCTRL Register ................................................................................................
Z2_LINKPOINTERERR Register .......................................................................................
Z2_CSMKEY0 Register ..................................................................................................
Z2_CSMKEY1 Register ..................................................................................................
3-148. PCLKCR10 Register
333
3-149. PCLKCR11 Register
334
3-150.
335
3-151.
3-152.
3-153.
3-154.
3-155.
3-156.
3-157.
3-158.
3-159.
3-160.
3-161.
3-162.
3-163.
3-164.
3-165.
3-166.
3-167.
3-168.
3-169.
3-170.
3-171.
3-172.
3-173.
3-174.
3-175.
3-176.
3-177.
3-178.
3-179.
3-180.
3-181.
3-182.
3-183.
3-184.
3-185.
3-186.
3-187.
3-188.
3-189.
3-190.
3-191.
3-192.
3-193.
3-194.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
336
337
339
340
341
343
346
349
351
354
356
357
360
363
364
365
366
367
368
370
371
372
373
374
375
376
377
378
379
382
384
387
390
391
392
393
394
395
397
398
399
400
401
402
21
www.ti.com
3-195. Z2_CSMKEY2 Register .................................................................................................. 403
3-196. Z2_CSMKEY3 Register .................................................................................................. 404
3-197. Z2_CR Register ........................................................................................................... 405
3-198. Z2_GRABSECTR Register .............................................................................................. 406
3-199. Z2_GRABRAMR Register ............................................................................................... 409
3-200. Z2_EXEONLYSECTR Register ......................................................................................... 411
3-201. Z2_EXEONLYRAMR Register .......................................................................................... 414
3-202. DxLOCK Register ......................................................................................................... 418
3-203. DxCOMMIT Register ..................................................................................................... 419
3-204. DxACCPROT0 Register
.................................................................................................
420
3-205. DxTEST Register ......................................................................................................... 421
3-206. DxINIT Register ........................................................................................................... 422
3-207. DxINITDONE Register ................................................................................................... 423
424
3-209.
426
3-210.
3-211.
3-212.
3-213.
3-214.
3-215.
3-216.
3-217.
3-218.
3-219.
3-220.
3-221.
3-222.
3-223.
3-224.
3-225.
3-226.
3-227.
3-228.
3-229.
3-230.
3-231.
3-232.
3-233.
3-234.
3-235.
3-236.
3-237.
3-238.
3-239.
3-240.
3-241.
3-242.
3-243.
22
.......................................................................................................
LSxCOMMIT Register ....................................................................................................
LSxMSEL Register .......................................................................................................
LSxCLAPGM Register ...................................................................................................
LSxACCPROT0 Register ................................................................................................
LSxACCPROT1 Register ................................................................................................
LSxTEST Register ........................................................................................................
LSxINIT Register ..........................................................................................................
LSxINITDONE Register ..................................................................................................
GSxLOCK Register .......................................................................................................
GSxCOMMIT Register ...................................................................................................
GSxACCPROT0 Register ...............................................................................................
GSxACCPROT1 Register ...............................................................................................
GSxACCPROT2 Register ...............................................................................................
GSxACCPROT3 Register ...............................................................................................
GSxTEST Register .......................................................................................................
GSxINIT Register .........................................................................................................
GSxINITDONE Register .................................................................................................
MSGxTEST Register .....................................................................................................
MSGxINIT Register .......................................................................................................
MSGxINITDONE Register ...............................................................................................
NMAVFLG Register ......................................................................................................
NMAVSET Register ......................................................................................................
NMAVCLR Register ......................................................................................................
NMAVINTEN Register....................................................................................................
NMCPURDAVADDR Register ..........................................................................................
NMCPUWRAVADDR Register ..........................................................................................
NMCPUFAVADDR Register .............................................................................................
NMDMAWRAVADDR Register .........................................................................................
NMCLA1RDAVADDR Register .........................................................................................
NMCLA1WRAVADDR Register .........................................................................................
NMCLA1FAVADDR Register............................................................................................
MAVFLG Register ........................................................................................................
MAVSET Register ........................................................................................................
MAVCLR Register ........................................................................................................
MAVINTEN Register .....................................................................................................
3-208. LSxLOCK Register
List of Figures
428
430
431
433
434
436
437
438
441
444
446
448
450
452
455
457
459
460
461
464
466
468
470
471
472
473
474
475
476
477
478
479
480
481
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
3-244. MCPUFAVADDR Register............................................................................................... 482
3-245. MCPUWRAVADDR Register ............................................................................................ 483
3-246. MDMAWRAVADDR Register
...........................................................................................
484
3-247. UCERRFLG Register..................................................................................................... 486
3-248. UCERRSET Register..................................................................................................... 487
....................................................................................................
UCCPUREADDR Register ..............................................................................................
UCDMAREADDR Register ..............................................................................................
UCCLA1READDR Register .............................................................................................
CERRFLG Register.......................................................................................................
CERRSET Register.......................................................................................................
CERRCLR Register ......................................................................................................
CCPUREADDR Register ................................................................................................
CERRCNT Register ......................................................................................................
CERRTHRES Register ...................................................................................................
CEINTFLG Register ......................................................................................................
CEINTCLR Register ......................................................................................................
CEINTSET Register ......................................................................................................
CEINTEN Register........................................................................................................
ROMWAITSTATE Register ..............................................................................................
FRDCNTL Register .......................................................................................................
FBAC Register ............................................................................................................
FBFALLBACK Register ..................................................................................................
FBPRDY Register ........................................................................................................
FPAC1 Register ...........................................................................................................
FMSTAT Register .........................................................................................................
FRD_INTF_CTRL Register ..............................................................................................
ECC_ENABLE Register..................................................................................................
SINGLE_ERR_ADDR_LOW Register..................................................................................
SINGLE_ERR_ADDR_HIGH Register .................................................................................
UNC_ERR_ADDR_LOW Register......................................................................................
UNC_ERR_ADDR_HIGH Register .....................................................................................
ERR_STATUS Register..................................................................................................
ERR_POS Register.......................................................................................................
ERR_STATUS_CLR Register ...........................................................................................
ERR_CNT Register .......................................................................................................
ERR_THRESHOLD Register............................................................................................
ERR_INTFLG Register ...................................................................................................
ERR_INTCLR Register ..................................................................................................
FDATAH_TEST Register ................................................................................................
FDATAL_TEST Register .................................................................................................
FADDR_TEST Register ..................................................................................................
FECC_TEST Register ....................................................................................................
FECC_CTRL Register....................................................................................................
FOUTH_TEST Register ..................................................................................................
FOUTL_TEST Register ..................................................................................................
FECC_STATUS Register ................................................................................................
UID_PSRAND0 Register.................................................................................................
UID_PSRAND1 Register.................................................................................................
3-249. UCERRCLR Register
3-250.
3-251.
3-252.
3-253.
3-254.
3-255.
3-256.
3-257.
3-258.
3-259.
3-260.
3-261.
3-262.
3-263.
3-264.
3-265.
3-266.
3-267.
3-268.
3-269.
3-270.
3-271.
3-272.
3-273.
3-274.
3-275.
3-276.
3-277.
3-278.
3-279.
3-280.
3-281.
3-282.
3-283.
3-284.
3-285.
3-286.
3-287.
3-288.
3-289.
3-290.
3-291.
3-292.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
488
489
490
491
492
493
494
495
496
497
498
499
500
501
503
505
506
507
508
509
510
512
515
516
517
518
519
520
522
523
524
525
526
527
528
529
530
531
532
533
534
535
537
538
23
www.ti.com
3-293. UID_PSRAND2 Register................................................................................................. 539
3-294. UID_PSRAND3 Register................................................................................................. 540
3-295. UID_PSRAND4 Register................................................................................................. 541
3-296. UID_PSRAND5 Register................................................................................................. 542
3-297. UID_UNIQUE Register ................................................................................................... 543
3-298. UID_CHECKSUM Register .............................................................................................. 544
Z1 and Z2 BOOTCTRL Selection
4-2.
CPU1 Device Boot Flow ................................................................................................. 563
4-3.
CPU1 Emulation Boot Flow
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
4-11.
4-12.
4-13.
4-14.
4-15.
4-16.
4-17.
4-18.
4-19.
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
5-19.
5-20.
5-21.
5-22.
5-23.
5-24.
24
......................................................................................
4-1.
.............................................................................................
CPU1 Standalone and Hibernate Boot Flow ..........................................................................
Overview of SCI Bootloader Operation ................................................................................
Overview of SCI Boot Function .........................................................................................
SPI Loader .................................................................................................................
Data Transfer From EEPROM Flow ....................................................................................
EEPROM Device at Address 0x50 .....................................................................................
Overview of I2C Boot Function .........................................................................................
Random Read .............................................................................................................
Sequential Read ..........................................................................................................
Overview of Parallel GPIO Bootloader Operation ....................................................................
Parallel GPIO Bootloader Handshake Protocol .......................................................................
Parallel GPIO Mode Overview ..........................................................................................
Parallel GPIO Mode - Host Transfer Flow .............................................................................
8-Bit Parallel GetWord Function ........................................................................................
Overview of CAN-A Bootloader Operation ............................................................................
USB Boot Flow ............................................................................................................
DMA Block Diagram ......................................................................................................
Common Peripheral Architecture .......................................................................................
DMA Trigger Architecture ................................................................................................
Peripheral Interrupt Trigger Input Diagram ...........................................................................
DMA State Diagram ......................................................................................................
3-Stage Pipeline DMA Transfer .........................................................................................
3-stage Pipeline With One Read Stall .................................................................................
Overrun Detection Logic .................................................................................................
DMACTRL Register ......................................................................................................
DEBUGCTRL Register ...................................................................................................
PRIORITYCTRL1 Register ..............................................................................................
PRIORITYSTAT Register ................................................................................................
MODE Register ...........................................................................................................
CONTROL Register ......................................................................................................
BURST_SIZE Register ...................................................................................................
BURST_COUNT Register ...............................................................................................
SRC_BURST_STEP Register...........................................................................................
DST_BURST_STEP Register ...........................................................................................
TRANSFER_SIZE Register .............................................................................................
TRANSFER_COUNT Register ..........................................................................................
SRC_TRANSFER_STEP Register .....................................................................................
DST_TRANSFER_STEP Register .....................................................................................
SRC_WRAP_SIZE Register .............................................................................................
SRC_WRAP_COUNT Register .........................................................................................
List of Figures
561
564
565
570
571
571
573
573
574
575
576
576
577
577
578
579
580
581
591
592
593
594
601
603
603
605
608
609
610
611
614
616
619
620
621
622
623
624
625
626
627
628
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
5-25.
SRC_WRAP_STEP Register............................................................................................ 629
5-26.
DST_WRAP_SIZE Register ............................................................................................. 630
5-27.
DST_WRAP_COUNT Register
5-28.
DST_WRAP_STEP Register ............................................................................................ 632
5-29.
SRC_BEG_ADDR_SHADOW Register ................................................................................ 633
5-30.
SRC_ADDR_SHADOW Register ....................................................................................... 634
5-31.
SRC_BEG_ADDR_ACTIVE Register .................................................................................. 635
5-32.
SRC_ADDR_ACTIVE Register
5-33.
DST_BEG_ADDR_SHADOW Register ................................................................................ 637
5-34.
DST_ADDR_SHADOW Register ....................................................................................... 638
5-35.
DST_BEG_ADDR_ACTIVE Register
5-36.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
6-8.
6-9.
6-10.
6-11.
6-12.
6-13.
6-14.
6-15.
6-16.
6-17.
6-18.
6-19.
6-20.
6-21.
6-22.
6-23.
6-24.
6-25.
6-26.
6-27.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
.........................................................................................
.........................................................................................
..................................................................................
DST_ADDR_ACTIVE Register ..........................................................................................
CLA (Type 1) Block Diagram ............................................................................................
MVECT1 Register ........................................................................................................
MVECT2 Register ........................................................................................................
MVECT3 Register ........................................................................................................
MVECT4 Register ........................................................................................................
MVECT5 Register ........................................................................................................
MVECT6 Register ........................................................................................................
MVECT7 Register ........................................................................................................
MVECT8 Register ........................................................................................................
MCTL Register ............................................................................................................
MIFR Register .............................................................................................................
MIOVF Register ...........................................................................................................
MIFRC Register ...........................................................................................................
MICLR Register ...........................................................................................................
MICLROVF Register .....................................................................................................
MIER Register .............................................................................................................
MIRUN Register...........................................................................................................
_MPC Register ............................................................................................................
_MAR0 Register ..........................................................................................................
_MAR1 Register ..........................................................................................................
_MSTF Register...........................................................................................................
_MR0 Register ............................................................................................................
_MR1 Register ............................................................................................................
_MR2 Register ............................................................................................................
_MR3 Register ............................................................................................................
SOFTINTEN Register ....................................................................................................
SOFTINTFRC Register ..................................................................................................
GPIO Logic for a Single Pin .............................................................................................
Input Qualification Using a Sampling Window ........................................................................
Input Qualifier Clock Cycles .............................................................................................
GPACTRL Register .......................................................................................................
GPAQSEL1 Register .....................................................................................................
GPAQSEL2 Register .....................................................................................................
GPAMUX1 Register ......................................................................................................
GPAMUX2 Register ......................................................................................................
GPADIR Register .........................................................................................................
GPAPUD Register ........................................................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
631
636
639
640
645
779
780
781
782
783
784
785
786
787
788
793
796
798
800
802
805
808
809
810
811
814
815
816
817
819
821
823
826
829
841
842
844
846
848
850
852
25
www.ti.com
7-11.
GPAINV Register ......................................................................................................... 854
7-12.
GPAODR Register ........................................................................................................ 856
7-13.
GPAGMUX1 Register .................................................................................................... 858
7-14.
GPAGMUX2 Register .................................................................................................... 859
7-15.
GPACSEL1 Register ..................................................................................................... 860
7-16.
GPACSEL2 Register ..................................................................................................... 861
7-17.
GPACSEL3 Register ..................................................................................................... 862
7-18.
GPACSEL4 Register ..................................................................................................... 863
7-19.
GPALOCK Register
7-20.
7-21.
7-22.
7-23.
7-24.
7-25.
7-26.
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
7-39.
7-40.
7-41.
7-42.
7-43.
7-44.
7-45.
7-46.
7-47.
7-48.
7-49.
7-50.
7-51.
7-52.
7-53.
7-54.
7-55.
7-56.
7-57.
7-58.
7-59.
26
......................................................................................................
GPACR Register ..........................................................................................................
GPBCTRL Register .......................................................................................................
GPBQSEL1 Register .....................................................................................................
GPBQSEL2 Register .....................................................................................................
GPBMUX1 Register ......................................................................................................
GPBMUX2 Register ......................................................................................................
GPBDIR Register .........................................................................................................
GPBPUD Register ........................................................................................................
GPBINV Register .........................................................................................................
GPBODR Register ........................................................................................................
GPBAMSEL Register.....................................................................................................
GPBGMUX1 Register ....................................................................................................
GPBGMUX2 Register ....................................................................................................
GPBCSEL1 Register .....................................................................................................
GPBCSEL2 Register .....................................................................................................
GPBCSEL3 Register .....................................................................................................
GPBCSEL4 Register .....................................................................................................
GPBLOCK Register ......................................................................................................
GPBCR Register ..........................................................................................................
GPCCTRL Register.......................................................................................................
GPCQSEL1 Register .....................................................................................................
GPCQSEL2 Register .....................................................................................................
GPCMUX1 Register ......................................................................................................
GPCMUX2 Register ......................................................................................................
GPCDIR Register .........................................................................................................
GPCPUD Register ........................................................................................................
GPCINV Register .........................................................................................................
GPCODR Register........................................................................................................
GPCGMUX1 Register ....................................................................................................
GPCGMUX2 Register ....................................................................................................
GPCCSEL1 Register .....................................................................................................
GPCCSEL2 Register .....................................................................................................
GPCCSEL3 Register .....................................................................................................
GPCCSEL4 Register .....................................................................................................
GPCLOCK Register ......................................................................................................
GPCCR Register ..........................................................................................................
GPDCTRL Register.......................................................................................................
GPDQSEL1 Register .....................................................................................................
GPDQSEL2 Register .....................................................................................................
GPDMUX1 Register ......................................................................................................
List of Figures
864
866
868
869
871
873
875
877
879
881
883
885
887
888
889
890
891
892
893
895
897
898
900
902
904
906
908
910
912
914
915
916
917
918
919
920
922
924
925
927
929
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
7-60.
GPDMUX2 Register ...................................................................................................... 931
7-61.
GPDDIR Register ......................................................................................................... 933
7-62.
GPDPUD Register ........................................................................................................ 935
7-63.
GPDINV Register ......................................................................................................... 937
7-64.
GPDODR Register........................................................................................................ 939
7-65.
GPDGMUX1 Register .................................................................................................... 941
7-66.
GPDGMUX2 Register .................................................................................................... 943
7-67.
GPDCSEL1 Register ..................................................................................................... 945
7-68.
GPDCSEL2 Register ..................................................................................................... 946
7-69.
GPDCSEL3 Register ..................................................................................................... 947
7-70.
GPDCSEL4 Register ..................................................................................................... 948
7-71.
GPDLOCK Register ...................................................................................................... 949
7-72.
GPDCR Register .......................................................................................................... 951
7-73.
GPECTRL Register ....................................................................................................... 953
7-74.
GPEQSEL1 Register ..................................................................................................... 954
7-75.
GPEQSEL2 Register ..................................................................................................... 956
7-76.
GPEMUX1 Register ...................................................................................................... 958
7-77.
GPEMUX2 Register ...................................................................................................... 960
7-78.
GPEDIR Register ......................................................................................................... 962
7-79.
GPEPUD Register ........................................................................................................ 964
7-80.
GPEINV Register ......................................................................................................... 966
7-81.
GPEODR Register ........................................................................................................ 968
7-82.
GPEGMUX1 Register .................................................................................................... 970
7-83.
GPEGMUX2 Register .................................................................................................... 972
7-84.
GPECSEL1 Register ..................................................................................................... 974
7-85.
GPECSEL2 Register ..................................................................................................... 975
7-86.
GPECSEL3 Register ..................................................................................................... 976
7-87.
GPECSEL4 Register ..................................................................................................... 977
7-88.
GPELOCK Register
7-89.
7-90.
7-91.
7-92.
7-93.
7-94.
7-95.
7-96.
7-97.
7-98.
7-99.
7-100.
7-101.
7-102.
7-103.
7-104.
7-105.
7-106.
7-107.
7-108.
...................................................................................................... 978
GPECR Register .......................................................................................................... 980
GPFCTRL Register ....................................................................................................... 982
GPFQSEL1 Register ..................................................................................................... 983
GPFMUX1 Register ...................................................................................................... 985
GPFDIR Register ......................................................................................................... 987
GPFPUD Register ........................................................................................................ 989
GPFINV Register ......................................................................................................... 991
GPFODR Register ........................................................................................................ 993
GPFGMUX1 Register .................................................................................................... 995
GPFCSEL1 Register ..................................................................................................... 996
GPFCSEL2 Register ..................................................................................................... 997
GPFLOCK Register....................................................................................................... 998
GPFCR Register ........................................................................................................ 1000
GPADAT Register ....................................................................................................... 1004
GPASET Register ....................................................................................................... 1006
GPACLEAR Register ................................................................................................... 1008
GPATOGGLE Register ................................................................................................. 1010
GPBDAT Register ....................................................................................................... 1012
GPBSET Register ....................................................................................................... 1014
GPBCLEAR Register ................................................................................................... 1016
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
27
www.ti.com
7-109. GPBTOGGLE Register ................................................................................................. 1018
7-110. GPCDAT Register ....................................................................................................... 1020
7-111. GPCSET Register ....................................................................................................... 1022
7-112. GPCCLEAR Register ................................................................................................... 1024
7-113. GPCTOGGLE Register ................................................................................................. 1026
7-114. GPDDAT Register ....................................................................................................... 1028
7-115. GPDSET Register ....................................................................................................... 1030
7-116. GPDCLEAR Register ................................................................................................... 1032
7-117. GPDTOGGLE Register ................................................................................................. 1034
7-118. GPEDAT Register ....................................................................................................... 1036
7-119. GPESET Register ....................................................................................................... 1038
7-120. GPECLEAR Register ................................................................................................... 1040
7-121. GPETOGGLE Register ................................................................................................. 1042
7-122. GPFDAT Register ....................................................................................................... 1044
7-123. GPFSET Register ....................................................................................................... 1046
1048
7-125.
1050
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
8-20.
8-21.
8-22.
8-23.
8-24.
8-25.
8-26.
8-27.
8-28.
8-29.
8-30.
8-31.
8-32.
28
...................................................................................................
GPFTOGGLE Register .................................................................................................
Input X-BAR ..............................................................................................................
ePWM X-BAR Architecture - Single Output .........................................................................
CLB X-BAR Architecture - Single Output ............................................................................
GPIO Output X-BAR Architecture .....................................................................................
ePWM and Output X-BARs Sources .................................................................................
XBARFLG1 Register ....................................................................................................
XBARFLG2 Register ....................................................................................................
XBARFLG3 Register ....................................................................................................
XBARCLR1 Register ....................................................................................................
XBARCLR2 Register ....................................................................................................
XBARCLR3 Register ....................................................................................................
INPUT1SELECT Register ..............................................................................................
INPUT2SELECT Register ..............................................................................................
INPUT3SELECT Register ..............................................................................................
INPUT4SELECT Register ..............................................................................................
INPUT5SELECT Register ..............................................................................................
INPUT6SELECT Register ..............................................................................................
INPUT7SELECT Register ..............................................................................................
INPUT8SELECT Register ..............................................................................................
INPUT9SELECT Register ..............................................................................................
INPUT10SELECT Register ............................................................................................
INPUT11SELECT Register ............................................................................................
INPUT12SELECT Register ............................................................................................
INPUT13SELECT Register ............................................................................................
INPUT14SELECT Register ............................................................................................
INPUTSELECTLOCK Register ........................................................................................
OUTPUT1MUX0TO15CFG Register .................................................................................
OUTPUT1MUX16TO31CFG Register ................................................................................
OUTPUT2MUX0TO15CFG Register .................................................................................
OUTPUT2MUX16TO31CFG Register ................................................................................
OUTPUT3MUX0TO15CFG Register .................................................................................
OUTPUT3MUX16TO31CFG Register ................................................................................
7-124. GPFCLEAR Register
List of Figures
1059
1061
1063
1065
1067
1070
1072
1074
1076
1078
1080
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1101
1104
1107
1110
1113
1116
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
8-33.
8-34.
8-35.
8-36.
8-37.
8-38.
8-39.
8-40.
8-41.
8-42.
8-43.
8-44.
8-45.
8-46.
8-47.
8-48.
8-49.
8-50.
8-51.
8-52.
8-53.
8-54.
8-55.
8-56.
8-57.
8-58.
8-59.
8-60.
8-61.
8-62.
8-63.
8-64.
8-65.
8-66.
8-67.
8-68.
8-69.
8-70.
8-71.
8-72.
8-73.
8-74.
8-75.
8-76.
8-77.
8-78.
8-79.
8-80.
8-81.
.................................................................................
OUTPUT4MUX16TO31CFG Register ................................................................................
OUTPUT5MUX0TO15CFG Register .................................................................................
OUTPUT5MUX16TO31CFG Register ................................................................................
OUTPUT6MUX0TO15CFG Register .................................................................................
OUTPUT6MUX16TO31CFG Register ................................................................................
OUTPUT7MUX0TO15CFG Register .................................................................................
OUTPUT7MUX16TO31CFG Register ................................................................................
OUTPUT8MUX0TO15CFG Register .................................................................................
OUTPUT8MUX16TO31CFG Register ................................................................................
OUTPUT1MUXENABLE Register .....................................................................................
OUTPUT2MUXENABLE Register .....................................................................................
OUTPUT3MUXENABLE Register .....................................................................................
OUTPUT4MUXENABLE Register .....................................................................................
OUTPUT5MUXENABLE Register .....................................................................................
OUTPUT6MUXENABLE Register .....................................................................................
OUTPUT7MUXENABLE Register .....................................................................................
OUTPUT8MUXENABLE Register .....................................................................................
OUTPUTLATCH Register ..............................................................................................
OUTPUTLATCHCLR Register.........................................................................................
OUTPUTLATCHFRC Register ........................................................................................
OUTPUTLATCHENABLE Register ...................................................................................
OUTPUTINV Register ..................................................................................................
OUTPUTLOCK Register ...............................................................................................
TRIP4MUX0TO15CFG Register ......................................................................................
TRIP4MUX16TO31CFG Register .....................................................................................
TRIP5MUX0TO15CFG Register ......................................................................................
TRIP5MUX16TO31CFG Register .....................................................................................
TRIP7MUX0TO15CFG Register ......................................................................................
TRIP7MUX16TO31CFG Register .....................................................................................
TRIP8MUX0TO15CFG Register ......................................................................................
TRIP8MUX16TO31CFG Register .....................................................................................
TRIP9MUX0TO15CFG Register ......................................................................................
TRIP9MUX16TO31CFG Register .....................................................................................
TRIP10MUX0TO15CFG Register .....................................................................................
TRIP10MUX16TO31CFG Register ...................................................................................
TRIP11MUX0TO15CFG Register .....................................................................................
TRIP11MUX16TO31CFG Register ...................................................................................
TRIP12MUX0TO15CFG Register .....................................................................................
TRIP12MUX16TO31CFG Register ...................................................................................
TRIP4MUXENABLE Register ..........................................................................................
TRIP5MUXENABLE Register ..........................................................................................
TRIP7MUXENABLE Register ..........................................................................................
TRIP8MUXENABLE Register ..........................................................................................
TRIP9MUXENABLE Register ..........................................................................................
TRIP10MUXENABLE Register ........................................................................................
TRIP11MUXENABLE Register ........................................................................................
TRIP12MUXENABLE Register ........................................................................................
TRIPOUTINV Register..................................................................................................
OUTPUT4MUX0TO15CFG Register
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
1119
1122
1125
1128
1131
1134
1137
1140
1143
1146
1149
1154
1159
1164
1169
1174
1179
1184
1189
1191
1193
1195
1197
1199
1202
1205
1208
1211
1214
1217
1220
1223
1226
1229
1232
1235
1238
1241
1244
1247
1250
1255
1260
1265
1270
1275
1280
1285
1290
29
www.ti.com
8-82.
8-83.
8-84.
8-85.
8-86.
8-87.
8-88.
8-89.
8-90.
8-91.
8-92.
8-93.
8-94.
8-95.
8-96.
8-97.
8-98.
8-99.
8-100.
8-101.
8-102.
8-103.
8-104.
8-105.
8-106.
8-107.
8-108.
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
10-1.
10-2.
10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
10-9.
10-10.
10-11.
10-12.
10-13.
30
....................................................................................................
AUXSIG0MUX0TO15CFG Register ..................................................................................
AUXSIG0MUX16TO31CFG Register .................................................................................
AUXSIG1MUX0TO15CFG Register ..................................................................................
AUXSIG1MUX16TO31CFG Register .................................................................................
AUXSIG2MUX0TO15CFG Register ..................................................................................
AUXSIG2MUX16TO31CFG Register .................................................................................
AUXSIG3MUX0TO15CFG Register ..................................................................................
AUXSIG3MUX16TO31CFG Register .................................................................................
AUXSIG4MUX0TO15CFG Register ..................................................................................
AUXSIG4MUX16TO31CFG Register .................................................................................
AUXSIG5MUX0TO15CFG Register ..................................................................................
AUXSIG5MUX16TO31CFG Register .................................................................................
AUXSIG6MUX0TO15CFG Register ..................................................................................
AUXSIG6MUX16TO31CFG Register .................................................................................
AUXSIG7MUX0TO15CFG Register ..................................................................................
AUXSIG7MUX16TO31CFG Register .................................................................................
AUXSIG0MUXENABLE Register......................................................................................
AUXSIG1MUXENABLE Register......................................................................................
AUXSIG2MUXENABLE Register......................................................................................
AUXSIG3MUXENABLE Register......................................................................................
AUXSIG4MUXENABLE Register......................................................................................
AUXSIG5MUXENABLE Register......................................................................................
AUXSIG6MUXENABLE Register......................................................................................
AUXSIG7MUXENABLE Register......................................................................................
AUXSIGOUTINV Register..............................................................................................
AUXSIGLOCK Register ................................................................................................
Analog Subsystem Block Diagram (176-Pin PTP) ..................................................................
Analog Subsystem Block Diagram (100-Pin PZP) ..................................................................
INTOSC1TRIM Register ................................................................................................
INTOSC2TRIM Register ................................................................................................
TSNSCTL Register ......................................................................................................
LOCK Register...........................................................................................................
ANAREFTRIMA Register...............................................................................................
ANAREFTRIMB Register...............................................................................................
ANAREFTRIMD Register ..............................................................................................
ADC Module Block Diagram ...........................................................................................
SOC Block Diagram.....................................................................................................
Single-Ended Input Model ..............................................................................................
Round Robin Priority Example ........................................................................................
High Priority Example ...................................................................................................
Burst Priority Example ..................................................................................................
ADC EOC Interrupts ....................................................................................................
ADC PPB Block Diagram ..............................................................................................
ADC PPB Interrupt Event ..............................................................................................
Opens/Shorts Detection Circuit ........................................................................................
Input Circuit Equivalent with OSDETECT Enabled .................................................................
ADC Timings for 12-bit Mode in Early Interrupt Mode .............................................................
ADC Timings for 12-bit Mode in Late Interrupt Mode ..............................................................
TRIPLOCK Register
List of Figures
1292
1295
1299
1303
1307
1311
1315
1319
1323
1327
1331
1335
1339
1343
1347
1351
1355
1359
1364
1369
1374
1379
1384
1389
1394
1399
1401
1409
1410
1414
1415
1416
1417
1419
1420
1421
1424
1427
1428
1433
1434
1436
1437
1438
1440
1441
1442
1445
1446
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
10-14. Example: Basic Synchronous Operation ............................................................................. 1447
10-15. Example: Synchronous Operation with Multiple Trigger Sources................................................. 1448
10-16. Example: Synchronous Operation with Uneven SOC Numbers .................................................. 1449
10-17. Example: Asynchronous Operation with Uneven SOC Numbers – Trigger Overflow .......................... 1449
10-18. Example: Synchronous Equivalent Operation with Non-Overlapping Conversions ............................ 1450
10-19. ADC Reference System ................................................................................................ 1452
10-20. ADC Shared Reference System....................................................................................... 1453
10-21. ADCCTL1 Register ...................................................................................................... 1458
10-22. ADCCTL2 Register ...................................................................................................... 1460
10-23. ADCBURSTCTL Register .............................................................................................. 1461
10-24. ADCINTFLG Register ................................................................................................... 1463
10-25. ADCINTFLGCLR Register ............................................................................................. 1465
10-26. ADCINTOVF Register
..................................................................................................
1467
10-27. ADCINTOVFCLR Register ............................................................................................. 1469
10-28. ADCINTSEL1N2 Register .............................................................................................. 1470
10-29. ADCINTSEL3N4 Register .............................................................................................. 1472
10-30. ADCSOCPRICTL Register ............................................................................................. 1474
...........................................................................................
...........................................................................................
ADCSOCFLG1 Register ................................................................................................
ADCSOCFRC1 Register ...............................................................................................
ADCSOCOVF1 Register ...............................................................................................
ADCSOCOVFCLR1 Register ..........................................................................................
ADCSOC0CTL Register ................................................................................................
ADCSOC1CTL Register ................................................................................................
ADCSOC2CTL Register ................................................................................................
ADCSOC3CTL Register ................................................................................................
ADCSOC4CTL Register ................................................................................................
ADCSOC5CTL Register ................................................................................................
ADCSOC6CTL Register ................................................................................................
ADCSOC7CTL Register ................................................................................................
ADCSOC8CTL Register ................................................................................................
ADCSOC9CTL Register ................................................................................................
ADCSOC10CTL Register ..............................................................................................
ADCSOC11CTL Register ..............................................................................................
ADCSOC12CTL Register ..............................................................................................
ADCSOC13CTL Register ..............................................................................................
ADCSOC14CTL Register ..............................................................................................
ADCSOC15CTL Register ..............................................................................................
ADCEVTSTAT Register ................................................................................................
ADCEVTCLR Register..................................................................................................
ADCEVTSEL Register ..................................................................................................
ADCEVTINTSEL Register..............................................................................................
ADCOSDETECT Register..............................................................................................
ADCCOUNTER Register ...............................................................................................
ADCREV Register .......................................................................................................
ADCOFFTRIM Register ................................................................................................
ADCPPB1CONFIG Register ...........................................................................................
ADCPPB1STAMP Register ............................................................................................
10-31. ADCINTSOCSEL1 Register
1477
10-32. ADCINTSOCSEL2 Register
1479
10-33.
1481
10-34.
10-35.
10-36.
10-37.
10-38.
10-39.
10-40.
10-41.
10-42.
10-43.
10-44.
10-45.
10-46.
10-47.
10-48.
10-49.
10-50.
10-51.
10-52.
10-53.
10-54.
10-55.
10-56.
10-57.
10-58.
10-59.
10-60.
10-61.
10-62.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
1486
1491
1495
1499
1502
1505
1508
1511
1514
1517
1520
1523
1526
1529
1532
1535
1538
1541
1544
1547
1549
1551
1553
1555
1556
1557
1558
1559
1561
31
www.ti.com
10-63. ADCPPB1OFFCAL Register ........................................................................................... 1562
10-64. ADCPPB1OFFREF Register........................................................................................... 1563
10-65. ADCPPB1TRIPHI Register
............................................................................................
1564
10-66. ADCPPB1TRIPLO Register............................................................................................ 1565
10-67. ADCPPB2CONFIG Register ........................................................................................... 1566
10-68. ADCPPB2STAMP Register ............................................................................................ 1568
10-69. ADCPPB2OFFCAL Register ........................................................................................... 1569
10-70. ADCPPB2OFFREF Register........................................................................................... 1570
............................................................................................
10-72. ADCPPB2TRIPLO Register............................................................................................
10-73. ADCPPB3CONFIG Register ...........................................................................................
10-74. ADCPPB3STAMP Register ............................................................................................
10-75. ADCPPB3OFFCAL Register ...........................................................................................
10-76. ADCPPB3OFFREF Register...........................................................................................
10-77. ADCPPB3TRIPHI Register ............................................................................................
10-78. ADCPPB3TRIPLO Register............................................................................................
10-79. ADCPPB4CONFIG Register ...........................................................................................
10-80. ADCPPB4STAMP Register ............................................................................................
10-81. ADCPPB4OFFCAL Register ...........................................................................................
10-82. ADCPPB4OFFREF Register...........................................................................................
10-83. ADCPPB4TRIPHI Register ............................................................................................
10-84. ADCPPB4TRIPLO Register............................................................................................
10-85. ADCINLTRIM1 Register ................................................................................................
10-86. ADCINLTRIM2 Register ................................................................................................
10-87. ADCINLTRIM3 Register ................................................................................................
10-88. ADCINLTRIM4 Register ................................................................................................
10-89. ADCINLTRIM5 Register ................................................................................................
10-90. ADCINLTRIM6 Register ................................................................................................
10-91. ADCRESULT0 Register ................................................................................................
10-92. ADCRESULT1 Register ................................................................................................
10-93. ADCRESULT2 Register ................................................................................................
10-94. ADCRESULT3 Register ................................................................................................
10-95. ADCRESULT4 Register ................................................................................................
10-96. ADCRESULT5 Register ................................................................................................
10-97. ADCRESULT6 Register ................................................................................................
10-98. ADCRESULT7 Register ................................................................................................
10-99. ADCRESULT8 Register ................................................................................................
10-100. ADCRESULT9 Register ...............................................................................................
10-101. ADCRESULT10 Register .............................................................................................
10-102. ADCRESULT11 Register .............................................................................................
10-103. ADCRESULT12 Register .............................................................................................
10-104. ADCRESULT13 Register .............................................................................................
10-105. ADCRESULT14 Register .............................................................................................
10-106. ADCRESULT15 Register .............................................................................................
10-107. ADCPPB1RESULT Register .........................................................................................
10-108. ADCPPB2RESULT Register .........................................................................................
10-109. ADCPPB3RESULT Register .........................................................................................
10-110. ADCPPB4RESULT Register .........................................................................................
11-1. DAC Module Block Diagram ...........................................................................................
10-71. ADCPPB2TRIPHI Register
32
List of Figures
1571
1572
1573
1575
1576
1577
1578
1579
1580
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1620
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
11-2.
DACREV Register ....................................................................................................... 1624
11-3.
DACCTL Register ....................................................................................................... 1625
11-4.
DACVALA Register
1626
11-5.
DACVALS Register
1627
11-6.
11-7.
11-8.
12-1.
12-2.
12-3.
12-4.
12-5.
12-6.
12-7.
12-8.
12-9.
12-10.
12-11.
12-12.
12-13.
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
12-26.
12-27.
12-28.
13-1.
13-2.
13-3.
13-4.
13-5.
13-6.
13-7.
13-8.
13-9.
13-10.
13-11.
13-12.
13-13.
13-14.
.....................................................................................................
.....................................................................................................
DACOUTEN Register ...................................................................................................
DACLOCK Register .....................................................................................................
DACTRIM Register ......................................................................................................
CMPSS Module Block Diagram .......................................................................................
Comparator Block Diagram ............................................................................................
Reference DAC Block Diagram .......................................................................................
Output Voltage Calculation.............................................................................................
Ramp Generator Block Diagram ......................................................................................
Ramp Generator Behavior .............................................................................................
Digital Filter Behavior ...................................................................................................
COMPCTL Register .....................................................................................................
COMPHYSCTL Register ...............................................................................................
COMPSTS Register.....................................................................................................
COMPSTSCLR Register ...............................................................................................
COMPDACCTL Register ...............................................................................................
DACHVALS Register ...................................................................................................
DACHVALA Register ...................................................................................................
RAMPMAXREFA Register .............................................................................................
RAMPMAXREFS Register .............................................................................................
RAMPDECVALA Register..............................................................................................
RAMPDECVALS Register..............................................................................................
RAMPSTS Register .....................................................................................................
DACLVALS Register ....................................................................................................
DACLVALA Register ....................................................................................................
RAMPDLYA Register ...................................................................................................
RAMPDLYS Register ...................................................................................................
CTRIPLFILCTL Register ...............................................................................................
CTRIPLFILCLKCTL Register ..........................................................................................
CTRIPHFILCTL Register ...............................................................................................
CTRIPHFILCLKCTL Register ..........................................................................................
COMPLOCK Register ..................................................................................................
Sigma Delta Filter Module (SDFM) CPU Interface .................................................................
Sigma Delta Filter Module (SDFM) Block Diagram .................................................................
Block Diagram of One Filter Module ..................................................................................
Different Modulator Modes Supported ................................................................................
Z-Transform of Sinc Filter of Order N ................................................................................
Simplified Sinc Filter Architecture .....................................................................................
Frequency Response of different Sinc Filters .......................................................................
SDSYNC Event ..........................................................................................................
Comparator Unit Structure .............................................................................................
SDFM Interrupt Unit .....................................................................................................
SDIFLG Register ........................................................................................................
SDIFLGCLR Register ...................................................................................................
SDCTL Register .........................................................................................................
SDMFILEN Register ....................................................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
1628
1629
1630
1634
1634
1635
1635
1637
1638
1638
1644
1646
1647
1648
1649
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1670
1671
1672
1674
1675
1675
1676
1678
1680
1682
1688
1690
1692
1693
33
www.ti.com
13-15. SDCTLPARM1 Register ................................................................................................ 1694
13-16. SDDFPARM1 Register ................................................................................................. 1695
13-17. SDDPARM1 Register ................................................................................................... 1696
13-18. SDCMPH1 Register ..................................................................................................... 1697
13-19. SDCMPL1 Register ..................................................................................................... 1698
13-20. SDCPARM1 Register ................................................................................................... 1699
13-21. SDDATA1 Register
.....................................................................................................
1700
13-22. SDCTLPARM2 Register ................................................................................................ 1701
13-23. SDDFPARM2 Register ................................................................................................. 1702
13-24. SDDPARM2 Register ................................................................................................... 1703
13-25. SDCMPH2 Register ..................................................................................................... 1704
13-26. SDCMPL2 Register ..................................................................................................... 1705
13-27. SDCPARM2 Register ................................................................................................... 1706
.....................................................................................................
SDCTLPARM3 Register ................................................................................................
SDDFPARM3 Register .................................................................................................
SDDPARM3 Register ...................................................................................................
SDCMPH3 Register .....................................................................................................
SDCMPL3 Register .....................................................................................................
SDCPARM3 Register ...................................................................................................
SDDATA3 Register .....................................................................................................
SDCTLPARM4 Register ................................................................................................
SDDFPARM4 Register .................................................................................................
SDDPARM4 Register ...................................................................................................
SDCMPH4 Register .....................................................................................................
SDCMPL4 Register .....................................................................................................
SDCPARM4 Register ...................................................................................................
SDDATA4 Register .....................................................................................................
Multiple ePWM Modules................................................................................................
Submodules and Signal Connections for an ePWM Module ......................................................
ePWM modules and Critical Internal Signal Interconnects ........................................................
Time-Base Submodule .................................................................................................
Time-Base Submodule Signals and Registers ......................................................................
Time-Base Frequency and Period ....................................................................................
Time-Base Counter Synchronization Scheme .......................................................................
Time-Base Up-Count Mode Waveforms .............................................................................
Time-Base Down-Count Mode Waveforms ..........................................................................
Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event ...
Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event ......
Global Load: Signals and Registers ..................................................................................
Counter-Compare Submodule .........................................................................................
Detailed View of the Counter-Compare Submodule ................................................................
Counter-Compare Event Waveforms in Up-Count Mode ..........................................................
Counter-Compare Events in Down-Count Mode ....................................................................
13-28. SDDATA2 Register
13-29.
13-30.
13-31.
13-32.
13-33.
13-34.
13-35.
13-36.
13-37.
13-38.
13-39.
13-40.
13-41.
13-42.
14-1.
14-2.
14-3.
14-4.
14-5.
14-6.
14-7.
14-8.
14-9.
14-10.
14-11.
14-12.
14-13.
14-14.
14-15.
14-16.
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1728
1729
1731
1734
1735
1737
1739
1741
1742
1742
1743
1744
1745
1746
1749
1750
14-17. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event ................................................................................................. 1751
14-18. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event ..................................................................................................................... 1751
14-19. Action-Qualifier Submodule ............................................................................................ 1752
34
List of Figures
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
14-20. Action-Qualifier Submodule Inputs and Outputs .................................................................... 1753
.........................................
...........................................................................................
AQCTL[SHDWAQBMODE] ............................................................................................
Up-Down-Count Mode Symmetrical Waveform .....................................................................
14-21. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs
1754
14-22. AQCTL[SHDWAQAMODE]
1757
14-23.
1757
14-24.
1759
14-25. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High ................................................................................................. 1760
14-26. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low ................................................................................................. 1761
14-27. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA ........... 1762
14-28. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ................................................................................................ 1762
14-29. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary .......................................................................................... 1763
14-30. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low ........................................................................................................................ 1764
.....................................
Dead_Band Submodule ................................................................................................
Configuration Options for the Dead-Band Submodule .............................................................
Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)..................................................
PWM Chopper Submodule.............................................................................................
PWM Chopper Submodule Operational Details .....................................................................
Simple PWM Chopper Submodule Waveforms Showing Chopping Action Only ...............................
PWM Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ......
14-31. Up-Down-Count, PWM Waveform Generation Utilizing T1 and T2 Events
14-32.
14-33.
14-34.
14-35.
14-36.
14-37.
14-38.
1764
1765
1767
1769
1771
1772
1772
1773
14-39. PWM Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ..................................................................................................................... 1774
14-40. Trip-Zone Submodule ................................................................................................... 1775
14-41. Trip-Zone Submodule Mode Control Logic .......................................................................... 1779
14-42. Trip-Zone Submodule Interrupt Logic................................................................................. 1780
14-43. Event-Trigger Submodule .............................................................................................. 1781
14-44. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs....................................... 1782
14-45. Event-Trigger Interrupt Generator ..................................................................................... 1784
...............................................................................
...............................................................................
Digital-Compare Submodule High-Level Block Diagram ...........................................................
GPIO MUX-to-Trip Input Connectivity ................................................................................
DCAEVT1 Event Triggering ............................................................................................
DCAEVT2 Event Triggering ............................................................................................
DCBEVT1 Event Triggering ............................................................................................
DCBEVT2 Event Triggering ............................................................................................
Event Filtering ...........................................................................................................
Blanking Window Timing Diagram ....................................................................................
Valley Switching .........................................................................................................
ePWM X-BAR ............................................................................................................
Simplified ePWM Module...............................................................................................
EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave .....................................
Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 ..................................................
Buck Waveforms for (Note: Only three bucks shown here) .......................................................
Control of Four Buck Stages. (Note: FPWM2 = N x FPWM1) ............................................................
Buck Waveforms for (Note: FPWM2 = FPWM1))...........................................................................
14-46. Event-Trigger SOCA Pulse Generator
1785
14-47. Event-Trigger SOCB Pulse Generator
1785
14-48.
1786
14-49.
14-50.
14-51.
14-52.
14-53.
14-54.
14-55.
14-56.
14-57.
14-58.
14-59.
14-60.
14-61.
14-62.
14-63.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
1787
1790
1790
1791
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
35
www.ti.com
14-64. Control of Two Half-H Bridge Stages (FPWM2 = N x FPWM1) .......................................................... 1802
14-65. Half-H Bridge Waveforms for (Note: Here FPWM2 = FPWM1 ) .......................................................... 1803
14-66. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control ............................. 1804
14-67. 3-Phase Inverter Waveforms for (Only One Inverter Shown) ..................................................... 1805
14-68. Configuring Two PWM Modules for Phase Control ................................................................. 1806
14-69. Timing Waveforms Associated With Phase Control Between Two Modules .................................... 1807
14-70. Control of a 3-Phase Interleaved DC/DC Converter ................................................................ 1808
...........................................................
...................................................................
14-73. ZVS Full-H Bridge Waveforms ........................................................................................
14-74. Peak Current Mode Control of a Buck Converter ...................................................................
14-75. Peak Current Mode Control Waveforms for .........................................................................
14-76. Control of Two Resonant Converter Stages .........................................................................
14-77. H-Bridge LLC Resonant Converter PWM Waveforms..............................................................
14-78. Resolution Calculations for Conventionally Generated PWM .....................................................
14-79. Operating Logic Using MEP ...........................................................................................
14-80. HRPWM Extension Registers and Memory Configuration .........................................................
14-81. HRPWM System Interface .............................................................................................
14-82. HRPWM Block Diagram ................................................................................................
14-83. HRPWM and HRCAL Source Clock ..................................................................................
14-84. Required PWM Waveform for a Requested Duty = 40.5% ........................................................
14-85. Low % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0) ...........................................
14-86. High % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0) ..........................................
14-87. Up-Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1) .........................................
14-88. Up-Down Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1) ..................................
14-89. Simple Buck Controlled Converter Using a Single PWM ..........................................................
14-90. PWM Waveform Generated for Simple Buck Controlled Converter ..............................................
14-91. Simple Reconstruction Filter for a PWM-based DAC ..............................................................
14-92. PWM Waveform Generated for the PWM DAC Function ..........................................................
14-93. TBCTL Register .........................................................................................................
14-94. TBCTL2 Register ........................................................................................................
14-95. TBCTR Register .........................................................................................................
14-96. TBSTS Register .........................................................................................................
14-97. CMPCTL Register .......................................................................................................
14-98. CMPCTL2 Register .....................................................................................................
14-99. DBCTL Register .........................................................................................................
14-100. DBCTL2 Register ......................................................................................................
14-101. AQCTL Register........................................................................................................
14-102. AQTSRCSEL Register ................................................................................................
14-103. PCCTL Register ........................................................................................................
14-104. VCAPCTL Register ....................................................................................................
14-105. VCNTCFG Register ...................................................................................................
14-106. HRCNFG Register .....................................................................................................
14-107. HRPWR Register ......................................................................................................
14-108. HRMSTEP Register ...................................................................................................
14-109. HRCNFG2 Register ...................................................................................................
14-110. HRPCTL Register ......................................................................................................
14-111. TRREM Register .......................................................................................................
14-112. GLDCTL Register ......................................................................................................
36
14-71. 3-Phase Interleaved DC/DC Converter Waveforms for
1809
14-72. Controlling a Full-H Bridge Stage (FPWM2 = FPWM1)
1810
List of Figures
1811
1812
1812
1813
1813
1814
1816
1817
1818
1819
1819
1822
1825
1827
1827
1828
1833
1833
1835
1835
1845
1848
1849
1850
1851
1853
1855
1858
1859
1861
1862
1864
1866
1868
1870
1871
1872
1873
1875
1876
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
14-113. GLDCFG Register ..................................................................................................... 1878
14-114. EPWMXLINK Register
................................................................................................
1880
14-115. AQCTLA Register ...................................................................................................... 1884
14-116. AQCTLA2 Register .................................................................................................... 1886
14-117. AQCTLB Register ...................................................................................................... 1888
14-118. AQCTLB2 Register .................................................................................................... 1890
14-119. AQSFRC Register ..................................................................................................... 1892
14-120. AQCSFRC Register
...................................................................................................
1894
14-121. DBREDHR Register ................................................................................................... 1895
14-122. DBRED Register ....................................................................................................... 1896
...................................................................................................
DBFED Register .......................................................................................................
TBPHS Register........................................................................................................
TBPRDHR Register ...................................................................................................
TBPRD Register .......................................................................................................
CMPA Register .........................................................................................................
CMPB Register .........................................................................................................
CMPC Register .........................................................................................................
CMPD Register .........................................................................................................
GLDCTL2 Register ....................................................................................................
SWVDELVAL Register ................................................................................................
TZSEL Register ........................................................................................................
TZDCSEL Register ....................................................................................................
TZCTL Register ........................................................................................................
TZCTL2 Register .......................................................................................................
TZCTLDCA Register ..................................................................................................
TZCTLDCB Register ..................................................................................................
TZEINT Register .......................................................................................................
TZFLG Register ........................................................................................................
TZCBCFLG Register ..................................................................................................
TZOSTFLG Register ..................................................................................................
TZCLR Register ........................................................................................................
TZCBCCLR Register ..................................................................................................
TZOSTCLR Register ..................................................................................................
TZFRC Register ........................................................................................................
ETSEL Register ........................................................................................................
ETPS Register .........................................................................................................
ETFLG Register ........................................................................................................
ETCLR Register ........................................................................................................
ETFRC Register........................................................................................................
ETINTPS Register .....................................................................................................
ETSOCPS Register ....................................................................................................
ETCNTINITCTL Register .............................................................................................
ETCNTINIT Register ..................................................................................................
DCTRIPSEL Register .................................................................................................
DCACTL Register ......................................................................................................
DCBCTL Register ......................................................................................................
DCFCTL Register ......................................................................................................
DCCAPCTL Register ..................................................................................................
14-123. DBFEDHR Register
1897
14-124.
1898
14-125.
14-126.
14-127.
14-128.
14-129.
14-130.
14-131.
14-132.
14-133.
14-134.
14-135.
14-136.
14-137.
14-138.
14-139.
14-140.
14-141.
14-142.
14-143.
14-144.
14-145.
14-146.
14-147.
14-148.
14-149.
14-150.
14-151.
14-152.
14-153.
14-154.
14-155.
14-156.
14-157.
14-158.
14-159.
14-160.
14-161.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1910
1912
1914
1916
1918
1920
1921
1923
1925
1927
1929
1931
1933
1934
1937
1940
1941
1942
1943
1944
1946
1947
1948
1950
1952
1954
1956
37
www.ti.com
................................................................................................
14-163. DCFOFFSETCNT Register ...........................................................................................
14-164. DCFWINDOW Register ...............................................................................................
14-165. DCFWINDOWCNT Register ..........................................................................................
14-166. DCCAP Register .......................................................................................................
14-167. DCAHTRIPSEL Register ..............................................................................................
14-168. DCALTRIPSEL Register ..............................................................................................
14-169. DCBHTRIPSEL Register ..............................................................................................
14-170. DCBLTRIPSEL Register ..............................................................................................
14-171. HWVDELVAL Register ................................................................................................
14-172. VCNTVAL Register ....................................................................................................
14-173. SYNCSELECT Register...............................................................................................
14-174. ADCSOCOUTSELECT Register .....................................................................................
14-175. SYNCSOCLOCK Register ............................................................................................
15-1. Capture and APWM Modes of Operation ............................................................................
15-2. Counter Compare and PRD Effects on the eCAP Output in APWM Mode ......................................
15-3. eCAP Block Diagram ...................................................................................................
15-4. Event Prescale Control .................................................................................................
15-5. Prescale Function Waveforms .........................................................................................
15-6. Details of the Continuous/One-shot Block ...........................................................................
15-7. Details of the Counter and Synchronization Block ..................................................................
15-8. Time-Base Counter Synchronization Scheme ......................................................................
15-9. Interrupts in eCAP Module .............................................................................................
15-10. PWM Waveform Details Of APWM Mode Operation ...............................................................
15-11. Time-Base Frequency and Period Calculation ......................................................................
15-12. Capture Sequence for Absolute Time-stamp and Rising Edge Detect...........................................
15-13. Capture Sequence for Absolute Time-stamp With Rising and Falling Edge Detect ............................
15-14. Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect .......................................
15-15. Capture Sequence for Delta Mode Time-stamp With Rising and Falling Edge Detect ........................
15-16. PWM Waveform Details of APWM Mode Operation................................................................
15-17. TSCTR Register .........................................................................................................
15-18. CTRPHS Register .......................................................................................................
15-19. CAP1 Register ...........................................................................................................
15-20. CAP2 Register ...........................................................................................................
15-21. CAP3 Register ...........................................................................................................
15-22. CAP4 Register ...........................................................................................................
15-23. ECCTL1 Register........................................................................................................
15-24. ECCTL2 Register........................................................................................................
15-25. ECEINT Register ........................................................................................................
15-26. ECFLG Register .........................................................................................................
15-27. ECCLR Register .........................................................................................................
15-28. ECFRC Register .........................................................................................................
16-1. Optical Encoder Disk ...................................................................................................
16-2. QEP Encoder Output Signal for Forward/Reverse Movement ....................................................
16-3. Index Pulse Example ...................................................................................................
16-4. Functional Block Diagram of the eQEP Peripheral .................................................................
16-5. Functional Block Diagram of Decoder Unit ..........................................................................
16-6. Quadrature Decoder State Machine ..................................................................................
16-7. Quadrature-clock and Direction Decoding ...........................................................................
14-162. DCFOFFSET Register
38
List of Figures
1958
1959
1960
1961
1962
1963
1965
1967
1969
1971
1972
1974
1977
1980
1992
1993
1994
1995
1995
1996
1997
1998
2000
2001
2002
2002
2003
2004
2005
2006
2009
2010
2011
2012
2013
2014
2015
2017
2019
2021
2023
2024
2028
2028
2029
2031
2033
2034
2035
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
16-8.
Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or 0xF9F) .............. 2037
16-9.
Position Counter Underflow/Overflow (QPOSMAX = 4)
...........................................................
2038
16-10. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1) ............................................... 2039
16-11. Strobe Event Latch (QEPCTL[SEL] = 1) ............................................................................. 2040
16-12. eQEP Position-compare Unit .......................................................................................... 2041
16-13. eQEP Position-compare Event Generation Points .................................................................. 2042
16-14. eQEP Position-compare Sync Output Pulse Stretcher ............................................................. 2042
16-15. eQEP Edge Capture Unit
..............................................................................................
2044
16-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010) ................................. 2044
16-17. eQEP Edge Capture Unit - Timing Details ........................................................................... 2045
16-18. eQEP Watchdog Timer ................................................................................................. 2046
16-19. eQEP Unit Time Base .................................................................................................. 2047
16-20. EQEP Interrupt Generation ............................................................................................ 2047
16-21. QPOSCNT Register..................................................................................................... 2051
16-22. QPOSINIT Register ..................................................................................................... 2052
16-23. QPOSMAX Register .................................................................................................... 2053
16-24. QPOSCMP Register .................................................................................................... 2054
....................................................................................................
...................................................................................................
QPOSLAT Register .....................................................................................................
QUTMR Register ........................................................................................................
QUPRD Register ........................................................................................................
QWDTMR Register .....................................................................................................
QWDPRD Register ......................................................................................................
QDECCTL Register .....................................................................................................
QEPCTL Register .......................................................................................................
QCAPCTL Register .....................................................................................................
QPOSCTL Register .....................................................................................................
QEINT Register ..........................................................................................................
QFLG Register...........................................................................................................
QCLR Register ..........................................................................................................
QFRC Register ..........................................................................................................
QEPSTS Register .......................................................................................................
QCTMR Register ........................................................................................................
QCPRD Register ........................................................................................................
QCTMRLAT Register ...................................................................................................
QCPRDLAT Register ...................................................................................................
SPI CPU Interface .......................................................................................................
SPI Interrupt Flags and Enable Logic Generation ..................................................................
SPI DMA Trigger Diagram .............................................................................................
SPI Master/Slave Connection .........................................................................................
SPI Module Master Configuration .....................................................................................
SPI Module Slave Configuration ......................................................................................
SPICLK Signal Options .................................................................................................
SPI: SPICLK-LSPCLK Characteristic When (BRR + 1) is Odd, BRR > 3, and CLKPOLARITY = 1 .........
SPI 3-wire Master Mode ................................................................................................
SPI 3-wire Slave Mode .................................................................................................
Five Bits per Character .................................................................................................
SPI Digital Audio Receiver Configuration Using Two SPIs ........................................................
16-25. QPOSILAT Register
2055
16-26. QPOSSLAT Register
2056
16-27.
2057
16-28.
16-29.
16-30.
16-31.
16-32.
16-33.
16-34.
16-35.
16-36.
16-37.
16-38.
16-39.
16-40.
16-41.
16-42.
16-43.
16-44.
17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
2058
2059
2060
2061
2062
2064
2067
2068
2069
2071
2073
2075
2077
2079
2080
2081
2082
2087
2089
2090
2091
2092
2093
2096
2096
2099
2099
2102
2104
39
www.ti.com
17-13. Standard Right-Justified Digital Audio Data Format ................................................................ 2104
17-14. SPICCR Register ........................................................................................................ 2107
2109
17-16. SPISTS Register
2111
17-17.
2113
17-18.
17-19.
17-20.
17-21.
17-22.
17-23.
17-24.
17-25.
18-1.
18-2.
18-3.
18-4.
18-5.
18-6.
18-7.
18-8.
18-9.
18-10.
18-11.
18-12.
18-13.
18-14.
18-15.
18-16.
18-17.
18-18.
18-19.
18-20.
18-21.
18-22.
18-23.
19-1.
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
19-9.
19-10.
19-11.
19-12.
19-13.
40
........................................................................................................
........................................................................................................
SPIBRR Register ........................................................................................................
SPIRXEMU Register ....................................................................................................
SPIRXBUF Register ....................................................................................................
SPITXBUF Register .....................................................................................................
SPIDAT Register ........................................................................................................
SPIFFTX Register .......................................................................................................
SPIFFRX Register.......................................................................................................
SPIFFCT Register .......................................................................................................
SPIPRI Register .........................................................................................................
SCI CPU Interface ......................................................................................................
Serial Communications Interface (SCI) Module Block Diagram ..................................................
Typical SCI Data Frame Formats .....................................................................................
Idle-Line Multiprocessor Communication Format ...................................................................
Double-Buffered WUT and TXSHF ...................................................................................
Address-Bit Multiprocessor Communication Format................................................................
SCI Asynchronous Communications Format ........................................................................
SCI RX Signals in Communication Modes ...........................................................................
SCI TX Signals in Communications Mode ...........................................................................
SCI FIFO Interrupt Flags and Enable Logic .........................................................................
SCICCR Register........................................................................................................
SCICTL1 Register .......................................................................................................
SCIHBAUD Register ....................................................................................................
SCILBAUD Register ....................................................................................................
SCICTL2 Register .......................................................................................................
SCIRXST Register ......................................................................................................
SCIRXEMU Register ....................................................................................................
SCIRXBUF Register ....................................................................................................
SCITXBUF Register.....................................................................................................
SCIFFTX Register .......................................................................................................
SCIFFRX Register ......................................................................................................
SCIFFCT Register.......................................................................................................
SCIPRI Register .........................................................................................................
Multiple I2C Modules Connected ......................................................................................
I2C Module Conceptual Block Diagram ..............................................................................
Clocking Diagram for the I2C Module ................................................................................
The Roles of the Clock Divide-Down Values (ICCL and ICCH) ...................................................
Bit Transfer on the I2C bus ............................................................................................
I2C Module START and STOP Conditions ..........................................................................
I2C Module Data Transfer (7-Bit Addressing with 8-bit Data Configuration Shown) ...........................
I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR) ............................................
I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR) ...........................................
I2C Module Free Data Format (FDF = 1 in I2CMDR) ..............................................................
Repeated START Condition (in This Case, 7-Bit Addressing Format) ...........................................
Synchronization of Two I2C Clock Generators During Arbitration ................................................
Arbitration Procedure Between Two Master-Transmitters .........................................................
17-15. SPICTL Register
List of Figures
2114
2115
2116
2117
2118
2120
2122
2123
2128
2129
2131
2133
2134
2135
2136
2136
2137
2139
2143
2145
2147
2148
2149
2151
2153
2154
2155
2156
2158
2160
2161
2165
2167
2167
2168
2169
2171
2172
2172
2172
2173
2173
2174
2175
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
19-14. Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit ..................................... 2176
19-15. Enable Paths of the I2C Interrupt Requests ......................................................................... 2177
19-16. Backwards Compatibility Mode Bit, Slave Transmitter ............................................................. 2178
19-17. I2C_FIFO_interrupt...................................................................................................... 2179
19-18. I2COAR Register ........................................................................................................ 2182
19-19. I2CIER Register ......................................................................................................... 2183
19-20. I2CSTR Register
........................................................................................................
2184
19-21. I2CCLKL Register ....................................................................................................... 2188
19-22. I2CCLKH Register....................................................................................................... 2189
19-23. I2CCNT Register ........................................................................................................ 2190
19-24. I2CDRR Register ........................................................................................................ 2191
19-25. I2CSAR Register ........................................................................................................ 2192
19-26. I2CDXR Register ........................................................................................................ 2193
19-27. I2CMDR Register........................................................................................................ 2194
19-28. I2CISRC Register ....................................................................................................... 2198
19-29. I2CEMDR Register ...................................................................................................... 2199
19-30. I2CPSC Register ........................................................................................................ 2200
19-31. I2CFFTX Register ....................................................................................................... 2201
19-32. I2CFFRX Register ....................................................................................................... 2203
20-1.
Conceptual Block Diagram of the McBSP ........................................................................... 2210
20-2.
McBSP Data Transfer Paths ........................................................................................... 2211
20-3.
Companding Processes ................................................................................................ 2212
20-4.
μ-Law Transmit Data Companding Format .......................................................................... 2212
20-5.
A-Law Transmit Data Companding Format .......................................................................... 2212
20-6.
Two Methods by Which the McBSP Can Compand Internal Data ................................................ 2213
20-7.
Example - Clock Signal Control of Bit Transfer Timing
20-8.
20-9.
20-10.
20-11.
20-12.
20-13.
20-14.
20-15.
20-16.
20-17.
20-18.
20-19.
20-20.
20-21.
20-22.
20-23.
20-24.
20-25.
20-26.
20-27.
20-28.
20-29.
20-30.
............................................................
McBSP Operating at Maximum Packet Frequency .................................................................
Single-Phase Frame for a McBSP Data Transfer ...................................................................
Dual-Phase Frame for a McBSP Data Transfer .....................................................................
Implementing the AC97 Standard With a Dual-Phase Frame .....................................................
Timing of an AC97-Standard Data Transfer Near Frame Synchronization ......................................
McBSP Reception Physical Data Path ...............................................................................
McBSP Reception Signal Activity .....................................................................................
McBSP Transmission Physical Data Path ...........................................................................
McBSP Transmission Signal Activity .................................................................................
Conceptual Block Diagram of the Sample Rate Generator ........................................................
Possible Inputs to the Sample Rate Generator and the Polarity Bits ............................................
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 ...........................
CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3 ...........................
Overrun in the McBSP Receiver ......................................................................................
Overrun Prevented in the McBSP Receiver .........................................................................
Possible Responses to Receive Frame-Synchronization Pulses .................................................
An Unexpected Frame-Synchronization Pulse During a McBSP Reception ....................................
Proper Positioning of Frame-Synchronization Pulses ..............................................................
Data in the McBSP Transmitter Overwritten and Thus Not Transmitted.........................................
Underflow During McBSP Transmission .............................................................................
Underflow Prevented in the McBSP Transmitter ....................................................................
Possible Responses to Transmit Frame-Synchronization Pulses ................................................
An Unexpected Frame-Synchronization Pulse During a McBSP Transmission ................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
2213
2215
2216
2217
2217
2218
2218
2218
2219
2219
2221
2223
2225
2226
2228
2229
2229
2230
2231
2231
2232
2233
2233
2234
41
www.ti.com
20-31. Proper Positioning of Frame-Synchronization Pulses .............................................................. 2235
20-32. Alternating Between the Channels of Partition A and the Channels of Partition B ............................. 2237
20-33. Reassigning Channel Blocks Throughout a McBSP Data Transfer .............................................. 2238
20-34. McBSP Data Transfer in the 8-Partition Mode ...................................................................... 2239
20-35. Activity on McBSP Pins for the Possible Values of XMCM ........................................................ 2242
20-36. Typical SPI Interface .................................................................................................... 2243
20-37. SPI Transfer With CLKSTP = 10b (No Clock Delay), CLKXP = 0, and CLKRP = 0
...........................
2245
20-38. SPI Transfer With CLKSTP = 11b (Clock Delay), CLKXP = 0, CLKRP = 1 ..................................... 2245
...........................
SPI Transfer With CLKSTP = 11b (Clock Delay), CLKXP = 1, CLKRP = 1 .....................................
SPI Interface with McBSP Used as Master ..........................................................................
SPI Interface With McBSP Used as Slave ...........................................................................
Unexpected Frame-Synchronization Pulse With (R/X)FIG = 0 ....................................................
Unexpected Frame-Synchronization Pulse With (R/X)FIG = 1 ....................................................
Companding Processes for Reception and for Transmission .....................................................
Range of Programmable Data Delay .................................................................................
2-Bit Data Delay Used to Skip a Framing Bit ........................................................................
Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge ..
Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods .......................................
Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge ..
Unexpected Frame-Synchronization Pulse With (R/X) FIG = 0 ...................................................
Unexpected Frame-Synchronization Pulse With (R/X) FIG = 1 ...................................................
Companding Processes for Reception and for Transmission .....................................................
μ-Law Transmit Data Companding Format ..........................................................................
A-Law Transmit Data Companding Format ..........................................................................
Range of Programmable Data Delay .................................................................................
2-Bit Data Delay Used to Skip a Framing Bit ........................................................................
Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge ..
Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods .......................................
Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge ..
Four 8-Bit Data Words Transferred To/From the McBSP ..........................................................
One 32-Bit Data Word Transferred To/From the McBSP ..........................................................
8-Bit Data Words Transferred at Maximum Packet Frequency ...................................................
Configuring the Data Stream of as a Continuous 32-Bit Word ....................................................
Receive Interrupt Generation ..........................................................................................
Transmit Interrupt Generation .........................................................................................
Data Receive Registers (DRR2 and DRR1) .........................................................................
Data Transmit Registers (DXR2 and DXR1) ........................................................................
Serial Port Control 1 Register (SPCR1) .............................................................................
Serial Port Control 2 Register (SPCR2) .............................................................................
Receive Control Register 1 (RCR1) ..................................................................................
Receive Control Register 2 (RCR2) ..................................................................................
Transmit Control 1 Register (XCR1) ..................................................................................
Transmit Control 2 Register (XCR2) .................................................................................
Sample Rate Generator 1 Register (SRGR1) .......................................................................
Sample Rate Generator 2 Register (SRGR2) .......................................................................
Multichannel Control 1 Register (MCR1) ............................................................................
Multichannel Control 2 Register (MCR2) .............................................................................
Pin Control Register (PCR) ...........................................................................................
20-39. SPI Transfer With CLKSTP = 10b (No Clock Delay), CLKXP = 1, and CLKRP = 0
20-40.
20-41.
20-42.
20-43.
20-44.
20-45.
20-46.
20-47.
20-48.
20-49.
20-50.
20-51.
20-52.
20-53.
20-54.
20-55.
20-56.
20-57.
20-58.
20-59.
20-60.
20-61.
20-62.
20-63.
20-64.
20-65.
20-66.
20-67.
20-68.
20-69.
20-70.
20-71.
20-72.
20-73.
20-74.
20-75.
20-76.
20-77.
20-78.
20-79.
42
List of Figures
2245
2245
2247
2248
2255
2255
2256
2257
2257
2262
2263
2265
2277
2278
2278
2279
2279
2280
2280
2284
2284
2286
2290
2290
2291
2291
2292
2292
2297
2297
2298
2301
2303
2304
2306
2307
2309
2309
2311
2313
2315
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
20-80. Receive Channel Enable Registers (RCERA...RCERH) ........................................................... 2317
..........................................................
........................................................................
CAN Block Diagram .....................................................................................................
CAN_MUX................................................................................................................
CAN Core in Silent Mode ..............................................................................................
CAN Core in Loopback Mode .........................................................................................
CAN Core in External Loopback Mode ...............................................................................
CAN Core in Loopback Combined with Silent Mode ...............................................................
CAN Interrupt Topology 1 ..............................................................................................
CAN Interrupt Topology 2 ..............................................................................................
Initialization of a Transmit Object .....................................................................................
Initialization of a Single Receive Object for Data Frames .........................................................
Initialization of a single Receive Object for Remote Frames ......................................................
CPU Handling of a FIFO Buffer (Interrupt Driven) ..................................................................
Bit Timing .................................................................................................................
The Propagation Time Segment ......................................................................................
Synchronization on Late and Early Edges ...........................................................................
Filtering of Short Dominant Spikes ....................................................................................
Structure of the CAN Core's CAN Protocol Controller .............................................................
Data Transfer Between IF1 / IF2 Registers and Message RAM ..................................................
Structure of a Message Object ........................................................................................
Message RAM Representation in Debug Mode .....................................................................
CAN_CTL Register ......................................................................................................
CAN_ES Register .......................................................................................................
CAN_ERRC Register ...................................................................................................
CAN_BTR Register .....................................................................................................
CAN_INT Register ......................................................................................................
CAN_TEST Register ....................................................................................................
CAN_PERR Register ...................................................................................................
CAN_RAM_INIT Register ..............................................................................................
CAN_GLB_INT_EN Register ..........................................................................................
CAN_GLB_INT_FLG Register .........................................................................................
CAN_GLB_INT_CLR Register.........................................................................................
CAN_ABOTR Register .................................................................................................
CAN_TXRQ_X Register ................................................................................................
CAN_TXRQ_21 Register ...............................................................................................
CAN_NDAT_X Register ................................................................................................
CAN_NDAT_21 Register ...............................................................................................
CAN_IPEN_X Register .................................................................................................
CAN_IPEN_21 Register ................................................................................................
CAN_MVAL_X Register ................................................................................................
CAN_MVAL_21 Register ...............................................................................................
CAN_IP_MUX21 Register ..............................................................................................
CAN_IF1CMD Register .................................................................................................
CAN_IF1MSK Register .................................................................................................
CAN_IF1ARB Register .................................................................................................
CAN_IF1MCTL Register ...............................................................................................
CAN_IF1DATA Register ................................................................................................
20-81. Transmit Channel Enable Registers (XCERA...XCERH)
2319
20-82. McBSP Interrupt Enable Register (MFFINT)
2321
21-1.
2327
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
21-15.
21-16.
21-17.
21-18.
21-19.
21-20.
21-21.
21-22.
21-23.
21-24.
21-25.
21-26.
21-27.
21-28.
21-29.
21-30.
21-31.
21-32.
21-33.
21-34.
21-35.
21-36.
21-37.
21-38.
21-39.
21-40.
21-41.
21-42.
21-43.
21-44.
21-45.
21-46.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
2332
2332
2333
2334
2334
2336
2337
2339
2339
2339
2344
2345
2346
2348
2349
2350
2354
2355
2358
2362
2365
2367
2368
2370
2371
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2392
2393
2395
2398
43
www.ti.com
21-47. CAN_IF1DATB Register ................................................................................................ 2399
21-48. CAN_IF2CMD Register ................................................................................................. 2400
21-49. CAN_IF2MSK Register ................................................................................................. 2404
21-50. CAN_IF2ARB Register ................................................................................................. 2405
21-51. CAN_IF2MCTL Register
...............................................................................................
2407
21-52. CAN_IF2DATA Register ................................................................................................ 2410
21-53. CAN_IF2DATB Register ................................................................................................ 2411
21-54. CAN_IF3OBS Register ................................................................................................. 2412
21-55. CAN_IF3MSK Register ................................................................................................. 2414
21-56. CAN_IF3ARB Register ................................................................................................. 2415
2416
21-58.
2418
21-59.
21-60.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
22-21.
22-22.
22-23.
22-24.
22-25.
22-26.
22-27.
22-28.
22-29.
22-30.
22-31.
22-32.
22-33.
22-34.
22-35.
44
...............................................................................................
CAN_IF3DATA Register ................................................................................................
CAN_IF3DATB Register ................................................................................................
CAN_IF3UPD Register .................................................................................................
USB Block Diagram .....................................................................................................
USB Scheme.............................................................................................................
Function Address Register (USBFADDR) ...........................................................................
Power Management Register (USBPOWER) in Host Mode.......................................................
Power Management Register (USBPOWER) in Device Mode ....................................................
USB Transmit Interrupt Status Register (USBTXIS) ................................................................
USB Transmit Interrupt Status Register (USBRXIS) ...............................................................
USB Transmit Interrupt Status Enable Register (USBTXIE) ......................................................
USB Transmit Interrupt Status Enable Register (USBRXIE) ......................................................
USB General Interrupt Status Register (USBIS) in Host Mode ...................................................
USB General Interrupt Status Register (USBIS) in Device Mode ................................................
USB Interrupt Enable Register (USBIE) in Host Mode .............................................................
USB Interrupt Enable Register (USBIE) in Device Mode ..........................................................
Frame Number Register (FRAME) ....................................................................................
USB Endpoint Index Register (USBEPIDX) .........................................................................
USB Test Mode Register (USBTEST) in Host Mode ...............................................................
USB Test Mode Register (USBTEST) in Device Mode ............................................................
USB FIFO Endpoint n Register (USBFIFO[n]) ......................................................................
USB Device Control Register (USBDEVCTL) .......................................................................
USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ) .................................................
USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ) ..................................................
USB Transmit FIFO Start Address Register (USBTXFIFOADDR]) ...............................................
USB Receive FIFO Start Address Register (USBRXFIFOADDR) ................................................
USB Connect Timing Register (USBCONTIM) ......................................................................
USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF) ...........................
USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF) ...........................
USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[n]) ............................
USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[n])......................................
USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[n]) ...........................................
USB Receive Functional Address Endpoint n Registers (USBFIFO[n]) .........................................
USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[n]) ......................................
USB Transmit Hub Port Endpoint n Registers (USBRXHUBPORT[n]) ..........................................
USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[n]) .........................................
USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Host Mode ................................
USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Device Mode .............................
21-57. CAN_IF3MCTL Register
List of Figures
2419
2420
2424
2425
2448
2449
2449
2451
2453
2455
2457
2459
2460
2461
2462
2463
2463
2464
2464
2466
2467
2469
2470
2471
2472
2473
2474
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
22-36. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Host Mode ............................... 2484
22-37. USB Control and Status Endpoint 0 High Register (USBCSRH0) in Device Mode ............................ 2484
22-38. USB Receive Byte Count Endpoint 0 Register (USBCOUNT0)................................................... 2485
22-39. USB Type Endpoint 0 Register (USBTYPE0) ....................................................................... 2485
22-40. USB NAK Limit Register (USBNAKLMT)
............................................................................
2486
22-41. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Host Mode ................ 2487
22-42. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Device Mode ............. 2488
22-43. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Host Mode ............... 2490
22-44. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Device Mode ............ 2491
22-45. USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[n]) ......................................... 2492
22-46. USB Receive Control and Status Endpoint n Low Register (USBCSRL[n]) in Host Mode .................... 2493
22-47. USB Control and Status Endpoint n Low Register (USBCSRL[n]) in Device Mode ............................ 2494
22-48. USB Receive Control and Status Endpoint n High Register (USBCSRH[n]) in Host Mode ................... 2495
22-49. USB Control and Status Endpoint n High Register (USBCSRH[n]) in Device Mode ........................... 2496
22-50. USB Maximum Receive Data Endpoint n Registers (USBRXCOUNT[n]) ....................................... 2497
22-51. USB Host Transmit Configure Type Endpoint n Register (USBTXTYPE[n]) .................................... 2498
.......................................
....................................
USB Host Receive Polling Interval Endpoint n Register (USBRXINTERVAL[n]) ...............................
USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[n]) ..............
USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS) .................................
USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS) ................................
USB External Power Control Register (USBEPC) ..................................................................
USB External Power Control Raw Interrupt Status Register (USBEPCRIS) ....................................
USB External Power Control Interrupt Mask Register (USBEPCIM) .............................................
USB External Power Control Interrupt Status and Clear Register (USBEPCISC) ..............................
USB Device RESUME Raw Interrupt Status Register (USBDRRIS) .............................................
USB Device RESUME Raw Interrupt Status Register (USBDRRIS) .............................................
USB Device RESUME Interrupt Status and Clear Register (USBDRISC).......................................
USB General-Purpose Control and Status Register (USBGPCS) ................................................
USB DMA Select Register (USBDMASEL) ..........................................................................
EMIF Module Overview .................................................................................................
EMIF Functional Block Diagram .......................................................................................
Timing Waveform of SDRAM PRE Command ......................................................................
EMIF to 2M × 16 × 4 bank SDRAM Interface .......................................................................
EMIF to 512K × 16 × 2 bank SDRAM Interface .....................................................................
Timing Waveform for Basic SDRAM Read Operation ..............................................................
Timing Waveform for Basic SDRAM Write Operation ..............................................................
EMIF Asynchronous Interface .........................................................................................
EMIF to 8-bit/16-bit Memory Interface ................................................................................
Common Asynchronous Interface .....................................................................................
Timing Waveform of an Asynchronous Read Cycle in Normal Mode ............................................
Timing Waveform of an Asynchronous Write Cycle in Normal Mode ............................................
Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode ....................................
Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode .....................................
Example Configuration Interface ......................................................................................
SDRAM Timing Register (SDRAM_TR) ..............................................................................
SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) ..................................................
SDRAM Refresh Control Register (SDRAM_RCR) .................................................................
22-52. USB Host Transmit Interval Endpoint n Register (USBTXINTERVAL[n])
2499
22-53. USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[n])
2500
22-54.
2501
22-55.
22-56.
22-57.
22-58.
22-59.
22-60.
22-61.
22-62.
22-63.
22-64.
22-65.
22-66.
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
2502
2503
2505
2506
2508
2509
2510
2511
2512
2513
2514
2515
2518
2519
2523
2523
2524
2531
2532
2534
2535
2535
2539
2541
2543
2545
2552
2553
2554
2555
45
www.ti.com
23-19. SDRAM Configuration Register (SDRAM_CR)...................................................................... 2555
23-20. LH28F800BJE-PTTL90 to EMIF Read Timing Waveforms ........................................................ 2556
23-21. LH28F800BJE-PTTL90 to EMIF Write Timing Waveforms ........................................................ 2557
23-22. Asynchronous m Configuration Register (m = 1, 2) (ASYNC_CSn_CR(n = 2, 3)) ............................. 2558
23-23. RCSR Register .......................................................................................................... 2561
23-24. ASYNC_WCCR Register ............................................................................................... 2562
23-25. SDRAM_CR Register ................................................................................................... 2563
23-26. SDRAM_RCR Register ................................................................................................. 2565
2566
23-28.
2568
23-29.
23-30.
23-31.
23-32.
23-33.
23-34.
23-35.
23-36.
23-37.
23-38.
23-39.
23-40.
24-1.
24-2.
24-3.
24-4.
24-5.
24-6.
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
46
............................................................................................
ASYNC_CS3_CR Register ............................................................................................
ASYNC_CS4_CR Register ............................................................................................
SDRAM_TR Register ...................................................................................................
TOTAL_SDRAM_AR Register .........................................................................................
TOTAL_SDRAM_ACTR Register .....................................................................................
SDR_EXT_TMNG Register ............................................................................................
INT_RAW Register ......................................................................................................
INT_MSK Register ......................................................................................................
INT_MSK_SET Register ...............................................................................................
INT_MSK_CLR Register ...............................................................................................
EMIF1LOCK Register ...................................................................................................
EMIF1COMMIT Register ...............................................................................................
EMIF1ACCPROT0 Register ...........................................................................................
Block Diagram of the CLB Subsystem in the Device ...............................................................
Block Diagram of a CLB Tile and CPU Interface ...................................................................
CLB Input Mux and Filter ...............................................................................................
GPIO to CLB Tile Connections ........................................................................................
CLB Outputs .............................................................................................................
Peripheral Signal Multiplexer ..........................................................................................
The CLB Tile Submodules .............................................................................................
Counter Block ............................................................................................................
FSM Block ................................................................................................................
FSM LUT Block ..........................................................................................................
LUT4 Block ...............................................................................................................
Output LUT Block .......................................................................................................
High Level Controller Block ............................................................................................
CLB_COUNT_RESET Register .......................................................................................
CLB_COUNT_MODE_1 Register .....................................................................................
CLB_COUNT_MODE_0 Register .....................................................................................
CLB_COUNT_EVENT Register .......................................................................................
CLB_FSM_EXTRA_IN0 Register .....................................................................................
CLB_FSM_EXTERNAL_IN0 Register ................................................................................
CLB_FSM_EXTERNAL_IN1 Register ................................................................................
CLB_FSM_EXTRA_IN1 Register .....................................................................................
CLB_LUT4_IN0 Register ...............................................................................................
CLB_LUT4_IN1 Register ...............................................................................................
CLB_LUT4_IN2 Register ...............................................................................................
CLB_LUT4_IN3 Register ...............................................................................................
CLB_FSM_LUT_FN1_0 Register .....................................................................................
CLB_FSM_LUT_FN2 Register ........................................................................................
23-27. ASYNC_CS2_CR Register
List of Figures
2570
2572
2573
2574
2575
2576
2577
2578
2579
2581
2582
2583
2586
2587
2588
2591
2592
2594
2595
2597
2599
2600
2600
2601
2601
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
24-28. CLB_LUT4_FN1_0 Register ........................................................................................... 2623
24-29. CLB_LUT4_FN2 Register .............................................................................................. 2624
24-30. CLB_FSM_NEXT_STATE_0 Register................................................................................ 2625
24-31. CLB_FSM_NEXT_STATE_1 Register................................................................................ 2626
24-32. CLB_FSM_NEXT_STATE_2 Register................................................................................ 2627
24-33. CLB_MISC_CONTROL Register ...................................................................................... 2628
......................................................................................
......................................................................................
CLB_OUTPUT_LUT_2 Register ......................................................................................
CLB_OUTPUT_LUT_3 Register ......................................................................................
CLB_OUTPUT_LUT_4 Register ......................................................................................
CLB_OUTPUT_LUT_5 Register ......................................................................................
CLB_OUTPUT_LUT_6 Register ......................................................................................
CLB_OUTPUT_LUT_7 Register ......................................................................................
CLB_HLC_EVENT_SEL Register .....................................................................................
CLB_LOAD_EN Register...............................................................................................
CLB_LOAD_ADDR Register ...........................................................................................
CLB_LOAD_DATA Register ...........................................................................................
CLB_INPUT_FILTER Register ........................................................................................
CLB_IN_MUX_SEL_0 Register .......................................................................................
CLB_LCL_MUX_SEL_1 Register .....................................................................................
CLB_LCL_MUX_SEL_2 Register .....................................................................................
CLB_BUF_PTR Register ...............................................................................................
CLB_GP_REG Register ................................................................................................
CLB_OUT_EN Register ................................................................................................
CLB_GLBL_MUX_SEL_1 Register ...................................................................................
CLB_GLBL_MUX_SEL_2 Register ...................................................................................
CLB_INTR_TAG_REG Register ......................................................................................
CLB_LOCK Register ....................................................................................................
CLB_DBG_R0 Register ................................................................................................
CLB_DBG_R1 Register ................................................................................................
CLB_DBG_R2 Register ................................................................................................
CLB_DBG_R3 Register ................................................................................................
CLB_DBG_C0 Register ................................................................................................
CLB_DBG_C1 Register ................................................................................................
CLB_DBG_C2 Register ................................................................................................
CLB_DBG_OUT Register ..............................................................................................
CLB_PUSH_y Register .................................................................................................
CLB_PULL_y Register..................................................................................................
CLB_PUSH_y Register .................................................................................................
CLB_PULL_y Register..................................................................................................
24-34. CLB_OUTPUT_LUT_0 Register
2631
24-35. CLB_OUTPUT_LUT_1 Register
2632
24-36.
2633
24-37.
24-38.
24-39.
24-40.
24-41.
24-42.
24-43.
24-44.
24-45.
24-46.
24-47.
24-48.
24-49.
24-50.
24-51.
24-52.
24-53.
24-54.
24-55.
24-56.
24-57.
24-58.
24-59.
24-60.
24-61.
24-62.
24-63.
24-64.
24-65.
24-66.
24-67.
24-68.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
2634
2635
2636
2637
2638
2639
2642
2643
2644
2645
2647
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2668
2669
2671
2672
47
www.ti.com
List of Tables
1-1.
C2000Ware Root Directories ............................................................................................. 81
2-1.
TMU Supported Instructions .............................................................................................. 84
3-1.
Reset Signals ............................................................................................................... 87
3-2.
PIE Channel Mapping
3-3.
CPU Interrupt Vectors ..................................................................................................... 94
3-4.
PIE Interrupt Vectors ....................................................................................................... 95
3-5.
Access to EALLOW-Protected Registers .............................................................................. 101
3-6.
Clock Connections Sorted by Clock Domain .......................................................................... 110
3-7.
Clock Connections Sorted by Module Name .......................................................................... 111
3-8.
Example Watchdog Key Sequences ................................................................................... 116
3-9.
Local Shared RAM........................................................................................................ 123
3-10.
Global Shared RAM ...................................................................................................... 123
3-11.
Error Handling in Different Scenarios .................................................................................. 127
3-12.
Mapping of ECC Bits in Read Data from ECC/Parity Address Map ............................................... 128
3-13.
Mapping of Parity Bits in Read Data from ECC/Parity Address Map .............................................. 128
3-14.
CLA Access Filter ......................................................................................................... 140
3-15.
RAM Status ................................................................................................................ 140
3-16.
Security Levels ............................................................................................................ 141
3-17.
System Control Base Address Table................................................................................... 153
3-18.
CPUTIMER_REGS Registers ........................................................................................... 154
3-19.
CPUTIMER_REGS Access Type Codes .............................................................................. 154
3-20.
TIM Register Field Descriptions
3-21.
3-22.
3-23.
3-24.
3-25.
3-26.
3-27.
3-28.
3-29.
3-30.
3-31.
3-32.
3-33.
3-34.
3-35.
3-36.
3-37.
3-38.
3-39.
3-40.
3-41.
3-42.
3-43.
3-44.
3-45.
48
.....................................................................................................
........................................................................................
PRD Register Field Descriptions .......................................................................................
TCR Register Field Descriptions........................................................................................
TPR Register Field Descriptions ........................................................................................
TPRH Register Field Descriptions ......................................................................................
PIE_CTRL_REGS Registers ............................................................................................
PIE_CTRL_REGS Access Type Codes ...............................................................................
PIECTRL Register Field Descriptions ..................................................................................
PIEACK Register Field Descriptions ...................................................................................
PIEIER1 Register Field Descriptions ...................................................................................
PIEIFR1 Register Field Descriptions ...................................................................................
PIEIER2 Register Field Descriptions ...................................................................................
PIEIFR2 Register Field Descriptions ...................................................................................
PIEIER3 Register Field Descriptions ...................................................................................
PIEIFR3 Register Field Descriptions ...................................................................................
PIEIER4 Register Field Descriptions ...................................................................................
PIEIFR4 Register Field Descriptions ...................................................................................
PIEIER5 Register Field Descriptions ...................................................................................
PIEIFR5 Register Field Descriptions ...................................................................................
PIEIER6 Register Field Descriptions ...................................................................................
PIEIFR6 Register Field Descriptions ...................................................................................
PIEIER7 Register Field Descriptions ...................................................................................
PIEIFR7 Register Field Descriptions ...................................................................................
PIEIER8 Register Field Descriptions ...................................................................................
PIEIFR8 Register Field Descriptions ...................................................................................
PIEIER9 Register Field Descriptions ...................................................................................
List of Tables
93
155
156
157
159
160
161
161
163
164
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
3-46.
PIEIFR9 Register Field Descriptions ................................................................................... 199
3-47.
PIEIER10 Register Field Descriptions ................................................................................. 201
3-48.
PIEIFR10 Register Field Descriptions
3-49.
PIEIER11 Register Field Descriptions ................................................................................. 205
3-50.
PIEIFR11 Register Field Descriptions
3-51.
PIEIER12 Register Field Descriptions ................................................................................. 209
3-52.
PIEIFR12 Register Field Descriptions
3-53.
WD_REGS Registers
3-54.
3-55.
3-56.
3-57.
3-58.
3-59.
3-60.
3-61.
3-62.
3-63.
3-64.
3-65.
3-66.
3-67.
3-68.
3-69.
3-70.
3-71.
3-72.
3-73.
3-74.
3-75.
3-76.
3-77.
3-78.
3-79.
3-80.
3-81.
3-82.
3-83.
3-84.
3-85.
3-86.
3-87.
3-88.
3-89.
3-90.
3-91.
3-92.
3-93.
3-94.
.................................................................................
.................................................................................
.................................................................................
....................................................................................................
WD_REGS Access Type Codes ........................................................................................
SCSR Register Field Descriptions ......................................................................................
WDCNTR Register Field Descriptions .................................................................................
WDKEY Register Field Descriptions ...................................................................................
WDCR Register Field Descriptions .....................................................................................
WDWCR Register Field Descriptions ..................................................................................
NMI_INTRUPT_REGS Registers .......................................................................................
NMI_INTRUPT_REGS Access Type Codes ..........................................................................
NMICFG Register Field Descriptions ..................................................................................
NMIFLG Register Field Descriptions ...................................................................................
NMIFLGCLR Register Field Descriptions..............................................................................
NMIFLGFRC Register Field Descriptions .............................................................................
NMIWDCNT Register Field Descriptions ..............................................................................
NMIWDPRD Register Field Descriptions ..............................................................................
NMISHDFLG Register Field Descriptions .............................................................................
XINT_REGS Registers ...................................................................................................
XINT_REGS Access Type Codes ......................................................................................
XINT1CR Register Field Descriptions..................................................................................
XINT2CR Register Field Descriptions..................................................................................
XINT3CR Register Field Descriptions..................................................................................
XINT4CR Register Field Descriptions..................................................................................
XINT5CR Register Field Descriptions..................................................................................
XINT1CTR Register Field Descriptions ................................................................................
XINT2CTR Register Field Descriptions ................................................................................
XINT3CTR Register Field Descriptions ................................................................................
DMA_CLA_SRC_SEL_REGS Registers ..............................................................................
DMA_CLA_SRC_SEL_REGS Access Type Codes ..................................................................
CLA1TASKSRCSELLOCK Register Field Descriptions .............................................................
DMACHSRCSELLOCK Register Field Descriptions .................................................................
CLA1TASKSRCSEL1 Register Field Descriptions ...................................................................
CLA1TASKSRCSEL2 Register Field Descriptions ...................................................................
DMACHSRCSEL1 Register Field Descriptions .......................................................................
DMACHSRCSEL2 Register Field Descriptions .......................................................................
DEV_CFG_REGS Registers ............................................................................................
DEV_CFG_REGS Access Type Codes ...............................................................................
PARTIDL Register Field Descriptions ..................................................................................
PARTIDH Register Field Descriptions .................................................................................
REVID Register Field Descriptions .....................................................................................
DC0 Register Field Descriptions ........................................................................................
DC1 Register Field Descriptions ........................................................................................
DC2 Register Field Descriptions ........................................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
203
207
211
213
213
214
215
216
217
218
219
219
220
221
223
225
226
227
228
230
230
231
232
233
234
235
236
237
238
239
239
240
241
242
243
244
245
246
247
248
250
251
252
253
254
49
www.ti.com
3-95.
DC3 Register Field Descriptions ........................................................................................ 255
3-96.
DC4 Register Field Descriptions ........................................................................................ 257
3-97.
DC5 Register Field Descriptions ........................................................................................ 258
3-98.
DC6 Register Field Descriptions ........................................................................................ 259
3-99.
DC7 Register Field Descriptions ........................................................................................ 260
3-100. DC8 Register Field Descriptions ........................................................................................ 261
3-101. DC9 Register Field Descriptions ........................................................................................ 262
3-102. DC10 Register Field Descriptions ...................................................................................... 263
3-103. DC11 Register Field Descriptions ...................................................................................... 264
3-104. DC12 Register Field Descriptions ...................................................................................... 265
3-105. DC13 Register Field Descriptions ...................................................................................... 266
3-106. DC14 Register Field Descriptions ...................................................................................... 267
3-107. DC15 Register Field Descriptions ...................................................................................... 268
3-108. DC17 Register Field Descriptions ...................................................................................... 270
3-109. DC18 Register Field Descriptions ...................................................................................... 271
3-110. DC20 Register Field Descriptions ...................................................................................... 272
3-111. PERCNF1 Register Field Descriptions................................................................................. 274
3-112. FUSEERR Register Field Descriptions ................................................................................ 275
3-113. SOFTPRES0 Register Field Descriptions ............................................................................. 276
3-114. SOFTPRES1 Register Field Descriptions ............................................................................. 277
3-115. SOFTPRES2 Register Field Descriptions ............................................................................. 278
3-116. SOFTPRES3 Register Field Descriptions ............................................................................. 280
3-117. SOFTPRES4 Register Field Descriptions ............................................................................. 281
3-118. SOFTPRES6 Register Field Descriptions ............................................................................. 282
3-119. SOFTPRES7 Register Field Descriptions ............................................................................. 283
3-120. SOFTPRES8 Register Field Descriptions ............................................................................. 284
3-121. SOFTPRES9 Register Field Descriptions ............................................................................. 285
3-122. SOFTPRES11 Register Field Descriptions............................................................................ 286
3-123. SOFTPRES13 Register Field Descriptions............................................................................ 287
3-124. SOFTPRES14 Register Field Descriptions............................................................................ 288
3-125. SOFTPRES16 Register Field Descriptions............................................................................ 289
3-126. SYSDBGCTL Register Field Descriptions ............................................................................. 290
3-127. CLK_CFG_REGS Registers
............................................................................................
291
3-128. CLK_CFG_REGS Access Type Codes ................................................................................ 291
3-129. CLKCFGLOCK1 Register Field Descriptions ......................................................................... 293
3-130. CLKSRCCTL1 Register Field Descriptions............................................................................ 295
3-131. CLKSRCCTL2 Register Field Descriptions............................................................................ 297
3-132. CLKSRCCTL3 Register Field Descriptions............................................................................ 299
3-133. SYSPLLCTL1 Register Field Descriptions ............................................................................ 300
3-134. SYSPLLMULT Register Field Descriptions............................................................................ 301
3-135. SYSPLLSTS Register Field Descriptions .............................................................................. 302
3-136. AUXPLLCTL1 Register Field Descriptions ............................................................................ 303
3-137. AUXPLLMULT Register Field Descriptions
...........................................................................
304
3-138. AUXPLLSTS Register Field Descriptions.............................................................................. 305
3-139. SYSCLKDIVSEL Register Field Descriptions ......................................................................... 306
3-140. AUXCLKDIVSEL Register Field Descriptions ......................................................................... 307
3-141. PERCLKDIVSEL Register Field Descriptions ......................................................................... 308
3-142. XCLKOUTDIVSEL Register Field Descriptions ....................................................................... 309
3-143. LOSPCP Register Field Descriptions .................................................................................. 310
50
List of Tables
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
3-144. MCDCR Register Field Descriptions ................................................................................... 311
3-145. X1CNT Register Field Descriptions .................................................................................... 312
3-146. CPU_SYS_REGS Registers
............................................................................................
313
3-147. CPU_SYS_REGS Access Type Codes ................................................................................ 313
3-148. CPUSYSLOCK1 Register Field Descriptions ......................................................................... 315
3-149. HIBBOOTMODE Register Field Descriptions ......................................................................... 318
3-150. IORESTOREADDR Register Field Descriptions...................................................................... 319
3-151. PIEVERRADDR Register Field Descriptions .......................................................................... 320
3-152. PCLKCR0 Register Field Descriptions ................................................................................. 321
3-153. PCLKCR1 Register Field Descriptions ................................................................................. 323
3-154. PCLKCR2 Register Field Descriptions ................................................................................. 324
3-155. PCLKCR3 Register Field Descriptions ................................................................................. 326
3-156. PCLKCR4 Register Field Descriptions ................................................................................. 328
3-157. PCLKCR6 Register Field Descriptions ................................................................................. 329
3-158. PCLKCR7 Register Field Descriptions ................................................................................. 330
3-159. PCLKCR8 Register Field Descriptions ................................................................................. 331
3-160. PCLKCR9 Register Field Descriptions ................................................................................. 332
3-161. PCLKCR10 Register Field Descriptions ............................................................................... 333
3-162. PCLKCR11 Register Field Descriptions ............................................................................... 334
3-163. PCLKCR12 Register Field Descriptions ............................................................................... 335
3-164. PCLKCR13 Register Field Descriptions ............................................................................... 336
3-165. PCLKCR14 Register Field Descriptions ............................................................................... 337
3-166. PCLKCR16 Register Field Descriptions ............................................................................... 339
3-167. SECMSEL Register Field Descriptions ................................................................................ 340
3-168. LPMCR Register Field Descriptions .................................................................................... 341
3-169. GPIOLPMSEL0 Register Field Descriptions .......................................................................... 343
3-170. GPIOLPMSEL1 Register Field Descriptions .......................................................................... 346
3-171. TMR2CLKCTL Register Field Descriptions
...........................................................................
349
3-172. RESC Register Field Descriptions ...................................................................................... 351
3-173. ROM_PREFETCH_REGS Registers................................................................................... 353
3-174. ROM_PREFETCH_REGS Access Type Codes ...................................................................... 353
3-175. ROMPREFETCH Register Field Descriptions ........................................................................ 354
3-176. DCSM_COMMON_REGS Registers ................................................................................... 355
3-177. DCSM_COMMON_REGS Access Type Codes ...................................................................... 355
3-178. FLSEM Register Field Descriptions .................................................................................... 356
3-179. SECTSTAT Register Field Descriptions ............................................................................... 357
3-180. RAMSTAT Register Field Descriptions ................................................................................ 360
3-181. DCSM_Z1_OTP Registers
..............................................................................................
362
3-182. DCSM_Z1_OTP Access Type Codes .................................................................................. 362
...............................................................
...............................................................
Z1OTP_LINKPOINTER3 Register Field Descriptions ...............................................................
Z1OTP_PSWDLOCK Register Field Descriptions ...................................................................
Z1OTP_CRCLOCK Register Field Descriptions ......................................................................
Z1OTP_BOOTCTRL Register Field Descriptions ....................................................................
DCSM_Z1_REGS Registers ............................................................................................
DCSM_Z1_REGS Access Type Codes ................................................................................
Z1_LINKPOINTER Register Field Descriptions ......................................................................
Z1_OTPSECLOCK Register Field Descriptions ......................................................................
3-183. Z1OTP_LINKPOINTER1 Register Field Descriptions
363
3-184. Z1OTP_LINKPOINTER2 Register Field Descriptions
364
3-185.
365
3-186.
3-187.
3-188.
3-189.
3-190.
3-191.
3-192.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
366
367
368
369
369
370
371
51
www.ti.com
3-193. Z1_BOOTCTRL Register Field Descriptions .......................................................................... 372
3-194. Z1_LINKPOINTERERR Register Field Descriptions ................................................................. 373
3-195. Z1_CSMKEY0 Register Field Descriptions............................................................................ 374
3-196. Z1_CSMKEY1 Register Field Descriptions............................................................................ 375
3-197. Z1_CSMKEY2 Register Field Descriptions............................................................................ 376
3-198. Z1_CSMKEY3 Register Field Descriptions............................................................................ 377
3-199. Z1_CR Register Field Descriptions..................................................................................... 378
3-200. Z1_GRABSECTR Register Field Descriptions ........................................................................ 379
3-201. Z1_GRABRAMR Register Field Descriptions ......................................................................... 382
3-202. Z1_EXEONLYSECTR Register Field Descriptions................................................................... 384
3-203. Z1_EXEONLYRAMR Register Field Descriptions .................................................................... 387
3-204. DCSM_Z2_OTP Registers
..............................................................................................
389
3-205. DCSM_Z2_OTP Access Type Codes .................................................................................. 389
390
3-207.
391
3-208.
3-209.
3-210.
3-211.
3-212.
3-213.
3-214.
3-215.
3-216.
3-217.
3-218.
3-219.
3-220.
3-221.
3-222.
3-223.
3-224.
3-225.
3-226.
3-227.
3-228.
3-229.
3-230.
3-231.
3-232.
3-233.
3-234.
3-235.
3-236.
3-237.
3-238.
3-239.
3-240.
3-241.
52
...............................................................
Z2OTP_LINKPOINTER2 Register Field Descriptions ...............................................................
Z2OTP_LINKPOINTER3 Register Field Descriptions ...............................................................
Z2OTP_PSWDLOCK Register Field Descriptions ...................................................................
Z2OTP_CRCLOCK Register Field Descriptions ......................................................................
Z2OTP_BOOTCTRL Register Field Descriptions ....................................................................
DCSM_Z2_REGS Registers ............................................................................................
DCSM_Z2_REGS Access Type Codes ................................................................................
Z2_LINKPOINTER Register Field Descriptions ......................................................................
Z2_OTPSECLOCK Register Field Descriptions ......................................................................
Z2_BOOTCTRL Register Field Descriptions ..........................................................................
Z2_LINKPOINTERERR Register Field Descriptions .................................................................
Z2_CSMKEY0 Register Field Descriptions............................................................................
Z2_CSMKEY1 Register Field Descriptions............................................................................
Z2_CSMKEY2 Register Field Descriptions............................................................................
Z2_CSMKEY3 Register Field Descriptions............................................................................
Z2_CR Register Field Descriptions.....................................................................................
Z2_GRABSECTR Register Field Descriptions ........................................................................
Z2_GRABRAMR Register Field Descriptions .........................................................................
Z2_EXEONLYSECTR Register Field Descriptions...................................................................
Z2_EXEONLYRAMR Register Field Descriptions ....................................................................
MEM_CFG_REGS Registers ...........................................................................................
MEM_CFG_REGS Access Type Codes ...............................................................................
DxLOCK Register Field Descriptions ..................................................................................
DxCOMMIT Register Field Descriptions ...............................................................................
DxACCPROT0 Register Field Descriptions ...........................................................................
DxTEST Register Field Descriptions ...................................................................................
DxINIT Register Field Descriptions .....................................................................................
DxINITDONE Register Field Descriptions .............................................................................
LSxLOCK Register Field Descriptions .................................................................................
LSxCOMMIT Register Field Descriptions..............................................................................
LSxMSEL Register Field Descriptions .................................................................................
LSxCLAPGM Register Field Descriptions .............................................................................
LSxACCPROT0 Register Field Descriptions ..........................................................................
LSxACCPROT1 Register Field Descriptions ..........................................................................
LSxTEST Register Field Descriptions..................................................................................
3-206. Z2OTP_LINKPOINTER1 Register Field Descriptions
List of Tables
392
393
394
395
396
396
397
398
399
400
401
402
403
404
405
406
409
411
414
416
416
418
419
420
421
422
423
424
426
428
430
431
433
434
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
...................................................................................
LSxINITDONE Register Field Descriptions............................................................................
GSxLOCK Register Field Descriptions.................................................................................
GSxCOMMIT Register Field Descriptions .............................................................................
GSxACCPROT0 Register Field Descriptions .........................................................................
GSxACCPROT1 Register Field Descriptions .........................................................................
GSxACCPROT2 Register Field Descriptions .........................................................................
GSxACCPROT3 Register Field Descriptions .........................................................................
GSxTEST Register Field Descriptions .................................................................................
GSxINIT Register Field Descriptions ...................................................................................
GSxINITDONE Register Field Descriptions ...........................................................................
MSGxTEST Register Field Descriptions ...............................................................................
MSGxINIT Register Field Descriptions.................................................................................
MSGxINITDONE Register Field Descriptions .........................................................................
ACCESS_PROTECTION_REGS Registers ...........................................................................
ACCESS_PROTECTION_REGS Access Type Codes ..............................................................
NMAVFLG Register Field Descriptions ................................................................................
NMAVSET Register Field Descriptions ................................................................................
NMAVCLR Register Field Descriptions ................................................................................
NMAVINTEN Register Field Descriptions .............................................................................
NMCPURDAVADDR Register Field Descriptions ....................................................................
NMCPUWRAVADDR Register Field Descriptions ...................................................................
NMCPUFAVADDR Register Field Descriptions ......................................................................
NMDMAWRAVADDR Register Field Descriptions ...................................................................
NMCLA1RDAVADDR Register Field Descriptions ...................................................................
NMCLA1WRAVADDR Register Field Descriptions ..................................................................
NMCLA1FAVADDR Register Field Descriptions .....................................................................
MAVFLG Register Field Descriptions ..................................................................................
MAVSET Register Field Descriptions ..................................................................................
MAVCLR Register Field Descriptions ..................................................................................
MAVINTEN Register Field Descriptions ...............................................................................
MCPUFAVADDR Register Field Descriptions ........................................................................
MCPUWRAVADDR Register Field Descriptions .....................................................................
MDMAWRAVADDR Register Field Descriptions .....................................................................
MEMORY_ERROR_REGS Registers..................................................................................
MEMORY_ERROR_REGS Access Type Codes .....................................................................
UCERRFLG Register Field Descriptions ..............................................................................
UCERRSET Register Field Descriptions ..............................................................................
UCERRCLR Register Field Descriptions ..............................................................................
UCCPUREADDR Register Field Descriptions ........................................................................
UCDMAREADDR Register Field Descriptions ........................................................................
UCCLA1READDR Register Field Descriptions .......................................................................
CERRFLG Register Field Descriptions ................................................................................
CERRSET Register Field Descriptions ................................................................................
CERRCLR Register Field Descriptions ................................................................................
CCPUREADDR Register Field Descriptions ..........................................................................
CERRCNT Register Field Descriptions ................................................................................
CERRTHRES Register Field Descriptions ............................................................................
CEINTFLG Register Field Descriptions ................................................................................
3-242. LSxINIT Register Field Descriptions
436
3-243.
437
3-244.
3-245.
3-246.
3-247.
3-248.
3-249.
3-250.
3-251.
3-252.
3-253.
3-254.
3-255.
3-256.
3-257.
3-258.
3-259.
3-260.
3-261.
3-262.
3-263.
3-264.
3-265.
3-266.
3-267.
3-268.
3-269.
3-270.
3-271.
3-272.
3-273.
3-274.
3-275.
3-276.
3-277.
3-278.
3-279.
3-280.
3-281.
3-282.
3-283.
3-284.
3-285.
3-286.
3-287.
3-288.
3-289.
3-290.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
438
441
444
446
448
450
452
455
457
459
460
461
462
462
464
466
468
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
485
486
487
488
489
490
491
492
493
494
495
496
497
498
53
www.ti.com
3-291. CEINTCLR Register Field Descriptions ................................................................................ 499
3-292. CEINTSET Register Field Descriptions ................................................................................ 500
3-293. CEINTEN Register Field Descriptions ................................................................................. 501
3-294. ROM_WAIT_STATE_REGS Registers ................................................................................ 502
502
3-296. ROMWAITSTATE Register Field Descriptions
503
3-297.
504
3-298.
3-299.
3-300.
3-301.
3-302.
3-303.
3-304.
3-305.
3-306.
3-307.
3-308.
3-309.
3-310.
3-311.
3-312.
3-313.
3-314.
3-315.
3-316.
3-317.
3-318.
3-319.
3-320.
3-321.
3-322.
3-323.
3-324.
3-325.
3-326.
3-327.
3-328.
3-329.
3-330.
3-331.
3-332.
3-333.
3-334.
3-335.
3-336.
3-337.
3-338.
3-339.
54
...................................................................
.......................................................................
FLASH_CTRL_REGS Registers ........................................................................................
FLASH_CTRL_REGS Access Type Codes ...........................................................................
FRDCNTL Register Field Descriptions.................................................................................
FBAC Register Field Descriptions ......................................................................................
FBFALLBACK Register Field Descriptions ............................................................................
FBPRDY Register Field Descriptions ..................................................................................
FPAC1 Register Field Descriptions ....................................................................................
FMSTAT Register Field Descriptions ..................................................................................
FRD_INTF_CTRL Register Field Descriptions........................................................................
FLASH_ECC_REGS Registers .........................................................................................
FLASH_ECC_REGS Access Type Codes ............................................................................
ECC_ENABLE Register Field Descriptions ...........................................................................
SINGLE_ERR_ADDR_LOW Register Field Descriptions ...........................................................
SINGLE_ERR_ADDR_HIGH Register Field Descriptions ...........................................................
UNC_ERR_ADDR_LOW Register Field Descriptions ...............................................................
UNC_ERR_ADDR_HIGH Register Field Descriptions ...............................................................
ERR_STATUS Register Field Descriptions ...........................................................................
ERR_POS Register Field Descriptions ................................................................................
ERR_STATUS_CLR Register Field Descriptions ....................................................................
ERR_CNT Register Field Descriptions ................................................................................
ERR_THRESHOLD Register Field Descriptions .....................................................................
ERR_INTFLG Register Field Descriptions ............................................................................
ERR_INTCLR Register Field Descriptions ............................................................................
FDATAH_TEST Register Field Descriptions ..........................................................................
FDATAL_TEST Register Field Descriptions ..........................................................................
FADDR_TEST Register Field Descriptions ...........................................................................
FECC_TEST Register Field Descriptions .............................................................................
FECC_CTRL Register Field Descriptions .............................................................................
FOUTH_TEST Register Field Descriptions ...........................................................................
FOUTL_TEST Register Field Descriptions ............................................................................
FECC_STATUS Register Field Descriptions ..........................................................................
UID_REGS Registers ....................................................................................................
UID_REGS Access Type Codes........................................................................................
UID_PSRAND0 Register Field Descriptions ..........................................................................
UID_PSRAND1 Register Field Descriptions ..........................................................................
UID_PSRAND2 Register Field Descriptions ..........................................................................
UID_PSRAND3 Register Field Descriptions ..........................................................................
UID_PSRAND4 Register Field Descriptions ..........................................................................
UID_PSRAND5 Register Field Descriptions ..........................................................................
UID_UNIQUE Register Field Descriptions ............................................................................
UID_CHECKSUM Register Field Descriptions........................................................................
CPUTIMER Registers to Driverlib Functions ..........................................................................
ASYSCTL Registers to Driverlib Functions............................................................................
3-295. ROM_WAIT_STATE_REGS Access Type Codes
List of Tables
504
505
506
507
508
509
510
512
513
513
515
516
517
518
519
520
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
536
537
538
539
540
541
542
543
544
545
545
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
...................................................................................
SYSCTL Registers to Driverlib Functions .............................................................................
NMI Registers to Driverlib Functions ...................................................................................
XINT Registers to Driverlib Functions ..................................................................................
DCSM Registers to Driverlib Functions ................................................................................
MEMCFG Registers to Driverlib Functions ............................................................................
ROM Memory .............................................................................................................
Boot ROM Registers .....................................................................................................
Boot ROM Sequence .....................................................................................................
Device Default Boot Modes .............................................................................................
BOOTCTRL Register Bit Fields .........................................................................................
Get Mode Decoding ......................................................................................................
Boot ROM Reset Causes and Actions .................................................................................
Boot ROM Exceptions and Actions .....................................................................................
Entry Point Addresses ...................................................................................................
Wait Point Addresses for CPU1 ........................................................................................
Boot ROM Memory Map .................................................................................................
CLA Data ROM Memory Map ...........................................................................................
Reserved RAM and Flash Memory Map ...............................................................................
CLA Data ROM Tables...................................................................................................
SPI 8-Bit Data Stream ...................................................................................................
I2C 8-Bit Data Stream ...................................................................................................
Parallel GPIO Boot 8-Bit Data Stream .................................................................................
Bit-Rate Value for Internal Oscillators ..................................................................................
CAN 8-Bit Data Stream ..................................................................................................
USB 8-Bit Data Stream ..................................................................................................
LSB/MSB Loading Sequence in 8-Bit Data Stream ..................................................................
SCI Boot Options .........................................................................................................
CAN Boot Options ........................................................................................................
I2C Boot Options ..........................................................................................................
USB Boot Options ........................................................................................................
RAM Boot Options ........................................................................................................
Flash Boot Options .......................................................................................................
Wait Boot Options ........................................................................................................
SPI Boot Options .........................................................................................................
Parallel Boot Options .....................................................................................................
Safe Copy Code Function ...............................................................................................
Safe CRC Calculation Function .........................................................................................
Boot Clock Sources ......................................................................................................
Clock State After Boot ROM ............................................................................................
ROM Wait States .........................................................................................................
CPU1 Boot Status Address..............................................................................................
CPU1 Boot Status Bit Fields ............................................................................................
Boot ROM Version Information .........................................................................................
DMA Trigger Source Options ...........................................................................................
BURSTSIZE vs DATASIZE Behavior ..................................................................................
DMA Base Address Table ...............................................................................................
DMA_REGS Registers ...................................................................................................
DMA_REGS Access Type Codes ......................................................................................
3-340. PIE Registers to Driverlib Functions
545
3-341.
547
3-342.
3-343.
3-344.
3-345.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
4-11.
4-12.
4-13.
4-14.
4-15.
4-16.
4-17.
4-18.
4-19.
4-20.
4-21.
4-22.
4-23.
4-24.
4-25.
4-26.
4-27.
4-28.
4-29.
4-30.
4-31.
4-32.
4-33.
4-34.
4-35.
4-36.
4-37.
4-38.
5-1.
5-2.
5-3.
5-4.
5-5.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
551
552
552
553
558
558
558
560
560
561
565
566
566
567
567
567
568
568
572
575
576
580
580
581
583
584
585
585
585
585
585
585
585
585
586
586
587
587
587
588
588
588
594
599
606
607
607
55
www.ti.com
5-6.
DMACTRL Register Field Descriptions ................................................................................ 608
5-7.
DEBUGCTRL Register Field Descriptions
5-8.
PRIORITYCTRL1 Register Field Descriptions ........................................................................ 610
5-9.
PRIORITYSTAT Register Field Descriptions
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
5-19.
5-20.
5-21.
5-22.
5-23.
5-24.
5-25.
5-26.
5-27.
5-28.
5-29.
5-30.
5-31.
5-32.
5-33.
5-34.
5-35.
5-36.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
6-8.
6-9.
6-10.
6-11.
6-12.
6-13.
6-14.
6-15.
6-16.
6-17.
6-18.
56
............................................................................
.........................................................................
DMA_CH_REGS Registers..............................................................................................
DMA_CH_REGS Access Type Codes .................................................................................
MODE Register Field Descriptions .....................................................................................
CONTROL Register Field Descriptions ................................................................................
BURST_SIZE Register Field Descriptions ............................................................................
BURST_COUNT Register Field Descriptions .........................................................................
SRC_BURST_STEP Register Field Descriptions ....................................................................
DST_BURST_STEP Register Field Descriptions.....................................................................
TRANSFER_SIZE Register Field Descriptions .......................................................................
TRANSFER_COUNT Register Field Descriptions ...................................................................
SRC_TRANSFER_STEP Register Field Descriptions ...............................................................
DST_TRANSFER_STEP Register Field Descriptions ...............................................................
SRC_WRAP_SIZE Register Field Descriptions ......................................................................
SRC_WRAP_COUNT Register Field Descriptions ...................................................................
SRC_WRAP_STEP Register Field Descriptions .....................................................................
DST_WRAP_SIZE Register Field Descriptions .......................................................................
DST_WRAP_COUNT Register Field Descriptions ...................................................................
DST_WRAP_STEP Register Field Descriptions......................................................................
SRC_BEG_ADDR_SHADOW Register Field Descriptions .........................................................
SRC_ADDR_SHADOW Register Field Descriptions .................................................................
SRC_BEG_ADDR_ACTIVE Register Field Descriptions ............................................................
SRC_ADDR_ACTIVE Register Field Descriptions ...................................................................
DST_BEG_ADDR_SHADOW Register Field Descriptions ..........................................................
DST_ADDR_SHADOW Register Field Descriptions .................................................................
DST_BEG_ADDR_ACTIVE Register Field Descriptions ............................................................
DST_ADDR_ACTIVE Register Field Descriptions ...................................................................
DMA Registers to Driverlib Functions ..................................................................................
Configuration Options ....................................................................................................
Write Followed by Read - Read Occurs First ........................................................................
Write Followed by Read - Write Occurs First ........................................................................
ADC to CLA Early Interrupt Response ................................................................................
Operand Nomenclature ..................................................................................................
INSTRUCTION dest, source1, source2 Short Description ..........................................................
Addressing Modes ........................................................................................................
Shift Field Encoding ......................................................................................................
Operand Encoding ........................................................................................................
Condition Field Encoding ................................................................................................
General Instructions ......................................................................................................
Pipeline Activity For MBCNDD, Branch Not Taken ..................................................................
Pipeline Activity For MBCNDD, Branch Taken .......................................................................
Pipeline Activity For MCCNDD, Call Not Taken .....................................................................
Pipeline Activity For MCCNDD, Call Taken ..........................................................................
Pipeline Activity For MMOV16 MARx, MRa , #16I ...................................................................
Pipeline Activity For MMOV16 MAR0/MAR1, mem16 ...............................................................
Pipeline Activity For MMOVI16 MAR0/MAR1, #16I ..................................................................
List of Tables
609
611
612
612
614
616
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
648
657
657
659
661
662
663
664
664
664
665
680
680
686
686
718
721
735
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
6-19.
6-20.
6-21.
6-22.
6-23.
6-24.
6-25.
6-26.
6-27.
6-28.
6-29.
6-30.
6-31.
6-32.
6-33.
6-34.
6-35.
6-36.
6-37.
6-38.
6-39.
6-40.
6-41.
6-42.
6-43.
6-44.
6-45.
6-46.
6-47.
6-48.
6-49.
6-50.
6-51.
6-52.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
..................................................................
Pipeline Activity For MRCNDD, Return Taken .......................................................................
Pipeline Activity For MSTOP ............................................................................................
CLA Base Address Table ................................................................................................
CLA_REGS Registers ....................................................................................................
CLA_REGS Access Type Codes .......................................................................................
MVECT1 Register Field Descriptions ..................................................................................
MVECT2 Register Field Descriptions ..................................................................................
MVECT3 Register Field Descriptions ..................................................................................
MVECT4 Register Field Descriptions ..................................................................................
MVECT5 Register Field Descriptions ..................................................................................
MVECT6 Register Field Descriptions ..................................................................................
MVECT7 Register Field Descriptions ..................................................................................
MVECT8 Register Field Descriptions ..................................................................................
MCTL Register Field Descriptions ......................................................................................
MIFR Register Field Descriptions.......................................................................................
MIOVF Register Field Descriptions.....................................................................................
MIFRC Register Field Descriptions.....................................................................................
MICLR Register Field Descriptions .....................................................................................
MICLROVF Register Field Descriptions ...............................................................................
MIER Register Field Descriptions ......................................................................................
MIRUN Register Field Descriptions ....................................................................................
_MPC Register Field Descriptions ......................................................................................
_MAR0 Register Field Descriptions ....................................................................................
_MAR1 Register Field Descriptions ....................................................................................
_MSTF Register Field Descriptions ....................................................................................
_MR0 Register Field Descriptions ......................................................................................
_MR1 Register Field Descriptions ......................................................................................
_MR2 Register Field Descriptions ......................................................................................
_MR3 Register Field Descriptions ......................................................................................
CLA_SOFTINT_REGS Registers .......................................................................................
CLA_SOFTINT_REGS Access Type Codes ..........................................................................
SOFTINTEN Register Field Descriptions ..............................................................................
SOFTINTFRC Register Field Descriptions ............................................................................
Sampling Period ..........................................................................................................
Sampling Frequency .....................................................................................................
Case 1: Three-Sample Sampling Window Width .....................................................................
Case 2: Six-Sample Sampling Window Width ........................................................................
USB I/O Signal Muxing ..................................................................................................
GPIO Configuration for High-Speed SPI ..............................................................................
GPIO Muxed Pins.........................................................................................................
GPIO and Peripheral Muxing ............................................................................................
Peripheral Muxing (multiple pins assigned) ...........................................................................
Specific vs Generic Termilogy for Registers ..........................................................................
GPIO Base Address Table ..............................................................................................
GPIO_CTRL_REGS Registers ..........................................................................................
GPIO_CTRL_REGS Access Type Codes .............................................................................
GPACTRL Register Field Descriptions ................................................................................
GPAQSEL1 Register Field Descriptions ...............................................................................
Pipeline Activity For MRCNDD, Return Not Taken
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
757
757
761
776
777
777
779
780
781
782
783
784
785
786
787
788
793
796
798
800
802
805
808
809
810
811
814
815
816
817
818
818
819
821
827
827
828
828
829
829
830
834
835
836
836
837
839
841
842
57
www.ti.com
7-16.
GPAQSEL2 Register Field Descriptions ............................................................................... 844
7-17.
GPAMUX1 Register Field Descriptions ................................................................................ 846
7-18.
GPAMUX2 Register Field Descriptions ................................................................................ 848
7-19.
GPADIR Register Field Descriptions ................................................................................... 850
7-20.
GPAPUD Register Field Descriptions .................................................................................. 852
7-21.
GPAINV Register Field Descriptions ................................................................................... 854
7-22.
GPAODR Register Field Descriptions
7-23.
GPAGMUX1 Register Field Descriptions .............................................................................. 858
7-24.
GPAGMUX2 Register Field Descriptions .............................................................................. 859
7-25.
GPACSEL1 Register Field Descriptions ............................................................................... 860
7-26.
GPACSEL2 Register Field Descriptions ............................................................................... 861
7-27.
GPACSEL3 Register Field Descriptions ............................................................................... 862
7-28.
GPACSEL4 Register Field Descriptions ............................................................................... 863
7-29.
GPALOCK Register Field Descriptions ................................................................................ 864
7-30.
GPACR Register Field Descriptions.................................................................................... 866
7-31.
GPBCTRL Register Field Descriptions
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
7-39.
7-40.
7-41.
7-42.
7-43.
7-44.
7-45.
7-46.
7-47.
7-48.
7-49.
7-50.
7-51.
7-52.
7-53.
7-54.
7-55.
7-56.
7-57.
7-58.
7-59.
7-60.
7-61.
7-62.
7-63.
7-64.
58
.................................................................................
................................................................................
GPBQSEL1 Register Field Descriptions ...............................................................................
GPBQSEL2 Register Field Descriptions ...............................................................................
GPBMUX1 Register Field Descriptions ................................................................................
GPBMUX2 Register Field Descriptions ................................................................................
GPBDIR Register Field Descriptions ...................................................................................
GPBPUD Register Field Descriptions ..................................................................................
GPBINV Register Field Descriptions ...................................................................................
GPBODR Register Field Descriptions .................................................................................
GPBAMSEL Register Field Descriptions ..............................................................................
GPBGMUX1 Register Field Descriptions ..............................................................................
GPBGMUX2 Register Field Descriptions ..............................................................................
GPBCSEL1 Register Field Descriptions ...............................................................................
GPBCSEL2 Register Field Descriptions ...............................................................................
GPBCSEL3 Register Field Descriptions ...............................................................................
GPBCSEL4 Register Field Descriptions ...............................................................................
GPBLOCK Register Field Descriptions ................................................................................
GPBCR Register Field Descriptions....................................................................................
GPCCTRL Register Field Descriptions ................................................................................
GPCQSEL1 Register Field Descriptions...............................................................................
GPCQSEL2 Register Field Descriptions...............................................................................
GPCMUX1 Register Field Descriptions ................................................................................
GPCMUX2 Register Field Descriptions ................................................................................
GPCDIR Register Field Descriptions ...................................................................................
GPCPUD Register Field Descriptions..................................................................................
GPCINV Register Field Descriptions ...................................................................................
GPCODR Register Field Descriptions .................................................................................
GPCGMUX1 Register Field Descriptions ..............................................................................
GPCGMUX2 Register Field Descriptions ..............................................................................
GPCCSEL1 Register Field Descriptions ...............................................................................
GPCCSEL2 Register Field Descriptions ...............................................................................
GPCCSEL3 Register Field Descriptions ...............................................................................
GPCCSEL4 Register Field Descriptions ...............................................................................
GPCLOCK Register Field Descriptions ................................................................................
List of Tables
856
868
869
871
873
875
877
879
881
883
885
887
888
889
890
891
892
893
895
897
898
900
902
904
906
908
910
912
914
915
916
917
918
919
920
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
7-65.
7-66.
7-67.
7-68.
7-69.
7-70.
7-71.
7-72.
7-73.
7-74.
7-75.
7-76.
7-77.
7-78.
7-79.
7-80.
7-81.
7-82.
7-83.
7-84.
7-85.
7-86.
7-87.
7-88.
7-89.
7-90.
7-91.
7-92.
7-93.
7-94.
7-95.
7-96.
7-97.
7-98.
7-99.
7-100.
7-101.
7-102.
7-103.
7-104.
7-105.
7-106.
7-107.
7-108.
7-109.
7-110.
7-111.
7-112.
7-113.
................................................................................... 922
GPDCTRL Register Field Descriptions ................................................................................ 924
GPDQSEL1 Register Field Descriptions............................................................................... 925
GPDQSEL2 Register Field Descriptions............................................................................... 927
GPDMUX1 Register Field Descriptions ................................................................................ 929
GPDMUX2 Register Field Descriptions ................................................................................ 931
GPDDIR Register Field Descriptions ................................................................................... 933
GPDPUD Register Field Descriptions.................................................................................. 935
GPDINV Register Field Descriptions ................................................................................... 937
GPDODR Register Field Descriptions ................................................................................. 939
GPDGMUX1 Register Field Descriptions .............................................................................. 941
GPDGMUX2 Register Field Descriptions .............................................................................. 943
GPDCSEL1 Register Field Descriptions ............................................................................... 945
GPDCSEL2 Register Field Descriptions ............................................................................... 946
GPDCSEL3 Register Field Descriptions ............................................................................... 947
GPDCSEL4 Register Field Descriptions ............................................................................... 948
GPDLOCK Register Field Descriptions ................................................................................ 949
GPDCR Register Field Descriptions ................................................................................... 951
GPECTRL Register Field Descriptions ................................................................................ 953
GPEQSEL1 Register Field Descriptions ............................................................................... 954
GPEQSEL2 Register Field Descriptions ............................................................................... 956
GPEMUX1 Register Field Descriptions ................................................................................ 958
GPEMUX2 Register Field Descriptions ................................................................................ 960
GPEDIR Register Field Descriptions ................................................................................... 962
GPEPUD Register Field Descriptions .................................................................................. 964
GPEINV Register Field Descriptions ................................................................................... 966
GPEODR Register Field Descriptions ................................................................................. 968
GPEGMUX1 Register Field Descriptions .............................................................................. 970
GPEGMUX2 Register Field Descriptions .............................................................................. 972
GPECSEL1 Register Field Descriptions ............................................................................... 974
GPECSEL2 Register Field Descriptions ............................................................................... 975
GPECSEL3 Register Field Descriptions ............................................................................... 976
GPECSEL4 Register Field Descriptions ............................................................................... 977
GPELOCK Register Field Descriptions ................................................................................ 978
GPECR Register Field Descriptions.................................................................................... 980
GPFCTRL Register Field Descriptions................................................................................. 982
GPFQSEL1 Register Field Descriptions ............................................................................... 983
GPFMUX1 Register Field Descriptions ................................................................................ 985
GPFDIR Register Field Descriptions ................................................................................... 987
GPFPUD Register Field Descriptions .................................................................................. 989
GPFINV Register Field Descriptions ................................................................................... 991
GPFODR Register Field Descriptions.................................................................................. 993
GPFGMUX1 Register Field Descriptions .............................................................................. 995
GPFCSEL1 Register Field Descriptions ............................................................................... 996
GPFCSEL2 Register Field Descriptions ............................................................................... 997
GPFLOCK Register Field Descriptions ................................................................................ 998
GPFCR Register Field Descriptions .................................................................................. 1000
GPIO_DATA_REGS Registers ........................................................................................ 1002
GPIO_DATA_REGS Access Type Codes ........................................................................... 1002
GPCCR Register Field Descriptions
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
59
www.ti.com
7-114. GPADAT Register Field Descriptions................................................................................. 1004
7-115. GPASET Register Field Descriptions ................................................................................. 1006
7-116. GPACLEAR Register Field Descriptions ............................................................................. 1008
7-117. GPATOGGLE Register Field Descriptions ........................................................................... 1010
7-118. GPBDAT Register Field Descriptions................................................................................. 1012
7-119. GPBSET Register Field Descriptions ................................................................................. 1014
7-120. GPBCLEAR Register Field Descriptions ............................................................................. 1016
7-121. GPBTOGGLE Register Field Descriptions ........................................................................... 1018
................................................................................
GPCSET Register Field Descriptions.................................................................................
GPCCLEAR Register Field Descriptions .............................................................................
GPCTOGGLE Register Field Descriptions...........................................................................
GPDDAT Register Field Descriptions ................................................................................
GPDSET Register Field Descriptions.................................................................................
GPDCLEAR Register Field Descriptions .............................................................................
GPDTOGGLE Register Field Descriptions...........................................................................
GPEDAT Register Field Descriptions.................................................................................
GPESET Register Field Descriptions .................................................................................
GPECLEAR Register Field Descriptions .............................................................................
GPETOGGLE Register Field Descriptions ...........................................................................
GPFDAT Register Field Descriptions .................................................................................
GPFSET Register Field Descriptions .................................................................................
GPFCLEAR Register Field Descriptions .............................................................................
GPFTOGGLE Register Field Descriptions ...........................................................................
GPIO Registers to Driverlib Functions................................................................................
Input X-BAR Destinations ..............................................................................................
ePWM X-BAR Mux Configuration Table ............................................................................
CLB X-BAR Mux Configuration Table ................................................................................
Output X-BAR Mux Configuration Table .............................................................................
X-BAR Base Address Table ...........................................................................................
XBAR_REGS Registers ................................................................................................
XBAR_REGS Access Type Codes ...................................................................................
XBARFLG1 Register Field Descriptions..............................................................................
XBARFLG2 Register Field Descriptions..............................................................................
XBARFLG3 Register Field Descriptions..............................................................................
XBARCLR1 Register Field Descriptions .............................................................................
XBARCLR2 Register Field Descriptions .............................................................................
XBARCLR3 Register Field Descriptions .............................................................................
INPUT_XBAR_REGS Registers ......................................................................................
INPUT_XBAR_REGS Access Type Codes ..........................................................................
INPUT1SELECT Register Field Descriptions........................................................................
INPUT2SELECT Register Field Descriptions........................................................................
INPUT3SELECT Register Field Descriptions........................................................................
INPUT4SELECT Register Field Descriptions........................................................................
INPUT5SELECT Register Field Descriptions........................................................................
INPUT6SELECT Register Field Descriptions........................................................................
INPUT7SELECT Register Field Descriptions........................................................................
INPUT8SELECT Register Field Descriptions........................................................................
INPUT9SELECT Register Field Descriptions........................................................................
7-122. GPCDAT Register Field Descriptions
7-123.
7-124.
7-125.
7-126.
7-127.
7-128.
7-129.
7-130.
7-131.
7-132.
7-133.
7-134.
7-135.
7-136.
7-137.
7-138.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
8-20.
8-21.
8-22.
8-23.
8-24.
60
List of Tables
1020
1022
1024
1026
1028
1030
1032
1034
1036
1038
1040
1042
1044
1046
1048
1050
1052
1060
1062
1063
1066
1068
1069
1069
1070
1072
1074
1076
1078
1080
1082
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
8-25.
INPUT10SELECT Register Field Descriptions ...................................................................... 1092
8-26.
INPUT11SELECT Register Field Descriptions ...................................................................... 1093
8-27.
INPUT12SELECT Register Field Descriptions ...................................................................... 1094
8-28.
INPUT13SELECT Register Field Descriptions ...................................................................... 1095
8-29.
INPUT14SELECT Register Field Descriptions ...................................................................... 1096
8-30.
INPUTSELECTLOCK Register Field Descriptions .................................................................. 1097
8-31.
OUTPUT_XBAR_REGS Registers
8-32.
OUTPUT_XBAR_REGS Access Type Codes ....................................................................... 1099
8-33.
OUTPUT1MUX0TO15CFG Register Field Descriptions ........................................................... 1101
8-34.
OUTPUT1MUX16TO31CFG Register Field Descriptions.......................................................... 1104
8-35.
OUTPUT2MUX0TO15CFG Register Field Descriptions ........................................................... 1107
8-36.
OUTPUT2MUX16TO31CFG Register Field Descriptions.......................................................... 1110
8-37.
OUTPUT3MUX0TO15CFG Register Field Descriptions ........................................................... 1113
8-38.
OUTPUT3MUX16TO31CFG Register Field Descriptions.......................................................... 1116
8-39.
OUTPUT4MUX0TO15CFG Register Field Descriptions ........................................................... 1119
8-40.
OUTPUT4MUX16TO31CFG Register Field Descriptions.......................................................... 1122
8-41.
OUTPUT5MUX0TO15CFG Register Field Descriptions ........................................................... 1125
8-42.
OUTPUT5MUX16TO31CFG Register Field Descriptions.......................................................... 1128
8-43.
OUTPUT6MUX0TO15CFG Register Field Descriptions ........................................................... 1131
8-44.
OUTPUT6MUX16TO31CFG Register Field Descriptions.......................................................... 1134
8-45.
OUTPUT7MUX0TO15CFG Register Field Descriptions ........................................................... 1137
8-46.
OUTPUT7MUX16TO31CFG Register Field Descriptions.......................................................... 1140
8-47.
OUTPUT8MUX0TO15CFG Register Field Descriptions ........................................................... 1143
8-48.
OUTPUT8MUX16TO31CFG Register Field Descriptions.......................................................... 1146
8-49.
OUTPUT1MUXENABLE Register Field Descriptions
1149
8-50.
OUTPUT2MUXENABLE Register Field Descriptions
1154
8-51.
8-52.
8-53.
8-54.
8-55.
8-56.
8-57.
8-58.
8-59.
8-60.
8-61.
8-62.
8-63.
8-64.
8-65.
8-66.
8-67.
8-68.
8-69.
8-70.
8-71.
8-72.
8-73.
...................................................................................
..............................................................
..............................................................
OUTPUT3MUXENABLE Register Field Descriptions ..............................................................
OUTPUT4MUXENABLE Register Field Descriptions ..............................................................
OUTPUT5MUXENABLE Register Field Descriptions ..............................................................
OUTPUT6MUXENABLE Register Field Descriptions ..............................................................
OUTPUT7MUXENABLE Register Field Descriptions ..............................................................
OUTPUT8MUXENABLE Register Field Descriptions ..............................................................
OUTPUTLATCH Register Field Descriptions ........................................................................
OUTPUTLATCHCLR Register Field Descriptions ..................................................................
OUTPUTLATCHFRC Register Field Descriptions ..................................................................
OUTPUTLATCHENABLE Register Field Descriptions .............................................................
OUTPUTINV Register Field Descriptions ............................................................................
OUTPUTLOCK Register Field Descriptions .........................................................................
EPWM_XBAR_REGS Registers ......................................................................................
EPWM_XBAR_REGS Access Type Codes .........................................................................
TRIP4MUX0TO15CFG Register Field Descriptions ................................................................
TRIP4MUX16TO31CFG Register Field Descriptions...............................................................
TRIP5MUX0TO15CFG Register Field Descriptions ................................................................
TRIP5MUX16TO31CFG Register Field Descriptions...............................................................
TRIP7MUX0TO15CFG Register Field Descriptions ................................................................
TRIP7MUX16TO31CFG Register Field Descriptions...............................................................
TRIP8MUX0TO15CFG Register Field Descriptions ................................................................
TRIP8MUX16TO31CFG Register Field Descriptions...............................................................
TRIP9MUX0TO15CFG Register Field Descriptions ................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
1099
1159
1164
1169
1174
1179
1184
1189
1191
1193
1195
1197
1199
1200
1200
1202
1205
1208
1211
1214
1217
1220
1223
1226
61
www.ti.com
8-74.
TRIP9MUX16TO31CFG Register Field Descriptions............................................................... 1229
8-75.
TRIP10MUX0TO15CFG Register Field Descriptions............................................................... 1232
8-76.
TRIP10MUX16TO31CFG Register Field Descriptions ............................................................. 1235
8-77.
TRIP11MUX0TO15CFG Register Field Descriptions............................................................... 1238
8-78.
TRIP11MUX16TO31CFG Register Field Descriptions ............................................................. 1241
8-79.
TRIP12MUX0TO15CFG Register Field Descriptions............................................................... 1244
8-80.
TRIP12MUX16TO31CFG Register Field Descriptions ............................................................. 1247
8-81.
TRIP4MUXENABLE Register Field Descriptions ................................................................... 1250
8-82.
TRIP5MUXENABLE Register Field Descriptions ................................................................... 1255
8-83.
TRIP7MUXENABLE Register Field Descriptions ................................................................... 1260
8-84.
TRIP8MUXENABLE Register Field Descriptions ................................................................... 1265
8-85.
TRIP9MUXENABLE Register Field Descriptions ................................................................... 1270
8-86.
TRIP10MUXENABLE Register Field Descriptions .................................................................. 1275
8-87.
TRIP11MUXENABLE Register Field Descriptions .................................................................. 1280
8-88.
TRIP12MUXENABLE Register Field Descriptions .................................................................. 1285
8-89.
TRIPOUTINV Register Field Descriptions ........................................................................... 1290
8-90.
TRIPLOCK Register Field Descriptions .............................................................................. 1292
8-91.
CLB_XBAR_REGS Registers
8-92.
CLB_XBAR_REGS Access Type Codes ............................................................................. 1293
8-93.
AUXSIG0MUX0TO15CFG Register Field Descriptions ............................................................ 1295
8-94.
AUXSIG0MUX16TO31CFG Register Field Descriptions
8-95.
8-96.
8-97.
8-98.
8-99.
8-100.
8-101.
8-102.
8-103.
8-104.
8-105.
8-106.
8-107.
8-108.
8-109.
8-110.
8-111.
8-112.
8-113.
8-114.
8-115.
8-116.
8-117.
8-118.
8-119.
8-120.
8-121.
8-122.
62
.........................................................................................
..........................................................
AUXSIG1MUX0TO15CFG Register Field Descriptions ............................................................
AUXSIG1MUX16TO31CFG Register Field Descriptions ..........................................................
AUXSIG2MUX0TO15CFG Register Field Descriptions ............................................................
AUXSIG2MUX16TO31CFG Register Field Descriptions ..........................................................
AUXSIG3MUX0TO15CFG Register Field Descriptions ............................................................
AUXSIG3MUX16TO31CFG Register Field Descriptions ..........................................................
AUXSIG4MUX0TO15CFG Register Field Descriptions ............................................................
AUXSIG4MUX16TO31CFG Register Field Descriptions ..........................................................
AUXSIG5MUX0TO15CFG Register Field Descriptions ............................................................
AUXSIG5MUX16TO31CFG Register Field Descriptions ..........................................................
AUXSIG6MUX0TO15CFG Register Field Descriptions ............................................................
AUXSIG6MUX16TO31CFG Register Field Descriptions ..........................................................
AUXSIG7MUX0TO15CFG Register Field Descriptions ............................................................
AUXSIG7MUX16TO31CFG Register Field Descriptions ..........................................................
AUXSIG0MUXENABLE Register Field Descriptions ...............................................................
AUXSIG1MUXENABLE Register Field Descriptions ...............................................................
AUXSIG2MUXENABLE Register Field Descriptions ...............................................................
AUXSIG3MUXENABLE Register Field Descriptions ...............................................................
AUXSIG4MUXENABLE Register Field Descriptions ...............................................................
AUXSIG5MUXENABLE Register Field Descriptions ...............................................................
AUXSIG6MUXENABLE Register Field Descriptions ...............................................................
AUXSIG7MUXENABLE Register Field Descriptions ...............................................................
AUXSIGOUTINV Register Field Descriptions .......................................................................
AUXSIGLOCK Register Field Descriptions ..........................................................................
EPWMXBAR Registers to Driverlib Functions.......................................................................
INPUTXBAR Registers to Driverlib Functions .......................................................................
OUTPUTXBAR Registers to Driverlib Functions ....................................................................
XBAR Registers to Driverlib Functions ...............................................................................
List of Tables
1293
1299
1303
1307
1311
1315
1319
1323
1327
1331
1335
1339
1343
1347
1351
1355
1359
1364
1369
1374
1379
1384
1389
1394
1399
1401
1402
1403
1403
1405
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
8-123. CLBXBAR Registers to Driverlib Functions .......................................................................... 1405
............................................................................................
9-1.
Analog Signal Descriptions
9-2.
Reference Summary .................................................................................................... 1410
9-3.
ANALOG_SUBSYS_REGS Registers ................................................................................ 1413
9-4.
ANALOG_SUBSYS_REGS Access Type Codes ................................................................... 1413
9-5.
INTOSC1TRIM Register Field Descriptions ......................................................................... 1414
9-6.
INTOSC2TRIM Register Field Descriptions ......................................................................... 1415
9-7.
TSNSCTL Register Field Descriptions
9-8.
LOCK Register Field Descriptions .................................................................................... 1417
9-9.
ANAREFTRIMA Register Field Descriptions ........................................................................ 1419
9-10.
ANAREFTRIMB Register Field Descriptions ........................................................................ 1420
9-11.
ANAREFTRIMD Register Field Descriptions ........................................................................ 1421
10-1.
ADC Options and Configuration Levels .............................................................................. 1424
10-2.
Analog to 12-bit Digital Formulas
10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
10-9.
10-10.
10-11.
10-12.
10-13.
10-14.
10-15.
10-16.
10-17.
10-18.
10-19.
10-20.
10-21.
10-22.
10-23.
10-24.
10-25.
10-26.
10-27.
10-28.
10-29.
10-30.
10-31.
10-32.
10-33.
10-34.
10-35.
10-36.
10-37.
...............................................................................
.....................................................................................
12-Bit Digital-to-Analog Formulas ....................................................................................
Channel Selection of Input Pins .......................................................................................
Example Requirements for Multiple Signal Sampling ..............................................................
Example Connections for Multiple Signal Sampling ................................................................
DETECTCFG Settings ..................................................................................................
ADC Timing Parameters ...............................................................................................
ADC Timings in 12-bit Mode (SYSCLK Cycles) .....................................................................
ADC_REGS Registers ..................................................................................................
ADC_REGS Access Type Codes .....................................................................................
ADCCTL1 Register Field Descriptions ...............................................................................
ADCCTL2 Register Field Descriptions ...............................................................................
ADCBURSTCTL Register Field Descriptions ........................................................................
ADCINTFLG Register Field Descriptions ............................................................................
ADCINTFLGCLR Register Field Descriptions .......................................................................
ADCINTOVF Register Field Descriptions ............................................................................
ADCINTOVFCLR Register Field Descriptions .......................................................................
ADCINTSEL1N2 Register Field Descriptions........................................................................
ADCINTSEL3N4 Register Field Descriptions........................................................................
ADCSOCPRICTL Register Field Descriptions ......................................................................
ADCINTSOCSEL1 Register Field Descriptions .....................................................................
ADCINTSOCSEL2 Register Field Descriptions .....................................................................
ADCSOCFLG1 Register Field Descriptions .........................................................................
ADCSOCFRC1 Register Field Descriptions .........................................................................
ADCSOCOVF1 Register Field Descriptions .........................................................................
ADCSOCOVFCLR1 Register Field Descriptions ....................................................................
ADCSOC0CTL Register Field Descriptions .........................................................................
ADCSOC1CTL Register Field Descriptions .........................................................................
ADCSOC2CTL Register Field Descriptions .........................................................................
ADCSOC3CTL Register Field Descriptions .........................................................................
ADCSOC4CTL Register Field Descriptions .........................................................................
ADCSOC5CTL Register Field Descriptions .........................................................................
ADCSOC6CTL Register Field Descriptions .........................................................................
ADCSOC7CTL Register Field Descriptions .........................................................................
ADCSOC8CTL Register Field Descriptions .........................................................................
ADCSOC9CTL Register Field Descriptions .........................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
1410
1416
1426
1426
1429
1431
1431
1441
1445
1446
1455
1456
1458
1460
1461
1463
1465
1467
1469
1470
1472
1474
1477
1479
1481
1486
1491
1495
1499
1502
1505
1508
1511
1514
1517
1520
1523
1526
63
www.ti.com
10-38. ADCSOC10CTL Register Field Descriptions ........................................................................ 1529
10-39. ADCSOC11CTL Register Field Descriptions ........................................................................ 1532
10-40. ADCSOC12CTL Register Field Descriptions ........................................................................ 1535
10-41. ADCSOC13CTL Register Field Descriptions ........................................................................ 1538
10-42. ADCSOC14CTL Register Field Descriptions ........................................................................ 1541
10-43. ADCSOC15CTL Register Field Descriptions ........................................................................ 1544
10-44. ADCEVTSTAT Register Field Descriptions .......................................................................... 1547
10-45. ADCEVTCLR Register Field Descriptions ........................................................................... 1549
10-46. ADCEVTSEL Register Field Descriptions............................................................................ 1551
10-47. ADCEVTINTSEL Register Field Descriptions ....................................................................... 1553
10-48. ADCOSDETECT Register Field Descriptions ....................................................................... 1555
10-49. ADCCOUNTER Register Field Descriptions......................................................................... 1556
10-50. ADCREV Register Field Descriptions
................................................................................
1557
10-51. ADCOFFTRIM Register Field Descriptions .......................................................................... 1558
10-52. ADCPPB1CONFIG Register Field Descriptions..................................................................... 1559
10-53. ADCPPB1STAMP Register Field Descriptions ...................................................................... 1561
10-54. ADCPPB1OFFCAL Register Field Descriptions
....................................................................
1562
10-55. ADCPPB1OFFREF Register Field Descriptions .................................................................... 1563
10-56. ADCPPB1TRIPHI Register Field Descriptions ...................................................................... 1564
10-57. ADCPPB1TRIPLO Register Field Descriptions ..................................................................... 1565
10-58. ADCPPB2CONFIG Register Field Descriptions..................................................................... 1566
10-59. ADCPPB2STAMP Register Field Descriptions ...................................................................... 1568
10-60. ADCPPB2OFFCAL Register Field Descriptions
....................................................................
1569
10-61. ADCPPB2OFFREF Register Field Descriptions .................................................................... 1570
10-62. ADCPPB2TRIPHI Register Field Descriptions ...................................................................... 1571
10-63. ADCPPB2TRIPLO Register Field Descriptions ..................................................................... 1572
10-64. ADCPPB3CONFIG Register Field Descriptions..................................................................... 1573
10-65. ADCPPB3STAMP Register Field Descriptions ...................................................................... 1575
1576
10-67.
1577
10-68.
10-69.
10-70.
10-71.
10-72.
10-73.
10-74.
10-75.
10-76.
10-77.
10-78.
10-79.
10-80.
10-81.
10-82.
10-83.
10-84.
10-85.
10-86.
64
....................................................................
ADCPPB3OFFREF Register Field Descriptions ....................................................................
ADCPPB3TRIPHI Register Field Descriptions ......................................................................
ADCPPB3TRIPLO Register Field Descriptions .....................................................................
ADCPPB4CONFIG Register Field Descriptions.....................................................................
ADCPPB4STAMP Register Field Descriptions ......................................................................
ADCPPB4OFFCAL Register Field Descriptions ....................................................................
ADCPPB4OFFREF Register Field Descriptions ....................................................................
ADCPPB4TRIPHI Register Field Descriptions ......................................................................
ADCPPB4TRIPLO Register Field Descriptions .....................................................................
ADCINLTRIM1 Register Field Descriptions ..........................................................................
ADCINLTRIM2 Register Field Descriptions ..........................................................................
ADCINLTRIM3 Register Field Descriptions ..........................................................................
ADCINLTRIM4 Register Field Descriptions ..........................................................................
ADCINLTRIM5 Register Field Descriptions ..........................................................................
ADCINLTRIM6 Register Field Descriptions ..........................................................................
ADC_RESULT_REGS Registers......................................................................................
ADC_RESULT_REGS Access Type Codes .........................................................................
ADCRESULT0 Register Field Descriptions ..........................................................................
ADCRESULT1 Register Field Descriptions ..........................................................................
ADCRESULT2 Register Field Descriptions ..........................................................................
10-66. ADCPPB3OFFCAL Register Field Descriptions
List of Tables
1578
1579
1580
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1594
1594
1595
1596
1597
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
10-87. ADCRESULT3 Register Field Descriptions .......................................................................... 1598
10-88. ADCRESULT4 Register Field Descriptions .......................................................................... 1599
10-89. ADCRESULT5 Register Field Descriptions .......................................................................... 1600
10-90. ADCRESULT6 Register Field Descriptions .......................................................................... 1601
10-91. ADCRESULT7 Register Field Descriptions .......................................................................... 1602
10-92. ADCRESULT8 Register Field Descriptions .......................................................................... 1603
10-93. ADCRESULT9 Register Field Descriptions .......................................................................... 1604
10-94. ADCRESULT10 Register Field Descriptions ........................................................................ 1605
10-95. ADCRESULT11 Register Field Descriptions ........................................................................ 1606
10-96. ADCRESULT12 Register Field Descriptions ........................................................................ 1607
10-97. ADCRESULT13 Register Field Descriptions ........................................................................ 1608
10-98. ADCRESULT14 Register Field Descriptions ........................................................................ 1609
10-99. ADCRESULT15 Register Field Descriptions ........................................................................ 1610
10-100. ADCPPB1RESULT Register Field Descriptions ................................................................... 1611
10-101. ADCPPB2RESULT Register Field Descriptions ................................................................... 1612
10-102. ADCPPB3RESULT Register Field Descriptions ................................................................... 1613
10-103. ADCPPB4RESULT Register Field Descriptions ................................................................... 1614
10-104. ADC Registers to Driverlib Functions ............................................................................... 1615
11-1.
DAC Base Address Table .............................................................................................. 1622
11-2.
DAC_REGS Registers .................................................................................................. 1623
11-3.
DAC_REGS Access Type Codes ..................................................................................... 1623
11-4.
DACREV Register Field Descriptions
11-5.
DACCTL Register Field Descriptions ................................................................................. 1625
11-6.
DACVALA Register Field Descriptions ............................................................................... 1626
11-7.
DACVALS Register Field Descriptions ............................................................................... 1627
11-8.
DACOUTEN Register Field Descriptions
11-9.
11-10.
11-11.
12-1.
12-2.
12-3.
12-4.
12-5.
12-6.
12-7.
12-8.
12-9.
12-10.
12-11.
12-12.
12-13.
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
................................................................................
............................................................................
DACLOCK Register Field Descriptions...............................................................................
DACTRIM Register Field Descriptions ...............................................................................
DAC Registers to Driverlib Functions .................................................................................
CMPSS Base Address Table ..........................................................................................
CMPSS_REGS Registers ..............................................................................................
CMPSS_REGS Access Type Codes .................................................................................
COMPCTL Register Field Descriptions ..............................................................................
COMPHYSCTL Register Field Descriptions .........................................................................
COMPSTS Register Field Descriptions ..............................................................................
COMPSTSCLR Register Field Descriptions .........................................................................
COMPDACCTL Register Field Descriptions .........................................................................
DACHVALS Register Field Descriptions .............................................................................
DACHVALA Register Field Descriptions .............................................................................
RAMPMAXREFA Register Field Descriptions .......................................................................
RAMPMAXREFS Register Field Descriptions .......................................................................
RAMPDECVALA Register Field Descriptions .......................................................................
RAMPDECVALS Register Field Descriptions .......................................................................
RAMPSTS Register Field Descriptions...............................................................................
DACLVALS Register Field Descriptions..............................................................................
DACLVALA Register Field Descriptions..............................................................................
RAMPDLYA Register Field Descriptions .............................................................................
RAMPDLYS Register Field Descriptions .............................................................................
CTRIPLFILCTL Register Field Descriptions .........................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
1624
1628
1629
1630
1631
1641
1642
1642
1644
1646
1647
1648
1649
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
65
www.ti.com
12-21. CTRIPLFILCLKCTL Register Field Descriptions .................................................................... 1663
12-22. CTRIPHFILCTL Register Field Descriptions......................................................................... 1664
12-23. CTRIPHFILCLKCTL Register Field Descriptions ................................................................... 1665
12-24. COMPLOCK Register Field Descriptions ............................................................................ 1666
12-25. CMPSS Registers to Driverlib Functions ............................................................................. 1667
13-1.
13-2.
13-3.
13-4.
13-5.
13-6.
13-7.
13-8.
13-9.
13-10.
13-11.
13-12.
13-13.
13-14.
13-15.
13-16.
13-17.
13-18.
13-19.
13-20.
13-21.
13-22.
13-23.
13-24.
13-25.
13-26.
13-27.
13-28.
13-29.
13-30.
13-31.
13-32.
13-33.
13-34.
13-35.
13-36.
13-37.
13-38.
13-39.
13-40.
13-41.
13-42.
13-43.
13-44.
66
................................................................................................
Order of Sinc Filter ......................................................................................................
Peak Data Values for Different DOSR/Filter Combinations .......................................................
Shift Control Bit Configuration Settings ..............................................................................
Number of Incorrect Samples Tabulated .............................................................................
Peak Data Values for Different OSR/Filter Combinations .........................................................
General Registers .......................................................................................................
Filter 1 Registers ........................................................................................................
Filter 2 Registers ........................................................................................................
Filter 3 Registers ........................................................................................................
Filter 4 Registers ........................................................................................................
SDFM Base Address Table ............................................................................................
SDFM_REGS Registers ................................................................................................
SDFM_REGS Access Type Codes ...................................................................................
SDIFLG Register Field Descriptions ..................................................................................
SDIFLGCLR Register Field Descriptions ............................................................................
SDCTL Register Field Descriptions ...................................................................................
SDMFILEN Register Field Descriptions ..............................................................................
SDCTLPARM1 Register Field Descriptions .........................................................................
SDDFPARM1 Register Field Descriptions ...........................................................................
SDDPARM1 Register Field Descriptions .............................................................................
SDCMPH1 Register Field Descriptions ..............................................................................
SDCMPL1 Register Field Descriptions ...............................................................................
SDCPARM1 Register Field Descriptions .............................................................................
SDDATA1 Register Field Descriptions ...............................................................................
SDCTLPARM2 Register Field Descriptions .........................................................................
SDDFPARM2 Register Field Descriptions ...........................................................................
SDDPARM2 Register Field Descriptions .............................................................................
SDCMPH2 Register Field Descriptions ..............................................................................
SDCMPL2 Register Field Descriptions ...............................................................................
SDCPARM2 Register Field Descriptions .............................................................................
SDDATA2 Register Field Descriptions ...............................................................................
SDCTLPARM3 Register Field Descriptions .........................................................................
SDDFPARM3 Register Field Descriptions ...........................................................................
SDDPARM3 Register Field Descriptions .............................................................................
SDCMPH3 Register Field Descriptions ..............................................................................
SDCMPL3 Register Field Descriptions ...............................................................................
SDCPARM3 Register Field Descriptions .............................................................................
SDDATA3 Register Field Descriptions ...............................................................................
SDCTLPARM4 Register Field Descriptions .........................................................................
SDDFPARM4 Register Field Descriptions ...........................................................................
SDDPARM4 Register Field Descriptions .............................................................................
SDCMPH4 Register Field Descriptions ..............................................................................
SDCMPL4 Register Field Descriptions ...............................................................................
Modulator Clock Modes
List of Tables
1673
1676
1677
1678
1679
1679
1683
1683
1683
1683
1684
1685
1686
1686
1688
1690
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
13-45. SDCPARM4 Register Field Descriptions ............................................................................. 1720
13-46. SDDATA4 Register Field Descriptions ............................................................................... 1721
13-47. SDFM Registers to Driverlib Functions ............................................................................... 1722
14-1.
Submodule Configuration Parameters................................................................................ 1732
14-2.
Key Time-Base Signals ................................................................................................. 1735
14-3.
Action-Qualifier Submodule Possible Input Events ................................................................. 1753
14-4.
Action-Qualifier Event Priority for Up-Down-Count Mode .......................................................... 1755
14-5.
Action-Qualifier Event Priority for Up-Count Mode.................................................................. 1755
14-6.
Action-Qualifier Event Priority for Down-Count Mode .............................................................. 1755
14-7.
Behavior if CMPA/CMPB is Greater than the Period ............................................................... 1756
14-8.
Classical Dead-Band Operating Modes
14-9.
14-10.
14-11.
14-12.
14-13.
14-14.
14-15.
14-16.
14-17.
14-18.
14-19.
14-20.
14-21.
14-22.
14-23.
14-24.
14-25.
14-26.
14-27.
14-28.
14-29.
14-30.
14-31.
14-32.
14-33.
14-34.
14-35.
14-36.
14-37.
14-38.
14-39.
14-40.
14-41.
14-42.
14-43.
14-44.
14-45.
14-46.
.............................................................................
Additional Dead-Band Operating Modes .............................................................................
Dead-Band Delay Values in μS as a Function of DBFED and DBRED .........................................
Possible Pulse Width Values for EPWMCLK = 80 MHz ...........................................................
Possible Actions On a Trip Event .....................................................................................
Resolution for PWM and HRPWM ....................................................................................
Relationship Between MEP Steps, PWM Frequency and Resolution ............................................
CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right).......................................................
Duty Cycle Range Limitation for Three EPWMCLK/TBCLK Cycles ..............................................
SFO Library Features ...................................................................................................
Factor Values ............................................................................................................
ePWM Base Address Table ...........................................................................................
EPWM_REGS Registers ...............................................................................................
EPWM_REGS Access Type Codes ..................................................................................
TBCTL Register Field Descriptions ...................................................................................
TBCTL2 Register Field Descriptions..................................................................................
TBCTR Register Field Descriptions ...................................................................................
TBSTS Register Field Descriptions ...................................................................................
CMPCTL Register Field Descriptions.................................................................................
CMPCTL2 Register Field Descriptions ...............................................................................
DBCTL Register Field Descriptions ...................................................................................
DBCTL2 Register Field Descriptions .................................................................................
AQCTL Register Field Descriptions ...................................................................................
AQTSRCSEL Register Field Descriptions ...........................................................................
PCCTL Register Field Descriptions ...................................................................................
VCAPCTL Register Field Descriptions ...............................................................................
VCNTCFG Register Field Descriptions...............................................................................
HRCNFG Register Field Descriptions ................................................................................
HRPWR Register Field Descriptions .................................................................................
HRMSTEP Register Field Descriptions ..............................................................................
HRCNFG2 Register Field Descriptions...............................................................................
HRPCTL Register Field Descriptions .................................................................................
TRREM Register Field Descriptions ..................................................................................
GLDCTL Register Field Descriptions .................................................................................
GLDCFG Register Field Descriptions ................................................................................
EPWMXLINK Register Field Descriptions ...........................................................................
AQCTLA Register Field Descriptions .................................................................................
AQCTLA2 Register Field Descriptions ...............................................................................
AQCTLB Register Field Descriptions .................................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
1768
1768
1770
1773
1777
1815
1822
1823
1826
1838
1839
1841
1842
1844
1845
1848
1849
1850
1851
1853
1855
1858
1859
1861
1862
1864
1866
1868
1870
1871
1872
1873
1875
1876
1878
1880
1884
1886
1888
67
www.ti.com
1890
14-48.
1892
14-49.
14-50.
14-51.
14-52.
14-53.
14-54.
14-55.
14-56.
14-57.
14-58.
14-59.
14-60.
14-61.
14-62.
14-63.
14-64.
14-65.
14-66.
14-67.
14-68.
14-69.
14-70.
14-71.
14-72.
14-73.
14-74.
14-75.
14-76.
14-77.
14-78.
14-79.
14-80.
14-81.
14-82.
14-83.
14-84.
14-85.
14-86.
14-87.
14-88.
14-89.
14-90.
14-91.
14-92.
14-93.
14-94.
14-95.
68
...............................................................................
AQSFRC Register Field Descriptions ................................................................................
AQCSFRC Register Field Descriptions ..............................................................................
DBREDHR Register Field Descriptions ..............................................................................
DBRED Register Field Descriptions ..................................................................................
DBFEDHR Register Field Descriptions...............................................................................
DBFED Register Field Descriptions ..................................................................................
TBPHS Register Field Descriptions ...................................................................................
TBPRDHR Register Field Descriptions...............................................................................
TBPRD Register Field Descriptions ..................................................................................
CMPA Register Field Descriptions ....................................................................................
CMPB Register Field Descriptions ....................................................................................
CMPC Register Field Descriptions ....................................................................................
CMPD Register Field Descriptions ....................................................................................
GLDCTL2 Register Field Descriptions ...............................................................................
SWVDELVAL Register Field Descriptions ...........................................................................
TZSEL Register Field Descriptions ...................................................................................
TZDCSEL Register Field Descriptions ...............................................................................
TZCTL Register Field Descriptions ...................................................................................
TZCTL2 Register Field Descriptions ..................................................................................
TZCTLDCA Register Field Descriptions..............................................................................
TZCTLDCB Register Field Descriptions..............................................................................
TZEINT Register Field Descriptions ..................................................................................
TZFLG Register Field Descriptions ...................................................................................
TZCBCFLG Register Field Descriptions .............................................................................
TZOSTFLG Register Field Descriptions..............................................................................
TZCLR Register Field Descriptions ...................................................................................
TZCBCCLR Register Field Descriptions .............................................................................
TZOSTCLR Register Field Descriptions .............................................................................
TZFRC Register Field Descriptions ...................................................................................
ETSEL Register Field Descriptions ...................................................................................
ETPS Register Field Descriptions.....................................................................................
ETFLG Register Field Descriptions ...................................................................................
ETCLR Register Field Descriptions ...................................................................................
ETFRC Register Field Descriptions ...................................................................................
ETINTPS Register Field Descriptions ................................................................................
ETSOCPS Register Field Descriptions ...............................................................................
ETCNTINITCTL Register Field Descriptions ........................................................................
ETCNTINIT Register Field Descriptions..............................................................................
DCTRIPSEL Register Field Descriptions ............................................................................
DCACTL Register Field Descriptions .................................................................................
DCBCTL Register Field Descriptions .................................................................................
DCFCTL Register Field Descriptions .................................................................................
DCCAPCTL Register Field Descriptions .............................................................................
DCFOFFSET Register Field Descriptions ...........................................................................
DCFOFFSETCNT Register Field Descriptions ......................................................................
DCFWINDOW Register Field Descriptions ..........................................................................
DCFWINDOWCNT Register Field Descriptions .....................................................................
DCCAP Register Field Descriptions ..................................................................................
14-47. AQCTLB2 Register Field Descriptions
List of Tables
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1910
1912
1914
1916
1918
1920
1921
1923
1925
1927
1929
1931
1933
1934
1937
1940
1941
1942
1943
1944
1946
1947
1948
1950
1952
1954
1956
1958
1959
1960
1961
1962
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
14-96. DCAHTRIPSEL Register Field Descriptions ......................................................................... 1963
14-97. DCALTRIPSEL Register Field Descriptions ......................................................................... 1965
14-98. DCBHTRIPSEL Register Field Descriptions ......................................................................... 1967
14-99. DCBLTRIPSEL Register Field Descriptions ......................................................................... 1969
14-100. HWVDELVAL Register Field Descriptions.......................................................................... 1971
14-101. VCNTVAL Register Field Descriptions .............................................................................. 1972
14-102. SYNC_SOC_REGS Registers ....................................................................................... 1973
14-103. SYNC_SOC_REGS Access Type Codes
..........................................................................
1973
14-104. SYNCSELECT Register Field Descriptions ........................................................................ 1974
14-105. ADCSOCOUTSELECT Register Field Descriptions
..............................................................
1977
14-106. SYNCSOCLOCK Register Field Descriptions...................................................................... 1980
14-107. EPWM Registers to Driverlib Functions............................................................................. 1981
..........................................................................
............................................................................................
ECAP_REGS Registers ................................................................................................
ECAP_REGS Access Type Codes ...................................................................................
TSCTR Register Field Descriptions ...................................................................................
CTRPHS Register Field Descriptions.................................................................................
CAP1 Register Field Descriptions.....................................................................................
CAP2 Register Field Descriptions.....................................................................................
CAP3 Register Field Descriptions.....................................................................................
CAP4 Register Field Descriptions.....................................................................................
ECCTL1 Register Field Descriptions .................................................................................
ECCTL2 Register Field Descriptions .................................................................................
ECEINT Register Field Descriptions ..................................................................................
ECFLG Register Field Descriptions ...................................................................................
ECCLR Register Field Descriptions ..................................................................................
ECFRC Register Field Descriptions ..................................................................................
ECAP Registers to Driverlib Functions ...............................................................................
EQEP Memory Map ....................................................................................................
Quadrature Decoder Truth Table .....................................................................................
EQEP_REGS Registers ................................................................................................
EQEP_REGS Access Type Codes ...................................................................................
QPOSCNT Register Field Descriptions ..............................................................................
QPOSINIT Register Field Descriptions ...............................................................................
QPOSMAX Register Field Descriptions ..............................................................................
QPOSCMP Register Field Descriptions ..............................................................................
QPOSILAT Register Field Descriptions ..............................................................................
QPOSSLAT Register Field Descriptions .............................................................................
QPOSLAT Register Field Descriptions ...............................................................................
QUTMR Register Field Descriptions ..................................................................................
QUPRD Register Field Descriptions ..................................................................................
QWDTMR Register Field Descriptions ...............................................................................
QWDPRD Register Field Descriptions ...............................................................................
QDECCTL Register Field Descriptions ...............................................................................
QEPCTL Register Field Descriptions .................................................................................
QCAPCTL Register Field Descriptions ...............................................................................
QPOSCTL Register Field Descriptions ...............................................................................
QEINT Register Field Descriptions ...................................................................................
14-108. HRPWM Registers to Driverlib Functions
1986
15-1.
2007
15-2.
15-3.
15-4.
15-5.
15-6.
15-7.
15-8.
15-9.
15-10.
15-11.
15-12.
15-13.
15-14.
15-15.
15-16.
16-1.
16-2.
16-3.
16-4.
16-5.
16-6.
16-7.
16-8.
16-9.
16-10.
16-11.
16-12.
16-13.
16-14.
16-15.
16-16.
16-17.
16-18.
16-19.
16-20.
eCAP Base Address Table
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
2008
2008
2009
2010
2011
2012
2013
2014
2015
2017
2019
2021
2023
2024
2025
2032
2034
2049
2049
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2064
2067
2068
2069
69
www.ti.com
16-21. QFLG Register Field Descriptions .................................................................................... 2071
16-22. QCLR Register Field Descriptions .................................................................................... 2073
16-23. QFRC Register Field Descriptions .................................................................................... 2075
16-24. QEPSTS Register Field Descriptions ................................................................................. 2077
16-25. QCTMR Register Field Descriptions .................................................................................. 2079
16-26. QCPRD Register Field Descriptions .................................................................................. 2080
16-27. QCTMRLAT Register Field Descriptions ............................................................................. 2081
16-28. QCPRDLAT Register Field Descriptions ............................................................................. 2082
16-29. EQEP Registers to Driverlib Functions ............................................................................... 2083
17-1.
SPI Module Signal Summary .......................................................................................... 2087
17-2.
SPI Interrupt Flag Modes ............................................................................................... 2090
17-3.
SPI Clocking Scheme Selection Guide ............................................................................... 2095
17-4.
4-wire vs. 3-wire SPI Pin Functions ................................................................................... 2098
17-5.
3-Wire SPI Pin Configuration .......................................................................................... 2099
17-6.
SPI Base Address Table ............................................................................................... 2105
17-7.
SPI_REGS Registers ................................................................................................... 2106
17-8.
SPI_REGS Access Type Codes
2106
17-9.
SPICCR Register Field Descriptions
2107
17-10.
17-11.
17-12.
17-13.
17-14.
17-15.
17-16.
17-17.
17-18.
17-19.
17-20.
17-21.
18-1.
18-2.
18-3.
18-4.
18-5.
18-6.
18-7.
18-8.
18-9.
18-10.
18-11.
18-12.
18-13.
18-14.
18-15.
18-16.
18-17.
18-18.
18-19.
70
......................................................................................
.................................................................................
SPICTL Register Field Descriptions ..................................................................................
SPISTS Register Field Descriptions ..................................................................................
SPIBRR Register Field Descriptions..................................................................................
SPIRXEMU Register Field Descriptions..............................................................................
SPIRXBUF Register Field Descriptions ..............................................................................
SPITXBUF Register Field Descriptions ..............................................................................
SPIDAT Register Field Descriptions ..................................................................................
SPIFFTX Register Field Descriptions.................................................................................
SPIFFRX Register Field Descriptions ................................................................................
SPIFFCT Register Field Descriptions ................................................................................
SPIPRI Register Field Descriptions ...................................................................................
SPI Registers to Driverlib Functions ..................................................................................
SCI Module Signal Summary ..........................................................................................
Programming the Data Format Using SCICCR .....................................................................
Asynchronous Baud Register Values for Common SCI Bit Rates ................................................
SCI Interrupt Flags ......................................................................................................
SCI Base Address Table ...............................................................................................
SCI_REGS Registers ...................................................................................................
SCI_REGS Access Type Codes ......................................................................................
SCICCR Register Field Descriptions .................................................................................
SCICTL1 Register Field Descriptions.................................................................................
SCIHBAUD Register Field Descriptions ..............................................................................
SCILBAUD Register Field Descriptions ..............................................................................
SCICTL2 Register Field Descriptions.................................................................................
SCIRXST Register Field Descriptions ................................................................................
SCIRXEMU Register Field Descriptions .............................................................................
SCIRXBUF Register Field Descriptions ..............................................................................
SCITXBUF Register Field Descriptions ..............................................................................
SCIFFTX Register Field Descriptions ................................................................................
SCIFFRX Register Field Descriptions ................................................................................
SCIFFCT Register Field Descriptions ................................................................................
List of Tables
2109
2111
2113
2114
2115
2116
2117
2118
2120
2122
2123
2125
2130
2131
2138
2140
2141
2142
2142
2143
2145
2147
2148
2149
2151
2153
2154
2155
2156
2158
2160
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
18-20. SCIPRI Register Field Descriptions ................................................................................... 2161
18-21. SCI Registers to Driverlib Functions .................................................................................. 2162
19-1.
Dependency of Delay d on the Divide-Down Value IPSC ......................................................... 2168
19-2.
Operating Modes of the I2C Module .................................................................................. 2169
19-3.
Master-Transmitter/Receiver Bus Activity Defined by the RM, STT, and STP Bits of I2CMDR .............. 2170
19-4.
How the MST and FDF Bits of I2CMDR Affect the Role of the TRX Bit of I2CMDR ........................... 2173
19-5.
Ways to Generate a NACK Bit ........................................................................................ 2174
19-6.
Descriptions of the Basic I2C Interrupt Requests ................................................................... 2177
19-7.
I2C Base Address Table (C28) ........................................................................................ 2180
19-8.
I2C_REGS Registers ................................................................................................... 2181
19-9.
I2C_REGS Access Type Codes....................................................................................... 2181
19-10. I2COAR Register Field Descriptions.................................................................................. 2182
19-11. I2CIER Register Field Descriptions ................................................................................... 2183
19-12. I2CSTR Register Field Descriptions .................................................................................. 2184
19-13. I2CCLKL Register Field Descriptions ................................................................................. 2188
19-14. I2CCLKH Register Field Descriptions ................................................................................ 2189
19-15. I2CCNT Register Field Descriptions .................................................................................. 2190
19-16. I2CDRR Register Field Descriptions.................................................................................. 2191
19-17. I2CSAR Register Field Descriptions .................................................................................. 2192
19-18. I2CDXR Register Field Descriptions .................................................................................. 2193
19-19. I2CMDR Register Field Descriptions ................................................................................. 2194
19-20. I2CISRC Register Field Descriptions ................................................................................. 2198
19-21. I2CEMDR Register Field Descriptions
...............................................................................
2199
19-22. I2CPSC Register Field Descriptions .................................................................................. 2200
19-23. I2CFFTX Register Field Descriptions ................................................................................. 2201
................................................................................
I2C Registers to Driverlib Functions ..................................................................................
McBSP Interface Pins/Signals .........................................................................................
Register Bits That Determine the Number of Phases, Words, and Bits .........................................
Interrupts and DMA Events Generated by a McBSP ...............................................................
Effects of DLB and CLKSTP on Clock Modes.......................................................................
Choosing an Input Clock for the Sample Rate Generator with the SCLKME and CLKSM Bits ..............
Polarity Options for the Input to the Sample Rate Generator .....................................................
Input Clock Selection for Sample Rate Generator ..................................................................
Block - Channel Assignment ...........................................................................................
2-Partition Mode .........................................................................................................
8-Partition mode .........................................................................................................
Receive Channel Assignment and Control With Eight Receive Partitions .......................................
Transmit Channel Assignment and Control When Eight Transmit Partitions Are Used .......................
Selecting a Transmit Multichannel Selection Mode With the XMCM Bits........................................
Bits Used to Enable and Configure the Clock Stop Mode .........................................................
Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme .................................................
Bit Values Required to Configure the McBSP as an SPI Master ................................................
Bit Values Required to Configure the McBSP as an SPI Slave ...................................................
Register Bits Used to Reset or Enable the McBSP Receiver Field Descriptions ...............................
Reset State of Each McBSP Pin ......................................................................................
Register Bit Used to Enable/Disable the Digital Loopback Mode .................................................
Receive Signals Connected to Transmit Signals in Digital Loopback Mode ....................................
Register Bits Used to Enable/Disable the Clock Stop Mode ......................................................
19-24. I2CFFRX Register Field Descriptions
2203
19-25.
2205
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
20-8.
20-9.
20-10.
20-11.
20-12.
20-13.
20-14.
20-15.
20-16.
20-17.
20-18.
20-19.
20-20.
20-21.
20-22.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
2209
2216
2220
2222
2222
2223
2226
2235
2236
2236
2238
2239
2240
2243
2244
2247
2248
2250
2250
2251
2251
2251
71
www.ti.com
20-23. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme ................................................. 2252
20-24. Register Bit Used to Enable/Disable the Receive Multichannel Selection Mode ............................... 2252
20-25. Register Bit Used to Choose One or Two Phases for the Receive Frame ...................................... 2252
20-26. Register Bits Used to Set the Receive Word Length(s) ............................................................ 2253
20-27. Register Bits Used to Set the Receive Frame Length .............................................................. 2253
20-28. How to Calculate the Length of the Receive Frame ................................................................ 2254
20-29. Register Bit Used to Enable/Disable the Receive Frame-Synchronization Ignore Function .................. 2254
20-30. Register Bits Used to Set the Receive Companding Mode ........................................................ 2255
20-31. Register Bits Used to Set the Receive Data Delay ................................................................. 2256
20-32. Register Bits Used to Set the Receive Sign-Extension and Justification Mode................................. 2258
20-33. Example: Use of RJUST Field With 12-Bit Data Value ABCh..................................................... 2258
20-34. Example: Use of RJUST Field With 20-Bit Data Value ABCDEh ................................................. 2258
20-35. Register Bits Used to Set the Receive Interrupt Mode ............................................................. 2259
2259
20-37.
2260
20-38.
20-39.
20-40.
20-41.
20-42.
20-43.
20-44.
20-45.
20-46.
20-47.
20-48.
20-49.
20-50.
20-51.
20-52.
20-53.
20-54.
20-55.
20-56.
20-57.
20-58.
20-59.
20-60.
20-61.
20-62.
20-63.
20-64.
20-65.
20-66.
20-67.
20-68.
20-69.
20-70.
20-71.
72
..........................................
Select Sources to Provide the Receive Frame-Synchronization Signal and the Effect on the FSR Pin.....
Register Bit Used to Set Receive Frame-Synchronization Polarity ...............................................
Register Bits Used to Set the SRG Frame-Synchronization Period and Pulse Width .........................
Register Bits Used to Set the Receive Clock Mode ...............................................................
Receive Clock Signal Source Selection ..............................................................................
Register Bit Used to Set Receive Clock Polarity ....................................................................
Register Bits Used to Set the Sample Rate Generator (SRG) Clock Divide-Down Value .....................
Register Bit Used to Set the SRG Clock Synchronization Mode .................................................
Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock) ......................................
Register Bits Used to Set the SRG Input Clock Polarity ...........................................................
Register Bits Used to Place Transmitter in Reset Field Descriptions ............................................
Register Bit Used to Enable/Disable the Digital Loopback Mode .................................................
Receive Signals Connected to Transmit Signals in Digital Loopback Mode ....................................
Register Bits Used to Enable/Disable the Clock Stop Mode ......................................................
Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme .................................................
Register Bits Used to Enable/Disable Transmit Multichannel Selection .........................................
Use of the Transmit Channel Enable Registers ....................................................................
Register Bit Used to Choose 1 or 2 Phases for the Transmit Frame ............................................
Register Bits Used to Set the Transmit Word Length(s) ...........................................................
Register Bits Used to Set the Transmit Frame Length .............................................................
How to Calculate Frame Length .......................................................................................
Register Bit Used to Enable/Disable the Transmit Frame-Synchronization Ignore Function .................
Register Bits Used to Set the Transmit Companding Mode .......................................................
Register Bits Used to Set the Transmit Data Delay ................................................................
Register Bit Used to Set the Transmit DXENA (DX Delay Enabler) Mode ......................................
Register Bits Used to Set the Transmit Interrupt Mode ............................................................
Register Bits Used to Set the Transmit Frame-Synchronization Mode ..........................................
How FSXM and FSGM Select the Source of Transmit Frame-Synchronization Pulses .......................
Register Bit Used to Set Transmit Frame-Synchronization Polarity ..............................................
Register Bits Used to Set SRG Frame-Synchronization Period and Pulse Width ..............................
Register Bit Used to Set the Transmit Clock Mode .................................................................
How the CLKXM Bit Selects the Transmit Clock and the Corresponding Status of the MCLKX pin .........
Register Bit Used to Set Transmit Clock Polarity ...................................................................
McBSP Emulation Modes Selectable with FREE and SOFT Bits of SPCR2....................................
Reset State of Each McBSP Pin ......................................................................................
20-36. Register Bits Used to Set the Receive Frame Synchronization Mode
List of Tables
2261
2262
2263
2264
2264
2266
2266
2267
2268
2269
2270
2270
2270
2271
2272
2272
2275
2275
2276
2276
2277
2278
2279
2281
2281
2282
2282
2283
2284
2285
2285
2285
2287
2287
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
..............................................................................
Transmit Interrupt Sources and Signals ..............................................................................
Error Flags ...............................................................................................................
McBSP Mode Selection ................................................................................................
McBSP Base Address Table...........................................................................................
McBSP Register Summary.............................................................................................
Serial Port Control 1 Register (SPCR1) Field Descriptions .......................................................
Serial Port Control 2 Register (SPCR2) Field Descriptions........................................................
Receive Control Register 1 (RCR1) Field Descriptions ............................................................
Frame Length Formula for Receive Control 1 Register (RCR1) ..................................................
Receive Control Register 2 (RCR2) Field Descriptions ............................................................
Frame Length Formula for Receive Control 2 Register (RCR2) ..................................................
Transmit Control 1 Register (XCR1) Field Descriptions ...........................................................
Frame Length Formula for Transmit Control 1 Register (XCR1) .................................................
Transmit Control 2 Register (XCR2) Field Descriptions ...........................................................
Frame Length Formula for Transmit Control 2 Register (XCR2) .................................................
Sample Rate Generator 1 Register (SRGR1) Field Descriptions .................................................
Sample Rate Generator 2 Register (SRGR2) Field Descriptions .................................................
Multichannel Control 1 Register (MCR1) Field Descriptions ......................................................
Multichannel Control 2 Register (MCR2) Field Descriptions ......................................................
Pin Control Register (PCR) Field Descriptions ......................................................................
Pin Configuration .......................................................................................................
Receive Channel Enable Registers (RCERA...RCERH) Field Descriptions.....................................
Use of the Receive Channel Enable Registers .....................................................................
Transmit Channel Enable Registers (XCERA...XCERH) Field Descriptions ....................................
Use of the Transmit Channel Enable Registers ....................................................................
McBSP Interrupt Enable Register (MFFINT) Field Descriptions ..................................................
MCBSP Registers to Driverlib Functions .............................................................................
CAN Register Access From Software ................................................................................
CAN Register Access From CCS .....................................................................................
PIE Nomenclature for Interrupts .......................................................................................
Programmable Ranges Required by CAN Protocol ................................................................
Message Object Field Descriptions ...................................................................................
Message RAM Addressing in Debug Mode .........................................................................
CAN Base Address Table ..............................................................................................
CAN_REGS Registers ..................................................................................................
CAN_REGS Access Type Codes .....................................................................................
CAN_CTL Register Field Descriptions ...............................................................................
CAN_ES Register Field Descriptions .................................................................................
CAN_ERRC Register Field Descriptions .............................................................................
CAN_BTR Register Field Descriptions ...............................................................................
CAN_INT Register Field Descriptions ................................................................................
CAN_TEST Register Field Descriptions..............................................................................
CAN_PERR Register Field Descriptions .............................................................................
CAN_RAM_INIT Register Field Descriptions ........................................................................
CAN_GLB_INT_EN Register Field Descriptions ....................................................................
CAN_GLB_INT_FLG Register Field Descriptions ..................................................................
CAN_GLB_INT_CLR Register Field Descriptions ..................................................................
CAN_ABOTR Register Field Descriptions ...........................................................................
20-72. Receive Interrupt Sources and Signals
20-73.
20-74.
20-75.
20-76.
20-77.
20-78.
20-79.
20-80.
20-81.
20-82.
20-83.
20-84.
20-85.
20-86.
20-87.
20-88.
20-89.
20-90.
20-91.
20-92.
20-93.
20-94.
20-95.
20-96.
20-97.
20-98.
20-99.
21-1.
21-2.
21-3.
21-4.
21-5.
21-6.
21-7.
21-8.
21-9.
21-10.
21-11.
21-12.
21-13.
21-14.
21-15.
21-16.
21-17.
21-18.
21-19.
21-20.
21-21.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
2292
2292
2293
2293
2296
2296
2298
2301
2303
2304
2304
2305
2306
2306
2307
2308
2309
2310
2311
2313
2315
2317
2317
2318
2319
2320
2321
2322
2329
2330
2336
2346
2355
2357
2359
2360
2361
2362
2365
2367
2368
2370
2371
2373
2374
2375
2376
2377
2378
73
www.ti.com
21-22. CAN_TXRQ_X Register Field Descriptions .......................................................................... 2379
21-23. CAN_TXRQ_21 Register Field Descriptions
........................................................................
2380
21-24. CAN_NDAT_X Register Field Descriptions .......................................................................... 2381
21-25. CAN_NDAT_21 Register Field Descriptions......................................................................... 2382
21-26. CAN_IPEN_X Register Field Descriptions ........................................................................... 2383
21-27. CAN_IPEN_21 Register Field Descriptions .......................................................................... 2384
21-28. CAN_MVAL_X Register Field Descriptions .......................................................................... 2385
21-29. CAN_MVAL_21 Register Field Descriptions......................................................................... 2386
2387
21-31.
2388
21-32.
21-33.
21-34.
21-35.
21-36.
21-37.
21-38.
21-39.
21-40.
21-41.
21-42.
21-43.
21-44.
21-45.
21-46.
21-47.
21-48.
21-49.
21-50.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
74
.......................................................................
CAN_IF1CMD Register Field Descriptions ..........................................................................
CAN_IF1MSK Register Field Descriptions ...........................................................................
CAN_IF1ARB Register Field Descriptions ...........................................................................
CAN_IF1MCTL Register Field Descriptions .........................................................................
CAN_IF1DATA Register Field Descriptions .........................................................................
CAN_IF1DATB Register Field Descriptions .........................................................................
CAN_IF2CMD Register Field Descriptions ..........................................................................
CAN_IF2MSK Register Field Descriptions ...........................................................................
CAN_IF2ARB Register Field Descriptions ...........................................................................
CAN_IF2MCTL Register Field Descriptions .........................................................................
CAN_IF2DATA Register Field Descriptions .........................................................................
CAN_IF2DATB Register Field Descriptions .........................................................................
CAN_IF3OBS Register Field Descriptions ...........................................................................
CAN_IF3MSK Register Field Descriptions ...........................................................................
CAN_IF3ARB Register Field Descriptions ...........................................................................
CAN_IF3MCTL Register Field Descriptions .........................................................................
CAN_IF3DATA Register Field Descriptions .........................................................................
CAN_IF3DATB Register Field Descriptions .........................................................................
CAN_IF3UPD Register Field Descriptions ...........................................................................
CAN Registers to Driverlib Functions .................................................................................
USB Memory Access From Software .................................................................................
USB Memory Access From CCS......................................................................................
USB Base Address Table (C28) ......................................................................................
Universal Serial Bus (USB) Controller Register Map ..............................................................
Function Address Register (USBFADDR) Field Descriptions .....................................................
Power Management Register (USBPOWER) in Host Mode Field Descriptions ................................
Power Management Register (USBPOWER) in Device Mode Field Descriptions..............................
USB Transmit Interrupt Status Register (USBTXIS) Field Descriptions .........................................
USB Transmit Interrupt Status Register (USBRXIS) Field Descriptions .........................................
USB Transmit Interrupt Status Register (USBTXIE) Field Descriptions .........................................
USB Transmit Interrupt Status Register (USBRXIE) Field Descriptions .........................................
USB General Interrupt Status Register (USBIS) in Host Mode Field Descriptions .............................
USB General Interrupt Status Register (USBIS) in Device Mode Field Descriptions ..........................
USB Interrupt Enable Register (USBIE) in Host Mode Field Descriptions ......................................
USB Interrupt Enable Register (USBIE) in Device Mode Field Descriptions ....................................
Frame Number Register (FRAME) Field Descriptions .............................................................
USB Endpoint Index Register (USBEPIDX) Field Descriptions ...................................................
USB Test Mode Register (USBTEST) in Host Mode Field Descriptions.........................................
USB Test Mode Register (USBTEST) in Device Mode Field Descriptions ......................................
USB FIFO Endpoint n Register (USBFIFO[n]) Field Descriptions ................................................
21-30. CAN_IP_MUX21 Register Field Descriptions
List of Tables
2392
2393
2395
2398
2399
2400
2404
2405
2407
2410
2411
2412
2414
2415
2416
2418
2419
2420
2421
2433
2434
2437
2438
2448
2449
2449
2451
2453
2455
2457
2459
2460
2461
2462
2463
2463
2464
2464
2466
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
22-21. USB Device Control Register (USBDEVCTL) Field Descriptions ................................................. 2467
22-22. USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ) Field Descriptions ........................... 2469
22-23. USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ) Field Descriptions ............................ 2470
22-24. USB Transmit FIFO Start Address Register (USBTXFIFOADDR) Field Descriptions ......................... 2471
22-25. USB Receive FIFO Start Address Register (USBRXFIFOADDR) Field Descriptions .......................... 2472
22-26. USB Connect Timing Register (USBCONTIM) Field Descriptions................................................ 2473
22-27. USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF) Field Descriptions ..... 2474
22-28. USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF) Field Descriptions..... 2474
22-29. USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[n]) Field Descriptions ...... 2475
22-30. USB Transmit Hub Address Endpoint n Registers(USBTXHUBADDR[n]) Field Descriptions ................ 2476
22-31. USB Transmit Hub Port Endpoint n Registers(USBTXHUBPORT[n]) Field Descriptions ..................... 2477
22-32. USB Recieve Functional Address Endpoint n Registers(USBFIFO[n]) Field Descriptions .................... 2478
22-33. USB Receive Hub Address Endpoint n Registers(USBRXHUBADDR[n]) Field Descriptions
................
2479
22-34. USB Transmit Hub Port Endpoint n Registers(USBRXHUBPORT[n]) Field Descriptions ..................... 2480
22-35. USB Maximum Transmit Data Endpoint n Registers(USBTXMAXP[n]) Field Descriptions ................... 2481
..........
USB Control and Status Endpoint 0 Low Register (USBCSRL0) in Device Mode Field Descriptions .......
USB Control and Status Endpoint 0 High Register (USBCSRH0) in Host Mode Field Descriptions.........
USB Control and Status Endpoint 0 High Register (USBCSRH0) in Device Mode Field Descriptions ......
USB Receive Byte Count Endpoint 0 Register (USBCOUNT0) Field Descriptions ............................
USB Type Endpoint 0 Register (USBTYPE0) Field Descriptions .................................................
USB NAK Limit Register (USBNAKLMT) Field Descriptions ......................................................
22-36. USB Control and Status Endpoint 0 Low Register(USBCSRL0) in Host Mode Field Descriptions
2482
22-37.
2483
22-38.
22-39.
22-40.
22-41.
22-42.
2484
2484
2485
2485
2486
22-43. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Host Mode Field
Descriptions .............................................................................................................. 2487
22-44. USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[n]) in Device Mode Field
Descriptions .............................................................................................................. 2488
22-45. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Host Mode Field
Descriptions .............................................................................................................. 2490
22-46. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Device Mode Field
Descriptions .............................................................................................................. 2491
22-47. USB Maximum Receive Data Endpoint n Registers (USBTXMAXP[n]) Field Descriptions ................... 2492
22-48. USB Control and Status Endpoint n Low Register(USBCSRL[n]) in Host Mode Field Descriptions ......... 2493
22-49. USB Control and Status Endpoint 0 Low Register(USBCSRL[n]) in Device Mode Field Descriptions ...... 2494
22-50. USB Control and Status Endpoint n High Register (USBCSRH[n]) in Host Mode Field Descriptions ....... 2495
22-51. USB Control and Status Endpoint 0 High Register(USBCSRH[n]) in Device Mode Field Descriptions ..... 2496
22-52. USB Maximum Receive Data Endpoint n Registers (USBRXCOUNT[n]) Field Descriptions ................. 2497
22-53. USB Host Transmit Configure Type Endpoint n Register(USBTXTYPE[n]) Field Descriptions
..............
2498
22-54. USBTXINTERVAL[n] Frame Numbers ............................................................................... 2499
22-55. USB Host Transmit Interval Endpoint n Register(USBTXINTERVAL[n]) Field Descriptions .................. 2499
22-56. USB Host Configure Receive Type Endpoint n Register(USBRXTYPE[n]) Field Descriptions ............... 2500
22-57. USBRXINTERVAL[n] Frame Numbers ............................................................................... 2501
22-58. USB Host Receive Polling Interval Endpoint n Register(USBRXINTERVAL[n]) Field Descriptions.......... 2501
22-59. USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[n]) Field
Descriptions .............................................................................................................. 2502
22-60. USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS) Field Descriptions .......... 2503
22-61. USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS) Field Descriptions .......... 2505
22-62. USB External Power Control Register (USBEPC) Field Descriptions ............................................ 2506
22-63. USB External Power Control Raw Interrupt Status Register (USBEPCRIS) Field Descriptions .............. 2508
22-64. USB External Power Control Interrupt Mask Register (USBEPCIM) Field Descriptions....................... 2509
22-65. USB External Power Control Interrupt Status and Clear Register (USBEPCISC) Field Descriptions ....... 2510
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
75
www.ti.com
22-66. USB Device RESUME Raw Interrupt Status Register (USBDRRIS) Field Descriptions....................... 2511
22-67. USB Device RESUME Raw Interrupt Status Register (USBDRRIS) Field Descriptions....................... 2512
22-68. USB Device RESUME Interrupt Status and Clear Register (USBDRISC) Field Descriptions ................ 2513
22-69. USB General-Purpose Control and Status Register (USBGPCS) Field Descriptions .......................... 2514
22-70. USB DMA Select Register (USBDMASEL) Field Descriptions .................................................... 2515
23-1.
Configuration for the EMIF1 Module .................................................................................. 2518
23-2.
EMIF Pins Used to Access Both SDRAM and Asynchronous Memories ........................................ 2520
23-3.
EMIF Pins Specific to SDRAM
2521
23-4.
EMIF Pins Specific to Asynchronous Memory
2521
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
23-28.
23-29.
23-30.
23-31.
23-32.
23-33.
23-34.
23-35.
23-36.
23-37.
23-38.
23-39.
23-40.
23-41.
23-42.
23-43.
23-44.
76
........................................................................................
......................................................................
EMIF SDRAM Commands .............................................................................................
Truth Table for SDRAM Commands ..................................................................................
16-bit EMIF Address Pin Connections................................................................................
Description of the SDRAM Configuration Register (SDRAM_CR) ................................................
Description of the SDRAM Refresh Control Register (SDRAM_RCR) ...........................................
Description of the SDRAM Timing Register (SDRAM_TR) ........................................................
Description of the SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) ............................
SDRAM LOAD MODE REGISTER Command ......................................................................
Refresh Urgency Levels ................................................................................................
Mapping from Logical Address to EMIF Pins for 32-bit SDRAM ..................................................
Mapping from Logical Address to EMIF Pins for 16-bit SDRAM ..................................................
Normal Mode vs. Select Strobe Mode ................................................................................
Description of the Asynchronous m Configuration Register (ASYNC_CSn_CR) ...............................
Description of the Asynchronous Wait Cycle Configuration Register (ASYNC_WCCR) ......................
Description of EMIF Interrupt Mask Set Register (INT_MSK_SET) ..............................................
Description of EMIF Interrupt Mast Clear Register (INT_MSK_CLR) ............................................
Asynchronous Read Operation in Normal Mode ....................................................................
Asynchronous Write Operation in Normal Mode ....................................................................
Asynchronous Read Operation in Select Strobe Mode ............................................................
Asynchronous Write Operation in Select Strobe Mode ............................................................
Interrupt Monitor and Control Bit Fields ..............................................................................
SR Field Value For EMIF to K4S641632H-TC(L)70 Interface.....................................................
SDRAM_TR Field Calculations for EMIF to K4S641632H-TC(L)70 Interface...................................
RR Calculation for EMIF to K4S641632H-TC(L)70 Interface .....................................................
RR Calculation for EMIF to K4S641632H-TC(L)70 Interface .....................................................
SDRAM_CR Field Values For EMIF to K4S641632H-TC(L)70 Interface ........................................
AC Characteristics for a Read Access ...............................................................................
AC Characteristics for a Write Access ...............................................................................
EMIF Base Address Table .............................................................................................
EMIF_REGS Registers .................................................................................................
EMIF_REGS Access Type Codes ....................................................................................
RCSR Register Field Descriptions ....................................................................................
ASYNC_WCCR Register Field Descriptions ........................................................................
SDRAM_CR Register Field Descriptions ............................................................................
SDRAM_RCR Register Field Descriptions...........................................................................
ASYNC_CS2_CR Register Field Descriptions ......................................................................
ASYNC_CS3_CR Register Field Descriptions ......................................................................
ASYNC_CS4_CR Register Field Descriptions ......................................................................
SDRAM_TR Register Field Descriptions .............................................................................
TOTAL_SDRAM_AR Register Field Descriptions ..................................................................
List of Tables
2522
2522
2524
2525
2525
2526
2526
2527
2528
2533
2533
2534
2536
2537
2537
2537
2538
2540
2542
2544
2547
2551
2553
2554
2554
2555
2556
2556
2559
2560
2560
2561
2562
2563
2565
2566
2568
2570
2572
2573
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
23-45. TOTAL_SDRAM_ACTR Register Field Descriptions ............................................................... 2574
23-46. SDR_EXT_TMNG Register Field Descriptions ...................................................................... 2575
23-47. INT_RAW Register Field Descriptions
...............................................................................
2576
23-48. INT_MSK Register Field Descriptions ................................................................................ 2577
23-49. INT_MSK_SET Register Field Descriptions ......................................................................... 2578
23-50. INT_MSK_CLR Register Field Descriptions ......................................................................... 2579
23-51. EMIF1_CONFIG_REGS Registers
...................................................................................
2580
23-52. EMIF1_CONFIG_REGS Access Type Codes ....................................................................... 2580
............................................................................
EMIF1COMMIT Register Field Descriptions .........................................................................
EMIF1ACCPROT0 Register Field Descriptions .....................................................................
EMIF Registers to Driverlib Functions ................................................................................
Global Signals and Mux Selection ....................................................................................
Local Signals and Mux Selection......................................................................................
Peripheral Signal Multiplexer Table ...................................................................................
Output Table .............................................................................................................
Input Table ...............................................................................................................
Ports Tied Off to Prevent Combinatorial Loops .....................................................................
Counter Block Operating Modes ......................................................................................
HLC Event List ...........................................................................................................
HLC Instruction Address Ranges .....................................................................................
Instruction Format .......................................................................................................
HLC Register Encoding ................................................................................................
Non-Memory Mapped Register Addresses ..........................................................................
CLB Base Address Table (C28) .......................................................................................
CLB_LOGIC_CONFIG_REGS Registers ............................................................................
CLB_LOGIC_CONFIG_REGS Access Type Codes................................................................
CLB_COUNT_RESET Register Field Descriptions .................................................................
CLB_COUNT_MODE_1 Register Field Descriptions ...............................................................
CLB_COUNT_MODE_0 Register Field Descriptions ...............................................................
CLB_COUNT_EVENT Register Field Descriptions .................................................................
CLB_FSM_EXTRA_IN0 Register Field Descriptions ...............................................................
CLB_FSM_EXTERNAL_IN0 Register Field Descriptions ..........................................................
CLB_FSM_EXTERNAL_IN1 Register Field Descriptions ..........................................................
CLB_FSM_EXTRA_IN1 Register Field Descriptions ...............................................................
CLB_LUT4_IN0 Register Field Descriptions.........................................................................
CLB_LUT4_IN1 Register Field Descriptions.........................................................................
CLB_LUT4_IN2 Register Field Descriptions.........................................................................
CLB_LUT4_IN3 Register Field Descriptions.........................................................................
CLB_FSM_LUT_FN1_0 Register Field Descriptions ...............................................................
CLB_FSM_LUT_FN2 Register Field Descriptions ..................................................................
CLB_LUT4_FN1_0 Register Field Descriptions .....................................................................
CLB_LUT4_FN2 Register Field Descriptions ........................................................................
CLB_FSM_NEXT_STATE_0 Register Field Descriptions .........................................................
CLB_FSM_NEXT_STATE_1 Register Field Descriptions .........................................................
CLB_FSM_NEXT_STATE_2 Register Field Descriptions .........................................................
CLB_MISC_CONTROL Register Field Descriptions ...............................................................
CLB_OUTPUT_LUT_0 Register Field Descriptions ................................................................
CLB_OUTPUT_LUT_1 Register Field Descriptions ................................................................
23-53. EMIF1LOCK Register Field Descriptions
23-54.
23-55.
23-56.
24-1.
24-2.
24-3.
24-4.
24-5.
24-6.
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
24-28.
24-29.
24-30.
24-31.
24-32.
24-33.
24-34.
24-35.
24-36.
24-37.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
2581
2582
2583
2584
2588
2590
2592
2595
2596
2596
2598
2602
2602
2603
2604
2605
2606
2607
2607
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2631
2632
77
www.ti.com
24-38. CLB_OUTPUT_LUT_2 Register Field Descriptions ................................................................ 2633
24-39. CLB_OUTPUT_LUT_3 Register Field Descriptions ................................................................ 2634
24-40. CLB_OUTPUT_LUT_4 Register Field Descriptions ................................................................ 2635
24-41. CLB_OUTPUT_LUT_5 Register Field Descriptions ................................................................ 2636
24-42. CLB_OUTPUT_LUT_6 Register Field Descriptions ................................................................ 2637
24-43. CLB_OUTPUT_LUT_7 Register Field Descriptions ................................................................ 2638
24-44. CLB_HLC_EVENT_SEL Register Field Descriptions
..............................................................
2639
24-45. CLB_LOGIC_CONTROL_REGS Registers.......................................................................... 2640
24-46. CLB_LOGIC_CONTROL_REGS Access Type Codes ............................................................. 2640
24-47. CLB_LOAD_EN Register Field Descriptions ........................................................................ 2642
2643
24-49.
2644
24-50.
24-51.
24-52.
24-53.
24-54.
24-55.
24-56.
24-57.
24-58.
24-59.
24-60.
24-61.
24-62.
24-63.
24-64.
24-65.
24-66.
24-67.
24-68.
24-69.
24-70.
24-71.
24-72.
24-73.
24-74.
24-75.
24-76.
24-77.
78
....................................................................
CLB_LOAD_DATA Register Field Descriptions .....................................................................
CLB_INPUT_FILTER Register Field Descriptions ..................................................................
CLB_IN_MUX_SEL_0 Register Field Descriptions .................................................................
CLB_LCL_MUX_SEL_1 Register Field Descriptions ...............................................................
CLB_LCL_MUX_SEL_2 Register Field Descriptions ...............................................................
CLB_BUF_PTR Register Field Descriptions.........................................................................
CLB_GP_REG Register Field Descriptions ..........................................................................
CLB_OUT_EN Register Field Descriptions ..........................................................................
CLB_GLBL_MUX_SEL_1 Register Field Descriptions .............................................................
CLB_GLBL_MUX_SEL_2 Register Field Descriptions .............................................................
CLB_INTR_TAG_REG Register Field Descriptions ................................................................
CLB_LOCK Register Field Descriptions..............................................................................
CLB_DBG_R0 Register Field Descriptions ..........................................................................
CLB_DBG_R1 Register Field Descriptions ..........................................................................
CLB_DBG_R2 Register Field Descriptions ..........................................................................
CLB_DBG_R3 Register Field Descriptions ..........................................................................
CLB_DBG_C0 Register Field Descriptions ..........................................................................
CLB_DBG_C1 Register Field Descriptions ..........................................................................
CLB_DBG_C2 Register Field Descriptions ..........................................................................
CLB_DBG_OUT Register Field Descriptions ........................................................................
CLB_DATA_EXCHANGE_REGS Registers .........................................................................
CLB_DATA_EXCHANGE_REGS Access Type Codes ............................................................
CLB_PUSH_y Register Field Descriptions...........................................................................
CLB_PULL_y Register Field Descriptions ...........................................................................
CLB_DATA_EXCHANGE_REGS Registers .........................................................................
CLB_DATA_EXCHANGE_REGS Access Type Codes ............................................................
CLB_PUSH_y Register Field Descriptions...........................................................................
CLB_PULL_y Register Field Descriptions ...........................................................................
CLB Registers to Driverlib Functions .................................................................................
24-48. CLB_LOAD_ADDR Register Field Descriptions
List of Tables
2645
2647
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2667
2667
2668
2669
2670
2670
2671
2672
2673
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Preface
SPRUHM9F – October 2014 – Revised September 2019
Read This First
This Technical Reference Manual (TRM) details the integration, the environment, the functional
description, and the programming models for each peripheral and subsystem in the device.
The TRM should not be considered a substitute for the data manual, rather a companion guide that should
be used alongside the device-specific data manual to understand the details to program the device. The
primary purpose of the TRM is to abstract the programming details of the device from the data manual.
This allows the data manual to outline the high-level features of the device without unnecessary
information about register descriptions or programming models.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers may be shown with the suffix h or the prefix 0x. For example, the following
number is 40 hexadecimal (decimal 64): 40h or 0x40.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties with default reset value below. A legend explains the notation used for the
properties.
– Reserved bits in a register figure can have one of multiple meanings:
• Not implemented on the device
• Reserved for future device expansion
• Reserved for TI testing
• Reserved configurations of the device that are not supported
– Writing nondefault values to the Reserved bits could cause unexpected behavior and should be
avoided.
Glossary
TI Glossary — This glossary lists and explains terms, acronyms, and definitions.
Related Documentation From Texas Instruments
For a complete listing of related documentation and development-support tools for these devices, visit the
Texas Instruments website at http://www.ti.com. Additionally, the TMS320C28x CPU and Instruction Set
Reference Guide (SPRU430) and TMS320C28x Floating Point Unit and Instruction Set Reference Guide
(SPRUEO2) must be used in conjunction with this TRM.
Trademarks
C2000, controlSUITE, Code Composer Studio are trademarks of Texas Instruments.
USB Specification Revision 2.0 is a trademark of Compaq Computer Corp.
C2000, controlSUITE, Code Composer Studio, are trademarks of ~ Texas Instruments.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Read This First
79
Chapter 1
SPRUHM9F – October 2014 – Revised September 2019
C2000 Software Support
C2000Ware for C2000™ Microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device
peripheral examples, C2000Ware provides a solid foundation to begin development and evaluation of your
product.
Topic
1.1
1.2
1.3
1.4
1.5
1.6
1.7
80
...........................................................................................................................
Introduction .......................................................................................................
C2000Ware Structure ..........................................................................................
Documentation ..................................................................................................
Devices .............................................................................................................
Libraries............................................................................................................
Code Composer Studio .......................................................................................
PinMUX Tool ......................................................................................................
C2000 Software Support
Page
81
81
81
81
81
81
82
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Introduction
www.ti.com
1.1
Introduction
C2000Ware for C2000™ Microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device
peripheral examples, C2000Ware provides a solid foundation to begin development and evaluation of your
product.
C2000Ware can be downloaded from: www.ti.com/tool/C2000WARE
1.2
C2000Ware Structure
The C2000Ware software package is organized into the following directory structure:
Table 1-1. C2000Ware Root Directories
Directory Name
1.3
Description
boards
Contains the hardware design schematics, BOM, gerber files, and documentation for
C2000 controlCARDS,
device_support
Contains all device-specific support files, bit field headers and device development
user's guides.
docs
Contains the C2000Ware package user's guides and the HTML index page of all
package documentation.
driverlib
Contains the device-specific driver library and driver-based peripheral examples.
libraries
Contains the device-specific and core libraries.
Documentation
Within C2000Ware, there is an extensive amount of development documentation ranging from board
design documentation, to library user's guides, to driver API documentation. The "boards" directory
contains all the hardware design, BOM, gerber files, and more for controlCARDs. To assist with locating
the necessary documentation, an HTML page is provided that contains a full list of all the documents in
the C2000Ware package. Locate this page in the "docs" directory.
1.4
Devices
C2000Ware contains the necessary software and documentation to jumpstart development for C2000
microcontrollers. Each device includes device-specific common source files, peripheral example projects,
bit field headers, and if available, a device peripheral driver library. Additionally, documentation is provided
for each device on how to set up a CCS project, as well as give an overview of all the included example
projects and assist with troubleshooting. For devices with a driver library, documentation is also included
that details all the peripheral APIs available.
To learn more about C2000 microcontrollers, visit www.ti.com/c2000.
1.5
Libraries
The libraries included in C2000Ware range from fixed point and floating point math libraries, to specialized
DSP libraries, as well as calibration libraries. Each library includes documentation and examples, where
applicable. Additionally, the flash API files and boot ROM source code are located in the "libraries"
directory.
1.6
Code Composer Studio
Code Composer Studio is an integrated development environment (IDE) that supports TI's microcontroller
and embedded processors portfolio. Code Composer Studio comprises a suite of tools used to develop
and debug embedded applications. The latest version of Code Composer Studio can be obtained at the
following link:
http://www.ti.com/ccstudio
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
C2000 Software Support
81
PinMUX Tool
www.ti.com
All projects and examples in C2000Ware are built for and tested with TI’s Code Composer Studio.
Although Code Composer Studio is not included with the C2000Ware installer, it is easily obtainable in a
variety of versions.
1.7
PinMUX Tool
The Pin MUX Utility is a software tool which provides a Graphical User Interface for configuring pin
multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs. Results are
output as C header/code files that can be imported into software development kits (SDKs) or used to
configure customer's custom software.
The latest version of the PinMux Tool can be obtained at the following link:http://dev.ti.com/
82
C2000 Software Support
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Chapter 2
SPRUHM9F – October 2014 – Revised September 2019
C28x Processor
This chapter contains a short description of the C28x Processor and extended instruction sets.
Further information can be found in the following document(s):
TMS320C28x CPU and Instruction Set Reference Guide
TMS320C28x Extended Instruction Sets Technical Reference Manual
Accelerators: Enhancing the Capabilities of the C2000 MCU Family Technical Brief
TMS320C28x FPU Primer
Topic
2.1
2.2
2.3
2.4
...........................................................................................................................
Introduction .......................................................................................................
Features ............................................................................................................
Floating-Point Unit ............................................................................................
Trigonometric Math Unit .....................................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
C28x Processor
Page
84
84
84
84
83
Introduction
2.1
www.ti.com
Introduction
The C28x CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal
processing, reduced instruction set computing (RISC), microcontroller architectures, firmware, and tool
sets.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction
Set Reference Guide.
2.2
Features
The CPU features include a modified Harvard architecture and circular addressing. The RISC features are
single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and
unpacking, and bit manipulation. The modified Harvard architecture of the CPU enables instruction and
data fetches to be performed in parallel. The CPU can read instructions and data while it writes data
simultaneously to maintain the single-cycle instruction operation across the pipeline.
2.3
Floating-Point Unit
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU
by adding registers and instructions to support IEEE single-precision floating point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point
unit registers. The additional floating-point unit registers are the following:
• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)
• Repeat Block Register (RB)
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be
used in high-priority interrupts for fast context save and restore of the floating-point registers.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual .
2.4
Trigonometric Math Unit
The TMU extends the capabilities of a C28x+FPU by adding instructions and leveraging existing FPU
instructions to speed up the execution of common trigonometric and arithmetic operations listed in
Table 2-1.
Table 2-1. TMU Supported Instructions
INSTRUCTIONS
C EQUIVALENT OPERATION
PIPELINE CYCLES
MPY2PIF32 RaH,RbH
a = b * 2pi
2/3
DIV2PIF32 RaH,RbH
a = b / 2pi
2/3
DIVF32 RaH,RbH,RcH
a = b/c
5
SQRTF32 RaH,RbH
a = sqrt(b)
5
SINPUF32 RaH,RbH
a = sin(b*2pi)
4
COSPUF32 RaH,RbH
a = cos(b*2pi)
4
ATANPUF32 RaH,RbH
a = atan(b)/2pi
4
QUADF32 RaH,RbH,RcH,RdH
Operation to assist in calculating ATANPU2
5
No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU
instructions use the existing FPU register set (R0H to R7H) to carry out their operations.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual .
84
C28x Processor
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Chapter 3
SPRUHM9F – October 2014 – Revised September 2019
System Control
This chapter explains system control and interrupts found on this MCU. The system control module
configures and manages the overall operation of the device and provides information about the device
status. Configurable features in system control include reset control, NMI operation, power control, clock
control, and low-power modes.
Topic
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
...........................................................................................................................
Page
Introduction ....................................................................................................... 86
System Control Functional Description................................................................. 86
Resets .............................................................................................................. 87
Peripheral Interrupts ........................................................................................... 89
Exceptions and Non-Maskable Interrupts ............................................................ 100
Safety Features ................................................................................................ 101
Clocking ......................................................................................................... 105
32-Bit CPU Timers 0/1/2 ..................................................................................... 114
Watchdog Timers ............................................................................................. 116
Low Power Modes ............................................................................................ 119
Memory Controller Module ................................................................................ 122
Flash and OTP Memory ..................................................................................... 129
Dual Code Security Module (DCSM) .................................................................... 140
JTAG............................................................................................................... 151
F2807x System Control Registers ....................................................................... 153
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
85
Introduction
3.1
www.ti.com
Introduction
The register space of the device system control module is divided into three categories and will be
explained further in this chapter. They are:
1. System Control Device Configuration Registers (DEV_CFG_REGS). The base address of these
registers begins at 0x5D000.
2. System Control Clock Configuration Registers (CLK_CFG_REGS). The base address of these
registers begins at 0x5D200.
3. System control CPU Subsystem Registers (CPU_SYS_REGS). The base address of these registers
begins at 0x5D300.
3.2
System Control Functional Description
The system control module provides the following capabilities:
• Device identification and configuration registers
• Reset control
• Exceptions and Interrupt control
• Safety and error handling features of the device
• Power control
• Clock control
• Low Power modes
• Security module
3.2.1 Device Identification
Device identification registers provide information on device class, device family, revision, part number, pin
count, operating temperature range, package type, and device qualification status.
All of the device information is part of the DEV_CFG_REGS space and is accessible only by the software
running on the CPU1 subsystem.
The control subsystem device identification registers are: PARTIDL, PARTIDH, and REVID.
A 256-bit Unique ID (UID) is available in UID_REGS. The 256 bits are separated into these registers:
• UID_PSRAND0-5: 192 bits of pseudo-random data
• UID_UNIQUE: 32-bit unique data, the value in this register will be unique across all devices with the
same PARTIDH
• UID_CHECKSUM: 32-bit fletcher checksum of UID_PSRAND0-5 and UID_UNIQUE
• CPU ID: 16-bit location in OTP. The value at this location provides the information about CPU (CPU1
or CPU2). Please refer to the device datasheet, for more detail.
3.2.2 Device Configuration Registers
Several registers provide users with configuration information for debug and identification purposes on this
MCU. This information includes the features of the peripheral and how much RAM and FLASH memory is
available on this part.
These registers are part of DEV_CFG_REGS space.
• DC0 – DC20: Device Configuration or Capabilities registers.
If a particular bit in these registers is set to ‘1’ then the associated/feature or module is available in the
device.
• PERCNF: Peripheral configuration register.
This register configures ADC capabilities, and enables or disables the USB internal PHY.
• CPUID: CPU identification register
86
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Resets
www.ti.com
3.3
Resets
This section explains the types and effects of the different resets on this device.
3.3.1 Reset Sources
Table 3-1 summarizes the various reset signals and their effect on the device.
Table 3-1. Reset Signals
Reset Source
CPU Core Reset
(C28x, TMU, FPU
Peripherals Reset
JTAG / Debug
Logic Reset
IOs
XRS Output
POR
Yes
Yes
Yes
Hi-Z
Yes
XRS Pin
Yes
Yes
No
Hi-Z
-
WDRS
Yes
Yes
No
Hi-Z
Yes
NMIWDRS
Yes
Yes
No
Hi-Z
Yes
SYSRS
(Debugger Reset)
Yes
Yes
No
Hi-Z
No
SCCRESET
Yes
Yes
No
Hi-Z
No
HIBRESET
Yes
Yes
Yes
Isolated
No
HWBISTRS
Yes
No
No
-
No
TRST
No
No
Yes
-
No
The resets can be divided into a few groups:
• Chip-level resets (XRS, POR, WDRS, and NMIWDRS), which reset all or almost all of the device.
• System resets (SYSRS and SCCRESET), which reset a large subset of the device but maintain some
system-level configuration.
• Special resets (HIBRESET, HWBISTRS,and TRST), which enable specific device functions.
After a reset, the reset cause register (RESC) is updated with the reset cause. The bits in this register
maintain their state across multiple resets. They can only be cleared by a power-on reset (POR) or by
writing ones to the register.
Many peripheral modules have individual resets accessible through the system control registers. For
information about a module's reset state, refer to the appropriate chapter for that module.
Note: After a POR, XRS, WDRS, NMIWDRS, or HIBRESET, the boot ROM will clear all of the system and
message RAMs.
3.3.2 External Reset (XRS)
The external reset (XRS) is the main chip-level reset for the device. It resets the CPU, all peripherals and
I/O pin configurations, and most of the system control registers. There is a dedicated open-drain pin for
XRS. This pin may be used to drive reset pins for other ICs in the application, and may itself be driven by
an external source. The XRS is driven internally during watchdog, NMI, and power-on resets. In hibernate
mode, toggling XRS will produce a HIBRESET.
The XRSn bit in the RESC register will be set whenever XRS is driven low for any reason. This bit is then
cleared by the boot ROM.
3.3.3 Power-On Reset (POR)
The power-on reset (POR) circuit creates a clean reset throughout the device during power-up,
suppressing glitches on the GPIOs. The XRS pin is held low for the duration of the POR. In most
applications, XRS is held low long enough to reset other system ICs, but some applications may require a
longer pulse. In these cases, XRS can be driven low externally to provide the correct reset duration. A
POR resets everything that XRS does, along with a few other registers – the reset cause register (RESC),
the NMI shadow flag register (NMISHDFLG), the X1 clock counter register (X1CNT), and the hibernate
configuration registers (HIBBOOTMODE, IORESTOREADDR, and LPMCR.M0M1MODE).
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
87
Resets
www.ti.com
After a POR, the POR and XRSn bits in RESC are set. These bits are then cleared by the boot ROM.
3.3.4 Debugger Reset (SYSRS)
During development, it is sometimes necessary to reset the CPU and its peripherals without disconnecting
the debugger or disrupting the system-level configuration. To facilitate this, the CPU has a subsystem
reset, which can be triggered by a debugger using Code Composer Studio. This reset (SYSRS) resets the
CPU, its peripherals, many system control registers (including its clock gating and LPM configuration), and
all I/O pin configurations.
The SYSRS does not reset the ICEPick debug module, the device capability registers, the clock source
and PLL configurations, the missing clock detection state, the PIE vector fetch error handler address, the
NMI flags, the analog trims, or anything reset only by a POR (see Section 3.3.3).
3.3.5 Watchdog Reset (WDRS)
The device has a watchdog timer that can optionally trigger a reset that lasts for 512 INTOSC1 cycles.
This watchdog reset (WDRS) produces an XRS.
After a watchdog reset, the WDRSn bit in RESC is set.
3.3.6 NMI Watchdog Reset (NMIWDRS)
The device has a non-maskable interrupt (NMI) module that detects hardware errors in the system. The
NMI module has a watchdog timer that triggers a reset if the CPU does not respond to an error within a
user-specified amount of time. This NMI watchdog reset (NMIWDRS) produces an XRS.
After an NMI watchdog reset, the NMIWDRSn bit in RESC is set.
3.3.7 DCSM Safe Code Copy Reset (SCCRESET)
The device has a dual-zone code security module (DCSM) that blocks read access to certain areas of the
flash memory. To facilitate CRC checks and copying of CLA code, TI provides ROM functions to securely
access those memory areas. To prevent security breaches, interrupts must be disabled before calling
these functions. If a vector fetch occurs in a safe copy or CRC function, the DCSM triggers a reset. The
security reset (SCCRESET) is similar to a SYSRS. However, the security reset also resets the debug logic
to deny access to a potential attacker.
After a security reset, the SCCRESETn bit in RESC is set.
3.3.8 Hibernate Reset (HIBRESET)
Hibernate is a chip-level low-power mode that gates power to large portions of the device. Waking up from
hibernate involves a special reset (HIBRESET). This reset is similar to a POR except that the I/O pins
remain isolated and the XRS pin is not toggled. (An external XRS toggle during hibernate will trigger a
HIBRESET). I/O isolation is disabled in software as part of a special boot ROM flow. For more information
on hibernate, refer to Section 3.10.
After a hibernate reset, the HIBRESETn bit in RESC is set. This bit is then cleared by the boot ROM.
3.3.9 Hardware BIST Reset (HWBISTRS)
The Hardware Built-In Self-Test (HWBIST) module tests the functionality of the CPU. At the end of the
test, it resets the CPU to return it to a working state. This reset (HWBISTRS) only affects the CPU itself.
The peripherals and system control remain as previously configured. The CPU state is restored in
software as part of a special boot ROM flow. For more information on the HWBIST flow, contact your local
TI representative.
After a HWBIST reset, the HWBISTn bit in RESC is set. This bit is then cleared by the boot ROM.
88
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Resets
www.ti.com
3.3.10 Test Reset (TRST)
The ICEPick debug module and associated JTAG logic has its own reset (TRST) which is controlled by a
dedicated pin. This reset is normally active unless the user connects a debugger to the device. For more
information on the debug module, see the TI Processors Wiki page on ICEPick:
http://processors.wiki.ti.com/index.php/ICEPICK.
The TRST does not have a normal RESC bit, but the TRSTn_pin_status bit indicates the state of the pin.
3.4
Peripheral Interrupts
This section explains the peripheral interrupt handling on the device. Non-maskable interrupts are covered
in Section 3.5. Software interrupts and emulation interrupts are not covered in this document. For
information on those, see the TMS320C28x CPU and Instruction Set Reference Guide (SPRU430).
3.4.1 Interrupt Concepts
An interrupt is a signal that causes the CPU to pause its current execution and branch to a different piece
of code known as an interrupt service routine (ISR). This is a useful mechanism for handling peripheral
events, and involves less CPU overhead or program complexity than register polling. However, because
interrupts are asynchronous to the program flow, care must be taken to avoid conflicts over resources that
are accessed both in interrupts and in the main program code.
Interrupts propagate to the CPU through a series of flag and enable registers. The flag registers store the
interrupt until it is processed. The enable registers block the propagation of the interrupt. When an
interrupt signal reaches the CPU, the CPU fetches the appropriate ISR address from a list called the
vector table.
3.4.2 Interrupt Architecture
The C28x CPU has fourteen peripheral interrupt lines. Two of them (INT13 and INT14) are connected
directly to CPU timers 1 and 2, respectively. The remaining twelve are connected to peripheral interrupt
signals through the enhanced Peripheral Interrupt Expansion module (ePIE, or PIE as a shortened
version). The PIE multiplexes up to sixteen peripheral interrupts into each CPU interrupt line. It also
expands the vector table to allow each interrupt to have its own ISR. This allows the CPU to support a
large number of peripherals.
An interrupt path is divided into three stages – the peripheral, the PIE, and the CPU. Each stage has its
own enable and flag registers. This system allows the CPU to handle one interrupt while others are
pending, implement and prioritize nested interrupts in software, and disable interrupts during certain
critical tasks.
Figure 3-1 shows the interrupt architecture for this device.
Figure 3-1. Device Interrupt Architecture
CPU1.TIMER0
LPM Logic
CPU1.WD
CPU1.LPMINT
CPU1.TINT0
CPU1.W AKEINT
CPU1.NMIWD
CPU1.W DINT
NMI
CPU1
GPIO0
GPIO1
...
...
GPIOx
INPUTXBAR4
Input
X-BAR
INPUTXBAR5
INPUTXBAR6
INPUTXBAR13
INPUTXBAR14
CPU1.XINT1 Control
CPU1.XINT2 Control
CPU1.XINT3 Control
CPU1.XINT4 Control
CPU1.XINT5 Control
INT1
to
INT12
CPU1.
ePIE
CPU1.TIMER1
CPU1.TIMER2
CPU1.TINT1
CPU1.TINT2
INT13
INT14
Peripherals
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
89
Peripheral Interrupts
3.4.2.1
www.ti.com
Peripheral Stage
Each peripheral has its own unique interrupt configuration, which is described in that peripheral's chapter.
Some peripherals allow multiple events to trigger the same interrupt signal. For example, a
communications peripheral might use the same interrupt to indicate that data has been received or that
there has been a transmission error. The cause of the interrupt can be determined by reading the
peripheral's status register. Often, the bits in the status register must be cleared manually before another
interrupt will be generated.
3.4.2.2
PIE Stage
The PIE provides individual flag and enable register bits for each of the peripheral interrupt signals, which
are sometimes called PIE channels. These channels are grouped according to their associated CPU
interrupt. Each PIE group has one 16-bit enable register (PIEIERx), one 16-bit flag register (PIEIFRx), and
one bit in the PIE acknowledge register (PIEACK). The PIEACK register bit acts as a common interrupt
mask for the entire PIE group.
When the CPU receives an interrupt, it fetches the address of the ISR from the PIE. The PIE returns the
vector for the lowest-numbered channel in the group that is both flagged and enabled. This gives lowernumbered interrupts a higher priority when multiple interrupts are pending.
If no interrupt is both flagged and enabled, the PIE returns the vector for channel 1. This condition will not
happen unless software changes the state of the PIE while an interrupt is propagating. Section 3.4.4
contains procedures for safely modifying the PIE configuration once interrupts have been enabled.
3.4.2.3
CPU Stage
Like the PIE, the CPU provides flag and enable register bits for each of its interrupts. There is one enable
register (IER) and one flag register (IFR), both of which are internal CPU registers. There is also a global
interrupt mask, which is controlled by the INTM bit in the ST1 register. This mask can be set and cleared
using the CPU's SETC instruction. In C code, controlSUITE's DINT and EINT macros can be used for this
purpose.
Writes to IER and INTM are atomic operations. In particular, if INTM is cleared, the next instruction in the
pipeline will run with interrupts disabled. No software delays are needed.
3.4.3 Interrupt Entry Sequence
Figure 3-2 shows how peripheral interrupts propagate to the CPU.
Figure 3-2. Interrupt Propagation Path
PIEIERx.1
Peripheral
Interrupt
A
0
PIEIFRx.1
Latch
1
PIEIERx.2
Peripheral
Interrupt
B
Set
0
PIEIFRx.2
Latch
1
PIEACK.x
IER.x
1
ST1.INTM
1
0
0
IFR.x
Latch
1
0
CPU
Interrupt
Logic
PIEIERx.16
Peripheral
Interrupt
P
90
0
PIEIFRx.16
Latch
System Control
1
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Peripheral Interrupts
www.ti.com
When a peripheral generates an interrupt (on PIE group x, channel y), it triggers the following sequence of
events:
1. The interrupt is latched in PIEIFRx.y.
2. If PIEIERx.y is set, the interrupt propagates.
3. If PIEACK.x is clear, the interrupt propagates and PIEACK.x is set.
4. The interrupt is latched in IFR.x.
5. If IER.x is set, the interrupt propagates.
6. If INTM is clear, the CPU receives the interrupt.
7. Any instructions in the D2 or later stage of the pipeline are run to completion. Instructions in earlier
stages are flushed.
8. The CPU saves its context on the stack.
9. IFR.x and IER.x are cleared. INTM is set. EALLOW is cleared.
10. The CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared.
11. The CPU branches to the ISR.
The interrupt latency is the time between PIEIFRx.y latching the interrupt and the first ISR instruction
entering the execution stage of the CPU pipeline. The minimum interrupt latency is 14 SYSCLK cycles.
Wait states on the ISR or stack memories will add to the latency. External interrupts add a minimum of two
SYSCLK cycles for GPIO synchronization plus extra time for input qualification (if used). Loops created
using the C28x RPT instruction cannot be interrupted.
3.4.4 Configuring and Using Interrupts
At power-up, no interrupts are enabled by default. The PIEIER and IER registers are cleared and INTM is
set. The application code is responsible for configuring and enabling all peripheral interrupts.
3.4.4.1
To
1.
2.
3.
4.
5.
6.
7.
Enabling Interrupts
enable a peripheral interrupt, perform the following steps:
Disable interrupts globally (DINT or SETC INTM).
Enable the PIE by setting the ENPIE bit of the PIECTRL register.
Write the ISR vector for each interrupt to the appropriate location in the PIE vector table, which can be
found in Table 3-2.
Set the appropriate PIEIERx bit for each interrupt. The PIE group and channel assignments can be
found in Table 3-2.
Set the CPU IER bit for any PIE group containing enabled interrupts.
Enable the interrupt in the peripheral.
Enable interrupts globally (EINT or CLRC INTM).
Step 4 does not apply to the Timer1 and Timer2 interrupts, which connect directly to the CPU.
3.4.4.2
Handling Interrupts
ISRs are similar to normal functions, but must do the following:
1. Save and restore the state of certain CPU registers (if used).
2. Clear the PIEACK bit for the interrupt group.
3. Return using the IRET instruction.
Requirements 1 and 3 are handled automatically by the TMS320C28x C compiler if the function is defined
using the __interrupt keyword. For information on this keyword, see the Keywords section of the
TMS320C28x Optimizing C/C++ Compiler v6.2.4 User's Guide (SPRU514). For information on writing
assembly code to handle interrupts, see the Standard Operation for Maskable Interrupts section of the
TMS320C28x CPU and Instruction Set Reference Guide (SPRU430).
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
91
Peripheral Interrupts
www.ti.com
The PIEACK bit for the interrupt group must be cleared manually in user code. This is normally done at
the end of the ISR. If the PIEACK bit is not cleared, the CPU will not receive any further interrupts from
that group. This does not apply to the Timer1 and Timer2 interrupts, which do not go through the PIE.
3.4.4.3
Disabling Interrupts
To disable all interrupts, set the CPU's global interrupt mask via DINT or SETC INTM. It is not necessary
to add NOPs after setting INTM or modifying IER – the next instruction will execute with interrupts
disabled.
Individual interrupts can be disabled using the PIEIERx registers, but care must be taken to avoid race
conditions. If an interrupt signal is already propagating when the PIEIER write completes, it may reach the
CPU and trigger a spurious interrupt condition. To avoid this, use the following procedure:
1. Disable interrupts globally (DINT or SETC INTM).
2. Clear the PIEIER bit for the interrupt.
3. Wait 5 cycles to make sure that any propagating interrupt has reached the CPU IFR register.
4. Clear the CPU IFR bit for the interrupt's PIE group.
5. Clear the PIEACK bit for the interrupt's PIE group.
6. Enable interrupts globally (EINT or CLRC INTM).
Interrupt groups can be disabled using the CPU IER register. This cannot cause a race condition, so no
special procedure is needed.
PIEIFR bits must never be cleared in software since the read/modify/write operation may cause incoming
interrupts to be lost. The only safe way to clear a PIEIFR bit is to have the CPU take the interrupt. The
following procedure can be used to bypass the normal ISR:
1. Disable interrupts globally (DINT or SETC INTM).
2. Modify the PIE vector table to map the PIEIFR bit's interrupt vector to an empty ISR. This ISR will only
contain a return from interrupt instruction (IRET).
3. Disable the interrupt in the peripheral registers.
4. Enable interrupts globally (EINT or CLRC INTM).
5. Wait for the pending interrupt to be serviced by the empty ISR.
6. Disable interrupts globally.
7. Modify the PIE vector table to map the interrupt vector back to its original ISR.
8. Clear the PIEACK bit for the interrupt's PIE group.
9. Enable interrupts globally.
3.4.4.4
Nesting Interrupts
By default, interrupts do not nest. It is possible to nest and prioritize interrupts via software control of the
IER and PIEIERx registers. Documentation and example code can be found in controlSUITE and on the TI
Processors wiki:
http://processors.wiki.ti.com/index.php/Interrupt_Nesting_on_C28x
92
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Peripheral Interrupts
www.ti.com
3.4.5 PIE Channel Mapping
Table 3-2 shows the PIE group and channel assignments for each peripheral interrupt. Each row is a group, and each column is a channel within
that group. When multiple interrupts are pending, the lowest-numbered channel is the lowest-numbered group is serviced first. Thus, the interrupts
at the top of the table have the highest priority, and the interrupts at the bottom have the lowest priority.
Table 3-2. PIE Channel Mapping
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
INTx.9
INTx.10
INTx.11
INTx.12
INT1.y
ADCA1
ADCB1
-
XINT1
XINT2
ADCD1
TIMER0
WAKE
-
-
-
-
INTx.13
INTx.14
INTx.15
INTx.16
INT2.y
EPWM1_
TZ
EPWM2_
TZ
EPWM3_
TZ
EPWM4_
TZ
EPWM5_
TZ
EPWM6_
TZ
EPWM7_
TZ
EPWM8_
TZ
EPWM9_
TZ
EPWM10_
TZ
EPWM11_
TZ
EPWM12_
TZ
-
-
-
-
INT3.y
EPWM1
EPWM2
EPWM3
EPWM4
EPWM5
EPWM6
EPWM7
EPWM8
EPWM9
EPWM10
INT4.y
ECAP1
ECAP2
ECAP3
ECAP4
ECAP5
ECAP6
-
-
-
-
EPWM11
EPWM12
-
-
-
-
-
-
-
-
-
INT5.y
EQEP1
EQEP2
EQEP3
-
CLB1
CLB2
CLB3
CLB4
SD1
-
SD2
-
-
-
-
-
INT6.y
SPIA_RX
SPIA_TX
SPIB_RX
SPIB_TX
MCBSPA_
RX
MCBSPA_
TX
MCBSPB_
RX
MCBSPB_
TX
-
SPIC_RX
SPIC_TX
-
-
-
-
-
-
INT7.y
DMA_CH1
DMA_CH2
DMA_CH3
DMA_CH4
DMA_CH5
DMA_CH6
-
INT8.y
I2CA
I2CA_
FIFO
I2CB
I2CB_
FIFO
SCIC_RX
SCIC_TX
SCID_RX
-
-
-
-
-
-
-
-
-
SCID_TX
-
-
-
-
-
-
UPPA
-
INT9.y
SCIA_RX
SCIA_TX
SCIB_RX
SCIB_TX
CANA_0
CANA_1
CANB_0
CANB_1
-
-
-
-
-
-
USBA
-
INT10.y
ADCA_
EVT
ADCA2
ADCA3
ADCA4
ADCB_EVT
ADCB2
ADCB3
ADCB4
-
-
-
-
ADCD_EVT
ADCD2
ADCD3
ADCD4
INT11.y
CLA1_1
CLA1_2
CLA1_3
CLA1_4
CLA1_5
CLA1_6
CLA1_7
CLA1_8
-
-
-
-
-
-
-
-
INT12.y
XINT3
XINT4
XINT5
-
-
FPU_OVER
FLOW
FPU_
UNDER
FLOW
EMIF_
ERROR
RAM_COR
RECTABLE
_ERROR
FLASH_CO
RRECTABL
E_ERROR
RAM_ACCE
SS_VIOLAT
ION
SYS_PLL_
SLIP
AUX_PLL_
SLIP
CLA OVER
FLOW
CLA
UNDER
FLOW
Note: Cells marked "-" are Reserved
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
System Control
Copyright © 2014–2019, Texas Instruments Incorporated
93
Peripheral Interrupts
www.ti.com
3.4.6 Vector Tables
Table 3-3 shows the CPU interrupt vector table. The vectors for INT1 – INT12 are not used in this device.
The reset vector is fetched from the boot ROM instead of from this table.
Table 3-3. CPU Interrupt Vectors
94
Name
Vector ID
Address
Size (x16)
Description
Core priority
ePIE group
Priority
Reset
0
0x0000 0D00
2
Reset is always fetched from
location 0x003F_FFC0 in Boot
ROM
1 (Highest)
-
INT1
1
0x0000 0D02
2
Not used. See PIE Group 1
5
-
INT2
2
0x0000 0D04
2
Not used. See PIE Group 2
6
-
INT3
3
0x0000 0D06
2
Not used. See PIE Group 3
7
-
INT4
4
0x0000 0D08
2
Not used. See PIE Group 4
8
-
INT5
5
0x0000 0D0A
2
Not used. See PIE Group 5
9
-
INT6
6
0x0000 0D0C
2
Not used. See PIE Group 6
10
-
INT7
7
0x0000 0D0E
2
Not used. See PIE Group 7
11
-
INT8
8
0x0000 0D10
2
Not used. See PIE Group 8
12
-
INT9
9
0x0000 0D12
2
Not used. See PIE Group 9
13
-
INT10
10
0x0000 0D14
2
Not used. See PIE Group 10
14
-
INT11
11
0x0000 0D16
2
Not used. See PIE Group 11
15
-
INT12
12
0x0000 0D18
2
Not used. See PIE Group 12
16
-
INT13
13
0x0000 0D1A
2
CPU TIMER1 Interrupt
17
-
INT14
14
0x0000 0D1C
2
CPU TIMER2 Interrupt (for
TI/RTOS use)
18
-
DATALOG
15
0x0000 0D1E
2
CPU Data Logging Interrupt
19 (lowest)
-
RTOSINT
16
0x0000 0D20
2
CPU Real-Time OS Interrupt
4
-
EMUINT
17
0x0000 0D22
2
CPU Emulation Interrupt
2
-
NMI
18
0x0000 0D24
2
Non-Maskable Interrupt
3
-
ILLEGAL
19
0x0000 0D26
2
Illegal Instruction (ITRAP)
-
-
USER 1
20
0x0000 0D28
2
User-Defined Trap
-
-
USER 2
21
0x0000 0D2A
2
User-Defined Trap
-
-
USER 3
22
0x0000 0D2C
2
User-Defined Trap
-
-
USER 4
23
0x0000 0D2E
2
User-Defined Trap
-
-
USER 5
24
0x0000 0D30
2
User-Defined Trap
-
-
USER 6
25
0x0000 0D32
2
User-Defined Trap
-
-
USER 7
26
0x0000 0D34
2
User-Defined Trap
-
-
USER 8
27
0x0000 0D36
2
User-Defined Trap
-
-
USER 9
28
0x0000 0D38
2
User-Defined Trap
-
-
USER 10
29
0x0000 0D3A
2
User-Defined Trap
-
-
USER 11
30
0x0000 0D3C
2
User-Defined Trap
-
-
USER 12
31
0x0000 0D3E
2
User-Defined Trap
-
-
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Peripheral Interrupts
www.ti.com
Table 3-4 shows the Pie vector table.
Table 3-4. PIE Interrupt Vectors
Name
Vector ID
Address
Size (x16)
Description
Core priority
ePIE group
Priority
PIE Group 1 Vectors - Muxed into CPU INT1
INT1.1
32
0x0000 0D40
2
ADCA1 interrupt
5
1 (Highest)
INT1.2
33
0x0000 0D42
2
ADCB1 interrupt
5
2
INT1.3
34
0x0000 0D44
2
Reserved
5
3
INT1.4
35
0x0000 0D46
2
XINT1 interrupt
5
4
INT1.5
36
0x0000 0D48
2
XINT2 interrupt
5
5
INT1.6
37
0x0000 0D4A
2
ADCD1 interrupt
5
6
INT1.7
38
0x0000 0D4C
2
TIMER0 interrupt
5
7
INT1.8
39
0x0000 0D4E
2
WAKE interrupt
5
8
INT1.9
128
0x0000 0E00
2
Reserved
5
9
INT1.10
129
0x0000 0E02
2
Reserved
5
10
INT1.11
130
0x0000 0E04
2
Reserved
5
11
INT1.12
131
0x0000 0E06
2
Reserved
5
12
INT1.13
132
0x0000 0E08
2
IPC1 interrupt
5
13
INT1.14
133
0x0000 0E0A
2
IPC2 interrupt
5
14
INT1.15
134
0x0000 0E0C
2
IPC3 interrupt
5
15
INT1.16
135
0x0000 0E0E
2
IPC4 interrupt
5
16 (Lowest)
PIE Group 2 Vectors - Muxed into CPU INT2
INT2.1
40
0x0000 0D50
2
EPWM1_TZ
interrupt
6
1 (Highest)
INT2.2
41
0x0000 0D52
2
EPWM2_TZ
interrupt
6
2
INT2.3
42
0x0000 0D54
2
EPWM3_TZ
interrupt
6
3
INT2.4
43
0x0000 0D56
2
EPWM4_TZ
interrupt
6
4
INT2.5
44
0x0000 0D58
2
EPWM5_TZ
interrupt
6
5
INT2.6
45
0x0000 0D5A
2
EPWM6_TZ
interrupt
6
6
INT2.7
46
0x0000 0D5C
2
EPWM7_TZ
interrupt
6
7
INT2.8
47
0x0000 0D5E
2
EPWM8_TZ
interrupt
6
8
INT2.9
136
0x0000 0E10
2
EPWM9_TZ
interrupt
6
9
INT2.10
137
0x0000 0E12
2
EPWM10_TZ
interrupt
6
10
INT2.11
138
0x0000 0E14
2
EPWM11_TZ
interrupt
6
11
INT2.12
139
0x0000 0E16
2
EPWM12_TZ
interrupt
6
12
INT2.13
140
0x0000 0E18
2
Reserved
6
13
INT2.14
141
0x0000 0E1A
2
Reserved
6
14
INT2.15
142
0x0000 0E1C
2
Reserved
6
15
INT2.16
143
0x0000 0E1E
2
Reserved
6
16 (Lowest)
PIE Group 3 Vectors - Muxed into CPU INT3
INT3.1
48
0x0000 0D60
2
EPWM1 interrupt
7
1 (Highest)
INT3.2
49
0x0000 0D62
2
EPWM2 interrupt
7
2
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
95
Peripheral Interrupts
www.ti.com
Table 3-4. PIE Interrupt Vectors (continued)
Name
Vector ID
Address
Size (x16)
Description
Core priority
ePIE group
Priority
INT3.3
50
0x0000 0D64
2
EPWM3 interrupt
7
3
INT3.4
51
0x0000 0D66
2
EPWM4 interrupt
7
4
INT3.5
52
0x0000 0D68
2
EPWM5 interrupt
7
5
INT3.6
53
0x0000 0D6A
2
EPWM6 interrupt
7
6
INT3.7
54
0x0000 0D6C
2
EPWM7 interrupt
7
7
INT3.8
55
0x0000 0D6E
2
EPWM8 interrupt
7
8
INT3.9
144
0x0000 0E20
2
EPWM9 interrupt
7
9
INT3.10
145
0x0000 0E22
2
EPWM10
interrupt
7
10
INT3.11
146
0x0000 0E24
2
EPWM11
interrupt
7
11
INT3.12
147
0x0000 0E26
2
EPWM12
interrupt
7
12
INT3.13
148
0x0000 0E28
2
Reserved
7
13
INT3.14
149
0x0000 0E2A
2
Reserved
7
14
INT3.15
150
0x0000 0E2C
2
Reserved
7
15
INT3.16
151
0x0000 0E2E
2
Reserved
7
16 (Lowest)
PIE Group 4 Vectors - Muxed into CPU INT4
INT4.1
56
0x0000 0D70
2
ECAP1 interrupt
8
1 (Highest)
INT4.2
57
0x0000 0D72
2
ECAP2 interrupt
8
2
INT4.3
58
0x0000 0D74
2
ECAP3 interrupt
8
3
INT4.4
59
0x0000 0D76
2
ECAP4 interrupt
8
4
INT4.5
60
0x0000 0D78
2
ECAP5 interrupt
8
5
INT4.6
61
0x0000 0D7A
2
ECAP6 interrupt
8
6
INT4.7
62
0x0000 0D7C
2
Reserved
8
7
INT4.8
63
0x0000 0D7E
2
Reserved
8
8
INT4.9
152
0x0000 0E30
2
Reserved
8
9
INT4.10
153
0x0000 0E32
2
Reserved
8
10
INT4.11
154
0x0000 0E34
2
Reserved
8
11
INT4.12
155
0x0000 0E36
2
Reserved
8
12
INT4.13
156
0x0000 0E38
2
Reserved
8
13
INT4.14
157
0x0000 0E3A
2
Reserved
8
14
INT4.15
158
0x0000 0E3C
2
Reserved
8
15
INT4.16
159
0x0000 0E3E
2
Reserved
8
16 (Lowest)
PIE Group 5 Vectors - Muxed into CPU INT5
96
INT5.1
64
0x0000 0D80
2
EQEP1 interrupt
9
1 (Highest)
INT5.2
65
0x0000 0D82
2
EQEP2 interrupt
9
2
INT5.3
66
0x0000 0D84
2
EQEP3 interrupt
9
3
INT5.4
67
0x0000 0D86
2
Reserved
9
4
INT5.5
68
0x0000 0D88
2
CLB1 Interrupt
9
5
INT5.6
69
0x0000 0D8A
2
CLB2 Interrupt
9
6
INT5.7
70
0x0000 0D8C
2
CLB3 Interrupt
9
7
INT5.8
71
0x0000 0D8E
2
CLB4 Interrupt
9
8
INT5.9
160
0x0000 0E40
2
SD1 interrupt
9
9
INT5.10
161
0x0000 0E42
2
SD2 interrupt
9
10
INT5.11
162
0x0000 0E44
2
Reserved
9
11
INT5.12
163
0x0000 0E46
2
Reserved
9
12
INT5.13
164
0x0000 0E48
2
Reserved
9
13
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Peripheral Interrupts
www.ti.com
Table 3-4. PIE Interrupt Vectors (continued)
Name
Vector ID
Address
Size (x16)
Description
Core priority
ePIE group
Priority
INT5.14
INT5.15
165
0x0000 0E4A
2
Reserved
9
14
166
0x0000 0E4C
2
Reserved
9
INT5.16
15
167
0x0000 0E4E
2
Reserved
9
16 (Lowest)
PIE Group 6 Vectors - Muxed into CPU INT6
INT6.1
72
0x0000 0D90
2
SPIA_RX
interrupt
10
1 (Highest)
INT6.2
73
0x0000 0D92
2
SPIA_TX
interrupt
10
2
INT6.3
74
0x0000 0D94
2
SPIB_RX
interrupt
10
3
INT6.4
75
0x0000 0D96
2
SPIB_TX
interrupt
10
4
INT6.5
76
0x0000 0D98
2
MCBSPA_RX
interrupt
10
5
INT6.6
77
0x0000 0D9A
2
MCBSPA_TX
interrupt
10
6
INT6.7
78
0x0000 0D9C
2
MCBSPB_RX
interrupt
10
7
INT6.8
79
0x0000 0D9E
2
MCBSPB_TX
interrupt
10
8
INT6.9
168
0x0000 0E50
2
SPIC_RX
interrupt
10
9
INT6.10
169
0x0000 0E52
2
SPIC_TX
interrupt
10
10
INT6.11
170
0x0000 0E54
2
Reserved
10
11
INT6.12
171
0x0000 0E56
2
Reserved
10
12
INT6.13
172
0x0000 0E58
2
Reserved
10
13
INT6.14
173
0x0000 0E5A
2
Reserved
10
14
INT6.15
174
0x0000 0E5C
2
Reserved
10
15
INT6.16
175
0x0000 0E5E
2
Reserved
10
16 (Lowest)
PIE Group 7 Vectors - Muxed into CPU INT7
INT7.1
80
0x0000 0DA0
2
DMA_CH1
interrupt
11
1 (Highest)
INT7.2
81
0x0000 0DA2
2
DMA_CH2
interrupt
11
2
INT7.3
82
0x0000 0DA4
2
DMA_CH3
interrupt
11
3
INT7.4
83
0x0000 0DA6
2
DMA_CH4
interrupt
11
4
INT7.5
84
0x0000 0DA8
2
DMA_CH5
interrupt
11
5
INT7.6
85
0x0000 0DAA
2
DMA_CH6
interrupt
11
6
INT7.7
86
0x0000 0DAC
2
Reserved
11
7
INT7.8
87
0x0000 0DAE
2
Reserved
11
8
INT7.9
176
0x0000 0E60
2
Reserved
11
9
INT7.10
177
0x0000 0E62
2
Reserved
11
10
INT7.11
178
0x0000 0E64
2
Reserved
11
11
INT7.12
179
0x0000 0E66
2
Reserved
11
12
INT7.13
180
0x0000 0E68
2
Reserved
11
13
INT7.14
181
0x0000 0E6A
2
Reserved
11
14
INT7.15
182
0x0000 0E6C
2
Reserved
11
15
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
97
Peripheral Interrupts
www.ti.com
Table 3-4. PIE Interrupt Vectors (continued)
Name
Vector ID
Address
Size (x16)
Description
Core priority
ePIE group
Priority
INT7.16
183
0x0000 0E6E
2
Reserved
11
16 (Lowest)
PIE Group 8 Vectors - Muxed into CPU INT8
INT8.1
88
0x0000 0DB0
2
I2CA interrupt
12
1 (Highest)
INT8.2
89
0x0000 0DB2
2
I2CA_FIFO
interrupt
12
2
INT8.3
90
0x0000 0DB4
2
I2CB interrupt
12
3
INT8.4
91
0x0000 0DB6
2
I2CB_FIFO
interrupt
12
4
INT8.5
92
0x0000 0DB8
2
SCIC_RX
interrupt
12
5
INT8.6
93
0x0000 0DBA
2
SCIC_TX
interrupt
12
6
INT8.7
94
0x0000 0DBC
2
SCID_RX
interrupt
12
7
INT8.8
95
0x0000 0DBE
2
SCID_TX
interrupt
12
8
INT8.9
184
0x0000 0E70
2
Reserved
12
9
INT8.10
185
0x0000 0E72
2
Reserved
12
10
INT8.11
186
0x0000 0E74
2
Reserved
12
11
INT8.12
187
0x0000 0E76
2
Reserved
12
12
INT8.13
188
0x0000 0E78
2
Reserved
12
13
INT8.14
189
0x0000 0E7A
2
Reserved
12
14
INT8.15
190
0x0000 0E7C
2
UPPA interrupt
(CPU1 only)
12
15
INT8.16
191
0x0000 0E7E
2
Reserved
12
16 (Lowest)
PIE Group 9 Vectors - Muxed into CPU INT9
INT9.1
96
0x0000 0DC0
2
SCIA_RX
interrupt
13
1 (Highest)
INT9.2
97
0x0000 0DC2
2
SCIA_TX
interrupt
13
2
INT9.3
98
0x0000 0DC4
2
SCIB_RX
interrupt
13
3
INT9.4
99
0x0000 0DC6
2
SCIB_TX
interrupt
13
4
INT9.5
100
0x0000 0DC8
2
CANA interrupt 0
13
5
INT9.6
101
0x0000 0DCA
2
CANA interrupt 1
13
6
INT9.7
102
0x0000 0DCC
2
CANB interrupt 0
13
7
INT9.8
103
0x0000 0DCE
2
CANB interrupt 1
13
8
INT9.9
192
0x0000 0E80
2
Reserved
13
9
INT9.10
193
0x0000 0E82
2
Reserved
13
10
INT9.11
194
0x0000 0E84
2
Reserved
13
11
INT9.12
195
0x0000 0E86
2
Reserved
13
12
INT9.13
196
0x0000 0E88
2
Reserved
13
13
INT9.14
197
0x0000 0E8A
2
Reserved
13
14
INT9.15
198
0x0000 0E8C
2
USBA interrupt
(CPU1 only)
13
15
INT9.16
199
0x0000 0E8E
2
Reserved
13
16 (Lowest)
PIE Group 10 Vectors - Muxed into CPU INT10
98
INT10.1
104
0x0000 0DD0
2
ADCA_EVT
interrupt
14
1 (Highest)
INT10.2
105
0x0000 0DD2
2
ADCA2 interrupt
14
2
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Peripheral Interrupts
www.ti.com
Table 3-4. PIE Interrupt Vectors (continued)
Name
Vector ID
Address
Size (x16)
Description
Core priority
ePIE group
Priority
INT10.3
106
0x0000 0DD4
2
ADCA3 interrupt
14
3
INT10.4
107
0x0000 0DD6
2
ADCA4 interrupt
14
4
INT10.5
108
0x0000 0DD8
2
ADCB_EVT
interrupt
14
5
INT10.6
109
0x0000 0DDA
2
ADCB2 interrupt
14
6
INT10.7
110
0x0000 0DDC
2
ADCB3 interrupt
14
7
INT10.8
111
0x0000 0DDE
2
ADCB4 interrupt
14
8
INT10.9
200
0x0000 0E90
2
Reserved
14
9
INT10.10
201
0x0000 0E92
2
Reserved
14
10
INT10.11
202
0x0000 0E94
2
Reserved
14
11
INT10.12
203
0x0000 0E96
2
Reserved
14
12
INT10.13
204
0x0000 0E98
2
ADCD_EVT
interrupt
14
13
INT10.14
205
0x0000 0E9A
2
ADCD2 interrupt
14
14
INT10.15
206
0x0000 0E9C
2
ADCD3 interrupt
14
15
INT10.16
207
0x0000 0E9E
2
ADCD4 interrupt
14
16 (Lowest)
PIE Group 11 Vectors - Muxed into CPU INT11
INT11.1
112
0x0000 0DE0
2
CLA1_1 interrupt
15
1 (Highest)
INT11.2
113
0x0000 0DE2
2
CLA1_2 interrupt
15
2
INT11.3
114
0x0000 0DE4
2
CLA1_3 interrupt
15
3
INT11.4
115
0x0000 0DE6
2
CLA1_4 interrupt
15
4
INT11.5
116
0x0000 0DE8
2
CLA1_5 interrupt
15
5
INT11.6
117
0x0000 0DEA
2
CLA1_6 interrupt
15
6
INT11.7
118
0x0000 0DEC
2
CLA1_7 interrupt
15
7
INT11.8
119
0x0000 0DEE
2
CLA1_8 interrupt
15
8
INT11.9
208
0x0000 0EA0
2
Reserved
15
9
INT11.10
209
0x0000 0EA2
2
Reserved
15
10
INT11.11
210
0x0000 0EA4
2
Reserved
15
11
INT11.12
211
0x0000 0EA6
2
Reserved
15
12
INT11.13
212
0x0000 0EA8
2
Reserved
15
13
INT11.14
213
0x0000 0EAA
2
Reserved
15
14
INT11.15
214
0x0000 0EAC
2
Reserved
15
15
INT11.16
215
0x0000 0EAE
2
Reserved
15
16 (Lowest)
PIE Group 12 Vectors - Muxed into CPU INT12
INT12.1
120
0x0000 0DF0
2
XINT3 interrupt
16
1 (Highest)
INT12.2
121
0x0000 0DF2
2
XINT4 interrupt
16
2
INT12.3
122
0x0000 0DF4
2
XINT5 interrupt
16
3
INT12.4
123
0x0000 0DF6
2
Reserved
16
4
INT12.5
124
0x0000 0DF8
2
Reserved
16
5
INT12.6
125
0x0000 0DFA
2
16
6
INT12.7
126
0x0000 0DFC
2
FPU_OVERFLO
W interrupt
16
7
INT12.8
127
0x0000 0DFE
2
FPU_UNDERFL
OW interrupt
16
8
INT12.9
216
0x0000 0EB0
2
EMIF_ERROR
interrupt
16
9
INT12.10
217
0x0000 0EB2
2
RAM_CORREC
TABLE_ERROR
interrupt
16
10
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
99
Exceptions and Non-Maskable Interrupts
www.ti.com
Table 3-4. PIE Interrupt Vectors (continued)
3.5
Name
Vector ID
Address
Size (x16)
Description
Core priority
ePIE group
Priority
INT12.11
218
0x0000 0EB4
2
FLASH_CORRE
CTABLE_ERRO
R interrupt
16
11
INT12.12
219
0x0000 0EB6
2
RAM_ACCESS_
VIOLATION
interrupt
16
12
INT12.13
220
0x0000 0EB8
2
SYS_PLL_SLIP
interrupt
16
13
INT12.14
221
0x0000 0EBA
2
AUX_PLL_SLIP
interrupt
16
14
INT12.15
222
0x0000 0EBC
2
CLA_OVERFLO
W interrupt
16
15
INT12.16
223
0x0000 0EBE
2
CLA_UNDERFL
OW interrupt
16
16 (Lowest)
Exceptions and Non-Maskable Interrupts
This section describes system-level error conditions that can trigger a non-maskable interrupt (NMI). The
interrupt allows the application to respond to the error.
3.5.1 Configuring and Using NMIs
An incoming NMI sets a status bit in the NMIFLG register and starts the NMI watchdog counter. This
counter is clocked by the SYSCLK, and if it reaches the value in the NMIWDPRD register, it triggers an
NMI watchdog reset (NMIWDRS). To prevent this, the NMI handler must clear the flag bit using the
NMIFLGCLR register. Once all flag bits are clear, the NMIINT bit in the NMIFLG register may also be
cleared to allow future NMIs to be taken.
The NMI module is enabled by the boot ROM during the startup process. To respond to NMIs, an NMI
handler vector must be written to the PIE vector table.
3.5.2 Emulation Considerations
The NMI watchdog counter behaves as follows under debug conditions:
CPU Suspended
Run-Free Mode
Real-Time Single-Step Mode
Real-Time Run-Free Mode
When the CPU is suspended, the NMI watchdog counter will
be suspended.
When the CPU is placed in run-free mode, the NMI watchdog
counter will resume operation as normal.
When the CPU is in real-time single-step mode, the NMI
watchdog counter will be suspended. The counter remains
suspended even within real-time interrupts.
When the CPU is in real-time run-free mode, the NMI
watchdog counter operates as normal.
3.5.3 NMI Sources
There are several types of hardware errors that can trigger an NMI. Additional information about the error
is usually available from the module that detects it.
3.5.3.1
Missing Clock Detection
The missing clock detection logic monitors OSCCLK for failure. If the OSCCLK source stops, the PLL is
bypassed, OSCCLK is connected to INTOSC1, and an NMI is fired to the CPU. For more information on
missing clock detection, see Section 3.6.2.
100
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Exceptions and Non-Maskable Interrupts
www.ti.com
3.5.3.2
RAM Uncorrectable ECC Error
A single-bit parity error, double-bit ECC data error, or single-bit ECC address error in a RAM read will
trigger an NMI. This applies to CPU, CLA, and DMA reads. Single-bit ECC data errors do not trigger an
NMI, but can optionally trigger a normal peripheral interrupt. For more information on RAM error detection,
see Section 3.11.1.7.
3.5.3.3
Flash Uncorrectable ECC Error
A double-bit ECC data error or single-bit ECC address error in a flash read will trigger an NMI. Single-bit
ECC data errors do not trigger an NMI, but can optionally trigger a normal peripheral interrupt. For more
information on flash error detection, see Section 3.12.10.
3.5.4 Illegal Instruction Trap (ITRAP)
If the CPU tries to execute an illegal instruction, it generates a special interrupt called an illegal instruction
trap (ITRAP). This interrupt is non-maskable and has its own vector in the PIE vector table. For more
information about ITRAPs, see the Illegal-Instruction Trap section of the TMS320C28x DSP CPU and
Instruction Set Reference Guide (SPRU430).
NOTE: A RAM fetch access violation will trigger an ITRAP in addition to the normal peripheral
interrupt for RAM access violations. The CPU will handle the ITRAP first.
3.6
Safety Features
This section gives details on features that monitor device operation during run-time to detect any error in
operation.
3.6.1 Write Protection on Registers
3.6.1.1
LOCK Protection on System Configuration Registers
Several system configuration registers are protected from spurious CPU writes by “LOCK” registers. Once
these associated LOCK register bits are set the respective locked registers can no longer be modified by
software. See specific register descriptions for details.
3.6.1.2
EALLOW Protection
Several control registers are protected from spurious CPU writes by the EALLOW protection mechanism.
The EALLOW bit in status register 1 (ST1) indicates the state of protection as shown in Table 3-5.
Table 3-5. Access to EALLOW-Protected Registers
(1)
EALLOW Bit
CPU Writes
CPU Reads
JTAG Writes
JTAG Reads
0
Ignored
Allowed
Allowed (1)
Allowed
1
Allowed
Allowed
Allowed
Allowed
The EALLOW bit is overridden via the JTAG port, allowing full access of protected registers during debug from the Code
Composer Studio interface.
At reset, the EALLOW bit is cleared, enabling EALLOW protection. While protected, all writes to protected
registers by the CPU are ignored and only CPU reads, JTAG reads, and JTAG writes are allowed. If this
bit is set, by executing the EALLOW instruction, the CPU is allowed to write freely to protected registers.
After modifying registers, they can once again be protected by executing the EDIS instruction to clear the
EALLOW bit.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
101
Safety Features
www.ti.com
3.6.2 Missing Clock Detection Logic
The missing clock detect (MCD) logic detects OSCCLK failure, using INTOSC1 as the reference clock
source. This circuit only detects complete loss of OSCCLK and doesn’t do any detection of frequency drift
on the OSCCLK.
This circuit monitors the OSCLK (primary clock) using the 10 MHz clock provided by the INTOSC1
(secondary clock) as a backup clock. This circuit functions as below:
1. The primary clock (OSCCLK) clock keeps ticking a 7-bit counter (named as MCDPCNT). This counter
is asynchronously reset with XRS.
2. The secondary clock (INTOSC1) clock keeps ticking a 13-bit counter (named as MCDSCNT). This
counter is asynchronously reset with XRS.
3. Each time MCDPCNT overflows, the MCDSCNT counter is reset. Thus, if OSCCLK is present or not
slower than INTOSC1 by a factor of 64, MCDSCNT will never overflow.
4. If OSCCLK stops for some reason, or is slower than INTOSC1 by at least a factor of 64, the
MCDSCNT will overflow and a missing clock condition will be detected on OSCCLK.
5. The above check is continuously active, unless the MCD is disabled using MCDCR register (by making
the MCLKOFF bit 1)
6. If the circuit ever detects a missing OSCCLK, the following occurs:
• The MCDSTS flag is set
• The MCDSCNT counter is frozen to prevent further missing clock detection
• The CLOCKFAIL signal goes high, which generates TRIP events to PWM modules and fires NMIs
to CPU1.NMIWD.
• PLL is forcefully bypassed and OSCCLK is switched to INTOSC1 (after the PLLSYSCLK divider).
PLLMULT is zeroed out automatically in this case.
• While the MCDSTS bit is set, the OSCCLKSRCSEL bits have no effect and OSCCLK is forcefully
connected to INTOSC1.
• PLLRAWCLK going to the system is switched to INTOSC1 automatically
7. If the MCLKCLR bit is written (this is a W=1 bit), MCDSTS bit will be cleared and OSCCLK source will
be decided by the OSCCLKSRCSEL bits. Writing to MCLKCLR will also clear the MCDPCNT and
MCDSCNT counters to allow the circuit re-evaluate missing clock detection. If user wants to lock the
PLL after missing clock detection, he needs to first switch the clock source to INTOSC1 (using
OSCCLKSRCSEL register), do a MCLKCLR and re-lock the PLL.
8. The MCD is enabled at power up. There is no support for missing clock detection if INTOSC2 is failed
from the device power-up.
Figure 3-3 shows the missing clock logic functional flow.
102
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Safety Features
www.ti.com
Figure 3-3. Missing Clock Detection Logic
Secondary Clock
INTOSC1
Primary Clock
INTOSC2
CLOCKFAIL
Missing
Clock
Detect
(MCD)
Logic
OSCCLK
Source
Select
Ckt
INTOSC1
Low
Power
Mode
Ckt
OSCCLK
X1/X2
CLKSRCCTL1.OSCCLRSRCSEL
SYSPLL
PLLRAWCLK
PLL Locking
Control
Ckt
Registers
Switch
Ckt
Mux
(glitchfree)
/1,
/2,
/4
..
/124
/126
PLLSYSCLK
Clock Dividers
SYSPLLCTL1/2/3,
SYSPLLMULT,
SYSPLLSTS
Clock Sources
3.6.3 PLLSLIP Detection
The PLL SLIP detection on this device can detect if the PLL reference clock goes too high or too slow
while PLL is locked. An interrupt to both the CPUs is triggered as shown in the ePIE table in Section 3.4.
Apart from the interrupt to both the CPUs, the PLLSTS.SLIP bit is set for user software to check the error.
The SLIP detection is available on both SYSPLL and AUXPLL.
3.6.4 CPU1 Vector Address Validity Check
The ePIE vector table is duplicated into two parts:
• Main ePIE Vector Table mapped from 0xD00 to 0xEFF in the C28x memory space
• Redundant ePIE Vector Table mapped from 0x1000D00 to 0x1000EFF in the C28x memory space
Following is the behavior of accesses to the ePIE memories:
• Data Writes to Main Vector Table: Writes to both memories
• Data Writes to Redundant Vector Table: Writes only to the Redundant Vector Table
• Vector Fetch: Data from both the vector tables are compared
• Data Read: Can read the Main and Redundant vector table separately
On every vector fetch from the ePIE, a hardware comparison (no cycle penalty is incurred to do the
comparison) of both the vector table outputs is performed and if there is a mismatch between the two
vector table outputs, the following occurs:
1. If the PIEVERRADDR register (default value 0x3F FFFF) is not initialized, the default error handler at
address 0x3FFFBE gets executed.
But, when the PIEVERRADDR register is initialized to the address of the user-defined routine, the
user-defined routine is executed instead of the default error handler.
2. Hardware also generates EPWM Trip signals which will trip the PWM outputs using TRIPIN15.
3. If there is no mismatch, the correct vector is jammed onto the C28 program control.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
103
Safety Features
www.ti.com
3.6.5 NMIWDs
CPU1 has a user-programmable NMIWD period register in which users can set a limit on how much time
they want to allocate for the device to acknowledge the NMI. If the NMI is not acknowledged, it will cause
a device reset.
3.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection
The CPU subsystem has different RAM blocks. Few RAM blocks are ECC-enabled and others are parityenabled. All single-bit errors in ECC RAM are auto-corrected and an error counter is incremented every
time a single bit error is detected. If the error counter reaches a predefined user configured limit, an
interrupt is generated to the corresponding CPU. A typical threshold setting to avoid triggering on transient
errors which are corrected, but identify persistent faults is 10. Refer to Section 3.11 for more details on
RAM errors.
All uncorrectable double-bit errors end up triggering an NMI to corresponding CPUs.
3.6.7 ECC Enabled Flash Memory
When ECC is programmed and enabled, flash single-bit errors are corrected automatically by ECC logic
before giving data to CPU1, but they are not corrected in flash memory. Flash memory will still contain
wrong data until another erase/program operation happens to correct the flash contents. Irrespective of
whether the error interrupt is enabled or disabled, single-bit errors are always corrected before giving data
to CPU1 . When the interrupt is disabled, users can check the single-bit error counter register for any
single-bit error occurrences. The error counter stops incrementing once its value is equal to the
threshold+1. It is always suggested to set the threshold register to a non-zero value so that the error
counter can increment. It is up to the user to decide the threshold value at which they have to reprogram
the flash with the correct data. A typical threshold setting to avoid triggering on transient errors which are
corrected, but identify persistent faults is 10. When ECC is programmed and enabled, flash uncorrectable
errors end up triggering an NMI to CPU1. Please refer to Section 3.11 for more details on flash error
correction and error catching mechanisms.
3.6.8 ERRORSTS Pin
The ERRORSTS pin is an ‘always output’ pin and remains low until an error is detected inside the chip.
On an error, the ERRORSTS pin goes high until the corresponding internal error status flag for that error
source is cleared. Figure 3-4 shows the functionality of the ERRORSTS pin.
The ERRORSTS pin will be tri-stated until the chip power rails ramp up to the lower operational limit. As
the ERRORSTS pin is an active-high pin, users who care about the state of this pin during power-up
should connect an external pull-down on this pin.
Figure 3-4. ERRORSTS Pin Diagram
CPU1's NMIWD Shadow flags
CPU1.NMIWD.NMISHDFLG.Bit-0
CPU1.NMIWD.NMISHDFLG.Bit-1
ERROR
CPU1.NMIWD.NMISHDFLG.Bit-15
104
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Clocking
www.ti.com
3.7
Clocking
This section explains the clock sources and clock domains on this device, and how to configure them for
application use. Figure 3-5 provides an overview of the device's clocking system.
Figure 3-5. Clocking System
INTOSC1
INTOSC2
To watchdog timer
WDCLK
CLKSRCCTL1
SYSPLLCTL1
SYSCLKDIVSEL
SYSCLK
Divider
OSCCLK
X1(XTAL)
System PLL
PLLRAWCLK
SYSCLK
CPU
PLLSYSCLK
To GS RAMs, GPIOs,
and NMIWDs
CPU1.CPUCLK
To local memories
CPU1.SYSCLK
To ePIEs, LS RAMs,
CLA message RAMs,
and DCSMs
One per SYSCLK peripheral
PCLKCRx
PERx.SYSCLK
To peripherals
PERx.LSPCLK
To SCIs, SPIs, and
McBSPs
EPWMCLK
To ePWMs
One per LSPCLK peripheral
LOSPCP
PCLKCRx
LSP
Divider
LSPCLK
One per ePWM
EPWMCLKDIV
PLLSYSCLK
PCLKCRx
/1
/2
HRPWM
PCLKCRx
HRPWMCLK
To HRPWMs
CAN Bit Clock
To CANs
AUXPLLCLK
To USB bit clock
One per CAN module
CLKSRCCTL2
AUXCLKIN
CLKSRCCTL2
AUXPLLCTL1
AUXCLKDIVSEL
AUXOSCCLK
Auxiliary PLL
AUXPLLRAWCLK
AUXCLK
Divider
Note that the default/2 divider for ePWMs and EMIFs is not shown.
3.7.1 Clock Sources
All of the clocks in the device are derived from one of four clock sources.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
105
Clocking
3.7.1.1
www.ti.com
Primary Internal Oscillator (INTOSC2)
At power-up, the device is clocked from an on-chip 10 MHz oscillator (INTOSC2). INTOSC2 is the primary
internal clock source, and is the default system clock at reset. It is used to run the boot ROM and can be
used as the system clock source for the application. Note that INTOSC2's frequency tolerance is too loose
to meet the timing requirements for CAN and USB, so an external clock must be used to support those
features.
3.7.1.2
Backup Internal Oscillator (INTOSC1)
The device also includes a redundant on-chip 10 MHz oscillator (INTOSC1). INTOSC1 is a backup clock
source that normally only clocks the watchdog timers and missing clock detection circuit (MCD). If MCD is
enabled and a missing system clock is detected, the system PLL is bypassed and all system clocks are
connected to INTOSC1 automatically. INTOSC1 may also be manually selected as the system and
auxiliary clock source for debug purposes.
3.7.1.3
External Oscillator (XTAL)
The dedicated X1 and X2 pins support an external clock source (XTAL), which can be used as the main
system and auxiliary clock source. Frequency limits and timing requirements can be found in the device
datasheet. Three types of external clock sources are supported:
• A single-ended 3.3V external clock. The clock signal should be connected to X1 while X2 is left
unconnected, as shown in Figure 3-6.
Figure 3-6. Single-ended 3.3V External Clock
VDDOSC
X1
VSSOSC
NC
3.3V
3.3V
X2
Clk
VDD
OUT
GND
3.3V Oscillator
•
An external crystal. The crystal should be connected across X1 and X2 with its load capacitors
connected to VSSOSC as shown in Figure 3-7.
Figure 3-7. External Crystal
VDDOSC X1
VSSOSC
X2
3.3V
Crystal
RD
•
106
CL2
CL1
An external resonator. The resonator should be connected across X1 and X2 with its ground
connected to VSSOSC as shown in Figure 3-8.
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Clocking
www.ti.com
Figure 3-8. External Resonator
VDDOSC X1
VSSOSC
X2
3.3V
Resonator
3.7.1.4
Auxiliary Clock Input (AUXCLKIN)
An additional external clock source is supported on GPIO133 (AUXCLKIN). This must be a single-ended
3.3V external clock. It can be used as the source for the USB and CAN bit clocks. Frequency limits and
timing requirements can be found in the device datasheet. The external clock should be connected directly
to the GPIO133 pin, as shown in Figure 3-9.
Figure 3-9. AUXCLKIN
3.7.2 Derived Clocks
The clock sources discussed in the previous section can be multiplied (via PLL) and divided down to
produce the desired clock frequencies for the application. This process produces a set of derived clocks,
which are described in this section.
3.7.2.1
Oscillator Clock (OSCCLK)
One of INTOSC2, XTAL, or INTOSC1 must be chosen to be the master reference clock (OSCCLK) for the
CPU and most of the peripherals. OSCCLK may be used directly or fed through the system PLL to reach
a higher frequency. At reset, OSCCLK is the default system clock, and is connected to INTOSC2.
3.7.2.2
System PLL Output Clock (PLLRAWCLK)
The system PLL allows the device to run at its maximum rated operating frequency, and in most
applications will generate the main system clock. This PLL uses OSCCLK as a reference, and features a
fractional multiplier and slip detection. For configuration instructions, see Section 3.7.6.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
107
Clocking
3.7.2.3
www.ti.com
Auxiliary Oscillator Clock (AUXOSCCLK)
One of INTOSC2, XTAL, or AUXCLKIN may be chosen to be the auxiliary reference clock (AUXOSCCLK)
for the USB module. (This selection does not affect the CAN bit clock, which uses AUXCLKIN directly).
AUXOSCCLK may be used directly or fed through the auxiliary PLL to reach a higher frequency. At reset,
AUXOSCCLK is connected to INTOSC2, but only an external oscillator can meet the USB timing
requirements.
3.7.2.4
Auxiliary PLL Output Clock (AUXPLLRAWCLK)
The auxiliary PLL is used to generate a 60 MHz clock for the USB module. This PLL uses AUXOSCCLK
as a reference, and features a fractional multiplier and slip detection. For configuration instructions, see
Section 3.7.6.
3.7.3 Device Clock Domains
The device clock domains feed the clock inputs of the various modules in the device. They are connected
to the derived clocks, either directly or through an additional divider.
3.7.3.1
System Clock (PLLSYSCLK)
The system control registers, GS RAMs, GPIO qualification, and NMI watchdog timer have their own clock
domain (PLLSYSCLK). Despite the name, PLLSYSCLK may be connected to the system PLL
(PLLRAWCLK) or to OSCCLK. The chosen clock source is run through a frequency divider, which is
configured via the SYSCLKDIVSEL register. PLLSYSCLK is gated in HALT mode.
3.7.3.2
CPU Clock (CPUCLK)
The CPU has its own clock (CPUCLK) which is used to clock the CPU, its coprocessors, its private RAMs
(M0, M1, D0, and D1), and its boot ROM and flash wrapper. This clock is identical to PLLSYSCLK, but is
gated when the CPU enters IDLE, STANDBY, or HALT mode.
3.7.3.3
CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
The CPU provides a clock (SYSCLK) to the CLA, DMA, and most peripherals. This clock is identical to
PLLSYSCLK, but is gated when the CPU enters STANDBY or HALT mode.
Each peripheral clock has its own independent clock gating which is controlled by the PCLKCRx registers.
By default, the ePWM, EMIF1, and EMIF2 clocks each have an additional /2 divider, which is required to
support CPU frequencies over 100 MHz. At slower CPU frequencies, these dividers can be disabled via
the PERCLKDIVSEL register.
3.7.3.4
Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
The SCI, SPI, and McBSP modules can communicate at bit rates that are much slower than the CPU
frequency. These modules are connected to a shared clock divider, which generates a low-speed
peripheral clock (LSPCLK) derived from SYSCLK. LSPCLK uses a /4 divider by default, but the ratio can
be changed via the LOSPCP register. Each SCI, SPI, and McBSP module's clock (PERx.LSPCLK) can be
gated independently via the PCLKCRx registers.
3.7.3.5
USB Auxiliary Clock (AUXPLLCLK)
The USB module requires a fixed 60 MHz clock for bit sampling. Since the main system clock is usually
not a multiple of 60 MHz, the correct frequency cannot be achieved with a simple divider. Instead, the
USB clock is provided through an auxiliary clock path (AUXPLLCLK), which can use an independent clock
source and PLL to generate the correct frequency.
USB clock tolerances are very tight. As stated in section 7.1.11 of the USB 2.0 specification, low-speed
devices (1.50 Mb/s) have a tolerance of +/- 1.5% , while high-speed devices (12.000 Mb/s) have a
tolerance of +/- 0.25%. Typically these tolerances are achieved by using an external crystal or resonator
as the source for AUXOSCCLK.
108
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Clocking
www.ti.com
3.7.3.6
CAN Bit Clock
The required frequency tolerance for the CAN bit clock depends on the bit timing setup and network
configuration, and can be as tight as 0.1%. Since the main system clock (in the form of PERx.SYSCLK)
may not be precise enough, the bit clock can also be connected to XTAL or AUXCLKIN via the
CLKSRCCTL2 register. There is an independent selection for each CAN module.
3.7.3.7
CPU Timer2 Clock (TIMER2CLK)
CPU timers 0 and 1 are connected to PERx.SYSCLK. Timer 2 is connected to PERx.SYSCLK by default,
but may also be connected to INTOSC1, INTOSC2, XTAL, or AUXPLLCLK via the TMR2CLKCTL register.
This register also provides a separate prescale divider for timer 2. If a source other than SYSCLK is used,
the SYSCLK frequency must be at least twice the source frequency to ensure correct sampling.
The main reason to use a non-SYSCLK source would be for internal frequency measurement. In most
applications, timer 2 will run off of the SYSCLK.
3.7.4 XCLKOUT
It is sometimes necessary to observe a clock directly for debug and testing purposes. The external clock
output (XCLKOUT) feature supports this by connecting a clock to an external pin, GPIO73. The available
clock sources are PLLSYSCLK, PLLRAWCLK, SYSCLK, AUXPLLRAWCLK, INTOSC1, and INTOSC2.
To use XCLKOUT, first select the clock source via the CLKSRCCTL3 register. Next, select the desired
output divider via the XCLKOUTDIVSEL register. Finally, connect GPIO73 to mux channel 3 using the
GPIO configuration registers.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
109
Clocking
www.ti.com
3.7.5 Clock Connectivity
The tables below provide details on the clock connections of every module present in the device.
Table 3-6. Clock Connections Sorted by Clock Domain
Clock Domain
Module Name
CPUCLK
CPU
FPU
TMU
Flash
M0 - M1 RAMs
D0 - D1 RAMs
BootROM
SYSCLK
ePIE
LS0 - LS5 RAMs
CLA1 Message RAMs
DCSM
PLLSYSCLK
NMIWD
GS0 - GS15 RAMs
GPIO Input Sync and Qual
EMIF1
PERx.SYSCLK
CLA1
DMA
Timer0 - 2
EMIF2
ADCA - D
CMPSS1 - 8
DACA - C
ePWM1 - 12
eCAP1 - 6
eQEP1 - 3
I2CA - B
McBSPA - B
SDFM1 - 8
uPP A
PERx.LSPCLK
McBSPA - B
SCIA - D
SPIA - C
CAN Bit Clock
CANA - B
AUXPLLCLK
USB
WDCLK (INTOSC1)
Watchdog Timer
110 System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Clocking
www.ti.com
Table 3-7. Clock Connections Sorted by Module Name
Module Name
Clock Domain
ADCA - D
PERx.SYSCLK
Boot ROM
CPUCLK
CANA - B
CAN Bit Clock
CLA
PERx.SYSCLK
CLA Message RAMs
SYSCLK
CMPSS1 - 8
PERx.SYSCLK
CPU
CPUCLK
CPU Timers
PERx.SYSCLK
D0 - D1 RAMs
CPUCLK
DACA - C
PERx.SYSCLK
DCSM
SYSCLK
DMA
PERx.SYSCLK
eCAP1 - 6
PERx.SYSCLK
EMIF1
PLLSYSCLK
EMIF2
PERx.SYSCLK
ePIE
SYSCLK
ePWM
PERx.SYSCLK
eQEP1 - 3
PERx.SYSCLK
Flash
CPUCLK
FPU
CPUCLK
GS0 - GS15 RAMs
PLLSYSCLK
I2CA - B
PERx.SYSCLK
LS0 - LS5 RAMs
SYSCLK
M0 - M1 RAMs
CPUCLK
McBSPA - B
PERx.LSPCLK
NMIWD
PLLSYSCLK
SCIA - D
PERx.LSPCLK
SDFM1 - 8
PERx.SYSCLK
SPIA - C
PERx.LSPCLK
TMU
CPUCLK
uPP
PERx.SYSCLK
USB
AUXPLLCLK
Watchdog Timer
WDCLK (INTOSC1)
3.7.6 Clock Source and PLL Setup
The needs of the application are what ultimately determine the clock configuration. Specific concerns such
as application performance, power consumption, total system cost, and EMC are beyond the scope of this
document, but they should provide answers to the following questions:
1. What is the desired CPU frequency?
2. Is CAN required?
3. Is USB required?
4. What types of external oscillators or clock sources are available?
If CAN or USB is required, an external clock source with a precise frequency must be used as a reference
clock. Otherwise, it may be possible to use only INTOSC2 and avoid the need for more external
components.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
111
Clocking
3.7.6.1
www.ti.com
Choosing PLL Settings
There are two settings to configure for each PLL – a multiplier and a divider. They obey the formulas:
fPLLSYSCLK = fOSCCLK * (SYSPLLMULT.IMULT + SYSPLLMULT.FMULT) / SYSCLKDIVSEL.PLLSYSCLKDIV
fAUXPLLCLK = fAUXOSCCLK * (AUXPLLMULT.IMULT + AUXPLLMULT.FMULT) / AUXCLKDIVSEL.AUXPLLDIV
where fOSCCLK is the system oscillator clock frequency, fAUXOSCCLK is the auxiliary oscillator clock frequency,
IMULT and FMULT are the integral and fractional parts of the multipliers, PLLSYSCLKDIV is the system
clock divider, and AUXPLLDIV is the auxiliary clock divider. For the permissible values of the multipliers
and dividers, see the documentation for their respective registers.
Many combinations of multiplier and divider can produce the same output frequency. However, the
product of the reference clock frequency and the multiplier (known as the VCO frequency) must be in the
range specified in the data manual.
NOTE: The system clock frequency (PLLSYSCLK) may not exceed the limit specified in the
datasheet. This limit does not allow for oscillator tolerance.
3.7.6.2
System Clock Setup
Once the application requirements are understood, a specific clock configuration can be determined. The
default configuration is for INTOSC2 to be used as the system clock (PLLSYSCLK) with a divider of 1.
The following procedure should be used to set up the desired application configuration:
1. Select the reference clock source (OSCCLK) by writing to CLKSRCCTL1.OSCCLKSRCSEL.
2. Set up the system PLL: (see the InitSysPll() function in your devices controlSUITE installation for an
example):
a. Bypass the PLL by clearing SYSPLLCTL1[PLLCLKEN].
b. Set the system clock divider to /1 to ensure the fastest PLL configuration by clearing
SYSCLKDIVSEL[ PLLSYSCLKDIV].
c. Set the integral and fractional multipliers by simultaneously writing them both to SYSPLLMULT.
This will automatically enable the PLL. Be sure that the product of OSCCLK and the multiplier is in
the range specified in the data manual.
d. Lock the PLL five times (see your device errata for details). This number can be increased
depending on application requirements. A higher number of lock attempts helps to ensure a
successful PLL start
e. Set the system clock divider one setting higher than the final desired value. For example
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1. This limits the current increase
when switching to the PLL.
f. Set up the watchdog to reset the device. Note that the SCRS[WDOVERRIDE] bit should not be
cleared prior to locking the PLL.
g. Set the SYSDBGCTL[BIT_0] bit. This bit is only reset by a POR reset. If the watchdog has to reset
the device due to an issue with switching to the PLL, this bit can be checked in the reset handler to
determine the reset was caused by a PLL error.
h. Switch to the PLL as the system clock by setting SYSPLLCTL1[PLLCLKEN].
i. Clear the SYSDBGCTL[BIT_0] bit.
j. Change the divider to the appropriate value.
k. Reconfigure the watchdog as needed for the application.
3.7.6.3
USB Auxiliary Clock Setup
See the InitAuxPll() function in your device’s controlSUITE installation for an example.
If USB functionality is needed, the auxiliary clock (AUXPLLCLK) must be configured to produce 60 MHz.
The procedure is similar to the system clock setup:
1. Select the reference clock source (AUXOSCCLK) by writing to CLKSRCCTL2.AUXOSCCLKSRCSEL.
112
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Clocking
www.ti.com
2. Wait two AUXOSCCLK cycles.
3. Set up the auxiliary PLL. If the PLL is not needed, bypass it and power it down by writing a 0 to
AUXPLLCTL1.PLLEN. To use the PLL:
a. Set the desired auxiliary clock divider by writing to AUXCLKDIVSEL.AUXPLLDIV.
b. ) Configure CPU Timer 2 to be clocked from AUXPLL. Keep the counter frozen.
c. ) Power down the AUXPLL by clearing AUXPLLCTL1[PLLEN].
d. Set the integral and fractional multipliers simultaneously. This will automatically enable the PLL. Be
sure that the product of AUXOSCCLK and the multiplier is in the range specified in the data
manual..
e. Wait for the PLL to lock by polling the AUXPLLSTS.LOCKS bit. This will take 16 µs plus 1024
AUXOSCCLK cycles.
f. Connect the auxiliary PLL output clock (AUXPLLRAWCLK) to AUXPLLCLK by writing a 1 to
AUXPLLCTL1.PLLCLKEN.
g. Start CPU Timer 2. In a large for() loop, continue polling the TCR[TIF] overflow flag. If it sets, the
AUXPLL started correctly. If not, repeat steps (c) through (g). The auxiliary clock configuration can
be changed at run time. Changing the AUXOSCCLK source will automatically bypass the PLL and
set the multiplier to zero. Changing the multiplier from one non-zero value to another will
temporarily bypass the PLL until it re-locks.
The auxiliary clock configuration can be changed at run time. Changing the AUXOSCCLK source will
automatically bypass the PLL and set the multiplier to zero. Changing the multiplier from one non-zero
value to another will temporarily bypass the PLL until it re-locks.
NOTE: If the AUXOSCCLK source is changed on the same AUXOSCCLK cycle as the multiplier, the
PLL will be disabled but the AUXPLLMULT register will show the written value. This can
happen when the system PLL is enabled before configuring the auxiliary PLL (CPUCLK >>
AUXOSCCLK). To avoid this issue, wait two AUXOSCCLK cycles between changing the
clock source and writing to AUXPLLMULT.
3.7.6.4
Clock Configuration Examples
Example 1: Using a crystal (15 MHz) as a reference, generate a CPU frequency of 100 MHz and a USB
clock of 60 MHz:
CLKSRCCTL1.OSCCLKSRCSEL = 0x1
SYSPLLMULT.IMULT = 26 (0x1A)
SYSPLLMULT.FMULT = .50 (0x2)
SYSCLKDIVSEL.PLLSYSCLKDIV = 4 (0x2)
SYSPLLCTL1.PLLCLKEN = 1
PERCLKDIVSEL.EPWMCLKDIV = 1 (0x0)
PERCLKDIVSEL.EMIF1CLKDIV = 1 (0x0)
PERCLKDIVSEL.EMIF2CLKDIV = 1 (0x0)
CLKSRCCTL2.AUXOSCCLKSRCSEL = 0x1
AUXPLLMULT.IMULT = 8 (0x08)
AUXPLLMULT.FMULT = .00 (0x0)
AUXCLKDIVSEL.AUXPLLDIV = 2 (0x1)
AUXPLLCTL1.PLLCLKEN = 1
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
113
32-Bit CPU Timers 0/1/2
www.ti.com
This gives a PLLRAWCLK of 397.5 MHz and an AUXPLLRAWCLK of 120 MHz, both of which are in the
acceptable range. The CPU frequency is 99.375 MHz. Crystals have tight frequency tolerances, which
should keep the system clock from exceeding 100 MHz. The USB frequency is exactly 60 MHz. Since the
CPU frequency is less than 100 MHz, the ePWM and EMIF clock dividers can be set to /1.
3.8
32-Bit CPU Timers 0/1/2
This section describes the three 32-bit CPU-Timers (TIMER0/1/2) shown in Figure 3-10.
CPU-Timer0 and CPU-Timer1 can be used in user applications. CPU-Timer2 is reserved for real-time
operating system uses (for example, TI-RTOS). If the application is not using an operating system that
utilizes this timer, then CPU-Timer2 can be used in the application. CPU-Timer0 and CPU-Timer1 run off
of SYSCLK. CPU-Timer2 normally runs off of SYSCLK, but can also use INTOSC1, INTOSC2, XTAL, and
AUXPLLCLK. The CPU-Timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in
Figure 3-11.
Figure 3-10. CPU-Timers
Reset
Timer reload
16-bit timer divide-down
TDDRH:TDDR
32-bit timer period
PRDH:PRD
16-bit prescale counter
PSCH:PSC
SYSCLKOUT
TCR.4
(Timer start status)
32-bit counter
TIMH:TIM
Borrow
Borrow
TINT
Figure 3-11. CPU-Timer Interrupts Signals and Output Signal
INT1
to
INT12
PIE
TINT0
TIMER0
28x
CPU
TINT1
TIMER1
INT13
TINT2
INT14
TIMER2
A
The timer registers are connected to the memory bus of the C28x processor.
B
The CPU Timers are synchronized to SYSCLKOUT.
The general operation of the CPU-Timer is as follows:
• The 32-bit counter register, TIMH:TIM, is loaded with the value in the period register PRDH:PRD
• The counter decrements once every (TPR[TDDRH:TDDR]+1) SYSCLKOUT cycles, where
TDDRH:TDDR is the timer divider.
114
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
32-Bit CPU Timers 0/1/2
www.ti.com
•
When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse.
The registers listed in Section 3.15 are used to configure the timers.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
115
Watchdog Timers
3.9
www.ti.com
Watchdog Timers
The watchdog module generates an output pulse 512 watchdog clocks (WDCLKs) wide whenever the 8bit watchdog up counter has reached its maximum value. The watchdog clock source is INTOSC1.
Software must periodically write a 0x55 + 0xAA sequence into the watchdog key register to reset the
watchdog counter. The counter can also be disabled. Figure 3-12 shows the various functional blocks
within the watchdog module.
Figure 3-12. CPU Watchdog Timer Module
WDCR(WDPS(2:0))
WDCR(WDDIS)
WDCNTR(7:0)
WDCLK
(INTOSC1)
Watchdog
Prescaler
/512
SYSRSn
8-bit
Watchdog
Counter
Overflow
1-count
delay
Clear
Count
WDWCR(MIN(7:0))
WDKEY(7:0)
Watchdog
Key Detector
55 + AA
WDRSTn
WDINTn
In Window
Good Key
Out of Window
Watchdog
Window
Detector
Bad Key
Generate
512-WDCLK
Output Pulse
Watchdog Timeout
SCSR(WDENINT)
3.9.1 Servicing the Watchdog Timer
The watchdog counter (WDCNTR) is reset when the proper sequence is written to the WDKEY register
before the 8-bit watchdog counter overflows. The WDCNTR is reset-enabled when a value of 0x55 is
written to the WDKEY. When the next value written to the WDKEY register is 0xAA, then the WDCNTR is
reset. Any value written to the WDKEY other than 0x55 or 0xAA causes no action. Any sequence of 0x55
and 0xAA values can be written to the WDKEY without causing a system reset; only a write of 0x55
followed by a write of 0xAA to the WDKEY resets the WDCNTR.
Table 3-8. Example Watchdog Key Sequences
Step
Value Written to WDKEY
1
0xAA
No action
2
0xAA
No action
3
0x55
WDCNTR is enabled to be reset if next value is 0xAA.
4
0x55
WDCNTR is enabled to be reset if next value is 0xAA.
5
0x55
WDCNTR is enabled to be reset if next value is 0xAA.
6
0xAA
WDCNTR is reset.
7
0xAA
No action
8
0x55
WDCNTR is enabled to be reset if next value is 0xAA.
116 System Control
Result
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Watchdog Timers
www.ti.com
Table 3-8. Example Watchdog Key Sequences (continued)
Step
Value Written to WDKEY
9
0xAA
WDCNTR is reset.
Result
10
0x55
WDCNTR is enabled to be reset if next value is 0xAA.
11
0x32
Improper value written to WDKEY.
No action, WDCNTR no longer enabled to be reset by next 0xAA.
12
0xAA
No action due to previous invalid value.
13
0x55
WDCNTR is enabled to be reset if next value is 0xAA.
14
0xAA
WDCNTR is reset.
Step 3 in Table 3-8 is the first action that enables the WDCNTR to be reset. The WDCNTR is not actually
reset until step 6. Step 8 again re-enables the WDCNTR to be reset and step 9 resets the WDCNTR. Step
10 again re-enables the WDCNTR to be reset. Writing the wrong key value to the WDKEY in step 11
causes no action, however the WDCNTR is no longer enabled to be reset and the 0xAA in step 12 now
has no effect.
If the watchdog is configured to reset the device, then a WDCR overflow or writing the incorrect value to
the WDCR[WDCHK] bits will reset the device and set the watchdog flag (WDRSn) in the reset cause
register (RESC). After a reset, the program can read the state of this flag to determine whether the reset
was caused by the watchdog. After doing this, the program should clear WDRSn to allow subsequent
watchdog resets to be detected. Watchdog resets are not prevented when the flag is set.
3.9.2 Minimum Window Check
To complement the timeout mechanism, the watchdog also contains an optional "windowing" feature that
requires a minimum delay between counter resets. This can help protect against error conditions that
bypass large parts of the normal program flow but still include watchdog handling.
To set the window minimum, write the desired minimum watchdog count to the WDWCR register. This
value will take effect after the next WDKEY sequence. From then on, any attempt to service the watchdog
when WDCNTR is less than WDWCR will trigger a watchdog interrupt or reset. When WDCNTR is greater
than or equal to WDWCR, the watchdog can be serviced normally.
At reset, the window minimum is zero, which disables the windowing feature.
3.9.3 Watchdog Reset or Watchdog Interrupt Mode
The watchdog can be configured in the SCSR register to either reset the device (WDRST) or assert an
interrupt (WDINT) if the watchdog counter reaches its maximum value. The behavior of each condition is
described below:
• Reset mode:
If the watchdog is configured to reset the device, then the WDRST signal will pull the device reset
(XRS) pin low for 512 OSCCLK cycles when the watchdog counter reaches its maximum value.
Note: After a watchdog reset, the boot ROM will clear all of the system and message RAMs.
• Interrupt mode:
When the watchdog counter expires, it will assert an interrupt by driving the WDINT signal low for 512
OSCCLK cycles. The falling edge of WDINT triggers a WAKEINT interrupt in the PIE if it is enabled.
Because the PIE is edge-triggered, re-enabling the WAKEINT while WDINT is active will not produce a
duplicate interrupt.
To avoid unexpected behavior, software should not change the configuration of the watchdog while
WDINT is active. For example, changing from interrupt mode to reset mode while WDINT is active will
immediately reset the device. Disabling the watchdog while WDINT is active will cause a duplicate
interrupt if the watchdog is later re-enabled. If a debug reset is issued while WDINT is active, the reset
cause register (RESC) will show a watchdog reset. The WDINTS bit in the SCSR register can be read
to determine the current state of WDINT.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
117
Watchdog Timers
www.ti.com
3.9.4 Watchdog Operation in Low Power Modes
In IDLE mode, the watchdog interrupt (WDINT) signal can generate an interrupt to the CPU to take the
CPU out of IDLE mode. As with any other peripheral, the watchdog interrupt will trigger a WAKEINT
interrupt in the PIE during IDLE mode. User software must determine which peripheral caused the
interrupt.
In STANDBY mode, all of the clocks to the peripherals are turned off within the CPU subsystem. The only
peripheral that remains functional is the watchdog since the watchdog module runs off the oscillator clock
(OSCCLK). The WDINT signal is fed to the Low Power Modes (LPM) block so that it can be used to wake
the CPU from STANDBY low power mode. This feature is enabled by setting LPMCR.WDINTE = 1. See
Section 3.10 for details.
Note: If the watchdog interrupt is used to wake-up from an IDLE or STANDBY low power mode condition,
software must make sure that the WDINT signal goes back high before attempting to reenter the IDLE or
STANDBY mode. The WDINT signal will be held low for 512 OSCCLK cycles when the watchdog interrupt
is generated. The current state of WDINT can be determined by reading the watchdog interrupt status bit
(WDINTS) bit in the SCSR register. WDINTS follows the state of WDINT by two SYSCLKOUT cycles.
In HALT mode, the internal oscillators and CPU1 watchdog are kept active if the user sets
CLKSRCCTL1.WDHALTI = 1. A watchdog reset can wake the system from HALT mode, but a watchdog
interrupt cannot.
3.9.5 Emulation Considerations
The watchdog module behaves as follows under various debug conditions:
CPU Suspended:
Run-Free Mode:
Real-Time Single-Step
Mode:
Real-Time Run-Free
Mode:
118
System Control
When the CPU is suspended, the watchdog clock (WDCLK) is suspended
When the CPU is placed in run-free mode, then the watchdog module
resumes operation as normal.
When the CPU is in real-time single-step mode, the watchdog clock
(WDCLK) is suspended. The watchdog remains suspended even within realtime interrupts.
When the CPU is in real-time run-free mode, the watchdog operates as
normal.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Low Power Modes
www.ti.com
3.10 Low Power Modes
This device has three clock-gating, low-power modes and a special power-gating mode. All low-power
modes are entered by setting the LPMCR register and executing the IDLE instruction. More information
about this instruction can be found in the TMS320C28x CPU and Instruction Set Reference Guide
(SPRU430).
Low-power modes should not be entered into while a flash program or erase is ongoing.
The application should verify the following before entering STANDBY or HALT Mode:
1. Check the value of the GPIODAT register of the pin selected for STANDBY or HALT wake-up
(GPIOLPMSEL0/1) prior to entering the Low-Power mode to ensure that the wake event has not
already been asserted.
2. The LPMCR.QUALSTDBY register should be set to a value greater than the ratio of
INTOSC1/PLLSYSCLK to ensure proper wake up. This is applicable to STANDBY only.
3.10.1 IDLE
IDLE is a standard feature of the C28x CPU. In this mode, the CPU clock is gated while all peripheral
clocks are left running. IDLE can thus be used to conserve power while a CPU is waiting for peripheral
events.
Any enabled interrupt will wake the CPU up from IDLE mode.
To enter IDLE mode, set LPMCR.LPM to 0x0 and execute the IDLE instruction.
3.10.2 STANDBY
STANDBY is a more aggressive low-power mode that gates both the CPU clock and any peripheral clocks
derived from the CPU's SYSCLK. The watchdog however, is left active. STANDBY is best suited for an
application where the wake-up signal will come from an external system rather than a peripheral input.
An NMI (or optionally) a watchdog interrupt or a configured GPIO can wake the CPU from STANDBY
mode. Each GPIO from GPIO0-63 can be configured to wake the CPU when they are driven active low.
Upon wakeup, the CPU receives the WAKEINT interrupt if configured.
To enter STANDBY mode:
1. Set LPMCR.LPM to 0x1.
2. Enable the WAKEINT interrupt in the PIE.
3. For watchdog interrupt wakeup, set LPMCR.WDINTE to 1 and configure the watchdog to generate
interrupts.
4. For GPIO wakeup, set GPIOLPMSEL0 and GPIOLPMSEL1 to connect the chosen GPIOs to the LPM
module, and set LPMCR.QUALSTDBY to select the number of OSCCLK cycles for input qualification.
5. Execute the IDLE instruction to enter STANDBY.
To wake up from Standby mode:
1. Configure the desired GPIO to trigger the wakeup.
2. Drive the selected GPIO signal low; it must remain low for the number of OSCCLK cycles specified in
the QUALSTDBY bits in the LPMCR register. If the signal is sampled high during this period, the count
restarts.
At the end of the qualification period, the PLL enables the CLKIN to the CPU and the WAKEINT interrupt
is latched in the PIE block. The WAKEINT interrupt can also be triggered by a watchdog interrupt.
The CPU is now out of STANDBY mode and can resume normal execution.
3.10.3 HALT
HALT is a global low-power mode that gates almost all system clocks and allows for power-down of
oscillators and analog blocks. HALT can be used for additional power savings over putting the CPU in
STANDBY, although the options for wakeup are more limited.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
119
Low Power Modes
www.ti.com
Similar to STANDBY, any of GPIO0-63 can be configured to wake up the system from HALT. No other
wakeup option is available. However, CPU1's watchdog may still be clocked, and can be configured to
produce a watchdog reset if a timeout mechanism is needed. On wakeup, the CPU receives a WAKEINT
interrupt.
To enter HALT mode:
1. Disable all interrupts with the exception of the WAKEINT interrupt on both CPUs. The other interrupts
can be reenabled after the device is brought out of HALT mode.
2. Set LPMCR.LPM to 0x2. Set GPIOLPMSEL0 and GPIOLPMSEL1 to connect the chosen GPIOs to the
LPM module.
3. Set CLKSRCCTL1.WDHALTI to 1 to keep the CPU1 watchdog active and INTOSC1 and INTOSC2
powered up in HALT.
4. Set CLKSRCCTL1.WDHALTI to 0 to disable the CPU1 watchdog and power down INTOSC1 and
INTOSC2 in HALT.
5. Execute the IDLE instruction on CPU1 to enter HALT.
If an interrupt or NMI is received while the IDLE instruction is in the pipeline, the system will begin
executing the WAKEINT ISR. After HALT wakeup, ISR execution will resume where it left off.
NOTE: Before entering HALT mode, if the system PLL is locked (SYSPLL.LOCKS = 1), it must also be
connected to the system clock (PLLCTL1.PLLCLKEN = 1). Otherwise, the device will never wake up.
To wake up from HALT mode:
1. Drive the selected GPIO low for a minimum 5us. This will activate the CPU1.WAKEINT PIE interrupt.
2. Drive the wake-up GPIO high again to initiate the powering up of the SYSPLL and AUXPLL
3. Wait 16us plus 1024 OSCLK cycles to allow the PLLs to lock and the WAKEINT ISR to be latched.
4. Execute the WAKEINT ISR.
The device is now out of HALT mode and can resume normal execution.
3.10.4 HIB
Hibernate (HIB) is a global low-power mode that gates the supply voltages to most of the system. HIB is
essentially a controlled power-down with remote wakeup capability, and can be used to save power during
long periods of inactivity. Because gating the supply voltage corrupts the state of the logic, a reset is
required to exit HIB. To prevent external systems from being affected by the reset, HIB provides isolation
of the I/O pin states as well as low-power data retention via the M0 and M1 memories.
Unlike the clock-gating modes, HIB does not have a true wakeup. Instead, GPIO41 becomes HIBWAKE,
an asynchronous reset signal. When the boot ROM detects a HIB wakeup, it will avoid clearing M0 and
M1 and call a user-specified I/O restore function. To prevent glitches on internal and external signals, XRS
will also generate a HIBWAKE signal during HIB. The I/O restore function should set up the GPIO control
registers to match their pre-HIB state, then write a 1 to LPMCR.IOISODIS to deactivate I/O isolation. If the
restore function does not disable isolation, the boot ROM will do it.
To enter HIB mode:
1. Save any necessary state to the M0 and M1 memories.
2. Put all I/Os in the desired state for isolation and deactivate any analog modules in use.
3. Write the address of the I/O restore function for the CPU to its IORESTOREADDR register.
4. Bypass the PLL by setting PLLCLKEN to 0.
5. Set CPU1's LPMCR.LPM to 0x3 and execute the IDLE instruction.
Any debugger connection will be lost on HIB entry since the JTAG logic is powered down.
Due to the loss of system state on HIB entry, it is possible for error information to be lost if an NMI is
triggered while the IDLE instruction is in the pipeline. The ERRORSTS pin will be set and remain set until
I/O isolation is disabled, but there will be no way to tell what caused the error.
To wake the device from HIB mode:
1. Assert the dedicated GPIOHIBWAKE pin (GPIO41) low to enable the power-up of the device clock
120
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Low Power Modes
www.ti.com
sources.
2. Assert GPIOHIBWAKE pin high again. This triggers the power-up of the rest of the device.
3. Boot ROM code will execute on HIB wake-up. Boot ROM will read CPU1.RESC.HIBRESTn bit to
determine this is a wakeup from HIB.
4. Boot ROM calls the I/O context restore routine. This I/O restore function should reconfigure the I/O
configuration and do any other necessary application setup.
Since waking up from HIB mode is a type of reset, the device will enter the main function. The device is
now out of HIB mode and can normal execution.
NOTE: The bootROM uses locations 0x02-0x122 on CPU1’s M0 RAM. To prevent losing any data
during HIB wake-up, avoid saving any critical data to these locations.
NOTE:
The application must bypass the PLL before executing the IDLE instruction to enter HIB. If
the PLL is not bypassed when entering HIB, there will be a brief current spike on the Vdd
supply that may cause the device to reset.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
121
Memory Controller Module
www.ti.com
3.11 Memory Controller Module
For these devices, the RAMs have different characteristics. Some are:
• dedicated to the CPU (M0, M1, and Dx RAMs),
• shared between the CPU and CLA (LSx RAM),
• shared between the CPU and DMA (GSx RAM), and
• used to send and receive messages between processors (MSGRAM).
All these RAMs are highly configurable to achieve control for write access and fetch access from different
masters. All dedicated RAMs are enabled with the ECC feature (both data and address) and shared
RAMs, are enabled with the PARITY (both data and address) feature. Some of the dedicated memories
are secure memory as well. Refer to Section 3.13 for more details. Each RAM has its own controller which
takes care of the access protection/security related checks and ECC/Parity features for that RAM.
Figure 3-13 shows the configuration of these RAMs.
Figure 3-13. Memory Architecture
CPU1.LSx RAM
GSx RAM
CPU1 TO
CPU1.CLA1
MSGRAM
CPU1.CLA1
CPU1.CLA1 TO
CPU1 MSGRAM
CPU1.DMA
CPU1
CPU1.M0 RAM
CPU1.M1 RAM
CPU1.Dx RAM
NOTE: All RAMs on these devices are SRAMs.
3.11.1 Functional Description
This section further defines and discusses the dedicated RAMs, shared RAMs, and MSG RAMs on this
device.
3.11.1.1 Dedicated RAM (Dx RAM)
This device has four dedicated RAM blocks: M0, M1, D0, and D1. M0/M1 memories are small blocks of
memory which are tightly coupled with the CPU. Only the CPU has access to these memories. No other
masters (including DMA) have any access to these memories.
All dedicated RAMs have the ECC feature. All dedicated memories (except for M0/M1) are secure
memory and also have the access protection (CPU write protection/CPU fetch protection) feature. Each
type of access protection for each RAM block can be enabled/disabled by configuring the specific bit in the
access protection register (DxACCPROT).
3.11.1.2 Local Shared RAM (LSx RAM)
RAM blocks which are accessible to the CPU and CLA only, are called local shared RAMs (LSx RAMs).
All such memories are secure memory and have the parity feature. By default, these memories are
dedicated to the CPU only, and the user could choose to share these memories with the CLA by
appropriately configuring the MSEL_LSx bit field in the LSxMSEL register. Further, when these memories
are shared between the CPU and CLA, the user could choose to use these memories as CLA program
memory by configuring the CLAPGM_LSx bit field in the LSxCLAPGM registers. CPU access to all
memory blocks, which are programmed as CLA program memory, are blocked.
122
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Memory Controller Module
www.ti.com
All these RAMs have the access protection (CPU write/CPU fetch) feature. Each type of access protection
for each RAM block can be enabled or disabled by configuring the specific bit in the local shared RAM
access protection registers. Table 3-9 shows the LSx RAM features.
Table 3-9. Local Shared RAM
MSEL_LSx
CLAPGM_LSx
CPUx Allowed
Access
CPUx.CLA1 Allowed
Access
Comment
00
X
All
-
LSx memory is configured as CPU
dedicated RAM
01
0
All
Data Read
Data Write
LSx memory is shared between
CPU and CLA1
01
1
Emulation Read
Emulation Write
Fetch Only
LSx memory is CLA1 program
memory
3.11.1.3 Global Shared RAM (GSx RAM)
RAM blocks which are accessible from the CPU and DMA are called global shared RAMs (GSx RAMs)..
shows the features of the GSx RAM.
Table 3-10. Global Shared RAM
CPU1
CPU1
CPU1
CPU1.DMA
CPU1.DMA
Fetch
Read
Write
Read
Write
Yes
Yes
Yes
Yes
Yes
Like other shared RAM, these RAMs also have a different levels of access protection which can be
enabled or disabled by configuring specific bits in the GSxACCPROT registers.
Master select and access protection configuration for each GSx RAM block can be individually locked by
the user to prevent further update to these bit fields. The user can also choose to permanently lock the
configuration to individual bit fields by setting the specific bit fields in the GSxCOMMIT register (refer to
the register description for more details). Once configuration is committed for a particular GSx RAM block,
it can not be changed further until CPU1.SYSRS is issued.
3.11.1.4 Message RAM (CLA MSGRAM)
These RAM blocks are be used to share data between the CPU and CLA. The CLA has read and write
access to the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA
MSGRAM." The CPU and CLA both have read access to both MSGRAMs.
This RAM has parity.
3.11.1.5 Access Arbitration
For a shared RAM, multiple accesses can happen at a given time. The maximum number of accesses to
any shared RAM at any given time depends on the type of shared RAM. On this device, a combination of
a fixed and round robin scheme is followed to arbitrate multiple access at any given time.
The following is the order of fixed priority for CPU accesses:
1. Data Write/Program Write
2. Data Read
3. Program Read/Program Fetch
The following is the order of fixed priority for CLA accesses:
1. Data Write
2. Data Read/Program Fetch
Figure 3-14 represents the arbitration scheme on global shared memories:
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
123
Memory Controller Module
www.ti.com
Figure 3-14. Arbitration Scheme on Global Shared Memories
Round Robin Arbitration
CPU1-DWRITE
CPU1
Fixed
Priority
Arbiter
CPU1-DREAD
CPU1-PREAD/FETCH
Granted CPU1 Access
RR-CPU1
CPU1.DMA READ/WRITE
RR-CPU1.DMA
Figure 3-15 represents the arbitration scheme on local shared memories.
Figure 3-15. Arbitration Scheme on Local Shared Memories
CPU-DWRITE
CPU-DREAD
CPU-PREAD/FETCH
CLA-DWRITE
CLA-DREAD
Round Robin Arbitration
CPU
Fixed
Priority
Arbiter
Granted CPU1 Access
CLA
Fixed
Priority
Arbiter
Granted CLA Access
RR-CPU
RR-CPU.CLA
3.11.1.6 Access Protection
All RAM blocks except for M0/M1 have different levels of protection. This feature allows the user to enable
or disable specific access to individual RAM blocks from individual masters. There is no protection for read
accesses, hence reads are always allowed from all the masters which have access to that RAM block.
The following sections describe the different kinds of protection available for RAM blocks on this device.
Note: For debug accesses, all the protections are disabled.
3.11.1.6.1 CPU Fetch Protection
Fetch accesses from the CPU can be protected by setting the FETCHPROTx bit of the specific register to
‘1.’ If fetch access is done by the CPU to a memory where CPU fetch protection is enabled, a fetch
protection violation occurs.
124
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Memory Controller Module
www.ti.com
If a fetch protection violation occurs, it results in an ITRAP for CPU. A flag gets set into the appropriate
access violation flag register, and the memory address for which the access violation occurred, get
latched into the appropriate CPU fetch access violation address register.
3.11.1.6.2 CPU Write Protection
Write accesses from the CPU can be protected by setting the CPUWRPROTx bit of the specific register to
‘1.’ If write access is done by a CPU to memory where it is protected, a write protection violation occurs.
If a write protection violation occurs, write gets ignored, a flag gets set into the appropriate access
violation flag register, and the memory address for which the access violation occurred, gets latched into
the appropriate CPU write access violation address register. Also, an access violation interrupt is
generated if enabled in the interrupt enable register.
3.11.1.6.3 CPU Read Protection
For local shared RAM, if memory is shared between the CPU and its CLA, the CPU will only have access
if the memory is configured as data RAM for the CLA. If it is programmed as program RAM, all the access
from the CPU, including a read, will be blocked and the violation will be considered as a non-master
access violation.
If a read protection violation occurs, a flag gets set into the appropriate access violation flag register, and
the memory address for which the access violation occurred, gets latched into the appropriate CPU read
access violation address register. Also, an access violation interrupt is generated, if enabled in the
interrupt enable register.
3.11.1.6.4 CLA Fetch Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as data RAM for the
CLA, any fetch access from the CLA to that particular LSx RAM results in a CLA fetch protection violation,
which is a non-master access violation.
If a CLA fetch protection violation occurs, it results in a MSTOP, a flag gets set into the appropriate access
violation flag register, and the memory address for which the access violation occurred, gets latched into
the appropriate CLA fetch access violation address register. Also, an access violation interrupt is
generated to the master CPU if enabled in the interrupt enable register.
3.11.1.6.5 CLA Write Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as program RAM for
the CLA, any data write access from the CLA to that particular LSx RAM results in a CLA write protection
violation, which is a non-master access violation.
If a CLA write protection violation occurs, write gets ignored, a flag gets set into the appropriate access
violation flag register, and the memory address for which the access violation occurred, gets latched into
the appropriate CLA write access violation address register. Also, an access violation interrupt is
generated to the master CPU if enabled in the interrupt enable register.
3.11.1.6.6 CLA Read Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as program RAM for
the CLA, any data read access from the CLA to that particular LSx RAM results in a CLA read protection
violation, which is a non-master access violation.
If a CLA read protection violation occurs, a flag gets set into the appropriate access violation flag register,
and the memory address for which the access violation occurred, gets latched into the appropriate CLA
read access violation address register. Also, an access violation interrupt is generated to the master CPU
if enabled in the interrupt enable register.
3.11.1.6.7 DMA Write Protection
Write accesses from the DMA can be protected by setting the DMAWRPROTx bit of a specific register to
‘1.’ If write access is done by the DMA to protected memory, a write protection violation occurs.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
125
Memory Controller Module
www.ti.com
If a write access is made to GSx memory by a non-master DMA, it is called a non-master write protection
violation. If a write access is made to a dedicated or shared memory by a master DMA, and
DMAWRPROTx is set to ‘1’ for that memory, it is called a master DMA write protection violation.
A flag gets set in the DMA access violation flag register, and the memory address where the violation
happened gets latched in the DMA fetch access violation address register. These are dedicated registers
for each subsystem.
Note 1:
Note 2:
Note 3:
All access protections are ignored during debug accesses. Write access to a protected
memory will go through when it is done via the debugger, irrespective of the write protection
configuration for that memory.
Access protection is not implemented for M0 and M1 memories.
In the case of local shared RAM, if memory is shared between the CPU and its CLA, the
CPU will only have access if the memory is configured as data RAM for the CLA. If it is
programmed as program RAM, all the access from the CPU (including read) and data access
from the CLA will be blocked, and violation will be considered as a non-master access
violation. If the memory is configured as dedicated to the CPU, all access from the CLA will
be blocked and the violation will be considered a non-master access violation.
3.11.1.7 Memory Error Detection, Correction and Error Handling
These devices have memory error detection and correction features to satisfy safety standards
requirements. These requirements warrant the addition of detection mechanisms for finite dangerous
failures.
In this device, all dedicated RAMs support error correction code (ECC) protection and the shared RAMs
have parity protection. The ECC scheme used is Single Error Correction Double Error Detection
(SECDED). The parity scheme used is even parity. ECC/Parity will cover the data bits stored in memory
as well as address.
ECC/Parity calculation is done inside the memory controller module and then calculated. ECC/Parity is
written into the memory along with the data. ECC/Parity is computed for 16-bit data; hence, for each 32-bit
data, there will be three 7-bit ECC codes (or 3-bit parity), two of which are for data and a third one for the
address.
3.11.1.7.1 Error Detection and Correction
Error detection is done while reading the data from memory. The error detection is performed for data as
well as address. For parity memory, only a single-bit error gets detected, whereas in case of ECC
memory, along with a single-bit error, a double-bit error also gets detected. These errors are called
correctable error and uncorrectable errors. The following are characteristics of these errors:
• Parity errors are always uncorrectable errors
• Single-bit ECC errors are correctable errors
• Double-bit ECC errors are uncorrectable errors
• Address ECC errors are also uncorrectable errors
Correctable errors get corrected by the memory controller module and then correct data is given back as
read data to the master. It is also written back into the memory to prevent double-bit error due to another
single-bit error at the same memory address.
NOTE: ECC/Parity for address is calculated for address offset only (based on RAM block size) of
corresponding 32bit aligned address. E.g. in case of LSx RAM which are 4KB RAM block,
only 11 LSB of 32bit aligned address are used. So if address is 0x8F8F, address ECC (or
Parity) will be calculated for address 0x78E (11bit offset of 32bit aligned address). Similarly
for 8KB RAM block, 12bit address offset will be used.
126
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Memory Controller Module
www.ti.com
3.11.1.7.2 Error Handling
For each correctable error, the count in the correctable error count register will increment by one. When
the value in this count register becomes equal to the value configured into the correctable error threshold
register, an interrupt is generated to the respective CPU, that is, if the interrupt is enabled in the
correctable interrupt enable register. The user needs to configure the correctable error threshold register
based on the system requirements. Also, the address for which the error occurred, gets latched into the
master-specific status register and a flag gets set. Each of these registers are dedicated for each CPU
subsystem.
If there are uncorrectable errors, an NMI gets generated for the respective CPU. In this case, the address
for which the error occurred, also gets latched into the master-specific address status register, and a flag
gets set.
Table 3-11 summarizes different error situations that can arise. These need to be handled appropriately in
the software, using the status and interrupt indications provided.
Table 3-11. Error Handling in Different Scenarios
Access
Type
Error Found In
Error Type
Reads
Data read from
memory
Uncorrectable
Error
(Single-bit error
for Parity RAMs
OR
Double bit Error
for ECC RAMs)
Reads
Data read from
memory
Reads
Address
Status Indication
Yes -CPU1/CPU1.DMA/CPU1.CLA1
CPU/DMA/CLA Read Error Address
Register Data returned to
CPU1/CPU1.DMA/CPU1.CLA1 is
incorrect
Single-bit error for Yes - CPU1/CPU1.DMA CPU/DMA
ECC RAMs
Read Error Address Register
Increment single error counter
Address error
Yes - CPU1/CPU1.DMA/CPU1.CLA1
CPU/DMA/CLA Read Address Error
Register Data returned to
CPU1/CPU1.DMA/CPU1.CLA1 is
incorrect
Error Notification
NMI for CPU1 access
NMI for CPU1.DMA access
NMI to CPU for CPU1.CLA1 access
Interrupt when error counter reaches
the user programmable threshold for
single errors
NMI to CPU for CPU1 access
NMI to CPU for CPU1.DMA access
NMI to CPU for CPU1.CLA1 access
NOTE: In the case of an uncorrectable error during fetch on the CPU, there is the possibility of
getting an ITRAP before an NMI exception, since garbage instructions enter into the CPU
pipeline before the NMI gets generated.
During debug accesses, correctable as well as uncorrectable errors are masked.
3.11.1.8 Application Test Hooks for Error Detection and Correction
Since error detection and correction logic is part of safety critical logic, safety applications may need to
ensure that the logic is always working fine (during run time also). To enable this, a test mode is provided,
in which a user can modify the data bits (without modifying the ECC/Parity bits) or ECC/Parity bits directly.
Using this feature, an ECC/Parity error could be injected into data.
NOTE:
The memory map for ECC/Parity bits and data bits are the same. The user must choose a
different test mode to access ECC/Parity bits.
Table 3-12 shows the bit mapping for the ECC/Parity bits when they are read in RAMTEST mode using
their respective addresses.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control 127
Memory Controller Module
www.ti.com
Table 3-12. Mapping of ECC Bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data
6:0
Content (ECC Memory)
ECC Code for lower 16 bits of data
7
Not Used
14:8
ECC Code for upper 16 bits of data
15
Not Used
22:16
ECC Code for address
31:23
Not Used
Table 3-13. Mapping of Parity Bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data
0
7:1
8
15:9
16
31:17
Content (Parity Memory)
Parity for lower 16 bits of data
Not Used
Parity for upper 16 bits of data
Not Used
Parity for address
Not Used
3.11.1.9 RAM Initialization
To ensure that read/fetch from uninitialized RAM locations do not cause ECC or parity errors, the
RAM_INIT feature is provided for each memory block. Using this feature, any RAM block can be initialized
with 0x0 data and respective ECC/Parity bits accordingly. This can be initiated by setting the INIT bit to ‘1’
for the specific RAM block in INIT registers. To check the status of RAM initialization, SW should poll for
the INITDONE bit for that RAM block in the INITDONE register to be set. Unless this bit gets set, no
access should be made to that RAM memory block.
NOTE:
128
None of the masters should access the memory while initialization is taking place. If memory
is accessed before RAMINITDONE is set, the memory read/write as well as initialization will
not happen correctly.
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Flash and OTP Memory
www.ti.com
3.12 Flash and OTP Memory
Flash is an electrically erasable/programmable nonvolatile memory that can be programmed and erased
many times to ease code development. Flash memory can be used primarily as a program memory for the
core, and secondarily as static data memory.
This section describes the proper sequence to configure the wait states and operating mode of flash. It
also includes information on flash and OTP power modes, how to improve flash performance by enabling
the flash prefetch/cache mode, and the SECDED safety feature.
3.12.1 Features
Features of flash memory include:
• A flash bank (refer to the device data manual for the size of the flash bank)
• 128 bits (bank width) can be programmed at a time along with ECC
• Flash module controller (FMC)
• Multiple sectors providing the option of leaving some sectors programmed and only erasing specific
sectors
• User-programmable OTP locations (in USER OTP) for configuring security, OTP boot-mode and bootmode select pins (if the user is unable to use the factory-default boot-mode select pins)
• Flash pump
• Enhanced performance using the code-prefetch mechanism and data cache in FMC
• Configurable wait states to give the best performance for a given execution speed
• Safety Features
– SECDED-single error correction and double error detection is supported in the FMC
– Address bits are included in ECC
– Test mode to check the health of ECC logic
• Supports low-power modes for flash bank and pump for power savings
• Built-in power mode control logic
• Integrated flash program/erase state machine (FSM) in the FMC
– Fast erase and program times (refer to the device data manual for details)
• Code Security Module (CSM) to prevent access to the flash by unauthorized persons (refer to
Section 3.13 for details)
3.12.2 Flash Tools
Texas Instruments provides the following tools for flash:
• Code Composer Studio (CCS) - the development environment with integrated flash plugin
• F021 Flash API Library - a set of software peripheral functions to erase/program flash
• UniFlash - standalone tool to erase/program/verify the flash content through JTAG. No CCS is
required.
• CCS On-Chip Flash Plugin and UniFlash tools developed for these devices support
AutoEccGeneration (see TMS320F2837xD Flash API Version 1.54 Reference Guide , SPNU629). But
they do not support the program of ECC generated by the linker -ecc options.
• Users must check and install available updates for CCS On-Chip Flash Plugin and UniFlash tools.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
129
Flash and OTP Memory
www.ti.com
3.12.3 Default Flash Configuration
The following are flash module configuration settings at power-up :
• Flash bank is in sleep power mode
• Pump is in sleep mode
• ECC is enabled
• Wait-states are set to the maximum (0xF)
• Code-prefetch mechanism and data cache are disabled in the FMC
During the boot process, the boot ROM performs a dummy read of the Code Security Module (CSM)
password locations in the OTP. This read is performed to unlock a new (or erased) device that has no
password stored in it, so that flash programming or loading of code into CSM-protected SARAM can be
performed. On devices with a password, this read has no effect and the device remains locked. One effect
of this read is that the flash will transition from the sleep (reset) state to the active state.
User application software must initialize wait-states using the FRDCNTL register, and configure
cache/prefetch features using the RD_INTF_CTRL register, to achieve optimum system performance.
Software that configures flash settings like wait-states, cache/prefetch features, and so on, must be
executed only from RAM memory, not from flash memory.
NOTE: Before initializing wait-states, turn off the pre-fetch and data caching in the FRD_INTF_CTRL
register.
3.12.4 Flash Bank, OTP and Pump
There is one flash bank. Also, there is a one-time programmable (OTP) memory called USER OTP, which
the user can program only once and cannot erase. Flash and OTP are uniformly mapped in both program
and data memory space.
There is also a TI-OTP which contains manufacturing information like settings used by the flash state
machine for erase and program operations, and so on. Users may read TI-OTP but it cannot be
programmed or erased. For memory map and size information of the bank, TI-OTP, USER OTP and
corresponding ECC locations, please refer to the device data manual.
Bank and OTP share a common flash pump.
Figure 3-20 depicts the user-programmable OTP locations in USER-OTP . For more information on the
functionality of these fields, please refer to Section 3.13 and the ROM Code and Peripheral Booting
chapter.
3.12.5 Flash Module Controller (FMC)
The CPU interfaces with the FMC, which in turn interfaces with the Bank and the shared pump to perform
erase or program operations as well as to read data and execute code from the bank.
Figure 3-16. FMC Interface with Core, Bank and Pump
Bank
CPU
CPU
System
Clock
Pump
FMC
Control signals to the flash pump will be controlled by the FMC.
130
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Flash and OTP Memory
www.ti.com
There is a state machine in the FMC which generates the erase/program sequences in hardware. This
simplifies the Flash API software which configures control registers in the FMC to perform flash erase and
program operations (see TMS320F2837xD Flash API Version 1.54 Reference Guide , SPNU629, for
details on Flash API).
Section 3.12.6 through Section 3.12.10 describe FMC in detail.
3.12.6 Flash and OTP Power-Down Modes and Wakeup
The flash bank and pump consume a significant amount of power when active. The flash module provides
a mechanism to power-down the flash bank and pump. Special timers automatically sequence the powerup of the Bank. The charge pump module has its own independent power-up timer as well.
The flash bank and OTP operate in three power modes: Sleep (lowest power), Standby, and Active
(highest power)
• Sleep State
This is the state after a device reset. In this state, a CPU data read or opcode fetch will automatically
initiate a change in power mode to the standby state and then to the active state. During this transition
time to the active state, the CPU will automatically be stalled.
• Standby State
This state uses more power than the sleep state, but takes a shorter time to transition to the active or
read state. In this state, a CPU data read or opcode fetch will automatically initiate a change in power
mode to the active state. During this transition time to the active state, the CPU will automatically be
stalled. Once the flash/OTP has reached the active state, the CPU access will complete as normal.
• Active or Read State
In this state, the bank and pump are in active power mode state (highest power)
The charge pump operates in two power modes:
• Sleep (lowest power)
• Active (highest power)
Any access to flash bank/OTP causes the charge pump to go into active mode, if it is in sleep mode. An
erase or program command causes the charge pump and bank to become active. If the bank is in active
or in standby mode, the charge pump will be in active mode, independent of the pump power mode
control configuration (PMPPWR bit-field in the FPAC1 register). The application software can also check
the current power mode of the flash bank and charge pump by reading the FBPRDY register. See the
register descriptions for detailed information.
While the pump is in sleep state, a charge pump sleep down counter holds a user configurable value
(PSLEEP bit field in the FPAC1 register) and when the charge pump exits sleep power mode, the down
counter delays from 0 to PSLEEP prescaled SYSCLK clock cycles (prescaled clock is SYSCLK/2) before
putting the charge pump into active power mode. Note that the configured PSLEEP value should yield at
least a delay of 20us for the pump to go to active mode. Refer to the register descriptions, Section 3.15,
for detailed information. Before configuring Flash bank and pump power modes to sleep, make sure that
the VREADST (refer to the FBAC register) value is 0xF (which is the reset value) to ensure the requisite
delay needed for the flash pump/bank to come out of low-power mode later.
Below are the number of cycles it will take for the Bank and pump to wake up from low power modes.
1. Pump sleep to active = PSLEEP * (SYSCLK/2) cycles
2. Bank sleep to standby = 425 Flash clock cycles
3. Bank standby to active = 90 Flash clock cycles
Where in Flash clock = SYSCLK/(RWAIT+1)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
131
Flash and OTP Memory
www.ti.com
3.12.7 Flash and OTP Performance
Once the flash bank and pump are in the active power state, a read or fetch access can be classified as a
flash access (access to an address location in flash) or an OTP access (access to an address location in
OTP). Once the CPU throws an access to a flash memory address, data is returned after RWAIT+1
number of SYSCLK cycles. For a USER-OTP access, data is returned after 11 SYSCLK cycles.
RWAIT defines the number of random access wait-states and is configurable using the RWAIT bit-field in
the FRDCNTL register. At reset, the RWAIT bit-field defaults to a worst-case wait-state count (15), and
therefore needs to be initialized for the appropriate number of wait states to improve performance, based
on the CPU clock rate and the access time of the flash. The flash supports 0-wait accesses when the
RWAIT bits are set to zero. This assumes that the CPU speed is low enough to accommodate the access
time.
For a given system clock frequency, RWAIT has to be configured using below formula:
RWAIT = ceiling[(SYSCLK/FCLK)-1]
where SYSCLK is the system operating frequency
FCLK is flash clock frequency. FCLK should be ≤ FCLKmax, allowed maximum flash clock frequency at
RWAIT=0.
If RWAIT results in a fractional value when calculated using the above formula, RWAIT has to be rounded
up to the nearest integer.
3.12.8 Flash Read Interface
This section provides details about the data read modes to access flash bank/OTP and the configuration
registers which control the read interface. In addition to a standard read mode, the FMC has a built-in
prefetch and cache mechanism to allow increased clock speeds and CPU throughput wherever applicable.
3.12.8.1 FMC Flash Read Interface
3.12.8.1.1 Standard Read Mode
Standard read mode is defined as the read mode in effect when code prefetch-mechanism and data
cache are disabled. It is also the default read mode after reset. During this mode, each read access to
flash is decoded by the flash wrapper to fetch the data from the addressed location and the data is
returned after the RWAIT+1 number of cycles.
Prefetch buffers associated with prefetch mechanism and data cache are bypassed in standard read
mode; therefore, every access to the flash/OTP is used by the CPU immediately, and every access
creates a unique flash bank access.
Standard read mode is the recommended mode for lower system frequency operation in which RWAIT
can be set to zero to provide single-cycle access operation. The FMC can operate at higher frequencies
using standard read mode at the expense of adding wait states. At higher system frequencies, it is
recommended to enable cache and prefetch mechanisms to improve performance. Refer to the device
specific data manual to determine the maximum flash frequency allowed in standard read mode (that is,
maximum flash clock frequency with RWAIT=0, FCLKMAX).
3.12.8.1.2 Prefetch Mode
Flash memory is typically used to store application code. During code execution, instructions are fetched
from sequential memory addresses, except when a discontinuity occurs. Usually the portion of the code
that resides in sequential addresses makes up the majority of the application code and is referred to as
linear code. To improve the performance of linear code execution, a flash prefetch-mechanism has been
implemented in the FMC. Figure 3-17 illustrates how this mode functions.
132
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Flash and OTP Memory
www.ti.com
Figure 3-17. Flash Prefetch Mode
Flash and OTP
16-bit
Flash prefetch
Instruction buffer
Flash or OTP Read (128-bit)
128-bit 128-bit
buffer buffer
Instruction fetch
CPU
128-bit
Data cache
M
32-bit U
X
Data read from data memory
This prefetch mechanism does a look-ahead prefetch on linear address increments starting from the
address of the last instruction fetch. The flash prefetch mechanism is disabled by default. Setting the
PREFETCH_EN bit in the FRD_INTF_CTRL register enables this prefetch mode.
An instruction fetch from the flash or OTP reads out 128 bits per access. The starting address of the
access from flash is automatically aligned to a 128-bit boundary, such that the instruction location is within
the 128 bits to be fetched. With the flash prefetch mode enabled, the 128 bits read from the instruction
fetch are stored in a 128-bit wide by 2-level deep instruction prefetch buffer. The contents of this prefetch
buffer are then sent to the CPU for processing as required.
Up to four 32-bit or eight 16-bit instructions can reside within a single 128-bit access. The majority of C28x
instructions are 16 bits, so for every 128-bit instruction fetch from the flash bank, it is likely that there are
up to eight instructions in the prefetch buffer ready to process through the CPU. During the time it takes to
process these instructions, the flash prefetch mechanism automatically initiates another access to the
flash bank to prefetch the next 128 bits. In this manner, the flash prefetch mechanism works in the
background to keep the instruction prefetch buffers as full as possible. Using this technique, the overall
efficiency of sequential code execution from flash or OTP is improved significantly.
NOTE: If the prefetch mechanism is enabled, then the last two rows (16 16-bit words, 256 bits) of
the bank which does not have valid address beyond its boundary should not be used,
because the prefetch logic which does a look-ahead prefetch, will try to fetch from outside
the bank and would result in an ECC error.
The flash prefetch is aborted only on a PC discontinuity caused by executing an instruction such as a
branch, BANZ, call, or loop. When this occurs, the prefetch mechanism is aborted and the contents of the
prefetch buffer are flushed. There are two possible scenarios when this occurs:
1. If the destination address is within the flash or OTP, the prefetch aborts and then resumes at the
destination address.
2. If the destination address is outside of the flash and OTP, the prefetch is aborted and begins again
only when a branch is made back into the flash or OTP. The flash prefetch mechanism only applies to
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
133
Flash and OTP Memory
www.ti.com
instruction fetches from program space. Data reads from data memory and from program memory do
not utilize the prefetch buffer capability and thus bypass the prefetch buffer. For example, instructions
such as MAC, DMAC, and PREAD read a data value from program memory. When this read happens,
the prefetch buffer is bypassed but the buffer is not flushed. If an instruction prefetch is already in
progress when a data read operation is initiated, then the data read will be stalled until the prefetch
completes.
Note that the prefetch mechanism gets bypassed when RWAIT is configured as zero.
3.12.8.1.2.1 Data Cache
Along with the prefetch mechanism, a data cache of 128 bits wide is also implemented to improve dataspace read performance. This data cache will not be filled by the prefetch mechanism. When any kind of
data-space read is made by the CPU from an address in the bank, and if the data corresponding to the
requested address is not in the data cache, then 128 bits of data will be read from the bank and loaded in
the data cache. This data is eventually sent to the CPU for processing. The starting address of the access
from flash is automatically aligned to a 128-bit boundary such that the requested address location is within
the 128 bits to be read from the bank. By default, this data cache is disabled and can be enabled by
setting DATA_CACHE_EN bit in the FRD_INTF_CTRL register. Note that the data cache gets bypassed
when RWAIT is configured as zero.
Some other points to keep in mind when working with flash/ OTP:
• Reads of the USER OTP locations are hardwired for 10 wait states. The RWAIT bits have no effect on
these locations.
• CPU writes to the flash or OTP memory map areas are ignored. They complete in a single cycle.
• If a security zone is in the locked state and the respective password lock bits are not all 1s, then,
– Data reads to Zx-CSMPSWD will return 0
– Program space reads to Zx-CSMPSWD will return 0
– Program fetches to Zx-CSMPSWD will return 0
.
• When the Code Security Module (CSM) is secured, reads to the flash/OTP memory map area from
outside the secure zone take the same number of cycles as a normal access. However, the read
operation returns a zero.
• The arbitration scheme in FMC prioritizes CPU accesses in the fixed priority order of data read
(highest priority), program space read and program fetches/program prefetches (lowest priority).
• When FSM interface is active for erase/program operations, data in the prefetch buffers and data
cache in FMC will be flushed.
• When data cache is enabled, the debugger memory window open to Flash/OTP space will invoke data
caching. Hence, debugger memory window should not be left open for Flash/OTP space when
benchmarking the code for performance.
NOTE: Flash contents are verified for ECC correctness before they enter prefetch buffer or data
cache and not inside the prefetch buffer or data cache itself.
3.12.9 Erase/Program Flash
Flash memory may be programmed either by using the CCS Flash plugin or by using Uniflash. If these
methods are not feasible in an application, the API may be used. The Flash memory should be
programmed, erased, and verified only by using the F021 Flash API library. These functions are written,
compiled and validated by Texas Instruments. The flash module contains a flash state machine (FSM) to
perform program and erase operations. This section only provides a high level description for these
operations, therefore, refer to the TMS320F2837xD Flash API Version 1.54 Reference Guide (SPNU629)
for more information. Note that Flash API execution is interruptible. However, there should not be any
read/fetch access from the Flash bank on which an erase/program operation is in progress. Flash API
must be executed from RAM.
134
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Flash and OTP Memory
www.ti.com
A typical flow to program flash is:
Erase → Program → Verify
Always refer to the device-specific support folder in controlSUITE™ for the latest Flash API library.
3.12.9.1 Erase
When the target flash is erased, it reads as all 1's. This state is called 'blank.' The erase function must be
executed before programming. The user should NOT skip erase on sectors that read as 'blank' because
these sectors may require additional erasing due to marginally erased bits columns. The FSM provides an
“Erase Sector” command to erase the target sector. The erase function erases the data and the ECC
together. This command is implemented by the following Flash API function:
Fapi_issueAsyncCommandWithAddress();
The Flash API provides the following function to determine if the flash bank is 'blank':
Fapi_doBlankCheck();
3.12.9.2 Program
The FSM provides a command to program the USER OTP and Flash. This command is also used to
program ECC check bits.
This command is implemented by the following Flash API function:
Fapi_issueProgrammingCommand();
The Program function provides the options to program data without ECC, data along with user-provided
ECC data, data along with ECC calculated by API software using ECC logic in the device, and to program
ECC only.
3.12.9.3 Verify
After programming, the user must perform verify using API function Fapi_doVerify(). This function verifies
the flash contents against supplied data.
Application software typically perform a CRC check of the Flash memory contents during power-up and at
regular intervals during runtime (as needed). Apart from this, ECC logic, when enabled (enabled by
default), catches single-bit errors, double-bit errors, and address errors whenever the CPU reads/fetches
from a Flash address.
3.12.10 Error Correction Code (ECC) Protection
FMC contains an embedded single error correction and double error detection (SECDED) module.
SECDED, when enabled, provides the capability to screen out memory faults. SECDED can detect and
correct single-bit data errors and detect address errors/double-bit data errors. For every 64 bits of
flash/OTP data (aligned on a 64-bit memory boundary) that is programmed, eight ECC check bits have to
be calculated and programmed in ECC memory space. Refer to the device data manual for the Flash/OTP
ECC memory map. SECDED works with a total of eight error correction code (ECC) check bits associated
with each 64-bit wide data word and its corresponding 128-bit memory-aligned address. Users must
program ECC check bits along with flash data. TI recommends using the AutoEccGeneration option
available in Plugin/API to program ECC. Users can use the F021 Flash API to calculate and program ECC
data along with flash data. Flash API uses hardware ECC logic in the device to generate the ECC data for
the given Flash data. The Flash Plugin, the Flash programming tool integrated with Code Composer
Studio, uses Flash API to generate and program ECC data).
Figure 3-18 illustrates the ECC logic inputs and outputs.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
135
Flash and OTP Memory
www.ti.com
Figure 3-18. ECC Logic Inputs and Outputs
Single-bit data error
Address/Double-bit data error
Single-bit Error position
Corrected data out
SECDED
ECC[15:8]
Data[127:64]
128-bit aligned 19-bit CPU address
Flash
and
OTP
Single-bit data error
Address/Double-bit data error
Single-bit Error position
Corrected data out
SECDED
Data[63:0]
ECC[7:0]
During an instruction fetch or a data read operation, the 19 most significant address bits (three least
significant bits of address are not considered), together with the 64-bit data/8-bit ECC read-out of flash
banks/ECC memory map area, pass through the SECDED logic and the eight checkbits are produced in
FMC. These eight calculated ECC check bits are then XORed with the stored check bits (user
programmed check bits) associated with the address and the read data. The 8-bit output is decoded inside
the SECDED module to determine one of three conditions:
• No error occurred
• A correctable error (single bit data error) occurred
• A non-correctable error (double bit data error or address error) occurred
If the SECDED logic finds a single-bit error in the address field, then it is considered to be a noncorrectable error.
NOTE: TI recommends programming ECC while programming Flash to avoid any error. Since ECC
is calculated for an entire 64-bit data, a non 64-bit read such as a byte read or a half-word
read will still force the entire 64-bit data to be read and calculated, but only the byte or halfword will be actually used by the CPU.
This ECC (SECDED) feature is enabled at reset. The ECC_ENABLE register can be used to configure(
enable/disable) the ECC feature. The ECC for the application code must be programmed.. There are two
SECDED modules in the FMC. Out of the 128-bit data (aligned on a 128-bit memory boundary) read from
the bank/OTP address, the lower 64-bits of data and corresponding 8 ECC bits (read from user
programmable ECC memory area) are fed as inputs to one SECDED module along with 128-bit aligned
19-bit address from where data has been read. The upper 64- bits of data and corresponding 8 ECC bits
are fed as inputs to another SECDED module in parallel, along with 128-bit aligned 19-bit address. Each
of the SECDED modules evaluate their inputs and determine if there is any single-bit data error or doublebit data error/address error.
ECC logic will be bypassed when the 64 data bits and the associated ECC bits fetched from the bank are
either all ones or zeros.
136
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Flash and OTP Memory
www.ti.com
3.12.10.1 Single-Bit Data Error
This section provides information for both single-bit data errors and single-bit ECC check bit errors. If
there is a single bit flip (0 to 1 or 1 to 0) in flash data or in ECC data, then it is considered as a single-bit
data error. The SECDED module detects and corrects single-bit errors, if any, in the 64-bit flash data or
eight ECC check bits read from the flash/ECC memory map before the read data is provided to the CPU.
When SECDED finds and corrects single bit data errors, the following information is logged in the ECC
registers if the ECC feature is enabled:
• Address where the error occurred – if the single-bit error occurs in the lower 64-bits of a 128-bit
memory-aligned data, the lower 64-bit memory-aligned address will be captured in the
SINGLE_ERR_ADDR_LOW register. If the single-bit error occurs in the upper 64-bits of a 128-bit
memory-aligned data, the upper 64-bit memory-aligned address will be captured in the
SINGLE_ERR_ADDR_HIGH register.
• Whether the error occurred in data bits or ECC bits – the ERR_TYPE_L and ERR_TYPE_H bit fields in
the ERR_POS register indicate whether the error occurred in data bits or ECC bits of the lower 64-bits,
or the upper 64-bits respectively, of a 128-bit memory-aligned data.
• Bit position at which error occurred – the ERR_POS_L and ERR_POS_H bit fields in the ERR_POS
register indicate the bit position of the error in the lower 64-bits/lower 8-bit ECC, or the upper 64bits/upper 8-bit ECC respectively, of a 128-bit memory-aligned data.
• Whether the corrected value is 0 (FAIL_0_L, FAIL_0_H flags in ERR_STATUS register)
• Whether the corrected value is 1 (FAIL_1_L, FAIL_1_H flags in ERR_STATUS register)
• A single bit error counter that increments on every single bit error occurrence (ERR_CNT register) until
a user-configurable threshold (see ERR_THRESHOLD) is met
• A flag that gets set when one or more single-bit errors occurs after ERR_CNT equals
ERR_THRESHOLD (SINGLE_ERR_INT_FLG flag in the ERR_INTFLG register)
When the ERR_CNT value equals THRESHOLD+1 value and a single bit error occurs, the
SINGLE_ERR_INT flag is set, and an interrupt (FLASH_CORRECTABLE_ERR on C28x PIE has to be
enabled for interrupt, if needed) is fired. The SINGLE_ERR interrupt will not be fired again until the
SINGLE_ERR_INTFLG is cleared. If the single error interrupt flag is not cleared using the corresponding
error interrupt clear bit in the ERR_INTCLR register, the error interrupt will not come again, as this is an
edge-based interrupt.
When multiple single-bit errors get caught by ECC logic, Flash ECC registers will hold the information
related to the latest ECC error. When multiple single-bit errors get caught, both FAIL_0_L and FAIL_1_L
(and/or FAIL_0_H and FAIL_1_H) might get set, indicating that single-bit fail0/fail1 occurred in different 64bit aligned addresses.
Although ECC is calculated on 64-bit basis, a read of any address location within a 128-bit aligned Flash
memory will cause the single-bit error flag to get set when there is a single-bit error in both or in either one
of the lower 64 and upper 64 bits (or corresponding ECC check bits) of that 128-bit data.
3.12.10.2 Uncorrectable Error
Uncorrectable errors include address errors and double-bit errors in data/ECC. When SECDED finds
uncorrectable errors, the following information is logged in ECC registers if the ECC feature is enabled:
• Address where the error occurred – if the uncorrectable error occurs in the lower 64-bits of a 128-bit
memory-aligned data, the lower 64-bit memory-aligned address will be captured in the
UNC_ERR_ADDR_LOW register. If the uncorrectable error occurs in the upper 64-bits of a 128-bit
memory-aligned data, the upper 64-bit memory-aligned address will be captured in the
UNC_ERR_ADDR_HIGH register.
• A flag is set indicating that an uncorrectable error occurred – the UNC_ERR_L and UNC_ERR_H flags
in the ERR_STATUS register indicate the uncorrectable error occurrence in the lower 64-bits/lower 8bit ECC, or the upper 64-bits/upper 8-bit ECC, respectively, of a 128-bit memory-aligned data.
• A flag is set indicating that an uncorrectable error interrupt is fired (UNC_ERR_INTFLG in
ERR_INTFLG register)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
137
Flash and OTP Memory
www.ti.com
When an uncorrectable error occurs, the UNC_ERR_INTFLG bit is set and an uncorrectable error interrupt
is fired. This uncorrectable error interrupt generates an NMI, if enabled. If an uncorrectable error interrupt
flag is not cleared using the corresponding error interrupt clear bit in the ERR_INTCLR register, an error
interrupt will not come again, as this is an edge based interrupt.
Although ECC is calculated on 64-bit basis, a read of any address location within a 128-bit aligned Flash
memory will cause the uncorrectable error flag to get set when there is a uncorrectable error in both or in
either one of the lower 64 and upper 64 bits (or corresponding ECC check bits) of that 128-bit data. NMI
will occur on the CPU for a read of any address location within a 128-bit aligned Flash memory, when
there is an uncorrectable error in both or in either one of the lower 64 and upper 64 bits (or corresponding
ECC check bits) of that 128-bit data.
3.12.10.3 SECDED Logic Correctness Check
Since error detection and correction logic are part of safety-critical logic, safety applications may need to
ensure that the SECDED logic is always working properly. For these safety concerns, in order to ensure
the correctness of the SECDED logic, an ECC test mode is provided to test the correctness of ECC logic
periodically. In this ECC test mode, data/ECC and address inputs to the ECC logic are controlled by the
ECC test mode registers FDATAH_TEST, FDATAL_TEST, FECC_TEST, and FADDR_TEST,
respectively. Using this test mode, users can introduce single-bit errors, double-bit errors, or address
errors and check whether or not SECDED logic is catching those errors. Users can also check if SECDED
logic is reporting any false errors when no errors are introduced.
This ECC test mode can be enabled by setting the ECC_TEST_EN bit in the FECC_CTRL register. When
ECC test mode is enabled, the CPU cannot read the data from flash and instead the CPU gets data from
the ECC test mode registers (FDATAH_TEST/FDATAL_TEST). This is because ECC test mode registers
(FDATAH_TEST, FDATAL_TEST, FECC_TEST) are multiplexed with data from the flash. Hence, the CPU
should not read/fetch from Flash when ECC test mode is enabled. For this reason, ECC test mode code
should be executed from RAM and not from flash.
Only one of the SECDED modules (out of the two SECDED modules that work on lower 64 bits and upper
64 bits of a read 128-bit data) at a time can be tested. The ECC_SELECT bit in the FECC_CTRL register
can be configured by users to select one of the SECDED modules for test.
To test the ECC logic using ECC test mode, users can follow the steps below:
1. Obtain the ECC for a given Flash address (128-bit aligned) and 64-bit data by using the Auto ECC
generation option provided in Flash API .
2. Develop an application to test ECC logic using the above data. In this application
• Write the 128-bit aligned 19-bit Flash address in FADDR_TEST
• Write 64-bit data in FDATAH_TEST (upper 32-bits) and FDATAL_TEST (lower 32-bits) registers
• Write the corresponding 8-bit ECC in the FECC_TEST register
• In any of the above three steps, users can insert errors (single-bit data error or double-bit data
error or address error or single-bit ECC error or double-bit ECC error) so that they can check
whether or not ECC logic is able to catch the errors
• Select the ECC logic block (lower 64-bits or upper 64-bits) which needs to be tested using the
ECC_SELECT bit in the FECC_CTRL register
• Enable ECC test mode usingthe ECC_TEST_EN bit in FECC_CTRL register
• Write a value of 1 in the DO_ECC_CALC bit in FECC_CTRL register to enable ECC test logic for a
single cycle to evaluate the address, data, ECC in FADDR_TEST, FDATAx_TEST and
FECC_TEST registers for ECC errors
Once the above ECC test mode registers are written by the user:
• The FECC_OUTH register holds the data output bits 63:32 from the SECDED block under test
• The FECC_OUTL register holds the data output bits 31:0 from the SECDED block under test
• The FECC_STATUS register holds the status of single-bit error occurrence, uncorrectable error
occurrence, and error position of single- bit error in data/check bits
138
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Flash and OTP Memory
www.ti.com
3.12.10.4 Reading ECC Memory From a Higher Address Space
In these devices, ECC memory for Flash and OTP is allocated at a higher address space (address width
more than 22 bits). C2000 Codegen tools (6.2 and onwards) are updated to include the below intrinsics to
read ECC space.
For 16-bit read:
unsigned int variable = __addr32_read_uint16(unsigned long address);
For 32-bit read:
unsigned long variable = __addr32_read_uint32(unsigned long address);
3.12.11 Reserved Locations Within Flash and OTP
When allocating code and data to flash and OTP memory, keep the following reserved locations in mind:
• The entire OTP has reserved user-configurable locations for security and boot process. For more
details on the functionality of these fields, please refer to Section 3.13, and the ROM Code and
Peripheral Booting chapter.
• Refer to the ROM Code and Peripheral Booting chapter for reserved locations in flash for real-time
operating system usage and a boot-to-flash entry point. A boot-to-flash entry point is reserved for an
entry-into-flash branch instruction. When the boot-to-flash boot option is used, the boot ROM will jump
to this address in flash. If the user programs a branch instruction here, that will then redirect code
execution to the entry point of the application.
3.12.12 Procedure to Change the Flash Control Registers
During flash configuration, no accesses to the flash or OTP can be in progress. This includes instructions
still in the CPU pipeline, data reads, and instruction prefetch operations. To be sure that no access takes
place during the configuration change, you should follow the procedure shown below for any code that
modifies the flash control registers.
1. Start executing application code from RAM/Flash/OTP.
2. Branch to or call the flash configuration code (that writes to flash control registers) in RAM. This is
required to properly flush the CPU pipeline before the configuration change. The function that changes
the flash configuration cannot execute from the Flash or OTP. It must reside in RAM.
3. Execute the flash configuration code (should be located in RAM) that writes to flash control registers
like FRDCNTL, FRD_INTF_CTRL, and so on.
4. At the end of the flash configuration code execution, wait eight cycles to let the write instructions
propagate through the CPU pipeline. This must be done before the return-from-function call is made.
5. Return to the calling function which might reside in RAM or Flash/OTP and continue execution.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
139
Dual Code Security Module (DCSM)
www.ti.com
3.13 Dual Code Security Module (DCSM)
The dual code security module (DCSM) is a security feature incorporated in this device. It prevents access
and visibility to on-chip secure memories (and other secure resources) to unauthorized persons. It also
prevents duplication and reverse engineering of proprietary code. The term “secure” implies access to onchip secure memories and resources are blocked. The term “unsecure” implies access is allowed (the
contents of the memory could be read by any means); for example, through a debugging tool such as
Code Composer Studio™.
The CPU subsystem's CSM has dual-zone security, zone1 and zone2.
3.13.1 Functional Description
The security module restricts the CPU access to on-chip secure memory and resources without
interrupting or stalling CPU execution. When a read occurs to a secure memory location, the read returns
a zero value and CPU execution continues with the next instruction. This, in effect, blocks read and write
access to secure memories through the JTAG port or external peripherals.
The code security mechanism offers protection for two zones, Zone 1 (Z1) and Zone 2 (Z2). The security
mechanism for both the zones is identical. Each zone has its own dedicated secure resource and
allocated secure resource. The following are different secure resources available on this device:
• OTP: Each zone has its own dedicated secure OTP (USER OTP). This contains the security
configurations for the individual zone. If a zone is secure, its USER OTP content (including CSM
passwords) can be read (execution not allowed) only if the zone is unlocked using the password match
flow (PMF).
• CLA: The CLA is a secure resource which can be allocated to either zone by configuring the
GRABRAM location in the USER OTP. CLA configuration can only be performed by code running from
the zone to which it has been allocated. The CLA message RAMs also belong to the same zone.
Table 3-14. CLA Access Filter
•
•
•
CLA Ownership
RAM Block Ownership
Fetch Access
Read Access
Write Access
None
None
Yes
Yes
Yes
None
Z1 or Z2
No
No
No
Z1
Z1
Yes
Yes
Yes
Z1
Z2
No
No
No
Z2
Z1
No
No
No
Z2
Z2
Yes
Yes
Yes
RAM: All Dx and LSx RAMs can be secure RAM on this device. These RAMs can be allocated to
either zone by configuring the respective GRABRAM location in the USER OTP.
Flash Sectors: Flash Sectors can be secure on this device. Each Flash sector can be allocated to
either zone by configuring the respective GRABSECT location in the USER OTP.
Secure ROM: This device also has secure ROM which is EXEONLY-protected. This ROM contains
specific function for the user, provided by TI.
Table 3-15 shows the status of a RAM block based on the configuration in GRABRAM register.
Table 3-15. RAM Status
140
GRAM_RAMx Bits in Z1_GRABRAMR
Register
GRAM_RAMx Bits in Z2_GRABRAMR
Register
00
XX
GRAM_RAMx is inaccessible
XX
00
GRAM_RAMx is inaccessible
Differential Value (01/10)
Differential Value (01/10)
GRAM_RAMx is inaccessible
Differential Value (01/10)
11
GRAM_RAMx belongs to Z1
11
Differential Value (01/10)
GRAM_RAMx belongs to Z2
11
11
GRAM_RAMx is Non-Secure
System Control
Ownership
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Dual Code Security Module (DCSM)
www.ti.com
The security of each zone is ensured by its own 128-bit (four 32-bit words) password (CSM password).
The password for each zone is stored in its dedicated OTP location based on a zone-specific link pointer.
A zone can be unsecured by executing the password match flow (PMF), described in Section 3.13.3.3.2.
There are three types of accesses: data/program reads, JTAG access, and instruction fetches (calls,
jumps, code executions, ISRs). Instruction fetches are never blocked. JTAG accesses are always blocked
when a memory is secure. Data reads to a secure memory are always blocked unless the program is
executing from a memory which belongs to the same zone. Data reads to unsecure memory are always
allowed. Table 3-16 shows the levels of security.
Table 3-16. Security Levels
PMF Executed With Correct
Password?
Operating Mode of the Zone
Program Fetch Location
Security Description
No
Secure
Outside secure memory
Only instruction fetches by the
CPU are allowed to secure
memory. In other words, code
can still be executed, but not
read.
No
Secure
Inside secure memory
CPU has full access (except for
EXEONLY memories where
read is not allowed). JTAG port
cannot read the secured
memory contents.
Yes
Non-Secure
Anywhere
Full access for CPU and JTAG
port to secure memory of that
zone.
If the password locations of a zone have all 128 bits as ones, the zone is considered unsecure. Since new
Flash devices have erased Flash (all ones), only a read of the password locations is required to bring any
zone into unsecure mode. If the password locations of a zone have all 128 bits as zeros, the zone is
secure, regardless of the contents of the CSMKEY registers. This means the zone can’t be unlocked using
PMF, the password match flow described in Section 3.13.3.3.2. Therefore, the user should never use all
zeros as a password. A password of all zeros will prevent debug of secure code or reprogramming the
Flash.
CSMKEY registers are user-accessible registers that are used to unsecure the zones.
3.13.1.1 Emulation Code Security Logic (ECSL)
In addition to the CSM, the emulation code security logic (ECSL) has been implemented using a 64-bit
password (part of existing CSM password) for each zone to prevent unauthorized users from stepping
through secure code. A halt in secure code while the emulator is connected will trip the ECSL and break
the emulation connection. To allow emulation of secure code, while maintaining the CSM protection
against secure memory reads, the user must write the correct 64-bit password into the CSMKEY (0/1)
registers, which matches the password value stored in the USER OTP of that zone. This will disable the
ECSL for the specific zone.
When initially debugging a device with the password locations in OTP programmed (secured), the
emulator takes some time to take control of the CPU. During this time, the CPU will start running and may
execute an instruction that performs an access to a protected ECSL area and ifthe CPU is halted when
the program counter (PC) is pointing to a secure location, the ECSL will trip and cause the emulator
connection to be broken.
The solution to this problem is:
• Use the Wait Boot Mode boot option. In this mode, the CPU will be in a loop and hence will not jump to
the user application code. Using this BOOTMODE, the user can connect to CCS and debug the code.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
141
Dual Code Security Module (DCSM)
www.ti.com
3.13.1.2 CPU Secure Logic
The CPU Secure Logic (CPUSL) on this device prevents a hacker from reading the CPU registers in a
watch window while code is running in a secure zone. All accesses to CPU registers when the PC points
to a secure location are blocked by this logic. The only exception to this is read access to the PC. It is
highly recommended not to write into the CPU register in this case, because proper code execution may
get affected. If the CSM is unlocked using the CSM password match flow, the CPUSL logic also gets
disabled.
3.13.1.3 Execute-Only Protection
To achieve a higher level of security on secure Flash sectors and RAM blocks that store critical user code
(instruction opcodes), the Execute-Only protection feature is provided. When the Execute-Only protection
is turned on for any secure Flash sector or RAM block, data reads to that Flash sectors are disallowed
from any code (even from secure code). Execute-only protection for a Flash sector and RAM block can be
turned on by configuring the bit field associated for that particular sector/RAM block in the zone's (which
has ownership of that sector/RAM block) EXEONLYSECT and EXEONLYRAM register, respectively.
3.13.1.4 Password Lock
The password locations for each zone can be locked by programming the zone’s PSWDLOCK field with
any value other than “1111” (0xF) at the PSWDLOCK location in OTP. Until the passwords of a zone are
locked, password locations will not be secure and can be read from the debugger as well as code running
from non-secure memory. This feature can be used by the user to avoid accidental locking of the zone
while programming the Flash sectors during the software development phase. On a fresh device the value
for password lock fields for all zones at the PSWDLOCK location in OTP will be “1111” which means the
password for all zones will be unlocked.
NOTE: Password unlock only makes password locations non-secure. All other secure memories and
other locations of Flash sectors, which contain a password, remains secure as per security
settings. But since passwords are non-secure, anyone can read the password and make the
zone non-secure by running through PMF.
3.13.1.5 Link Pointer and Zone Select
For each of the two security zones a dedicated OTP block exists that holds the configuration related to
zone’s security. The following are the available programmed configurations:
• Zx-LINKPOINTER1
• Zx-LINKPOINTER2
• Zx-LINKPOINTER3
• Zx-PSWDLOCK
• Zx-CRCLOCK
• Zx-BOOTCTRL
• Zx-EXEONLYRAM
• Zx-EXEONLYSECT
• Zx-GRABRAM
• Zx-GRABSECT
• Zx-CSMPASSWORD
Since OTP can’t be erased, to provide flexibility of configuring some of the security settings like CSM
passwords, allocation of RAM/Flash sectors and their attributes, multiple times by the user, the following
configurations are placed in zone select regions of each zone’s OTP Flash.
• Zx-EXEONLYRAM
• Zx-EXEONLYSECT
• Zx-GRABRAM
142
System Control
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Dual Code Security Module (DCSM)
www.ti.com
•
•
Zx-GRABSECT
Zx-CSMPASSWORD
The location of the zone select region in OTP is decided based on the value of three 29-bit link pointers
(Zx-LINKPOINTERx) programmed in the OTP of each zone. All OTP locations except link pointer locations
are protected with ECC. Since the link pointer locations are not protected with ECC, three link pointers are
provided that need to be programmed with the same value. The final value of the link pointer is resolved in
hardware when a dummy read is done to all the link pointers by comparing all the three values (bit-wise
voting logic). Since in OTP, a ‘1’ can be flipped by the user to ‘0’ but ‘0’ can’t be flipped to ‘1’ (no erase
operation for OTP), the most significant bit position in the resolved link pointer which is ‘0’, defines the
valid base address for the zone select region. While generating the final link pointer value, if the bit
patterns is not one of those listed in Figure 3-19, the final link pointer value becomes All_1
(0xFFFF_FFFF) which selects the Zone-Select-Block1 (also known as the default zone select block).
Figure 3-19. Storage of Zone-Select Bits in OTP
Zx-LINKPOINTER
32’bxxx11111111111111111111111111111
32’bxxx1111111111111111111111111111
0
32’bxxx111111111111111111111111111
0x
32’bxxx11111111111111111111111111
0xx
32’bxxx1111111111111111111111111
0xxx
32’bxxx111111111111111111111111
0xxxx
32’bxxx11111111111111111111111
0xxxxx
32’bxxx1111111111111111111111
0xxxxxx
32’bxxx111111111111111111111
0xxxxxxx
32’bxxx11111111111111111111
0xxxxxxxx
32’bxxx1111111111111111111 0xxxxxxxxx
32’bxxx111111111111111111 0xxxxxxxxxx
32’bxxx11111111111111111 0xxxxxxxxxxx
32’bxxx1111111111111111 0xxxxxxxxxxxx
32’bxxx111111111111111 0xxxxxxxxxxxxx
32’bxxx11111111111111 0xxxxxxxxxxxxxx
32’bxxx1111111111111 0xxxxxxxxxxxxxxx
32’bxxx111111111111 0xxxxxxxxxxxxxxxx
32’bxxx11111111111 0xxxxxxxxxxxxxxxxx
32’bxxx1111111111 0xxxxxxxxxxxxxxxxxx
32’bxxx111111111 0xxxxxxxxxxxxxxxxxxx
32’bxxx11111111 0xxxxxxxxxxxxxxxxxxxx
32’bxxx1111111 0xxxxxxxxxxxxxxxxxxxxx
32’bxxx111111 0xxxxxxxxxxxxxxxxxxxxxx
32’bxxx11111 0xxxxxxxxxxxxxxxxxxxxxxx
32’bxxx1111 0xxxxxxxxxxxxxxxxxxxxxxxx
32’bxxx111 0xxxxxxxxxxxxxxxxxxxxxxxxx
32’bxxx11 0xxxxxxxxxxxxxxxxxxxxxxxxxx
32’bxxx10xxxxxxxxxxxxxxxxxxxxxxxxxxx
32’bxxx0xxxxxxxxxxxxxxxxxxxxxxxxxxxx
Addr Offset Of
Zone-Select
Block
0x20
0x30
0x40
0x50
0x60
0x70
0x80
0x90
0xa0
0xb0
0xc0
0xd0
0xe0
0xf0
0x100
0x110
0x120
0x130
0x140
0x150
0x160
0x170
0x180
0x190
0x1a0
0x1b0
0x1c0
0x1d0
0x1e0
0x1f0
Zone Select Block
Addr Offset
32-Bit Content
0x0
Zx-EXEONLYRAM
0x2
Zx-EXEONLYSECT
0x4
Zx-GRABRAM
0x6
Zx-GRABSECT
0x8
Zx-CSMPSWD0
0xa
Zx-CSMPSWD1
0xc
Zx-CSMPSWD2
0xe
Zx-CSMPSWD3
NOTE: Address locations for other security settings (PSWDLOCK/CRCLOCK) that are not part of
Zone Select blocks) can be programmed only once; therefore, the user should program them
towards end of the development cycle.
NOTE: Since linkpointer location in USER OTP does not have ECC user should always define
separate structure and section for linkpointers.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System Control
143
Dual Code Security Module (DCSM)
www.ti.com
Figure 3-20. Location of Zone-Select Block Based on Link-Pointer
Zone 1 OTP Flash
0x78000
Zone 2 OTP Flash
Z1-LINKPOINTER 1
0x78200
Z2-LINKPOINTER 1
0x78002
Reserved
0x78202
Reserved
0x78004
Z1-LINKPOINTER 2
0x78204
Z2-LINKPOINTER 2
0x78006
Reserved
0x78206
Reserved
0x78008
Z1-LINKPOINTER 3
0x78208
Z2-LINKPOINTER 3
Reserved
0x7820A
Reserved
0x78210
Z2 PSWDLOCK
0x78212
Reserved
0x7800A
0x78010
Z1-PSWDLOCK
0x78012
0x78014
Zone Select Block
Reserved
Addr
Offset
Z1-CRCLOCK
0x78016
Reserved
0x78018
Reserved
32-Bit Content
0x78214
0x0
Zx-EXEONLYRAM
0x2
Zx-EXEONLYSECT
0x4
Zx-GRABRAM
0x7801A
Reserved
0x7801E
Z1-BOOTCTRL
0x78020
ZoneSelectBlock1
(16x16Bits)
0x6
Zx-GRABSECT
0x8
Zx-CSMPSWD0
0x78030
ZoneSelectBlock2
(16x16Bits)
0xa
Zx-CSMPSWD1
0xc
Zx-CSMPSWD2
0xe
Zx-CSMPSWD3
.
.
0x781F0
Z2-CRCLOCK
0x78216
Reserved
0x78218
Reserved
0x7821A
Reserved
0x7821E
Z2-BOOTCTRL
0x78220
ZoneSelectBlock1
(16x16Bits)
0x78230
ZoneSelectBlock2
(16x16Bits)
.
.
ZoneSelectBlockn
(16x16Bits)
0x783F0
ZoneSelectBlockn
(16x16Bits)
3.13.1.5.1 C Code Example to get Zone Select Block Addr for Zone1
unsigned long LinkPointer;
unsigned long *Zone1SelBlockPtr;
int Bitpos = 28;
int ZeroFound = 0;
// Read Z1-Linkpointer register of DCSM module.
LinkPointer = *(unsigned long *)0x5F000;
// Bits 31 30 and 29 as most-sigificant 0 are reserved LinkPointer options
LinkPointer = LinkPointer -1))
{
if ((LinkPointer & 0x80000000) == 0)
{
ZeroFound = 1;
Zone1SelBlockPtr = (unsigned long *)(0x78000 + ((bitpos + 3)*16));
} else
{
bitpos--;
LinkPointer = LinkPointer 0
No (Burst Complete)
HALT
here
Burst Complete (BURSTSTS = 0)
TRANSFER_COUNT-SRC_ADDR_ACTIVE += SRC_TRANSFER_STEP
DST_ADDR_ACTIVE += DST_TRANSFER_STEP
TRANSFER_COUNT > 0
No
Points where
state machine
branches to next
channel
When CHINTMODE == 1,
Generate EPIE interrupt
at end of DMA transfer
Yes
CONTINUOUS Enabled?
[CONTINUOUS = 1]
End DMA Transfer
[TRANSFERSTS = 0]
No
DMA Channel disabled
RUNSTS = 0
Yes
Yes
SRC_WRAP_COUNT --
SRC_WRAP_COUNT > 0
DST_WRAP_COUNT --
DST_WRAP_COUNT > 0
No
SRC_WRAP_COUNT
= SRC_WRAP_SIZE
SRC_BEG_ADDR_ACTIVE += SRC_WRAP_STEP
SRC_ADDR_ACTIVE
= SRC_BEG_ADDR_ACTIVE
( }v[š v
š} Á ]š (}Œ
DMA trigger event)
Yes
Points where
state machine
branches to next
channel
ONESHOT Enabled?
[ONESHOT = 1]
DST_WRAP_COUNT
= DST_WRAP_SIZE
DST_BEG_ADDR_ACTIVE += DST_WRAP_STEP
DST_ADDR_ACTIVE
= DST_BEG_ADDR_ACTIVE
HALT
here
No
Wait for DMA Trigger Event
No
Another DMA trigger
event
Yes
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
601
Pipeline Timing and Throughput
www.ti.com
The following items are in reference to Figure 5-5.
• The HALT points represent where the channel halts operation when interrupted by a high priority
channel 1 trigger, or when the HALT command is set, or when an emulation halt is issued and the
FREE bit is cleared to 0.
• The SRC/DST_ADDR_ACTIVE registers are not affected by SRC/DST_BEG_ADDR_ACTIVE at the
start of a transfer. SRC/DST_BEG_ADDR_ACTIVE only affects the SRC/DST_ADDR_ACTIVE
registers on a wrap. Following is what happens when a transfer first starts:
– SRC/DST_BEG_ADDR_SHADOW remains unchanged.
– SRC/DST_ADDR_SHADOW remains unchanged.
– SRC/DST_BEG_ADDR_ACTIVE = SRC/DST_BEG_ADDR_SHADOW
– SRC/DST_ADDR_ACTIVE = SRC/DST_ADDR_SHADOW
• The active registers get updated when a wrap occurs. The shadow registers remain unchanged.
Specifically:
– SRC/DST_BEG_ADDR_SHADOW remains unchanged.
– SRC/DST_ADDR_SHADOW remains unchanged.
– SRC/DST_BEG_ADDR_ACTIVE += SRC/DST_WRAP_STEP
– SRC/DST_ADDR_ACTIVE = SRC/DST_BEG_ADDR_ACTIVE
• The best way to remember this is:
– The shadow registers never change except by software.
– The active registers never change except by hardware, and a shadow register is only copied into its
own active register, never an active register by another name.
5.5
Pipeline Timing and Throughput
In
•
•
•
•
addition to the pipeline there are a few other behaviors of the DMA that affect its total throughput:
A 1-cycle delay is added at the beginning of each burst
A 1-cycle delay is added when returning from a CH1 high priority interrupt
Collisions with the CPU may add delay slots (see Section 5.6)
32-bit transfers run at double the speed of a 16-bit transfer (it takes the same amount of time to
transfer a 32-bit word as it does a 16-bit word)
For example, to transfer 128 16-bit words from GS0 RAM to GS3 RAM, a channel can be configured to
transfer 8 bursts of 16 words/burst. This will give:
8 bursts * [(3 cycles/word * 16 words/burst) + 1] = 392 cycles
If instead the channel were configured to transfer the same amount of data 32 bits at a time (the word size
is configured to 32 bits) the transfer would take:
8 bursts * [(3 cycles/word * 8 words/burst) + 1] = 200 cycles
602
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CPU and CLA Arbitration
www.ti.com
The DMA module consists of a 3-stage pipeline as shown in Figure 5-6 and Figure 5-7.
Figure 5-6. 3-Stage Pipeline DMA Transfer
Figure 5-7. 3-stage Pipeline With One Read Stall
5.6
CPU and CLA Arbitration
Typically, DMA activity is independent of CPU and CLA activity. However, when the DMA and CPU (or
CLA) try to access the same peripheral at the same time, an arbitration procedure is required to resolve
the conflict. All instances of the same peripheral type conflict with each other. For instance, CAN-A and
CAN-B conflict, as do the GS0 and GS2 RAMs. Different peripheral types can share a bus interface, which
creates further opportunities for conflicts. These bus interfaces are:
• Peripheral frame 1: ePWM, eCAP, eQEP, SDFM, CMPSS, DAC
• Peripheral frame 2: PMBus and SPI
Conflict Example: The CLA is accessing DAC-A while the DMA is simultaneously accessing DAC-B.
Conflict Example: The CPU is accessing an SPI FIFO while the DMA is simultaneously accessing a
PMBus register.
Non-conflict Example: The CPU is accessing a shared ePWM while the DMA is accessing an SPI.
The exception to all this is the ADC result registers, which are duplicated for each bus master. The CPU,
DMA, and CLA can all simultaneously read these registers with no stalls for any master.
A DMA transfer consists of four phases: send source address, read source data, send destination
address, and write destination data (see Section 5.5). Suppose CPU accesses a peripheral / memory
causing conflict in middle of a DMA transfer, CPU is stalled till the current DMA access is complete and
not until the completion of whole DMA transfer.
The following priority schemes are implemented for the various interfaces on the device.
• The fixed priority scheme for the peripheral frames is:
– CLA/DMA Write
– CLA/DMA Read
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
603
Channel Priority
•
•
www.ti.com
– CPU Write
– CPU Read
The priority scheme for GSx RAM accesses is round-robin.
All masters can access the ADC result registers simultaneously without delay.
NOTE: If the CPU is performing a read-modify-write operation and the DMA performs a write to the
same location, the DMA write may be lost if the operation occurs in between the CPU read
and the CPU write. Avoid mixing CPU writes with DMA writes to the same locations.
Arbitration within DMA channels is based on a round robin priority (or) Channel 1 high priority scheme
described in Section 5.7.
5.7
Channel Priority
Two priority schemes exist when determining channel priority: Round-robin mode and Channel 1 highpriority mode.
5.7.1 Round-Robin Mode
In this mode, all channels have equal priority and each enabled channel is serviced in round-robin fashion
as follows:
CH1 → CH2 → CH3 → CH4 → CH5 → CH6 → CH1 → CH2 → …
In the case above, after each channel has transferred a burst of words, the next channel is serviced. You
can specify the size of the burst for each channel. Once CH6 (or the last enabled channel) has been
serviced, and no other channels are pending, the round-robin state machine enters an idle state.
From the idle state, channel 1 (if enabled) is always serviced first. However, if the DMA is currently
processing another channel x, all other pending channels between x and the end of the round are serviced
before CH1. It is in this sense that all the channels are of equal priority. For instance, take an example
where CH1, CH4, and CH5 are enabled in round-robin mode and CH4 is currently being processed. Then
CH1 and CH5 both receive an interrupt trigger from their respective peripherals before CH4 completes.
CH1 and CH5 are now both pending. When CH4 completes its burst, CH5 will be serviced next. Only after
CH5 completes will CH1 be serviced. Upon completion of CH1, if there are no more channels pending, the
round-robin state machine will enter an idle state.
A
•
•
•
•
•
•
•
•
•
•
more complicated example is shown below:
Assume all channels are enabled, and the DMA is in an idle state,
Initially a trigger occurs on CH1, CH3, and CH5 on the same cycle,
When the CH1 burst transfer starts, requests from CH3 and CH5 are pending,
Before completion of the CH1 burst, the DMA receives a request from CH2. Now the pending requests
are from CH2, CH3, and CH5,
After completing the CH1 burst, CH2 will be serviced since it is next in the round-robin scheme after
CH1.
After the burst from CH2 is finished, the CH3 burst will be serviced, followed by CH5 burst.
Now while the CH5 burst is being serviced, the DMA receives a request from CH1, CH3, and CH6.
The burst from CH6 will start after the completion of the CH5 burst since it is the next channel after
CH5 in the round-robin scheme.
This will be followed by the CH1 burst and then the CH3 burst
After the CH3 burst finishes, assuming no more triggers have occurred, the round-robin state machine
will enter an idle state.
The round-robin state machine may be reset to the idle state via the DMACTRL[PRIORITYRESET] bit.
604
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Channel Priority
www.ti.com
5.7.2 Channel 1 High Priority Mode
In this mode, Channel 1 has high priority over all the other channels. Channel 2 – 6 have equal priority
and each enabled channel is serviced in round-robin fashion.
Higher Priority:
Lower priority:
CH1
CH2 → CH3 → CH4 → CH5 → CH6 → CH2 → …
Given an example where CH1, CH4 and CH5 are enabled in Channel 1 High Priority Mode and CH4 is
currently being processed. Then CH1 and CH5 both receive an interrupt trigger from their respective
peripherals before CH4 completes. CH1 and CH5 are now both pending. When the current CH4 word
transfer is completed, regardless of whether the DMA has completed the entire CH4 burst, CH4 execution
will be suspended and CH1 will be serviced. After the CH1 burst completes, CH4 will resume execution.
Upon completion of CH4, CH5 will be serviced. After CH5 completes, if there are no more channels
pending, the round-robin state machine will enter an idle state.
Typically Channel 1 would be used in this mode for the ADC, since its data rate is so high. However,
Channel 1 High Priority Mode may be used in conjunction with any peripheral.
NOTE: High-priority mode and ONESHOT mode may not be used at the same time on channel 1.
Other channels may use ONESHOT mode when channel 1 is in high-priority mode.
5.8
Overrun Detection Feature
The DMA contains overrun detection logic. When a peripheral event trigger is received by the DMA, the
PERINTFLG bit in the CONTROL register is set, pending the channel to the DMA state machine. When
the burst for that channel is started, the PERINTFLG is cleared. If however, between the time that the
PERINTFLG bit is set by an event trigger and cleared by the start of the burst, an additional event trigger
arrives, the second trigger will be lost. This condition will set the OVRFLG bit in the CONTROL register as
in Figure 5-8. If the overrun interrupt is enabled, the channel interrupt will be generated to the PIE module.
Figure 5-8. Overrun Detection Logic
DMA
channel interrupt
DMACHx interrupt generated
at beginning or end of transfer
PIE
CHx.MODE[CHINTE]
CHx.CONTROL[OVRFLG]
CHx.CONTROL[PERINTFLG]
PERx_INT
Latch
CHx.CONTROL[ERRCLR]
CHx.MODE[OVERINTE]
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
605
DMA Registers
5.9
www.ti.com
DMA Registers
This section describes the C28x Direct Memory Access Registers.
5.9.1 DMA Base Addresses
Table 5-3. DMA Base Address Table
Device Registers
DmaRegs
606
Direct Memory Access (DMA)
Register Name
Start Address
End Address
DMA_REGS
0x0000_1000
0x0000_11FF
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
5.9.2 DMA_REGS Registers
Table 5-4 lists the DMA_REGS registers. All register offset addresses not listed in Table 5-4 should be
considered as reserved locations and the register contents should not be modified.
Table 5-4. DMA_REGS Registers
Offset
Acronym
Register Name
Write Protection
0h
DMACTRL
DMA Control Register
EALLOW
Section
Go
1h
DEBUGCTRL
Debug Control Register
EALLOW
Go
4h
PRIORITYCTRL1
Priority Control 1 Register
EALLOW
Go
6h
PRIORITYSTAT
Priority Status Register
EALLOW
Go
Complex bit access types are encoded to fit into small table cells. Table 5-5 shows the codes that are
used for access types in this section.
Table 5-5. DMA_REGS Access Type Codes
Access Type
Code
Description
R
R
Read
R-0
R
-0
Read
Returns 0s
W
W
Write
W1S
W
1S
Write
1 to set
Read Type
Write Type
Reset or Default Value
-n
Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y
When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
607
DMA Registers
5.9.2.1
www.ti.com
DMACTRL Register (Offset = 0h) [reset = 0h]
DMACTRL is shown in Figure 5-9 and described in Table 5-6.
Return to the Summary Table.
DMA Control Register
Figure 5-9. DMACTRL Register
15
14
13
12
11
10
9
8
3
2
1
PRIORITYRES
ET
R-0/W1S-0h
0
HARDRESET
RESERVED
R-0h
7
6
5
4
RESERVED
R-0h
R-0/W1S-0h
Table 5-6. DMACTRL Register Field Descriptions
Bit
15-2
1
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
PRIORITYRESET
R-0/W1S
0h
The priority reset bit resets the round-robin state machine when a 1
is written. Service starts from the first enabled channel. Writes of 0
are ignored and this bit always reads back a 0.
When a 1 is written to this bit, any pending burst transfer completes
before resetting the channel priority machine. If CH1 is configured as
a high-priority channel, and this bit is
written to while CH1 is servicing a burst, both the CH1 burst and the
next pending low-priority burst are completed before the state
machine is reset.
If CH1 is high-priority, the state machine restarts from CH2 (or the
next highest enabled channel).
Reset type: SYSRSn
0
HARDRESET
R-0/W1S
0h
Writing a 1 to the hard reset bit resets the whole DMA and aborts
any current access (similar to applying a device reset). Writes of 0
are ignored and this bit always reads back a 0.
For a soft reset, a bit is provided for each channel to perform a
gentler reset. Refer to the channel control registers.
When writing to this bit, there is a one cycle delay before it takes
effect. Hence, a one-cycle delay (such as a NOP instruction) is
required in software before attempting to access any other DMA
register.
Reset type: SYSRSn
608
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
5.9.2.2
DEBUGCTRL Register (Offset = 1h) [reset = 0h]
DEBUGCTRL is shown in Figure 5-10 and described in Table 5-7.
Return to the Summary Table.
Debug Control Register
Figure 5-10. DEBUGCTRL Register
15
FREE
R/W-0h
14
13
12
7
6
5
4
11
RESERVED
R-0h
10
9
8
3
2
1
0
RESERVED
R-0h
Table 5-7. DEBUGCTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
FREE
R/W
0h
Emulation Control
This bit specifies the action when an emulation halt event occurs.
Reset type: SYSRSn
0h (R/W) = The DMA completes the current read-write operation,
then halts.
1h (R/W) = The DMA continues running during an emulation halt.
14-0
RESERVED
R
0h
Reserved
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
609
DMA Registers
5.9.2.3
www.ti.com
PRIORITYCTRL1 Register (Offset = 4h) [reset = 0h]
PRIORITYCTRL1 is shown in Figure 5-11 and described in Table 5-8.
Return to the Summary Table.
Priority Control 1 Register
Figure 5-11. PRIORITYCTRL1 Register
15
14
13
12
11
10
9
8
3
2
1
0
CH1PRIORITY
R/W-0h
RESERVED
R-0h
7
6
5
4
RESERVED
R-0h
Table 5-8. PRIORITYCTRL1 Register Field Descriptions
Bit
15-1
0
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
CH1PRIORITY
R/W
0h
DMA Channel 1 Priority
This bit selects whether CH1 has high priority or not. The priority can
only be changed when all channels are disabled. A priority reset
should be performed before restarting channels after changing
priority
Reset type: SYSRSn
0h (R/W) = CH1 has the same priority as the other channels
1h (R/W) = CH1 has a higher priority than the other channels
610
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
5.9.2.4
PRIORITYSTAT Register (Offset = 6h) [reset = 0h]
PRIORITYSTAT is shown in Figure 5-12 and described in Table 5-9.
Return to the Summary Table.
Priority Status Register
Figure 5-12. PRIORITYSTAT Register
15
14
13
12
11
10
9
8
3
RESERVED
R-0h
2
1
ACTIVESTS
R-0h
0
RESERVED
R-0h
7
RESERVED
R-0h
6
5
ACTIVESTS_SHADOW
R-0h
4
Table 5-9. PRIORITYSTAT Register Field Descriptions
Field
Type
Reset
Description
15-7
Bit
RESERVED
R
0h
Reserved
6-4
ACTIVESTS_SHADOW
R
0h
Active Channel Status Shadow
These bits are only meaningful when CH1 is in high-priority mode.
When CH1 is serviced, the ACTIVESTS bits are copied to the
shadow bits and indicate which channel was interrupted by CH1.
When CH1 service is completed, the shadow bits are copied back to
the ACTIVESTS bits. If this bit field is zero or the same as the
ACTIVESTS bit field, then no channel is pending due to a CH1
interrupt. When CH1 is not a higher priority channel, these bits
should be ignored.
Reset type: SYSRSn
0h (R/W) = No channel is active
1h (R/W) = CH 1
2h (R/W) = CH 2
3h (R/W) = CH 3
4h (R/W) = CH 4
5h (R/W) = CH 5
6h (R/W) = CH 6
7h (R/W) = Reserved
3
RESERVED
R
0h
Reserved
2-0
ACTIVESTS
R
0h
Active Channel Status
These bits indicate which channel (if any) is currently active or
performing a transfer.
Reset type: SYSRSn
0h (R/W) = No channel is active
1h (R/W) = CH 1
2h (R/W) = CH 2
3h (R/W) = CH 3
4h (R/W) = CH 4
5h (R/W) = CH 5
6h (R/W) = CH 6
7h (R/W) = Reserved
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
611
DMA Registers
www.ti.com
5.9.3 DMA_CH_REGS Registers
Table 5-10 lists the DMA_CH_REGS registers. All register offset addresses not listed in Table 5-10 should
be considered as reserved locations and the register contents should not be modified.
Table 5-10. DMA_CH_REGS Registers
Offset
Acronym
Register Name
Write Protection
0h
MODE
Mode Register
EALLOW
Section
Go
1h
CONTROL
Control Register
EALLOW
Go
2h
BURST_SIZE
Burst Size Register
EALLOW
Go
3h
BURST_COUNT
Burst Count Register
EALLOW
Go
4h
SRC_BURST_STEP
Source Burst Step Register
EALLOW
Go
5h
DST_BURST_STEP
Destination Burst Step Register
EALLOW
Go
6h
TRANSFER_SIZE
Transfer Size Register
EALLOW
Go
7h
TRANSFER_COUNT
Transfer Count Register
EALLOW
Go
8h
SRC_TRANSFER_STEP
Source Transfer Step Register
EALLOW
Go
9h
DST_TRANSFER_STEP
Destination Transfer Step Register
EALLOW
Go
Ah
SRC_WRAP_SIZE
Source Wrap Size Register
EALLOW
Go
Bh
SRC_WRAP_COUNT
Source Wrap Count Register
EALLOW
Go
Ch
SRC_WRAP_STEP
Source Wrap Step Register
EALLOW
Go
Dh
DST_WRAP_SIZE
Destination Wrap Size Register
EALLOW
Go
Eh
DST_WRAP_COUNT
Destination Wrap Count Register
EALLOW
Go
Fh
DST_WRAP_STEP
Destination Wrap Step Register
EALLOW
Go
10h
SRC_BEG_ADDR_SHADOW
Source Begin Address Shadow Register
EALLOW
Go
12h
SRC_ADDR_SHADOW
Source Address Shadow Register
EALLOW
Go
14h
SRC_BEG_ADDR_ACTIVE
Source Begin Address Active Register
EALLOW
Go
16h
SRC_ADDR_ACTIVE
Source Address Active Register
EALLOW
Go
18h
DST_BEG_ADDR_SHADOW
Destination Begin Address Shadow Register
EALLOW
Go
1Ah
DST_ADDR_SHADOW
Destination Address Shadow Register
EALLOW
Go
1Ch
DST_BEG_ADDR_ACTIVE
Destination Begin Address Active Register
EALLOW
Go
1Eh
DST_ADDR_ACTIVE
Destination Address Active Register
EALLOW
Go
Complex bit access types are encoded to fit into small table cells. Table 5-11 shows the codes that are
used for access types in this section.
Table 5-11. DMA_CH_REGS Access Type Codes
Access Type
Code
Description
R
R
Read
R-0
R
-0
Read
Returns 0s
W
W
Write
W1S
W
1S
Write
1 to set
Read Type
Write Type
Reset or Default Value
-n
Value after reset or the default
value
Register Array Variables
612
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
Table 5-11. DMA_CH_REGS Access Type
Codes (continued)
Access Type
Code
Description
i,j,k,l,m,n
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y
When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
613
DMA Registers
5.9.3.1
www.ti.com
MODE Register (Offset = 0h) [reset = 0h]
MODE is shown in Figure 5-13 and described in Table 5-12.
Return to the Summary Table.
Mode Register
Figure 5-13. MODE Register
15
CHINTE
R/W-0h
14
DATASIZE
R/W-0h
13
RESERVED
12
RESERVED
11
CONTINUOUS
R/W-0h
10
ONESHOT
R/W-0h
9
CHINTMODE
R/W-0h
8
PERINTE
R/W-0h
7
OVRINTE
R/W-0h
6
5
4
3
2
PERINTSEL
R/W-0h
1
0
RESERVED
R-0h
Table 5-12. MODE Register Field Descriptions
Bit
Field
Type
Reset
Description
15
CHINTE
R/W
0h
Channel Interrupt Enable Bit
This bit enables the DMA channel's CPU interrupt.
Reset type: SYSRSn
0h (R/W) = Interrupt disabled
1h (R/W) = Interrupt enabled
14
DATASIZE
R/W
0h
Data Size Mode Bit
This bit determines whether the DMA channel transfers 16 bits or 32
bits of data per read/write operation. Regardless of this setting, all
data lengths and offsets in other DMA registers refer to 16- bit
words. The pointer step increments must be configured to
accomodate 32-bit words.
Reset type: SYSRSn
0h (R/W) = 16-bit data transfer size
1h (R/W) = 32-bit data transfer size
13
RESERVED
R/W
0h
Reserved
12
RESERVED
R/W
0h
Reserved
11
CONTINUOUS
R/W
0h
Continuous Mode Bit
If this bit is set to 1, then the channel re-initializes when
TRANSFER_COUNT is zero and waits for the next event trigger.
Otherwise, the DMA stops and clears the RUNSTS bit.
Reset type: SYSRSn
10
ONESHOT
R/W
0h
One Shot Mode
If this bit is set to 1, each peripheral event trigger causes the channel
to perform an entire transfer. Otherwise, the channel only performs
one burst per trigger.
Reset type: SYSRSn
9
CHINTMODE
R/W
0h
Channel Interrupt Generation Mode
This bit specifies when the DMA channel generates a CPU interrupt
for a transfer.
Reset type: SYSRSn
0h (R/W) = Generate interrupt at beginning of new transfer
1h (R/W) = Generate interrupt at end of transfer.
614
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
Table 5-12. MODE Register Field Descriptions (continued)
Bit
8
Field
Type
Reset
Description
PERINTE
R/W
0h
Peripheral Event Trigger Enable
This bit enables peripheral event triggers on the DMA channel.
Reset type: SYSRSn
0h (R/W) = Peripheral event trigger disabled. Neither the selected
peripheral nor software can start a DMA burst.
1h (R/W) = Peripheral event trigger enabled.
7
OVRINTE
R/W
0h
Overflow Interrupt Enable
The bit determines whether the DMA module generates a CPU
interrupt when it detects an overflow event.
Reset type: SYSRSn
0h (R/W) = Overflow interrupt disabled
1h (R/W) = Overflow interrupt enabled
6-5
RESERVED
R
0h
Reserved
4-0
PERINTSEL
R/W
0h
Peripheral Event Trigger Source Select
These are legacy bits and should be set to the channel number. The
actual source selection is done via the DMACHSRCSELn registers,
which are part of the DMA_CLA_SRC_SEL_REGS group.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
615
DMA Registers
5.9.3.2
www.ti.com
CONTROL Register (Offset = 1h) [reset = 0h]
CONTROL is shown in Figure 5-14 and described in Table 5-13.
Return to the Summary Table.
Control Register
Figure 5-14. CONTROL Register
15
RESERVED
14
OVRFLG
13
RUNSTS
12
BURSTSTS
10
RESERVED
R-0h
11
TRANSFERST
S
R-0h
R-0h
R-0h
R-0h
7
ERRCLR
R-0/W1S-0h
6
RESERVED
5
RESERVED
4
PERINTCLR
R-0/W1S-0h
3
PERINTFRC
R-0/W1S-0h
2
SOFTRESET
R-0/W1S-0h
9
RESERVED
8
PERINTFLG
R-0h
1
HALT
R-0/W1S-0h
0
RUN
R-0/W1S-0h
Table 5-13. CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R
0h
Reserved
14
OVRFLG
R
0h
Overflow Flag
This bit indicates that a peripheral event trigger was received while
PERINTFLG was already set. It can be cleared by writing to the
ERRCLR bit.
Reset type: SYSRSn
0h (R/W) = No overflow detected
1h (R/W) = Overflow detected
13
RUNSTS
R
0h
Run Status Flag
This bit indicates that the DMA channel is ready to respond to
peripheral event triggers. This bit is set when a 1 is written to the
RUN bit. It is cleared when a transfer completes
(TRANSFER_COUNT = 0) and continuous mode is disabled, or
when the HARDRESET, SOFTRESET, or HALT bit is set.
Reset type: SYSRSn
0h (R/W) = The channel is disabled
1h (R/W) = The channel is enabled
12
BURSTSTS
R
0h
Burst Status Flag
This bit is set when a DMA burst begins. The BURST_COUNT is set
to the BURST_SIZE. This bit is cleared when BURST_COUNT
reaches zero, or when the HARDRESET or SOFTRESET bit is set.
Reset type: SYSRSn
0h (R/W) = No burst activity
1h (R/W) = The DMA is currently servicing or suspending a burst
transfer from this channel
11
TRANSFERSTS
R
0h
Transfer Status Flag
This bit is set when a DMA transfer begins. The address registers
are copied to the shadow set and the TRANSFER_COUNT is set to
the TRANSFER_SIZE. This bit is cleared when
TRANSFER_COUNT reaches zero, or when the HARDRESET or
SOFTRESET bit is set.
Reset type: SYSRSn
0h (R/W) = No transfer activity
1h (R/W) = The channel is currently in the middle of a transfer
regardless of whether a burst of data is actively being transferred
or not
616
10
RESERVED
R
0h
Reserved
9
RESERVED
R
0h
Reserved
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
Table 5-13. CONTROL Register Field Descriptions (continued)
Bit
8
Field
Type
Reset
Description
PERINTFLG
R
0h
Peripheral Event Trigger Flag
This bit indicates whether a peripheral event trigger has arrived. This
bit is automatically cleared when the first burst transfer begins.
Reset type: SYSRSn
0h (R/W) = Waiting for event trigger
1h (R/W) = Event trigger pending
7
ERRCLR
R-0/W1S
0h
Clear Error
Writing a 1 to this bit will clear the OVRFLG bit. This is normally
done when initializing the DMA module or if an overflow condition is
detected. If an overflow event occurs at the same time this bit is set,
the overrun has priority and the OVRFLG bit is set.
Reset type: SYSRSn
6
RESERVED
R-0/W1S
0h
Reserved
5
RESERVED
R-0/W1S
0h
Reserved
4
PERINTCLR
R-0/W1S
0h
Clear Peripheral Event Trigger
Writing a 1 to this bit clears PERINTFLG, which cancels a pending
event trigger. This is normally done when initializing the DMA
module. If an event trigger arrives at the same time this bit is set, the
trigger has priority and PERINTFLG is set.
Reset type: SYSRSn
3
PERINTFRC
R-0/W1S
0h
Force Peripheral Event Trigger
If the PERINTE bit of the MODE register is set, writing a 1 to this bit
sets PERINTFLG, which triggers a DMA burst. This bit can be used
to start a DMA transfer in software.
Reset type: SYSRSn
2
SOFTRESET
R-0/W1S
0h
Channel Soft Reset
Writing a 1 to this bit places the channel into its default state after
the current read/write access has completed:
RUNSTS = 0
TRANSFERSTS = 0
BURSTSTS = 0
BURST_COUNT = 0
TRANSFER_COUNT = 0
SRC_WRAP_COUNT = 0
DST_WRAP_COUNT = 0
When writing to this bit, there is a one cycle delay before it takes
effect. Hence, a one-cycle delay (such as a NOP instruction) is
required in software before attempting to access any other DMA
register.
Reset type: SYSRSn
1
HALT
R-0/W1S
0h
Halt Channel
Writing a 1 to this bit halts the DMA channel in its current state after
any ongoing read/write access has completed.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
617
DMA Registers
www.ti.com
Table 5-13. CONTROL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
RUN
R-0/W1S
0h
Run Channel
Writing a 1 to this bit enables the DMA channel and sets the
RUNSTS bit to 1. This bit is also used to resume after a channel
halt.
The RUN bit is typically used to start the DMA channel after
configuration. The channel will then wait for the first peripheral event
trigger (PERINTFLG == 1) to start a burst.
Reset type: SYSRSn
618
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
5.9.3.3
BURST_SIZE Register (Offset = 2h) [reset = 0h]
BURST_SIZE is shown in Figure 5-15 and described in Table 5-14.
Return to the Summary Table.
Burst Size Register
Figure 5-15. BURST_SIZE Register
15
14
13
12
11
10
9
8
3
2
BURSTSIZE
R/W-0h
1
0
RESERVED
R-0h
7
6
RESERVED
R-0h
5
4
Table 5-14. BURST_SIZE Register Field Descriptions
Field
Type
Reset
Description
15-5
Bit
RESERVED
R
0h
Reserved
4-0
BURSTSIZE
R/W
0h
These bits specify the burst size in 16-bit words. The actual size is
equal to BURSTSIZE + 1.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
619
DMA Registers
5.9.3.4
www.ti.com
BURST_COUNT Register (Offset = 3h) [reset = 0h]
BURST_COUNT is shown in Figure 5-16 and described in Table 5-15.
Return to the Summary Table.
Burst Count Register
Figure 5-16. BURST_COUNT Register
15
14
13
12
11
10
9
8
3
2
BURSTCOUNT
R-0h
1
0
RESERVED
R-0h
7
6
RESERVED
R-0h
5
4
Table 5-15. BURST_COUNT Register Field Descriptions
Bit
620
Field
Type
Reset
Description
15-5
RESERVED
R
0h
Reserved
4-0
BURSTCOUNT
R
0h
These bits indicate the number of words left in the current burst.
Reset type: SYSRSn
0h (R/W) = 0 word left in a burst
1h (R/W) = 1 word left in a burst
2h (R/W) = 2 word left in a burst
3h (R/W) = 3 word left in a burst
4h (R/W) = 4 word left in a burst
5h (R/W) = 5 word left in a burst
6h (R/W) = 6 word left in a burst
7h (R/W) = 7 word left in a burst
8h (R/W) = 8 word left in a burst
9h (R/W) = 9 word left in a burst
Ah (R/W) = 10 word left in a burst
Bh (R/W) = 11 word left in a burst
Ch (R/W) = 12 word left in a burst
Dh (R/W) = 13 word left in a burst
Eh (R/W) = 14 word left in a burst
Fh (R/W) = 15 word left in a burst
10h (R/W) = 16 word left in a burst
11h (R/W) = 17 word left in a burst
12h (R/W) = 18 word left in a burst
13h (R/W) = 19 word left in a burst
14h (R/W) = 20 word left in a burst
15h (R/W) = 21 word left in a burst
16h (R/W) = 22 word left in a burst
17h (R/W) = 23 word left in a burst
18h (R/W) = 24 word left in a burst
19h (R/W) = 25 word left in a burst
1Ah (R/W) = 26 word left in a burst
1Bh (R/W) = 27 word left in a burst
1Ch (R/W) = 28 word left in a burst
1Dh (R/W) = 29 word left in a burst
1Eh (R/W) = 30 word left in a burst
1Fh (R/W) = 31 word left in a burst
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
5.9.3.5
SRC_BURST_STEP Register (Offset = 4h) [reset = 0h]
SRC_BURST_STEP is shown in Figure 5-17 and described in Table 5-16.
Return to the Summary Table.
Source Burst Step Register
Figure 5-17. SRC_BURST_STEP Register
15
14
13
12
11
SRCBURSTSTEP
R/W-0h
10
9
8
7
6
5
4
3
SRCBURSTSTEP
R/W-0h
2
1
0
Table 5-16. SRC_BURST_STEP Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
SRCBURSTSTEP
R/W
0h
These bits specify the change in the source address after each word
in a burst. The size must be a 16-bit two's complement value
between -4096 and 4095 (inclusive). This value is added to the
source address after each read/write operation in a burst.
Reset type: SYSRSn
0h (R/W) = No address change
1h (R/W) = Add 1 to the address
2h (R/W) = Add 2 to the address
FFEh (R/W) = Add 4094 to the address
FFFh (R/W) = Add 4095 to the address
F000h (R/W) = Subtract 4096 from the address
F001h (R/W) = Subtract 4095 from the address
FFFEh (R/W) = Subtract 2 from the address
FFFFh (R/W) = Subtract 1 from the address
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
621
DMA Registers
5.9.3.6
www.ti.com
DST_BURST_STEP Register (Offset = 5h) [reset = 0h]
DST_BURST_STEP is shown in Figure 5-18 and described in Table 5-17.
Return to the Summary Table.
Destination Burst Step Register
Figure 5-18. DST_BURST_STEP Register
15
14
13
12
11
DSTBURSTSTEP
R/W-0h
10
9
8
7
6
5
4
3
DSTBURSTSTEP
R/W-0h
2
1
0
Table 5-17. DST_BURST_STEP Register Field Descriptions
Bit
15-0
622
Field
Type
Reset
Description
DSTBURSTSTEP
R/W
0h
These bits specify the change in the destination address after each
word in a burst. The size must be a 16-bit two's complement value
between -4096 and 4095 (inclusive). This value is added to the
destination address after each read/write operation in a burst.
Reset type: SYSRSn
0h (R/W) = No address change
1h (R/W) = Add 1 to the address
2h (R/W) = Add 2 to the address
FFEh (R/W) = Add 4094 to the address
FFFh (R/W) = Add 4095 to the address
F000h (R/W) = Subtract 4096 from the address
F001h (R/W) = Subtract 4095 from the address
FFFEh (R/W) = Subtract 2 from the address
FFFFh (R/W) = Subtract 1 from the address
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
5.9.3.7
TRANSFER_SIZE Register (Offset = 6h) [reset = 0h]
TRANSFER_SIZE is shown in Figure 5-19 and described in Table 5-18.
Return to the Summary Table.
Transfer Size Register
Figure 5-19. TRANSFER_SIZE Register
15
14
13
12
11
TRANSFERSIZE
R/W-0h
10
9
8
7
6
5
4
3
TRANSFERSIZE
R/W-0h
2
1
0
Table 5-18. TRANSFER_SIZE Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
TRANSFERSIZE
R/W
0h
These bits specify the transfer size in bursts. The actual size is equal
to TRANSFERSIZE + 1.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
623
DMA Registers
5.9.3.8
www.ti.com
TRANSFER_COUNT Register (Offset = 7h) [reset = 0h]
TRANSFER_COUNT is shown in Figure 5-20 and described in Table 5-19.
Return to the Summary Table.
Transfer Count Register
Figure 5-20. TRANSFER_COUNT Register
15
14
13
12
11
TRANSFERCOUNT
R/W-0h
10
9
8
7
6
5
4
3
TRANSFERCOUNT
R/W-0h
2
1
0
Table 5-19. TRANSFER_COUNT Register Field Descriptions
Bit
15-0
624
Field
Type
Reset
Description
TRANSFERCOUNT
R/W
0h
These bits indicate the number of bursts left in the current transfer.
Reset type: SYSRSn
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
5.9.3.9
SRC_TRANSFER_STEP Register (Offset = 8h) [reset = 0h]
SRC_TRANSFER_STEP is shown in Figure 5-21 and described in Table 5-20.
Return to the Summary Table.
Source Transfer Step Register
Figure 5-21. SRC_TRANSFER_STEP Register
15
14
13
12
11
SRCTRANSFERSTEP
R/W-0h
10
9
8
7
6
5
4
3
SRCTRANSFERSTEP
R/W-0h
2
1
0
Table 5-20. SRC_TRANSFER_STEP Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
SRCTRANSFERSTEP
R/W
0h
These bits specify the change in the source address after a burst
completes. The size must be a 16-bit two's complement value
between -4096 and 4095 (inclusive). This value is added to the
source address after each burst completes.
Reset type: SYSRSn
0h (R/W) = No address change
1h (R/W) = Add 1 to the address
2h (R/W) = Add 2 to the address
FFEh (R/W) = Add 4094 to the address
FFFh (R/W) = Add 4095 to the address
F000h (R/W) = Subtract 4096 from the address
F001h (R/W) = Subtract 4095 from the address
FFFEh (R/W) = Subtract 2 from the address
FFFFh (R/W) = Subtract 1 from the address
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
625
DMA Registers
www.ti.com
5.9.3.10 DST_TRANSFER_STEP Register (Offset = 9h) [reset = 0h]
DST_TRANSFER_STEP is shown in Figure 5-22 and described in Table 5-21.
Return to the Summary Table.
Destination Transfer Step Register
Figure 5-22. DST_TRANSFER_STEP Register
15
14
13
12
11
DSTTRANSFERSTEP
R/W-0h
10
9
8
7
6
5
4
3
DSTTRANSFERSTEP
R/W-0h
2
1
0
Table 5-21. DST_TRANSFER_STEP Register Field Descriptions
Bit
15-0
626
Field
Type
Reset
Description
DSTTRANSFERSTEP
R/W
0h
These bits specify the change in the destination address after a
burst completes. The size must be a 16-bit two's complement value
between -4096 and 4095 (inclusive). This value is added to the
destination address after each burst completes.
Reset type: SYSRSn
0h (R/W) = No address change
1h (R/W) = Add 1 to the address
2h (R/W) = Add 2 to the address
FFEh (R/W) = Add 4094 to the address
FFFh (R/W) = Add 4095 to the address
F000h (R/W) = Subtract 4096 from the address
F001h (R/W) = Subtract 4095 from the address
FFFEh (R/W) = Subtract 2 from the address
FFFFh (R/W) = Subtract 1 from the address
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
5.9.3.11 SRC_WRAP_SIZE Register (Offset = Ah) [reset = 0h]
SRC_WRAP_SIZE is shown in Figure 5-23 and described in Table 5-22.
Return to the Summary Table.
Source Wrap Size Register
Figure 5-23. SRC_WRAP_SIZE Register
15
14
13
12
11
10
9
8
3
2
1
0
WRAPSIZE
R/W-0h
7
6
5
4
WRAPSIZE
R/W-0h
Table 5-22. SRC_WRAP_SIZE Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
WRAPSIZE
R/W
0h
These bits specify the number of bursts to transfer before the source
address wraps around to the beginning address. The actual number
is equal to WRAPSIZE + 1. To disable the wrapping function, set
WRAPSIZE to a value larger than TRANSFERSIZE.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
627
DMA Registers
www.ti.com
5.9.3.12 SRC_WRAP_COUNT Register (Offset = Bh) [reset = 0h]
SRC_WRAP_COUNT is shown in Figure 5-24 and described in Table 5-23.
Return to the Summary Table.
Source Wrap Count Register
Figure 5-24. SRC_WRAP_COUNT Register
15
14
13
12
11
10
9
8
3
2
1
0
WRAPSIZE
R/W-0h
7
6
5
4
WRAPSIZE
R/W-0h
Table 5-23. SRC_WRAP_COUNT Register Field Descriptions
Bit
15-0
628
Field
Type
Reset
Description
WRAPSIZE
R/W
0h
These bits indicate the number of bursts left before wrapping the
source address.
Reset type: SYSRSn
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
5.9.3.13 SRC_WRAP_STEP Register (Offset = Ch) [reset = 0h]
SRC_WRAP_STEP is shown in Figure 5-25 and described in Table 5-24.
Return to the Summary Table.
Source Wrap Step Register
Figure 5-25. SRC_WRAP_STEP Register
15
14
13
12
11
10
9
8
3
2
1
0
WRAPSTEP
R/W-0h
7
6
5
4
WRAPSTEP
R/W-0h
Table 5-24. SRC_WRAP_STEP Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
WRAPSTEP
R/W
0h
These bits specify the change in the source beginning address when
the wrap counter reaches zero. The size must be a 16-bit two's
complement value between -4096 and 4095 (inclusive). This value is
added to the source address when wrapping occurs.
Reset type: SYSRSn
0h (R/W) = No address change
1h (R/W) = Add 1 to the address
2h (R/W) = Add 2 to the address
FFEh (R/W) = Add 4094 to the address
FFFh (R/W) = Add 4095 to the address
F000h (R/W) = Subtract 4096 from the address
F001h (R/W) = Subtract 4095 from the address
FFFEh (R/W) = Subtract 2 from the address
FFFFh (R/W) = Subtract 1 from the address
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
629
DMA Registers
www.ti.com
5.9.3.14 DST_WRAP_SIZE Register (Offset = Dh) [reset = 0h]
DST_WRAP_SIZE is shown in Figure 5-26 and described in Table 5-25.
Return to the Summary Table.
Destination Wrap Size Register
Figure 5-26. DST_WRAP_SIZE Register
15
14
13
12
11
10
9
8
3
2
1
0
WRAPSIZE
R/W-0h
7
6
5
4
WRAPSIZE
R/W-0h
Table 5-25. DST_WRAP_SIZE Register Field Descriptions
Bit
15-0
630
Field
Type
Reset
Description
WRAPSIZE
R/W
0h
These bits specify the number of bursts to transfer before the
destination address wraps around to the beginning address. The
actual number is equal to WRAPSIZE + 1. To disable the wrapping
function, set WRAPSIZE to a value larger than TRANSFERSIZE.
Reset type: SYSRSn
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
5.9.3.15 DST_WRAP_COUNT Register (Offset = Eh) [reset = 0h]
DST_WRAP_COUNT is shown in Figure 5-27 and described in Table 5-26.
Return to the Summary Table.
Destination Wrap Count Register
Figure 5-27. DST_WRAP_COUNT Register
15
14
13
12
11
10
9
8
3
2
1
0
WRAPSIZE
R/W-0h
7
6
5
4
WRAPSIZE
R/W-0h
Table 5-26. DST_WRAP_COUNT Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
WRAPSIZE
R/W
0h
These bits indicate the number of bursts left before wrapping the
destination address.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
631
DMA Registers
www.ti.com
5.9.3.16 DST_WRAP_STEP Register (Offset = Fh) [reset = 0h]
DST_WRAP_STEP is shown in Figure 5-28 and described in Table 5-27.
Return to the Summary Table.
Destination Wrap Step Register
Figure 5-28. DST_WRAP_STEP Register
15
14
13
12
11
10
9
8
3
2
1
0
WRAPSTEP
R/W-0h
7
6
5
4
WRAPSTEP
R/W-0h
Table 5-27. DST_WRAP_STEP Register Field Descriptions
Bit
15-0
632
Field
Type
Reset
Description
WRAPSTEP
R/W
0h
These bits specify the change in the destination beginning address
when the wrap counter reaches zero. The size must be a 16-bit two's
complement value between -4096 and 4095 (inclusive). This value is
added to the destination address when wrapping occurs.
Reset type: SYSRSn
0h (R/W) = No address change
1h (R/W) = Add 1 to the address
2h (R/W) = Add 2 to the address
FFEh (R/W) = Add 4094 to the address
FFFh (R/W) = Add 4095 to the address
F000h (R/W) = Subtract 4096 from the address
F001h (R/W) = Subtract 4095 from the address
FFFEh (R/W) = Subtract 2 from the address
FFFFh (R/W) = Subtract 1 from the address
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
5.9.3.17 SRC_BEG_ADDR_SHADOW Register (Offset = 10h) [reset = 0h]
SRC_BEG_ADDR_SHADOW is shown in Figure 5-29 and described in Table 5-28.
Return to the Summary Table.
Source Begin Address Shadow Register
Figure 5-29. SRC_BEG_ADDR_SHADOW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BEGADDR
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 5-28. SRC_BEG_ADDR_SHADOW Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
BEGADDR
R/W
0h
Shadow Source Beginning Address
At the start of a transfer, the value in this register is loaded into the
SRC_BEG_ADDR_ACTIVE register and used as the beginning
value for the source address. This register can be safely updated
during a transfer.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
633
DMA Registers
www.ti.com
5.9.3.18 SRC_ADDR_SHADOW Register (Offset = 12h) [reset = 0h]
SRC_ADDR_SHADOW is shown in Figure 5-30 and described in Table 5-29.
Return to the Summary Table.
Source Address Shadow Register
Figure 5-30. SRC_ADDR_SHADOW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 5-29. SRC_ADDR_SHADOW Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
ADDR
R/W
0h
Shadow Source Address
At the start of a transfer, the value in this register is loaded into the
SRC_ADDR_ACTIVE register and used as the value of the source
address. This register can be safely updated during a transfer.
Reset type: SYSRSn
634
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
5.9.3.19 SRC_BEG_ADDR_ACTIVE Register (Offset = 14h) [reset = 0h]
SRC_BEG_ADDR_ACTIVE is shown in Figure 5-31 and described in Table 5-30.
Return to the Summary Table.
Source Begin Address Active Register
Figure 5-31. SRC_BEG_ADDR_ACTIVE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BEGADDR
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 5-30. SRC_BEG_ADDR_ACTIVE Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
BEGADDR
R/W
0h
Active Source Beginning Address
If a transfer is ongoing, this register holds the current beginning
value for the source address. This address may be updated after
wrapping.
When a transfer starts, this register is loaded with the shadow
address from the SRC_BEG_ADDR_SHADOW register.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
635
DMA Registers
www.ti.com
5.9.3.20 SRC_ADDR_ACTIVE Register (Offset = 16h) [reset = 0h]
SRC_ADDR_ACTIVE is shown in Figure 5-32 and described in Table 5-31.
Return to the Summary Table.
Source Address Active Register
Figure 5-32. SRC_ADDR_ACTIVE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 5-31. SRC_ADDR_ACTIVE Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
ADDR
R/W
0h
Active Source Address
If a transfer is ongoing, this register holds the current value of the
source address. This address may change after a write, a burst, or
wrapping.
Reset type: SYSRSn
636
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
5.9.3.21 DST_BEG_ADDR_SHADOW Register (Offset = 18h) [reset = 0h]
DST_BEG_ADDR_SHADOW is shown in Figure 5-33 and described in Table 5-32.
Return to the Summary Table.
Destination Begin Address Shadow Register
Figure 5-33. DST_BEG_ADDR_SHADOW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BEGADDR
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 5-32. DST_BEG_ADDR_SHADOW Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
BEGADDR
R/W
0h
Shadow Destination Beginning Address
At the start of a transfer, the value in this register is loaded into the
DST_BEG_ADDR_ACTIVE register and used as the beginning value
for the destination address. This register can be safely updated
during a transfer.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
637
DMA Registers
www.ti.com
5.9.3.22 DST_ADDR_SHADOW Register (Offset = 1Ah) [reset = 0h]
DST_ADDR_SHADOW is shown in Figure 5-34 and described in Table 5-33.
Return to the Summary Table.
Destination Address Shadow Register
Figure 5-34. DST_ADDR_SHADOW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 5-33. DST_ADDR_SHADOW Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
ADDR
R/W
0h
Shadow Destination Address
At the start of a transfer, the value in this register is loaded into the
DST_ADDR_ACTIVE register and used as the value of the
destination address. This register can be safely updated during a
transfer.
Reset type: SYSRSn
638
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
5.9.3.23 DST_BEG_ADDR_ACTIVE Register (Offset = 1Ch) [reset = 0h]
DST_BEG_ADDR_ACTIVE is shown in Figure 5-35 and described in Table 5-34.
Return to the Summary Table.
Destination Begin Address Active Register
Figure 5-35. DST_BEG_ADDR_ACTIVE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BEGADDR
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 5-34. DST_BEG_ADDR_ACTIVE Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
BEGADDR
R/W
0h
Active Destination Beginning Address
If a transfer is ongoing, this register holds the current destination
value for the source address. This address may be updated after
wrapping.
When a transfer starts, this register is loaded with the shadow
address from the DST_BEG_ADDR_SHADOW register.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
639
DMA Registers
www.ti.com
5.9.3.24 DST_ADDR_ACTIVE Register (Offset = 1Eh) [reset = 0h]
DST_ADDR_ACTIVE is shown in Figure 5-36 and described in Table 5-35.
Return to the Summary Table.
Destination Address Active Register
Figure 5-36. DST_ADDR_ACTIVE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 5-35. DST_ADDR_ACTIVE Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
ADDR
R/W
0h
Active Destination Address
If a transfer is ongoing, this register holds the current value of the
destination address. This address may change after a write, a burst,
or wrapping.
Reset type: SYSRSn
640
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
DMA Registers
www.ti.com
5.9.4 Register to Driverlib Function Mapping
Table 5-36. DMA Registers to Driverlib Functions
File
Driverlib Function
CTRL
dma.h
DMA_initController
DEBUGCTRL
dma.h
DMA_setEmulationMode
PRIORITYCTRL1
dma.h
DMA_setPriorityMode
MODE
dma.c
DMA_configMode
dma.h
DMA_enableTrigger
dma.h
DMA_disableTrigger
dma.h
DMA_enableInterrupt
dma.h
DMA_disableInterrupt
dma.h
DMA_enableOverrunInterrupt
dma.h
DMA_disableOverrunInterrupt
dma.h
DMA_setInterruptMode
CONTROL
dma.h
DMA_forceTrigger
dma.h
DMA_clearTriggerFlag
dma.h
DMA_getTriggerFlagStatus
dma.h
DMA_startChannel
dma.h
DMA_stopChannel
dma.h
DMA_clearErrorFlag
BURST_SIZE
dma.c
DMA_configBurst
SRC_BURST_STEP
dma.c
DMA_configBurst
DST_BURST_STEP
dma.c
DMA_configBurst
TRANSFER_SIZE
dma.c
DMA_configTransfer
SRC_TRANSFER_STEP
dma.c
DMA_configTransfer
DST_TRANSFER_STEP
dma.c
DMA_configTransfer
SRC_WRAP_SIZE
dma.c
DMA_configWrap
SRC_WRAP_STEP
dma.c
DMA_configWrap
DST_WRAP_SIZE
dma.c
DMA_configWrap
DST_WRAP_STEP
dma.c
DMA_configWrap
SRC_BEG_ADDR_SHADOW
dma.c
DMA_configAddresses
dma.h
DMA_configSourceAddress
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Direct Memory Access (DMA) 641
DMA Registers
www.ti.com
Table 5-36. DMA Registers to Driverlib Functions (continued)
File
Driverlib Function
SRC_ADDR_SHADOW
dma.c
DMA_configAddresses
dma.h
DMA_configSourceAddress
DST_BEG_ADDR_SHADOW
dma.c
DMA_configAddresses
dma.h
DMA_configDestAddress
DST_ADDR_SHADOW
642
dma.c
DMA_configAddresses
dma.h
DMA_configDestAddress
Direct Memory Access (DMA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Chapter 6
SPRUHM9F – October 2014 – Revised September 2019
Control Law Accelerator (CLA)
The Control Law Accelerator (CLA) Type-1 is an independent, fully-programmable, 32-bit floating-point
math processor that brings concurrent control-loop execution to the C28x family. The low interrupt latency
of the CLA allows it to read ADC samples "just-in-time." This significantly reduces the ADC sample to
output delay to enable faster system response and higher MHz control loops. By using the CLA to service
time-critical control loops, the main CPU is free to perform other system tasks such as communications
and diagnostics. This chapter provides an overview of the architectural structure and components of the
control law accelerator.
Topic
...........................................................................................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Introduction .....................................................................................................
Features ..........................................................................................................
CLA Interface ...................................................................................................
CLA and CPU Arbitration ...................................................................................
CLA Configuration and Debug ...........................................................................
Pipeline ...........................................................................................................
Instruction Set..................................................................................................
CLA Registers ..................................................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
Page
644
644
646
650
652
656
661
776
643
Introduction
6.1
www.ti.com
Introduction
The Control Law Accelerator extends the capabilities of the C28x CPU by adding parallel processing.
Time-critical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the
CLA enables faster system response and higher frequency control loops. Utilizing the CLA for time-critical
tasks frees up the main CPU to perform other system and communication functions concurrently.
6.2
Features
The following is a list of major features of the CLA:
• C compilers are available for CLA software development.
• Clocked at the same rate as the main CPU (SYSCLKOUT).
• An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
• Program Address Bus (PAB) and Program Data Bus (PDB)
• Data Read Address Bus (DRAB), Data Read Data Bus (DRDB), Data Write Address Bus
(DWAB), and Data Write Data Bus (DWDB)
– Independent eight stage pipeline.
– 16-bit program counter (MPC)
– Four 32-bit result registers (MR0-MR3)
– Two 16-bit auxiliary registers (MAR0, MAR1)
– Status register (MSTF)
• Instruction set includes:
– IEEE single-precision (32-bit) floating point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions.
– Conditional branch and call
– Data load/store operations
• The CLA program code can consist of up to eight tasks or interrupt service routines
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the configurable CLA program memory space.
– One task is serviced at a time until its completion. There is no nesting of tasks.
– Upon task completion a task-specific interrupt is flagged within the PIE.
– When a task finishes the next highest-priority pending task is automatically started.
• Task trigger mechanisms:
– C28x CPU via the IACK instruction
– Task1 to Task8: up to 256 possible trigger sources from peripherals connected to the shared bus
on which the CLA assumes secondary ownership.
• Memory and Shared Peripherals:
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
– The CLA, on reset, is the secondary master for all peripherals which can have either the CLA or
DMA as their secondary master.
644
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Features
www.ti.com
Figure 6-1. CLA (Type 1) Block Diagram
CLA Control
Register Set
From
Shared
Peripherals
MPERINT1
to
MPERINT8
SYSCLK
CLA Clock Enable
SYSRSn
MIFR(16)
MIOVF(16)
MICLR(16)
MICLROVF(16)
MIFRC(16)
MIER(16)
MIRUN(16)
MVECT1(16)
MVECT2(16)
MVECT3(16)
MVECT4(16)
MVECT5(16)
MVECT6(16)
MVECT7(16)
MVECT8(16)
CLA_INT1
to
CLA_INT8
INT11
INT12
PIE
C28x
CPU
LVF
LUF
CPU Read/Write Data Bus
CLA Program Bus
CLA Program
Memory (LSx)
MCTL(16)
MPC(16)
MSTF(32)
MR0(32)
MR1(32)
MR2(32)
MR3(32)
MAR0(16)
MAR1(16)
CLA Data Bus
CLA Execution
Register Set
CLA Data
Memory (LSx)
CPU Data Bus
LSxMSEL[MSEL_LSx]
LSxCLAPGM[CLAPGM_LSx]
CLA Message
RAMs
Shared
Peripherals
MEALLOW
CPU Read Data Bus
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
645
CLA Interface
6.3
www.ti.com
CLA Interface
This chapter describes how the C28x main CPU can interface to the CLA and vice versa.
6.3.1 CLA Memory
The CLA can access three types of memory: program, data and message RAMs. The behavior and
arbitration for each type of memory is described in detail below. The CLA RAMs are protected by the
DCSM module. Refer to the DCSM section of this manual for more details on the security scheme.
• CLA Program Memory
The CLA program can be loaded any of the local shared memories (LSxRAM). At reset, all memory
blocks are mapped to the CPU. While mapped to the CPU space, the CPU can copy the CLA program
code into the memory. During debug, the memory can also be loaded directly by Code Composer
Studio™.
Once the memory is initialized with CLA code, the CPU maps it to the CLA program space by:
1. Assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s
MemCfgRegs.LSxMSEL[MSEL_LSx] bit.
2. Specifying the memory block as a code block for the CLA by writing a 1 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit.
When a memory block is configured as CLA program memory, debug accesses are allowed only on
cycles where the CLA is not fetching a new instruction. A detailed explanation of the memory
configurations and access arbitration (CPU, CLA, and DEBUG) process can be found in Section 3.11.
All CLA program fetches are performed as 32-bit read operations and all opcodes must be aligned to
an even address. Since all CLA opcodes are 32-bits, this alignment occurs naturally.
• CLA Data Memory
Any of the device’s LSxRAMs can serve as data memory blocks to the CLA. At reset, all blocks are
mapped to the CPU memory space, whereby the CPU can initialize the memory with data tables,
coefficients, and so on, for the CLA to use.
Once the memory is initialized with CLA data, the CPU maps it to the CLA data space by:
1. Assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s
MemCfgRegs.LSxMSEL[MSEL_LSx] bit.
2. Specifying the memory block as a data block for the CLA by writing a 0 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit. The value of this bit at reset is 0.
When a memory block is configured as CLA data memory, CLA read and write accesses are arbitrated
along with CPU accesses. The user has the option of turning on CPU fetch or write protection to the
memory by writing to the appropriate bits of the MemCfgRegs.LSxACCPROTx registers. A detailed
explanation of the memory configurations and access arbitration (CPU, CLA, and DEBUG) process
can be found in Section 3.11.
• CLA Shared Message RAMs
There are two memory blocks for data sharing and communication between the CLA and the CPU.
The message RAMs are always mapped to both CPU and CLA memory spaces, and only data access
is allowed; no program fetches can be performed.
– CLA to CPU Message RAM
The CLA can use this block to pass data to the CPU. This block is both readable and writable by
the CLA. This block is also readable by the CPU but writes by the CPU are ignored.
– CPU to CLA Message RAM
The CPU can use this block to pass data and messages to the CLA. This message RAM is both
readable and writable by the CPU. The CLA can perform reads but writes by the CLA are ignored.
646
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CLA Interface
www.ti.com
6.3.2 CLA Memory Bus
The CLA has dedicated bus architecture similar to that of the C28x CPU where there are separate
program read, data read, and data write buses. Thus, there can be simultaneous instruction fetch, data
read, and data write in a single cycle. Like the C28x CPU, the CLA expects memory logic to align any 32bit read or write to an even address. If the address-generation logic generates an odd address, the CLA
will begin reading or writing at the previous even address. This alignment does not affect the address
values generated by the address-generation logic.
• CLA Program Bus
The CLA program bus has an access range of 32K 32-bit instructions. Since all CLA instructions are
32 bits, this bus always fetches 32 bits at a time and the opcodes must be even-word aligned. The
amount of program space available for the CLA is limited to the number of available LSxRAM blocks.
This number is device-dependent and will be described in the device-specific data manual.
• CLA Data Read Bus
The CLA data read bus has a 64K x 16 address range. The bus can perform 16 or 32-bit reads and
will automatically stall if there are memory access conflicts. The data read bus has access to both the
message RAMs, CLA data memory, and the shared peripherals.
• CLA Data Write Bus
The CLA data write bus has a 64K x 16 address range. This bus can perform 16 or 32-bit writes. The
bus will automatically stall if there are memory access conflicts. The data write bus has access to the
CLA to CPU message RAM, CLA data memory, and the shared peripherals.
6.3.3 Shared Peripherals and EALLOW Protection
For a given CPU subsystem, the CLA and DMA share secondary access to some peripherals. The
secondary ownership of the bus is determined by the CpuSysRegs.SECMSEL[VBUS32_x] bit. If it is set to
0, the CLA is the secondary owner. If it is set to 1, the DMA is the secondary owner. By default, at reset,
the CLA is given the secondary ownership of the bus and, therefore, can access all the peripherals
connected to it.
Note: The CLA read access time to the bus is 2-wait states while write access is 0-wait.
Refer to the device data manual for the list of peripherals connected to the bus.
Several peripheral control registers are protected from spurious 28x CPU writes by the EALLOW
protection mechanism. These same registers are also protected from spurious CLA writes. The EALLOW
bit in the CPU status register 1 (ST1) indicates the state of protection for the CPU. Likewise the
MEALLOW bit in the CLA status register (MSTF) indicates the state of write protection for the CLA. The
MEALLOW CLA instruction enables write access by the CLA to EALLOW protected registers. Likewise the
MEDIS CLA instruction will disable write access. This way the CLA can enable/disable write access
independent of the CPU.
The ADC offers the option to generate an early interrupt pulse at the start of a sample conversion. If this
option is used to start an ADC-triggered CLA task, the user may use the intervening cycles, until the
completion of the conversion, to perform preliminary calculations or loads and stores before finally reading
the ADC value. The CLA pipeline activity for this scenario is shown in Section 6.6.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
647
CLA Interface
www.ti.com
6.3.4 CLA Tasks and Interrupt Vectors
The CLA program code is divided up into tasks or interrupt service routines. Tasks do not have a fixed
starting location or length. The CLA program memory can be divided up as desired. The CLA uses the
contents of the interrupt vectors (MVECT1 to MVECT8) to determine where a task begins; tasks are
terminated by the MSTOP instruction.
The CLA supports eight tasks. Task 1 has the highest priority and task 8 has the lowest priority.
A task can be requested by a peripheral interrupt or by software:
• Peripheral interrupt trigger
Each task can be triggered by software-selectable interrupt sources. The trigger for each task is
defined by writing an appropriate value to the DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx] bit
field. Each option specifies an interrupt source from a specific peripheral on the shared bus. The
peripheral interrupt triggers are listed in Table 6-1.
Table 6-1. Configuration Options
Select Value (8-bit)
CLA Trigger Source
0
Software Trigger
1
ADCAINT1
2
ADCAINT2
3
ADCAINT3
4
ADCAINT4
648 Control Law Accelerator (CLA)
5
ADCAEVT
6
ADCBINT1
7
ADCBINT2
8
ADCBINT3
9
ADCBINT4
10
ADCBEVT
11-15
Reserved
16
ADCDINT1
17
ADCDINT2
18
ADCDINT3
19
ADCDINT4
20
ADCDEVT
28:21
Reserved
29
XINT1
30
XINT2
31
XINT3
32
XINT4
33
XINT5
34
Reserved
35
Reserved
36
EPWM1INT
37
EPWM2INT
38
EPWM3INT
39
EPWM4INT
40
EPWM5INT
41
EPWM6INT
42
EPWM7INT
43
EPWM8INT
44
EPWM9INT
45
EPWM10INT
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CLA Interface
www.ti.com
Table 6-1. Configuration Options (continued)
•
Select Value (8-bit)
CLA Trigger Source
46
EPWM11NT
47
EPWM12INT
67:48
Reserved
68
TINT0
69
TINT1
70
TINT2
71
MXINTA
72
MRINTA
73
MXINTB
74
MRINTB
75
ECAP1INT
76
ECAP2INT
77
ECAP3INT
78
ECAP4INT
79
ECAP5INT
80
ECAP6INT
81
Reserved
82
Reserved
83
EQEP1INT
84
EQEP2INT
85
EQEP3INT
86
Reserved
87
Reserved
88
Reserved
94:89
Reserved
95
SD1INT
96
SD2INT
106:97
Reserved
107
UPP1INT
108
Reserved
109
SPITXINTA
110
SPIRXINTA
111
SPITXINTB
112
SPIRXINTB
113
SPITXINTC
114
SPIRXINTC
126:115
Reserved
127
CLB1INT
128
CLB2INT
129
CLB3INT
130
CLB4INT
255:130
Reserved
For example, Task 1 (MVECT1) can be set to trigger on EPWMINT1 by writing 36 to
DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK1. To disable the triggering of a task by a
peripheral, the user must set the DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx] bit field to 0. It
should be noted that a CLA task only triggers on a level transition (an edge) of the configured interrupt
source.
Software Trigger
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
649
CLA Interface
www.ti.com
CPU software can trigger tasks by writing to the MIFRC register or by the IACK instruction. Using the
IACK instruction is more efficient because it does not require you to issue an EALLOW to set MIFR
bits. Set the MCTL[IACKE] bit to enable the IACK feature. Each bit in the operand of the IACK
instruction corresponds to a task. For example IACK #0x0001 will set bit 0 in the MIFR register to start
task 1. Likewise IACK #0x0003 will set bits 0 and 1 in the MIFR register to start task 1 and task 2.
The CLA has its own fetch mechanism and can run and execute a task independent of the CPU. Only one
task is serviced at a time; there is no nesting of tasks. The task currently running is indicated in the
MIRUN register. Interrupts that have been received but not yet serviced are indicated in the flag register
(MIFR). If an interrupt request from a peripheral is received and that same task is already flagged, then
the overflow flag bit is set. Overflow flags will remain set until they are cleared by the CPU.
If the CLA is idle (no task is currently running) then the highest priority interrupt request that is both
flagged (MIFR) and enabled (MIER) will start. The flow is as follows:
1. The associated RUN register bit is set (MIRUN) and the flag bit (MIFR) is cleared.
2. The CLA begins execution at the location indicated by the associated interrupt vector (MVECTx).
MVECT contains the absolute 16-bit address of the task in the lower 64K memory space.
3. The CLA executes instructions until the MSTOP instruction is found. This indicates the end of the task.
4. The MIRUN bit is cleared.
5. The task-specific interrupt to the PIE is issued. This informs the main CPU that the task has
completed.
6. The CLA returns to idle.
Once a task completes the next highest-priority pending task is automatically serviced and this sequence
repeats.
6.3.5 CLA Software Interrupt to CPU
The CLA can issue a software interrupt to the C28x CPU at any point in the code through the use of the
CLA1SOFTINTEN and CLA1INTFRC registers. Please see Section 6.8 for a description of these registers.
If a software interrupt is selected for a CLA task, then an end-of-task interrupt will not be issued to the
C28x when that task completes.
6.4
CLA and CPU Arbitration
Typically, CLA activity is independent of the CPU activity. Under the circumstance where the CLA or CPU
attempt to concurrently access memory or a peripheral register within the same interface, an arbitration
procedure will occur. This section describes this arbitration.
The arbitration follows a fixed arbitration scheme with highest priority first:
1. CLA WRITE
2. CLA READ
3. CPU WRITE
4. CPU READ
They are covered in detail in the Section 3.11.
6.4.1 CLA Message RAM
Message RAMs consist of two blocks:
• CLA to CPU Message RAM
• CPU to CLA Message RAM
These blocks are useful for passing data between the CLA and CPU. No opcode fetches, from either the
CLA or CPU, are allowed from the message RAMs. A write protection violation will not be generated if the
CLA attempts to write to the CPU to CLA message RAM but the write will be ignored. The arbitration
scheme for the message RAMs are the same as those for the shared memories described in the
Section 3.11.
The message RAMs have the following characteristics:
650
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CLA and CPU Arbitration
www.ti.com
•
•
CLA to CPU Message RAM:
The following accesses are allowed:
– CPU reads
– CLA data reads and writes
– CPU debug reads and writes
The following accesses are ignored:
– CPU writes
CPU to CLA Message RAM:
The following accesses are allowed:
– CPU reads and writes
– CLA reads
– CPU debug reads and writes
The following accesses are ignored:
– CLA writes
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
651
CLA Configuration and Debug
6.5
www.ti.com
CLA Configuration and Debug
This section discusses the steps necessary to configure and debug the CLA.
6.5.1 Building a CLA Application
The control law accelerator can be programmed in either CLA assembly code, using the instructions
described in Section 6.7, or a reduced subset of the C language. CLA assembly code resides in the same
project with C28x code. The only restriction is the CLA code must be in its own assembly section. This
can be easily done using the .sect assembly directive. This does not prevent CLA and C28x code from
being linked into the same memory region in the linker command file.
System and CLA initialization are performed by the main CPU. This would typically be done in C or C++
but can also include C28x assembly code. The main CPU will also copy the CLA code to the program
memory and, if needed, initialize the CLA data RAM(s). Once system initialization is complete and the
application begins, the CLA will service its interrupts using the CLA assembly code (or tasks). The main
CPU can perform other tasks concurrently with CLA program execution.
The CLA Type 1 requires Codegen V6.2.4 or later with the compiler switch: --cla_support=cla1.
6.5.2 Typical CLA Initialization Sequence
A typical CLA initialization sequence is performed by the main CPU as described in this section.
1. Copy CLA code into the CLA program RAM
The source for the CLA code can initially reside in the flash or a data stream from a communications
peripheral or anywhere the main CPU can access it. The debugger can also be used to load code
directly to the CLA program RAM during development.
2. Initialize CLA data RAM, if necessary
Populate the CLA data RAM with any required data coefficients or constants.
3. Configure the CLA registers
Configure the CLA registers, but keep interrupts disabled until later (leave MIER = 0):
• Enable the CLA peripheral clock using the assigned PCLKCRn register
The peripheral clock control (PCLKCRn) registers are defined in the System Control chapter.
• Populate the CLA task interrupt vectors
– MVECT1 to MVECT8
Each vector needs to be initialized with the start address of the task to be executed when the
CLA receives the associated interrupt. This address is the full 16-bit starting address of the task
in the lower 64K section of memory.
• Select the task interrupt sources
For each task select the interrupt source in the CLA1TASKSRCSELx register. If a task is software
triggered, select no interrupt.
• Enable IACK to start a task from software, if desired
To enable the IACK instruction to start a task set the MCTL[IACKE] bit. Using the IACK instruction
avoids having to set and clear the EALLOW bit.
• Map CLA data RAM to CLA space, if necessary
Map the data RAM to the CLA space by first, assigning ownership of the memory block to the CLA
by writing a 1 to the memory block’s MemCfgRegs.LSxMSEL[MSEL_LSx] bit, and then specifying
the memory block as a CLA data block by writing a 0 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit. When an LSx memory is configured as a CLA data
memory, the CLA read/write accesses are arbitrated along with CPU accesses. The user has the
option of turning on CPU fetch or write protection to the memory by writing to the appropriate bits of
the MemCfgRegs.LSxACCPROTx registers.
• Map CLA program RAM to CLA space
Map the CLA program RAM to CLA space by first assigning ownership of the memory block to the
CLA by writing a 1 to the memory block’s MemCfgRegs.LSxMSEL[MSEL_LSx] bit, and then
652
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CLA Configuration and Debug
www.ti.com
specifying the memory block as CLA code memory by writing a 1 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit. When an LSx memory is configured as CLA
program memory, only debug accesses are allowed on cycles in which the CLA is not fetching a
new instruction.
4. Initialize the PIE vector table and registers
When a CLA task completes, the associated interrupt in the PIE will be flagged. The CLA overflow and
underflow flags also have associated interrupts within the PIE.
5. Enable CLA tasks/interrupts
Set appropriate bits in the interrupt enable register (MIER) to allow the CLA to service interrupts.
6. Initialize other peripherals
Initialize any peripherals (such as ePWM, ADC, and others) that will generate interrupt triggers for
enabled CLA tasks.
The CLA is now ready to service interrupts and the message RAMs can be used to pass data between
the CPU and the CLA. Mapping of the CLA program and data RAMs typically occurs only during the
initialization process. If the RAM mapping needs to be changed after initialization, the CLA interrupts
must be disabled and all tasks must be completed (by checking the MIRUN register) prior to modifying
the RAM ownership.
6.5.3 Debugging CLA Code
Debugging the CLA code is a simple process that occurs independently of the main CPU. .
6.5.3.1 Breakpoint Support (MDEBUGSTOP)
1. Insert a breakpoint in CLA code
Insert a CLA breakpoint (MDEBUGSTOP instruction) into the code where you want the CLA to halt,
then rebuild and reload the code. Because the CLA does not flush its pipeline when you single-step,
the MDEBUGSTOP instruction must be inserted as part of the code. The debugger cannot insert it as
needed.
If CLA breakpoints are not enabled, then the MDEBUGSTOP will be ignored and is treated as a
MNOP. The MDEBUGSTOP instruction can be placed anywhere in the CLA code as long as it is not
within three instructions of a MBCNDD, MCCNDD, or MRCNDD instruction. When programming in C,
the user can use the __mdebugstop() intrinsic instead; the compiler will ensure that the placement of
the MDEBUSTOP instruction in the generated assembly does not violate any of the pipeline
restrictions.
2. Enable CLA breakpoints
Enable the CLA breakpoints in the debugger. In Code Composer Studio, this is done by connecting to
the CLA core (or tap) from the debug perspective. Breakpoints are disabled when the core is
disconnected.
3. Start the task
There are three ways to start the task:
1. The peripheral can assert an interrupt,
2. The main CPU can execute an IACK instruction, or
3. The user can manually write to the MIFRC register in the debugger window
When the task starts, the CLA will execute instructions until the MDEBUGSTOP is in the D2 phase of
the pipeline. At this point, the CLA will halt and the pipeline will be frozen. The MPC register will reflect
the address of the MDEBUGSTOP instruction.
4. Single-step the CLA code
Once halted, the user can single-step the CLA code. The behavior of a CLA single-step is different
than the main C28x. When issuing a CLA single-step, the pipeline is clocked only one cycle and then
again frozen. On the 28x CPU, the pipeline is flushed for each single-step.
You can also run to the next MDEBUGSTOP or to the end of the task. If another task is pending, it will
automatically start when you run to the end of the task.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
653
CLA Configuration and Debug
www.ti.com
NOTE: A CLA fetch has higher priority than CPU debug reads. For this reason, it is possible for the
CLA to permanently block CPU debug accesses if the CLA is executing in a loop. This might
occur when initially developing CLA code due to a bug that causes an infinite loop. To avoid
locking up the main CPU, the program memory will return all 0x0000 for CPU debug reads
when the CLA is running. When the CLA is halted or idle then normal CPU debug read and
write access to CLA program memory can be performed.
If the CLA gets caught in an infinite loop, you can use a soft or hard reset to exit the
condition. A debugger reset will also exit the condition.
There are special cases that can occur when single-stepping a task such that the program counter,
MPC, reaches the MSTOP instruction at the end of the task.
• MPC halts at or after the MSTOP with a task already pending
If you are single-stepping or halted in "task A" and "task B" comes in before the MPC reaches the
MSTOP, then "task B" will start if you continue to step through the MSTOP instruction. Basically if
"task B" is pending before the MPC reaches MSTOP in "task A" then there is no issue in "task B"
starting and no special action is required.
• MPC halts at or after the MSTOP with no task pending
In this case you have single-stepped or halted in "task A" and the MPC has reached the MSTOP
with no tasks pending. If "task B" comes in at this point, it will be flagged in the MIFR register but it
may or may not start if you continue to single-step through the MSTOP instruction of "task A."
It depends on exactly when the new task comes in. To reliably start "task B" perform a soft reset
and reconfigure the MIER bits. Once this is done, you can start single-stepping "task B."
This case can be handled slightly differently if there is control over when "task B" comes in (for
example using the IACK instruction to start the task). In this case you have single-stepped or halted
in "task A" and the MPC has reached the MSTOP with no tasks pending. Before forcing "task B,"
run free to force the CLA out of the debug state. Once this is done you can force "task B" and
continue debugging.
5. Disable CLA breakpoints, if desired
In Code Composer Studio you can disable the CLA breakpoints by disconnecting the CLA core in the
debug perspective. Make sure to first issue a run or reset; otherwise, the CLA will be halted and no
other tasks will start.
6.5.4 CLA Illegal Opcode Behavior
If the CLA fetches an opcode that does not correspond to a legal instruction, it will behave as follows:
• The CLA will halt with the illegal opcode in the D2 phase of the pipeline as if it were a breakpoint. This
will occur whether CLA breakpoints are enabled or not.
• The CLA will issue the task-specific interrupt to the PIE.
• The MIRUN bit for the task will remain set.
Further single-stepping is ignored once execution halts due to an illegal op-code. To exit this situation,
issue either a soft or hard reset of the CLA as described in Section 6.5.5.
6.5.5 Resetting the CLA
There may be times when you need to reset the CLA. For example, during code debug the CLA may enter
an infinite loop due to a code bug. The CLA has two types of resets: hard and soft. Both of these resets
can be performed by the debugger or by the main CPU.
• Hard Reset
Writing a 1 to the MCTL[HARDRESET] bit will perform a hard reset of the CLA. The behavior of a hard
reset is the same as a system reset (via XRS or the debugger). In this case all CLA configuration and
execution registers will be set to their default state and CLA execution will halt.
• Soft Reset
Writing a 1 to the MCTL[SOFTRESET] bit performs a soft reset of the CLA. If a task is executing it will
halt and the associated MIRUN bit will be cleared. All bits within the interrupt enable (MIER) register
654
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CLA Configuration and Debug
www.ti.com
will also be cleared so that no new tasks start.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
655
Pipeline
6.6
www.ti.com
Pipeline
This section describes the CLA pipeline stages and presents cases where pipeline alignment must be
considered.
6.6.1 Pipeline Overview
The CLA pipeline is very similar to the C28x pipeline with eight stages:
1. Fetch 1 (F1)
During the F1 stage the program read address is placed on the CLA program address bus.
2. Fetch 2 (F2)
During the F2 stage the instruction is read using the CLA program data bus.
3. Decode 1 (D1)
During D1 the instruction is decoded.
4. Decode 2 (D2)
Generate the data read address. Changes to MAR0 and MAR1 due to post-increment using indirect
addressing takes place in the D2 phase. Conditional branch decisions are also made at this stage
based on the MSTF register flags.
5. Read 1 (R1)
Place the data read address on the CLA data-read address bus. If a memory conflict exists, the R1
stage will be stalled.
6. Read 2 (R2)
Read the data value using the CLA data read data bus.
7. Execute (EXE)
Execute the operation. Changes to MAR0 and MAR1 due to loading an immediate value or value from
memory take place in this stage.
8. Write (W)
Place the write address and write data on the CLA write data bus. If a memory conflict exists, the W
stage will be stalled.
6.6.2 CLA Pipeline Alignment
The majority of the CLA instructions do not require any special pipeline considerations. This section lists
the few operations that do require special consideration.
• Write Followed by Read
In both the C28x and the CLA pipeline the read operation occurs before the write. This means that if a
read operation immediately follows a write, then the read will complete first as shown in Table 6-2. In
most cases this does not cause a problem since the contents of one memory location does not depend
on the state of another. For accesses to peripherals where a write to one location can affect the value
in another location the code must wait for the write to complete before issuing the read as shown in
Table 6-3.
This behavior is different for the 28x CPU. For the 28x CPU any write followed by read to the same
location is protected by what is called write-followed-by-read protection. This protection automatically
stalls the pipeline so that the write will complete before the read. In addition some peripheral frames
are protected such that a 28x CPU write to one location within the frame will always complete before a
read to the frame. The CLA does not have this protection mechanism. Instead the code must wait to
perform the read.
656 Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Pipeline
www.ti.com
Table 6-2. Write Followed by Read - Read Occurs First
Instruction
F1
I1 MMOV16 @Reg1, MR3
I1
I2 MMOV16 MR2, @Reg2
I2
F2
D1
D2
R1
R2
E
W
I1
I2
I1
I2
I1
I2
I1
I2
I1
I2
I1
I2
I1
Table 6-3. Write Followed by Read - Write Occurs First
Instruction
F1
I1 MMOV16 @Reg1, MR3
I1
F2
D1
D2
R1
R2
E
I2
I2
I1
I3
I3
I2
I1
I4
I4
I3
I2
I1
I5 MMOV16 MR2, @Reg2
I5
I4
I3
I2
I1
I5
I4
I3
I2
I1
I5
I4
I3
I2
I1
I5
I4
I3
I2
I5
I4
I3
I5
I4
W
I1
I5
•
Delayed Conditional instructions: MBCNDD, MCCNDD and MRCNDD
Referring to Example 6-1, the following applies to delayed conditional instructions:
– I1
I1 is the last instruction that can effect the CNDF flags for the branch, call or return instruction. The
CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is made whether to
branch or not when MBCNDD, MCCNDD or MRCNDD is in the D2 phase.
– I2, I3 and I4
The three instructions preceding MBCNDD can change MSTF flags but will have no effect on
whether the MBCNDD instruction branches or not. This is because the flag modification will occur
after the D2 phase of the branch, call or return instruction. These three instructions must not be a
MSTOP, MDEBUGSTOP, MBCNDD, MCCNDD or MRCNDD.
– I5, I6 and I7
The three instructions following a branch, call or return are always executed irrespective of whether
the condition is true or not. These instructions must not be MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD or MRCNDD.
For a more detailed description refer to the functional description for MBCNDD, MCCNDD and
MRCNDD.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
657
Pipeline
www.ti.com
Example 6-1. Code Fragment For MBCNDD, MCCNDD or MRCNDD
; I1 Last instruction that can affect flags for
;
the branch, call or return operation
; I2 Cannot be stop, branch, call or return
; I3 Cannot be stop, branch, call or return
; I4 Cannot be stop, branch, call or return
; MBCNDD, MCCNDD or MRCNDD
; I5-I7: Three instructions after are always
; executed whether the branch/call or return is
; taken or not
; I5 Cannot be stop, branch, call or return
; I6 Cannot be stop, branch, call or return
; I7 Cannot be stop, branch, call or return
....
; I8
; I9
•
•
Stop or Halting a Task: MSTOP and MDEBUGSTOP
The MSTOP and MDEBUGSTOP instructions cannot be placed three instructions before or after a
conditional branch, call or return instruction (MBCNDD, MCCNDD or MRCNDD). Refer to Example 6-1.
To single-step through a branch/call or return, insert the MDEBUGSTOP at least four instructions back
and step from there.
Loading MAR0 or MAR1
A load of auxiliary register MAR0 or MAR1 will occur in the EXE phase of the pipeline. Any post
increment of MAR0 or MAR1 using indirect addressing will occur in the D2 phase of the pipeline.
Referring to Example 6-2, the following applies when loading the auxiliary registers:
– I1 and I2
The two instructions following the load instruction will use the value in MAR0 or MAR1 before the
update occurs.
– I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-increment
addressing occur in the D2 phase. Thus I3 cannot use the auxiliary register or there will be a
conflict. In the case of a conflict, the update due to address-mode post increment will win and the
auxiliary register will not be updated with #_X.
– I4
Starting with the 4th instruction MAR0 or MAR1 will have the new value.
Example 6-2. Code Fragment for Loading MAR0 or MAR1
; Assume MAR0 is 50 and #_X is 20
MMOVI16 MAR0, #_X
....
658
;
;
;
;
;
;
Load MAR0 with address of
I1 Will use the old value
I2 Will use the old value
I3 Cannot use MAR0
I4 Will use the new value
I5 Will use the new value
Control Law Accelerator (CLA)
X (20)
of MAR0 (50)
of MAR0 (50)
of MAR0 (20)
of MAR0 (20
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Pipeline
www.ti.com
6.6.2.1
ADC Early Interrupt to CLA Response
The ADC can be configured to generate an early interrupt pulse before the ADC conversion completes. If
this option is used to start a CLA task, the CLA will be able to read the result as soon as the conversion
result is available in the ADC result register. This combination of just-in-time sampling along with the low
interrupt response of the CLA enable faster system response and higher frequency control loops.
Timings for ADC conversions are shown in the timing diagrams of the ADC chapter. If the ADCCLK is a
divided down version of the SYSCLK, the user will have to account for the conversion time in SYSCLK
cycles.
For example, if using the 12-bit ADC with ADCCLK at SYSCLK / 4, it would take 10.5 ADCCLK x 4
SYSCLK = 42 SYSCLK cycles to complete a conversion.
From a CLA perspective, the pipeline activity is shown in Table 6-4 for an N-cycle (SYSCLK) ADC
conversion. The N-2 instruction will arrive in the R2 phase just in time to read the result register. While the
prior instructions will enter the R2 phase of the pipeline too soon to read the conversion, they can be
efficiently used for pre-processing calculations needed by the task.
Table 6-4. ADC to CLA Early Interrupt Response
ADC Activity
CLA Activity
F1
F2
D1
D2
R1
R2
E
W
Sample
Sample
...
Sample
Conversion(Cycle 1)
Interrupt Received
Conversion(Cycle 2)
Task Startup
Conversion(Cycle 3)
Task Startup
Conversion(Cycle 4)
I(Cycle 4)
I(Cycle
4)
Conversion(Cycle 5)
I(Cycle 5)
I(Cycle
5)
Conversion(...)
...
...
...
...
...
...
...
Conversion(Cycle N-6)
I(Cycle N-6)
I(Cycle N-6)
I(Cycle N-7)
I(Cycle N-8)
I(Cycle N-9)
I(Cycle N-10)
I(Cycle N-11)
Conversion(Cycle N-5)
I(Cycle N-5)
I(Cycle N-5)
I(Cycle N-6)
I(Cycle N-7)
I(Cycle N-8)
I(Cycle N-9)
I(Cycle N-10)
Conversion(Cycle N-4)
I(Cycle N-4)
I(Cycle N-4)
I(Cycle N-5)
I(Cycle N-6)
I(Cycle N-7)
I(Cycle N-8)
I(Cycle N-9)
Conversion(Cycle N-3)
I(Cycle N-3)
I(Cycle N-3)
I(Cycle N-4)
I(Cycle N-5)
I(Cycle N-6)
I(Cycle N-7)
I(Cycle N-8)
Read RESULT
Read
RESULT
I(Cycle N-3)
I(Cycle N-4)
I(Cycle N-5)
I(Cycle N-6)
I(Cycle N-7)
Read
RESULT
I(Cycle N-3)
I(Cycle N-4)
I(Cycle N-5)
I(Cycle N-6)
Read
RESULT
I(Cycle N-3)
I(Cycle N-4)
I(Cycle N-5)
Read
RESULT
I(Cycle N-3)
I(Cycle N-4)
Read
RESULT
I(Cycle N-3)
Conversion(Cycle N-2)
Conversion(Cycle N-1)
Conversion(Cycle N-0)
Conversion Complete
I(Cycle
4)
RESULT Latched
Read
RESULT
RESULT Available
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
659
Pipeline
www.ti.com
6.6.3 Parallel Instructions
Parallel instructions are single opcodes that perform two operations in parallel. The following types of
parallel instructions are available: math operation in parallel with a move operation, or two math
operations in parallel. Both operations complete in a single cycle and there are no special pipeline
alignment requirements.
Example 6-3. Math Operation with Parallel Load
;
;
;
MADDF32 || MMOV32 instruction: 32-bit floating-point add with parallel move
MADDF32 is a 1 cycle operation
MMOV32 is a 1 cycle operation
MADDF32
MR0, MR1, #2
; MR0 = MR1 + 2,
|| MMOV32
MR1, @Val
; MR1 gets the contents of Val
; #16FHi:0) {ZF=0, NF=0;}
If(MRa < #16FHi:0) {ZF=0, NF=1;}
Pipeline
This is a single-cycle instruction
Example 1
; Behavior of ZF and NF flags for different comparisons
MMOVIZ
MMOVIZ
MCMPF32
MCMPF32
MCMPF32
MR1,
MR0,
MR1,
MR0,
MR0,
#-2.0
#5.0
#-2.2
#6.5
#5.0
;
;
;
;
;
MR1 = -2.0 (0xC0000000)
MR0 = 5.0 (0x40A00000)
ZF = 0, NF = 0
ZF = 0, NF = 1
ZF = 1, NF = 0
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
689
Instruction Set
Example 2
www.ti.com
; X is an array of 32-bit floating-point values
; and has len elements. Find the maximum value in
; the array and store it in Result
;
; Note: MCMPF32 and MSWAPF can be replaced with MMAXF32
;
_Cla1Task1:
MMOVI16 MAR1,#_X
; Start address
MUI16TOF32 MR0, @_len
; Length of the array
MNOP
; delay for MAR1 load
MNOP
; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++
MCMPF32 MR2, MR1
MSWAPF MR1, MR2, GT
MADDF32 MR0, MR0, #-1.0
MCMPF32 MR0 #0.0
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ
MMOV32 @_Result, MR1
MNOP
MNOP
MSTOP
See also
690
;
;
;
;
;
MR2 = next element
Compare MR2 with MR1
MR1 = MAX(MR1, MR2)
Decrememt the counter
Set/clear flags for MBCNDD
;
;
;
;
;
Branch
Always
Always
Always
End of
if not equal to zero
executed
executed
executed
task
MCMPF32 MRa, MRb
MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, #16FHi
MMINF32 MRa, MRb
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Instruction Set
www.ti.com
MDEBUGSTOP
Debug Stop Task
Operands
none
This instruction does not have any operands
Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 0110 0000
Description
When CLA breakpoints are enabled, the MDEBUGSTOP instruction is used to halt a
task so that it can be debugged. That is, MDEBUGSTOP is the CLA breakpoint. If CLA
breakpoints are not enabled, the MDEBUGSTOP instruction behaves like a MNOP.
Unlike the MSTOP, the MIRUN flag is not cleared and an interrupt is not issued. A
single-step or run operation will continue execution of the task.
Restrictions
The MDEBUGSTOP instruction cannot be placed 3 instructions before or after a
MBCNDD, MCCNDD or MRCNDD instruction.
Flags
This instruction does not modify flags in the MSTF register.
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
Pipeline
This is a single-cycle instruction.
Example
;
See also
MSTOP,
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
691
Instruction Set
MEALLOW
www.ti.com
Enable CLA Write Access to EALLOW Protected Registers
Operands
none
This instruction does not have any operands
Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1001 0000
Description
This instruction sets the MEALLOW bit in the CLA status register MSTF. When this bit is
set, the CLA is allowed write access to EALLOW protected registers. To again protect
against CLA writes to protected registers, use the MEDIS instruction.
MEALLOW and MEDIS only control CLA write access; reads are allowed even if
MEALLOW has not been executed. MEALLOW and MEDIS are also independent from
the main CPU's EALLOW/EDIS. This instruction does not modify the EALLOW bit in the
main CPU's status register. The MEALLOW bit in MSTF only controls access for the
CLA while the EALLOW bit in the ST1 register only controls access for the main CPU.
As with EALLOW, the MEALLOW bit is overridden via the JTAG port, allowing full control
of register accesses during debug from Code Composer Studio.
This instruction does not modify flags in the MSTF register.
Flags
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
Pipeline
This is a single-cycle instruction.
Example
; C header file including definition of
; the EPwm1Regs structure
;
; The ePWM TZSEL register is EALLOW protected
;
.cdecls C,LIST,"CLAShared.h"
...
_Cla1Task1:
...
MEALLOW
; Allow CLA write access
MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL
MEDIS
; Disallow CLA write access
...
...
MSTOP
See also
MEDIS
692
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Instruction Set
www.ti.com
MEDIS
Disable CLA Write Access to EALLOW Protected Registers
Operands
none
This instruction does not have any operands
Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1011 0000
Description
This instruction clears the MEALLOW bit in the CLA status register MSTF. When this bit
is clear, the CLA is not allowed write access to EALLOW-protected registers. To enable
CLA writes to protected registers, use the MEALLOW instruction.
MEALLOW and MEDIS only control CLA write access; reads are allowed even if
MEALLOW has not been executed. MEALLOW and MEDIS are also independent from
the main CPU's EALLOW/EDIS. This instruction does not modify the EALLOW bit in the
main CPU's status register. The MEALLOW bit in MSTF only controls access for the
CLA while the EALLOW bit in the ST1 register only controls access for the main CPU.
As with EALLOW, the MEALLOW bit is overridden via the JTAG port, allowing full control
of register accesses during debug from Code Composer Studio.
Flags
This instruction does not modify flags in the MSTF register.
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
Pipeline
This is a single-cycle instruction.
Example
; C header file including definition of
; the EPwm1Regs structure
;
; The ePWM TZSEL register is EALLOW protected
;
.cdecls C,LIST,"CLAShared.h"
...
_Cla1Task1:
...
MEALLOW
; Allow CLA write access
MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL
MEDIS
; Disallow CLA write access
...
...
MSTOP
See also
MEALLOW
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
693
Instruction Set
www.ti.com
MEINVF32 MRa, MRb 32-Bit Floating-Point Reciprocal Approximation
Operands
MRa
CLA floating-point destination register (MR0 to MR3)
MRb
CLA floating-point source register (MR0 to MR3)
Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1111 0000 0000
Description
This operation generates an estimate of 1/X in 32-bit floating-point format accurate to
approximately 8 bits. This value can be used in a Newton-Raphson algorithm to get a
more accurate answer. That is:
Ye = Estimate(1/X);
Ye = Ye*(2.0 - Ye*X);
Ye = Ye*(2.0 - Ye*X);
After two iterations of the Newton-Raphson algorithm, you will get an exact answer
accurate to the 32-bit floating-point format. On each iteration the mantissa bit accuracy
approximately doubles. The MEINVF32 operation will not generate a negative zero,
DeNorm or NaN value.
MRa = Estimate of 1/MRb;
This instruction modifies the following flags in the MSTF register:
Flags
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
Yes
Yes
The MSTF register flags are modified as follows:
• LUF = 1 if MEINVF32 generates an underflow condition.
• LVF = 1 if MEINVF32 generates an overflow condition.
Pipeline
This is a single-cycle instruction.
Example
; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den
; MR1 = Den
MEINVF32 MR2, MR1
; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num
; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den
; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ
; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0
; Store result
MSTOP
; end of task
See also
MEISQRTF32 MRa, MRb
694
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Instruction Set
www.ti.com
MEISQRTF32 MRa, MRb 32-Bit Floating-Point Square-Root Reciprocal Approximation
Operands
MRa
CLA floating-point destination register (MR0 to MR3)
MRb
CLA floating-point source register (MR0 to MR3)
Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0100 0000
Description
This operation generates an estimate of 1/sqrt(X) in 32-bit floating-point format accurate
to approximately 8 bits. This value can be used in a Newton-Raphson algorithm to get a
more accurate answer. That is:
Ye = Estimate(1/sqrt(X));
Ye = Ye*(1.5 - Ye*Ye*X/2.0);
Ye = Ye*(1.5 - Ye*Ye*X/2.0);
After 2 iterations of the Newton-Raphson algorithm, you will get an exact answer
accurate to the 32-bit floating-point format. On each iteration the mantissa bit accuracy
approximately doubles. The MEISQRTF32 operation will not generate a negative zero,
DeNorm or NaN value.
MRa = Estimate of 1/sqrt (MRb);
Flags
This instruction modifies the following flags in the MSTF register:
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
Yes
Yes
The MSTF register flags are modified as follows:
• LUF = 1 if MEISQRTF32 generates an underflow condition.
• LVF = 1 if MEISQRTF32 generates an overflow condition.
Pipeline
This is a single-cycle instruction.
Example
; Y = sqrt(X)
; Ye = Estimate(1/sqrt(X));
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Y = X*Ye
;
_Cla1Task3:
MMOV32 MR0, @_x
;
MEISQRTF32 MR1, MR0
;
MMOV32 MR1, @_x, EQ
;
MMPYF32 MR3, MR0, #0.5
;
MMPYF32 MR2, MR1, MR3
;
MMPYF32 MR2, MR1, MR2
;
MSUBF32 MR2, #1.5, MR2
;
MMPYF32 MR1, MR1, MR2
;
MMPYF32 MR2, MR1, MR3
;
MMPYF32 MR2, MR1, MR2
;
MSUBF32 MR2, #1.5, MR2
;
MMPYF32 MR1, MR1, MR2
;
MMPYF32 MR0, MR1, MR0
;
MMOV32 @_y, MR0
;
MSTOP
;
See also
MR0 = X
MR1 = Ye = Estimate(1/sqrt(X))
if(X == 0.0) Ye = 0.0
MR3 = X*0.5
MR2 = Ye*X*0.5
MR2 = Ye*Ye*X*0.5
MR2 = 1.5 - Ye*Ye*X*0.5
MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MR2 = Ye*X*0.5
MR2 = Ye*Ye*X*0.5
MR2 = 1.5 - Ye*Ye*X*0.5
MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MR0 = Y = Ye*X
Store Y = sqrt(X)
end of task
MEINVF32 MRa, MRb
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
695
Instruction Set
www.ti.com
MF32TOI16 MRa, MRb Convert 32-Bit Floating-Point Value to 16-Bit Integer
Operands
MRa
CLA floating-point destination register (MR0 to MR3)
MRb
CLA floating-point source register (MR0 to MR3)
Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1110 0000
Description
Convert a 32-bit floating point value in MRb to a 16-bit integer and truncate. The result
will be stored in MRa.
MRa(15:0) = F32TOI16(MRb);
MRa(31:16) = sign extension of MRa(15);
This instruction does not affect any flags:
Flags
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
Pipeline
This is a single-cycle instruction.
Example
MMOVIZ
MF32TOI16
MR0, #5.0
MR1, MR0
MMOVIZ
MF32TOI16
MR2, #-5.0
MR3, MR2
See also
696
;
;
;
;
;
;
MR0
MR1(15:0)
MR1(31:16)
MR2
MR3(15:0)
MR3(31:16)
=
=
=
=
=
=
5.0 (0x40A00000)
MF32TOI16(MR0) = 0x0005
Sign extension of MR1(15) = 0x0000
-5.0 (0xC0A00000)
MF32TOI16(MR2) = -5 (0xFFFB)
Sign extension of MR3(15) = 0xFFFF
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Instruction Set
www.ti.com
MF32TOI16R MRa, MRb Convert 32-Bit Floating-Point Value to 16-Bit Integer and Round
Operands
MRa
CLA floating-point destination register (MR0 to MR3)
MRb
CLA floating-point source register (MR0 to MR3)
Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0110 0000
Description
Convert the 32-bit floating point value in MRb to a 16-bit integer and round to the nearest
even value. The result is stored in MRa.
MRa(15:0) = F32TOI16round(MRb);
MRa(31:16) = sign extension of MRa(15);
Flags
This instruction does not affect any flags:
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
Pipeline
This is a single-cycle instruction.
Example
MMOVIZ MR0, #0x3FD9
MMOVXI MR0, #0x999A
MF32TOI16R MR1, MR0
MMOVF32 MR2, #-1.7
MF32TOI16R MR3, MR2
See also
;
;
;
;
;
;
;
;
MR0(31:16) = 0x3FD9
MR0(15:0) = 0x999A
MR0 = 1.7 (0x3FD9999A)
MR1(15:0) = MF32TOI16round (MR0) = 2 (0x0002)
MR1(31:16) = Sign extension of MR1(15) = 0x0000
MR2 = -1.7 (0xBFD9999A)
MR3(15:0) = MF32TOI16round (MR2) = -2 (0xFFFE)
MR3(31:16) = Sign extension of MR2(15) = 0xFFFF
MF32TOI16 MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
697
Instruction Set
www.ti.com
MF32TOI32 MRa, MRb Convert 32-Bit Floating-Point Value to 32-Bit Integer
Operands
MRa
CLA floating-point destination register (MR0 to MR3)
MRb
CLA floating-point source register (MR0 to MR3)
Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0110 0000
Description
Convert the 32-bit floating-point value in MRb to a 32-bit integer value and truncate.
Store the result in MRa.
MRa = F32TOI32(MRb);
This instruction does not affect any flags:
Flags
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
Pipeline
This is a single-cycle instruction.
Example 1
MMOVF32
MF32TOI32
MMOVF32
MF32TOI32
Example 2
; Given X, M and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
; Convert M, X and B from IQ24 to float
;
_Cla1Task2:
MI32TOF32 MR0, @_M
; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X
; MR1 = 0x4C200000
MI32TOF32 MR2, @_B
; MR2 = 0xCB000000
MMPYF32
MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32
MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32
MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32
MR3, MR0, MR1
; M*X
MADDF32
MR2, MR2, MR3
; Y=MX+B = 3.25 (0x40500000)
MR2,
MR3,
MR0,
MR1,
#11204005.0
MR2
#-11204005.0
MR0
;
;
;
;
MR2
MR3
MR0
MR1
; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80
;
MF32TOI32 MR2, MR2
;
MMOV32 @_Y, MR2
;
MSTOP
;
See also
698
=
=
=
=
11204005.0 (0x4B2AF5A5)
MF32TOI32(MR2) = 11204005 (0x00AAF5A5)
-11204005.0 (0xCB2AF5A5)
MF32TOI32(MR0) = -11204005 (0xFF550A5B)
Y * 1*2^24
IQ24(Y) = 0x03400000
store result
end of task
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Instruction Set
www.ti.com
MF32TOUI16 MRa, MRb Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer
Operands
MRa
CLA floating-point destination register (MR0 to MR3)
MRb
CLA floating-point source register (MR0 to MR3)
Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1010 0000
Description
Convert the 32-bit floating point value in MRb to an unsigned 16-bit integer value and
truncate to zero. The result will be stored in MRa. To instead round the integer to the
nearest even value use the MF32TOUI16R instruction.
MRa(15:0) = F32TOUI16(MRb);
MRa(31:16) = 0x0000;
Flags
This instruction does not affect any flags:
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
Pipeline
This is a single-cycle instruction.
Example
MMOVIZ
MF32TOUI16
MR0, #9.0
MR1, MR0
MMOVIZ
MF32TOUI16
MR2, #-9.0
MR3, MR2
See also
;
;
;
;
;
;
MR0 = 9.0 (0x41100000)
MR1(15:0) = MF32TOUI16(MR0) = 9 (0x0009)
MR1(31:16) = 0x0000
MR2 = -9.0 (0xC1100000)
MR3(15:0) = MF32TOUI16(MR2) = 0 (0x0000)
MR3(31:16) = 0x0000
MF32TOI16 MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
699
Instruction Set
www.ti.com
MF32TOUI16R MRa, MRb Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer and Round
Operands
MRa
CLA floating-point destination register (MR0 to MR3)
MRb
CLA floating-point source register (MR0 to MR3)
Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1100 0000
Description
Convert the 32-bit floating-point value in MRb to an unsigned 16-bit integer and round to
the closest even value. The result will be stored in MRa. To instead truncate the
converted value, use the MF32TOUI16 instruction.
MRa(15:0) = MF32TOUI16round(MRb);
MRa(31:16) = 0x0000;
This instruction does not affect any flags:
Flags
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
Pipeline
This is a single-cycle instruction.
Example
MMOVIZ
MMOVXI
MF32TOUI16R
MR0, #0x412C
MR0, #0xCCCD
MR1, MR0
MMOVF32
MF32TOUI16R
MR2, #-10.8
MR3, MR2
See also
700
;
;
;
;
;
;
;
MR0 = 0x412C
MR0 = 0xCCCD ; MR0 = 10.8 (0x412CCCCD)
MR1(15:0) = MF32TOUI16round(MR0) = 11 (0x000B)
MR1(31:16) = 0x0000
MR2 = -10.8 (0x0xC12CCCCD)
MR3(15:0) = MF32TOUI16round(MR2) = 0 (0x0000)
MR3(31:16) = 0x0000
MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Instruction Set
www.ti.com
MF32TOUI32 MRa, MRb Convert 32-Bit Floating-Point Value to 32-Bit Unsigned Integer
Operands
MRa
CLA floating-point destination register (MR0 to MR3)
MRb
CLA floating-point source register (MR0 to MR3)
Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1010 0000
Description
Convert the 32-bit floating-point value in MRb to an unsigned 32-bit integer and store the
result in MRa.
MRa = F32TOUI32(MRb);
Flags
This instruction does not affect any flags:
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
Pipeline
This is a single-cycle instruction.
Example
MMOVIZ
MF32TOUI32
MMOVIZ
MF32TOUI32
See also
MF32TOI32 MRa, MRb
MI32TOF32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32
MR0,
MR0,
MR1,
MR2,
#12.5
MR0
#-6.5
MR1
;
;
;
;
MR0
MR0
MR1
MR2
=
=
=
=
12.5 (0x41480000)
MF32TOUI32 (MR0) = 12 (0x0000000C)
-6.5 (0xC0D00000)
MF32TOUI32 (MR1) = 0.0 (0x00000000)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
701
Instruction Set
www.ti.com
MFRACF32 MRa, MRb Fractional Portion of a 32-Bit Floating-Point Value
Operands
MRa
CLA floating-point destination register (MR0 to MR3)
MRb
CLA floating-point source register (MR0 to MR3)
Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0000 0000
Description
Returns in MRa the fractional portion of the 32-bit floating-point value in MRb
Flags
This instruction does not affect any flags:
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
Pipeline
This is a single-cycle instruction.
Example
MMOVIZ
MFRACF32
MR2, #19.625 ; MR2 = 19.625 (0x419D0000)
MR3, MR2
; MR3 = MFRACF32(MR2) = 0.625 (0x3F200000)0)
See also
702
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Instruction Set
www.ti.com
MI16TOF32 MRa, MRb Convert 16-Bit Integer to 32-Bit Floating-Point Value
Operands
MRa
CLA floating-point destination register (MR0 to MR3)
MRb
CLA floating-point source register (MR0 to MR3)
Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1000 0000
Description
Convert the 16-bit signed integer in MRb to a 32-bit floating point value and store the
result in MRa.
MRa = MI16TOF32(MRb);
Flags
This instruction does not affect any flags:
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
Pipeline
This is a single-cycle instruction.
Example
MMOVIZ
MMOVXI
MI16TOF32
MR0, #0x0000
MR0, #0x0004
MR1, MR0
; MR0(31:16) = 0.0 (0x0000)
; MR0(15:0) = 4.0 (0x0004)
; MR1 = MI16TOF32 (MR0) = 4.0 (0x40800000)
MMOVIZ
MMOVXI
MI16TOF32
MSTOP
MR2, #0x0000
MR2, #0xFFFC
MR3, MR2
; MR2(31:16) = 0.0 (0x0000)
; MR2(15:0) = -4.0 (0xFFFC)
; MR3 = MI16TOF32 (MR2) = -4.0 (0xC0800000)
See also
MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
703
Instruction Set
www.ti.com
MI16TOF32 MRa, mem16 Convert 16-Bit Integer to 32-Bit Floating-Point Value
Operands
MRa
CLA floating-point destination register (MR0 to MR3)
mem16
16-bit source memory location to be converted
Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 00aa addr
Description
Convert the 16-bit signed integer indicated by the mem16 pointer to a 32-bit floatingpoint value and store the result in MRa.
MRa = MI16TOF32[mem16];
This instruction does not affect any flags:
Flags
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
Pipeline
This is a single-cycle instruction:
Example
; Assume A = 4 (0x0004)
;
B = -4 (0xFFFC)
MI16TOF32 MR0, @_A ; MR0 = MI16TOF32(A) = 4.0 (0x40800000)
MI16TOF32 MR1, @_B ; MR1 = MI16TOF32(B) = -4.0 (0xC0800000
See also
704
MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Instruction Set
www.ti.com
MI32TOF32 MRa, mem32 Convert 32-Bit Integer to 32-Bit Floating-Point Value
Operands
MRa
CLA floating-point destination register (MR0 to MR3)
mem32
32-bit memory source for the MMOV32 operation.
Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 01aa addr
Description
Convert the 32-bit signed integer indicated by mem32 to a 32-bit floating point value and
store the result in MRa.
MRa = MI32TOF32[mem32];
Flags
This instruction does not affect any flags:
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
Pipeline
This is a single-cycle instruction.
Example
;
;
;
;
;
;
;
;
;
Given X, M and
X = IQ24(+2.5)
M = IQ24(+1.5)
B = IQ24(-0.5)
B
=
=
=
are IQ24 numbers:
0x02800000
0x01800000
0xFF800000
Calculate Y = X * M + B
Convert M, X and B from IQ24 to float
_Cla1Task3:
MI32TOF32 MR0, @_M
MI32TOF32 MR1, @_X
MI32TOF32 MR2, @_B
MMPYF32 MR0, MR0, #0x3380
MMPYF32 MR1, MR1, #0x3380
MMPYF32 MR2, MR2, #0x3380
MMPYF32 MR3, MR0, MR1
MADDF32 MR2, MR2, MR3
;
;
;
;
;
;
;
;
MR0 = 0x4BC00000
MR1 = 0x4C200000
MR2 = 0xCB000000
M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
M*X
Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2
; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2
; store result
MSTOP
; end of task
See also
MF32TOI32 MRa, MRb
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
705
Instruction Set
www.ti.com
MI32TOF32 MRa, MRb Convert 32-Bit Integer to 32-Bit Floating-Point Value
Operands
MRa
CLA floating-point destination register (MR0 to MR3)
MRb
CLA floating-point source register (MR0 to MR3)
Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1000 0000
Description
Convert the signed 32-bit integer in MRb to a 32-bit floating-point value and store the
result in MRa.
MRa = MI32TOF32(MRb);
This instruction does not affect any flags:
Flags
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
Pipeline
This is a single-cycle instruction.
Example
; Example1:
;
MMOVIZ
MMOVXI
MR2, #0x1111 ;
MR2, #0x1111 ;
;
MI32TOF32 MR3, MR2
;
See also
706
MR2(31:16) = 4369 (0x1111)
MR2(15:0) = 4369 (0x1111)
MR2 = +286331153 (0x11111111)
MR3 = MI32TOF32 (MR2) = 286331153.0 (0x4D888888)
MF32TOI32 MRa, MRb
MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Instruction Set
www.ti.com
MLSL32 MRa, #SHIFT Logical Shift Left
Operands
MRa
CLA floating-point source/destination register (MR0 to MR3)
#SHIFT
Number of bits to shift (1 to 32)
Opcode
LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 1100 0000
Description
Logical shift left of MRa by the number of bits indicated. The number of bits can be 1 to
32.
MARa(31:0) = Logical Shift Left(MARa(31:0) by #SHIFT bits);
Flags
This instruction modifies the following flags in the MSTF register:
Flag
TF
ZF
NF
LUF
LVF
Modified
No
Yes
Yes
No
No
The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }
Pipeline
This is a single-cycle instruction.
Example
; Given m2 = (int32)32
;
x2 = (int32)64
;
b2 = (int32)-128
;
; Calculate:
;
m2 = m2*2
;
x2 = x2*4
;
b2 = b2*8
;
_Cla1Task3:
MMOV32 MR0, @_m2
; MR0 = 32 (0x00000020)
MMOV32 MR1, @_x2
; MR1 = 64 (0x00000040)
MMOV32 MR2, @_b2
; MR2 = -128 (0xFFFFFF80)
MLSL32 MR0, #1
; MR0 = 64 (0x00000040)
MLSL32 MR1, #2
; MR1 = 256 (0x00000100)
MLSL32 MR2, #3
; MR2 = -1024 (0xFFFFFC00)
MMOV32 @_m2, MR0
; Store results
MMOV32 @_x2, MR1
MMOV32 @_b2, MR2
MSTOP
; end of task
See also
MADD32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MAND32 MRa, MRb, MRc
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
707
Instruction Set
www.ti.com
MLSR32 MRa, #SHIFT Logical Shift Right
Operands
MRa
CLA floating-point source/destination register (MR0 to MR3)
#SHIFT
Number of bits to shift (1 to 32)
Opcode
LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 1000 0000
Description
Logical shift right of MRa by the number of bits indicated. The number of bits can be 1 to
32. Unlike the arithmetic shift (MASR32), the logical shift does not preserve the number's
sign bit. Every bit in the operand is moved the specified number of bit positions, and the
vacant bit-positions are filled in with zeros
MARa(31:0) = Logical Shift Right(MARa(31:0) by #SHIFT bits);
This instruction modifies the following flags in the MSTF register:
Flags
Flag
TF
ZF
NF
LUF
LVF
Modified
No
Yes
Yes
No
No
The MSTF register flags are modified based on the integer results of the operation.
NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1;}
Pipeline
This is a single-cycle instruction.
Example
; Illustrate the difference between MASR32 and MLSR32
See also
708
MMOVIZ MR0, #0xAAAA
MMOVXI MR0, #0x5555
; MR0 = 0xAAAA5555
MMOV32 MR1, MR0
MMOV32 MR2, MR0
; MR1 = 0xAAAA5555
; MR2 = 0xAAAA5555
MASR32 MR1, #1
MLSR32 MR2, #1
; MR1 = 0xD5552AAA
; MR2 = 0x55552AAA
MASR32 MR1, #1
MLSR32 MR2, #1
; MR1 = 0xEAAA9555
; MR2 = 0x2AAA9555
MASR32 MR1, #6
MLSR32 MR2, #6
; MR1 = 0xFFAAAA55
; MR2 = 0x00AAAA55
MADD32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MAND32 MRa, MRb, MRc
MLSL32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Instruction Set
www.ti.com
MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 32-Bit Floating-Point Multiply and
Accumulate with Parallel Move
Operands
MR3
floating-point destination/source register MR3 for the add operation
MR2
CLA floating-point source register MR2 for the add operation
MRd
CLA floating-point destination register (MR0 to MR3) for the multiply operation
MRd cannot be the same register as MRa
MRe
CLA floating-point source register (MR0 to MR3) for the multiply operation
MRf
CLA floating-point source register (MR0 to MR3) for the multiply operation
MRa
CLA floating-point destination register for the MMOV32 operation (MR0 to MR3).
MRa cannot be MR3 or the same register as MRd.
mem32
32-bit source for the MMOV32 operation
Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0011 ffee ddaa addr
Description
Multiply and accumulate the contents of floating-point registers and move from register
to memory. The destination register for the MMOV32 cannot be the same as the
destination registers for the MMACF32.
MR3 = MR3 + MR2;
MRd = MRe * MRf;
MRa = [mem32];
Restrictions
The destination registers for the MMACF32 and the MMOV32 must be unique. That is,
MRa cannot be MR3 and MRa cannot be the same register as MRd.
Flags
This instruction modifies the following flags in the MSTF register:
Flag
TF
ZF
NF
LUF
LVF
Modified
No
Yes
Yes
Yes
Yes
The MSTF register flags are modified as follows:
• LUF = 1 if MMACF32 (add or multiply) generates an underflow condition.
• LVF = 1 if MMACF32 (add or multiply) generates an overflow condition.
MMOV32 sets the NF and ZF flags as follows:
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }
Pipeline
MMACF32 and MMOV32 complete in a single cycle.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
709
Instruction Set
Example 1
www.ti.com
; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating point arrays
;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3
;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X
; MAR0 points to X array
MMOVI16 MAR1, #_Y
; MAR1 points to Y array
MNOP
; Delay for MAR0, MAR1 load
MNOP
; Delay for MAR0, MAR1 load
; #16FHi:0) {ZF=0; NF=0;}
if(MRa < #16FHi:0) {ZF=0; NF=1;}
Pipeline
This is a single-cycle instruction.
Example
MMOVIZ
MMOVIZ
MMOVIZ
MMAXF32
MMAXF32
MMAXF32
MMAXF32
See also
714
MR0,
MR1,
MR2,
MR0,
MR1,
MR2,
MR2,
#5.0
#4.0
#-1.5
#5.5
#2.5
#-1.0
#-1.0
;
;
;
;
;
;
;
MR0
MR1
MR2
MR0
MR1
MR2
MR2
= 5.0
= 4.0
= -1.5
= 5.5,
= 4.0,
= -1.0,
= -1.5,
(0x40A00000)
(0x40800000)
(0xBFC00000)
ZF = 0, NF =
ZF = 0, NF =
ZF = 0, NF =
ZF = 1, NF =
1
0
1
0
MMAXF32 MRa, MRb
MMINF32 MRa, MRb
MMINF32 MRa, #16FHi
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Instruction Set
www.ti.com
MMINF32 MRa, MRb 32-Bit Floating-Point Minimum
Operands
MRa
CLA floating-point source/destination register (MR0 to MR3)
MRb
CLA floating-point source register (MR0 to MR3)
Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0100 0000
Description
if(MRa > MRb) MRa = MRb;
Special cases for the output from the MMINF32 operation:
• NaN output will be converted to infinity
• A denormalized output will be converted to positive zero.
Flags
This instruction modifies the following flags in the MSTF register:
Flag
TF
ZF
NF
LUF
LVF
Modified
No
Yes
Yes
No
No
The ZF and NF flags are configured on the result of the operation, not the result stored
in the destination register.
if(MRa == MRb) {ZF=1; NF=0;}
if(MRa > MRb) {ZF=0; NF=0;}
if(MRa < MRb) {ZF=0; NF=1;}
Pipeline
This is a single-cycle instruction.
Example 1
MMOVIZ MR0, #5.0
MMOVIZ MR1, #4.0
MMOVIZ MR2, #-1.5
MMINF32 MR0, MR1
MMINF32 MR1, MR2
MMINF32 MR2, MR1
MMINF32 MR1, MR0
Example 2
;
; X is an array of 32-bit floating-point values
; Find the minimum value in an array X
; and store it in Result
;
;
;
;
;
;
;
;
MR0
MR1
MR2
MR0
MR1
MR2
MR2
=
=
=
=
=
=
=
5.0 (0x40A00000)
4.0 (0x40800000)
-1.5 (0xBFC00000)
4.0, ZF = 0, NF = 0
-1.5, ZF = 0, NF = 0
-1.5, ZF = 1, NF = 0
-1.5, ZF = 0, NF = 1
_Cla1Task1:
MMOVI16
MAR1,#_X
MUI16TOF32 MR0, @_len
MNOP
MNOP
MMOV32
MR1, *MAR1[2]++
LOOP
MMOV32
MR2, *MAR1[2]++
MMINF32
MR1, MR2
MADDF32
MR0, MR0, #-1.0
MCMPF32
MR0 #0.0
MNOP
MNOP
MNOP
MBCNDD
LOOP, NEQ
MMOV32
@_Result, MR1
MNOP
MNOP
MSTOP
;
;
;
;
;
Start address
Length of the array
delay for MAR1 load
delay for MAR1 load
MR1 = X0
;
;
;
;
MR2 = next element
MR1 = MAX(MR1, MR2)
Decrememt the counter
Set/clear flags for MBCNDD
;
;
;
;
;
Branch
Always
Always
Always
End of
if not equal to zero
executed
executed
executed
task
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
715
Instruction Set
See also
716
www.ti.com
MMAXF32 MRa, MRb
MMAXF32 MRa, #16FHi
MMINF32 MRa, #16FHi
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Instruction Set
www.ti.com
MMINF32 MRa, #16FHi 32-Bit Floating-Point Minimum
Operands
MRa
floating-point source/destination register (MR0 to MR3)
#16FHi
A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floatingpoint value. The low 16-bits of the mantissa are assumed to be all 0.
Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1001 0100 00aa
Description
Compare MRa with the floating-point value represented by the immediate operand. If the
immediate value is smaller, then load it into MRa.
if(MRa > #16FHi:0) MRa = #16FHi:0;
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler will accept either a hex or float as the immediate
value. That is, -1.5 can be represented as #-1.5 or #0xBFC0.
Special cases for the output from the MMINF32 operation:
• NaN output will be converted to infinity
• A denormalized output will be converted to positive zero.
Flags
This instruction modifies the following flags in the MSTF register:
Flag
TF
ZF
NF
LUF
LVF
Modified
No
Yes
Yes
No
No
The ZF and NF flags are configured on the result of the operation, not the result stored
in the destination register.
if(MRa == #16FHi:0)
{ZF=1; NF=0;}
if(MRa > #16FHi:0) {ZF=0; NF=0;}
if(MRa < #16FHi:0) {ZF=0; NF=1;}
Pipeline
This is a single-cycle instruction.
Example
MMOVIZ
MMOVIZ
MMOVIZ
MMINF32
MMINF32
MMINF32
MMINF32
See also
MR0,
MR1,
MR2,
MR0,
MR1,
MR2,
MR2,
#5.0
#4.0
#-1.5
#5.5
#2.5
#-1.0
#-1.5
;
;
;
;
;
;
;
MR0
MR1
MR2
MR0
MR1
MR2
MR2
= 5.0
= 4.0
= -1.5
= 5.0,
= 2.5,
= -1.5,
= -1.5,
(0x40A00000)
(0x40800000)
(0xBFC00000)
ZF = 0, NF =
ZF = 0, NF =
ZF = 0, NF =
ZF = 1, NF =
1
0
1
0
MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, MRb
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
717
Instruction Set
www.ti.com
MMOV16 MARx, MRa, #16I Load the Auxiliary Register with MRa + 16-bit Immediate Value
Operands
Opcode
MARx
Auxiliary register MAR0 or MAR1
MRa
CLA Floating-point register (MR0 to MR3)
#16I
16-bit immediate value
LSW: IIII IIII IIII IIII (opcode of MMOV16 MAR0, MRa, #16I)
MSW: 0111 1111 1101 00AA
LSW: IIII IIII IIII IIII (opcode of MMOV16 MAR1, MRa, #16I)
MSW: 0111 1111 1111 00AA
Description
Load the auxiliary register, MAR0 or MAR1, with MRa(15:0) + 16-bit immediate value.
Refer to the pipeline section for important information regarding this instruction.
MARx = MRa(15:0) + #16I;
Flags
Pipeline
This instruction does not modify flags in the MSTF register:
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
This is a single-cycle instruction. The load of MAR0 or MAR1 will occur in the EXE
phase of the pipeline. Any post increment of MAR0 or MAR1 using indirect addressing
will occur in the D2 phase of the pipeline. Therefore the following applies when loading
the auxiliary registers:
• I1 and I2
The two instructions following MMOV16 will use MAR0/MAR1 before the update
occurs. Thus these two instructions will use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to postincrement addressing occur in the D2 phase. Thus I3 cannot use the auxiliary
register or there will be a conflict. In the case of a conflict, the update due to addressmode post increment will win and the auxiliary register will not be updated with #_X.
• I4
Starting with the 4th instruction MAR0 or MAR1 will be the new value loaded with
MMOVI16.
; Assume MAR0 is 50, MR0 is 10, and #_X is 20
MMOV16 MAR0,
;
;
;
;
;
I1
I2
I3
I4
I5
; Load MAR0 with address
Will use the old value of
Will use the old value of
Cannot use MAR0
Will use the new value of
of X (20) + MR0 (10)
MAR0 (50)
MAR0 (50)
MAR0 (30)
Table 6-16. Pipeline Activity For MMOV16 MARx, MRa , #16I
718
Instruction
F1
F2
D1
D2
R1
R2
MMOV16 MAR0, MR0, #_X
MMOV16
I1
I1
MMOV16
I2
I2
I1
MMOV16
I3
I3
I2
I1
MMOV16
I4
I4
I3
I2
I1
MMOV16
I5
I5
I4
I3
I2
I1
MMOV16
I6
I6
I5
I4
I3
I2
I1
E
W
MMOV1
6
Control Law Accelerator (CLA) SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Instruction Set
www.ti.com
Example 1
; Calculate an offset into a sin/cos table
;
_Cla1Task1:
MMOV32 MR0,@_rad
; MR0 =
MMOV32 MR1,@_TABLE_SIZEDivTwoPi ; MR1 =
MMPYF32 MR1,MR0,MR1
; MR1 =
|| MMOV32 MR2,@_TABLE_MASK
; MR2 =
MF32TOI32 MR3,MR1
; MR3 =
MAND32 MR3,MR3,MR2
; MR3 =
MLSL32 MR3,#1
; MR3 =
||
Example 2
rad
TABLE_SIZE/(2*Pi)
rad* TABLE_SIZE/(2*Pi)
TABLE_MASK
K=int(rad*TABLE_SIZE/(2*Pi))
K & TABLE_MASK
K * 2
MMOV16 MAR0,MR3,#_Cos0
MFRACF32 MR1,MR1
MMOV32 MR0,@_TwoPiDivTABLE_SIZE
MMPYF32 MR1,MR1,MR0
MMOV32 MR0,@_Coef3
;
;
;
;
MAR0 K*2+addr of table.Cos0
I1
I2
I3
MMOV32 MR2,*MAR0[#-64]++
...
...
MSTOP ; end of task
; MR2 = *MAR0, MAR0 += (-64)
; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task will go back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC will trigger this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
;
T_sys = 1/200MHz = 5ns
;
T_adc = 4*T_sys = 20ns
; The ADC will take 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register may be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg
0, N
.loop
MNOP
;I1 - I28 Wait till I36 to read result
.eval
N + 1, N
.break
N = 28
.endloop
MMOVZ16
MR0, @_ConversionCount
;I29 Current Conversion
MMOV16
MAR1, MR0, #_VoltageCLA
;I30 Next array location
MUI16TOF32 MR0, MR0
;I31 Convert count to float32
MADDF32
MR0, MR0, #1.0
;I32 Add 1 to conversion count
MCMPF32
MR0, #NUM_DATA_POINTS.0
;I33 Compare count to max
MF32TOUI16 MR0, MR0
;I34 Convert count to Uint16
MNOP
;I35 Wait till I36 to read result
MMOVZ16
MR2, @_AdcaResultRegs.ADCRESULT1
;I36 Read ADCRESULT1
MMOV16
*MAR1, MR2
; Store ADCRESULT1
MBCNDD
_RestartCount, GEQ
; If count >= NUM_DATA_POINTS
MMOVIZ
MR1, #0.0
; Always executed: MR1=0
MNOP
MNOP
MMOV16
@_ConversionCount, MR0
; If branch not taken
MSTOP
; store current count
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
719
Instruction Set
www.ti.com
_RestartCount
MMOV16
@_ConversionCount, MR1
MSTOP
; If branch taken, restart count
; end of task
; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ
MR0, #0.0
MMOV16
@_ConversionCount, MR0
MSTOP
_ClaT8End:
See also
720
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Instruction Set
www.ti.com
MMOV16 MARx, mem16 Load MAR1 with 16-bit Value
Operands
Opcode
MARx
CLA auxiliary register MAR0 or MAR1
mem16
16-bit destination memory accessed using one of the available addressing modes
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 MAR0, mem16)
MSW: 0111 0110 0000 addr
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 MAR1, mem16)
MSW: 0111 0110 0100 addr
Description
Load MAR0 or MAR1 with the 16-bit value pointed to by mem16. Refer to the pipeline
section for important information regarding this instruction.
MAR1 = [mem16];
Flags
Pipeline
No flags MSTF flags are affected.
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
This is a single-cycle instruction. The load of MAR0 or MAR1 will occur in the EXE
phase of the pipeline. Any post increment of MAR0 or MAR1 using indirect addressing
will occur in the D2 phase of the pipeline. Therefore the following applies when loading
the auxiliary registers:
• I1 and I2
The two instructions following MMOV16 will use MAR0/MAR1 before the update
occurs. Thus these two instructions will use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to postincrement addressing occur in the D2 phase. Thus I3 cannot use the auxiliary
register or there will be a conflict. In the case of a conflict, the update due to addressmode post increment will win send the auxiliary register will not be updated with #_X.
• I4
Starting with the 4th instruction MAR0 or MAR1 will be the new value loaded with
MMOV16.
; Assume MAR0 is 50 and @_X is 20
MMOV16 MAR0,
;
;
;
;
;
;
Load MAR0 with the contents of X (20)
I1 Will use the old value of MAR0 (50)
I2 Will use the old value of MAR0 (50)
I3 Cannot use MAR0
I4 Will use the new value of MAR0 (20)
I5
Table 6-17. Pipeline Activity For MMOV16 MAR0/MAR1, mem16
Instruction
F1
MMOV16 MAR0, @_X
MMOV16
F2
D1
D2
I1
I1
MMOV16
I2
I2
I1
MMOV16
I3
I3
I2
I1
MMOV16
I4
I4
I3
I2
I1
MMOV16
I5
I5
I4
I3
I2
I1
MMOV16
I6
I6
I5
I4
I3
I2
I1
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
R1
R2
E
W
MMOV1
6
Control Law Accelerator (CLA) 721
Instruction Set
Example
www.ti.com
; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task will go back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC will trigger this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
;
T_sys = 1/200MHz = 5ns
;
T_adc = 4*T_sys = 20ns
; The ADC will take 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register may be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg
0, N
.loop
MNOP
;I1 - I28 Wait till I36 to read result
.eval
N + 1, N
.break
N = 28
.endloop
MMOVZ16
MR0, @_ConversionCount
;I29 Current Conversion
MMOV16
MAR1, MR0, #_VoltageCLA
;I30 Next array location
MUI16TOF32 MR0, MR0
;I31 Convert count to float32
MADDF32
MR0, MR0, #1.0
;I32 Add 1 to conversion count
MCMPF32
MR0, #NUM_DATA_POINTS.0
;I33 Compare count to max
MF32TOUI16 MR0, MR0
;I34 Convert count to Uint16
MNOP
;I35 Wait till I36 to read result
MMOVZ16
MR2, @_AdcaResultRegs.ADCRESULT1
;I36 Read ADCRESULT1
MMOV16
*MAR1, MR2
; Store ADCRESULT1
MBCNDD
_RestartCount, GEQ
; If count >= NUM_DATA_POINTS
MMOVIZ
MR1, #0.0
; Always executed: MR1=0
MNOP
MNOP
MMOV16
@_ConversionCount, MR0
; If branch not taken
MSTOP
; store current count
_RestartCount
MMOV16
@_ConversionCount, MR1
MSTOP
; If branch taken, restart count
; end of task
; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ
MR0, #0.0
MMOV16
@_ConversionCount, MR0
MSTOP
_ClaT8End:
See also
722
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Instruction Set
www.ti.com
MMOV16 mem16, MARx Move 16-Bit Auxiliary Register Contents to Memory
Operands
Opcode
mem16
16-bit destination memory accessed using one of the available addressing modes
MARx
CLA auxiliary register MAR0 or MAR1
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 mem16, MAR0)
MSW: 0111 0110 1000 addr
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 mem16, MAR1)
MSW: 0111 0110 1100 addr
Description
Store the contents of MAR0 or MAR1 in the 16-bit memory location pointed to by
mem16.
[mem16] = MAR0;
Flags
Pipeline
No flags MSTF flags are affected.
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
This is a single-cycle instruction.
Example
See also
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
723
Instruction Set
www.ti.com
MMOV16 mem16, MRa Move 16-Bit Floating-Point Register Contents to Memory
Operands
mem16
16-bit destination memory accessed using one of the available addressing modes
MRa
CLA floating-point source register (MR0 to MR3)
Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 11aa addr
Description
Move 16-bit value from the lower 16-bits of the floating-point register (MRa(15:0)) to the
location pointed to by mem16.
[mem16] = MRa(15:0);
No flags MSTF flags are affected.
Flags
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
Pipeline
This is a single-cycle instruction.
Example
; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task will go back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC will trigger this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
;
T_sys = 1/200MHz = 5ns
;
T_adc = 4*T_sys = 20ns
; The ADC will take 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register may be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg
0, N
.loop
MNOP
;I1 - I28 Wait till I36 to read result
.eval
N + 1, N
.break
N = 28
.endloop
MMOVZ16
MR0, @_ConversionCount
;I29 Current Conversion
MMOV16
MAR1, MR0, #_VoltageCLA
;I30 Next array location
MUI16TOF32 MR0, MR0
;I31 Convert count to float32
MADDF32
MR0, MR0, #1.0
;I32 Add 1 to conversion count
MCMPF32
MR0, #NUM_DATA_POINTS.0
;I33 Compare count to max
MF32TOUI16 MR0, MR0
;I34 Convert count to Uint16
MNOP
;I35 Wait till I36 to read result
MMOVZ16
MR2, @_AdcaResultRegs.ADCRESULT1
;I36 Read ADCRESULT1
MMOV16
*MAR1, MR2
; Store ADCRESULT1
MBCNDD
_RestartCount, GEQ
; If count >= NUM_DATA_POINTS
MMOVIZ
MR1, #0.0
; Always executed: MR1=0
MNOP
MNOP
MMOV16
@_ConversionCount, MR0
; If branch not taken
MSTOP
; store current count
724
Control Law Accelerator (CLA)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Instruction Set
www.ti.com
_RestartCount
MMOV16
@_ConversionCount, MR1
MSTOP
; If branch taken, restart count
; end of task
; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ
MR0, #0.0
MMOV16
@_ConversionCount, MR0
MSTOP
_ClaT8End:
See also
MMOVIZ MRa, #16FHi
MMOVXI MRa, #16FLoHex
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Control Law Accelerator (CLA)
725
Instruction Set
www.ti.com
MMOV32 mem32, MRa Move 32-Bit Floating-Point Register Contents to Memory
Operands
MRa
floating-point register (MR0 to MR3)
mem32
32-bit destination memory accessed using one of the available addressing modes
Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 11aa addr
Description
Move from MRa to 32-bit memory location indicated by mem32.
[mem32] = MRa;
This instruction modifies the following flags in the MSTF register:
Flags
Flag
TF
ZF
NF
LUF
LVF
Modified
No
No
No
No
No
No flags affected.
Pipeline
This is a single-cycle instruction.
Example
; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating point arrays;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16
MAR0, #_X
; MAR0 points to X array
MMOVI16
MAR1, #_Y
; MAR1 points to Y array
MNOP
; Delay for MAR0, MAR1 load
MNOP
; Delay for MAR0, MAR1 load
; 485ns
485ns/8.333ns = 59 (round up)
59 – 1 = 58
Next decide which ADC pins to connect to each signal. This will be highly dependent on application board
layout. Once the pins are selected, determining the value of CHSEL is straightforward (see Table 10-6).
Table 10-6. Example Connections for Multiple Signal Sampling
Signal Name
ADC PIN
CHSEL Register Value
Signal 1
ADCINA5
5
Signal 2
ADCINA0
0
Signal 3
ADCINA3
3
Signal 4
ADCINA2
2
With the information tabulated, it is easy to generate the SOC configurations:
AdcaRegs.ADCSOC0CTL.bit.CHSEL =
AdcaRegs.ADCSOC0CTL.bit.ACQPS =
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL
AdcaRegs.ADCSOC1CTL.bit.CHSEL =
AdcaRegs.ADCSOC1CTL.bit.ACQPS =
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL
AdcaRegs.ADCSOC2CTL.bit.CHSEL =
AdcaRegs.ADCSOC2CTL.bit.ACQPS =
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL
AdcaRegs.ADCSOC3CTL.bit.CHSEL =
AdcaRegs.ADCSOC3CTL.bit.ACQPS =
AdcaRegs.ADCSOC3CTL.bit.TRIGSEL
5;
23;
= 3;
0;
88;
= 3;
3;
21;
= 3;
2;
58;
= 3;
//SOC0
//SOC0
//SOC0
//SOC1
//SOC1
//SOC1
//SOC2
//SOC2
//SOC2
//SOC3
//SOC3
//SOC3
will
will
will
will
will
will
will
will
will
will
will
will
convert ADCINA5
use sample duration
begin conversion on
convert ADCINA0
use sample duration
begin conversion on
convert ADCINA3
use sample duration
begin conversion on
convert ADCINA2
use sample duration
begin conversion on
of 24 SYSCLK cycles
CPU1 Timer 2
of 89 SYSCLK cycles
CPU1 Timer 2
of 22 SYSCLK cycles
CPU1 Timer 2
of 59 SYSCLK cycles
CPU1 Timer 2
As configured, when CPU1 Timer 2 generates an event, SOC0, SOC1, SOC2, and SOC3 will eventually
be sampled and converted, in that order. The conversion results for ACINA5 (Signal 1) will be in
ADCRESULT0. Similarly, The results for ADCINA0 (Signal 2), ADCINA3 (Signal 3), and ADCINA2 (Signal
4) will be in ADCRESULT1, ADCRESULT2, and ADCRESULT3, respectively.
NOTE: It is possible, but unlikely, that the ADC could begin converting SOC1, SOC2, or SOC3
before SOC0 depending on the position of the round-robin pointer when the CPU Timer
trigger is received. See ADC Conversion Priority to understand how the next SOC to be
converted is chosen.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Analog-to-Digital Converter (ADC)
1431
SOC Configuration Examples
www.ti.com
10.6.4 Software Triggering of SOCs
At any point, whether or not the SOCs have been configured to accept a specific trigger, a software trigger
can set the SOCs to be converted. This is accomplished by writing bits in the ADCSOCFRC1 register.
Software triggering of the previous example without waiting for the CPU1 Timer 2 to generate the trigger
could be accomplished by the statement:
AdcaRegs.ADCSOCFRC1.all = 0x000F;
//set SOC flags for SOC0 to SOC3
10.7 ADC Conversion Priority
When multiple SOC flags are set at the same time, one of two forms of priority determines the order in
which they are converted. The default priority method is round robin. In this scheme, no SOC has an
inherent higher priority than another. Priority depends on the round robin pointer (RRPOINTER). The
RRPOINTER reflected in the ADCSOCPRIORITYCTL register points to the last SOC converted. The
highest priority SOC is given to the next value greater than the RRPOINTER value, wrapping around back
to SOC0 after SOC15. At reset the value is 16 since 0 indicates a conversion has already occurred. When
RRPOINTER equals 16 the highest priority is given to SOC0. The RRPOINTER is reset by a device reset,
when the ADCCTL1.RESET bit is set, or when the SOCPRICTL register is written.
An example of the round robin priority method is given in Figure 10-4 .
1432
Analog-to-Digital Converter (ADC)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ADC Conversion Priority
www.ti.com
Figure 10-4. Round Robin Priority Example
A After reset, SOC0 is highest priority SOC ;
SOC7 receives trigger ;
SOC7 configured channel is converted
immediately .
A
SOC
15
SOC
3
SOC
12
RRPOINTER
(default = 16)
SOC
5
SOC
10
SOC
9
SOC
1
SOC
14
SOC
15
SOC
2
SOC
13
RRPOINTER
(value = 7)
SOC
4
SOC
10
D
SOC
15
SOC
10
SOC
1
SOC
6
SOC
15
RRPOINTER
(value = 12)
SOC
4
SOC
5
SOC
11
SOC
10
SOC
6
SOC
7
SOC
8
SOC
0
SOC
7
SOC
1
SOC
14
SOC
3
SOC
8
SOC
5
SOC
9
SOC
13
SOC
4
SOC
11
SOC
2
SOC
9
RRPOINTER
(value = 7)
E
SOC
0
SOC
14
SOC
12
SOC
3
SOC
7
SOC
8
SOC
1
SOC
2
SOC
12
SOC
6
SOC
9
SOC
0
SOC
7
SOC
13
SOC
5
SOC
11
SOC
8
SOC
14
SOC
3
SOC
12
SOC
6
C
SOC
0
SOC
4
SOC
11
E RRPOINTER changes to point to SOC 2;
SOC3 is now highest priority SOC .
SOC
15
SOC
2
SOC
13
D RRPOINTER changes to point to SOC 12;
SOC2 configured channel is now converted .
B
SOC
1
SOC
14
B RRPOINTER changes to point to SOC 7;
SOC8 is now highest priority SOC .
C SOC2 & SOC12 triggers rcvd . simultaneously ;
SOC12 is first on round robin wheel ;
SOC12 configured channel is converted while
SOC2 stays pending .
SOC
0
SOC
2
SOC
13
SOC
3
SOC
12
RRPOINTER
(value = 2)
SOC
4
SOC
5
SOC
11
SOC
10
SOC
6
SOC
9
SOC
8
SOC
7
The SOCPRIORITY field in the ADCSOCPRIORITYCTL register can be used to assign high priority from
a single to all of the SOCs. When configured as high priority, an SOC will interrupt the round robin wheel
after any current conversion completes and insert itself in as the next conversion. After its conversion
completes, the round robin wheel will continue where it was interrupted. If two high priority SOC’s are
triggered at the same time, the SOC with the lower number will take precedence.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Analog-to-Digital Converter (ADC)
1433
ADC Conversion Priority
www.ti.com
High priority mode is assigned first to SOC0, then in increasing numerical order. The value written in the
SOCPRIORITY field defines the first SOC that is not high priority. In other words, if a value of 4 is written
into SOCPRIORITY, then SOC0, SOC1, SOC2, and SOC3 are defined as high priority, with SOC0 the
highest.
An example using high priority SOC’s is given in Figure 10-5 .
Figure 10-5. High Priority Example
A
Example when SOCPRIORITY = 4
A
B
C
D
E
After reset, SOC4 is 1 st on round robin wheel ;
SOC7 receives trigger ;
SOC7 configured channel is converted immediately .
High Priority
SOC
0
RRPOINTER changes to point to SOC 7;
SOC8 is now 1 st on round robin wheel .
SOC
1
SOC2 & SOC12 triggers rcvd . simultaneously ;
SOC2 interrupts round robin wheel and SOC 2 configured
channel is converted while SOC 12 stays pending .
SOC
2
SOC
3
High Priority
SOC
0
SOC
1
SOC
2
SOC
3
SOC
4
SOC
13
RRPOINTER
(default = 16)
SOC
8
SOC
13
RRPOINTER
(value = 7)
SOC
1
SOC
2
SOC
3
SOC
1
SOC
2
SOC
8
SOC
10
D
SOC
4
SOC
15
High Priority
SOC
0
SOC
7
SOC
12
SOC
12
SOC
8
Analog-to-Digital Converter (ADC)
SOC
0
SOC
1
SOC
2
SOC
3
SOC
5
RRPOINTER
(value = 7)
SOC
7
SOC
12
SOC
8
SOC
15
High Priority
SOC
7
RRPOINTER
(value = 7)
SOC
10
SOC
13
E
SOC
5
SOC
4
SOC
9
SOC
6
SOC
11
SOC
6
SOC
11
SOC
3
SOC
10
SOC
14
SOC
9
SOC
14
SOC
13
SOC
15
High Priority
SOC
6
SOC
11
SOC
0
C
SOC
14
SOC
7
SOC
12
SOC
11
SOC
5
SOC
5
SOC
6
RRPOINTER changes to point to SOC 12;
SOC13 is now 1st on round robin wheel .
SOC
15
SOC
4
SOC
14
RRPOINTER stays pointing to 7;
SOC12 configured channel is now converted .
B
1434
SOC
15
SOC
10
SOC
4
SOC
9
SOC
5
SOC
14
SOC
6
SOC
13
RRPOINTER
(value = 12)
SOC
7
SOC
12
SOC
9
SOC
8
SOC
11
SOC
10
SOC
9
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Burst Mode
www.ti.com
10.8 Burst Mode
Burst mode allows a single trigger to walk through the round-robin SOCs one or more at a time. Setting
the bit BURSTEN in the ADCBURSTCTL register configures the ADC wrapper for burst mode. This
causes the TRIGSEL field to be ignored, but only for SOCs that are configured for round-robin operation
(not high priority). Instead of the TRIGSEL field, all round-robin SOCs are triggered based on the
BURSTTRIG field in the ADCBURSTCTL register. Upon reception of the burst trigger, the ADC wrapper
will not set all round-robin SOCs to be converted, but only (ADCBURSTCTL.BURSTSIZE + 1) SOCs. The
first SOC to be set will be that with the highest priority based on the round-robin pointer, and subsequent
SOCs will be set until BURSTSIZE SOCs have been set.
NOTE: When configuring the ADC for burst mode, the user is responsible for ensuring that each
burst of conversions is allowed to complete before the next burst trigger is received.
10.8.1 Burst Mode Example
Burst mode can be used to sample a different set of signals on every other trigger. In the following
example, ADCIN7 and ADCIN5 are converted on the first trigger from CPU1 Timer 2 and every other
trigger thereafter. ADCIN2 and ACIN3 are converted on the second trigger from CPU1 Timer 2 and every
other trigger thereafter. All signals are converted with 20 SYSCLK cycle wide acquisition windows, but
different durations could be configured for each SOC as desired.
AdcaRegs.BURSTCTL.BURSTEN = 1;
AdcaRegs.BURSTCTL.BURSTTRIG = 3;
AdcaRegs.BURSTCTL.BURSTSIZE = 1;
//Enable ADC burst mode
//CPU1 Timer 2 will trigger burst of conversions
//conversion bursts are 1 + 1 = 2 conversions long
AdcaRegs.SOCPRICTL.bit.SOCPRIORITY = 12;
//SOC0 to SOC11 are high priority
AdcaRegs.ADCSOC12CTL.bit.CHSEL
AdcaRegs.ADCSOC12CTL.bit.ACQPS
AdcaRegs.ADCSOC13CTL.bit.CHSEL
AdcaRegs.ADCSOC13CTL.bit.ACQPS
AdcaRegs.ADCSOC14CTL.bit.CHSEL
AdcaRegs.ADCSOC14CTL.bit.ACQPS
AdcaRegs.ADCSOC15CTL.bit.CHSEL
AdcaRegs.ADCSOC15CTL.bit.ACQPS
//SOC12
//SOC12
//SOC13
//SOC13
//SOC14
//SOC14
//SOC15
//SOC15
=
=
=
=
=
=
=
=
7;
19;
5;
19;
2;
19;
3;
19;
will
will
will
will
will
will
will
will
convert ADCINA7
use sample duration
convert ADCINA5
use sample duration
convert ADCINA2
use sample duration
convert ADCINA3
use sample duration
of 20 SYSCLK cycles
of 20 SYSCLK cycles
of 20 SYSCLK cycles
of 20 SYSCLK cycles
When the first CPU1 Timer 2 trigger is received, SOC12 and SOC13 will be converted immediately if the
ADC is idle. If the ADC is busy, SOC12 and SOC13 will be converted once their SOCs gain priority. The
results for SOC12 and SOC13 will be in ADCRESULT12 and ADCRESULT13, respectively. After SOC13
completes, the round robin pointer will give highest priority to SOC14. Because of this, when the next
CPU1 Timer 2 trigger is received, SOC14 and SOC15 will be set as pending and eventually be converted.
The results for SOC14 and SOC15 will be in ADCRESULT14 and ADCRESULT15, respectively.
Subsequent triggers will continue to toggle between converting SOC12 and SOC13, and converting
SOC14 and SOC15.
While the above example toggles between two sets of conversions, three or more different sets of
conversions could be achieved using a similar approach.
10.8.2 Burst Mode Priority Example
An example of priority resolution using burst mode and high-priority SOCs is presented in Figure 10-6.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Analog-to-Digital Converter (ADC)
1435
Burst Mode
www.ti.com
Figure 10-6. Burst Priority Example
A
Example when SOCPRIORITY = 4, BURSTEN = 1, and
BURSTSIZE = 1
A
B
RRPOINTER changes to point to SOC5;
SOC6 is now 1st on round robin wheel.
SOC
1
C
BURSTTRIG & SOC1 triggers rcvd. simultaneously;
SOC1, SOC6, and SOC7 are set;
SOC1 interrupts round robin wheel and SOC1 configured
channel is converted while SOC6 and SOC7 stay pending.
SOC
2
D
RRPOINTER stays pointing to 5;
SOC6/SOC7 configured channels are now converted.
E
RRPOINTER changes to point to SOC7;
SOC8 is now 1st on round robin wheel, waiting for BURSTTRIG.
SOC
15
High
Priority
SOC
0
SOC
1
SOC
2
SOC
3
SOC
1
SOC
2
SOC
3
SOC
5
RRPOINTER
(value = 5)
SOC
1
SOC
2
SOC
8
SOC
15
SOC
5
RRPOINTER
(value = 5)
SOC
8
Analog-to-Digital Converter (ADC)
SOC
0
SOC
1
SOC
2
SOC
3
SOC
10
SOC
4
SOC
9
SOC
5
SOC
14
SOC
6
RRPOINTER
(value = 5)
SOC
13
SOC
7
SOC
12
SOC
8
SOC
15
High
Priority
SOC
7
SOC
12
SOC
10
SOC
15
E
SOC
4
SOC
7
SOC
8
SOC
11
SOC
6
SOC
11
RRPOINTER
(default = 16)
SOC
12
SOC
9
SOC
10
SOC
14
SOC
13
SOC
3
SOC
5
SOC
6
SOC
13
High
Priority
SOC
0
SOC
4
SOC
14
SOC
11
SOC
7
SOC
12
D
SOC
0
SOC
3
SOC
6
SOC
13
High
Priority
SOC
0
C
SOC
4
SOC
14
SOC
11
1436
High
Priority
After reset, SOC4 is 1st on round robin wheel;
BURSTTRIG trigger is received;
SOC4 & SOC5 are set and configured channels converted
immediately.
B
SOC
15
SOC
10
SOC
4
SOC
9
SOC
5
SOC
14
SOC
6
RRPOINTER
(value = 7)
SOC
13
SOC
7
SOC
12
SOC
9
SOC
8
SOC
11
SOC
10
SOC
9
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
EOC and Interrupt Operation
www.ti.com
10.9 EOC and Interrupt Operation
Each SOC has a corresponding end-of-conversion (EOC) signal. This EOC signal can be used to trigger
an ADC interrupt. The ADC can be configured to generate the EOC pulse at either the end of the
acquisition window or at the end of the voltage conversion. This is configured using the bit INTPULSEPOS
in the ADCCTL1 register. See Section 10.14, for exact EOC pulse location.
Each ADC module has 4 configurable ADC interrupts. These interrupts can be triggered by any of the 16
EOC signals. The flag bit for each ADCINT can be read directly to determine if the associated SOC is
complete or the interrupt can be passed on to the PIE.
NOTE: The ADCCTL1.ADCBSY bit being clear does not indicate that all conversions in a set of
SOCs have completed, only that the ADC is ready to process the next conversion. To
determine if a sequence of SOCs is complete, link an ADCINT flag to the last SOC in the
sequence and monitor that ADCINT flag.
Figure 10-7 shows a block diagram of the ADC interrupt structure.
Figure 10-7. ADC EOC Interrupts
INT4
INT3
INT2
INT1
INTSEL1N2.INT1SEL
ADCINT4 to PIE
INTSEL1N2.INT1E
INTSEL1N2.INT1CONT
EOC
0
1
2
EOC15:EOC0
ADCINT2 to PIE
1
15
ADCINT3 to PIE
0
1
Set
ADCINT1 to PIE
0
Latch
Clear
INTOVF
ADCINTFLGCLR.ADCINT1
ADC Sample
Generation
Logic
ADCINTFLG.ADCINT1
10.9.1 Interrupt Overflow
If the EOC signal would set a flag in the ADCINTFLG register, but that flag is already set, an interrupt
overflow occurs. By default, overflow interrupts will not be passed on to the PIE module. When an
overflow occurs on a given flag in the ADCINTFLG register, the corresponding flag in the ADCINOVF
register is set. This overflow flag is only used to detect that an overflow has occurred; it does not block
further interrupts from propagating to the PIE module.
When an ADC interrupt overflow could occur, the application should check the appropriate ADCINTOVF
flag inside the ISR or in the background loop and take appropriate action when an overflow is detected.
The following code snippet demonstrates how to check the ADCINOVF flag inside the ISR after attempting
to clear the ADCINT flag.
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
//clear INT1 flag for ADC-A
if(1 == AdcaRegs.ADCINTOVF.bit.ADCINT1)
//ADCINT overflow occurred
{
AdcaRegs.ADCINTOVFCLR.bit.ADCINT1 = 1 //Clear overflow flag
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Analog-to-Digital Converter (ADC)
1437
EOC and Interrupt Operation
www.ti.com
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1 //Re-clear ADCINT flag
}
10.9.2 Continue to Interrupt Mode
The INTxCONT bits in the ADCINTSEL1N2 and ADCINTSEL3N4 registers configure how interrupts are
handled when an ADCINTFLG has not yet been cleared from a prior interrupt. This mode is disabled by
default and additional overlapping interrupts will not be issued to the PIE. By activating this mode ADC
interrupts will always reach the PIE. The ADCINTOVF register will still be set if an interrupts occur while
ADCINTFLG is still set regardless of this configuration.
10.10 Post-Processing Blocks
Each ADC module contains four post-processing blocks (PPB). These blocks can be associated with any
of the 16 RESULT registers using the ADCPPBxCONFIG.CONFIG bit field. Each PPB can simultaneously
remove an offset associated with the ADCIN channel, subtract out a reference value, flag a zero-crossing
point, and flag a high or low compare limit. Furthermore, the zero-crossing and compare flags can trip a
PWM and/or generate an interrupt. A PPB is also capable of recording the delay between when the SOC
associated with the PPB is triggered and when it actually begins to be sampled. Figure 10-8 presents the
structure of each PPB. Subsequent sections explain the use of each submodule.
Figure 10-8. ADC PPB Block Diagram
ADC Post Processing Block
ADCEVTSEL.PPBxTRIPLO
ADCEVTSEL.PPBxTRIPHI
Delay Capture
ADCEVTSEL.PPBxZERO
SOC Control Signals
ADCEVTSTAT.PPBxTRIPLO
SOC
Start
Detect
SOC
Trigger
Detect
EVENTx
ADCEVTSTAT.PPBxTRIPHI
Latch
Latch
-
REQSTAMPx
DLYSTAMPx
ADCEVTSTAT.PPBxZERO
+
FREECOUNT
Zero Crossing Detection Logic
ADCPPBxOFFCAL
ADC Output
Detects when
ADCPPBxRESULT
changes sign
Offset Correction
with Saturation
INTx
-
+
Pulse
Threshold Compare
Saturate
ADCRESULTy
ADCPPBxTRIPHI
+
Pulse
-
Error/Bipolar Calculation
ADCPPBxOFFREF
-
+
Twos
Comp
Inv
+
ADCPPBxRESULT
ADCPPBxTRIPLO
-
Pulse
Enable
ADCPPBxCONFIG.TWOSCOMPEN
ADCEVTINTSEL.PPBxZERO
ADCEVTINTSEL.PPBxTRIPHI
ADCEVTINTSEL.PPBxTRIPLO
10.10.1 PPB Offset Correction
In many applications, external sensors and signal sources produce an offset. A global trimming of the
ADC offset is not enough to compensate for these offsets, which vary from channel to channel. The postprocessing block can remove these offsets with zero overhead, saving numerous cycles in tight control
loops.
1438
Analog-to-Digital Converter (ADC)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Post-Processing Blocks
www.ti.com
Offset correction is accomplished by first pointing the ADCPPBxCONFIG.CONFIG to the desired SOC,
then writing an offset correction value to the ADCPPBxOFFCAL.OFFCAL register. The post-processing
block will automatically add or subtract the value in the OFFCAL register from the raw conversion result
and store it in the ADCRESULT register. This addition/subtraction will saturate at 0 on the low end and
4095 on the high end.
NOTES:
• Writing a 0 to the OFFCAL register effectively disables the offset correction feature, passing the raw
result unchanged to the ADCRESULT register.
• It is possible to point multiple PPBs to the same SOC. In this case, the OFFCAL value that will actually
be applied will be that of the PPB with the highest number.
• In particular, care needs to be taken when using the PPB on SOC0, as all the PPB point to this SOC
by default. This may cause unintentional overwriting of offset correction of a lower numbered PPB by a
higher numbered PPB.
10.10.2 PPB Error Calculation
In many applications, an error from a setpoint or expected value must be computed from the digital output
of an ADC conversion. In other cases, a bipolar signal is necessary or convenient for control calculations.
The PPB can perform these function automatically, reducing the sample to output latency and reducing
software overhead.
Error calculation is accomplished by first pointing the ADCPPBxCONFIG.CONFIG to the desired SOC,
then writing a value to the ADCPPBxOFFCAL.OFFREF register. The post-processing block will
automatically subtract the value in the OFFREF register from the ADCRESULT value and store it in the
ADCPPBxRESULT register. This subtraction will produce a sign-extended 32-bit result. It is also possible
to selectively invert the calculated value before storing in the ADCPPBxRESULT register by setting the
TWOSCOMPEN bit in the ADCPPBxCONFIG register.
NOTES:
• Do not write a value larger than 12 bits to the OFFREF register.
• Since the PPBxRESULT register is unique for each PPB, it is possible to point multiple PPBs to the
same SOC and get different results for each PPB.
• Writing a 0 to the OFFREF register effectively disables the error calculation feature, passing the
ADCRESULT value unchanged to the ADCPPBxRESULT register.
10.10.3 PPB Limit Detection and Zero-Crossing Detection
Many applications perform a limit check against the ADC conversion results. The PPB can automatically
perform a check against a high and low limit or whenever ADCPPBxRESULT changes sign. Based on
these comparisons, it can generate a trip to the PWM and/or an interrupt automatically, lowering the
sample to ePWM latency and reducing software overhead. This functionality also enables safety
conscious applications to trip the ePWM based on an out-of-range ADC conversion without any CPU
intervention.
To enable this functionality, first point the ADCPPBxCONFIG.CONFIG to the desired SOC, then write a
value to one or both of the registers ADCPPBxTRIPHI.LIMITHI and ADCPPBxTRIPLO.LIMITLO
(zerocrossing detection does not require further configuration). Whenever these limits are exceeded, the
PPBxTRIPHI bit or PPBxTRIPLO bit will be set in the ADCEVTSTAT register. Note that the PPBxZERO
bit in the ADCEVTSTAT register is gated by EOC and not by the sign change in the ADCPPBxRESULT
register. The ADCEVTCLR register has corresponding bits to clear these event flags. The ADCEVTSEL
register has corresponding bits which allow the events to propagate through to the PWM. The
ADCINTSEL register has corresponding bits which allow the events to propagate through to the PIE.
One PIE interrupt is shared between all the PPBs for a given ADC module as shown in Figure 10-9.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Analog-to-Digital Converter (ADC)
1439
Post-Processing Blocks
www.ti.com
Figure 10-9. ADC PPB Interrupt Event
Post Processing Block1
EVENTx
ADCEVT1
INTx
Post Processing Block2
EVENTx
ADCEVT2
INTx
ADCEVTINT
Post Processing Block3
EVENTx
ADCEVT3
INTx
Post Processing Block4
EVENTx
ADCEVT4
INTx
NOTES:
• Zero-crossing and limit compare reference the ADCPPBxRESULT register. This will include any
correction applied by the OFFCAL and OFFREF registers. TRIPHI and TRIPLO do NOT perform a
signed comparison. It is recommended to leave OFFREF as 0 when using limit compare functionality.
• If different actions need to be taken for different PPB events from the same ADC module, then the
ADCEVTINT ISR will have to read the PPB event flags in the ADCEVTSTAT register to determine
which event caused the interrupt.
• If different ePWM trips need to be generated separately for high compare, low compare, and/or zerocrossing, this can be achieved by pointing multiple PPBs to the same SOC.
• The zero-crossing detect circuit considers a result of zero to be positive.
10.10.4 PPB Sample Delay Capture
When multiple control loops are running asynchronously on the same ADC, there is a chance that an ADC
request from two or more loops will collide, causing one of the samples to be delayed. This shows up as a
measurement error in the system. By knowing when this delay occurs and the amount of delay that has
occurred software can employ extrapolation techniques to reduce the error.
To this effect, each PPB has the field DLYSTAMP in the ADCPPBxSTAMP register. This field will contain
the number of SYSCLK cycles between when the associate SOC was triggered and when it began
converting.
This is achieved by having a global 12-bit free running counter based off of SYSCLK, which is in the field
FREECOUNT in the ADCCOUNTER register. When the trigger for the associated SOC arrives, the value
of this counter is loaded into the bit field ADCPPBxTRIPLO.REQSTAMP. When the actual sample window
for that SOC begins, the value in REQSTAMP is subtracted from the current FREECOUNT value and
stored in DLYSTAMP.
NOTE: If more than 4096 SYSCLK cycles elapse between the SOC trigger and the actual start of
the SOC acquisition, the FREECOUNT register may overflow more than once, leading to
incorrect DLYSTAMP value. Be cautious when using very slow conversions to prevent this
from happening.
1440
Analog-to-Digital Converter (ADC)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Opens/Shorts Detection Circuit (OSDETECT)
www.ti.com
NOTE: The sample delay capture will not function if the associated SOC is triggered via software. It
will, however, correctly record the delay if the software triggering of a different SOC causes
the SOC associated with the PPB to be delayed
10.11 Opens/Shorts Detection Circuit (OSDETECT)
The opens/shorts detection circuit (OSDETECT) can be used to detect pin faults in the system. The circuit
connects to the ADC input after the channel select multiplexer but before the S+H circuit as shown in
Figure 10-10.
NOTES:
• The divider resistance tolerances can vary widely, hence this feature should not be used to check for
conversion accuracy.
• Consult the device data manual for implementation and availability of analog input channels.
• Due to high drive impedance, a S+H duration much longer than the ADC minimum will be needed .
Figure 10-10. Opens/Shorts Detection Circuit
CHSEL
Opens/Shorts Detection Circuit
VDDA
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ADCIN0
ADCIN1
ADCIN2
ADCIN3
ADCIN4
ADCIN5
ADCIN6
ADCIN7
ADCIN8
ADCIN9
ADCIN10
ADCIN11
ADCIN12
ADCIN13
ADCIN014
ADCIN15
VSSA
S2
S1
5 kW
To S+H
7 kW
S3
VDDA
S4
VSSA
The circuit can be operated by writing a value to the DETECTCFG field in the ADCOSDETECT register.
This will cause the circuit to source a voltage onto the input during the S+H phase of any conversion. The
voltage and drive strength of the OSDETECT circuit for different DETECTCFG settings is given in
Table 10-7.
Table 10-7. DETECTCFG Settings
ADCOSDETECT.DETEC
TCFG
Source Voltage
S4
S3
S2
S1
Drive Impedance
0
Off
Open
Open
Open
Open
Open
1
Zero Scale
Closed
Open
Open
Closed
5K || 7K
2
Full Scale
Open
Closed
Closed
Open
5K || 7K
3
5/12 VDDA
Open
Closed
Open
Closed
5K || 7K
4
7/12 VDDA
Closed
Open
Closed
Open
5K || 7K
5
Zero Scale
Open
Open
Open
Closed
5K
6
Full Scale
Open
Open
Closed
Open
5K
7
Zero Scale
Closed
Open
Open
Open
7K
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Analog-to-Digital Converter (ADC)
1441
Opens/Shorts Detection Circuit (OSDETECT)
www.ti.com
10.11.1 Implementation
A representative circuit with the OSDETECT implementation consists of the signal source with series
resistance RS, shunt capacitor CP, the equivalent OSDETECT resistance ROSDETECT and voltage VOSDETECT is
shown in Figure 10-11 and can be used as a basis to calculate the signal level going in to the sampling
capacitor. ROSDETECT and VOSDETECT are the equivalent input resistance and voltage source contributed by
the OSDETECT circuit with values shown in Table 10-7 for the different configuration settings. Refer to
Figure 10-11 when deriving the input signal to S/H if signal source VS is driving while the OSDETECT
feature is enabled.
Figure 10-11. Input Circuit Equivalent with OSDETECT Enabled
RS
ADCINx
TO S/H
ROSDETECT
VS
CP
VOSDETECT
The input impedance RS and CP may be integral parts of the signal source or these could have been
implemented in the design to precondition the signal or to control signal settling time to meet S/H
requirements. The input path has to be considered when using the OSDETECT feature as this would
affect the conversion results. For instance, driving an input signal when this feature is enabled would
connect signal VS to the OSDETECT circuit through RS and affecting the ADC results. Larger CP values (in
the order greater than hundreds of pF) would require using higher ACQPS to ensure that signal at the
input has settled prior to conversion.
To
1.
2.
3.
enable the circuit:
Configure the ADC for conversion (for example, channel, SOC, ACQPS, prescaler, trigger, and so on).
Set up the ADCOSDETECT register for the desired voltage divider connection as shown in Table 10-7.
Initiate a conversion and inspect the conversion result.
Note: You must interpret the results based on what is driving on the input side and what are the values
of RS and CP. If the VS signal can be disconnected from the input pin, the circuit can be used to detect
open and shorted input pins as described in the following sections.
first then
10.11.2 Detecting an Open Input Pin
By cycling through the various OSDETECT settings, the input signal will be pulled towards the sourced
voltages. An input with good drive strength (pin not open) will be minimally affected. However, if the pin is
open, the sampled voltages will be close to the source voltages specified in Table 10-7.
10.11.3 Detecting a Shorted Input Pin
By cycling through the various OSDETECT settings, the input signal will be pulled towards the sourced
voltages. An input with finite drive strength (pin not shorted) will be pulled toward each sourced voltage.
However, if the pin is shorted, the signal will remain at the same voltage.
10.12 Power-Up Sequence
Upon device power-up or system level reset, the ADC will be powered down and disabled. When
powering up the ADC, use the following sequence:
1. Set the bit to enable the desired ADC clock in the PCLKCR13 register.
2. Set the desired ADC clock divider in the PRESCALE field of ADCCTL2.
3. Power up the ADC by setting the ADCPWDNZ bit in ADCCTL1.
4. Allow a delay before sampling. See the data manual for the necessary time.
1442
Analog-to-Digital Converter (ADC)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ADC Calibration
www.ti.com
If multiple ADCs are powered up simultaneously, steps 1 and step 3 can each be done for all ADCs in one
write instruction. Also, only one delay is necessary as long as it occurs after all the ADCs have begun
powering up.
10.13 ADC Calibration
During the fabrication and test process, Texas Instruments calibrates the gain, offset, and linearity of the
ADCs and the offset of the buffered DACs . These trim settings are embedded into TI reserved OTP
memory as part of C-callable functions.
• The Device_cal() function copies the trim values for ADC from OTP memory to their respective trim
registers.
• The trim functions in Device_cal() are callable in C2000ware as ADC_setOFFSETTRIM() and
ADC_setINLTRIM(). These functions fetch trim values from the TI reserved OTP memory source
locations where the values are stored during test process as well as the analog module register
destinations where the trim values are copied to.
Until the appropriate factory trim is loaded, the ADC (and other modules) will not be guaranteed to operate
within datasheet specifications. Similarly, if trim values other than the factory settings are placed into the
trim registers, the ADC (and other modules) will not be guaranteed to operate within datasheet
specifications.
The boot ROM will call the calibration functions, so trim values should be initially populated without user
intervention. However, if the trims are cleared due to a module reset or modified for some other reason,
then the user can call the calibration functions (defined in the headerfiles).
10.13.1 ADC Zero Offset Calibration
Zero offset error is defined as the difference from 0 that occurs when converting a voltage at VREFLO.
The zero offset error can be positive or negative. To correct this error, an adjustment of equal magnitude
and opposite polarity is written into the ADCOFFTRIM register. The value contained in this register will be
applied before the results are available in the ADC result registers. This operation is fully contained within
the ADC core, so the timing of the results will not be affected and the full dynamic range of the ADC will
be maintained for any trim value.
Using the GetAdcOffsetTrimOTP(Uint16) function, the ADCOFFTRIM register can be loaded with the
factory calibrated offset error correction. The user can modify the ADCOFFTRIM register to compensate
for additional offset error induced by the application environment if desired, but this is not typically
necessary to achieve datasheet specified performance.
NOTE: Regardless of the converter resolution, the size of each ADCOFFTRIM step is (VREFHIVREFLO)/65536.
Use the following procedure to re-calibrate the ADC offset in 12-bit, single-ended mode:
1. Set ADCOFFTRIM to +112 steps (0x70). This adds an artificial offset to account for negative offset that
may reside in the ADC core.
2. Perform some multiple of 16 conversions on VREFLO (internal connection), accumulating the results
(for example, 32*16 conversions = 512 conversions).
3. Divide the accumulated result by the multiple of 16 (for example, for 512 conversions, divide by 32).
4. Set ADCOFFTRIM to 112 – result from step 3.
10.14 ADC Timings
The process of converting an analog voltage to a digital value is broken down into an S+H phase and a
conversion phase. The ADC sample and hold circuits (S+H) are clocked by SYSCLK while the ADC
conversion process is clocked by ADCCLK. ADCCLK is generated by dividing down SYSCLK based on
the PRESCALE field in the ADCCTL2 register.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Analog-to-Digital Converter (ADC)
1443
ADC Timings
www.ti.com
The S+H duration is the value of the ACQPS field of the SOC being converted, plus one, times the
SYSCLK period. The user must ensure that this duration exceeds both 1 ADCCLK period and the
minimum S+H duration specified in the datasheet. The conversion time is approximately 10.5 ADCCLK
cycles. The exact conversion time is always a whole number of SYSCLK cycles. See the timing diagrams
and tables in Section 10.14.1 for exact timings.
10.14.1 ADC Timing Diagrams
The following diagrams show the ADC conversion timings for two SOCs given the following assumptions:
• SOC0 and SOC1 are configured to use the same trigger.
• No other SOCs are converting or pending when the trigger occurs.
• The round robin pointer is in a state that causes SOC0 to convert first.
• ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag
propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE
module).
The following parameters are identified in the timing diagrams:
1444Analog-to-Digital Converter (ADC)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ADC Timings
www.ti.com
Table 10-8. ADC Timing Parameters
PARAMETER
DESCRIPTION
The duration of the S+H window.
At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital
value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each
SOC, so tSH will not necessarily be the same for different SOCs.
tSH
Note: The value on the S+H capacitor will be captured approximately 5ns before the end of the S+H window
regardless of device clock settings.
The time from the end of the S+H window until the ADC results latch in the ADCRESULTx register.
tLAT
If the ADCRESULTx register is read before this time, the previous conversion results will be returned.
The time from the end of the S+H window until the S+H window for the next ADC conversion can begin. The
subsequent sample can start before the conversion results are latched.The subsequent sample can start before
the conversion results are latched.
tEOC
The time from the end of the S+H window until an ADCINT flag is set (if configured).
If the INTPULSEPOS bit in the ADCCTL1 register is set, tINT will coincide with the conversion results being
latched into the result register.
If the INTPULSEPOS bit is 0, tINT will coincide with the end of the S+H window. If tINT triggers a read of the ADC
result register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be taken
to ensure the read occurs after the results latch (otherwise, the previous results will be read).
tINT
If the INTPULSEPOS bit is 0, and the OFFSET field in the ADCINTCYCLE register is not 0, then there will be a
delay of OFFSET SYSCLK cycles before the ADCINT flag is set. This delay can be used to enter the ISR or
trigger the DMA at exactly the time the sample is ready.
Figure 10-12. ADC Timings for 12-bit Mode in Early Interrupt Mode
Sample n
Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1
ADC S+H
SOC0
SOC1
SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0
(old data)
ADCRESULT1
(old data)
Sample n
Sample n+1
ADCINTFLG.ADCINTx
tSH
tLAT
tEOC
tINT
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Analog-to-Digital Converter (ADC)
1445
ADC Timings
www.ti.com
Figure 10-13. ADC Timings for 12-bit Mode in Late Interrupt Mode
Sample n
Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1
ADC S+H
SOC0
SOC1
SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0
(old data)
ADCRESULT1
(old data)
Sample n
Sample n+1
ADCINTFLG.ADCINTx
tSH
tLAT
tEOC
tINT
Table 10-9. ADC Timings in 12-bit Mode (SYSCLK Cycles)
1446
ADCCTL2.
PRESCALE
Prescale Ratio
tEOC
tLAT
tINT
(Early)
tINT
(Late)
0
1
11
13
0
11
2
2
21
23
0
21
3
2.5
26
28
0
26
4
3
31
34
0
31
5
3.5
36
39
0
36
6
4
41
44
0
41
7
4.5
46
49
0
46
8
5
51
55
0
51
9
5.5
56
60
0
56
10
6
61
65
0
61
11
6.5
66
70
0
66
12
7
71
76
0
71
13
7.5
76
81
0
76
14
8
81
86
0
81
15
8.5
86
91
0
86
Analog-to-Digital Converter (ADC)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Additional Information
www.ti.com
10.15 Additional Information
The following sections contain additional practical information.
10.15.1 Ensuring Synchronous Operation
For best performance, all ADCs on the device should be operated synchronously. The device datasheet
specifies the performance in both synchronous and asynchronous mode for those parameters which differ
between the modes of operation.
To ensure synchronous operation, all ADCs on the device should operate in lockstep. This is
accomplished by writing configurations to all ADCs that cause the sampling and conversion phases of all
ADCs to be exactly aligned. The easiest way to accomplish this is to write identical values to the SOC
configurations for each ADC for trigger select and ACQPS (S+H duration).
10.15.1.1 Basic Synchronous Operation
The below example configures two SOCs each on ADCA and ADCB with identical trigger select and
ACQPS values. This will result in synchronous operation between ADCA and ADCB. For devices with
more than two ADCs, the same principles can be used to synchronize all the ADCs.
Example: Basic Synchronous Operation
AdcaRegs.ADCSOC0CTL.bit.CHSEL =
AdcaRegs.ADCSOC0CTL.bit.ACQPS =
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL
AdcbRegs.ADCSOC0CTL.bit.CHSEL =
AdcbRegs.ADCSOC0CTL.bit.ACQPS =
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL
4;
19;
= 10;
0;
19;
= 10;
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
will
will
will
will
will
will
convert ADCINA4
use sample duration
begin conversion on
convert ADCINB0
use sample duration
begin conversion on
AdcaRegs.ADCSOC1CTL.bit.CHSEL =
AdcaRegs.ADCSOC1CTL.bit.ACQPS =
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL
AdcbRegs.ADCSOC1CTL.bit.CHSEL =
AdcbRegs.ADCSOC1CTL.bit.ACQPS =
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL
4;
30;
= 10;
1;
30;
= 10;
//SOC1
//SOC1
//SOC1
//SOC1
//SOC1
//SOC1
will
will
will
will
will
will
convert ADCINA4
use sample duration
begin conversion on
convert ADCINB1
use sample duration
begin conversion on
of 20 SYSCLK cycles
ePWM3 SOCB
of 20 SYSCLK cycles
ePWM3 SOCB
of 31 SYSCLK cycles
ePWM3 SOCB
of 31 SYSCLK cycles
ePWM3 SOCB
Figure 10-14. Example: Basic Synchronous Operation
ePWM3B
Trigger
ADC A
SOC0 - S+H
SOC0 - Conversion
SOC1 - S+H
SOC1 - Conversion
ADC B
SOC0 - S+H
SOC0 - Conversion
SOC1 - S+H
SOC1 - Conversion
Several things should be noted from Figure 10-14. First, while the ACQPS values must be the same for
SOCs with the same number, different ACQPS values can be used for SOCs with different numbers.
Because of this, synchronous operation does not require a single global S+H time, but instead only
channels sampled simultaneously require identical S+H durations. Another important point from this
example is that any channel select value can be used for any SOC. Finally, this example assumes roundrobin operation. If high priority SOCs are to be used, the priority must be configured the same on all
ADCs.
10.15.1.2 Synchronous Operation with Multiple Trigger Sources
As long as each set of SOCs has identical trigger select and ACQPS settings, multiple trigger sources can
be used while still achieving synchronous operation.
The below example demonstrates synchronous operation between ADCA and ADCB while using three
SOCs and two trigger sources. Figure 10-15 demonstrates that any combination of relative trigger timings
still results in synchronous operation.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Analog-to-Digital Converter (ADC)
1447
Additional Information
www.ti.com
Example: Synchronous Operation With Multiple Trigger Sources
AdcaRegs.ADCSOC0CTL.bit.CHSEL =
AdcaRegs.ADCSOC0CTL.bit.ACQPS =
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL
AdcbRegs.ADCSOC0CTL.bit.CHSEL =
AdcbRegs.ADCSOC0CTL.bit.ACQPS =
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL
4;
19;
= 10;
0;
19;
= 10;
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
will
will
will
will
will
will
convert ADCINA4
use sample duration
begin conversion on
convert ADCINB0
use sample duration
begin conversion on
AdcaRegs.ADCSOC1CTL.bit.CHSEL =
AdcaRegs.ADCSOC1CTL.bit.ACQPS =
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL
AdcbRegs.ADCSOC1CTL.bit.CHSEL =
AdcbRegs.ADCSOC1CTL.bit.ACQPS =
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL
4;
30;
= 10;
1;
30;
= 10;
//SOC1
//SOC1
//SOC1
//SOC1
//SOC1
//SOC1
will
will
will
will
will
will
convert ADCINA4
use sample duration
begin conversion on
convert ADCINB1
use sample duration
begin conversion on
AdcaRegs.ADCSOC2CTL.bit.CHSEL =
AdcaRegs.ADCSOC2CTL.bit.ACQPS =
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL
AdcbRegs.ADCSOC2CTL.bit.CHSEL =
AdcbRegs.ADCSOC2CTL.bit.ACQPS =
AdcbRegs.ADCSOC2CTL.bit.TRIGSEL
0;
19;
= 2;
2;
19;
= 2;
//SOC2
//SOC2
//SOC2
//SOC2
//SOC2
//SOC2
will
will
will
will
will
will
convert ADCINA0
use sample duration
begin conversion on
convert ADCINB2
use sample duration
begin conversion on
of 20 SYSCLK cycles
ePWM3 SOCB
of 20 SYSCLK cycles
ePWM3 SOCB
of 31 SYSCLK cycles
ePWM3 SOCB
of 31 SYSCLK cycles
ePWM3 SOCB
of 31 SYSCLK cycles
CPU Timer1
of 31 SYSCLK cycles
CPU Timer1
Figure 10-15. Example: Synchronous Operation with Multiple Trigger Sources
ePWM3B
Trigger
CPU1 Timer 1
Trigger
ADC A
SOC0 - S+H
SOC0 - Conversion
SOC1 - S+H
SOC1 - Conversion
SOC2 - S+H
SOC2 - Conversion
ADC B
SOC0 - S+H
SOC0 - Conversion
SOC1 - S+H
SOC1 - Conversion
SOC2 - S+H
SOC2 - Conversion
ePWM3B
Trigger
CPU1 Timer 1
Trigger
ADC A
SOC0 - S+H
SOC0 - Conversion
SOC1 - S+H
SOC1 - Conversion
SOC2 - S+H
SOC2 - Conversion
ADC B
SOC0 - S+H
SOC0 - Conversion
SOC1 - S+H
SOC1 - Conversion
SOC2 - S+H
SOC2 - Conversion
CPU1 Timer 1
Trigger
ePWM3B
Trigger
ADC A
SOC2 - S+H
SOC2 - Conversion
SOC0 - S+H
SOC0 - Conversion
SOC1 - S+H
SOC1 - Conversion
ADC B
SOC2 - S+H
SOC2 - Conversion
SOC0 - S+H
SOC0 - Conversion
SOC1 - S+H
SOC1 - Conversion
Note that any trigger source that can be selected in the TRIGSEL field can be used except for software
triggering. There is no way to issue the software triggers for all ADCs simultaneously, so it will likely result
in asynchronous operation. ADCINT1 or ADCINT2 can also be used as a trigger as long as the
ADCINTSOCSEL1 and ADCINTSOCSEL2 registers are configured identically for all ADCs and software
triggering is not used to start the chain of conversions.
10.15.1.3 Synchronous Operation with Uneven SOC Numbers
If only one trigger source is used, one ADC can use more SOCs than the other ADCs while still operating
synchronously.
1448
Analog-to-Digital Converter (ADC)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Additional Information
www.ti.com
Example: Synchronous Operation With Uneven SOC Numbers
AdcaRegs.ADCSOC0CTL.bit.CHSEL =
AdcaRegs.ADCSOC0CTL.bit.ACQPS =
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL
AdcbRegs.ADCSOC0CTL.bit.CHSEL =
AdcbRegs.ADCSOC0CTL.bit.ACQPS =
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL
4;
19;
= 10;
0;
19;
= 10;
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
will
will
will
will
will
will
convert ADCINA4
use sample duration
begin conversion on
convert ADCINB0
use sample duration
begin conversion on
AdcaRegs.ADCSOC1CTL.bit.CHSEL =
AdcaRegs.ADCSOC1CTL.bit.ACQPS =
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL
AdcbRegs.ADCSOC1CTL.bit.CHSEL =
AdcbRegs.ADCSOC1CTL.bit.ACQPS =
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL
4;
30;
= 10;
1;
30;
= 10;
//SOC1
//SOC1
//SOC1
//SOC1
//SOC1
//SOC1
will
will
will
will
will
will
convert ADCINA4
use sample duration
begin conversion on
convert ADCINB1
use sample duration
begin conversion on
of 20 SYSCLK cycles
ePWM3 SOCB
of 20 SYSCLK cycles
ePWM3 SOCB
of 31 SYSCLK cycles
ePWM3 SOCB
of 31 SYSCLK cycles
ePWM3 SOCB
AdcaRegs.ADCSOC2CTL.bit.CHSEL = 0;
//SOC2 will convert ADCINA0
AdcaRegs.ADCSOC2CTL.bit.ACQPS = 19;
//SOC2 will use sample duration of 31 SYSCLK cycles
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 10; //SOC2 will begin conversion on ePWM3 SOCB
Figure 10-16. Example: Synchronous Operation with Uneven SOC Numbers
ePWM3B
Trigger
ADC A
SOC0 - S+H
SOC0 - Conversion
SOC1 - S+H
SOC1 - Conversion
ADC B
SOC0 - S+H
SOC0 - Conversion
SOC1 - S+H
SOC1 - Conversion
SOC2 - S+H
SOC2 - Conversion
Note that if the trigger comes again before all SOCs have completed their conversions, ADCB will begin
converting immediately on SOC0 while ADCA will not start converting SOC0 again until SOC2 is
complete. This will result in asynchronous operation, so care must be taken to not overflow the trigger.
Figure 10-17. Example: Asynchronous Operation with Uneven SOC Numbers – Trigger Overflow
ePWM3B
Trigger
ADC A
SOC0 - S+H
SOC0 - Conversion
SOC1 - S+H
SOC1 - Conversion
ADC B
SOC0 - S+H
SOC0 - Conversion
SOC1 - S+H
SOC1 - Conversion
SOC2 - S+H
SOC0 - S+H
SOC2 - Conversion
SOC0 - Conversion
SOC0 - S+H
SOC1 - S+H
...
SOC1 - Conversion
10.15.1.4 Non-overlapping Conversions
If conversion timings can be guaranteed to not overlap by the user, then it is not necessary to configure all
SOCs identically on all ADCs to achieve performance equivalent to synchronous operation. For example,
if the two ADC triggers in a system come from two ePWM sources which are always 180 degrees out-ofphase, then SOC0 could be used for both ADCA and ADCB with different trigger sources and different
ACQPS values.
Example: Operation with Non-overlapping
Conversions
//ePWM3 SOCA and SOCB are 180 degrees out of
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 4;
//SOC0
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 19;
//SOC0
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 10; //SOC0
AdcbRegs.ADCSOC0CTL.bit.CHSEL = 0;
//SOC0
AdcbRegs.ADCSOC0CTL.bit.ACQPS = 19;
//SOC0
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 9; //SOC0
phase
will convert ADCINA4
will use sample duration
will begin conversion on
will convert ADCINB0
will use sample duration
will begin conversion on
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
of 20 SYSCLK cycles
ePWM3 SOCB
of 20 SYSCLK cycles
ePWM3 SOCA
Analog-to-Digital Converter (ADC)
1449
Additional Information
www.ti.com
Figure 10-18. Example: Synchronous Equivalent Operation with Non-Overlapping Conversions
ePWM3B
Trigger
ADC A
ePWM3A
Trigger
SOC0 - S+H
ePWM3B
Trigger
SOC0 - Conversion
ePWM3A
Trigger
SOC0 - S+H
ADC B
SOC0 - S+H
SOC0 - Conversion
SOC0 - Conversion
SOC0 - S+H
SOC0 - Conversion
10.15.2 Choosing an Acquisition Window Duration
For correct operation, the input signal to the ADC must be allowed adequate time to charge the sample
and hold capacitor, Ch. Typically, the S+H duration is chosen such that the sampling capacitor will be
charged to within ½ LSB or ¼ LSB of the final value, depending on the tolerable settling error.
An approximation of the required settling time can be determined using an RC settling model. The time
constant for the model is given by the equation:
W
Rs Ron · Ch Rs · Cs Cp
And the number of time constants needed is given by the equation:
k
§
2n
In ¨
¨ settling error
©
·
¸
¸
¹
CP ·
§C
In ¨ S
¸
CH
©
¹
So the total S+H time should be set to at least:
t = k·•
Where the following parameters are provided by the ADC input model in the device data manual:
• n = ADC resolution (in bits)
• RON = ADC sampling switch resistance (in Ohms)
• CH = ADC sampling capacitor (in pF)
• Cp = ADC channel parasitic input capacitance (in pF)
And the following parameters are dependent on the application design:
• settling error = tolerable settling error (in LSBs)
• Rs = ADC driving circuit source impedance (in Ohms)
• CS = capacitance on ADC input pin (in pF)
For example, assuming the following parameters:
• n = 12-bits
• RON = 500Ω
• CH = 12.5pF
• Cp = 12.7pF
• settling error = ¼ LSB
• Rs = 180Ω
• Cs = 150pF
The time constant would be calculated as:
W
180
500
· 12.5 pF
180 · (150 pF
12.7 pF )
8.5ns
29.3ns
37.8ns
And the number of required time constants would be:
1450
Analog-to-Digital Converter (ADC)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Additional Information
www.ti.com
k
§ 212 ·
¸
In ¨
¨ 0.25 ¸
©
¹
§ 150 pF 12.7 pF ·
In ¨
¸
12.5 pF
©
¹
9.70
2.57
7.13
So the S+H time should be set to at least:
37.8ns · 7.13 = 270ns
If SYSCLK = 100 MHz, then each SYSCLK is 10ns. S+H duration should be 270ns/10ns = 27.0 SYSCLKs
so ACQPS for this input should be set to at least CEILING(27.0) – 1 = 26.
While this gives a rough estimate of the required acquisition window, a better method would be to setup a
circuit with the ADC input model, a model of the source impedance/capacitance, and any board parasitics
in SPICE (or similar software) and simulate to verify that the sampling capacitor settles to the desired
accuracy.
NOTE: The device datasheet will specify a minimum ADC S+H window duration. Do not use an
ACQPS value that gives a duration less than this specification.
10.15.3 Achieving Simultaneous Sampling
While each ADC does not have dual S+H circuits, it is easy to achieve simultaneous sampling. This is
accomplished by setting the SOC triggers on two or more ADC modules to use the same trigger source.
The example below demonstrates x3 simultaneous sampling based on an ePWM3 event. ADCINA3,
ADCINB5, and ADCIND2 are sampled. An acquisition window of 20 SYSCLK cycles is used, but different
durations are possible.
AdcaRegs.ADCSOC0CTL.bit.CHSEL =
AdcaRegs.ADCSOC0CTL.bit.ACQPS =
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL
AdcbRegs.ADCSOC0CTL.bit.CHSEL =
AdcbRegs.ADCSOC0CTL.bit.ACQPS =
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL
AdcdRegs.ADCSOC0CTL.bit.CHSEL =
AdcdRegs.ADCSOC0CTL.bit.ACQPS =
AdcdRegs.ADCSOC0CTL.bit.TRIGSEL
3;
19;
= 10;
5;
19;
= 10;
2;
19;
= 10;
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
//SOC0
will
will
will
will
will
will
will
will
will
convert ADCINA3
use sample duration
begin conversion on
convert ADCINB5
use sample duration
begin conversion on
convert ADCIND2
use sample duration
begin conversion on
of 20 SYSCLK cycles
ePWM3 SOCB
of 20 SYSCLK cycles
ePWM3 SOCB
of 20 SYSCLK cycles
ePWM3 SOCB
When the ePWM3 trigger is received, all three ADCs will begin converting in parallel immediately. All
results will be in the ADCRESULT0 register for each ADC. Note that this assumes that all ADCs are idle
when the trigger is received. If one or more ADCs is busy, the samples will not happen at exactly the
same time.
10.15.4 Designing an External Reference Circuit
Figure 10-19 shows the basic organization of the external voltage reference generation circuitry. A single
reference voltage generation source should be shared by all ADC modules. This will minimize reference
voltage mismatch between ADC modules. The reference voltage should then be buffered by a precision
op-amp with good bandwidth and low output impedance before being driven into the reference pin. A
capacitor between the high and low reference pins should be placed on the PCB as close to the pins as
practical to help absorb high frequency currents. A series resistor (typically Voltage B
1
Voltage A < Voltage B
0
12.4 Reference DAC
Each reference 12-bit DAC can be configured to drive a reference voltage into the negative input of its
respective comparator. The reference 12-bit DAC output is internal only and cannot be observed
externally.
Two sets of DACxVAL registers, DACxVALA and DACxVALS, are present for each reference 12-bit DAC.
DACxVALA is a read-only register that actively controls the reference 12-bit DAC value. DACxVALS is a
writable shadow register that loads into DACxVALA either immediately or synchronized with the next
EPWMSYNCPER event. The high reference 12-bit DAC (DACH) can optionally source its DACHVALA
value from the ramp generator instead of DACHVALS.
1634
Comparator Subsystem (CMPSS)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Reference DAC
www.ti.com
The operating range of the reference 12-bit DAC is bounded by DACREF and VSSA. The high voltage
reference is VDDA by default, but it can be configured to be VDAC. The reference 12-bit DAC is illustrated
in Figure 12-3.
Figure 12-3. Reference DAC Block Diagram
COMPDACCTL[SELREF]
VDDA 0
DACREF
VDAC 1
DACHVALA
12-bit DACOUTH
DACH To COMPH
DACLVALA
12-bit DACOUTL
DACL To COMPL
VSSA
The ideal output of the reference 12-bit DAC can be calculated as follows:
Figure 12-4. Output Voltage Calculation
DACOUT =
DACVALA * DACREF
4096
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS)
1635
Ramp Generator
www.ti.com
12.5 Ramp Generator
This section discusses the characteristic s of the ramp generator and its behavior.
12.5.1 Ramp Generator Overview
The ramp generator produces a falling-ramp input for the high reference 12-bit DAC when selected. In this
mode, the reference 12-bit DAC uses the most significant 12 bits of the RAMPSTS countdown register as
its input. The low 4 bits of the RAMPSTS countdown register effectively act as a prescale for the fallingramp rate configurable with RAMPDECVALA.
The ramp generator is enabled by setting DACSOURCE = 1. On setting DACSOURCE = 1, the value of
RAMPSTS is loaded from RAMPMAXREFS and the register remains static until the selected
EPWMSYNCPER signal is received. After receiving the selected EPWMSYNCPER signal, the value of
RAMPDECVALA is subtracted from RAMPSTS on every subsequent SYSCLK cycle.
To prevent the subtraction from commencing a SYSCLK cycle after a EPWMSYNCPER event, the
RAMPDLYA register which serves as a delay counter can be used to hold off the RAMPSTS subtraction.
On receiving a EPWMSYNCPER event, the value of RAMPDLYA is decremented by one on every
SYSCLK cycle until the register reaches zero. The RAMPSTS subtraction will only begin when
RAMPDLYA is zero.
12.5.2 Ramp Generator Behavior
The ramp generator makes state changes on every rising edge of DACSOURCE, EPWMSYNCPER and
COMPHSTS.
On the rising edge of DACSOURCE, RAMPMAXREFA, RAMPDECVALA and RAMPDLYA are loaded with
their shadow registers. RAMPSTS is loaded with RAMPMAXREFS.
On the rising edge of the selected EPWMSYNCPER, RAMPMAXREFA, RAMPDECVALA and
RAMPDLYA are loaded with their shadow registers. RAMPSTS is loaded with RAMPMAXREFS and starts
decrementing when RAMPDLYA counter reaches zero.
On the rising edge of COMPHSTS with RAMPLOADSEL = 1, RAMPMAXREFA, RAMPDECVALA and
RAMPDLYA are loaded with their shadow registers. RAMPSTS is loaded with RAMPMAXREFS and stops
decrementing.
On the rising edge of COMPHSTS with RAMPLOADSEL = 0, RAMPSTS is loaded with RAMPMAXREFA
and stops decrementing.
Additionally, if the value of RAMPSTS reaches zero, the RAMPSTS register will remain static at zero until
the next EPWMSYNCPER is received. These state changes are illustrated in the ramp generator block
diagram in Figure 12-5.
1636
Comparator Subsystem (CMPSS)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Ramp Generator
www.ti.com
Figure 12-5. Ramp Generator Block Diagram
12.5.3 Ramp Generator Behavior at Corner Cases
Since the ramp generator makes state changes on every rising edge of EPWMSYNCPER and
COMPHSTS, the following behavior can be expected on instances when these two events occur
simultaneously or very close together.
Case 1: COMPHSTS rising edge occurs one or more cycles before EPWMSYNCPER rising edge.
RAMPSTS stops decrementing on COMPHSTS rising edge event. RAMPSTS starts decrementing on
EPWMSYNCPER rising edge event when RAMPDLYA reaches 0.
Case 2: COMPHSTS rising edge occurs simultaneously as EPWMSYNCPER rising edge.
COMPHSTS rising edge event takes precedence and RAMPSTS stops decrementing. EPWMSYNCPER
rising edge event is ignored and does not start decrementing RAMPSTS when RAMPDLYA reaches 0.
Case 3: COMPHSTS rising edge occurs one or more cycles after EPWMSYNCPER rising edge but before
RAMPDLYA reaches 0.
RAMPSTS does not decrement when RAMPDLYA reaches 0.
Case 4: COMPHSTS rising edge occurs simultaneously as RAMPDLYA reaches 0 from EPWMSYNCPER
rising edge.
RAMPSTS does not decrement.
This behavior is also illustrated in Figure 12-6.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS)
1637
Digital Filter
www.ti.com
Figure 12-6. Ramp Generator Behavior
EPWMSYNCPER
0xFFFF
RAMPMAXREFS
RAMPMAXREFS
RAMPSTS
RAMPMAXREFS
CMPINxP
RAMPMAXREFS
0x0000
COMPHSTS
12.6 Digital Filter
The digital filter works on a window of FIFO samples (SAMPWIN) taken from the input. The filter output
resolves to the majority value of the sample window, where majority is defined by the threshold (THRESH)
value. If the majority threshold is not satisfied, the filter output remains unchanged.
For proper operation, the value of THRESH must be greater than SAMPWIN / 2 and less than or equal to
SAMPWIN.
A prescale function (CLKPRESCALE) determines the filter sampling rate, where the filter FIFO captures
one sample every prescale system clocks. Old data from the FIFO is discarded.
Note that for SAMPWIN, THRESH and CLKPRESCALE, the internal number used by the digital filter is +
1 in all cases. In essence, samples = SAMPWIN + 1, threshold = THRESH + 1 and prescale =
CLKPRESCALE + 1.
A conceptual model of the digital filter is shown in Figure 12-7.
Figure 12-7. Digital Filter Behavior
Digital Filter
Filter Input
Data Latch
32-bit FIFO
0 1 2 3 4 5 6 7 8 9 «... 28 29 30 31
Filter Output
[Data Discard]
SAMPWIN = 9
CLKPRESCALE
SYSCLK
1638
Comparator Subsystem (CMPSS)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Digital Filter
www.ti.com
Equivalent C code of the filter implementation is shown below:
if (FILTER_OUTPUT == 0) {
if (Num_1s_in_SAMPWIN >= THRESH) {
FILTER_OUTPUT = 1;
}
}
else {
if (Num_0s_in_SAMPWIN >= THRESH) {
FILTER_OUTPUT = 0;
}
}
12.6.1 Filter Initialization Sequence
To ensure proper operation of the digital filter, the following initialization sequence is recommended:
1. Configure and enable the comparator for operation
2. Configure the digital filter parameters for operation
• Set SAMPWIN for the number of samples to monitor in the FIFO window
• Set THRESH for the threshold required for majority qualification
• Set CLKPRESCALE for the digital filter clock prescale value
3. Initialize the sample values in the digital FIFO window by setting FILINIT
4. Clear COMPSTS latch via COMPSTSCLR if the latched path is desired
5. Configure the CTRIP and CTRIPOUT signal paths
6. If desired, configure the ePWM and GPIO modules to accept the filtered signals
12.7 Using the CMPSS
12.7.1 LATCHCLR and EPWMSYNCPER Signals
The LATCHCLR signal holds the latch output in reset (0). It is activated in software using xLATCHCLR(x=
“H” or “L”). It can also be activated by EPWMSYNCPER when xSYNCCLREN(x= "H" or "L") is set.
EPWMSYNCPER comes from the Time-Base submodule of the EPWM. For a detailed description of how
this signal is generated, refer to the Time-Base submodule chapter of the EPWM.
The EPWMSYNCPER signal that loads DACxVALA when COMPDACCTL [SWLOADSEL] = 1 is a level
trigger load. If TBCTR and TBPRD of the EPWM are both 0, EPWMSYNCPER will be held at level high
and DACxVALA will be loaded immediately from DACxVALS irrespective of the value of COMPDACCTL
[SWLOADSEL]. Due to this, it is recommended to configure the EPWM first before setting COMPDACCTL
[SWLOADSEL] to 1.
NOTE: The name of the sync signal that the CMPSS receives from the EPWM has been updated
from PWMSYNC to EPWMSYNCPER (SYNCPER/PWMSYNCPER/EPWMxSYNCPER) to
avoid confusion with the other EPWM sync signals EPWMSYNCI and EPWMSYNCO. For a
description of what these signals are, see the EPWM chapter.
12.7.2 Synchronizer, Digital Filter and Latch Delays
The synchronization block adds a delay of 1-2 sysclks. If the digital filter is bypassed (all filter settings are
0), the digital filter will add a delay of 2 sysclks. The latch adds 1 sysclk delay.
12.7.3 Calibrating the CMPSS
The CMPSS has two sources of offset errors: comparator offset error and compdac offset error. In the
data manual, the comparator offset error is referred to as Input referred offset error and compdac offset
error is referred to as Static offset error. See the device specific data manual for their values.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS)
1639
Using the CMPSS
www.ti.com
If both inputs of the comparator are driven from a pin, only the comparator offset error applies. However if
the inverting input of the comparator is driven from the compdac, then only the compdac offset error
applies. This is because the compdac offset error includes comparator offset error.
Due to the offset errors, it is recommended that the CMPSS be calibrated to ensure trips happen at the
expected levels. The flow below outlines how the calibration can be performed if the inverting input of the
comparator is driven from the compdac.
Notes before calibration:
1. A static DC signal is required on the non-inverting input of the comparator.
2. Hysteresis should be disabled for calibration. It can be re-enabled after calibration is complete.
3. A noisy input can make calibration difficult so it is recommended to use the latch with non-zero filter
settings depending on how noisy the signal on the non-inverting input is.
This approach sweeps down the compdac:
1. Set the starting compdac value to max, 0xFFF.
• Optional: Instead of setting the starting compdac value to max, it can be set to Vtarget + Static
offset error + Margin. Where Vtarget is the approximate DC voltage on the non-inverting input,
Static offset error is the compdac offset error specification and Margin is some amount of guard
band. This can lead to a faster calibration but will only work if Vtarget is known. Alternatively if
Vtarget is unknown, the ADC can be used to convert it.
2. Decrement compdac value by 1.
3. Wait for compdac to settle.
4. Clear latch.
5. Wait for possible latch set.
6. If latch is set, trip code is found exit.
• Optional: The trip code can be double checked by:
I. Increasing compdac value by 1.
II. Clear latch.
III. Wait for possible latch set.
IV. Latch should be unset.
7. If latch is unset, go back to step 2 and repeat.
It is also possible to calibrate the CMPSS if both inputs of the comparator are driven from a pin. For this
case, the flow stays the same but the voltage on the inverting pin of the comparator is swept externally.
12.7.4 Enabling and Disabling the CMPSS Clock
If the clock to the CMPSS module is disabled while the comparator is active, the following behavior can be
expected:
• The comparator remains unaffected and will continue to trip from voltages on its inputs.
• If the reference 12-bit DAC is driving the negative input of the comparator, the voltage on the negative
input remains static and unaffected but DACVALA would no longer be updated from the ramp
generator or DACVALS.
• The ramp generator, synchronize block and digital filter freeze on their current states.
Enabling the clock to the CMPSS restores it to the state before the clock was disabled.
1640
Comparator Subsystem (CMPSS)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CMPSS Registers
www.ti.com
12.8 CMPSS Registers
This section describes the CMPSS Registers.
12.8.1 CMPSS Base Addresses
Table 12-1. CMPSS Base Address Table
Device Registers
Register Name
Start Address
End Address
0x0000_5C80
0x0000_5C9F
Cmpss1Regs
CMPSS_REGS
Cmpss2Regs
CMPSS_REGS
0x0000_5CA0
0x0000_5CBF
Cmpss3Regs
CMPSS_REGS
0x0000_5CC0
0x0000_5CDF
Cmpss4Regs
CMPSS_REGS
0x0000_5CE0
0x0000_5CFF
Cmpss5Regs
CMPSS_REGS
0x0000_5D00
0x0000_5D1F
Cmpss6Regs
CMPSS_REGS
0x0000_5D20
0x0000_5D3F
Cmpss7Regs
CMPSS_REGS
0x0000_5D40
0x0000_5D5F
Cmpss8Regs
CMPSS_REGS
0x0000_5D60
0x0000_5D7F
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS)
1641
CMPSS Registers
www.ti.com
12.8.2 CMPSS_REGS Registers
Table 12-2 lists the CMPSS_REGS registers. All register offset addresses not listed in Table 12-2 should
be considered as reserved locations and the register contents should not be modified.
Table 12-2. CMPSS_REGS Registers
Offset
Acronym
Register Name
Write Protection
0h
COMPCTL
CMPSS Comparator Control Register
EALLOW
Section
Go
1h
COMPHYSCTL
CMPSS Comparator Hysteresis Control Register
EALLOW
Go
2h
COMPSTS
CMPSS Comparator Status Register
3h
COMPSTSCLR
CMPSS Comparator Status Clear Register
EALLOW
Go
4h
COMPDACCTL
CMPSS DAC Control Register
EALLOW
Go
6h
DACHVALS
CMPSS High DAC Value Shadow Register
Go
7h
DACHVALA
CMPSS High DAC Value Active Register
Go
8h
RAMPMAXREFA
CMPSS Ramp Max Reference Active Register
Go
Ah
RAMPMAXREFS
CMPSS Ramp Max Reference Shadow Register
Go
Ch
RAMPDECVALA
CMPSS Ramp Decrement Value Active Register
Go
Eh
RAMPDECVALS
CMPSS Ramp Decrement Value Shadow
Register
Go
10h
RAMPSTS
CMPSS Ramp Status Register
Go
12h
DACLVALS
CMPSS Low DAC Value Shadow Register
Go
13h
DACLVALA
CMPSS Low DAC Value Active Register
Go
14h
RAMPDLYA
CMPSS Ramp Delay Active Register
Go
15h
RAMPDLYS
CMPSS Ramp Delay Shadow Register
16h
CTRIPLFILCTL
CTRIPL Filter Control Register
EALLOW
Go
17h
CTRIPLFILCLKCTL
CTRIPL Filter Clock Control Register
EALLOW
Go
18h
CTRIPHFILCTL
CTRIPH Filter Control Register
EALLOW
Go
19h
CTRIPHFILCLKCTL
CTRIPH Filter Clock Control Register
EALLOW
Go
1Ah
COMPLOCK
CMPSS Lock Register
EALLOW
Go
Go
Go
Complex bit access types are encoded to fit into small table cells. Table 12-3 shows the codes that are
used for access types in this section.
Table 12-3. CMPSS_REGS Access Type Codes
Access Type
Code
Description
R
R
Read
R-0
R
-0
Read
Returns 0s
W
W
Write
W1S
W
1S
Write
1 to set
WSonce
W
Sonce
Write
Set once
Read Type
Write Type
Reset or Default Value
-n
Value after reset or the default
value
Register Array Variables
1642
Comparator Subsystem (CMPSS)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CMPSS Registers
www.ti.com
Table 12-3. CMPSS_REGS Access Type
Codes (continued)
Access Type
Code
Description
i,j,k,l,m,n
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y
When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS)
1643
CMPSS Registers
www.ti.com
12.8.2.1 COMPCTL Register (Offset = 0h) [reset = 0h]
COMPCTL is shown in Figure 12-8 and described in Table 12-4.
Return to the Summary Table.
CMPSS Comparator Control Register
Figure 12-8. COMPCTL Register
15
COMPDACE
14
ASYNCLEN
13
12
CTRIPOUTLSEL
R/W-0h
R/W-0h
R/W-0h
7
RESERVED
6
ASYNCHEN
5
4
CTRIPOUTHSEL
R-0h
R/W-0h
R/W-0h
11
CTRIPLSEL
10
9
COMPLINV
R/W-0h
R/W-0h
3
CTRIPHSEL
2
1
COMPHINV
R/W-0h
R/W-0h
8
COMPLSOUR
CE
R/W-0h
0
COMPHSOUR
CE
R/W-0h
Table 12-4. COMPCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
COMPDACE
R/W
0h
Comparator/DAC enable.
0 Comparator/DAC disabled
1 Comparator/DAC enabled
Reset type: SYSRSn
14
ASYNCLEN
R/W
0h
Low comparator asynchronous path enable. Allows asynchronous
comparator output to feed into OR gate with latched digital filter
signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3.
0 Asynchronous comparator output does not feed into OR gate with
latched digital filter output
1 Asynchronous comparator output feeds into OR gate with latched
digital filter output
Reset type: SYSRSn
13-12
CTRIPOUTLSEL
R/W
0h
Low comparator CTRIPOUTL source select.
0 Asynchronous comparator output drives CTRIPOUTL
1 Synchronous comparator output drives CTRIPOUTL
2 Output of digital filter drives CTRIPOUTL
3 Latched output of digital filter drives CTRIPOUTL
Reset type: SYSRSn
11-10
CTRIPLSEL
R/W
0h
Low comparator CTRIPL source select.
0 Asynchronous comparator output drives CTRIPL
1 Synchronous comparator output drives CTRIPL
2 Output of digital filter drives CTRIPL
3 Latched output of digital filter drives CTRIPL
Reset type: SYSRSn
9
COMPLINV
R/W
0h
Low comparator output invert.
0 Output of comparator is not inverted
1 Output of comparator is inverted
Reset type: SYSRSn
8
COMPLSOURCE
R/W
0h
Low comparator input source.
0 Inverting input of comparator driven by internal DAC
1 Inverting input of comparator driven through external pin
Reset type: SYSRSn
7
1644
RESERVED
Comparator Subsystem (CMPSS)
R
0h
Reserved
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CMPSS Registers
www.ti.com
Table 12-4. COMPCTL Register Field Descriptions (continued)
Bit
6
Field
Type
Reset
Description
ASYNCHEN
R/W
0h
High comparator asynchronous path enable. Allows asynchronous
comparator output to feed into OR gate with latched digital filter
signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3.
0 Asynchronous comparator output does not feed into OR gate with
latched digital filter output
1 Asynchronous comparator output feeds into OR gate with latched
digital filter output
Reset type: SYSRSn
5-4
CTRIPOUTHSEL
R/W
0h
High comparator CTRIPOUTH source select.
0 Asynchronous comparator output drives CTRIPOUTH
1 Synchronous comparator output drives CTRIPOUTH
2 Output of digital filter drives CTRIPOUTH
3 Latched output of digital filter drives CTRIPOUTH
Reset type: SYSRSn
3-2
CTRIPHSEL
R/W
0h
High comparator CTRIPH source select.
0 Asynchronous comparator output drives CTRIPH
1 Synchronous comparator output drives CTRIPH
2 Output of digital filter drives CTRIPH
3 Latched output of digital filter drives CTRIPH
Reset type: SYSRSn
1
COMPHINV
R/W
0h
High comparator output invert.
0 Output of comparator is not inverted
1 Output of comparator is inverted
Reset type: SYSRSn
0
COMPHSOURCE
R/W
0h
High comparator input source.
0 Inverting input of comparator driven by internal DAC
1 Inverting input of comparator driven through external pin
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS)
1645
CMPSS Registers
www.ti.com
12.8.2.2 COMPHYSCTL Register (Offset = 1h) [reset = 0h]
COMPHYSCTL is shown in Figure 12-9 and described in Table 12-5.
Return to the Summary Table.
CMPSS Comparator Hysteresis Control Register
Figure 12-9. COMPHYSCTL Register
15
14
13
12
11
10
9
8
3
2
1
COMPHYS
R/W-0h
0
RESERVED
R-0h
7
6
5
RESERVED
R-0h
4
Table 12-5. COMPHYSCTL Register Field Descriptions
Field
Type
Reset
Description
15-3
Bit
RESERVED
R
0h
Reserved
2-0
COMPHYS
R/W
0h
Comparator hysteresis. Sets the amount of hysteresis on the
comparator inputs.
0 None
1 Set to typical hysteresis
2 Set to 2x of typical hysteresis
3 Set to 3x of typical hysteresis
4 Set to 4x of typical hysteresis
Reset type: SYSRSn
1646
Comparator Subsystem (CMPSS)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CMPSS Registers
www.ti.com
12.8.2.3 COMPSTS Register (Offset = 2h) [reset = 0h]
COMPSTS is shown in Figure 12-10 and described in Table 12-6.
Return to the Summary Table.
CMPSS Comparator Status Register
Figure 12-10. COMPSTS Register
15
14
13
12
11
10
9
COMPLLATCH
R-0h
8
COMPLSTS
R-0h
4
3
2
1
COMPHLATCH
R-0h
0
COMPHSTS
R-0h
RESERVED
R-0h
7
6
5
RESERVED
R-0h
Table 12-6. COMPSTS Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
9
COMPLLATCH
R
0h
Latched value of low comparator digital filter output
Reset type: SYSRSn
8
COMPLSTS
R
0h
Low comparator digital filter output
Reset type: SYSRSn
7-2
RESERVED
R
0h
Reserved
1
COMPHLATCH
R
0h
Latched value of high comparator digital filter output
Reset type: SYSRSn
0
COMPHSTS
R
0h
High comparator digital filter output
Reset type: SYSRSn
15-10
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS)
1647
CMPSS Registers
www.ti.com
12.8.2.4 COMPSTSCLR Register (Offset = 3h) [reset = 0h]
COMPSTSCLR is shown in Figure 12-11 and described in Table 12-7.
Return to the Summary Table.
CMPSS Comparator Status Clear Register
Figure 12-11. COMPSTSCLR Register
15
14
13
RESERVED
R-0h
12
11
10
LSYNCCLREN
R/W-0h
9
LLATCHCLR
R-0/W1S-0h
8
RESERVED
R-0h
7
6
5
RESERVED
R-0h
4
3
2
HSYNCCLREN
R/W-0h
1
HLATCHCLR
R-0/W1S-0h
0
RESERVED
R-0h
Table 12-7. COMPSTSCLR Register Field Descriptions
Bit
15-11
10
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
LSYNCCLREN
R/W
0h
Low comparator latch EPWMSYNCPER clear. Enable
EPWMSYNCPER reset of low comparator digital filter output latch
COMPSTS[COMPLLATCH].
0 EPWMSYNCPER will not reset latch
1 EPWMSYNCPER will reset latch
Reset type: SYSRSn
9
LLATCHCLR
R-0/W1S
0h
Low comparator latch software clear. Perform software reset of low
comparator digital filter output latch COMPSTS[COMPLLATCH].
Reads always return 0.
0 No effect
1 Generate a single pulse of latch reset signal for
COMPSTS[COMPLLATCH]
Reset type: SYSRSn
8-3
2
RESERVED
R
0h
Reserved
HSYNCCLREN
R/W
0h
High comparator latch EPWMSYNCPER clear. Enable
EPWMSYNCPER reset of high comparator digital filter output latch
COMPSTS[COMPHLATCH].
0 EPWMSYNCPER will not reset latch
1 EPWMSYNCPER will reset latch
Reset type: SYSRSn
1
HLATCHCLR
R-0/W1S
0h
High comparator latch software clear. Perform software reset of high
comparator digital filter output latch COMPSTS[COMPHLATCH].
Reads always return 0.
0 No effect
1 Generate a single pulse of latch reset signal for
COMPSTS[COMPHLATCH]
Reset type: SYSRSn
0
1648
RESERVED
Comparator Subsystem (CMPSS)
R
0h
Reserved
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CMPSS Registers
www.ti.com
12.8.2.5 COMPDACCTL Register (Offset = 4h) [reset = 0h]
COMPDACCTL is shown in Figure 12-12 and described in Table 12-8.
Return to the Summary Table.
CMPSS DAC Control Register
Figure 12-12. COMPDACCTL Register
15
14
13
12
11
10
9
8
2
1
RAMPSOURCE
0
DACSOURCE
R/W-0h
R/W-0h
FREESOFT
R/W-0h
7
SWLOADSEL
R/W-0h
6
RAMPLOADSE
L
R/W-0h
RESERVED
R-0h
5
SELREF
4
3
R/W-0h
Table 12-8. COMPDACCTL Register Field Descriptions
Bit
15-14
Field
Type
Reset
Description
FREESOFT
R/W
0h
Free-run or software-run emulation behavior. Behavior of the ramp
generator during emulation suspend.
00b Ramp generator stops immediately during emulation suspend
01b Ramp generator completes current ramp and stops at next
EPWMSYNCPER during emulation suspend
1Xb Ramp generator runs freely
Reset type: SYSRSn
13-8
7
RESERVED
R
0h
Reserved
SWLOADSEL
R/W
0h
Software load select. Determines whether DACxVALA is updated
from DACxVALS on SYSCLK or EPWMSYNCPER.
0 DACxVALA is updated from DACxVALS on SYSCLK
1 DACxVALA is updated from DACxVALS on EPWMSYNCPER
Reset type: SYSRSn
6
RAMPLOADSEL
R/W
0h
Ramp load select. Determines whether RAMPSTS is updated from
RAMPMAXREFA or RAMPMAXREFS when
COMPSTS[COMPHSTS] is triggered.
0 RAMPSTS is loaded from RAMPMAXREFA
1 RAMPSTS is loaded from RAMPMAXREFS
Reset type: SYSRSn
5
SELREF
R/W
0h
DAC reference select. Determines which voltage supply is used as
the reference for the internal comparator DACs.
0 VDDA is the voltage reference for the DAC
1 VDAC is the voltage reference for the DAC
Reset type: SYSRSn
4-1
RAMPSOURCE
R/W
0h
Ramp generator source select. Determines which EPWMSYNCPER
signal is used within the CMPSS module.
Where n represents the maximum number of EPWMSYNCPER
signals available on the device:
0 EPWM1SYNCPER
1 EPWM2SYNCPER
2 EPWM3SYNCPER
...
n-1 EPWMnSYNCPER
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS)
1649
CMPSS Registers
www.ti.com
Table 12-8. COMPDACCTL Register Field Descriptions (continued)
Bit
0
Field
Type
Reset
Description
DACSOURCE
R/W
0h
DAC source select. Determines whether DACHVALA is updated
from DACHVALS or from the ramp generator.
0 DACHVALA is updated from DACHVALS
1 DACHVALA is updated from the ramp generator
Reset type: SYSRSn
1650
Comparator Subsystem (CMPSS)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CMPSS Registers
www.ti.com
12.8.2.6 DACHVALS Register (Offset = 6h) [reset = 0h]
DACHVALS is shown in Figure 12-13 and described in Table 12-9.
Return to the Summary Table.
CMPSS High DAC Value Shadow Register
Figure 12-13. DACHVALS Register
15
14
13
12
11
10
RESERVED
R-0h
7
6
9
8
1
0
DACVAL
R/W-0h
5
4
3
2
DACVAL
R/W-0h
Table 12-9. DACHVALS Register Field Descriptions
Field
Type
Reset
Description
15-12
Bit
RESERVED
R
0h
Reserved
11-0
DACVAL
R/W
0h
High DAC shadow value. When COMPDACCTL[DACSOURCE]=0,
the value of DACHVALS is loaded into DACHVALA on the trigger
signal selected by COMPDACCTL[SWLOADSEL].
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS)
1651
CMPSS Registers
www.ti.com
12.8.2.7 DACHVALA Register (Offset = 7h) [reset = 0h]
DACHVALA is shown in Figure 12-14 and described in Table 12-10.
Return to the Summary Table.
CMPSS High DAC Value Active Register
Figure 12-14. DACHVALA Register
15
14
13
12
11
10
RESERVED
R-0h
7
6
9
8
1
0
DACVAL
R-0h
5
4
3
2
DACVAL
R-0h
Table 12-10. DACHVALA Register Field Descriptions
Field
Type
Reset
Description
15-12
Bit
RESERVED
R
0h
Reserved
11-0
DACVAL
R
0h
High DAC active value. Value that is actively driven by the high
DAC.
Reset type: SYSRSn
1652
Comparator Subsystem (CMPSS)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CMPSS Registers
www.ti.com
12.8.2.8 RAMPMAXREFA Register (Offset = 8h) [reset = 0h]
RAMPMAXREFA is shown in Figure 12-15 and described in Table 12-11.
Return to the Summary Table.
CMPSS Ramp Max Reference Active Register
Figure 12-15. RAMPMAXREFA Register
15
14
13
12
11
RAMPMAXREF
R-0h
10
9
8
7
6
5
4
2
1
0
3
RAMPMAXREF
R-0h
Table 12-11. RAMPMAXREFA Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
RAMPMAXREF
R
0h
Ramp maximum reference active value. Latched value to be loaded
into ramp generator RAMPSTS.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS)
1653
CMPSS Registers
www.ti.com
12.8.2.9 RAMPMAXREFS Register (Offset = Ah) [reset = 0h]
RAMPMAXREFS is shown in Figure 12-16 and described in Table 12-12.
Return to the Summary Table.
CMPSS Ramp Max Reference Shadow Register
Figure 12-16. RAMPMAXREFS Register
15
14
13
12
11
RAMPMAXREF
R/W-0h
10
9
8
7
6
5
4
2
1
0
3
RAMPMAXREF
R/W-0h
Table 12-12. RAMPMAXREFS Register Field Descriptions
Bit
15-0
1654
Field
Type
Reset
Description
RAMPMAXREF
R/W
0h
Ramp maximum reference shadow. Unlatched value to be loaded
into ramp generator RAMPSTS.
Reset type: SYSRSn
Comparator Subsystem (CMPSS)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CMPSS Registers
www.ti.com
12.8.2.10 RAMPDECVALA Register (Offset = Ch) [reset = 0h]
RAMPDECVALA is shown in Figure 12-17 and described in Table 12-13.
Return to the Summary Table.
CMPSS Ramp Decrement Value Active Register
Figure 12-17. RAMPDECVALA Register
15
14
13
12
11
RAMPDECVAL
R-0h
10
9
8
7
6
5
4
2
1
0
3
RAMPDECVAL
R-0h
Table 12-13. RAMPDECVALA Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
RAMPDECVAL
R
0h
Ramp decrement value active. Latched value that will be subtracted
from RAMPSTS.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS)
1655
CMPSS Registers
www.ti.com
12.8.2.11 RAMPDECVALS Register (Offset = Eh) [reset = 0h]
RAMPDECVALS is shown in Figure 12-18 and described in Table 12-14.
Return to the Summary Table.
CMPSS Ramp Decrement Value Shadow Register
Figure 12-18. RAMPDECVALS Register
15
14
13
12
11
RAMPDECVAL
R/W-0h
10
9
8
7
6
5
4
2
1
0
3
RAMPDECVAL
R/W-0h
Table 12-14. RAMPDECVALS Register Field Descriptions
Bit
15-0
1656
Field
Type
Reset
Description
RAMPDECVAL
R/W
0h
Ramp decrement value shadow. Unlatched value to be loaded into
RAMPDECVALA.
Reset type: SYSRSn
Comparator Subsystem (CMPSS)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CMPSS Registers
www.ti.com
12.8.2.12 RAMPSTS Register (Offset = 10h) [reset = 0h]
RAMPSTS is shown in Figure 12-19 and described in Table 12-15.
Return to the Summary Table.
CMPSS Ramp Status Register
Figure 12-19. RAMPSTS Register
15
14
13
12
11
10
9
8
3
2
1
0
RAMPVALUE
R-0h
7
6
5
4
RAMPVALUE
R-0h
Table 12-15. RAMPSTS Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
RAMPVALUE
R
0h
Ramp value. Present value of ramp generator.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS)
1657
CMPSS Registers
www.ti.com
12.8.2.13 DACLVALS Register (Offset = 12h) [reset = 0h]
DACLVALS is shown in Figure 12-20 and described in Table 12-16.
Return to the Summary Table.
CMPSS Low DAC Value Shadow Register
Figure 12-20. DACLVALS Register
15
14
13
12
11
10
RESERVED
R-0h
7
6
9
8
1
0
DACVAL
R/W-0h
5
4
3
2
DACVAL
R/W-0h
Table 12-16. DACLVALS Register Field Descriptions
Field
Type
Reset
Description
15-12
Bit
RESERVED
R
0h
Reserved
11-0
DACVAL
R/W
0h
Low DAC shadow value. value to be loaded into DACLVALA on the
trigger signal selected by COMPDACCTL[SWLOADSEL].
Reset type: SYSRSn
1658
Comparator Subsystem (CMPSS)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CMPSS Registers
www.ti.com
12.8.2.14 DACLVALA Register (Offset = 13h) [reset = 0h]
DACLVALA is shown in Figure 12-21 and described in Table 12-17.
Return to the Summary Table.
CMPSS Low DAC Value Active Register
Figure 12-21. DACLVALA Register
15
14
13
12
11
10
RESERVED
R-0h
7
6
9
8
1
0
DACVAL
R-0h
5
4
3
2
DACVAL
R-0h
Table 12-17. DACLVALA Register Field Descriptions
Field
Type
Reset
Description
15-12
Bit
RESERVED
R
0h
Reserved
11-0
DACVAL
R
0h
Low DAC active value. Value that is actively driven by the low DAC.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS)
1659
CMPSS Registers
www.ti.com
12.8.2.15 RAMPDLYA Register (Offset = 14h) [reset = 0h]
RAMPDLYA is shown in Figure 12-22 and described in Table 12-18.
Return to the Summary Table.
CMPSS Ramp Delay Active Register
Figure 12-22. RAMPDLYA Register
15
14
RESERVED
R-0h
13
12
7
6
5
4
11
10
DELAY
R-0h
9
8
3
2
1
0
DELAY
R-0h
Table 12-18. RAMPDLYA Register Field Descriptions
Field
Type
Reset
Description
15-13
Bit
RESERVED
R
0h
Reserved
12-0
DELAY
R
0h
Ramp delay active value. Latched value of the number of cycles to
delay the start of the ramp generator decrementer after a
EPWMSYNCPER is received.
Reset type: SYSRSn
1660
Comparator Subsystem (CMPSS)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CMPSS Registers
www.ti.com
12.8.2.16 RAMPDLYS Register (Offset = 15h) [reset = 0h]
RAMPDLYS is shown in Figure 12-23 and described in Table 12-19.
Return to the Summary Table.
CMPSS Ramp Delay Shadow Register
Figure 12-23. RAMPDLYS Register
15
14
RESERVED
R-0h
13
12
7
6
5
4
11
10
DELAY
R/W-0h
9
8
3
2
1
0
DELAY
R/W-0h
Table 12-19. RAMPDLYS Register Field Descriptions
Field
Type
Reset
Description
15-13
Bit
RESERVED
R
0h
Reserved
12-0
DELAY
R/W
0h
Ramp delay shadow value. Unlatched value to be loaded into
RAMPDLYA.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS)
1661
CMPSS Registers
www.ti.com
12.8.2.17 CTRIPLFILCTL Register (Offset = 16h) [reset = 0h]
CTRIPLFILCTL is shown in Figure 12-24 and described in Table 12-20.
Return to the Summary Table.
CTRIPL Filter Control Register
Figure 12-24. CTRIPLFILCTL Register
15
FILINIT
R-0/W1S-0h
14
RESERVED
R-0h
13
12
11
THRESH
R/W-0h
10
7
6
5
4
3
2
SAMPWIN
R/W-0h
9
8
SAMPWIN
R/W-0h
1
0
RESERVED
R-0h
Table 12-20. CTRIPLFILCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
FILINIT
R-0/W1S
0h
Low filter initialization.
0 No effect
1 Initialize all samples to the filter input value
Reset type: SYSRSn
14
RESERVED
R
0h
Reserved
13-9
THRESH
R/W
0h
Low filter majority voting threshold. At least THRESH samples of the
opposite state must appear within the sample window in order for the
output to change state. Threshold used is THRESH+1.
Reset type: SYSRSn
8-4
SAMPWIN
R/W
0h
Low filter sample window size. Number of samples to monitor is
SAMPWIN+1.
Reset type: SYSRSn
3-0
RESERVED
R
0h
Reserved
1662
Comparator Subsystem (CMPSS)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CMPSS Registers
www.ti.com
12.8.2.18 CTRIPLFILCLKCTL Register (Offset = 17h) [reset = 0h]
CTRIPLFILCLKCTL is shown in Figure 12-25 and described in Table 12-21.
Return to the Summary Table.
CTRIPL Filter Clock Control Register
Figure 12-25. CTRIPLFILCLKCTL Register
15
14
13
12
11
10
9
RESERVED
R-0h
7
6
5
8
CLKPRESCALE
R/W-0h
4
3
2
1
0
CLKPRESCALE
R/W-0h
Table 12-21. CTRIPLFILCLKCTL Register Field Descriptions
Bit
15-10
9-0
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
CLKPRESCALE
R/W
0h
Low filter sample clock prescale. Number of system clocks between
samples is CLKPRESCALE+1.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS)
1663
CMPSS Registers
www.ti.com
12.8.2.19 CTRIPHFILCTL Register (Offset = 18h) [reset = 0h]
CTRIPHFILCTL is shown in Figure 12-26 and described in Table 12-22.
Return to the Summary Table.
CTRIPH Filter Control Register
Figure 12-26. CTRIPHFILCTL Register
15
FILINIT
R-0/W1S-0h
14
RESERVED
R-0h
13
12
11
THRESH
R/W-0h
10
7
6
5
4
3
2
SAMPWIN
R/W-0h
9
8
SAMPWIN
R/W-0h
1
0
RESERVED
R-0h
Table 12-22. CTRIPHFILCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
FILINIT
R-0/W1S
0h
High filter initialization.
0 No effect
1 Initialize all samples to the filter input value
Reset type: SYSRSn
14
RESERVED
R
0h
Reserved
13-9
THRESH
R/W
0h
High filter majority voting threshold. At least THRESH samples of the
opposite state must appear within the sample window in order for the
output to change state. Threshold used is THRESH+1.
Reset type: SYSRSn
8-4
SAMPWIN
R/W
0h
High filter sample window size. Number of samples to monitor is
SAMPWIN+1.
Reset type: SYSRSn
3-0
RESERVED
R
0h
Reserved
1664
Comparator Subsystem (CMPSS)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CMPSS Registers
www.ti.com
12.8.2.20 CTRIPHFILCLKCTL Register (Offset = 19h) [reset = 0h]
CTRIPHFILCLKCTL is shown in Figure 12-27 and described in Table 12-23.
Return to the Summary Table.
CTRIPH Filter Clock Control Register
Figure 12-27. CTRIPHFILCLKCTL Register
15
14
13
12
11
10
9
RESERVED
R-0h
7
6
5
8
CLKPRESCALE
R/W-0h
4
3
2
1
0
CLKPRESCALE
R/W-0h
Table 12-23. CTRIPHFILCLKCTL Register Field Descriptions
Bit
15-10
9-0
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
CLKPRESCALE
R/W
0h
High filter sample clock prescale. Number of system clocks between
samples is CLKPRESCALE+1.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS)
1665
CMPSS Registers
www.ti.com
12.8.2.21 COMPLOCK Register (Offset = 1Ah) [reset = 0h]
COMPLOCK is shown in Figure 12-28 and described in Table 12-24.
Return to the Summary Table.
CMPSS Lock Register
Figure 12-28. COMPLOCK Register
15
14
13
12
11
10
9
8
3
CTRIP
R/WSonce-0h
2
DACCTL
R/WSonce-0h
1
COMPHYSCTL
R/WSonce-0h
0
COMPCTL
R/WSonce-0h
RESERVED
R-0h
7
6
RESERVED
R-0h
5
4
RESERVED
Table 12-24. COMPLOCK Register Field Descriptions
Field
Type
Reset
Description
15-5
Bit
RESERVED
R
0h
Reserved
4
RESERVED
R/WSonce
0h
Reserved
3
CTRIP
R/WSonce
0h
Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL
registers.
0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked.
Write 0 to this bit has no effect.
1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only
a system reset can clear this bit.
Reset type: SYSRSn
2
DACCTL
R/WSonce
0h
Lock write-access to the DACCTL register.
0 DACCTL register is not locked. Write 0 to this bit has no effect.
1 DACCTL register is locked. Only a system reset can clear this bit.
Reset type: SYSRSn
1
COMPHYSCTL
R/WSonce
0h
Lock write-access to the COMPHYSCTL register.
0 COMPHYSCTL register is not locked. Write 0 to this bit has no
effect.
1 COMPHYSCTL register is locked. Only a system reset can clear
this bit.
Reset type: SYSRSn
0
COMPCTL
R/WSonce
0h
Lock write-access to the COMPCTL register.
0 COMPCTL register is not locked. Write 0 to this bit has no effect.
1 COMPCTL register is locked. Only a system reset can clear this
bit.
Reset type: SYSRSn
1666
Comparator Subsystem (CMPSS)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
CMPSS Registers
www.ti.com
12.8.3 Register to Driverlib Function Mapping
Table 12-25. CMPSS Registers to Driverlib Functions
File
Driverlib Function
COMPCTL
cmpss.h
CMPSS_enableModule
cmpss.h
CMPSS_disableModule
cmpss.h
CMPSS_configHighComparator
cmpss.h
CMPSS_configLowComparator
cmpss.h
CMPSS_configOutputsHigh
cmpss.h
CMPSS_configOutputsLow
COMPHYSCTL
cmpss.h
CMPSS_setHysteresis
COMPSTS
cmpss.c
CMPSS_configLatchOnPWMSYNC
cmpss.h
CMPSS_getStatus
cmpss.h
CMPSS_clearFilterLatchHigh
cmpss.h
CMPSS_clearFilterLatchLow
COMPSTSCLR
cmpss.c
CMPSS_configLatchOnPWMSYNC
cmpss.h
CMPSS_clearFilterLatchHigh
cmpss.h
CMPSS_clearFilterLatchLow
COMPDACCTL
cmpss.c
CMPSS_configRamp
cmpss.h
CMPSS_configDAC
DACHVALS
cmpss.h
CMPSS_setDACValueHigh
DACHVALA
cmpss.h
CMPSS_getDACValueHigh
RAMPMAXREFA
cmpss.h
CMPSS_getMaxRampValue
RAMPMAXREFS
cmpss.c
CMPSS_configRamp
cmpss.h
CMPSS_setMaxRampValue
RAMPDECVALA
cmpss.h
CMPSS_getRampDecValue
RAMPDECVALS
cmpss.c
CMPSS_configRamp
cmpss.h
CMPSS_setRampDecValue
DACLVALS
cmpss.h
CMPSS_setDACValueLow
DACLVALA
cmpss.h
CMPSS_getDACValueLow
RAMPDLYA
cmpss.h
CMPSS_getRampDelayValue
RAMPDLYS
cmpss.c
CMPSS_configRamp
cmpss.h
CMPSS_setRampDelayValue
CTRIPLFILCTL
cmpss.c
CMPSS_configFilterLow
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator Subsystem (CMPSS) 1667
CMPSS Registers
www.ti.com
Table 12-25. CMPSS Registers to Driverlib Functions (continued)
File
cmpss.h
Driverlib Function
CMPSS_initFilterLow
CTRIPLFILCLKCTL
cmpss.c
CMPSS_configFilterLow
CTRIPHFILCTL
cmpss.c
CMPSS_configFilterHigh
cmpss.h
CMPSS_initFilterHigh
CTRIPHFILCLKCTL
cmpss.c
1668
Comparator Subsystem (CMPSS)
CMPSS_configFilterHigh
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Chapter 13
SPRUHM9F – October 2014 – Revised September 2019
Sigma Delta Filter Module (SDFM)
This chapter describes the sigma delta filter module (SDFM). The SDFM is a four-channel digital filter
designed specifically for current measurement and resolver position decoding in motor control
applications. Each input channel can receive an independent delta-sigma (ΔΣ) modulator bit stream. The
bit streams are processed by four individually-programmable digital decimation filters. The filter set
includes a fast comparator (secondary filter) for immediate digital threshold comparisons for over-current
and under-current monitoring, and zeros crossing detection.
Topic
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
...........................................................................................................................
Introduction ...................................................................................................
Configuring Device Pins ..................................................................................
Input Control Unit ...........................................................................................
Sinc Filter ......................................................................................................
Data (Primary) Filter Unit .................................................................................
Comparator (Secondary) Filter Unit ...................................................................
Interrupt Unit ..................................................................................................
Register Descriptions ......................................................................................
SDFM Registers ..............................................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Page
1670
1672
1673
1675
1677
1679
1681
1683
1685
Sigma Delta Filter Module (SDFM)
1669
Introduction
www.ti.com
13.1 Introduction
Figure 13-1 shows the SDFM CPU Interface.
Figure 13-1. Sigma Delta Filter Module (SDFM) CPU Interface
CPU1.SYSCLK
CPU1.SYSRSn
CPU1.PCLKCR6.SD1 / SD2
CPU1.CLA1
CPU1.DMA
CPU1.SECMSEL
rb
it
e
Arbiter
C
P
U
1
R
e
g
i
s
t
e
r
s
SDFM
SDINT1
SDINT2
SD-D1 to 8
CPU1.ePIE
SD-C1 to 8
GPIO MUX
13.1.1 SDFM Features
SDFM features include:
• Eight external pins per SDFM module
– Four sigma-delta data input pins per SDFM module (SD-Dx, where x = 1 to 4)
– Four sigma-delta clock input pins per SDFM module (SD-Cx, where x = 1 to 4)
• Four different configurable modulator clock modes:
– Mode 0: Modulator clock rate equals the modulator data rate.
– Mode 1: Modulator clock rate running at half the modulator data rate.
– Mode 2: Modulator data is Manchester-encoded. Modulator clock is not required.
– Mode 3: Modulator clock rate is double that of the modulator data rate
• Four independent, configurable secondary filter (comparator) units per SDFM module:
– Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
– Ability to detect over-value condition, under-value condition, and Threshold-crossing conditions
– OSR value for comparator filter unit (COSR) programmable from 1 to 32
• Four independent configurable primary filter (data filter) units per SDFM module:
– Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
– OSR value for data filter unit (DOSR) programmable from 1 to 256
– Ability to enable or disable (or both) individual filter module
– Ability to synchronize all four independent filters of an SDFM module by using the Master Filter
Enable (MFE) bit or by using PWM signals
• Data filter output can be represented in either 16 bits or 32 bits.
• PWMs can be used to generate a modulator clock for sigma-delta modulators.
1670
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Introduction
www.ti.com
13.1.2 Block Diagram
Each SDFM module has four independent filter modules. These filter modules are identical and can be
configured independently. Each individual filter module has the following units:
• Input control unit
• Primary filter (data filter) unit
• Secondary filter (comparator filter) unit with 4 independent comparators
Figure 13-2 shows the SDFM module block diagram. The SDFM port operation is configured and
controlled by the registers listed in Section 13.9.
Figure 13-2. Sigma Delta Filter Module (SDFM) Block Diagram
SDFM- Sigma Delta Filter Module
SDyFLTx
G4
Streams
Filter Module 1
Input
Ctrl
SDy_C1
Secondary
(Comparator)
Filter
Primary (Data) R
Filter
PWMj.CMPC
SDy_D2
GPIO
MUX
Interrupt
Unit
R
SDINTy
Peripheral Frame 1
SDy_D1
FIFO
Filter Module 2
SDy_C2
PWMj.CMPD
SDy_D3
DMA
CLA
SDINTy
C28x
Filter Module 3
SDy_C3
PWMj.CMPD
SDy_D4
Filter Module 4
Register
Map
SDyFLTx.COMPL
SDyFLTx.COMPH
Output XBAR
PWM XBAR
SDy_C4
PWMj.CMPD
LEGEND
Interrupt / trigger sources from SDFM
Internal secondary filter signals
Where,
j
y
x
11 for SDFM1, 12 for SDFM2
1 for SDFM1, 2 for SDFM2
1t4
NOTE: When using PWM11 (or) PWM12 for SDFM Data filter synchronization, users MUST ensure
that ONLY ONE CMPC (or) CMPD event will be generated per PWM timer period. Using
PWM in up-count (or) down- count mode would automatically ensure that you get ONLY one
PWMC (or) PWMD event. But, if the user wishes to use up-down count mode, then they
need to make sure that only one CMPC (or) CMPD event per PWM cycle is generated
otherwise filter synchronizer will corrupt SDFM timing by providing two pulses per PWM
cycle.
Each filter module shown in Figure 13-3 has a primary (data) filter and a secondary (comparator) filter pair
which receives the same bit stream. Except for the input bit stream, both the primary and secondary filter
are completely independent of each other. Each of these filter modules can be independently configured.
So, in a SDFM module, there is a total of four primary filters and four secondary filters.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1671
Configuring Device Pins
www.ti.com
Figure 13-3. Block Diagram of One Filter Module
Comparator Filter Unit
HLT
COMPH
SINCx
Comparator
Filter Output
COMPL
LLT
Input Control Unit
Data Filter Unit
SINCx
SD-Cx
SD-Dx
Data
Shift
Decoding
SDDATAx
AFx (Data Ready)
SDSYNC
SYSCLK
PWM
SDDFPARM.SDSYNCEN
LEGEND
Interrupt / trigger sources from SDFM
Internal secondary filter signals
13.2 Configuring Device Pins
The GPIO mux registers must be configured to connect this peripheral to the device pins. To avoid
glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding
GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value.
For proper SDFM operation, following GPIO input qualification can be used. Other GPIO qualifications are
not supported.
● If GPIO Input qualification is ASYNC, please make sure to check SDFM Electrical Data and Timing
(Using ASYNC) requirement is met and be aware of the warning message posted below.
● If GPIO Input qualification is 3-sample window, please make sure to check SDFM Electrical Data and
Timing (Using 3-Sample GPIO Input Qualification) and be aware of warning message and note posted
below
WARNING
The SDFM clock inputs (SDx_Cy pins) directly clock the SDFM
module. Any glitches or ringing noise on these inputs can corrupt
the SDFM module operation. Special precautions should be taken
on these signals to ensure a clean and noise-free signal that meets
SDFM timing requirements. Precautions such as series termination
for ringing due to any impedance mismatch of the clock driver and
spacing of traces from other noisy signals are recommended.
1672
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Input Control Unit
www.ti.com
NOTE: The SDFM Qualified GPIO (3-sample) option provides protection against SDFM module
corruption due to occasional random noise glitches on the SDx_Cy pin that may result in a
false comparator trip and filter output.
The SDFM Qualified GPIO (3-sample) option does not provide protection against persistent
violations of the above timing requirements. Timing violations will result in data corruption
proportional to the number of bits which violate the requirements
See the GPIO chapter for more details on GPIO mux and settings.
13.3 Input Control Unit
The input control unit receives sigma delta modulated data and a sigma delta modulated clock. The
modulated data received is captured and passed on to the data filter unit and comparator unit. This unit
can be configured to receive the modulated data in four different modes. Table 13-1 and Figure 13-4 show
how SDCTLPARMx.MOD bits can be configured in these four different modes.
Table 13-1. Modulator Clock Modes
MODULATOR MODE [MOD]
DESCRIPTION
0
The modulator clock is running with the modulator data rate. The modulator data is
strobed at every rising edge of the modulator clock.
1
The modulator clock is running with half of the modulator data rate. The modulator data
is strobed at every edge of the modulator clock.
2
The modulator clock is off and the modulator data is Manchester-encoded.
3
The modulator clock is running with double the modulator data rate. The modulator
data is strobed at every other positive modulator clock edge.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1673
Input Control Unit
NOTE:
www.ti.com
In order to achieve the maximum value, the sigma-delta modulator has to be
operated at absolute maximum positive or negative full scale, which is outside of
the recommended full scale range of 80% of most sigma-delta modulators.
Figure 13-4. Different Modulator Modes Supported
When MOD=2, data and modulated clock signals are encoded into modulated data as shown in Mode 2 of
Figure 13-4. In this mode, the clock input SD-Cx pin should be left floating. The input control unit performs
continuous automatic calibration to achieve optimum decoding performance.
1674
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sinc Filter
www.ti.com
13.4 Sinc Filter
Both comparator filter and data filter available in SDFM have the SincN filter as its core. The SincN filter is
essentially a low pass filter which converts the input bit stream into digital data by digital filtering and
decimation. This filtered digital data represents analog input given to the sigma delta modulator. Simplified
SincN architecture consists of cascaded integrators and differentiators separated by a down-sampler as
shown in Figure 13-6.The Z-transfer function of the Sinc filter of order N is shown below.
Figure 13-5. Z-Transform of Sinc Filter of Order N
N
H(Z) =
1- Z
-OSR
1- Z-1
N = Order of Sinc filter
OSR = Over Sampling Ratio
Figure 13-6. Simplified Sinc Filter Architecture
Differentiator
Integrator
N
Input digital bit-stream
1
N
OSR
1- Z-1
Filtered Digital data
1- Z-1
Effective resolution of the Sinc filter (ENOB) depends upon filter type, OSR and sigma-delta modulator
frequency. Typically, higher resolution (or) ENOB can be achieved by higher OSR for a given filter type;
however, the tradeoff is increased filter delay. It is important to choose the right sigma delta modulator by
studying the optimal speed versus resolution tradeoff. Refer to the corresponding sigma delta modulator
datasheet to determine the effective resolution for a given Sinc filter configuration. The figure below shows
the frequency response of different filter structures when OSR = 32 and when the sigma delta modulator
frequency is 10 MHz.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1675
Sinc Filter
www.ti.com
Figure 13-7. Frequency Response of different Sinc Filters
The order of different sinc filter is shown in the table below.
Table 13-2. Order of Sinc Filter
filter Type
Order of Sinc Filter
Sinc1
1
Sinc2
2
Sinc3
3
SincFast
3
13.4.1 Data Rate and Latency of the Sinc Filter
The data rate of the sinc filter (filter throughput) represented in samples/sec can be calculated by the
formula shown here:
Data rate of Sinc filter =
Modulator data rate
OSR
The latency of the sinc filter represented in secs is defined as the amount of time taken by a sinc filter type
to deliver the correct filtered output upon initiation. For a given filter type, latency can be calculated as
shown in this equation:
Latency of Sinc filter =
Order of Sinc filter
Data rate of Sinc filter
Example configuration:
1676
Sinc filter type
Modulator data rate
OSR
= sinc3
= 10 MHz
= 256
Data rate of Sinc Filter
Sinc filter latency
= 10 MHz / 256 = 39.1 K samples / sec
= 76.8 µs
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Data (Primary) Filter Unit
www.ti.com
Sinc filter type
Modulator data rate
OSR
= sinc2
= 10 MHz
= 256
Data rate of Sinc Filter
Sinc filter latency
= 10 MHz / 256 = 39.1 K samples / sec
=51.2 µs
13.5 Data (Primary) Filter Unit
The data filter is a configurable Sinc filter which supports the following filter types: Sinc1, Sinc2, Sinc3 and
SincFast. The data filter OSR (DOSR) settings can be configured from 1 to 256 and is independent of the
comparator filter. Effective resolution of the data filter (ENOB) depends upon Data filter type, DOSR, and
sigma-delta modulator frequency. By default, the data filter is disabled and setting of SDDFPARMx.FEN =
1 enables the data filter. The data filter output is represented in 25-bit signed integer in two’s complement
format. This filter unit translates a low input signal as ‘-1’ and a high input signal as ‘1’. The resulting
calculation gives both positive and negative values for the output of the data filter. Table 13-3 shows the
different full scale values that the data filter can store using different OSRs.
See Section 13.4.1 to understand how to calculate data rate and latency of data filter.
Table 13-3. Peak Data Values for Different DOSR/Filter Combinations
DOSR
Sinc1
Sinc2
Sinc3
Sincfast
x
x
x2
x3
2x2
4
–4 to 4
–16 to 16
–64 to 64
–32 to 32
8
–8 to 8
–64 to 64
–512 to 512
–128 to 128
16
–16 to 16
–256 to 256
–4096 to 4096
–512 to 512
32
–32 to 32
–1024 to 1024
–32,768 to 32,768
–2048 to 2048
64
–64 to 64
–4096 to 4096
–262,144 to 262,144
–8192 to 8192
128
–128 to 128
–16,384 to 16,384
–2,097,152 to 2,097,152 –32,768 to 32,768
256
–256 to 256
–65,536 to 65,536
–16,777,216 to
16,777,216
–131,072 to 131,072
13.5.1 32-bit or 16-bit Data Filter Output Representation
The data filter output can be represented in either 32-bit or 16-bit format.
32-bit data filter representation:
• When SDDPARMx.DR = 1, data filter output is represented in 32-bit format. Writes to shift control bits
do not have any bearing on the output of the data filter in this configuration.
16-bit data filter representation:
• By default, data filter output is represented in 16-bit format
• When SDDPARMx.DR = 0, data filter output is represented in 16-bit format. But it is the responsibility
of the user to configure the corresponding shift control bits in the SDDPARMx register to control which
16-bit part of the 32-bit word is sent to the register map.
For example, for the data filter configuration below:
– Filter type = Sinc3
– OSR = 128
– SDDPARMx.DR = 0
The data filter with a 25-bit signed output value can be in the range of –16,777,216 to 16,777,216. But,
16-bit signed output supports values only from –32,768 to 32,767. Therefore, it is required to configure
shift control bits (SDDPARMx.SH) to 7 to represent the data filter output correctly in 16-bit format. The
table below shows the configuration settings of shift control bits for different OSR and filter types.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1677
Data (Primary) Filter Unit
www.ti.com
Table 13-4. Shift Control Bit Configuration Settings
OSR
SINC1
SINC2
SINCFAST
SINC3
1 to 31
0
0
0
0
32 to 40
0
0
0
1
41 to 50
0
0
0
2
51 to 63
0
0
0
3
64 to 80
0
0
0
4
81 to 101
0
0
0
5
102 to 127
0
0
0
6
128 to 161
0
0
1
7
162 to 181
0
0
1
8
182 to 203
0
1
2
8
204 to 255
0
1
2
9
256
0
2
3
9
WARNING
Configuring shift control bits incorrectly will result in getting
incorrect 16-bit data filter output.
13.5.2 SDSYNC Event
Primary (data) filters can be synchronized with respect to the PWM event (called SDSYNC event). The
SDSYNC signal from the PWM module is used to reset the DOSR counter. This feature is by default
disabled and can be enabled by setting SDDFPARMx.SDSYNCEN = 1. Figure 13-8 shows how the PWM
signals are connected to the sigma delta module. In this device, PWM11 can be used to reset SDFM1
filter modules and PWM12 can be used to reset SDFM2 modules.
Figure 13-8 shows how the PWM signals are connected to SDFM.
Figure 13-8. SDSYNC Event
SDFM
PWM
SDSYNC
Filter 1
PWMn.CMPC
Filter 2
SDSYNC
Filter 3
PWMn.CMPD
Filter 4
NOTE: Ensure that ONLY ONE SDSYNC event will be generated per PWM timer period. Using
PWM in up-count or down-count mode would automatically ensure that you get ONLY
SDSYNC event. But, if up-down count mode is used, then make sure that only one SDSYNC
event per PWM cycle is generated; otherwise, the filter synchronizer will corrupt SDFM
timing by providing two pulses per PWM cycle.
1678
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Comparator (Secondary) Filter Unit
www.ti.com
Because of the inherent architecture of the Sinc filter (Sinc1, Sinc2, Sinc3, SincFast), the first few
samples, depending upon filter type will be incorrect. Table 13-5 shows the number of incorrect samples
on the following conditions:• When Sinc filter is enabled / configured for first time.
• When Sinc filter is disabled / re-enabled or reconfigured in the middle of operation.
• When data filter receives SDSYNC event from PWM.
Table 13-5. Number of Incorrect Samples Tabulated
Number of incorrect samples after the filter is enabled and
configured
Filter type
Sinc1
No incorrect sample
Sinc2
The first sample of the Sinc2 filter is incorrect
SincFast
The first two samples of the SincFast filter are incorrect
Sinc3
The first two samples of the Sinc3 filter are incorrect
WARNING
SDFM comparator interrupts should be enabled only after
providing sufficient settling time to make sure the comparator filter
does not trip on these incorrect samples. Therefore, SDFM
comparator interrupts (IELx and IEHx) should be enabled only after
a sufficient delay is provided after the comparator filter is
configured. This sufficient delay is calculated by adding the
latency of the comparator filter and five SD-Cx clock cycles.
13.6 Comparator (Secondary) Filter Unit
Most control systems require protection of the system by tripping the PWM in case the current or voltage
goes out of bounds. The primary purpose of the secondary (comparator) filter is to allow the user to
monitor input conditions with a fast settling time. This allows the user to trip PWMs to protect the system
from potential damage.
NOTE: The secondary (comparator) filter cannot be synchronized with respect to the PWM event
(SDSYNC event).
The comparator filter is a configurable Sinc filter which supports the following filter types: - Sinc1, Sinc2,
Sinc3 and SincFast. The comparator OSR (COSR) settings can be configured from 1 to 32 and is
independent of the data filter. Effective resolution of the comparator filter (ENOB) depends upon the
comparator filter type, COSR, and sigma-delta modulator frequency. By default, the comparator filter is
enabled. The comparator filter output is represented in 16-bit unsigned format. This filter unit translates a
low input signal as ‘0’ and a high input signal as ‘1’. The resulting calculations give only positive values for
the output of the comparator filter. Table 13-6 shows the different full-scale values that the comparator
filter can store using different OSRs.
Table 13-6. Peak Data Values for Different OSR/Filter Combinations
OSR
Sinc1
Sinc2
Sinc3
Sincfast
x
0 to x
0 to x2
0 to x3
0 to 2x2
4
0 to 4
0 to 16
0 to 64
0 to 32
8
0 to 8
0 to 64
0 to 512
0 to 128
16
0 to 16
0 to 256
0 to 4096
0 to 512
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1679
Comparator (Secondary) Filter Unit
www.ti.com
Table 13-6. Peak Data Values for Different OSR/Filter Combinations (continued)
OSR
Sinc1
Sinc2
Sinc3
Sincfast
32
0 to 32
0 to 1024
0 to 32,768
0 to 2048
See Section 13.4.1 to understand how to calculate data rate and latency of comparator filter.
The output of the comparator filter is not memory mapped; instead it is connected to digital comparators
explained below.
Figure 13-9. Comparator Unit Structure
Comparator Unit
HTL
COMPH
SINCx
COMPL
LLT
13.6.1 Higher threshold (HLT) comparator
•
•
•
•
High threshold comparator can be used to detect over-value condition.
When comparator data > = higher threshold register, a high threshold event is generated.
Higher threshold comparator events can be configured to trigger following events : CPU interrupt, CLA
task, PWM trip.
This device has one High Threshold comparator.
– Higher Threshold (HLT) Comparator : When SDCTL.MIE = 1 and SDCPARMx.IEH = 1, the high
threshold event triggers an SDFM interrupt (SDINT) and sets the SDIFLG.IEHx flag showing the
over-value condition is triggered. This SDIFLG.IEHx flag can be reset if the corresponding bit in the
SDIFLGCLR register is set and if the interrupt source is no longer active.
13.6.2 Lower Threshold (LLT) comparator
•
•
•
•
1680
The low threshold comparator can be used to detect under-value condition.
When comparator data < = Lower Threshold register, a low threshold event is generated.
Lower threshold comparator events can be configured to trigger following events : CPU interrupt, CLA
task, PWM trip.
This device has one low threshold comparator.
– Lower Threshold (LLT) Comparator : When SDCTL.MIE = 1 and SDCPARMx.IEL = 1, the low
threshold event triggers an SDFM interrupt (SDINT) and sets the SDIFLG.IELx flag showing an
under-value condition is triggered. This SDIFLG.IELx flag can be reset if the corresponding bit in
the SDIFLGCLR register is set and if the interrupt source is no longer active.
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Interrupt Unit
www.ti.com
13.7 Interrupt Unit
Each SDFM can generate one CPU interrupt (SDINT).
13.7.1 SDFM (SDINT) Interrupt sources:
Figure 13-10 shows the structure of the interrupt unit. Each SDFM module can generate a CPU interrupt.
An SDFM interrupt can be triggered by any of these 16 events.
shows the structure of SDy_ERR interrupt. SDy_ERR interrupt can be triggered by any of these 16
events.
1. Comparator Lower Threshold events (COMPLx)
COMPL events from any of the four comparator filter module can trigger CPU interrupt. This event can be
configured to trigger SDINT interrupt only if below configurations are made:
• Enable master interrupt enable (SDCTL.MIE = 1)
• Enable comparator filter lower threshold interrupt (SDCPARMx.IEL = 1)
On a COMPL event, SDIFLG.IELx flag bit is set. This flag bit can only be reset if the corresponding bit in
SDIFLGCLR register is set and if the interrupt source is no longer active.
2. Comparator High Threshold events (COMPHx)
COMPH events from any of the four comparator filter module can trigger CPU interrupt. This event can be
configured to trigger SDINT interrupt only if below configurations are made:
• Enable master interrupt enable (SDCTL.MIE = 1)
• Enable comparator filter lower threshold interrupt (SDCPARMx.IEH = 1)
On a COMPH event, SDIFLG.IEHx flag bit is set. This flag bit can only be reset if the corresponding bit in
SDIFLGCLR register is set and if the interrupt source is no longer active.
3. Modulator Failure (MFx) event
Modulator failures (MFx) are generated when SD-Cx goes missing. The modulator clock is considered
missing if SD-Cx does not toggle for 64-SYSCLKs. MFx events from any of the four filter modules can
trigger CPU interrupt. This event can be configured to trigger SDINT interrupt only if below configurations
are made:
• Enable master Interrupt Enable (SDCTL.MIE = 1)
• Enable modulator clock failure interrupt source (SDCPARMx.MFIE = 1)
On a MFx event, SDIFLG.MFx flag bit is set. This flag bit can only be reset if the corresponding bit in
SDIFLGCLR register is set and if the interrupt source is no longer active.
4. New Filter Data Ready (AFx) event
When the primary filter is ready with a new filter data, the AFx event is generated. AFx events from any of
the four primary filter modules can be configured to trigger a CPU interrupt. This event can be configured
to trigger SDINT interrupt only if below configurations are made:
• Enable master interrupt enable (SDCTL.MIE = 1)
• Enable data filter acknowledge (SDDFPARMx.AE = 1)
On an AFx event, the SDIFLG.AFx flag bit is set. This flag bit can only be reset if the corresponding bit in
SDIFLGCLR register is set and if the interrupt source is no longer active.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1681
Interrupt Unit
www.ti.com
Figure 13-10. SDFM Interrupt Unit
SDCMPHx.HLTx
+
SDCTL .MIE
COMPHx
S
-
SDCPARMx.IEH
R
Data
IEHx flag bit
Q
SDIFLGCLR.IEHx
SDCTL .MIE
+
SDCMPLx.LLTx
COMPLx
-
S
R
IELx flag bit
Q
SDCPARMx.IEL
SDIFLGCLR.IELx
SDCTL .MIE
Modulator failure
S
IEHx flag bit
MFx flag bit
Q
IELx flag bit
SDCPARMx.MFIE
R
SDINTy
MFx flag bit
SDIFLGCLR.MFx
AFx flag bit
SDCTL .MIE
New filter data
S
R
Where,
x = 1 to 4
y = 1 (or) 2
AFx flag bit
Q
SDSFPARM x.AE
SDIFLGCLR.AFx
1682
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Register Descriptions
www.ti.com
13.8 Register Descriptions
The register descriptions are shown in the following table and subsections.
Table 13-7. General Registers
Name
SDFM1 address
SDFM2 address
Size (x16)
Description
SDIFLG
0x5E00
0x5E80
2
Interrupt Flag Register
EALLOW?
SDIFLGCLR
0x5E02
0x5E82
2
Interrupt Flag Clear Register
SDCTL
0x5E04
0x5E84
1
SD Control Register
YES
SDMFILEN
0x5E06
0x5E86
1
SD Master Filter Enable
YES
Reserved
0x5E07
0x5E87
1
Reserved
Table 13-8. Filter 1 Registers
Name
SDFM1 address
SDFM2 address
Size (x16)
Description
EALLOW?
SDCTLPARM1
0x5E10
0x5E90
1
Control Parameter Register
for Ch1
YES
SDDFPARM1
0x5E11
0x5E91
1
Data Filter Parameter
Register for Ch1
YES
SDDPARM1
0x5E12
0x5E92
1
Integer Parameter Register
for Ch1
YES
SDCMPH1
0x5E13
0x5E93
1
High-level Threshold
Register for Ch1
YES
SDCMPL1
0x5E14
0x5E94
1
Low-level Threshold Register
for Ch1
YES
SDCPARM1
0x5E15
0x5E95
1
Comparator Parameter
Register for Ch1
YES
SDDATA1
0x5E16
0x5E96
2
Filter Data Register (16- or
32-bit) for Ch1
Table 13-9. Filter 2 Registers
Name
SDFM1 address
SDFM2 address
Size (x16)
Description
EALLOW?
SDCTLPARM2
0x5E20
0x5EA0
1
Control Parameter Register
for Ch2
YES
SDDFPARM2
0x5E21
0x5EA1
1
Data Filter Parameter
Register for Ch2
YES
SDDPARM2
0x5E22
0x5EA2
1
Integer Parameter Register
for Ch2
YES
SDCMPH2
0x5E23
0x5EA3
1
High-level Threshold
Register for Ch2
YES
SDCMPL2
0x5E24
0x5EA4
1
Low-level Threshold Register
for Ch2
YES
SDCPARM2
0x5E25
0x5EA5
1
Comparator Parameter
Register for Ch2
YES
SDDATA2
0x5E26
0x5EA6
2
Filter Data Register (16- or
32-bit) for Ch2
Table 13-10. Filter 3 Registers
Name
SDFM1 address
SDFM2 address
Size (x16)
Description
EALLOW?
SDCTLPARM3
0x5E30
0x5EB0
1
Control Parameter Register
for Ch3
YES
SDDFPARM3
0x5E31
0x5EB1
1
Data Filter Parameter
Register for Ch3
YES
SDDPARM3
0x5E32
0x5EB2
1
Integer Parameter Register
for Ch3
YES
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM) 1683
Register Descriptions
www.ti.com
Table 13-10. Filter 3 Registers (continued)
Name
SDFM1 address
SDFM2 address
Size (x16)
Description
EALLOW?
SDCMPH3
0x5E33
0x5EB3
1
High-level Threshold
Register for Ch3
YES
SDCMPL3
0x5E34
0x5EB4
1
Low-level Threshold Register
for Ch3
YES
SDCPARM3
0x5E35
0x5EB5
1
Comparator Parameter
Register for Ch3
YES
SDDATA3
0x5E36
0x5EB6
2
Filter Data Register (16- or
32-bit) for Ch3
Table 13-11. Filter 4 Registers
1684
Name
SDFM1 address
SDFM2 address
Size (x16)
Description
EALLOW?
SDCTLPARM4
0x5E40
0x5EC0
1
Control Parameter Register
for Ch4
YES
SDDFPARM4
0x5E41
0x5EC1
1
Data Filter Parameter
Register for Ch4
YES
SDDPARM4
0x5E42
0x5EC2
1
Integer Parameter Register
for Ch4
YES
SDCMPH4
0x5E43
0x5EC3
1
High-level Threshold
Register for Ch4
YES
SDCMPL4
0x5E44
0x5EC4
1
Low-level Threshold Register
for Ch4
YES
SDCPARM4
0x5E45
0x5EC5
1
Comparator Parameter
Register for Ch4
YES
SDDATA4
0x5E46
0x5EC6
2
Filter Data Register (16- or
32-bit) for Ch4
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
13.9 SDFM Registers
This section describes the Sigma Delta Filter registers.
13.9.1 SDFM Base Addesses
Table 13-12. SDFM Base Address Table
Device Registers
Register Name
Start Address
End Address
Sdfm1Regs
SDFM_REGS
0x0000_5E00
0x0000_5E7F
Sdfm2Regs
SDFM_REGS
0x0000_5E80
0x0000_5EFF
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1685
SDFM Registers
www.ti.com
13.9.2 SDFM_REGS Registers
Table 13-13 lists the SDFM_REGS registers. All register offset addresses not listed in Table 13-13 should
be considered as reserved locations and the register contents should not be modified.
Table 13-13. SDFM_REGS Registers
Offset
Acronym
Register Name
0h
SDIFLG
Interrupt Flag Register
Write Protection
Section
2h
SDIFLGCLR
Interrupt Flag Clear Register
4h
SDCTL
SD Control Register
EALLOW
Go
Go
Go
6h
SDMFILEN
SD Master Filter Enable
EALLOW
Go
10h
SDCTLPARM1
Control Parameter Register for Ch1
EALLOW
Go
11h
SDDFPARM1
Data Filter Parameter Register for Ch1
EALLOW
Go
12h
SDDPARM1
Integer Parameter Register for Ch1
EALLOW
Go
13h
SDCMPH1
High-level Threshold Register for Ch1
EALLOW
Go
14h
SDCMPL1
Low-level Threshold Register for Ch1
EALLOW
Go
15h
SDCPARM1
Comparator Parameter Register for Ch1
EALLOW
Go
16h
SDDATA1
Filter Data Register (16 or 32bit) for Ch1
20h
SDCTLPARM2
Control Parameter Register for Ch2
EALLOW
Go
21h
SDDFPARM2
Data Filter Parameter Register for Ch2
EALLOW
Go
22h
SDDPARM2
Integer Parameter Register for Ch2
EALLOW
Go
23h
SDCMPH2
High-level Threshold Register for Ch2
EALLOW
Go
24h
SDCMPL2
Low-level Threshold Register for Ch2
EALLOW
Go
25h
SDCPARM2
Comparator Parameter Register for Ch2
EALLOW
Go
26h
SDDATA2
Filter Data Register (16 or 32bit) for Ch2
30h
SDCTLPARM3
Control Parameter Register for Ch3
EALLOW
Go
31h
SDDFPARM3
Data Filter Parameter Register for Ch3
EALLOW
Go
32h
SDDPARM3
Integer Parameter Register for Ch3
EALLOW
Go
33h
SDCMPH3
High-level Threshold Register for Ch3
EALLOW
Go
34h
SDCMPL3
Low-level Threshold Register for Ch3
EALLOW
Go
35h
SDCPARM3
Comparator Parameter Register for Ch3
EALLOW
Go
36h
SDDATA3
Filter Data Register (16 or 32bit) for Ch3
40h
SDCTLPARM4
Control Parameter Register for Ch4
EALLOW
Go
41h
SDDFPARM4
Data Filter Parameter Register for Ch4
EALLOW
Go
42h
SDDPARM4
Integer Parameter Register for Ch4
EALLOW
Go
43h
SDCMPH4
High-level Threshold Register for Ch4
EALLOW
Go
44h
SDCMPL4
Low-level Threshold Register for Ch4
EALLOW
Go
45h
SDCPARM4
Comparator Parameter Register for Ch4
EALLOW
Go
46h
SDDATA4
Filter Data Register (16 or 32bit) for Ch4
Go
Go
Go
Go
Complex bit access types are encoded to fit into small table cells. Table 13-14 shows the codes that are
used for access types in this section.
Table 13-14. SDFM_REGS Access Type Codes
Access Type
Code
Description
R
R
Read
R=0
R
Read
W
W
Write
W=1
W
Write
Read Type
Write Type
1686
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
Table 13-14. SDFM_REGS Access Type
Codes (continued)
Access Type
Code
Description
Reset or Default Value
-n
Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y
When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1687
SDFM Registers
www.ti.com
13.9.2.1 SDIFLG Register (Offset = 0h) [reset = 0h]
SDIFLG is shown in Figure 13-11 and described in Table 13-15.
Return to the Summary Table.
Interrupt Flag Register
Figure 13-11. SDIFLG Register
31
MIF
R-0h
30
29
28
23
22
21
20
27
RESERVED
26
25
24
19
18
17
16
RESERVED
15
AF4
R-0h
14
AF3
R-0h
13
AF2
R-0h
12
AF1
R-0h
11
MF4
R-0h
10
MF3
R-0h
9
MF2
R-0h
8
MF1
R-0h
7
IFL4
R-0h
6
IFH4
R-0h
5
IFL3
R-0h
4
IFH3
R-0h
3
IFL2
R-0h
2
IFH2
R-0h
1
IFL1
R-0h
0
IFH1
R-0h
Table 13-15. SDIFLG Register Field Descriptions
Bit
Field
Type
Reset
Description
31
MIF
R
0h
Set whenever any interrupt (ACK1-4, MF1-4,IFL1-4,IFH1-4) is active
Reset type: SYSRSn
RESERVED
R=0
0h
Reserved
AF4
R
0h
0: No new data available from Filter 4
30-16
15
1: New data available from Filter 4
Reset type: SYSRSn
14
AF3
R
0h
0: No new data available from Filter 3
1: New data available from Filter 3
Reset type: SYSRSn
13
AF2
R
0h
0: No new data available from Filter 2
1: New data available from Filter 2
Reset type: SYSRSn
12
AF1
R
0h
0: No new data available from Filter 1
1: New data available from Filter 1
Reset type: SYSRSn
11
MF4
R
0h
0: Modulator is operating normally for Filter 4
1: Modulator failure for Filter 4
Reset type: SYSRSn
10
MF3
R
0h
0: Modulator is operating normally for Filter 3
1: Modulator failure for Filter 3
Reset type: SYSRSn
9
MF2
R
0h
0: Modulator is operating normally for Filter 2
1: Modulator failure for Filter 2
Reset type: SYSRSn
8
MF1
R
0h
0: Modulator is operating normally for Filter 1
1: Modulator failure for Filter 1
Reset type: SYSRSn
1688
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
Table 13-15. SDIFLG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
7
IFL4
R
0h
0: Comparator Filter 4 output is above the low limit threshold
1: Comparator Filter 4 output is equal to or below the low level
threshold, if enabled
Reset type: SYSRSn
6
IFH4
R
0h
0: Comparator Filter 4 output is below the high limit threshold
1: Comparator Filter 4 output is equal to or above the high level
threshold, if enabled
Reset type: SYSRSn
5
IFL3
R
0h
0: Comparator Filter 3 output is above the low limit threshold
1: Comparator Filter 3 output is equal to or below the low level
threshold, if enabled
Reset type: SYSRSn
4
IFH3
R
0h
0: Comparator Filter 3 output is below the high limit threshold
1: Comparator Filter 3 output is equal to or above the high level
threshold, if enabled
Reset type: SYSRSn
3
IFL2
R
0h
0: Comparator Filter 2 output is above the low limit threshold
1: Comparator Filter 2 output is equal to or below the low level
threshold, if enabled
Reset type: SYSRSn
2
IFH2
R
0h
0: Comparator Filter 2 output is below the high limit threshold
1: Comparator Filter 2 output is equal to or above the high level
threshold, if enabled
Reset type: SYSRSn
1
IFL1
R
0h
0: Comparator Filter 1 output is above the low limit threshold
1: Comparator Filter 1 output is equal to or below the low level
threshold, if enabled
Reset type: SYSRSn
0
IFH1
R
0h
0: Comparator Filter 1 output is below the high limit threshold
1: Comparator Filter 1 output is equal to or above the high level
threshold, if enabled
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1689
SDFM Registers
www.ti.com
13.9.2.2 SDIFLGCLR Register (Offset = 2h) [reset = 0h]
SDIFLGCLR is shown in Figure 13-12 and described in Table 13-16.
Return to the Summary Table.
Interrupt Flag Clear Register
Figure 13-12. SDIFLGCLR Register
31
MIF
R=0/W=1-0h
30
29
28
23
22
21
20
27
RESERVED
26
25
24
19
18
17
16
RESERVED
15
AF4
R=0/W=1-0h
14
AF3
R=0/W=1-0h
13
AF2
R=0/W=1-0h
12
AF1
R=0/W=1-0h
11
MF4
R=0/W=1-0h
10
MF3
R=0/W=1-0h
9
MF2
R=0/W=1-0h
8
MF1
R=0/W=1-0h
7
IFL4
R=0/W=1-0h
6
IFH4
R=0/W=1-0h
5
IFL3
R=0/W=1-0h
4
IFH3
R=0/W=1-0h
3
IFL2
R=0/W=1-0h
2
IFH2
R=0/W=1-0h
1
IFL1
R=0/W=1-0h
0
IFH1
R=0/W=1-0h
Table 13-16. SDIFLGCLR Register Field Descriptions
Bit
Field
Type
Reset
Description
31
MIF
R=0/W=1
0h
Flag-clear bit for SDFM Master Interrupt flag. Write 1 to clear MIF.
Writes of "0" are ignored.
Note: If the MIF flag is cleared and other Interrupts are still pending,
MIF will again be set to 1 on the following SysClk cycle, and the INT
output will be reasserted (pulsed low)
Reset type: SYSRSn
30-16
15
RESERVED
R=0
0h
Reserved
AF4
R=0/W=1
0h
SD Module Interrupt Flag Clear Bits:
Writing a "1" will clear the respective flag bit in the SDINTFLG
register. Writes of "0" are ignored.
Note: If user writes a "1" to clear a bit on the same cycle that the
hardware is trying to set the bit to "1", then hardware has priority and
the bit will not be cleared.
Flag-clear bit for Acknowledge flag for Filter 4
Reset type: SYSRSn
1690
14
AF3
R=0/W=1
0h
Flag-clear bit for Acknowledge flag for Filter 3
Reset type: SYSRSn
13
AF2
R=0/W=1
0h
Flag-clear bit for Acknowledge flag for Filter 2
Reset type: SYSRSn
12
AF1
R=0/W=1
0h
Flag-clear bit for Acknowledge flag for Filter 1
Reset type: SYSRSn
11
MF4
R=0/W=1
0h
Flag-clear bit for Modulator Failure for Filter 4
Reset type: SYSRSn
10
MF3
R=0/W=1
0h
Flag-clear bit for Modulator Failure for Filter 3
Reset type: SYSRSn
9
MF2
R=0/W=1
0h
Flag-clear bit for Modulator Failure for Filter 2
Reset type: SYSRSn
8
MF1
R=0/W=1
0h
Flag-clear bit for Modulator Failure for Filter 1
Reset type: SYSRSn
7
IFL4
R=0/W=1
0h
Flag-clear bit for Low-Level Interrupt flag Filter 4
Reset type: SYSRSn
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
Table 13-16. SDIFLGCLR Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6
IFH4
R=0/W=1
0h
Flag-clear bit for High-level Interrupt flag Filter 4
Reset type: SYSRSn
5
IFL3
R=0/W=1
0h
Flag-clear bit for Low-Level Interrupt flag Filter 3
Reset type: SYSRSn
4
IFH3
R=0/W=1
0h
Flag-clear bit for High-level Interrupt flag Filter 3
Reset type: SYSRSn
3
IFL2
R=0/W=1
0h
Flag-clear bit for Low-Level Interrupt flag Filter 2
Reset type: SYSRSn
2
IFH2
R=0/W=1
0h
Flag-clear bit for High-level Interrupt flag Filter 2
Reset type: SYSRSn
1
IFL1
R=0/W=1
0h
Flag-clear bit for Low-Level Interrupt flag Filter 1
Reset type: SYSRSn
0
IFH1
R=0/W=1
0h
Flag-clear bit for High-level Interrupt flag Filter 1
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1691
SDFM Registers
www.ti.com
13.9.2.3 SDCTL Register (Offset = 4h) [reset = 0h]
SDCTL is shown in Figure 13-13 and described in Table 13-17.
Return to the Summary Table.
SD Control Register
Figure 13-13. SDCTL Register
15
RESERVED
14
RESERVED
13
MIE
R/W-0h
12
7
6
5
4
11
10
RESERVED
9
8
3
2
1
0
RESERVED
Table 13-17. SDCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R=0
0h
Reserved
14
RESERVED
R=0
0h
Reserved
13
MIE
R/W
0h
Master interrupt enable.
0: Interrupt pin and interrupt flags are blocked (interrupt pin INT
always inactive).
1: Interrupt pin and interrupt flags are not blocked and can be set
and reset (if individually
enabled).
Reset type: SYSRSn
12-0
1692
RESERVED
Sigma Delta Filter Module (SDFM)
R=0
0h
Reserved
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
13.9.2.4 SDMFILEN Register (Offset = 6h) [reset = 0h]
SDMFILEN is shown in Figure 13-14 and described in Table 13-18.
Return to the Summary Table.
SD Master Filter Enable
Figure 13-14. SDMFILEN Register
15
14
RESERVED
13
12
RESERVED
11
MFE
R/W-0h
10
RESERVED
9
RESERVED
8
RESERVED
7
RESERVED
6
5
RESERVED
4
3
2
1
0
RESERVED
Table 13-18. SDMFILEN Register Field Descriptions
Field
Type
Reset
Description
15-13
Bit
RESERVED
R=0
0h
Reserved
12
RESERVED
R=0
0h
Reserved
11
MFE
R/W
0h
Master Filter Enable. Functionally AND'ed with bit FEN in the Data
Filter Parameter Register
0: Data filter units of all filter modules are disabled.
1: Data filter units can be enabled if bit FEN is '1'.
Reset type: SYSRSn
10
RESERVED
R=0
0h
Reserved
9
RESERVED
R=0
0h
Reserved
8-7
RESERVED
R=0
0h
Reserved
6-4
RESERVED
R=0
0h
Reserved
3-0
RESERVED
R=0
0h
Reserved
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1693
SDFM Registers
www.ti.com
13.9.2.5 SDCTLPARM1 Register (Offset = 10h) [reset = 0h]
SDCTLPARM1 is shown in Figure 13-15 and described in Table 13-19.
Return to the Summary Table.
Control Parameter Register for Ch1
Figure 13-15. SDCTLPARM1 Register
15
14
13
12
11
10
9
3
RESERVED
2
RESERVED
1
8
RESERVED
7
6
RESERVED
5
4
RESERVED
0
MOD
R/W-0h
Table 13-19. SDCTLPARM1 Register Field Descriptions
Field
Type
Reset
Description
15-5
Bit
RESERVED
R
0h
Reserved
4
RESERVED
R=0
0h
Reserved
3
RESERVED
R=0
0h
Reserved
2
RESERVED
R=0
0h
Reserved
MOD
R/W
0h
Delta-Sigma Modulator mode
1-0
00: The clock speed is equal to the data rate from the modulator
01: The clock rate is half of the data rate from the modulator
10: The data from the modulator is Manchester decoded
11: The clock rate is twice the data rate of the modulator
Reset type: SYSRSn
1694
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
13.9.2.6 SDDFPARM1 Register (Offset = 11h) [reset = 0h]
SDDFPARM1 is shown in Figure 13-16 and described in Table 13-20.
Return to the Summary Table.
Data Filter Parameter Register for Ch1
Figure 13-16. SDDFPARM1 Register
15
14
RESERVED
13
6
5
7
12
SDSYNCEN
R/W-0h
11
4
3
10
9
AE
R/W-0h
8
FEN
R/W-0h
2
1
0
SST
R/W-0h
DOSR
R/W-0h
Table 13-20. SDDFPARM1 Register Field Descriptions
Field
Type
Reset
Description
15-13
Bit
RESERVED
R
0h
Reserved
12
SDSYNCEN
R/W
0h
Data Filter Reset enable for External Reset typ from PWM Compare
output.
0: Data filter cannot be reset by external PWM compare output
1: Data filter can be reset by external PWM compare output
Reset type: SYSRSn
11-10
SST
R/W
0h
Data filter structure.
00: Data filter runs with a Sincfast structure
01: Data filter runs with a Sinc1 structure
10: Data filter runs with a Sinc2 structure
11: Data filter runs with a Sinc3 structure
Reset type: SYSRSn
9
AE
R/W
0h
Acknowledge enable.
0: Acknowledge flag is disabled for the particular filter
1: Acknowledge flag is enabled for the particular filter
Reset type: SYSRSn
8
FEN
R/W
0h
Filter enable.
0: The filter is disabled and no data is produced
1: The filter is enabled and data are produced in the Data filter
Reset type: SYSRSn
7-0
DOSR
R/W
0h
Oversampling ratio. The actual rate is DOSR + 1.
These bits set the oversampling ratio of the filter.
0x0FF represents an oversampling ratio of 256.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1695
SDFM Registers
www.ti.com
13.9.2.7 SDDPARM1 Register (Offset = 12h) [reset = 0h]
SDDPARM1 is shown in Figure 13-17 and described in Table 13-21.
Return to the Summary Table.
Integer Parameter Register for Ch1
Figure 13-17. SDDPARM1 Register
15
14
13
SH
R/W-0h
12
11
10
DR
R/W-0h
9
RESERVED
R/W-0h
8
RESERVED
R/W-0h
7
RESERVED
6
5
4
3
RESERVED
R/W-0h
2
1
0
Table 13-21. SDDPARM1 Register Field Descriptions
Bit
15-11
Field
Type
Reset
Description
SH
R/W
0h
Shift Control
These bits indicate by how many bits the 16-bit window is shifted up
when 16-bit data representation is chosen.
Reset type: SYSRSn
10
DR
R/W
0h
Data representation
0: Data stored in 16b 2's complement
1: Data stored in 32b 2's complement
Reset type: SYSRSn
1696
9
RESERVED
R/W
0h
Reserved
8
RESERVED
R/W
0h
Reserved
7
RESERVED
R=0
0h
Reserved
6-0
RESERVED
R/W
0h
Reserved
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
13.9.2.8 SDCMPH1 Register (Offset = 13h) [reset = 0h]
SDCMPH1 is shown in Figure 13-18 and described in Table 13-22.
Return to the Summary Table.
High-level Threshold Register for Ch1
Figure 13-18. SDCMPH1 Register
15
RESERVED
14
13
12
7
6
5
4
11
HLT
R/W-0h
10
9
8
3
2
1
0
HLT
R/W-0h
Table 13-22. SDCMPH1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R=0
0h
Reserved
HLT
R/W
0h
Unsigned high-level threshold for the comparator filter output.
Reset type: SYSRSn
14-0
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1697
SDFM Registers
www.ti.com
13.9.2.9 SDCMPL1 Register (Offset = 14h) [reset = 0h]
SDCMPL1 is shown in Figure 13-19 and described in Table 13-23.
Return to the Summary Table.
Low-level Threshold Register for Ch1
Figure 13-19. SDCMPL1 Register
15
RESERVED
14
13
12
7
6
5
4
11
LLT
R/W-0h
10
9
8
3
2
1
0
LLT
R/W-0h
Table 13-23. SDCMPL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R=0
0h
Reserved
LLT
R/W
0h
Unsigned low-level threshold for the comparator filter output.
Reset type: SYSRSn
14-0
1698
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
13.9.2.10 SDCPARM1 Register (Offset = 15h) [reset = 0h]
SDCPARM1 is shown in Figure 13-20 and described in Table 13-24.
Return to the Summary Table.
Comparator Parameter Register for Ch1
Figure 13-20. SDCPARM1 Register
15
14
13
12
11
10
9
MFIE
R/W-0h
8
CS1_CS0
R/W-0h
4
3
2
COSR
R/W-0h
1
0
RESERVED
7
CS1_CS0
R/W-0h
6
IEL
R/W-0h
5
IEH
R/W-0h
Table 13-24. SDCPARM1 Register Field Descriptions
Bit
15-10
9
Field
Type
Reset
Description
RESERVED
R=0
0h
Reserved
MFIE
R/W
0h
0: The modulator failure flag as well as the output INT is disabled for
this particular flag
1: The modulator failure flag is enabled
Reset type: SYSRSn
8-7
CS1_CS0
R/W
0h
Comparator filter structure.
00: Comparator filter runs with a sincfast structure
01: Comparator filter runs with a Sinc1 structure
10: Comparator filter runs with a Sinc2 structure
11: Comparator filter runs with a Sinc3 structure
Reset type: SYSRSn
6
IEL
R/W
0h
Low-level interrupt enable.
0: The low-level interrupt flag as well as the output INT is disabled
for this particular flag
1: The low-level interrupt flag is enabled
Reset type: SYSRSn
5
IEH
R/W
0h
High-level interrupt enable.
0: The high-level interrupt flag as well as the output INT is disabled
for this particular flag
1: The high-level interrupt flag is enabled
Reset type: SYSRSn
4-0
COSR
R/W
0h
Oversampling ratio. The actual rate is COSR + 1.
These bits set the oversampling ratio of the filter.
0x1F represents an oversampling ratio of 31.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1699
SDFM Registers
www.ti.com
13.9.2.11 SDDATA1 Register (Offset = 16h) [reset = 0h]
SDDATA1 is shown in Figure 13-21 and described in Table 13-25.
Return to the Summary Table.
Filter Data Register (16 or 32bit) for Ch1
Figure 13-21. SDDATA1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA32HI
R-0h
9
8 7 6
DATA16
R-0h
5
4
3
2
1
0
Table 13-25. SDDATA1 Register Field Descriptions
Field
Type
Reset
Description
31-16
Bit
DATA32HI
R
0h
Hi-order 16-bit in 32-bit mode
Reset type: SYSRSn
15-0
DATA16
R
0h
16-bit data in 16-bit mode
Reset type: SYSRSn
1700
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
13.9.2.12 SDCTLPARM2 Register (Offset = 20h) [reset = 0h]
SDCTLPARM2 is shown in Figure 13-22 and described in Table 13-26.
Return to the Summary Table.
Control Parameter Register for Ch2
Figure 13-22. SDCTLPARM2 Register
15
14
13
12
11
10
9
3
RESERVED
2
RESERVED
1
8
RESERVED
7
6
RESERVED
5
4
RESERVED
0
MOD
R/W-0h
Table 13-26. SDCTLPARM2 Register Field Descriptions
Field
Type
Reset
Description
15-5
Bit
RESERVED
R
0h
Reserved
4
RESERVED
R=0
0h
Reserved
3
RESERVED
R=0
0h
Reserved
2
RESERVED
R=0
0h
Reserved
MOD
R/W
0h
Delta-Sigma Modulator mode
1-0
00: The clock speed is equal to the data rate from the modulator
01: The clock rate is half of the data rate from the modulator
10: The data from the modulator is Manchester decoded
11: The clock rate is twice the data rate of the modulator
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1701
SDFM Registers
www.ti.com
13.9.2.13 SDDFPARM2 Register (Offset = 21h) [reset = 0h]
SDDFPARM2 is shown in Figure 13-23 and described in Table 13-27.
Return to the Summary Table.
Data Filter Parameter Register for Ch2
Figure 13-23. SDDFPARM2 Register
15
14
RESERVED
13
6
5
7
12
SDSYNCEN
R/W-0h
11
4
3
10
9
AE
R/W-0h
8
FEN
R/W-0h
2
1
0
SST
R/W-0h
DOSR
R/W-0h
Table 13-27. SDDFPARM2 Register Field Descriptions
Field
Type
Reset
Description
15-13
Bit
RESERVED
R
0h
Reserved
12
SDSYNCEN
R/W
0h
Data Filter Reset enable for External Reset typ from PWM Compare
output.
0: Data filter cannot be reset by external PWM compare output
1: Data filter can be reset by external PWM compare output
Reset type: SYSRSn
11-10
SST
R/W
0h
Data filter structure.
00: Data filter runs with a Sincfast structure
01: Data filter runs with a Sinc1 structure
10: Data filter runs with a Sinc2 structure
11: Data filter runs with a Sinc3 structure
Reset type: SYSRSn
9
AE
R/W
0h
Acknowledge enable.
0: Acknowledge flag is disabled for the particular filter
1: Acknowledge flag is enabled for the particular filter
Reset type: SYSRSn
8
FEN
R/W
0h
Filter enable.
0: The filter is disabled and no data is produced
1: The filter is enabled and data are produced in the Data filter
Reset type: SYSRSn
7-0
DOSR
R/W
0h
Oversampling ratio. The actual rate is DOSR + 1.
These bits set the oversampling ratio of the filter.
0x0FF represents an oversampling ratio of 256.
Reset type: SYSRSn
1702
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
13.9.2.14 SDDPARM2 Register (Offset = 22h) [reset = 0h]
SDDPARM2 is shown in Figure 13-24 and described in Table 13-28.
Return to the Summary Table.
Integer Parameter Register for Ch2
Figure 13-24. SDDPARM2 Register
15
14
13
SH
R/W-0h
12
11
10
DR
R/W-0h
9
RESERVED
R/W-0h
8
RESERVED
R/W-0h
7
RESERVED
6
5
4
3
RESERVED
R/W-0h
2
1
0
Table 13-28. SDDPARM2 Register Field Descriptions
Bit
15-11
Field
Type
Reset
Description
SH
R/W
0h
Shift Control
These bits indicate by how many bits the 16-bit window is shifted up
when 16-bit data representation is chosen.
Reset type: SYSRSn
10
DR
R/W
0h
Data representation
0: Data stored in 16b 2's complement
1: Data stored in 32b 2's complement
Reset type: SYSRSn
9
RESERVED
R/W
0h
Reserved
8
RESERVED
R/W
0h
Reserved
7
RESERVED
R=0
0h
Reserved
6-0
RESERVED
R/W
0h
Reserved
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1703
SDFM Registers
www.ti.com
13.9.2.15 SDCMPH2 Register (Offset = 23h) [reset = 0h]
SDCMPH2 is shown in Figure 13-25 and described in Table 13-29.
Return to the Summary Table.
High-level Threshold Register for Ch2
Figure 13-25. SDCMPH2 Register
15
RESERVED
14
13
12
7
6
5
4
11
HLT
R/W-0h
10
9
8
3
2
1
0
HLT
R/W-0h
Table 13-29. SDCMPH2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R=0
0h
Reserved
HLT
R/W
0h
Unsigned high-level threshold for the comparator filter output.
Reset type: SYSRSn
14-0
1704
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
13.9.2.16 SDCMPL2 Register (Offset = 24h) [reset = 0h]
SDCMPL2 is shown in Figure 13-26 and described in Table 13-30.
Return to the Summary Table.
Low-level Threshold Register for Ch2
Figure 13-26. SDCMPL2 Register
15
RESERVED
14
13
12
7
6
5
4
11
LLT
R/W-0h
10
9
8
3
2
1
0
LLT
R/W-0h
Table 13-30. SDCMPL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R=0
0h
Reserved
LLT
R/W
0h
Unsigned low-level threshold for the comparator filter output.
Reset type: SYSRSn
14-0
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1705
SDFM Registers
www.ti.com
13.9.2.17 SDCPARM2 Register (Offset = 25h) [reset = 0h]
SDCPARM2 is shown in Figure 13-27 and described in Table 13-31.
Return to the Summary Table.
Comparator Parameter Register for Ch2
Figure 13-27. SDCPARM2 Register
15
14
13
12
11
10
9
MFIE
R/W-0h
8
CS1_CS0
R/W-0h
4
3
2
COSR
R/W-0h
1
0
RESERVED
7
CS1_CS0
R/W-0h
6
IEL
R/W-0h
5
IEH
R/W-0h
Table 13-31. SDCPARM2 Register Field Descriptions
Bit
15-10
9
Field
Type
Reset
Description
RESERVED
R=0
0h
Reserved
MFIE
R/W
0h
0: The modulator failure flag as well as the output INT is disabled for
this particular flag
1: The modulator failure flag is enabled
Reset type: SYSRSn
8-7
CS1_CS0
R/W
0h
Comparator filter structure.
00: Comparator filter runs with a sincfast structure
01: Comparator filter runs with a Sinc1 structure
10: Comparator filter runs with a Sinc2 structure
11: Comparator filter runs with a Sinc3 structure
Reset type: SYSRSn
6
IEL
R/W
0h
Low-level interrupt enable.
0: The low-level interrupt flag as well as the output INT is disabled
for this particular flag
1: The low-level interrupt flag is enabled
Reset type: SYSRSn
5
IEH
R/W
0h
High-level interrupt enable.
0: The high-level interrupt flag as well as the output INT is disabled
for this particular flag
1: The high-level interrupt flag is enabled
Reset type: SYSRSn
4-0
COSR
R/W
0h
Oversampling ratio. The actual rate is COSR + 1.
These bits set the oversampling ratio of the filter.
0x1F represents an oversampling ratio of 31.
Reset type: SYSRSn
1706
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
13.9.2.18 SDDATA2 Register (Offset = 26h) [reset = 0h]
SDDATA2 is shown in Figure 13-28 and described in Table 13-32.
Return to the Summary Table.
Filter Data Register (16 or 32bit) for Ch2
Figure 13-28. SDDATA2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA32HI
R-0h
9
8 7 6
DATA16
R-0h
5
4
3
2
1
0
Table 13-32. SDDATA2 Register Field Descriptions
Field
Type
Reset
Description
31-16
Bit
DATA32HI
R
0h
Hi-order 16b in 32b mode
Reset type: SYSRSn
15-0
DATA16
R
0h
16-bit data in 16-bit mode
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1707
SDFM Registers
www.ti.com
13.9.2.19 SDCTLPARM3 Register (Offset = 30h) [reset = 0h]
SDCTLPARM3 is shown in Figure 13-29 and described in Table 13-33.
Return to the Summary Table.
Control Parameter Register for Ch3
Figure 13-29. SDCTLPARM3 Register
15
14
13
12
11
10
9
3
RESERVED
2
RESERVED
1
8
RESERVED
7
6
RESERVED
5
4
RESERVED
0
MOD
R/W-0h
Table 13-33. SDCTLPARM3 Register Field Descriptions
Field
Type
Reset
Description
15-5
Bit
RESERVED
R
0h
Reserved
4
RESERVED
R=0
0h
Reserved
3
RESERVED
R=0
0h
Reserved
2
RESERVED
R=0
0h
Reserved
MOD
R/W
0h
Delta-Sigma Modulator mode
1-0
00: The clock speed is equal to the data rate from the modulator
01: The clock rate is half of the data rate from the modulator
10: The data from the modulator is Manchester decoded
11: The clock rate is twice the data rate of the modulator
Reset type: SYSRSn
1708
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
13.9.2.20 SDDFPARM3 Register (Offset = 31h) [reset = 0h]
SDDFPARM3 is shown in Figure 13-30 and described in Table 13-34.
Return to the Summary Table.
Data Filter Parameter Register for Ch3
Figure 13-30. SDDFPARM3 Register
15
14
RESERVED
13
6
5
7
12
SDSYNCEN
R/W-0h
11
4
3
10
9
AE
R/W-0h
8
FEN
R/W-0h
2
1
0
SST
R/W-0h
DOSR
R/W-0h
Table 13-34. SDDFPARM3 Register Field Descriptions
Field
Type
Reset
Description
15-13
Bit
RESERVED
R
0h
Reserved
12
SDSYNCEN
R/W
0h
Data Filter Reset enable for External Reset typ from PWM Compare
output.
0: Data filter cannot be reset by external PWM compare output
1: Data filter can be reset by external PWM compare output
Reset type: SYSRSn
11-10
SST
R/W
0h
Data filter structure.
00: Data filter runs with a Sincfast structure
01: Data filter runs with a Sinc1 structure
10: Data filter runs with a Sinc2 structure
11: Data filter runs with a Sinc3 structure
Reset type: SYSRSn
9
AE
R/W
0h
Acknowledge enable.
0: Acknowledge flag is disabled for the particular filter
1: Acknowledge flag is enabled for the particular filter
Reset type: SYSRSn
8
FEN
R/W
0h
Filter enable.
0: The filter is disabled and no data is produced
1: The filter is enabled and data are produced in the data filter
Reset type: SYSRSn
7-0
DOSR
R/W
0h
Oversampling ratio. The actual rate is DOSR + 1.
These bits set the oversampling ratio of the filter.
0x0FF represents an oversampling ratio of 256.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1709
SDFM Registers
www.ti.com
13.9.2.21 SDDPARM3 Register (Offset = 32h) [reset = 0h]
SDDPARM3 is shown in Figure 13-31 and described in Table 13-35.
Return to the Summary Table.
Integer Parameter Register for Ch3
Figure 13-31. SDDPARM3 Register
15
14
13
SH
R/W-0h
12
11
10
DR
R/W-0h
9
RESERVED
R/W-0h
8
RESERVED
R/W-0h
7
RESERVED
6
5
4
3
RESERVED
R/W-0h
2
1
0
Table 13-35. SDDPARM3 Register Field Descriptions
Bit
15-11
Field
Type
Reset
Description
SH
R/W
0h
Shift Control
These bits indicate by how many bits the 16-bit window is shifted up
when 16-bit data representation is chosen.
Reset type: SYSRSn
10
DR
R/W
0h
Data representation
0: Data stored in 16b 2's complement
1: Data stored in 32b 2's complement
Reset type: SYSRSn
1710
9
RESERVED
R/W
0h
Reserved
8
RESERVED
R/W
0h
Reserved
7
RESERVED
R=0
0h
Reserved
6-0
RESERVED
R/W
0h
Reserved
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
13.9.2.22 SDCMPH3 Register (Offset = 33h) [reset = 0h]
SDCMPH3 is shown in Figure 13-32 and described in Table 13-36.
Return to the Summary Table.
High-level Threshold Register for Ch3
Figure 13-32. SDCMPH3 Register
15
RESERVED
14
13
12
7
6
5
4
11
HLT
R/W-0h
10
9
8
3
2
1
0
HLT
R/W-0h
Table 13-36. SDCMPH3 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R=0
0h
Reserved
HLT
R/W
0h
Unsigned high-level threshold for the comparator filter output.
Reset type: SYSRSn
14-0
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1711
SDFM Registers
www.ti.com
13.9.2.23 SDCMPL3 Register (Offset = 34h) [reset = 0h]
SDCMPL3 is shown in Figure 13-33 and described in Table 13-37.
Return to the Summary Table.
Low-level Threshold Register for Ch3
Figure 13-33. SDCMPL3 Register
15
RESERVED
14
13
12
7
6
5
4
11
LLT
R/W-0h
10
9
8
3
2
1
0
LLT
R/W-0h
Table 13-37. SDCMPL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R=0
0h
Reserved
LLT
R/W
0h
Unsigned low-level threshold for the comparator filter output.
Reset type: SYSRSn
14-0
1712
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
13.9.2.24 SDCPARM3 Register (Offset = 35h) [reset = 0h]
SDCPARM3 is shown in Figure 13-34 and described in Table 13-38.
Return to the Summary Table.
Comparator Parameter Register for Ch3
Figure 13-34. SDCPARM3 Register
15
14
13
12
11
10
9
MFIE
R/W-0h
8
CS1_CS0
R/W-0h
4
3
2
COSR
R/W-0h
1
0
RESERVED
7
CS1_CS0
R/W-0h
6
IEL
R/W-0h
5
IEH
R/W-0h
Table 13-38. SDCPARM3 Register Field Descriptions
Bit
15-10
9
Field
Type
Reset
Description
RESERVED
R=0
0h
Reserved
MFIE
R/W
0h
0: The modulator failure flag as well as the output INT is disabled for
this particular flag
1: The modulator failure flag is enabled
Reset type: SYSRSn
8-7
CS1_CS0
R/W
0h
Comparator filter structure.
00: Comparator filter runs with a sincfast structure
01: Comparator filter runs with a Sinc1 structure
10: Comparator filter runs with a Sinc2 structure
11: Comparator filter runs with a Sinc3 structure
Reset type: SYSRSn
6
IEL
R/W
0h
Low-level interrupt enable.
0: The low-level interrupt flag as well as the output INT is disabled
for this particular flag
1: The low-level interrupt flag is enabled
Reset type: SYSRSn
5
IEH
R/W
0h
High-level interrupt enable.
0: The high-level interrupt flag as well as the output INT is disabled
for this particular flag
1: The high-level interrupt flag is enabled
Reset type: SYSRSn
4-0
COSR
R/W
0h
Oversampling ratio. The actual rate is COSR + 1.
These bits set the oversampling ratio of the filter.
0x1F represents an oversampling ratio of 31.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1713
SDFM Registers
www.ti.com
13.9.2.25 SDDATA3 Register (Offset = 36h) [reset = 0h]
SDDATA3 is shown in Figure 13-35 and described in Table 13-39.
Return to the Summary Table.
Filter Data Register (16 or 32bit) for Ch3
Figure 13-35. SDDATA3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA32HI
R-0h
9
8 7 6
DATA16
R-0h
5
4
3
2
1
0
Table 13-39. SDDATA3 Register Field Descriptions
Field
Type
Reset
Description
31-16
Bit
DATA32HI
R
0h
Hi-order 16b in 32b mode
Reset type: SYSRSn
15-0
DATA16
R
0h
16-bit data in 16-bit mode
Reset type: SYSRSn
1714
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
13.9.2.26 SDCTLPARM4 Register (Offset = 40h) [reset = 0h]
SDCTLPARM4 is shown in Figure 13-36 and described in Table 13-40.
Return to the Summary Table.
Control Parameter Register for Ch4
Figure 13-36. SDCTLPARM4 Register
15
14
13
12
11
10
9
3
RESERVED
2
RESERVED
1
8
RESERVED
7
6
RESERVED
5
4
RESERVED
0
MOD
R/W-0h
Table 13-40. SDCTLPARM4 Register Field Descriptions
Field
Type
Reset
Description
15-5
Bit
RESERVED
R
0h
Reserved
4
RESERVED
R=0
0h
Reserved
3
RESERVED
R=0
0h
Reserved
2
RESERVED
R=0
0h
Reserved
MOD
R/W
0h
Delta-Sigma Modulator mode
1-0
00: The clock speed is equal to the data rate from the modulator
01: The clock rate is half of the data rate from the modulator
10: The data from the modulator is Manchester decoded
11: The clock rate is twice the data rate of the modulator
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1715
SDFM Registers
www.ti.com
13.9.2.27 SDDFPARM4 Register (Offset = 41h) [reset = 0h]
SDDFPARM4 is shown in Figure 13-37 and described in Table 13-41.
Return to the Summary Table.
Data Filter Parameter Register for Ch4
Figure 13-37. SDDFPARM4 Register
15
14
RESERVED
13
6
5
7
12
SDSYNCEN
R/W-0h
11
4
3
10
9
AE
R/W-0h
8
FEN
R/W-0h
2
1
0
SST
R/W-0h
DOSR
R/W-0h
Table 13-41. SDDFPARM4 Register Field Descriptions
Field
Type
Reset
Description
15-13
Bit
RESERVED
R
0h
Reserved
12
SDSYNCEN
R/W
0h
Data Filter Reset enable for External Reset typ from PWM Compare
output.
0: Data filter cannot be reset by external PWM compare output
1: Data filter can be reset by external PWM compare output
Reset type: SYSRSn
11-10
SST
R/W
0h
Data filter structure.
00: Data filter runs with a Sincfast structure
01: Data filter runs with a Sinc1 structure
10: Data filter runs with a Sinc2 structure
11: Data filter runs with a Sinc3 structure
Reset type: SYSRSn
9
AE
R/W
0h
Acknowledge enable.
0: Acknowledge flag is disabled for the particular filter
1: Acknowledge flag is enabled for the particular filter
Reset type: SYSRSn
8
FEN
R/W
0h
Filter enable.
0: The filter is disabled and no data is produced
1: The filter is enabled and data are produced in the sinc filter
Reset type: SYSRSn
7-0
DOSR
R/W
0h
Oversampling ratio. The actual rate is DOSR + 1.
These bits set the oversampling ratio of the filter.
0x0FF represents an oversampling ratio of 256.
Reset type: SYSRSn
1716
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
13.9.2.28 SDDPARM4 Register (Offset = 42h) [reset = 0h]
SDDPARM4 is shown in Figure 13-38 and described in Table 13-42.
Return to the Summary Table.
Integer Parameter Register for Ch4
Figure 13-38. SDDPARM4 Register
15
14
13
SH
R/W-0h
12
11
10
DR
R/W-0h
9
RESERVED
R/W-0h
8
RESERVED
R/W-0h
7
RESERVED
6
5
4
3
RESERVED
R/W-0h
2
1
0
Table 13-42. SDDPARM4 Register Field Descriptions
Bit
15-11
Field
Type
Reset
Description
SH
R/W
0h
Shift Control
These bits indicate by how many bits the 16-bit window is shifted up
when 16-bit data representation is chosen.
Reset type: SYSRSn
10
DR
R/W
0h
Data representation
0: Data stored in 16b 2's complement
1: Data stored in 32b 2's complement
Reset type: SYSRSn
9
RESERVED
R/W
0h
Reserved
8
RESERVED
R/W
0h
Reserved
7
RESERVED
R=0
0h
Reserved
6-0
RESERVED
R/W
0h
Reserved
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1717
SDFM Registers
www.ti.com
13.9.2.29 SDCMPH4 Register (Offset = 43h) [reset = 0h]
SDCMPH4 is shown in Figure 13-39 and described in Table 13-43.
Return to the Summary Table.
High-level Threshold Register for Ch4
Figure 13-39. SDCMPH4 Register
15
RESERVED
14
13
12
7
6
5
4
11
HLT
R/W-0h
10
9
8
3
2
1
0
HLT
R/W-0h
Table 13-43. SDCMPH4 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R=0
0h
Reserved
HLT
R/W
0h
Unsigned high-level threshold for the comparator filter output.
Reset type: SYSRSn
14-0
1718
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
13.9.2.30 SDCMPL4 Register (Offset = 44h) [reset = 0h]
SDCMPL4 is shown in Figure 13-40 and described in Table 13-44.
Return to the Summary Table.
Low-level Threshold Register for Ch4
Figure 13-40. SDCMPL4 Register
15
RESERVED
14
13
12
7
6
5
4
11
LLT
R/W-0h
10
9
8
3
2
1
0
LLT
R/W-0h
Table 13-44. SDCMPL4 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R=0
0h
Reserved
LLT
R/W
0h
Unsigned low-level threshold for the comparator filter output.
Reset type: SYSRSn
14-0
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1719
SDFM Registers
www.ti.com
13.9.2.31 SDCPARM4 Register (Offset = 45h) [reset = 0h]
SDCPARM4 is shown in Figure 13-41 and described in Table 13-45.
Return to the Summary Table.
Comparator Parameter Register for Ch4
Figure 13-41. SDCPARM4 Register
15
14
13
12
11
10
9
MFIE
R/W-0h
8
CS1_CS0
R/W-0h
4
3
2
COSR
R/W-0h
1
0
RESERVED
7
CS1_CS0
R/W-0h
6
IEL
R/W-0h
5
IEH
R/W-0h
Table 13-45. SDCPARM4 Register Field Descriptions
Bit
15-10
9
Field
Type
Reset
Description
RESERVED
R=0
0h
Reserved
MFIE
R/W
0h
0: The modulator failure flag as well as the output INT is disabled for
this particular flag
1: The modulator failure flag is enabled
Reset type: SYSRSn
8-7
CS1_CS0
R/W
0h
Comparator filter structure.
00: Comparator filter runs with a sincfast structure
01: Comparator filter runs with a Sinc1 structure
10: Comparator filter runs with a Sinc2 structure
11: Comparator filter runs with a Sinc3 structure
Reset type: SYSRSn
6
IEL
R/W
0h
Low-level interrupt enable.
0: The low-level interrupt flag as well as the output INT is disabled
for this particular flag
1: The low-level interrupt flag is enabled
Reset type: SYSRSn
5
IEH
R/W
0h
High-level interrupt enable.
0: The high-level interrupt flag as well as the output INT is disabled
for this particular flag
1: The high-level interrupt flag is enabled
Reset type: SYSRSn
4-0
COSR
R/W
0h
Oversampling ratio. The actual rate is COSR + 1.
These bits set the oversampling ratio of the filter.
0x1F represents an oversampling ratio of 31.
Reset type: SYSRSn
1720
Sigma Delta Filter Module (SDFM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
13.9.2.32 SDDATA4 Register (Offset = 46h) [reset = 0h]
SDDATA4 is shown in Figure 13-42 and described in Table 13-46.
Return to the Summary Table.
Filter Data Register (16 or 32bit) for Ch4
Figure 13-42. SDDATA4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA32HI
R-0h
9
8 7 6
DATA16
R-0h
5
4
3
2
1
0
Table 13-46. SDDATA4 Register Field Descriptions
Field
Type
Reset
Description
31-16
Bit
DATA32HI
R
0h
Hi-order 16b in 32b mode
Reset type: SYSRSn
15-0
DATA16
R
0h
16-bit data in 16-bit mode
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1721
SDFM Registers
www.ti.com
13.9.3 Register to Driverlib Function Mapping
Table 13-47. SDFM Registers to Driverlib Functions
File
Driverlib Function
SDIFLG
sdfm.h
SDFM_getThresholdStatus
sdfm.h
SDFM_getModulatorStatus
sdfm.h
SDFM_getNewFilterDataStatus
sdfm.h
SDFM_getIsrStatus
sdfm.h
SDFM_clearInterruptFlag
SDIFLGCLR
sdfm.h
SDFM_clearInterruptFlag
SDCTL
sdfm.h
SDFM_setupModulatorClock
sdfm.h
SDFM_enableMasterInterrupt
sdfm.h
SDFM_disableMasterInterrupt
SDMFILEN
sdfm.h
SDFM_enableMasterFilter
sdfm.h
SDFM_disableMasterFilter
SDCTLPARM1
sdfm.h
SDFM_setupModulatorClock
SDDFPARM1
sdfm.h
SDFM_enableExternalReset
sdfm.h
SDFM_disableExternalReset
sdfm.h
SDFM_enableFilter
sdfm.h
SDFM_disableFilter
sdfm.h
SDFM_setFilterType
sdfm.h
SDFM_setFilterOverSamplingRatio
sdfm.h
SDFM_enableInterrupt
sdfm.h
SDFM_disableInterrupt
SDDPARM1
sdfm.h
SDFM_setOutputDataFormat
sdfm.h
SDFM_setDataShiftValue
SDCMPH1
sdfm.h
SDFM_setCompFilterHighThreshold
SDCMPL1
sdfm.h
SDFM_setCompFilterLowThreshold
SDCPARM1
sdfm.h
SDFM_enableInterrupt
sdfm.h
SDFM_disableInterrupt
sdfm.h
SDFM_setComparatorFilterType
sdfm.h
SDFM_setCompFilterOverSamplingRatio
SDDATA1
sdfm.h
SDFM_getFilterData
SDCTLPARM2
-
See SDCTLPARM1
SDDFPARM2
-
See SDDFPARM1
SDDPARM2
1722Sigma Delta Filter Module (SDFM)
See SDDPARM1
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
SDFM Registers
www.ti.com
Table 13-47. SDFM Registers to Driverlib Functions (continued)
File
Driverlib Function
SDCMPH2
-
See SDCMPH1
SDCMPL2
-
See SDCMPL1
SDCPARM2
-
See SDCPARM1
SDDATA2
-
See SDDATA1
SDCTLPARM3
-
See SDCTLPARM1
SDDFPARM3
-
See SDDFPARM1
SDDPARM3
-
See SDDPARM1
SDCMPH3
-
See SDCMPH1
SDCMPL3
-
See SDCMPL1
SDCPARM3
-
See SDCPARM1
SDDATA3
-
See SDDATA1
SDCTLPARM4
-
See SDCTLPARM1
SDDFPARM4
-
See SDDFPARM1
SDDPARM4
-
See SDDPARM1
SDCMPH4
-
See SDCMPH1
SDCMPL4
-
See SDCMPL1
SDCPARM4
-
See SDCPARM1
SDDATA4
-
See SDDATA1
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Sigma Delta Filter Module (SDFM)
1723
Chapter 14
SPRUHM9F – October 2014 – Revised September 2019
Enhanced Pulse Width Modulator (ePWM)
The enhanced pulse width modulator (ePWM) peripheral is a key element in controlling many of the power
electronic systems found in both commercial and industrial equipment. These systems include digital
motor control, switch mode power supply control, uninterruptible power supplies (UPS), and other forms of
power conversion. The ePWM peripheral can also perform a digital to analog (DAC) function, where the
duty cycle is equivalent to a DAC analog value; it is sometimes referred to as a power DAC.
This chapter is applicable for ePWM type 4 with added register protection capability. See the
TMS320x28xx, 28xxx DSP Peripheral Reference Guide for a list of all devices with an ePWM module of
the same type, to determine the differences between the types, and for a list of device-specific differences
within a type.
Further information can be found in the following document(s):
• Flexible PWMs Enable Multi-Axis Drives, Multi-Level Inverters
Topic
...........................................................................................................................
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10
14.11
14.12
14.13
14.14
14.15
1724
Introduction ...................................................................................................
Configuring Device Pins ..................................................................................
ePWM Modules Overview .................................................................................
Time-Base (TB) Submodule ..............................................................................
Counter-Compare (CC) Submodule ...................................................................
Action-Qualifier (AQ) Submodule ......................................................................
Dead-Band Generator (DB) Submodule .............................................................
PWM Chopper (PC) Submodule .......................................................................
Trip-Zone (TZ) Submodule ...............................................................................
Event-Trigger (ET) Submodule ........................................................................
Digital Compare (DC) Submodule ....................................................................
ePWM X-BAR ................................................................................................
Applications to Power Topologies ...................................................................
High-Resolution Pulse Width Modulator (HRPWM) ............................................
ePWM Registers ............................................................................................
Enhanced Pulse Width Modulator (ePWM)
Page
1725
1732
1732
1734
1745
1751
1765
1771
1775
1780
1786
1794
1796
1814
1841
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Introduction
www.ti.com
14.1 Introduction
This chapter includes an overview and information about each submodule:
• Time-Base Submodule
• Counter Compare Submodule
• Action Qualifier Submodule
• Dead-Band Generator Submodule
• PWM Chopper (PC) Submodule
• Trip Zone Submodule
• Event Trigger Submodule
• Digital Compare Submodule
The ePWM Type 4 is functionally compatible to Type 2 (a Type 3 does not exist). Type 4 has the following
enhancements in addition to the Type 2 features:
• Register Address Map
Additional registers are required for new features on ePWM Type 4. The ePWM register address
space has been remapped for better alignment and easy usage.
• Delayed Trip Functionality
Changes have been added to achieve deadband insertion capabilities to support, for example, delayed
trip functionality needed for peak current mode control type application scenarios. This has been
accomplished by allowing comparator events to go into the Action Qualifier as a trigger event ( Events
T1 and T2 ). If comparator T1 / T2 events are used to edit the PWM, changes to the PWM waveform
will not take place immediately. Instead, they will synchronize to the next TBCLK.
• Dead-Band Generator Submodule Enhancements
Shadowing of the DBCTL register to allow dynamic configuration changes.
• One Shot and Global Load of Registers
The ePWM Type 4 allows one shot and global load capability from shadow to active registers to avoid
partial loads in, for example, multi-phase applications. It also allows a programmable prescale of
shadow to active load events. ePWM Type 4 Global Load can simplify ePWM software by removing
interrupts and ensuring that all registers are loaded at the same time.
• Trip Zone Submodule Enhancements
Independent flags have been added to reflect the trip status for each of the TZ sources. Changes have
been made to the trip zone submodule to support certain power converter switching techniques like
valley switching.
• Digital Compare Submodule Enhancements
Blanking window filter register width has been increased from 8 to 16 bits. DCCAP functionality has
been enhanced to provide more programmability.
• PWM SYNC Related Enhancements
The ePWM Type 4 allows PWM SYNCOUT generation based on CMPC and CMPD events. These
events can also be used for PWMSYNC pulse selection.
The ePWM Type 2 is fully compatible to Type 1. Type 2 has the following enhancements in addition to the
Type 1 features:
• High Resolution Dead-Band Capability
High resolution capability is added to dead-band RED and FED in half-cycle clocking mode.
• Dead-Band Generator Submodule Enhancements
The ePWM Type 2 has features to enable both RED and FED on either PWM outputs. Provides
increased dead band with 14-bit counters and dead-band / dead-band high-resolution registers are
shadowed
• High Resolution Extension available on ePWMxB outputs
Provides the ability to enable high-resolution period and duty cycle control on ePWMxB outputs. This is
discussed in more detail in Section 14.14.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1725
Introduction
•
•
•
•
•
www.ti.com
Counter Compare Submodule Enhancements
The ePWM Type 2 allows Interrupts and SOC events to be generated by additional counter compares
CMPC and CMPD.
Event Trigger Submodule Enhancements
Prescaling logic to issue interrupt requests and ADC start of conversion expanded up to every 15
events. It allows software initialization of event counters on SYNC event.
Digital Compare Submodule Enhancements
Digital Compare Trip Select logic [DCTRIPSEL] has up to 12 external trip sources selected by the
Input X-BAR logic in addition to an ability to OR all of them (up to 14 [external and internal sources]) to
create the respective DCxEVTs.
Simultaneous Writes to TBPRD and CMPx Registers
This feature allows writes to TBPRD, CMPA:CMPAHR, CMPB:CMPBHR, CMPC and CMPD of any
ePWM module to be tied to any other ePWM module, and also allows all ePWM modules to be tied to
a particular ePWM module if desired.
Shadow to Active Load on SYNC of TBPRD and CMP Registers
This feature supports simultaneous writes of TBPRD and CMPA/B/C/D registers.
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU
overhead or intervention. It must be highly programmable and very flexible while being easy to understand
and use. The ePWM unit described here addresses these requirements by allocating all needed timing
and control resources on a per PWM channel basis. Cross coupling or sharing of resources has been
avoided; instead, the ePWM is built up from smaller single channel submodules with separate resources
that can operate together as required to form a system. This modular approach results in an orthogonal
architecture and provides a more transparent view of the peripheral structure, helping users to understand
its operation quickly.
In this document, the letter x within a signal or submodule name is used to indicate a generic ePWM
instance on a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from
the ePWMx instance. Thus, EPWM1A and EPWM1B belong to ePWM1 and likewise EPWM4A and
EPWM4B belong to ePWM4.
Type0 to Type1 Enhancements
• Increased Dead-Band Resolution
Dead-band clocking has been enhanced to allow half-cycle clocking to double resolution.
• Enhanced Interrupt and SOC Generation
Interrupts and ADC start-of-conversion can now be generated on both the TBCTR == zero and TBCTR
== period events. This feature enables dual edge PWM control. Additionally, the ADC start-ofconversion can be generated from an event defined in the digital compare submodule.
• High Resolution Period Capability
Provides the ability to enable high-resolution period. This is discussed in more detail in the devicespecific High-Resolution Pulse Width Modulator (HRPWM) document..
• Digital Compare Submodule
The digital compare submodule enhances the event triggering and trip zone submodules by providing
filtering, blanking and improved trip functionality to digital compare signals. Such features are essential
for peak current mode control and for support of analog comparators.
NOTE: The name of the sync signal that goes to the CMPSS and GPDAC has been updated from
PWMSYNC to EPWMSYNCPER (SYNCPER/PWMSYNCPER/EPWMxSYNCPER) to avoid
confusion with the other EPWM sync signals EPWMSYNCI and EPWMSYNCO. For a
description of what these signals are, see Table 14-2.
1726
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Introduction
www.ti.com
14.1.1 Submodule Overview
The ePWM module represents one complete PWM channel composed of two PWM outputs: EPWMxA
and EPWMxB. Multiple ePWM modules are instanced within a device as shown in Figure 14-1. Each
ePWM instance is identical with one exception. Some instances include a hardware extension that allows
more precise control of the PWM outputs. This extension is the high-resolution pulse width modulator
(HRPWM) and is described in Section 14.14. See the device-specific data manual to determine which
ePWM instances include this feature. Each ePWM module is indicated by a numerical value starting with
1. For example ePWM1 is the first instance and ePWM3 is the third instance in the system and ePWMx
indicates any instance.
The ePWM modules are chained together via a clock synchronization scheme that allows them to operate
as a single system when required. Additionally, this synchronization scheme can be extended to the
capture peripheral submodules (eCAP). The number of submodules is device-dependent and based on
target application needs. Submodules can also operate standalone.
Each ePWM module supports the following features:
• Dedicated 16-bit time-base counter with period and frequency control
• Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations:
– Two independent PWM outputs with single-edge operation
– Two independent PWM outputs with dual-edge symmetric operation
– One independent PWM output with dual-edge asymmetric operation
• Asynchronous override control of PWM signals through software.
• Programmable phase-control support for lag or lead operation relative to other ePWM modules.
• Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis.
• Dead-band generation with independent rising and falling edge delay control.
• Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions.
• A trip condition can force either high, low, or high-impedance state logic levels at PWM outputs.
• All events can trigger both CPU interrupts and ADC start of conversion (SOC)
• Programmable event prescaling minimizes CPU overhead on interrupts.
• PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives.
Each ePWM module is connected to the input/output signals shown in Figure 14-1. The signals are
described in detail in subsequent sections.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1727
Introduction
www.ti.com
Figure 14-1. Multiple ePWM Modules
To PWMs
INPUTXBAR5
SYNC SCHEME
INPUTXBAR6
ECCDBLERR
PIEERR
EPWM1TZINT
EPWM1
Module
EPWM1INT
TZ1 to TZ3
EPWM2TZINT
PIE
EPWM2INT
TZ4
EPWMxTZINT
TZ5
EPWMxINT
TZ6
From PWMs
EQEPxERR
CLOCKFAIL
EMUSTOP
EPWM1ENCLK
TBCLKSYNC
TZ1 to TZ3
EPWM XBAR
INPUTXBAR1
INPUTXBAR2
INPUTXBAR3
ECCDBLERR
PIEERR
EPWM2
Module
TZ4
TZ5
TZ6
EQEPxERR
ePWM1A/ePWM1B
H
R
P
W
M
CLOCKFAIL
EMUSTOP
EPWM2ENCLK
TBCLKSYNC
ePWMxA/ePWMxB
G
P
I
O
Peripheral Bus
SOCA1
SOCB1
SOCA2
ADC
ePWM2A/ePWM2B
SOCB2
M
U
X
EQEP1ERR
TZ1 to TZ3
SOCAx
EPWMx
Module
SOCBx
EQEPnERR
TZ4
TZ5
TZ6
EQEPxERR
CLOCKFAIL
EMUSTOP
EPWMxENCLK
PIE
TBCLKSYNC
28x RAM/Flash
ECC
ECCDBLERR
PIEERR
System Control
PIEERR
ECCDBLERR
C28x CPU
Copyright © 2017, Texas Instruments Incorporated
A
This signal exists only on devices with an eQEP submodule.
The order in which the ePWM modules are connected may differ from what is shown in Figure 14-1. See
Section 14.4.3.3 for the synchronization scheme for a particular device. Each ePWM module consists of
eight submodules and is connected within a system via the signals shown in Figure 14-2.
1728
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Introduction
www.ti.com
Figure 14-2. Submodules and Signal Connections for an ePWM Module
EPWMxSYNCI
ECCDBLERR
ePWM submodule
GPIO
MUX
EPWMxSYNCO
EMUSTOP
COMPxOUT
CLOCKFAIL
EQEPxERR
Time-base (TB) submodule
EPWMxTZINT
PIE
EPWMxINT
PIEERR
Counter-compare (CC) submodule
ePWMxA
Action-qualifier (AQ) submodule
ePWMxB
GPIO
MUX
EPWMxSOCA
ADC
Dead-band (DB) submodule
EPWMxSOCB
PWM-chopper (PC) submodule
Peripheral bus
Event-trigger (ET) submodule
INPUTXBAR
Trip-zone (TZ) submodule
TZ1 to TZ3
Digital Compare (DC) submodule
TRIPIN1
TRIPIN2
TRIPIN3
TRIPIN4
TRIPIN5
TRIPIN6
TRIPIN7
TRIPIN8
TRIPIN9
TRIPIN10
TRIPIN11
TRIPIN12
Figure 14-3 shows more internal details of a single ePWM module. The main signals used by the ePWM
module are:
• PWM output signals (EPWMxA and EPWMxB).
The PWM output signals are made available external to the device through the GPIO peripheral
described in the System Control and Interrupts chapter for your device.
• Trip-zone signals (TZ1 to TZ6).
These input signals alert the ePWM module of fault conditions external to the ePWM module. Each
submodule on a device can be configured to either use or ignore any of the trip-zone signals. The TZ1
to TZ3 trip-zone signals can be configured as asynchronous inputs through the GPIO peripheral using
the Input X-BAR logic, refer to . TZ4 is connected to an inverted EQEPx error signal (EQEPxERR),
which can be generated from any one of the EQEP submodule (for those devices with an EQEP
module). TZ5 is connected to the system clock fail logic, and TZ6 is connected to the EMUSTOP
output from the CPU. This allows you to configure a trip action when the clock fails or the CPU halts.
• Time-base synchronization input (EPWMxSYNCI), output (EPWMxSYNCO) and peripheral
(EPWMxSYNCPER) signals.
The synchronization signals daisy chain the ePWM module together. Each module can be configured
via INPUTXBAR6 to either use or ignore its synchronization input. The clock synchronization input and
output signal are brought out to pins only for ePWM1 (ePWM module #1). The ePWM module are
separate into groups of three for syncing purposes. An external sync signal (EXTSYNCIN1 or
EXTSYNCIN2) may be used to issue a sync signal to the first ePWM module in each chain. These
same module can also send their EPWMxSYNCOUT signal to a GPIO. For more information, see
Section 14.4.3.3.
Each ePWM module also generates another PWMSYNC signal called EPWMxSYNCPER.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1729
Introduction
•
•
•
1730
www.ti.com
EPWMxSYNCPER goes to the GPDAC and CMPSS for synchronization purposes. It is configured
using the HRPCTL register but has no relation with the HRPWM. For more information on how
EPWMxSYNCPER is used by the GPDAC and CMPSS, see their respective chapters.
ADC start-of-conversion signals (EPWMxSOCA and EPWMxSOCB).
Each ePWM module has two ADC start of conversion signals. Any ePWM module can trigger a start of
conversion. Whichever event triggers the start of conversion is configured in the event-trigger
submodule of the ePWM.
Comparator output signals (COMPxOUT).
Output signals from the comparator module can be fed through the Input X-BAR to one or all of the 12
trip inputs [TRIPIN1 - TRIPIN12] and in conjunction with the trip zone signals can generate digital
compare events.
Peripheral Bus
The peripheral bus is 32-bits wide and allows both 16-bit and 32-bit writes to the ePWM register file.
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Introduction
www.ti.com
Figure 14-3. ePWM modules and Critical Internal Signal Interconnects
TBCTL2[SYNCOSELX]
Time-Base (TB)
Disable
CTR=CMPC
CTR=CMPD
Rsvd
TBPRD Shadow (24)
TBPRDHR (8)
TBPRD Active (24)
8
CTR=PRD
00
01
10
11
CTR=ZERO
CTR=CMPB
TBCTL[SWFSYNC]
Sync
Out
Select
EPWMxSYNCO
EPWMxSYNCI
TBCTL[PHSEN]
TBCTL[SYNCOSEL]
Counter
Up/Down
(16 Bit)
(A)
DCAEVT1.sync
(A)
DCBEVT1.sync
CTR=ZERO
TBCTR
Active (16)
CTR_Dir
CTR=PRD
TBPHSHR (8)
16
8
TBPHS Active (24)
EPWMx_INT
CTR=ZERO
CTR=PRD or ZERO
Phase
Control
CTR=CMPA
CTR=CMPB
CTR=CMPC
CTR=CMPD
Counter Compare (CC)
CTR=CMPA
Event
Trigger
and
Interrupt
(ET)
EPWMxSOCA
EPWMxSOCB
ADCSOCOUTSELECT
CTR_Dir
Action
Qualifier
(AQ)
DCAEVT1.soc
DCBEVT1.soc
CMPAHR (8)
Select and pulse stretch
for external ADC
(A)
(A)
ADCSOCAO
ADCSOCBO
16
CMPA Active (24)
CMPA Shadow (24)
ePWMxA
EPWMA
Dead
Band
(DB)
CMPBHR (8)
16
HiRes PWM (HRPWM)
CMPAHR (8)
CTR=CMPB
On-chip
ADC
PWM
Chopper
(PC)
Trip
Zone
(TZ)
ePWMxB
EPWMB
CMPB Active (24)
CMPB Shadow (24)
CMPBHR (8)
EPWMx_TZ_INT
TBCNT(16)
CTR=CMPC
CMPC[15-0]
16
CMPC Active (16)
TZ1 to TZ3
EMUSTOP
CTR=ZERO
DCAEVT1.inter
DCBEVT1.inter
DCAEVT2.inter
DCBEVT2.inter
CLOCKFAIL
EQEPxERR
DCAEVT1.force
CMPC Shadow (16)
DCAEVT2.force
DCBEVT1.force
DCBEVT2.force
TBCNT(16)
(A)
(A)
(A)
(A)
CTR=CMPD
CMPD[15-0]
16
CMPD Active (16)
CMPD Shadow (16)
Copyright © 2017, Texas Instruments Incorporated
A
--*These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN
inputs.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1731
Configuring Device Pins
www.ti.com
14.2 Configuring Device Pins
To connect the device input pins to the module, the Input X-BAR must be used. Some examples of when
an external signal may be needed are TZx, TRIPx, and EXTSYNCIN. Any GPIO on the device can be
configured as an input. The GPIO input qualification should be set to asynchronous mode by setting the
appropriate GPxQSEL register bits to 11b. The internal pullups can be configured in the GPyPUD register.
Since the GPIO mode is used, the GPyINV register can invert the signals. Additionally, some TRIPx
(TRIP4-12 excluding TRIP6) signals must be routed through the ePWM X-Bar in addition to the Input XBar.
The GPIO mux registers must be configured for this peripheral. To avoid glitches on the pins, the
GPyGMUX bits must be configured first (while keeping the corresponding GPyMUX bits at the default of
zero), followed by writing the GPyMUX register to the desired value.
See the GPIO chapter for more details on GPIO mux, GPIO settings, and XBAR configuration.
14.3 ePWM Modules Overview
Eight submodules are included in every ePWM peripheral. Each of these submodules performs specific
tasks that can be configured by software.
Table 14-1 lists the eight key submodules together with a list of their main configuration parameters. For
example, if you need to adjust or control the duty cycle of a PWM waveform, then you should see the
counter-compare submodule in Section 14.5 for relevant details.
Table 14-1. Submodule Configuration Parameters
Submodule
Time Base (TB)
Configuration Parameter or Option
• Scale the time-base clock (TBCLK) relative to the ePWM clock (EPWMCLK).
• Configure the PWM time-base counter (TBCTR) frequency or period.
• Set the mode for the time-base counter:
•
•
•
•
•
•
–
count-up mode: used for asymmetric PWM
–
count-down mode: used for asymmetric PWM
– count-up-and-down mode: used for symmetric PWM
Configure the time-base phase relative to another ePWM module.
Synchronize the time-base counter between modules through hardware or software.
Configure the direction (up or down) of the time-base counter after a synchronization event.
Simultaneous writes to the TBPRD registers on all PWM's corresponding to the configuration on
EPWMXLINK.
Configure how the time-base counter will behave when the device is halted by an emulator.
Specify the source for the synchronization output of the ePWM module
–
Synchronization input signal
–
Time-base counter equal to zero
–
Time-base counter equal to counter-compare B (CMPB)
– No output synchronization signal generated.
• Configure one shot and global load of registers in this module.
Counter Compare (CC)
•
•
•
•
Specify the PWM duty cycle for output EPWMxA and/or output EPWMxB
Specify the time at which switching events occur on the EPWMxA or EPWMxB output
Specify the programmable delay for interrupt and SOC generation with additional comparators
Simultaneous writes to the CMPA, CMPB, CMPC, CMPD registers on all PWM's corresponding
to the configuration on EPWMXLINK.
• Configure one shot and global load of registers in this module.
1732Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Modules Overview
www.ti.com
Table 14-1. Submodule Configuration Parameters (continued)
Submodule
Action Qualifier (AQ)
Configuration Parameter or Option
• Specify the type of action taken when a time-base counter-compare, trip-zone submodule, or
comparator event occurs:
–
No action taken
–
Output EPWMxA and/or EPWMxB switched high
–
Output EPWMxA and/or EPWMxB switched low
– Output EPWMxA and/or EPWMxB toggled
• Force the PWM output state through software control
• Configure and control the PWM dead band through software
• Configure one shot and global load of registers in this module.
Dead Band (DB)
•
•
•
•
PWM Chopper (PC)
•
•
•
•
Trip Zone (TZ)
• Configure the ePWM module to react to one, all, or none of the trip-zone signals or digital
compare events.
• Specify the trip action taken when a fault occurs:
Control of traditional complementary dead-band relationship between upper and lower switches
Specify the output rising-edge-delay value
Specify the output falling-edge delay value
Bypass the dead-band module entirely. In this case the PWM waveform is passed through
without modification.
• Option to enable half-cycle clocking for double resolution.
• Allow ePWMxB phase shifting with respect to the ePWMxA output.
• Configure one shot and global load of registers in this module.
Create a chopping (carrier) frequency.
Pulse width of the first pulse in the chopped pulse train.
Duty cycle of the second and subsequent pulses.
Bypass the PWM chopper module entirely. In this case the PWM waveform is passed through
without modification.
–
Force EPWMxA and/or EPWMxB high
–
Force EPWMxA and/or EPWMxB low
–
Force EPWMxA and/or EPWMxB to a high-impedance state
– Configure EPWMxA and/or EPWMxB to ignore any trip condition.
• Configure how often the ePWM will react to each trip-zone signal:
–
•
•
•
•
One-shot
– Cycle-by-cycle
Enable the trip-zone to initiate an interrupt.
Bypass the trip-zone module entirely.
Programmable option for cycle-by-cycle trip clear
If desired, independently configure trip actions taken when time-base counter is counting down.
Event Trigger (ET)
• Enable the ePWM events that will trigger an interrupt.
• Enable ePWM events that will trigger an ADC start-of-conversion event.
• Specify the rate at which events cause triggers (every occurrence or every 2nd or up to 15th
occurrence)
• Poll, set, or clear event flags
Digital Compare (DC)
• Enables comparator (COMP) module outputs and trip zone signals which are configured using
the Input X-BAR to create events and filtered events
• Specify event-filtering options to capture TBCTR counter, generate blanking window, or insert
delay in PWM output or time-base counter based on captured value.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1733
Time-Base (TB) Submodule
www.ti.com
14.4 Time-Base (TB) Submodule
Each ePWM module has its own time-base submodule that determines all of the event timing for the
ePWM module. Built-in synchronization logic allows the time-base of multiple ePWM modules to work
together as a single system. Figure 14-4 illustrates the time-base module's place within the ePWM.
Figure 14-4. Time-Base Submodule
Time Base
Signals
EPWMxSYNCI
CTR = PRD
EPWMxSYNCO
Digital Compare
Signals
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR = 0
Digital Compare
Signals
PIE
EPWMxSOCA
ADC
EPWMxSOCB
CTR_Dir
T1
T2
ePWMxA
ePWMxB
CTR = CMPA
Counter
Compare
(CC)
Counter Compare
Signals
EPWMxINT
Event
Trigger
and
Interrupt
(ET)
ePWMxA
ePWMxB
Dead
Band
(DB)
PWMchopper
(PC)
CTR = CMPB
CTR = CMPC
Trip
Zone
(TZ)
CTR = PRD
CTR = CMPD
GPIO
MUX
TZ1 to TZ3
Input X-BAR
EMUSTOP
CPU
CLOCKFAIL
SYSCTRL
CTR = 0
EQEPxERR
EPWMxTZINT
GPIO
MUX
PIE
EQEPx
TZ1 to TZ3
Digital Compare
Signals
Digital
Compare
(DC)
ECCDBLERR
PIEERR
CMPSSx
28x RAM/
Flash ECC
EPWM X-BAR
14.4.1 Purpose of the Time-Base Submodule
You can configure the time-base submodule for the following:
• Specify the ePWM time-base counter (TBCTR) frequency or period to control how often events occur.
• Manage time-base synchronization with other ePWM modules.
• Maintain a phase relationship with other ePWM modules.
• Set the time-base counter to count-up, count-down, or count-up-and-down mode.
• Generate the following events:
– CTR = PRD: Time-base counter equal to the specified period (TBCTR = TBPRD).
– CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00).
• Configure the rate of the time-base clock; a prescaled version of the ePWM clock (EPWMCLK). This
allows the time-base counter to increment/decrement at a slower rate.
NOTE: The Type 4 ePWM clocking varies from previous ePWM types . Prior to the Type 4 ePWM,
the time-base submodule was clocked directly by the system clock ( SYSCLKOUT ) . On this
version of the ePWM , there is a divider ( EPWMCLKDIV ) of the system clock which defaults
to EPWMCLK = SYSCLKOUT/2
1734
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Time-Base (TB) Submodule
www.ti.com
14.4.2 Controlling and Monitoring the Time-Base Submodule
The block diagram in shows the critical signals and registers of the time-base submodule. Table 14-2
provides descriptions of the key signals associated with the time-base submodule.
Figure 14-5. Time-Base Submodule Signals and Registers
TBPRD
Period Shadow
TBCTL[PRDLD]
TBCTL2[SYNCOSELX]
TBPRD
Period Active
Rsvd
CTR=CMPD
CTR=CMPC
Disable
16
CTR = PRD
TBCTR[15:0]
11
10
01
00
TBCTL[SYNCOSEL]
CTR=CMPB
CTR=ZERO
TBCTL[SWFSYNC]
16
CTR_max
TBCLK
EPWMxSYNCO
EPWMxSYNCI
CTR = Zero
CTR_dir
11
10
01
00
Reset
Zero
Dir
Counter
UP/DOWN Mode
TBCTL[CTRMODE]
(A)
DCAEVT1.sync
(A)
DCBEVT1.sync
Load
Max
clk
TBCTL[PHSEN]
TBCTR
Counter Active Reg
HRPCTL[PWMSYNCSELX]
16
CTR=CMPD (Count Down)
CTR=CMPD (Count Up)
CTR=CMPC (Count Down)
CTR=CMPC (Count Up)
Rsvd
HRPCTL[PWMSYNCSEL]
Rsvd
Rsvd
1
CTR=ZERO
0
CTR=PRD
TBPHS
Phase Active Reg
SYSCLK
EPWMCLK
Prescale
Clock
Prescale
EPWMCLK
111
110
101
100
011
010
001
000
EPWMxSYNCPER
TBCLK
TBCTL[HSPCLKDIV]
TBCTL[CLKDIV]
ClkCfgRegs.PERCLKDIVSEL[EPWMCLKDIV]
A. These signals are generated by the digital compare (DC) submodule.
Table 14-2. Key Time-Base Signals
Signal
Description
EPWMxSYNCI
Time-base synchronization input.
Input pulse used to synchronize the time-base counter with the counter of ePWM module earlier in the
synchronization chain. An ePWM peripheral can be configured to use or ignore this signal. For the first
ePWM module in each synchronization chain, this signal may come from a device pin via INPUT5 or
INPUT6 of the Input X-BAR or from a previous ePWM module. For subsequent ePWM modules in each
chain, this signal is passed from another ePWM peripheral. For example, EPWM2SYNCI is generated by
the ePWM1 peripheral, EPWM3SYNCI is generated by ePWM2 and so forth. For information on the
synchronization order of a particular device, see Section 14.4.3.3.
EPWMxSYNCO
Time-base synchronization output.
This output pulse is used to synchronize the counter of an ePWM module later in the synchronization
chain. The ePWM module generates this signal from one of three event sources:
1.
2.
3.
EPWMxSYNCPER
EPWMxSYNCI (Synchronization input pulse)
CTR = Zero: The time-base counter equal to zero (TBCTR = 0x00).
CTR = CMPB: The time-base counter equal to the counter-compare B (TBCTR = CMPB) register.
Time-base peripheral synchronization output.
This output signal is used to synchronize the GPDAC and CMPSS to the EPWM. It can be configured
using the HRPCTL register. Note that this signal has no relation with the HRPWM.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM) 1735
Copyright © 2014–2019, Texas Instruments Incorporated
Time-Base (TB) Submodule
www.ti.com
Table 14-2. Key Time-Base Signals (continued)
Signal
Description
CTR = PRD
Time-base counter equal to the specified period.
This signal is generated whenever the counter value is equal to the active period register value. That is
when TBCTR = TBPRD.
CTR = Zero
Time-base counter equal to zero
This signal is generated whenever the counter value is zero. That is when TBCTR equals 0x00.
CTR = CMPB
Time-base counter equal to active counter-compare B register (TBCTR = CMPB).
This event is generated by the counter-compare submodule and used by the synchronization out logic
CTR_dir
Time-base counter direction.
Indicates the current direction of the ePWM's time-base counter. This signal is high when the counter is
increasing and low when it is decreasing.
CTR_max
Time-base counter equal max value. (TBCTR = 0xFFFF)
Generated event when the TBCTR value reaches its maximum value. This signal is only used only as a
status bit
TBCLK
Time-base clock.
This is a prescaled version of the ePWM clock (EPWMCLK) and is used by all submodules within the
ePWM. This clock determines the rate at which time-base counter increments or decrements.
14.4.3 Calculating PWM Period and Frequency
The frequency of PWM events is controlled by the time-base period (TBPRD) register and the mode of the
time-base counter. Figure 14-6 shows the period (Tpwm) and frequency (Fpwm) relationships for the upcount, down-count, and up-down-count time-base counter modes when the period is set to 4 (TBPRD =
4). The time increment for each step is defined by the time-base clock (TBCLK) which is a prescaled
version of the ePWM clock (EPWMCLK).
The time-base counter has three modes of operation selected by the time-base control register (TBCTL):
• Up-Down-Count Mode:
In up-down-count mode, the time-base counter starts from zero and increments until the period
(TBPRD) value is reached. When the period value is reached, the time-base counter then decrements
until it reaches zero. At this point the counter repeats the pattern and begins to increment.
• Up-Count Mode:
In this mode, the time-base counter starts from zero and increments until it reaches the value in the
period register (TBPRD). When the period value is reached, the time-base counter resets to zero and
begins to increment once again.
• Down-Count Mode:
In down-count mode, the time-base counter starts from the period (TBPRD) value and decrements until
it reaches zero. When it reaches zero, the time-base counter is reset to the period value and it begins
to decrement once again.
1736
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Time-Base (TB) Submodule
www.ti.com
Figure 14-6. Time-Base Frequency and Period
TPWM
4
PRD
4
4
3
3
2
3
2
1
2
1
0
Z 1
0
0
For Up Count and Down Count
TPWM
4
4
3
TPWM = (TBPRD + 1) x TTBCLK
FPWM = 1/ (TPWM)
PRD
4
3
2
3
2
1
2
1
0
1 Z
0
0
TPWM
TPWM
4
3
3
3
2
2
1
14.4.3.1
3
2
2
1
0
CTR_dir
1
1
0
0
Up
For Up and Down Count
TPWM = 2 x TBPRD x TTBCLK
FPWM = 1 / (TPWM)
4
Down
Up
Down
Time-Base Period Shadow Register
The time-base period register (TBPRD) has a shadow register. Shadowing allows the register update to
be synchronized with the hardware. The following definitions are used to describe all shadow registers in
the ePWM module:
• Active Register
The active register controls the hardware and is responsible for actions that the hardware causes or
invokes.
• Shadow Register
The shadow register buffers or provides a temporary holding location for the active register. It has no
direct effect on any control hardware. At a strategic point in time the shadow register's content is
transferred to the active register. This prevents corruption or spurious operation due to the register
being asynchronously modified by software.
The memory address of the shadow period register is the same as the active register. Which register is
written to or read from is determined by the TBCTL[PRDLD] bit. This bit enables and disables the TBPRD
shadow register as follows:
• Time-Base Period Shadow Mode:
The TBPRD shadow register is enabled when TBCTL[PRDLD] = 0. Reads from and writes to the
TBPRD memory address go to the shadow register. The shadow register contents are transferred to
the active register (TBPRD (Active) ← TBPRD (shadow)) when the time-base counter equals zero
(TBCTR = 0x00) and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. The
PRDLDSYNC bit is valid only if TBCTL[PRDLD] = 0. By default the TBPRD shadow register is
enabled. The sources for the SYNC input is explained in Section 14.4.3.3.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1737
Time-Base (TB) Submodule
•
www.ti.com
The global load control mechanism can also be used with the time-base period register by configuring
the appropriate bits in the global load configuration register (GLDCFG). When global load mode is
selected the transfer of contents from shadow register to active register, for all registers that have this
mode enabled, occurs at the same event as defined by the configuration bits in Global Shadow to
Active Load Control Register (GLDCTL). Global load control mechanism is explained in Section 14.4.7.
Time-Base Period Immediate Load Mode:
If immediate load mode is selected (TBCTL[PRDLD] = 1), then a read from or a write to the TBPRD
memory address goes directly to the active register.
14.4.3.2 Time-Base Clock Synchronization
The TBCLKSYNC bit in the peripheral clock enable registers allows all users to globally synchronize all
enabled ePWM modules to the time-base clock (TBCLK). When set, all enabled ePWM module clocks are
started with the first rising edge of TBCLK aligned. For perfectly synchronized TBCLKs, the prescalers for
each ePWM module must be set identically.
The proper procedure for enabling ePWM clocks is as follows:
1. Enable ePWM module clocks in the PCLKCRx register
2. Set TBCLKSYNC= 0
3. Configure ePWM modules
4. Set TBCLKSYNC= 1
14.4.3.3
Time-Base Counter Synchronization
The ePWM type 4 introduces a new synchronization scheme that allows for increased flexibility of
synchronization of the ePWM modules. Each ePWM module has a synchronization input (SYNCI), a
synchronization output (SYNCO) and a peripheral synchronization output (SYNCPER). In Figure 158Figure 14-7, EXTSYNC1 is sourced from INPUTXBAR5 and EXTSYNC2 is sourced from INPUTXBAR6,
which can be configured to select any GPIO as the synchronization input. When configuring the sync
chain propagation path using the SYNCSEL registers, make sure that the longest path does not exceed
four ePWM/eCAP modules.
1738
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Time-Base (TB) Submodule
www.ti.com
Figure 14-7. Time-Base Counter Synchronization Scheme
EXTSYNCIN1
EXTSYNCIN2
EPWM1
EPWM1SYNCOUT
EPWM2
EPWM4
EPWM3
EPWM4SYNCOUT
EPWM5
SYNCSEL.EPWM4SYNCIN
EPWM6
EPWM7
EXTSYNCOUT
EPWM7SYNCOUT
Pulse-Stretched
(8 PLLSYSCLK
Cycles)
EPWM8
SYNCSEL.EPWM7SYNCIN
EPWM9
EPWM10
EPWM10SYNCOUT
EPWM11
SYNCSEL.EPWM10SYNCIN
EPWM12
ECAP1
ECAP1SYNCOUT
SYNCSEL.ECAP1SYNCIN
ECAP2
ECAP3
SYNCSEL.ECAP4SYNCIN
ECAP4
ECAP5
SYNCSEL.SYNCOUT
ECAP6
NOTE: See the data manual for the number of ePWM and eCAP modules available on your specific
device.
Each ePWM module can be configured to use or ignore the synchronization input. If the TBCTL[PHSEN]
bit is set, then the time-base counter (TBCTR) of the ePWM module will be automatically loaded with the
phase register (TBPHS) contents when one of the following conditions occur:
• EPWMxSYNCI: Synchronization Input Pulse:
The value of the phase register is loaded into the counter register when an input synchronization pulse
is detected (TBPHS → TBCTR). This operation occurs on the next valid time-base clock (TBCLK)
edge.
The delay from internal master module to slave modules is given by:
– if ( TBCLK = EPWMCLK): 2 x EPWMCLK
– if ( TBCLK < EPWMCLK): 1 x TBCLK
• Software Forced Synchronization Pulse:
Writing a 1 to the TBCTL[SWFSYNC] control bit invokes a software forced synchronization. This pulse
is ORed with the synchronization input signal, and therefore has the same effect as a pulse on
EPWMxSYNCI.
• Digital Compare Event Synchronization Pulse:
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1739
Time-Base (TB) Submodule
www.ti.com
DCAEVT1 and DCBEVT1 digital compare events can be configured to generate synchronization
pulses which have the same affect as EPWMxSYNCI.
This feature enables the ePWM module to be automatically synchronized to the time base of another
ePWM module. Lead or lag phase control can be added to the waveforms generated by different ePWM
modules to synchronize them. In up-down-count mode, the TBCTL[PSHDIR] bit configures the direction of
the time-base counter immediately after a synchronization event. The new direction is independent of the
direction prior to the synchronization event. The PHSDIR bit is ignored in count-up or count-down modes.
See Figure 14-8 through Figure 14-11 for examples.
Clearing the TBCTL[PHSEN] bit configures the ePWM to ignore the synchronization input pulse. The
synchronization pulse can still be allowed to flow-through to the EPWMxSYNCO and be used to
synchronize other ePWM modules. In this way, you can set up a master time-base (for example, ePWM1)
and downstream modules (ePWM2 - ePWMx) may elect to run in synchronization with the master. See
Section 14.13 for more details on synchronization strategies.
14.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM
modules on a device. This bit is part of the device's clock enable registers and is described in the System
Control and Interrupts section of this manual. When TBCLKSYNC = 0, the time-base clock of all ePWM
modules is stopped (default). When TBCLKSYNC = 1, all ePWM time-base clocks are started with the
rising edge of TBCLK aligned. For perfectly synchronized TBCLKs, the prescaler bits in the TBCTL
register of each ePWM module must be set identically. The proper procedure for enabling the ePWM
clocks is as follows:
1. Enable the individual ePWM module clocks. This is described in the System Control and Interrupts
chapter.
2. Set TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module.
3. Configure the prescaler values and desired ePWM modes.
4. Set TBCLKSYNC = 1.
14.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
For variable frequency applications, there is a need for simultaneous writes of TBPRD and CMPx registers
between ePWM modules. This prevents situations where a CTR = 0 or CTR = PRD pulse forces a
shadow to active load of these registers before all registers are updated between ePWM modules
(resulting in some registers being loaded from new shadow values while others are loaded from old
shadow values). To support this, an ePWM register linking scheme for TBPRD:TBPRDHR,
CMPA:CMPAHR, CMPB:CMPBHR, CMPC, and CMPD registers between PWM modules has been
added.
For a particular ePWM module # A , user code writes “B+1”, to the linked register bit-field in EPWMXLINK.
“B” is the ePWM module # being linked to (that is, writes to the ePWM module “B” TBPRD:TBPRDHR,
CMPA:CMPAHR, CMPB:CMPBHR, or CMPC will simultaneously be written to corresponding register in
ePWM module “A”). For instance if ePWM3 EPWMXLINK register is configured so that CMPA:CMPAHR
are linked to ePWM1, then a write to CMPA:CMPAHR in ePWM 1 will simultaneously write the same
value to CMPA:CMPAHR in ePWM3. If ePWM4 also has its CMPA:CMPAHR registers linked to ePWM1,
then a write to ePWM 1 will write the same value to the CMPA:CMPAHR registers in both ePWM3 and
ePWM4.
The register description for EPWMXLINK clearly explains the linked register bit-field values for
corresponding ePWM.
14.4.6 Time-Base Counter Modes and Timing Waveforms
The time-base counter operates in one of four modes:
• Up-count mode which is asymmetrical
• Down-count mode which is asymmetrical
• Up-down-count which is symmetrical
• Frozen where the time-base counter is held constant at the current value
1740
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Time-Base (TB) Submodule
www.ti.com
To illustrate the operation of the first three modes, the following timing diagrams show when events are
generated and how the time-base responds to an EPWMxSYNCI signal.
Figure 14-8. Time-Base Up-Count Mode Waveforms
TBCTR[15:0]
0xFFFF
TBPRD
(value)
TBPHS
(value)
0000
EPWMxSYNCI
CTR_dir
CTR = zero
CTR = PRD
CNT_max
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1741
Time-Base (TB) Submodule
www.ti.com
Figure 14-9. Time-Base Down-Count Mode Waveforms
TBCTR[15:0]
0xFFFF
TBPRD
(value)
TBPHS
(value)
0x000
EPWMxSYNCI
CTR_dir
CTR = zero
CTR = PRD
CNT_max
Figure 14-10. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event
TBCTR[15:0]
0xFFFF
TBPRD
(value)
TBPHS
(value)
0x0000
EPWMxSYNCI
UP
UP
UP
UP
CTR_dir
DOWN
DOWN
DOWN
CTR = zero
CTR = PRD
CNT_max
1742
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Time-Base (TB) Submodule
www.ti.com
Figure 14-11. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event
TBCTR[15:0]
0xFFFF
TBPRD (value)
TBPHS (value)
0x0000
EPWMxSYNCI
UP
UP
UP
CTR_dir
DOWN
DOWN
DOWN
CTR = zero
CTR = PRD
CNT_max
14.4.7 Global Load
Figure 14-12 illustrates the signals and registers associated with the global load feature.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1743
Time-Base (TB) Submodule
www.ti.com
Figure 14-12. Global Load: Signals and Registers
Write 1 to
GLDCTL2[OSHTLD]
CNT_ZRO
PRD_EQ
CNT_ZRO or PRD_EQ
DCAEVT1.sync(A)
SYNCEVT
SYNCEVT
CNT_ZRO
SYNCEVT
PRD_EQ
SYNCEVT
CNT_ZRO or PRD_EQ
GLDCTL2[GFRCLD]
0011
CLR
One
Shot
Latch
Load
Strobe
Set
Q
1
0100
0110
0
0
0101
…
DCBEVT1.sync(A)
EPWMxSYNCI
TBCTL[SWFSYNC]
0000
0001
0010
1
GLDCTL[GLDCNT]
1111
clear CNT
3-bit
Counter
inc CNT
Global
Load
Strobe
1
0
Load
Strobe
Load
Strobe
GLDCTL[OSHTMODE]
Local
Load
Strobe
GLDCTL[GLDMODE]
0
GLDCTL[GLDPRD]
event1
event2
event3
event14
LOADMODE
NOTE: The SYNCEVT signal is only propagated through when PHSEN is SET.
When this feature is enabled, the transfer of contents from the shadow register to the active register, for
all registers that have this mode enabled, occurs at the same event as defined by the configuration bits in
Global Shadow to Active Load Control Register (GLDCTL[GLDMODE]). When GLDCTL[GLD] = ’1’,
shadow to active load event selection bits for individual shadowed registers are ignored and global load
mode takes effect for the corresponding registers enabled by GLDCFG[REGx].
When GLDCTL[GLD] = ’1’ and GLDCFG[REGx] = ‘0’ global load mode does not affect the corresponding
register (REGx). Shadow to active load event selection bits for individual shadowed registers decide how
the transfer of contents from shadow register to active register takes place.
14.4.7.1 Global Load Pulse Pre-Scalar
This feature provides the capability to choose shadow to active transfers to happen once in ‘N’
occurrences of selected global load pulse (GLDCTL[GLDMODE]). This pre-scale functionality is not
available for registers that cannot or are not configured to use the global load mechanism (that is,
GLDCTL[GLD] = ’0’ or GLDCFG[REGx] = ‘0’).
14.4.7.2 One-Shot Load Mode
This feature allows users to cause the shadow register to active register transfers to occur once. When
GLDCTL2[OSHTLD] = ‘1’ the shadow to active register transfer, for registers that are configured to use the
global load mechanism, takes place on the event selected by GLDCTL[GLDMODE].
1744
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Counter-Compare (CC) Submodule
www.ti.com
Software force loading of contents from shadow register to active register is possible by using
GLDCTL2[GFRCLD]. The GLDCTL2 register can also be linked across multiple PWM modules by using
EPWMXLINK[GLDCTL2LINK]. This, along with the one-shot load mode feature discussed above, provides
a method to correctly update multiple PWM registers in one or more PWM modules at certain PWM
events or, if desired, in the same clock cycle. This is very useful in variable frequency applications and/or
multi-phase interleaved applications.
14.5 Counter-Compare (CC) Submodule
Figure 14-13 illustrates the counter-compare submodule within the ePWM.
Figure 14-13. Counter-Compare Submodule
Time Base
Signals
EPWMxSYNCI
CTR = PRD
EPWMxSYNCO
Digital Compare
Signals
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR = 0
Digital Compare
Signals
PIE
EPWMxSOCA
ADC
EPWMxSOCB
CTR_Dir
T1
T2
ePWMxA
ePWMxB
CTR = CMPA
Counter
Compare
(CC)
Counter Compare
Signals
EPWMxINT
Event
Trigger
and
Interrupt
(ET)
ePWMxA
ePWMxB
Dead
Band
(DB)
PWMchopper
(PC)
CTR = CMPB
CTR = CMPC
Trip
Zone
(TZ)
CTR = PRD
CTR = CMPD
CTR = 0
EPWMxTZINT
GPIO
MUX
TZ1 to TZ3
Input X-BAR
EMUSTOP
CPU
CLOCKFAIL
SYSCTRL
EQEPxERR
PIE
GPIO
MUX
EQEPx
TZ1 to TZ3
Digital Compare
Signals
Digital
Compare
(DC)
ECCDBLERR
PIEERR
COMPxOUT
28x RAM/
Flash ECC
Input X-BAR
14.5.1 Purpose of the Counter-Compare Submodule
The counter-compare submodule takes as input the time-base counter value. This value is continuously
compared to the counter-compare A (CMPA) counter-compare B (CMPB) counter-compare C (CMPC) and
counter-compare D (CMPD )registers. When the time-base counter is equal to one of the compare
registers, the counter-compare unit generates an appropriate event.
The counter-compare:
• Generates events based on programmable time stamps using the CMPA, CMPB, CMPC and CMPD
registers
– CTR = CMPA: Time-base counter equals counter-compare A register (TBCTR = CMPA)
– CTR = CMPB: Time-base counter equals counter-compare B register (TBCTR = CMPB)
– CTR = CMPC: Time-base counter equals counter-compare C register (TBCTR = CMPC)
– CTR = CMPD: Time-base counter equals counter-compare D register (TBCTR = CMPD)
• Controls the PWM duty cycle if the action-qualifier submodule is configured appropriately using
counter-compare A (CMPA) & counter-compare B (CMPB)
• Shadows new compare values to prevent corruption or glitches during the active PWM cycle
14.5.2 Controlling and Monitoring the Counter-Compare Submodule
The counter-compare submodule operation is shown in Figure 14-14.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1745
Counter-Compare (CC) Submodule
www.ti.com
Figure 14-14. Detailed View of the Counter-Compare Submodule
TBCTR[15:0]
Time
Base
(TB)
Module
16
CTR = CMPA
16
CMPA[15:0]
CMPCTL
[LOADASYNC]
Shadow load
(A)
DCAEVT1.sync
(A)
DCBEVT1.sync
EPWMxSYNCI
TBCTL[SWFSYNC]
0
CMPCTL
[SHDWAFULL]
CMPA
Compare A Active Reg.
CMPA
Compare A Shadow Reg.
CMPCTL
[LOADAMODE]
Counter
Compare A
Action
Qualifier
(AQ)
Module
CMPCTL
[SHDWAMODE]
16
TBCTR[15:0]
CTR = PRD
CTR = CMPB
CMPB[15:0]
CTR = Zero
16
CMPCTL
[LOADBSYNC]
Shadow load
(A)
DCAEVT1.sync
(A)
DCBEVT1.sync
EPWMxSYNCI
TBCTL[SWFSYNC]
0
CMPCTL
[SHDWBFULL]
CMPB
Compare B Active Reg.
CMPB
Compare B Shadow Reg.
CMPCTL
[LOADBMODE]
Counter
Compare B
CMPCTL
[SHDWBMODE]
16
TBCTR[15:0]
CTR = PRD
CTR = CMPC
CMPC[15:0]
CTR = Zero
16
Counter
Compare C
CMPCTL2
[LOADCSYNC]
Shadow load
(A)
DCAEVT1.sync
(A)
DCBEVT1.sync
EPWMxSYNCI
TBCTL[SWFSYNC]
0
SOCA
CMPCTL2
[SHDWCMODE]
CMPC
Compare C Active Reg.
CMPC
Compare C Shadow Reg.
CMPCTL2
[LOADCMODE]
Event
Trigger
and
Interrupt
(ET)
SOCB
EPWMxINT
16
TBCTR[15:0]
CTR = PRD
CTR = CMPD
CMPD[15:0]
CTR = Zero
16
Counter
Compare D
CMPCTL2
[LOADDSYNC]
Shadow load
(A)
DCAEVT1.sync
(A)
DCBEVT1.sync
EPWMxSYNCI
TBCTL[SWFSYNC]
0
CMPD
Compare D Active Reg.
CMPCTL2
[SHDWDMODE]
CMPD
Compare D Shadow Reg.
CMPCTL2
[LOADDMODE]
CTR = PRD
CTR = Zero
A
These events are generated by the type 4 ePWM digital compare (DC) submodule based on the levels of the TRIPIN
inputs(for example, CMPSSx and TZ signals).
14.5.3 Operational Highlights for the Counter-Compare Submodule
The counter-compare submodule is responsible for generating events which can be used in the actionqualifier and/or event-trigger submodules. There are four independent compare events described below:
1. CTR = CMPA: Time-base counter equal to counter-compare A register (TBCTR = CMPA).
2. CTR = CMPB: Time-base counter equal to counter-compare B register (TBCTR = CMPB).
3. CTR = CMPC: Time-base counter equal to counter-compare C register (TBCTR = CMPC). This event
can be used to generate an event in the event trigger submodule only.
4. CTR = CMPD: Time-base counter equal to counter-compare D register (TBCTR = CMPD). This event
1746
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Counter-Compare (CC) Submodule
www.ti.com
can be used to generate an event in the event trigger submodule only
For up-count or down-count mode, each event occurs only once per cycle. For up-down count mode each
event occurs twice per cycle if the compare value is between 0x00-TBPRD and once per cycle if the
compare value is equal to 0x00 or equal to TBPRD. These events are fed into the action-qualifier
submodule where they are qualified by the counter direction and converted into actions if enabled. Refer
to Section 14.6.1 for more details.
The counter-compare registers CMPA and CMPB each have an associated shadow register. Shadowing
provides a way to keep updates to the registers synchronized with the hardware. When shadowing is
used, updates to the active registers only occur at strategic points. This prevents corruption or spurious
operation due to the register being asynchronously modified by software. The memory address of the
active register and the shadow register is identical. The register that is written to or read from is
determined by the CMPCTL[SHDWAMODE] and CMPCTL[SHDWBMODE] bits. These bits enable and
disable the CMPC shadow register and CMPD shadow register, respectively. The behavior of the two load
modes is described below:
Shadow Mode:
The shadow mode for the CMPA is enabled by clearing the CMPCTL[SHDWAMODE] bit and the shadow
register for CMPB is enabled by clearing the CMPCTL[SHDWBMODE] bit. Shadow mode is enabled by
default for both CMPA and CMPB.
If the shadow register is enabled then the content of the shadow register is transferred to the active
register on one of the following events as specified by the CMPCTL[LOADAMODE]
CMPCTL[LOADBMODE] CMPCTL[LOADASYNC] & CMPCTL[LOADBSYNC] register bits:
• CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).
• CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00)
• Both CTR = PRD and CTR = Zero
• SYNC event caused by DCAEVT1 or DCBEVT1 or EPWMxSYNCI or TBCTL[SWFSYNC]
• Both SYNC event or a selection made by LOADAMODE/LOADBMODE
Only the active register contents are used by the counter-compare submodule to generate events to be
sent to the action-qualifier.
Immediate Mode:
If immediate load mode is selected (that is, CMPCTL[SHDWAMODE] = 1 or CMPCTL[SHDWBMODE] =
1), then a read from or a write to the register will go directly to the active register.
Additional Comparators
The counter-compare submodule on ePWMs type 2 and later are responsible for generating two additional
independent compare events based on two compare registers, which is fed to Event Trigger submodule :
1. CTR = CMPC: Time-base counter equal to counter-compare C register (TBCTR = CMPC).
2. CTR = CMPD: Time-base counter equal to counter-compare D register (TBCTR = CMPD).
The counter-compare registers CMPC and CMPD each have an associated shadow register. By default
this register is shadowed. The memory address of the active register and the shadow register is identical.
The value in the active CMPC and CMPD register is compared to the time-base counter (TBCTR). When
the values are equal, the counter compare module generates a “time-base counter equal to counter
compare C or counter compare D ” event respectively. Shadowing of this register is enabled and disabled
by the CMPCTL2[SHDWCMODE] and CMPCTL2[SHDWDMODE] bit. These bits enable and disable the
CMPC shadow register and CMPD shadow register respectively. The behavior of the two load modes is
described below:
Shadow Mode:
The shadow mode for the CMPC is enabled by clearing the CMPCTL2[SHDWCMODE] bit and the
shadow register for CMPD is enabled by clearing the CMPCTL2[SHDWDMODE] bit. Shadow mode is
enabled by default for both CMPC and CMPD.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1747
Counter-Compare (CC) Submodule
www.ti.com
If the shadow register is enabled then the content of the shadow register is transferred to the active
register on one of the following events as specified by the CMPCTL2[LOADCMODE]
CMPCTL2[LOADDMODE] CMPCTL2[LOADCSYNC] & CMPCTL2[LOADDSYNC] register bits:
• CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).
• CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00)
• Both CTR = PRD and CTR = Zero
• SYNC event caused by DCAEVT1 or DCBEVT1 or EPWMxSYNCI or TBCTL[SWFSYNC]
• Both SYNC event or a selection made by LOADCMODE/LOADDMODE
Only the active register contents are used by the counter-compare submodule to generate events to be
sent to the action-qualifier.
Immediate Load Mode:
If the immediate load mode is selected (that is, CMPCTL2[SHDWCMODE] = 1 or
CMPCTL2[SHDWDMODE] = 1), then a read from or a write to the register will go directly to the active
register.
Global Load Support
The global load control mechanism can also be used for all counter-compare registers by configuring the
appropriate bits in the global load configuration register (GLDCFG). When the global load mode is
selected the transfer of contents from shadow register to active register, for all registers that have this
mode enabled, occurs at the same event as defined by the configuration bits in the Global Shadow to
Active Load Control Register (GLDCTL). The global load control mechanism is explained in
Section 14.4.7.
14.5.4 Count Mode Timing Waveforms
The counter-compare module can generate compare events in all three count modes:
• Up-count mode: used to generate an asymmetrical PWM waveform.
• Down-count mode: used to generate an asymmetrical PWM waveform.
• Up-down-count mode: used to generate a symmetrical PWM waveform.
To best illustrate the operation of the first three modes, the timing diagrams in Figure 14-15 through
Figure 14-18 show when events are generated and how the EPWMxSYNCI signal interacts.
1748
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Counter-Compare (CC) Submodule
www.ti.com
Figure 14-15. Counter-Compare Event Waveforms in Up-Count Mode
TBCTR[15:0]
0xFFFF
TBPRD
(value)
CMPA
(value)
CMPB
(value)
TBPHS
(value)
0x0000
EPWMxSYNCI
CTR = CMPA
CTR = CMPB
NOTE: An EPWMxSYNCI external synchronization event can cause a discontinuity in the TBCTR count
sequence. This can lead to a compare event being skipped. This skipping is considered normal operation and
must be taken into account.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1749
Counter-Compare (CC) Submodule
www.ti.com
Figure 14-16. Counter-Compare Events in Down-Count Mode
TBCTR[15:0]
0xFFFF
TBPRD
(value)
CMPA
(value)
CMPB
(value)
TBPHS
(value)
0x0000
EPWMxSYNCI
CTR = CMPA
CTR = CMPB
1750
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Action-Qualifier (AQ) Submodule
www.ti.com
Figure 14-17. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event
TBCTR[15:0]
0xFFFF
TBPRD (value)
CMPA (value)
CMPB (value)
TBPHS (value)
0x0000
EPWMxSYNCI
CTR = CMPB
CTR = CMPA
Figure 14-18. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On
Synchronization Event
TBCTR[15:0]
0xFFFF
TBPRD
(value)
CMPA
(value)
CMPB
(value)
TBPHS
(value)
0x0000
EPWMxSYNCI
CTR = CMPB
CTR = CMPA
14.6 Action-Qualifier (AQ) Submodule
The figure below shows the action-qualifier (AQ) submodule in the ePWM system.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1751
Action-Qualifier (AQ) Submodule
www.ti.com
Figure 14-19. Action-Qualifier Submodule
Time Base
Signals
EPWMxSYNCI
CTR = PRD
EPWMxSYNCO
Digital Compare
Signals
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR = 0
Digital Compare
Signals
PIE
EPWMxSOCA
ADC
EPWMxSOCB
CTR_Dir
T1
T2
ePWMxA
ePWMxB
CTR = CMPA
Counter
Compare
(CC)
Counter Compare
Signals
EPWMxINT
Event
Trigger
and
Interrupt
(ET)
ePWMxA
ePWMxB
Dead
Band
(DB)
PWMchopper
(PC)
CTR = CMPB
CTR = CMPC
Trip
Zone
(TZ)
CTR = PRD
CTR = CMPD
GPIO
MUX
TZ1 to TZ3
Input X-BAR
EMUSTOP
CPU
CLOCKFAIL
CTR = 0
SYSCTRL
EQEPxERR
EPWMxTZINT
PIE
GPIO
MUX
EQEPx
TZ1 to TZ3
Digital Compare
Signals
Digital
Compare
(DC)
ECCDBLERR
PIEERR
28x RAM/
Flash ECC
EPWM X-BAR
The action-qualifier submodule has the most important role in waveform construction and PWM
generation. It decides which events are converted into various action types, thereby producing the
required switched waveforms at the EPWMxA and EPWMxB outputs.
14.6.1 Purpose of the Action-Qualifier Submodule
The action-qualifier submodule is responsible for the following:
• Qualifying and generating actions (set, clear, toggle) based on the following events:
– CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).
– CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00)
– CTR = CMPA: Time-base counter equal to the counter-compare A register (TBCTR = CMPA)
– CTR = CMPB: Time-base counter equal to the counter-compare B register (TBCTR = CMPB)
• T1, T2 events: Trigger events based on comparator, trip or syncin events
• Managing priority when these events occur concurrently
• Providing independent control of events when the time-base counter is increasing and when it is
decreasing
14.6.2 Action-Qualifier Submodule Control and Status Register Definitions
The action-qualifier submodule operation is shown in the figure below and monitored via the registers in
Section 14.15.
1752
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Action-Qualifier (AQ) Submodule
www.ti.com
Figure 14-20. Action-Qualifier Submodule Inputs and Outputs
Action-qualifier (AQ) Module
AQCTLR[15:0]
Action-qualifier control register
TBCLK
ePWMA
AQCTLA[15:0]
Action-qualifier control A
CTR = PRD
AQCTLB[15:0]
Action-qualifier control B
CTR = Zero
CTR = CMPA
AQSFRC[15:0]
Action-qualifier S/W force
ePWMB
CTR = CMPB
AQCSFRC[3:0] (shadow)
continuous S/W force
CTR_dir
T1
AQCSFRC[3:0] (active)
continuous S/W force
T2
For convenience, the possible input events are summarized again in the table below.
Table 14-3. Action-Qualifier Submodule Possible Input Events
Signal
Description
Registers Compared
CTR = PRD
Time-base counter equal to the period value
TBCTR = TBPRD
CTR = Zero
Time-base counter equal to zero
TBCTR = 0x00
CTR = CMPA
Time-base counter equal to the counter-compare A
TBCTR = CMPA
CTR = CMPB
Time-base counter equal to the counter-compare B
TBCTR = CMPB
T1 event
Based on comparator, trip or syncin events
None
T2 event
Based on comparator, trip or syncin events
None
Software forced event
Asynchronous event initiated by software
The software forced action is a useful asynchronous event. This control is handled by the AQSFRC and
AQCSFRC registers.
The action-qualifier submodule controls how the two outputs EPWMxA and EPWMxB behave when a
particular event occurs. The event inputs to the action-qualifier submodule are further qualified by the
counter direction (up or down). This allows for independent action on outputs on both the count-up and
count-down phases.
The possible actions imposed on outputs EPWMxA and EPWMxB are:
• Set High:
Set output EPWMxA or EPWMxB to a high level.
• Clear Low:
Set output EPWMxA or EPWMxB to a low level.
• Toggle:
If EPWMxA or EPWMxB is currently pulled high, then pull the output low. If EPWMxA or EPWMxB is
currently pulled low, then pull the output high.
• Do Nothing:
Keep outputs EPWMxA and EPWMxB at same level as currently set. Although the "Do Nothing" option
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1753
Action-Qualifier (AQ) Submodule
www.ti.com
prevents an event from causing an action on the EPWMxA and EPWMxB outputs, this event can still
trigger interrupts and ADC start of conversion. See the description in theSection 14.10 for details.
Actions are specified independently for either output (EPWMxA or EPWMxB). Any or all events can be
configured to generate actions on a given output. For example, both CTR = CMPA and CTR = CMPB can
operate on output EPWMxA. All qualifier actions are configured via the control registers found at the end
of this section.
For clarity, the drawings in this document use a set of symbolic actions. These symbols are summarized in
Figure 14-21. Each symbol represents an action as a marker in time. Some actions are fixed in time (zero
and period) while the CMPA and CMPB actions are moveable and their time positions are programmed
via the counter-compare A and B registers, respectively. To turn off or disable an action, use the "Do
Nothing option"; it is the default at reset.
Figure 14-21. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs
S/W
force
SW
TB Counter equals
Zero
Z
Trigger Events Actions
Comp
A
Comp Period
B
T1
T2
CA
CB
P
T1
T2
SW
Z
CA
CB
P
T1
T2
SW
Z
CA
CB
P
T1
T2
SW
Z
CA
CB
P
T1
T2
Do Nothing
Clear Lo
Set Hi
Toggle
The Action Qualifier Trigger Event Source Selection register (AQTSRCSEL) is used to select the source
for T1 and T2 events. T1/T2 selection and configuration of a trip/digital-compare event in Action Qualifier
submodule is independent of the configuration of that event in the Trip-Zone submodule. A particular trip
event may or may not be configured to cause trip action in the Trip Zone submodule, but the same event
can be used by the Action Qualifier to generate T1/T2 for controlling PWM generation.
1754
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Action-Qualifier (AQ) Submodule
www.ti.com
14.6.3 Action-Qualifier Event Priority
It is possible for the ePWM action qualifier to receive more than one event at the same time. In this case
events are assigned a priority by the hardware. The general rule is events occurring later in time have a
higher priority and software forced events always have the highest priority. The event priority levels for updown-count mode are shown in the table below. A priority level of 1 is the highest priority and level 10 is
the lowest. The priority changes slightly depending on the direction of TBCTR.
Table 14-4. Action-Qualifier Event Priority for Up-Down-Count Mode
Priority Level
Event If TBCTR is Incrementing
TBCTR = Zero up to TBCTR = TBPRD
Event If TBCTR is Decrementing
TBCTR = TBPRD down to TBCTR = 1
1 (Highest)
Software forced event
Software forced event
2
T1 on up-count (T1U)
T1 on down-count (T1D)
3
T2 on up-count (T2U)
T2 on down-count (T2D)
4
Counter equals CMPB on up-count (CBU)
Counter equals CMPB on down-count (CBD)
5
Counter equals CMPA on up-count (CAU)
Counter equals CMPA on down-count (CAD)
6
Counter equals zero
Counter equals period (TBPRD)
7
T1 on down-count (T1D)
T1 on up-count (T1U)
8
T2 on down-count (T2D)
T2 on up-count (T2U)
9
Counter equals CMPB on down-count (CBD)
Counter equals CMPB on up-count (CBU)
10 (Lowest)
Counter equals CMPA on down-count (CAD)
Counter equals CMPA on up-count (CBU)
The table below shows the action-qualifier priority for up-count mode. In this case, the counter direction is
always defined as up and therefore, down-count events will never be taken.
Table 14-5. Action-Qualifier Event Priority for Up-Count Mode
Priority Level
Event
1 (Highest)
Software forced event
2
Counter equal to period (TBPRD)
3
T1 on up-count (T1U)
4
T2 on up-count (T2U)
5
Counter equal to CMPB on up-count (CBU)
6
Counter equal to CMPA on up-count (CAU)
7 (Lowest)
Counter equal to Zero
The table below shows the action-qualifier priority for down-count mode. In this case, the counter direction
is always defined as down and thus up-count events will never be taken.
Table 14-6. Action-Qualifier Event Priority for Down-Count Mode
Priority Level
Event
1 (Highest)
Software forced event
2
Counter equal to Zero
3
T1 on down-count (T1D)
4
T2 on down-count (T2D)
5
Counter equal to CMPB on down-count (CBD)
6
Counter equal to CMPA on down-count (CAD)
7 (Lowest)
Counter equal to period (TBPRD)
It is possible to set the compare value greater than the period. In this case the action will take place as
shown in the table below.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1755
Action-Qualifier (AQ) Submodule
www.ti.com
Table 14-7. Behavior if CMPA/CMPB is Greater than the Period
Counter Mode
Compare on Up-Count Event
CAD/CBD
Compare on Down-Count Event
CAD/CBD
Up-Count Mode
If CMPA/CMPB ≤ TBPRD period, then the event
occurs on a compare match (TBCTR=CMPA or
CMPB).
Never occurs.
If CMPA/CMPB > TBPRD, then the event will not
occur.
Down-Count Mode Never occurs.
If CMPA/CMPB < TBPRD, the event will occur on a
compare match (TBCTR=CMPA or CMPB).
If CMPA/CMPB ≥ TBPRD, the event will occur on a
period match (TBCTR=TBPRD).
Up-Down-Count
Mode
If CMPA/CMPB < TBPRD and the counter is
incrementing, the event occurs on a compare match
(TBCTR=CMPA or CMPB).
If CMPA/CMPB < TBPRD and the counter is
decrementing, the event occurs on a compare match
(TBCTR=CMPA or CMPB).
If CMPA/CMPB is ≥ TBPRD, the event will occur on a
period match (TBCTR = TBPRD).
If CMPA/CMPB ≥ TBPRD, the event occurs on a
period match (TBCTR=TBPRD).
14.6.4 AQCTLA and AQCTLB Shadow Mode Operations
To enable Action Qualifier mode changes which must occur at the end of a period even when the phase
changes, shadowing of the AQCTLA and AQCTLB registers has been added on ePWMs type 2 and later.
Additionally, shadow to active load on SYNC of these registers is supported as well. Shadowing of this
register is enabled and disabled by the AQCTL[SHDWAQAMODE] and AQCTL[SHDWAQBMODE] bits.
These bits enable and disable the AQCTLA shadow register and AQCTLB shadow register, respectively.
The behavior of the two load modes is described below:
Shadow Mode:
The shadow mode for the AQCTLA is enabled by setting the AQCTL[SHDWAQAMODE] bit, and the
shadow register for AQCTLB is enabled by setting the AQCTL[SHDWAQBMODE] bit. Shadow mode is
disabled by default for both AQCTLA and AQCTLB
If the shadow register is enabled, then the content of the shadow register is transferred to the active
register on one of the following events as specified by the AQCTL[LDAQAMODE] AQCTL[LDAQBMODE]
AQCTL[LDAQASYNC] & AQCTL[LDAQBSYNC] register bits:
• CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).
• CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00)
• Both CTR = PRD and CTR = Zero
• SYNC event caused by DCAEVT1 or DCBEVT1 or EPWMxSYNCI or TBCTL[SWFSYNC]
• Both SYNC event or a selection made by LDAQAMODE/LDAQBMODE
Global Load Support
Global load control mechanism can also be used for AQCTLA:AQCTLA2, AQCTLB:AQCTLB2 and
AQCSFRC registers by configuring the appropriate bits in the global load configuration register
(GLDCFG). When global load mode is selected, the transfer of contents from shadow register to active
register for all registers that have this mode enabled, occurs at the same event as defined by the
configuration bits in the Global Shadow to Active Load Control Register (GLDCTL). The global load control
mechanism is explained in Section 14.4.7.
Immediate Load Mode:
If immediate load mode is selected (that is, AQCTL[SHDWAQAMODE] = 0 or AQCTL[SHDWAQBMODE]
= 0), then a read from or a write to the register will go directly to the active register. See Figure 14-22 and
Figure 14-23.
1756
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Action-Qualifier (AQ) Submodule
www.ti.com
NOTE: Shadow to Active Load of Action Qualifier Output A/B Control Register [AQCTLA &
AQCTLB] on CMPA = 0 or CMPB = 0 boundary
If the Counter-Compare A Register (CMPA) or Counter-Compare B Register (CMPB) is set
to a value of 0 and the action qualifier action on AQCTLA and AQCTLB is configured to
occur in the same instant as a shadow to active load (that is, CMPA=0 and AQCTLA shadow
to active load on TBCTR=0 using AQCTL register LDAQAMODE and LDAQAMODE bits),
then both events enter contention and it is recommended to use a Non-Zero CounterCompare when using Shadow to Active Load of Action Qualifier Output A/B Control Register
on TBCTR = 0 boundary.
Figure 14-22. AQCTL[SHDWAQAMODE]
AQCTLR
[LDAQASYNC]
0
(A)
DCAEVT1.sync(A)
DCBEVT1.sync
EPWMxSYNCI
TBCTL[SWFSYNC]
11
16
Load
Strobe
10
01
AQCTLA(16)
Active Reg
00
AQCTLR
[LDAQAMODE]
AQCTLA(16)
Shadow Reg
AQCTLR[SHDWAQAMODE]
CTR = PRD
01
10
00
CTR = Zero
Figure 14-23. AQCTL[SHDWAQBMODE]
AQCTLR
[LDAQBSYNC]
0
(A)
DCAEVT1.sync(A)
DCBEVT1.sync
EPWMxSYNCI
TBCTL[SWFSYNC]
16
11
10
Load
Strobe
AQCTLB(16)
Active Reg
01
AQCTLR
[LDAQBMODE]
00
AQCTLB(16)
Shadow Reg
AQCTLR[SHDWAQBMODE]
CTR = PRD
01
10
CTR = Zero
00
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1757
Action-Qualifier (AQ) Submodule
www.ti.com
14.6.5 Waveforms for Common Configurations
NOTE:
The waveforms in this document show the behavior of the ePWMs for a static compare
register value. In a running system, the active compare registers (CMPA and CMPB) are
typically updated from their respective shadow registers once every period. The user
specifies when the update will take place; either when the time-base counter reaches zero or
when the time-base counter reaches period. There are some cases when the action based
on the new value can be delayed by one period or the action based on the old value can
take effect for an extra period. Some PWM configurations avoid this situation. These include,
but are not limited to, the following:
Use up-down-count mode to generate a symmetric PWM:
• If you load CMPA/CMPB on zero, then use CMPA/CMPB values greater
than or equal to 1.
• If you load CMPA/CMPB on period, then use CMPA/CMPB values less than
or equal to TBPRD-1.
This means there will always be a pulse of at least one TBCLK cycle in a
PWM period which, when very short, tend to be ignored by the system.
Use up-down-count mode to generate an asymmetric PWM:
• To achieve 50%-0% asymmetric PWM use the following configuration: Load
CMPA/CMPB on period and use the period action to clear the PWM and a
compare-up action to set the PWM. Modulate the compare value from 0 to
TBPRD to achieve 50%-0% PWM duty.
When using up-count mode to generate an asymmetric PWM:
• To achieve 0-100% asymmetric PWM use the following configuration: Load
CMPA/CMPB on TBPRD. Use the Zero action to set the PWM and a
compare-up action to clear the PWM. Modulate the compare value from 0 to
TBPRD+1 to achieve 0-100% PWM duty.
See the Using Enhanced Pulse Width Modulator (ePWM) Module for 0-100%
Duty Cycle Control Application Report (literature number SPRAAI1)
The figure below shows how a symmetric PWM waveform can be generated using the up-down-count
mode of the TBCTR. In this mode 0%-100% DC modulation is achieved by using equal compare matches
on the up count and down count portions of the waveform. In the example shown, CMPA is used to make
the comparison. When the counter is incrementing the CMPA match will pull the PWM output high.
Likewise, when the counter is decrementing the compare match will pull the PWM signal low. When
CMPA = 0, the PWM signal is low for the entire period giving the 0% duty waveform. When CMPA =
TBPRD, the PWM signal is high achieving 100% duty.
When using this configuration in practice, if you load CMPA/CMPB on zero, then use CMPA/CMPB values
greater than or equal to 1. If you load CMPA/CMPB on period, then use CMPA/CMPB values less than or
equal to TBPRD-1. This means there will always be a pulse of at least one TBCLK cycle in a PWM period
which, when very short, tend to be ignored by the system.
1758
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Action-Qualifier (AQ) Submodule
www.ti.com
Figure 14-24. Up-Down-Count Mode Symmetrical Waveform
4
4
Mode: Up-Down Count
TBPRD = 4
CAU = SET, CAD = CLEAR
0% - 100% Duty
3
TBCTR
1
1
1
1
2
2
2
2
3
3
3
0
0
0
TBCTR Direction
DOWN
UP
DOWN
UP
Case 1:
CMPA = 4, 0% Duty
EPWMxA/EPWMxB
Case 2:
CMPA = 3, 25% Duty
EPWMxA/EPWMxB
Case 3:
CMPA = 2, 50% Duty
EPWMxA/EPWMxB
Case 3:
CMPA = 1, 75% Duty
EPWMxA/EPWMxB
Case 4:
CMPA = 0, 100% Duty
EPWMxA/EPWMxB
The PWM waveforms in Figure 14-25 through Figure 14-30 show some common action-qualifier
configurations. Some conventions used in the figures and examples are as follows:
• TBPRD, CMPA, and CMPB refer to the value written in their respective registers. The active register,
not the shadow register, is used by the hardware.
• CMPx, refers to either CMPA or CMPB.
• EPWMxA and EPWMxB refer to the output signals from ePWMx
• Up-Down means Count-up-and-down mode, Up means up-count mode and Dwn means down-count
mode
• Sym = Symmetric, Asym = Asymmetric
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1759
Action-Qualifier (AQ) Submodule
www.ti.com
Figure 14-25. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High
TBCTR
TBPRD
value
Z
P
CB
CA
Z
P
CB
CA
Z
P
Z
P
CB
CA
Z
P
CB
CA
Z
P
EPWMxA
EPWMxB
A
1760
PWM period = (TBPRD + 1 ) × TTBCLK
B
Duty modulation for EPWMxA is set by CMPA, and is active high (that is, high time duty proportional to CMPA).
C
Duty modulation for EPWMxB is set by CMPB and is active high (that is, high time duty proportional to CMPB).
D
The "Do Nothing" actions ( X ) are shown for completeness, but will not be shown on subsequent diagrams.
E
Actions at zero and period, although appearing to occur concurrently, are actually separated by one TBCLK period.
TBCTR wraps from period to 0000.
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Action-Qualifier (AQ) Submodule
www.ti.com
Figure 14-26. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low
TBCTR
TBPRD
value
P
CA
P
CA
P
EPWMxA
P
CB
CB
P
P
EPWMxB
A
PWM period = (TBPRD + 1 ) × TTBCLK
B
Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proportional to CMPA).
C
Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to CMPB).
D
Actions at zero and period, although appearing to occur concurrently, are actually separated by one TBCLK period.
TBCTR wraps from period to 0000.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1761
Action-Qualifier (AQ) Submodule
www.ti.com
Figure 14-27. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on
EPWMxA
TBCTR
TBPRD
value
CB
CA
CA
CB
EPWMxA
Z
T
Z
T
Z
T
EPWMxB
A
PWM frequency = 1/( (TBPRD + 1 ) × TTBCLK )
B
Pulse can be placed anywhere within the PWM cycle (0000 - TBPRD)
C
High time duty proportional to (CMPB - CMPA)
Figure 14-28. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on
EPWMxA and EPWMxB — Active Low
TBCTR
TBPRD
value
CA
CA
CA
CA
EPWMxA
CB
CB
CB
CB
EPWMxB
A
1762
PWM period = 2 x TBPRD × TTBCLK
B
Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proportional to CMPA).
C
Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to CMPB).
D
Outputs EPWMxA and EPWMxB can drive independent power switches.
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Action-Qualifier (AQ) Submodule
www.ti.com
Figure 14-29. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on
EPWMxA and EPWMxB — Complementary
TBCTR
TBPRD
value
CA
CA
CA
CA
EPWMxA
CB
CB
CB
CB
EPWMxB
A
PWM period = 2 × TBPRD × TTBCLK
B
Duty modulation for EPWMxA is set by CMPA, and is active low, that is, low time duty proportional to CMPA.
C
Duty modulation for EPWMxB is set by CMPB and is active high, that is, high time duty proportional to CMPB.
D
Outputs EPWMx can drive upper/lower (complementary) power switches.
E
Dead-band = CMPB - CMPA (fully programmable edge placement by software). Note the dead-band module is also
available if the more classical edge delay method is required.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1763
Action-Qualifier (AQ) Submodule
www.ti.com
Figure 14-30. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on
EPWMxA—Active Low
TBCTR
CA
CA
CB
CB
EPWMxA
Z
P
Z
P
EPWMxB
A
PWM period = 2 × TBPRD × TBCLK
B
Rising edge and falling edge can be asymmetrically positioned within a PWM cycle. This allows for pulse placement
techniques.
C
Duty modulation for EPWMxA is set by CMPA and CMPB.
D
Low time duty for EPWMxA is proportional to (CMPA + CMPB).
E
To change this example to active high, CMPA and CMPB actions need to be inverted (that is, Clear on CMPA, Set on
CMPB).
F
Duty modulation for EPWMxB is fixed at 50% (utilizes spare action resources for EPWMxB).
Figure 14-31. Up-Down-Count, PWM Waveform Generation Utilizing T1 and T2 Events
TBCTR
T1U
T1D
T1U
T1D
EPWMxA
T2U
T2D
T2U
T2D
EPWMxB
1764
A
PWM period = 2 × TBPRD × TTBCLK
B
Independent T1 event actions when counter is counting up and when it is counting down are used to generate
EPWMxA output.
C
Independent T2 event actions when counter is counting up and when it is counting down are used to generate
EPWMxB output.
D
TZ1 is selected as the source for T1.
E
TZ2 is selected as the source for T2.
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Dead-Band Generator (DB) Submodule
www.ti.com
14.7 Dead-Band Generator (DB) Submodule
Figure 14-32 illustrates the dead-band submodule within the ePWM module.
Figure 14-32. Dead_Band Submodule
Time Base
Signals
EPWMxSYNCI
CTR = PRD
EPWMxSYNCO
Digital Compare
Signals
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR = 0
Digital Compare
Signals
PIE
EPWMxSOCA
ADC
EPWMxSOCB
CTR_Dir
T1
T2
ePWMxA
ePWMxB
CTR = CMPA
Counter
Compare
(CC)
Counter Compare
Signals
EPWMxINT
Event
Trigger
and
Interrupt
(ET)
ePWMxA
ePWMxB
Dead
Band
(DB)
PWMchopper
(PC)
CTR = CMPB
CTR = CMPC
Trip
Zone
(TZ)
CTR = PRD
CTR = CMPD
CTR = 0
EPWMxTZINT
GPIO
MUX
TZ1 to TZ3
Input X-BAR
EMUSTOP
CPU
CLOCKFAIL
SYSCTRL
EQEPxERR
PIE
GPIO
MUX
EQEPx
TZ1 to TZ3
Digital Compare
Signals
Digital
Compare
(DC)
ECCDBLERR
PIEERR
28x RAM/
Flash ECC
EPWM X-BAR
14.7.1 Purpose of the Dead-Band Submodule
The action-qualifier (AQ) module section discussed how it is possible to generate the required dead band
by having full control over edge placement using both the CMPA and CMPB resources of the ePWM
module. However, if the more classical edge delay-based dead band with polarity control is required, then
the dead-band submodule described here should be used.
The key functions of the dead-band module are:
• Generating appropriate signal pairs (EPWMxA and EPWMxB) with dead-band relationship from a
single EPWMxA input
• Programming signal pairs for:
– Active high (AH)
– Active low (AL)
– Active high complementary (AHC)
– Active low complementary (ALC)
• Adding programmable delay to rising edges (RED)
• Adding programmable delay to falling edges (FED)
• Can be totally bypassed from the signal path (note dotted lines in diagram)
14.7.2 Dead-band Submodule Additional Operating Modes
On type 1 ePWM RED could appear on one channel output and FED could appear on the other channel
output.
The following list shows the distinct difference between type 1 and type 4 modules with respect to deadband operating modes:
• By adding S6, S7, and S8 in Figure 14-33, RED and FED can appear on both the A-channel and Bchannel outputs. Additionally, both RED and FED together can be applied to either the A-channel or Bchannel outputs to allow B-channel phase shifting with respect to the A-channel.
Note: Phase shifting B-channel with respect to the A-channel using the dead-band submodule
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1765
Dead-Band Generator (DB) Submodule
•
•
•
www.ti.com
additional operating modes has limitations with respect to the choice of RED and FED delay with
respect to the operating duty cycle of the ePWMxA and ePWMxB outputs.
The dead-band counters have also been increased to 14 bits
Dead-band and dead-band High-resolution registers are now shadowed.
High-resolution dead-band RED and FED have been enabled using the DBREDHR and DBFEDHR
registers
NOTE: The PWM chopper will not be enabled when high-resolution dead band is enabled.
NOTE: High-resolution dead-band RED and FED requires Half-Cycle clocking mode
(DBCTL[HALFCYCLE] = 1).
Cannot have both RED and FED together applied to both ePWMxA and ePWMxB. RED and
FED together can be applied only to either OutA OR OutB.
NOTE: Phase shifting B-channel with respect to the A-channel: When PWMxB is derived from
PWMxA using the DEDB_MODE bit and by delaying rising edge and falling edge by the
phase shift amount. When the duty cycle value on PWMxA is less than this phase shift
amount, PWMxA’s falling edge has precedence over the delayed rising edge for PWMxB. It
is recommended to make sure the duty cycle value of the current waveform fed to the deadband module is greater than the required phase shift amount.
NOTE: The Type 4 action qualifier and deadband outputs of the ePWM module are delayed by one
TBCLK cycle in comparison to the Type 2 ePWM module, although the Type 4 behavior is
the same as the Type 3 PWM. Both PWMA and PWMB signals are delayed under all
circumstances.
Shadow Mode:
The shadow mode for the DBRED is enabled by setting the DBCTL[SHDWDBREDMODE] bit and the
shadow register for DBFED is enabled by setting the DBCTL [SHDWDBFEDMODE] bit. Shadow mode is
disabled by default for both DBRED and DBFED
If the shadow register is enabled, then the content of the shadow register is transferred to the active
register on one of the following events as specified by the DBCTL [LOADREDMODE] & DBCTL
[LOADFEDMODE] register bits:
• CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).
• CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00)
• Both CTR = PRD and CTR = Zero
The DBCTL register can be shadowed. The shadow mode for DBCTL is enabled by setting the
DBCTL2[SHDWDBCTLMODE] bit. If the shadow register is enabled then the content of the shadow
register is transferred to the active register on one of the following events as specified by the
DBCTL2[LOADDBCTLMODE] register bit:
• CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD)
• CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00)
• Both CTR = PRD and CTR = Zero
Global Load Support
Global load control mechanism can also be used for DBRED:DBREDHR, DBFED:DBFEDHR and DBCTL
registers by configuring the appropriate bits in the global load configuration register (GLDCFG). When
global load mode is selected the transfer of contents from shadow register to active register, for all
registers that have this mode enabled, occurs at the same event as defined by the configuration bits in the
Global Shadow to Active Load Control Register (GLDCTL). The Global load control mechanism is
explained in Section 14.4.7.
1766
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Dead-Band Generator (DB) Submodule
www.ti.com
NOTE: When DBRED/DBFED active is loaded with a new shadow value while DB counters are
counting, the new DBRED / DBFED value only affects the NEXT PWMx edge and not the
current edge.
NOTE: A Deadband value of ZERO should not be used when the Global Shadow to Active Load is
set to occur at CTR=ZERO. Similarly, a Deadband value of PRD should not be used when
the Global Shadow to Active Load is set to occur at CTR=PRD.
NOTE:
TBPRDHR should not be used with Global load. If high resolution period must be changed
in the application, users must write to the individual period registers from an ePWM ISR (The
ISR must be synchronous with the PWM switching period), where the Global Load One-Shot
bit is also written to.
14.7.3 Operational Highlights for the Dead-Band Submodule
The configuration options for the dead-band submodule are shown in Figure 14-33.
Figure 14-33. Configuration Options for the Dead-Band Submodule
ePWMxA
DBCTL
[LOADREDMODE]
Rising Edge
Delay
DBRED
Shadow
0
1
DBRED
Active Out
In
(14-bit counter)
S4
0
0
A path
0
RED
1
1
S2
S6
OutA
S1
1
0
S8
1
Falling Edge
Delay
1
0
S5
1
0
S8
DBFED
Active Out
In
(14-bit counter)
DBFED
Shadow
0 S7
0 S3
FED
1
OutB
1 S0
0
1
B path
DBCTL
[LOADFEDMODE]
DBCTL[HALFCYCLE]
ePWMxB
DBCTL[OUT_MODE]
DBCTL[IN_MODE]
DBCTL[DEDB_MODE]
DBCTL[POLSEL]
DBCTL[OUTSWAP]
Although all combinations are supported, not all are typical usage modes. Table 14-8 documents some
classical dead-band configurations. These modes assume that the DBCTL[IN_MODE] is configured such
that EPWMxA In is the source for both falling-edge and rising-edge delay. Enhanced, or non-traditional
modes can be achieved by changing the input signal source. The modes shown in Table 14-8 fall into the
following categories:
• Mode 1: Bypass both falling-edge delay (FED) and rising-edge delay (RED)
Allows you to fully disable the dead-band submodule from the PWM signal path.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1767
Dead-Band Generator (DB) Submodule
•
•
www.ti.com
Mode 2-5: Classical Dead-Band Polarity Settings:
These represent typical polarity configurations that should address all the active high/low modes
required by available industry power switch gate drivers. The waveforms for these typical cases are
shown in Figure 14-34. Note that to generate equivalent waveforms to Figure 14-34, configure the
action-qualifier submodule to generate the signal as shown for EPWMxA.
Mode 6: Bypass rising-edge-delay and Mode 7: Bypass falling-edge-delay
Finally the last two entries in Table 14-8 show combinations where either the falling-edge-delay (FED)
or rising-edge-delay (RED) blocks are bypassed.
Table 14-8. Classical Dead-Band Operating Modes
Mode
DBCTL[POLSEL]
Mode Description
S1
S0
EPWMxA and EPWMxB Passed Through (No Delay)
X
X
0
0
2
Active High Complementary (AHC)
1
0
1
1
3
Active Low Complementary (ALC)
0
1
1
1
4
Active High (AH)
0
0
1
1
5
Active Low (AL)
1
1
1
1
0 or 1
0 or 1
0
1
0 or 1
0 or 1
1
0
7
EPWMxA Out = EPWMxA In (No Delay)
EPWMxB Out = EPWMxA In with Falling Edge Delay
EPWMxA Out = EPWMxA In with Rising Edge Delay
EPWMxB Out = EPWMxB In with No Delay
S2
DBCTL[OUT_MODE]
1
6
S3
Table 14-9. Additional Dead-Band Operating Modes
DBCTL[DEDBMODE]
Mode Description
DBCTL[OUTSWAP]
S8
S6
S7
EPWMxA and EPWMxB signals are as defined by OUT-MODE bits.
0
0
0
EPWMxA = A-path as defined by OUT-MODE bits.
0
0
1
0
1
0
0
1
1
0
X
X
1
X
X
EPWMxB = A-path as defined by OUT-MODE bits (rising edge delay or delaybypassed A-signal path)
EPWMxA = B-path as defined by OUT-MODE bits (falling edge delay or delaybypassed B-signal path)
EPWMxB = B-path as defined by OUT-MODE bits
EPWMxA = B-path as defined by OUT-MODE bits (falling edge delay or delaybypassed B-signal path)
EPWMxB = A-path as defined by OUT-MODE bits (rising edge delay or delaybypassed A-signal path)
Rising edge delay applied to EPWMxA / EPWMxB as selected by S4 switch (INMODE bits) on A signal path only.
Falling edge delay applied to EPWMxA / EPWMxB as selected by S5 switch (INMODE bits) on B signal path only.
Rising edge delay and falling edge delay applied to source selected by S4 switch
(IN-MODE bits) and output to B signal path only. (1)
(1)
1768
When this bit is set to 1, user should always either set OUT_MODE bits such that Apath = InA or OUTSWAP bits such that
EPWMxA=Bpath. Otherwise, EPWMxA will be invalid.
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Dead-Band Generator (DB) Submodule
www.ti.com
Figure 14-34 shows waveforms for typical cases where 0% < duty < 100%.
Figure 14-34. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)
Period
Original
(outA)
RED
Rising Edge
Delayed (RED)
FED
Falling Edge
Delayed (FED)
Active High
Complementary
(AHC)
Active Low
Complementary
(ALC)
Active High
(AH)
Active Low
(AL)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1769
Dead-Band Generator (DB) Submodule
www.ti.com
The dead-band submodule supports independent values for rising-edge (RED) and falling-edge (FED)
delays. The amount of delay is programmed using the DBRED and DBFED registers. These are 10-bit
registers and their value represents the number of time-base clock, TBCLK, periods by which a signal
edge is delayed. For example, the formula to calculate falling-edge-delay and rising-edge-delay is:
FED = DBFED × TTBCLK
RED = DBRED × TTBCLK
Where TTBCLK is the period of TBCLK, the prescaled version of EPWMCLK.
For convenience, delay values for various TBCLK options are shown in Table 14-10. The ePWM input
clock frequency that these delay values been computed by is 100 MHz.
Table 14-10. Dead-Band Delay Values in μS as a Function of DBFED and DBRED
Dead-Band Value
Dead-Band Delay in μS
DBFED, DBRED
TBCLK = EPWMCLK/1
TBCLK = EPWMCLK /2
TBCLK = EPWMCLK/4
1
0.01 μS
0.02 μS
0.04 μS
5
0.05 μS
0.10 μS
0.20 μS
10
0.10 μS
0.20 μS
0.40 μS
100
1.00 μS
2.00 μS
4.00 μS
200
2.00 μS
4.00 μS
8.00 μS
400
4.00 μS
8.00 μS
16.00 μS
500
5.00 μS
10.00 μS
20.00 μS
600
6.00 μS
12.00 μS
24.00 μS
700
7.00 μS
14.00 μS
28.00 μS
800
8.00 μS
16.00 μS
32.00 μS
900
9.00 μS
18.00 μS
36.00 μS
1000
10.00 μS
20.00 μS
40.00 μS
When half-cycle clocking is enabled, the formula to calculate the falling-edge-delay and rising-edge-delay
becomes:
FED = DBFED × TTBCLK/2
RED = DBRED × TTBCLK/2
1770
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
PWM Chopper (PC) Submodule
www.ti.com
14.8 PWM Chopper (PC) Submodule
Figure 14-35 illustrates the PWM chopper (PC) submodule within the ePWM module.
Figure 14-35. PWM Chopper Submodule
Time Base
Signals
EPWMxSYNCI
CTR = PRD
EPWMxSYNCO
Digital Compare
Signals
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR = 0
Digital Compare
Signals
PIE
EPWMxSOCA
ADC
EPWMxSOCB
CTR_Dir
ePWMxA
ePWMxB
CTR = CMPA
Counter
Compare
(CC)
Counter Compare
Signals
EPWMxINT
Event
Trigger
and
Interrupt
(ET)
ePWMxA
ePWMxB
Dead
Band
(DB)
PWMchopper
(PC)
CTR = CMPB
CTR = CMPC
Trip
Zone
(TZ)
CTR = PRD
CTR = CMPD
CTR = 0
EPWMxTZINT
GPIO
MUX
TZ1 to TZ3
Input X-BAR
EMUSTOP
CPU
CLOCKFAIL
SYSCTRL
EQEPxERR
PIE
GPIO
MUX
EQEPx
TZ1 to TZ3
Digital Compare
Signals
Digital
Compare
(DC)
ECCDBLERR
PIEERR
28x RAM/
Flash ECC
ePWM X-BAR
The PWM chopper submodule allows a high-frequency carrier signal to modulate the PWM waveform
generated by the action-qualifier and dead-band submodules. This capability is important if you need
pulse transformer-based gate drivers to control the power switching elements.
14.8.1 Purpose of the PWM Chopper Submodule
The key functions of the PWM chopper submodule are:
• Programmable chopping (carrier) frequency
• Programmable pulse width of first pulse
• Programmable duty cycle of second and subsequent pulses
• Can be fully bypassed if not required
14.8.2 Operational Highlights for the PWM Chopper Submodule
Figure 14-36 shows the operational details of the PWM chopper submodule. The carrier clock is derived
from EPWMCLK. Its frequency and duty cycle are controlled via the CHPFREQ and CHPDUTY bits in the
PCCTL register. The one-shot block is a feature that provides a high energy first pulse to ensure hard and
fast power switch turn on, while the subsequent pulses sustain pulses, ensuring the power switch remains
on. The one-shot width is programmed via the OSHTWTH bits. The PWM chopper submodule can be fully
disabled (bypassed) via the CHPEN bit.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1771
PWM Chopper (PC) Submodule
www.ti.com
Figure 14-36. PWM Chopper Submodule Operational Details
Bypass
0
EPWMxA
EPWMxA
Start
One
shot
OSHT
PWMA_ch
1
Clk
Pulse-width
EPWMCLK
/8
PCCTL
[OSHTWTH]
PCCTL
[OSHTWTH]
Pulse-width
Divider and
duty control
PCCTL
[CHPEN]
PSCLK
PCCTL[CHPFREQ]
PCCTL[CHPDUTY]
Clk
One
shot
EPWMxB
PWMB_ch
1
OSHT
EPWMxB
Start
Bypass
0
14.8.3 Waveforms
Figure 14-37 shows simplified waveforms of the chopping action only; one-shot and duty-cycle control are
not shown. Details of the one-shot and duty-cycle control are discussed in the following sections.
Figure 14-37. Simple PWM Chopper Submodule Waveforms Showing Chopping Action Only
EPWMxA
EPWMxB
PSCLK
EPWMxA
EPWMxB
1772
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
PWM Chopper (PC) Submodule
www.ti.com
14.8.3.1
One-Shot Pulse
The width of the first pulse can be programmed to any of 16 possible pulse width values. The width or
period of the first pulse is given by:
T1stpulse = TEPWMCLK × 8 × OSHTWTH
Where TEPWMCLK is the period of the system clock (EPWMCLK) and OSHTWTH is the four control bits
(value from 1 to 16)
Figure 14-38 shows the first and subsequent sustaining pulses and Table 14-11 gives the possible pulse
width values for a EPWMCLK = 80 MHz.
Figure 14-38. PWM Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining
Pulses
Start OSHT pulse
EPWMxA in
PSCLK
Prog. pulse width
(OSHTWTH)
OSHT
EPWMxA out
Sustaining pulses
Table 14-11. Possible Pulse Width Values for
EPWMCLK = 80 MHz
OSHTWTHz
(hex)
Pulse Width
(nS)
0
100
1
200
2
300
3
400
4
500
5
600
6
700
7
800
8
900
9
1000
A
1100
B
1200
C
1300
D
1400
E
1500
F
1600
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1773
PWM Chopper (PC) Submodule
14.8.3.2
www.ti.com
Duty Cycle Control
Pulse transformer-based gate drive designs need to comprehend the magnetic properties or
characteristics of the transformer and associated circuitry. Saturation is one such consideration. To assist
the gate drive designer, the duty cycles of the second and subsequent pulses have been made
programmable. These sustaining pulses ensure the correct drive strength and polarity is maintained on the
power switch gate during the on period, and hence a programmable duty cycle allows a design to be
tuned or optimized via software control.
Figure 14-39 shows the duty cycle control that is possible by programming the CHPDUTY bits. One of
seven possible duty ratios can be selected ranging from 12.5% to 87.5%.
Figure 14-39. PWM Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of
Sustaining Pulses
PSCLK
PSCLK
period
75%
50%
25%
62.5% 37.5%
87.5%
12.5%
PSCLK Period
Duty
1/8
Duty
2/8
Duty
3/8
Duty
4/8
Duty
5/8
Duty
6/8
Duty
7/8
1774
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Trip-Zone (TZ) Submodule
www.ti.com
14.9 Trip-Zone (TZ) Submodule
Figure 14-40 shows how the trip-zone (TZ) submodule fits within the ePWM module.
Figure 14-40. Trip-Zone Submodule
Time Base
Signals
EPWMxSYNCI
CTR = PRD
EPWMxSYNCO
Digital Compare
Signals
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR = 0
Digital Compare
Signals
PIE
EPWMxSOCA
ADC
EPWMxSOCB
CTR_Dir
T1
T2
ePWMxA
ePWMxB
CTR = CMPA
Counter
Compare
(CC)
Counter Compare
Signals
EPWMxINT
Event
Trigger
and
Interrupt
(ET)
ePWMxA
ePWMxB
Dead
Band
(DB)
PWMchopper
(PC)
CTR = CMPB
CTR = CMPC
Trip
Zone
(TZ)
CTR = PRD
CTR = CMPD
CTR = 0
EPWMxTZINT
GPIO
MUX
TZ1 to TZ3
Input X-BAR
EMUSTOP
CPU
CLOCKFAIL
SYSCTRL
EQEPxERR
PIE
GPIO
MUX
EQEPx
TZ1 to TZ3
Digital Compare
Signals
Digital
Compare
(DC)
ECCDBLERR
PIEERR
28x RAM/
Flash ECC
ePWM X-BAR
Each ePWM module is connected to six TZn signals (TZ1 to TZ6). TZ1 to TZ3 are sourced from the GPIO
mux. TZ4 is sourced from an inverted EQEPxERR signal on those devices with an EQEP module. TZ5 is
connected to the system clock fail logic, and TZ6 is sourced from the EMUSTOP output from the CPU.
These signals indicate external fault or trip conditions, and the ePWM outputs can be programmed to
respond accordingly when faults occur.
14.9.1 Purpose of the Trip-Zone Submodule
The key functions of the trip-zone submodule are:
• Trip inputs TZ1 to TZ6 can be flexibly mapped to any ePWM module.
• Upon a fault condition, outputs EPWMxA and EPWMxB can be forced to one of the following:
– High
– Low
– High-impedance
– No action taken
• Support for one-shot trip (OSHT) for major short circuits or over-current conditions.
• Support for cycle-by-cycle tripping (CBC) for current limiting operation.
• Support for digital compare tripping (DC) based on state of on-chip analog comparator module outputs
and/or TZ1 to TZ3 signals.
• Each trip-zone input and digital compare (DC) submodule DCAEVT1/2 or DCBEVT1/2 force event can
be allocated to either one-shot or cycle-by-cycle operation.
• Interrupt generation is possible on any trip-zone input.
• Software-forced tripping is also supported.
• The trip-zone submodule can be fully bypassed if it is not required.
14.9.2 Operational Highlights for the Trip-Zone Submodule
The following sections describe the operational highlights and configuration options for the trip-zone
submodule.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1775
Trip-Zone (TZ) Submodule
www.ti.com
The trip-zone signals TZ1 to TZ6 (also collectively referred to as TZn) are active low input signals. When
one of these signals goes low, or when a DCAEVT1/2 or DCBEVT1/2 force happens based on the
TZDCSEL register event selection, it indicates that a trip event has occurred. Each ePWM module can be
individually configured to ignore or use each of the trip-zone signals or DC events. Which trip-zone signals
or DC events are used by a particular ePWM module is determined by the TZSEL register for that specific
ePWM module. The trip-zone signals may or may not be synchronized to the ePWMclock (EPWMCLK)
and digitally filtered within the GPIO MUX block. A minimum of 3*TBCLK low pulse width on TZn inputs is
sufficient to trigger a fault condition on the ePWM module. If the pulse width is less than this, the trip
condition may not be latched by CBC or OST latches. The asynchronous trip makes sure that if clocks are
missing for any reason, the outputs can still be tripped by a valid event present on TZn inputs . The
GPIOs or peripherals must be appropriately configured. For more information, see the device-specific
version of the System Control and Interrupts chapter.
Each TZn input can be individually configured to provide either a cycle-by-cycle or one-shot trip event for
an ePWM module. DCAEVT1 and DCBEVT1 events can be configured to directly trip an ePWM module or
provide a one-shot trip event to the module. Likewise, DCAEVT2 and DCBEVT2 events can also be
configured to directly trip an ePWM module or provide a cycle-by-cycle trip event to the module. This
configuration is determined by the TZSEL[DCAEVT1/2], TZSEL[DCBEVT1/2], TZSEL[CBCn], and
TZSEL[OSHTn] control bits (where n corresponds to the trip input) respectively.
•
•
•
1776
Cycle-by-Cycle (CBC):
When a cycle-by-cycle trip event occurs, the action specified in the TZCTL[TZA] and TZCTL[TZB] bits
is carried out immediately on the EPWMxA and/or EPWMxB outputs. Table 14-12 lists some of the
possible actions. Independent actions can be specified based on the occurrence of the event while the
counter is counting up and/or while it is counting down by appropriately configuring bits in the TZCTL2
register. Actions specified in the TZCTL2 register take effect only when the ETZE bit in TZCTL2 is set.
Additionally, when a cycle-by-cycle trip event occurs, the cycle-by-cycle trip event flag (TZFLG[CBC])
is set and a EPWMx_TZINT interrupt is generated if it is enabled in the TZEINT register and PIE
peripheral. A corresponding flag for the event that caused the CBC event is also set in register
TZCBCFLG.
If the CBC interrupt is enabled via the TZEINT register, and DCAEVT2 or DCBEVT2 are selected as
CBC trip sources via the TZSEL register, it is not necessary to also enable the DCAEVT2 or DCBEVT2
interrupts in the TZEINT register, as the DC events trigger interrupts through the CBC mechanism.
The specified condition on the inputs is automatically cleared based on the selection made with
TZCLR[CBCPULSE] if the trip event is no longer present. Therefore, in this mode, the trip event is
cleared or reset every PWM cycle. The TZFLG[CBC] and TZCBCFLG flag bits will remain set until they
are manually cleared by writing to the TZCLR[CBC] and TZCBCCLR flag bits. If the cycle-by-cycle trip
event is still present when the TZFLG[CBC] and/or TZCBCFLG register bits are cleared, then these
bits will again be immediately set..
One-Shot (OSHT):
When a one-shot trip event occurs, the action specified in the TZCTL[TZA] and TZCTL[TZB] bits is
carried out immediately on the EPWMxA and/or EPWMxB output. Table 14-12 lists some of the
possible actions. Independent actions can be specified based on the occurrence of the event while the
counter is counting up and/or while it is counting down by appropriately configuring bits in TZCTL2
register. Actions specified in TZCTL2 register take effect only when ETZE bit in TZCTL2 is set.
Additionally, when a one-shot trip event occurs, the one-shot trip event flag (TZFLG[OST]) is set and a
EPWMx_TZINT interrupt is generated if it is enabled in the TZEINT register and PIE peripheral. A
corresponding flag for the event that caused the OST event is also set in register TZOSTFLG. The
one-shot trip condition must be cleared manually by writing to the TZCLR[OST] bit. If desired,
TZOSTFLG register bit should be cleared by manually writing to the corresponding bit in the
TZOSTCLR register.
If the one-shot interrupt is enabled via the TZEINT register, and DCAEVT1 or DCBEVT1 are selected
as OSHT trip sources via the TZSEL register, it is not necessary to also enable the DCAEVT1 or
DCBEVT1 interrupts in the TZEINT register, as the DC events trigger interrupts through the OSHT
mechanism.
Digital Compare Events (DCAEVT1/2 and DCBEVT1/2):
A digital compare DCAEVT1/2 or DCBEVT1/2 event is generated based on a combination of the
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Trip-Zone (TZ) Submodule
www.ti.com
DCAH/DCAL and DCBH/DCBL signals as selected by the TZDCSEL register. The signals which
source the DCAH/DCAL and DCBH/DCBL signals are selected via the DCTRIPSEL register and can
be either trip zone input pins or analog comparator CMPSSx signals. For more information on the
digital compare submodule signals, see Section 14.11.
When a digital compare event occurs, the action specified in the TZCTL[DCAEVT1/2] and
TZCTL[DCBEVT1/2] bits is carried out immediately on the EPWMxA and/or EPWMxB output.
Table 14-12 lists the possible actions. Independent actions can be specified based on the occurrence
of the event while the counter is counting up and/or while it is counting down by appropriately
configuring bits in TZCTLDCA and TZCTLDCB register. Actions specified in TZCTLDCA and
TZCTLDCB registers take effect only when ETZE bit in TZCTL2 is set.
In addition, the relevant DC trip event flag (TZFLG[DCAEVT1/2] / TZFLG[DCBEVT1/2]) is set and a
EPWMx_TZINT interrupt is generated if it is enabled in the TZEINT register and PIE peripheral.
The specified condition on the pins is automatically cleared when the DC trip event is no longer
present. The TZFLG[DCAEVT1/2] or TZFLG[DCBEVT1/2] flag bit will remain set until it is manually
cleared by writing to the TZCLR[DCAEVT1/2] or TZCLR[DCBEVT1/2] bit. If the DC trip event is still
present when the TZFLG[DCAEVT1/2] or TZFLG[DCBEVT1/2] flag is cleared, then it will again be
immediately set.
The action taken when a trip event occurs can be configured individually for each of the ePWM output
pins by way of the TZCTL, TZCTL2, TZCTLDCA,, and TZCTLDCB register bit fields. Some of the possible
actions, shown in the table below, can be taken on a trip event.
Table 14-12. Possible Actions On a Trip Event
TZCTL Register bitfield Settings
EPWMxA
and/or
EPWMxB
Comment
0,0
High-Impedance
Tripped
0,1
Force to High State
Tripped
1,0
Force to Low State
Tripped
1,1
No Change
Do Nothing.
No change is made to the output.
Example 14‑1. Trip-Zone Configurations
Scenario A:
A one-shot trip event on TZ1 pulls both EPWM1A, EPWM1B low and also forces EPWM2A and EPWM2B
high.
• Configure the ePWM1 registers as follows:
– TZSEL[OSHT1] = 1: enables TZ1 as a one-shot event source for ePWM1
– TZCTL[TZA] = 2: EPWM1A will be forced low on a trip event.
– TZCTL[TZB] = 2: EPWM1B will be forced low on a trip event.
• Configure the ePWM2 registers as follows:
– TZSEL[OSHT1] = 1: enables TZ1 as a one-shot event source for ePWM2
– TZCTL[TZA] = 1: EPWM2A will be forced high on a trip event.
– TZCTL[TZB] = 1: EPWM2B will be forced high on a trip event.
Scenario B:
A cycle-by-cycle event on TZ5 pulls both EPWM1A, EPWM1B low.
A one-shot event on TZ1 or TZ6 puts EPWM2A into a high impedance state.
• Configure the ePWM1 registers as follows:
– TZSEL[CBC5] = 1: enables TZ5 as a one-shot event source for ePWM1
– TZCTL[TZA] = 2: EPWM1A will be forced low on a trip event.
– TZCTL[TZB] = 2: EPWM1B will be forced low on a trip event.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1777
Trip-Zone (TZ) Submodule
www.ti.com
Example 14‑1. Trip-Zone Configurations (continued)
•
Configure the ePWM2 registers as follows:
– TZSEL[OSHT1] = 1: enables TZ1 as a one-shot event source for ePWM2
– TZSEL[OSHT6] = 1: enables TZ6 as a one-shot event source for ePWM2
– TZCTL[TZA] = 0: EPWM2A will be put into a high-impedance state on a trip event.
– TZCTL[TZB] = 3: EPWM2B will ignore the trip event.
NOTE: When configuring the GPIOs and INPUT X-BAR/EPWM X-BAR options, be aware that a change
in the X-BAR input selections may cause an unwanted event. Therefore, ideally, the user will set
up the GPIO and X-BAR input configurations before enabling the ePWM Trip-Zone. If it is a
requirement to change the GPIO/X-BAR configurations while the ePWM Trip-Zone is enabled, the
user can turn off the TRIPs by clearing the TZSEL register and re-configuring the TRIP selection
(TZSEL) after the INPUT XBAR selection is changed.
14.9.3 Generating Trip Event Interrupts
Figure 14-41 and Figure 14-42 illustrate the trip-zone submodule control and interrupt logic, respectively.
DCAEVT1/2 and DCBEVT1/2 signals are described in further detail in Section 14.11.
1778
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Trip-Zone (TZ) Submodule
www.ti.com
Figure 14-41. Trip-Zone Submodule Mode Control Logic
TZCTLDCA[DCAEVT1U, DCAEVT1D, DCAEVT2U, DCAEVT2D]
TZCTL[TZA, DCAEVT1, DCAEVT2]
TZCTL2[TZAU, TZAD, ETZE]
EPWMxA (from PC submodule)
DCAEVT1.force
DCAEVT2.force
TRIPx
TZx
DCAEVT1.force
Digital
DCAEVT2.force
Compare
DCBEVT1.force
Submodule
DCBEVT2.force
EPWMxB (from PC submodule)
DCBEVT1.force
DCBEVT2.force
EPWMB
Trip
Logic
EPWMxB
01
10
CTR = Zero
EPWMxA
TZCTLDCB[DCBEVT1U, DCBEVT1D,
DCBEVT2U, DCBEVT2D]
TZCTL[TZB, DCBEVT1, DCBEVT2]
TZCTL2[TZBU, TZBD, ETZE]
TZCLR[CBCPULSE]
CTR = PRD
EPWMA
Trip
Logic
Clear
Clear
00
CBC Latch
TZFRC[CBC]
Trip
Set
TZ1
TZ2
TZ3
TZ4
TZ5
TZ6
DCAEVT2.force
DCBEVT2.force
Sync
Set
TZCLR[CBC]
Async
Trip
TZFLG[CBC]
Clear
Cycle-by-Cycle (CBC)
Trip Events
TZSEL[CBC1 to CBC6, DCAEVT2, DCBEVT2]
TZCLR[OST]
Clear
OSHT Latch
TZFRC[OSHT]
Trip
Set
TZ1
TZ2
TZ3
TZ4
TZ5
TZ6
DCAEVT1.force
DCBEVT1.force
Sync
Clear
Set
Async
Trip
TZFLG[OST]
One-Shot (OSHT)
Trip Events
TZSEL[OSHT1 to OSHT6, DCAEVT1, DCBEVT1]
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1779
Event-Trigger (ET) Submodule
www.ti.com
Figure 14-42. Trip-Zone Submodule Interrupt Logic
TZFLG[CBC]
TZEINT[CBC]
TZFLG[INT]
TZCLR[INT]
Clear
Latch
Set
Clear
Latch
Set
TZCLR[CBC]
Clear
Latch
Set
TZCLR[OST]
CBC Force
Output Event
TZFLG[OST]
TZEINT[OST]
OST Force
Output Event
TZFLG[DCAEVT1]
Generate
Interrupt
Pulse
EPWMxTZINT (PIE)
When
Input = 1
TZEINT[DCAEVT1]
Clear
Latch
Set
TZCLR[DCAEVT1]
DCAEVT1.inter
TZFLG[DCAEVT2]
TZEINT[DCAEVT2]
Clear
Latch
Set
TZCLR[DCAEVT2]
DCAEVT2.inter
TZFLG[DCBEVT1]
TZEINT[DCBEVT1]
Clear
Latch
Set
TZCLR[DCBEVT1]
DCBEVT1.inter
TZFLG[DCBEVT2]
TZEINT[DCBEVT2]
Clear
Latch
Set
TZCLR[DCBEVT2]
DCBEVT2.inter
These individual flags for the CBC, OST and DCxEVTy can be used to detect the source of the
EPWMxTZINT Interrupt. When multiple sources are used to generate the EPWMxTZINT interrupt, reading
and clearing the flags will user to take different actions based on the specific event.
14.10 Event-Trigger (ET) Submodule
The key functions of the event-trigger submodule are:
• Receives event inputs generated by the time-base, counter-compare, and digital-compare submodules
• Uses the time-base direction information for up/down event qualification
• Uses prescaling logic to issue interrupt requests and ADC start of conversion at:
– Every event
– Every second event
– Up to every fifteenth event
• Provides full visibility of event generation via event counters and flags
• Allows software forcing of Interrupts and ADC start of conversion
The event-trigger submodule manages the events generated by the time-base submodule, the countercompare submodule, and the digital-compare submodule to generate an interrupt to the CPU and/or a
start of conversion pulse to the ADC when a selected event occurs. Figure 14-43 illustrates where the
event-trigger submodule fits within the ePWM system.
1780
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Event-Trigger (ET) Submodule
www.ti.com
Figure 14-43. Event-Trigger Submodule
Time Base
Signals
EPWMxSYNCI
CTR = PRD
EPWMxSYNCO
Digital Compare
Signals
Time-Base
(TB)
Action
Qualifier
(AQ)
CTR = 0
Digital Compare
Signals
PIE
EPWMxSOCA
ADC
EPWMxSOCB
CTR_Dir
T1
T2
ePWMxA
ePWMxB
CTR = CMPA
Counter
Compare
(CC)
Counter Compare
Signals
EPWMxINT
Event
Trigger
and
Interrupt
(ET)
ePWMxA
ePWMxB
Dead
Band
(DB)
PWMchopper
(PC)
CTR = CMPB
CTR = CMPC
Trip
Zone
(TZ)
CTR = PRD
CTR = CMPD
CTR = 0
EPWMxTZINT
GPIO
MUX
TZ1 to TZ3
Input X-BAR
EMUSTOP
CPU
CLOCKFAIL
SYSCTRL
EQEPxERR
PIE
GPIO
MUX
EQEPx
TZ1 to TZ3
Digital Compare
Signals
Digital
Compare
(DC)
ECCDBLERR
PIEERR
28x RAM/
Flash ECC
EPWM X-BAR
14.10.1 Operational Overview of the ePWM Type 4 Event-Trigger Submodule
The event-trigger submodule monitors various event conditions (shown as inputs on the left side of
Figure 14-44) and can be configured to prescale these events before issuing an Interrupt request or an
ADC start of conversion. The event-trigger prescaling logic can issue Interrupt requests and ADC start of
conversion at:
• Every event
• Every second event
• Up to Every fifteenth event
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1781
Event-Trigger (ET) Submodule
www.ti.com
Figure 14-44. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs
clear
CTR=Zero
Event Trigger
Module Logic
CTR=PRD
/n
EPWMxINTn
PIE
ETSEL reg
CTR=Zero or PRD
count
CTRU=CMPA
ETPS reg
CTR=CMPA
CTRD=CMPA
Direction
qualifier
CTR=CMPB
CTRU=CMPB
clear
ETFLG reg
/n
CTRD=CMPB
ETCLR reg
EPWMxSOCA
count
CTRU=CMPC
CTR=CMPC
CTRD=CMPC
CTRU=CMPD
CTR=CMPD
ETFRC reg
ETINTPS reg
CTRD=CMPD
ETSOCPS reg
ADC
clear
/n
EPWMxSOCB
count
CTR_dir
DCAEVT1.soc
From Digital Compare
(DC) Submodule
ETNTINITCTL reg
DCBEVT1.soc
ETCNTINIT reg
EPWMxSYNCI
•
•
•
•
•
•
•
•
•
ETSEL - This selects which of the possible events will trigger an interrupt or start an ADC conversion.
ETPS - This programs the event prescaling options mentioned above.
ETFLG - These are flag bits indicating status of the selected and prescaled events.
ETCLR - These bits allow you to clear the flag bits in the ETFLG register via software.
ETFRC - These bits allow software forcing of an event. Useful for debugging or software intervention.
ETINTPS - This programs the interrupt event prescaling options, supporting count and period up to 15
events.
ETSOCPS - This programs the SOC event prescaling options, supporting count and period up to 15
events.
ETCNTINITCTL - These bits enable ETCNTINIT initialization via SYNC event OR via software force.
ETCNTINIT - These bits allow you to initialize INT/SOCA/SOCB counters on SYNC events (or software
force) with user programmed value.
A more detailed look at how the various register bits interact with the Interrupt and ADC start of
conversion logic are shown in Figure 14-45, Figure 14-46, and Figure 14-47.
Figure 14-45 shows the event-trigger's interrupt generation logic. The interrupt-period (ETPS[INTPRD])
bits specify the number of events required to cause an interrupt pulse to be generated. The choices
available are:
• Do not generate an interrupt.
• Generate an interrupt on every event
• Generate an interrupt on every second event
• Generate an interrupt on every third event
On ePWM type 4, in order to enable event generation capability up to 15 events the following changes
have been made. The selection made on ETPS[INTPSSEL] bit determines whether ETINTPS register,
INTCNT2 and INTPRD2 bit fields determine frequency of events (interrupt once every 0-15 events).
Which event can cause an interrupt is configured by the interrupt selection (ETSEL[INTSEL]) and
(ETSEL[INTSELCMP]) bits. The event can be one of the following:
1782
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Event-Trigger (ET) Submodule
www.ti.com
•
•
•
•
•
•
•
•
•
•
•
Time-base
Time-base
Time-base
Time-base
Time-base
Time-base
Time-base
Time-base
Time-base
Time-base
Time-base
counter equal
counter equal
counter equal
counter equal
counter equal
counter equal
counter equal
counter equal
counter equal
counter equal
counter equal
to
to
to
to
to
to
to
to
to
to
to
zero (TBCTR = 0x00).
period (TBCTR = TBPRD).
zero or period (TBCTR = 0x00 || TBCTR = TBPRD).
the compare A register (CMPA) when the timer is incrementing.
the compare A register (CMPA) when the timer is decrementing.
the compare B register (CMPB) when the timer is incrementing.
the compare B register (CMPB) when the timer is decrementing.
the compare C register (CMPC) when the timer is incrementing.
the compare C register (CMPC) when the timer is decrementing.
the compare D register (CMPD) when the timer is incrementing.
the compare D register (CMPD) when the timer is decrementing.
The number of events that have occurred can be read from the interrupt event counter ETPS[INTCNT] or
ETINTPS[INTCNT2] register bits based off of the selection made using ETPS[INTPSSEL]. That is, when
the specified event occurs the ETPS[INTCNT] or ETINTPS[INTCNT2] bits are incremented until they
reach the value specified by ETPS[INTPRD] or ETINTPS[INTPRD2] determined again by the selection
made in ETPS[INTPSSEL]. When ETPS[INTCNT] = ETPS[INTPRD] the counter stops counting and its
output is set. The counter is only cleared when an interrupt is sent to the PIE.
When ETPS[INTCNT] reaches ETPS[INTPRD] the following behavior will occur [The below behavior is
also applicable to ETINTPS[INTCNT2] & ETINTPS[INTPRD2] :
• If interrupts are enabled, ETSEL[INTEN] = 1 and the interrupt flag is clear, ETFLG[INT] = 0, then an
interrupt pulse is generated and the interrupt flag is set, ETFLG[INT] = 1, and the event counter is
cleared ETPS[INTCNT] = 0. The counter will begin counting events again.
• If interrupts are disabled, ETSEL[INTEN] = 0, or the interrupt flag is set, ETFLG[INT] = 1, the counter
stops counting events when it reaches the period value ETPS[INTCNT] = ETPS[INTPRD].
• If interrupts are enabled, but the interrupt flag is already set, then the counter will hold its output high
until the ENTFLG[INT] flag is cleared. This allows for one interrupt to be pending while one is serviced.
Writing to the INTPRD bits will automatically clear the counter INTCNT = 0 and the counter output will be
reset (so no interrupts are generated). Writing a 1 to the ETFRC[INT] bit will increment the event counter
INTCNT. The counter will behave as described above when INTCNT = INTPRD. When INTPRD = 0, the
counter is disabled and hence no events will be detected and the ETFRC[INT] bit is also ignored. The
same applies to ETINTPS[INTCNT2] & ETINTPS[INTPRD2]
The above definition means that you can generate an interrupt on every event, on every second event, or
on every third event if using the INTCNT and INTPRD. You can generate an interrupt on every event up to
15 events if using the INTCNT2 and INTPRD2.
The INTCNT2 value can be initialized with the value from ETCNTINIT[INTINIT] based on the selection
made in ETCNTINITCTL[INTINITEN]. When ETCNTINITCTL[INTINITEN] is set, then it enables
initialization of INTCNT2 counter with contents of ETCNTINIT[INTINIT] on a SYNC event or software force
determined by ETCNTINITCTL[INTINITFRC] .
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1783
Event-Trigger (ET) Submodule
www.ti.com
Figure 14-45. Event-Trigger Interrupt Generator
ETFLG[INT]
ETINTPS[INTCNT2]
ETPS[INTCNT]
ETCLR[INT]
Clear
Latch
Set
1
0
ETPS[INTPSSEL]
ETSEL[INTSEL]
EPWMxINT
Generate
Interrupt
Pulse
When
Input = 1
1
0
Clear CNT
4-bit
Counter
0
ETSEL[INT]
ETCNTINIT[INTINIT]
4
ETFRC[INT]
Inc CNT
4
ETCNTINITCTL[INTINITFRC]
000
001
010
011
0
CTR = Zero
CTR = PRD
100
0
1
CTRU = CMPA
CTRU = CMPC
101
0
1
CTRD = CMPA
CTRD = CMPC
101
0
1
CTRU = CMPB
CTRU = CMPD
111
0
1
CTRD = CMPB
CTRD = CMPD
EPWMxSYNCI
0
ETCNTINITCTL[INTINITEN]
1
ETPS[INTPSSEL]
ETPS[INTPRD] ETINTPS[INTPRD2]
ETSEL[INTSELCMP]
Figure 14-46 shows the operation of the event-trigger's start-of-conversion-A (SOCA) pulse generator. The
enhancements include SOCASELCMP and SOCBSELCMP bit fields defined in the ETSEL register enable
CMPC and CMPD events respectively to cause a start of conversion. The ETPS[SOCPSSEL] bit field
determines whether SOCACNT2 and SOCAPRD2 take control or not. The ETPS[SOCACNT] counter and
ETPS[SOCAPRD] period values behave similarly to the interrupt generator except that the pulses are
continuously generated. That is, the pulse flag ETFLG[SOCA] is latched when a pulse is generated, but it
does not stop further pulse generation. The enable/disable bit ETSEL[SOCAEN] stops pulse generation,
but input events can still be counted until the period value is reached as with the interrupt generation logic.
The event that will trigger an SOCA and SOCB pulse can be configured separately in the
ETSEL[SOCASEL] and ETSEL[SOCBSEL] bits. The possible events are the same events that can be
specified for the interrupt generation logic with the addition of the DCAEVT1.soc and DCBEVT1.soc event
signals from the digital compare (DC) submodule. The SOCACNT2 initialization scheme is very similar to
the interrupt generator with respective enable, value initialize and SYNC or software force options.
1784
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Event-Trigger (ET) Submodule
www.ti.com
Figure 14-46. Event-Trigger SOCA Pulse Generator
ETFLG[SOCA]
ETPS[SOCACNT] ETSOCPS[SOCACNT2]
ETCLR[SOCA]
Clear
Latch
Set
1
0
ETPS[SOCPSSEL]
ETSEL[SOCASEL]
EPWMxSOCA
Generate
SOC
Pulse
When
Input = 1
ClrCNT
4-bit
Counter
ETSEL[SOCA]
ETCNTINIT[SOCAINIT]
4
ETFRC[SOCA]
Inc CNT
4
ETCNTINITCTL[SOCAINITFRC]
000
001
010
011
DCAEVT1.soc
CTR = Zero
CTR = PRD
100
0
1
CTRU = CMPA
CTRU = CMPC
101
0
1
CTRD = CMPA
CTRD = CMPC
110
0
1
CTRU = CMPB
CTRU = CMPD
111
0
1
CTRD = CMPB
CTRD = CMPD
EPWMxSYNCI
0
ETCNTINITCTL[SOCAINITEN]
1
ETPS[SOCPSSEL]
ETPS[SOCAPRD] ETINTPS[SOCAPRD2]
A
ETSEL[SOCASELCMP]
The DCAEVT1.soc signals are signals generated by the Digital compare (DC) submodule in Section 14.11.
Figure 14-47 shows the operation of the event-trigger's start-of-conversion-B (SOCB) pulse generator. The
event-trigger's SOCB pulse generator operates the same way as the SOCA.
Figure 14-47. Event-Trigger SOCB Pulse Generator
ETFLG[SOCB]
ETPS[SOCBCNT] ETSOCPS[SOCBCNT2]
ETCLR[SOCB]
Clear
Latch
Set
1
0
ETPS[SOCPSSEL]
ETSEL[SOCBSEL]
EPWMxSOCB
Generate
SOC
Pulse
When
Input = 1
ClrCNT
4-bit
Counter
ETSEL[SOCB]
ETCNTINIT[SOCBINIT]
4
ETFRC[SOCB]
Inc CNT
4
ETCNTINITCTL[SOCBINITFRC]
000
001
010
011
DCBEVT1.soc
CTR = Zero
CTR = PRD
100
0
1
CTRU = CMPA
CTRU = CMPC
101
0
1
CTRD = CMPA
CTRD = CMPC
110
0
1
CTRU = CMPB
CTRU = CMPD
111
0
1
CTRD = CMPB
CTRD = CMPD
EPWMxSYNCI
0
ETCNTINITCTL[SOCBINITEN]
1
ETPS[SOCPSSEL]
ETPS[SOCBPRD] ETINTPS[SOCBPRD2]
A
ETSEL[SOCBSELCMP]
The DCBEVT1.soc signals are signals generated by the Digital compare (DC) submodule in Section 14.11.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1785
Digital Compare (DC) Submodule
www.ti.com
14.11 Digital Compare (DC) Submodule
Figure 14-48 illustrates where the digital compare (DC) submodule signals interface to other submodules
in the ePWM system.
Figure 14-48. Digital-Compare Submodule High-Level Block Diagram
Digital Compare Submodule
Input X-BAR
TRIPIN3 and TZ3
TRIPIN6
TRIPIN4
TRIPIN5
TRIPIN7
TRIPIN8
TRIPIN9
TRIPIN10
TRIPIN11
TRIPIN12
EPWM X-BAR
DCAH
DCAL
DCAEVT1.sync
DCBEVT1.sync
DCAEVT1
Event A
Qual
DCAEVT2
Blanking
Window
Counter
Capture
DCBH
DCBL
DCBEVT1
Event B
Qual
DCBEVT2
Time-Base
submodule
DCAEVT1.force
DCAEVT2.force
Event
Filtering
DCTRIPSEL
GPIO
MUX
TRIPIN1 and TZ1
TRIPIN2 and TZ2
DCEVTFILT
Event
Triggering
DCBEVT1.force
DCBEVT2.force
DCAEVT1.inter
DCAEVT2.inter
Trip-Zone
submodule
DCBEVT1.inter
DCBEVT2.inter
DCAEVT1.soc
DCBEVT1.soc
TRIPIN14 [ECCDBLERR]
TRIPIN15 [PIEERR]
Event-Trigger
submodule
TRIPIN1 and TZ1
TRIPIN2 and TZ2
TRIPIN3 and TZ3
TRIPIN4
TRIPIN5
TRIPIN6
TRIPIN7
TRIPIN8
TRIPIN9
TRIPIN10
TRIPIN11
TRIPIN12
Trip Combination Input
TRIPIN14 [ECCDBLERR]
TRIPIN15 [PIEERR]
[DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL]
The eCAP input signals are sourced from the Input X-BAR signals as shown in Figure 14-49.
1786
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Digital Compare (DC) Submodule
www.ti.com
Figure 14-49. GPIO MUX-to-Trip Input Connectivity
On this device, any of the GPIO pins can be flexibly mapped to be the trip-zone input and/or trip inputs to
the trip-zone submodule and digital compare submodule. The Input X-BAR Input Select (INPUTxSELECT)
register defines which GPIO pins gets assigned to be the trip-zone inputs / trip inputs.
The digital compare (DC) submodule compares signals external to the ePWM module (for instance,
CMPSSx signals from the analog comparators) to directly generate PWM events/actions which then feed
to the event-trigger, trip-zone, and time-base submodules. Additionally, blanking window functionality is
supported to filter noise or unwanted pulses from the DC event signals.
NOTE:
The user is responsible for driving correct state on the selected pin before enabling clock
and configuring the trip input for the respective ePWM peripheral to avoid spurious latch of
TRIP signal.
14.11.1 Purpose of the Digital Compare Submodule
The key functions of the digital compare submodule are:
• Analog comparator (COMP) module outputs fed though the Input X-BAR logic externally using the
GPIO peripheral, internal PIE, ECC error signals, TZ1, TZ2, and TZ3 inputs generate Digital Compare
A High/Low (DCAH, DCAL) and Digital Compare B High/Low (DCBH, DCBL) signals.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1787
Digital Compare (DC) Submodule
•
•
www.ti.com
DCAH/L and DCBH/L signals trigger events which can then either be filtered or fed directly to the tripzone, event-trigger, and time-base submodules to:
– generate a trip zone interrupt
– generate an ADC start of conversion
– force an event
– generate a synchronization event for synchronizing the ePWM module TBCTR.
Event filtering (blanking window logic) can optionally blank the input signal to remove noise.
14.11.2 Enhanced Trip Action Using CMPSS
In order to allow multiple CMPSS at a time to affect DCA/BEVTx events and trip actions, there is a OR
logic to bring together ALL trip inputs (up to 15) from sources external to the ePWM module and feed into
DCAH, DCAL, DCBH, and DCBL as a “combinational input” using the DCTRIPSEL register. This is
configured by selecting “Trip combination input” (value of 0xF) in the DCTRIPSEL register.
The user has a discrete choice of which trip inputs to put through the combinational logic for generating
the DCAH, DCAL, DCBH and DCBL signals. This is achieved using the DCAHTRIPSEL, DCALTRIPSEL,
DCBHTRIPSEL and DCBLTRIPSEL register selections. Inputs selected for combinational input are
passed through to the DCTRIPSEL register.
14.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
When using the CMPSS to trip the ePWM on a cycle-by-cycle basis, steps should be taken to prevent an
asserted comparator trip state in one PWM cycle from extending into the following cycle. The CMPSS can
be used to signal a trip condition to the downstream ePWM modules. For applications like peak current
mode control, only one trip event per PWM cycle is expected. Under certain conditions, it is possible for a
sustained or late trip event (arriving near the end of a PWM cycle) to carry over into the next PWM cycle if
precautions are not taken. If either the CMPSS Digital Filter or the ePWM Digital Compare (DC)
submodule is configured to qualify the comparator trip signal, “N” number of clock cycles of qualification
will be introduced before the ePWM trip logic can respond to logic changes of the trip signal. Once an
ePWM trip condition is qualified, the trip condition will remain active for N clock cycles after the
comparator trip signal has de-asserted. If a qualified comparator trip signal remains asserted within N
clock cycles prior to the end of a PWM cycle, the trip condition will not be cleared until after the following
PWM cycle has started. Thus, the new PWM cycle will detect a trip condition as soon as it begins.
To avoid this undesired trip condition, the user application should take steps to ensure that the qualified
trip signal seen by the ePWM trip logic is deasserted prior to the end of each PWM cycle. This can be
accomplished through various methods:
• Design the system such that a comparator trip will not be asserted within N clock cycles prior to the
end of the PWM cycle.
• Activate blanking of the comparator trip signal via the ePWM event filter at least two clock cycles prior
to the PWMSYNCPER signal and continue blanking for at least N clock cycles into the next PWM
cycle.
• If the CMPSS COMPxLATCH path is used, clear the COMPxLATCH at least N clock cycles prior to the
end of the PWM cycle. The latch can be cleared by software (via COMPSTSCLR) or by generating an
early PWMSYNCPER signal. The ePWM modules on this device include the ability to generate
PWMSYNCPER upon a CMPC or CMPD match (via HRPCTL) for arbitrary PWMSYNCPER placement
within the PWM cycle.
14.11.4 Operation Highlights of the Digital Compare Submodule
The following sections describe the operational highlights and configuration options for the digital compare
submodule.
1788
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Digital Compare (DC) Submodule
www.ti.com
14.11.4.1 Digital Compare Events
As illustrated in Section 14.11.4.2 earlier in this section, trip zone inputs (TZ1, TZ2, and TZ3) and
CMPSSx signals from the analog comparator (COMP) module can be selected via the DCTRIPSEL bits to
generate the Digital Compare A High and Low (DCAH/L) and Digital Compare B High and Low (DCBH/L)
signals. Then, the configuration of the TZDCSEL register qualifies the actions on the selected DCAH/L
and DCBH/L signals, which generate the DCAEVT1/2 and DCBEVT1/2 events (Event Qualification A and
B).
NOTE: The TZn signals, when used as a DCEVT tripping functions, are treated as a normal input
signal and can be defined to be active high or active low inputs. ePWM outputs are
asynchronously tripped when either the TZn, DCAEVTx.force, or DCBEVTx.force signals are
active. For the condition to remain latched, a minimum of 3*TBCLK sync pulse width is
required. If pulse width is < 3*TBCLK sync pulse width, the trip condition may or may not get
latched by CBC or OST latches.
The DCAEVT1/2 and DCBEVT1/2 events can then be filtered to provide a filtered version of the event
signals (DCEVTFILT) or the filtering can be bypassed. Filtering is discussed further in Section 14.11.4.2.
Either the DCAEVT1/2 and DCBEVT1/2 event signals or the filtered DCEVTFILT event signals can
generate a force to the trip zone module, a TZ interrupt, an ADC SOC, or a PWM sync signal.
• force signal:
DCAEVT1/2.force signals force trip zone conditions which either directly influence the output on the
EPWMxA pin (via TZCTL, TZCTLDCA, TZCTLDCB register configurations) or, if the DCAEVT1/2
signals are selected as one-shot or cycle-by-cycle trip sources (via the TZSEL register), the
DCAEVT1/2.force signals can effect the trip action via the TZCTL or TZCTL2 register configurations.
The DCBEVT1/2.force signals behaves similarly, but affect the EPWMxB output pin instead of the
EPWMxA output pin.
The priority of conflicting actions on the TZCTL, TZCTL2, TZCTLDCA and TZCTLDCB registers is as
follows (highest priority overrides lower priority):
Output EPWMxA:
– TZA (highest) -> DCAEVT1 -> DCAEVT2 (lowest)
– TZAU (highest) -> DCAEVT1U -> DCAEVT2U (lowest)
– TZAD (highest) -> DCAEVT1D -> DCAEVT2D (lowest)
Output EPWMxB:
– TZB (highest) -> DCBEVT1 -> DCBEVT2 (lowest)
– TZBU (highest) -> DCBEVT1U -> DCBEVT2U (lowest)
– TZBD (highest) -> DCBEVT1D -> DCBEVT2D (lowest)
• interrupt signal:
DCAEVT1/2.interrupt signals generate trip zone interrupts to the PIE. To enable the interrupt, the user
must set the DCAEVT1, DCAEVT2, DCBEVT1, or DCBEVT2 bits in the TZEINT register. Once one of
these events occurs, an EPWMxTZINT interrupt is triggered, and the corresponding bit in the TZCLR
register must be set in order to clear the interrupt.
• soc signal:
The DCAEVT1.soc signal interfaces with the event-trigger submodule and can be selected as an event
which generates an ADC start-of-conversion-A (SOCA) pulse via the ETSEL[SOCASEL] bit. Likewise,
the DCBEVT1.soc signal can be selected as an event which generates an ADC start-of-conversion-B
(SOCB) pulse via the ETSEL[SOCBSEL] bit.
• sync signal:
The DCAEVT1.sync and DCBEVT1.sync events are ORed with the EPWMxSYNCI input signal and the
TBCTL[SWFSYNC] signal to generate a synchronization pulse to the time-base counter.
The diagrams below show how the DCAEVT1, DCAEVT2 or DCEVTFLT signals are processed to
generate the digital compare A event force, interrupt, soc and sync signals.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1789
Digital Compare (DC) Submodule
www.ti.com
Figure 14-50. DCAEVT1 Event Triggering
DCACTL[EVT1SRCSEL]
DCACTL[EVT1FRCSYNCSEL]
DCEVTFILT
1
DCAEVT1
0
Async
1
Sync
DCAEVT1.force
0
TZEINT[DCAEVT1]
TBCLK
Set
Latch
Clear
DCAEVT1.inter
TZFLG[DCAEVT1]
TZCLR[DCAEVT1]
DCAEVT1.soc
DCACTL[EVT1SOCE]
DCAEVT1.sync
TZFRC[DCAEVT1]
DCACTL[EVT1SYNCE]
Figure 14-51. DCAEVT2 Event Triggering
DCACTL[EVT2SRCSEL]
DCACTL[EVT2FRCSYNCSEL]
DCEVTFILT
1
DCAEVT2
0
Async
1
Sync
DCAEVT2.force
0
TZEINT[DCAEVT2]
TBCLK
Set
Latch
Clear
TZFRC[DCAEVT2]
TZCLR[DCAEVT2]
1790
Enhanced Pulse Width Modulator (ePWM)
DCAEVT2.inter
TZFLG[DCAEVT2]
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Digital Compare (DC) Submodule
www.ti.com
Figure 14-52 and Figure 14-53 show how the DCBEVT1, DCBEVT2 or DCEVTFLT signals are processed
to generate the digital compare B event force, interrupt, soc and sync signals.
Figure 14-52. DCBEVT1 Event Triggering
DCBCTL[EVT1SRCSEL]
DCEVTFILT
1
DCBEVT1
0
DCBCTL[EVT1FRCSYNCSEL]
1
async
Sync
DCBEVT1.force
0
TBCLK
TZEINT[DCBEVT1]
set
Latch
clear
TZCLR[DCBEVT1]
DCBEVT1.inter
TZFLG[DCBEVT1]
DCBEVT1.soc
DCBCTL[EVT1SOCE]
DCBEVT1.sync
TZFRC[DCBEVT1]
DCBCTL[EVT1SYNCE]
Figure 14-53. DCBEVT2 Event Triggering
DCBCTL[EVT2SRCSEL]
DCEVTFILT
1
DCBEVT2
0
DCBCTL[EVT2FRCSYNCSEL]
1
async
Sync
DCBEVT2.force
0
TBCLK
TZEINT[DCBEVT2]
set
Latch
clear
TZCLR[DCBEVT2]
DCBEVT2.inter
TZFLG[DCBEVT2]
TZFRC[DCBEVT2]
14.11.4.2 Event Filtering
The DCAEVT1/2 and DCBEVT1/2 events can be filtered via event filtering logic to remove noise by
optionally blanking events for a certain period of time. This is useful for cases where the analog
comparator outputs may be selected to trigger DCAEVT1/2 and DCBEVT1/2 events, and the blanking
logic is used to filter out potential noise on the signal prior to tripping the PWM outputs or generating an
interrupt or ADC start-of-conversion. The event filtering can also capture the TBCTR value of the trip
event. The following figure shows the details of the event filtering logic.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1791
Digital Compare (DC) Submodule
www.ti.com
Figure 14-54. Event Filtering
DCCAP[15:0] Reg
Blank
Control
Logic
CTR=PRD
CTR=Zero
TBCLK
BLANKWDW
DCFCTL[BLANKE, PULSESEL]
DCFOFFSET[OFFSET]
TBCTR(16)
DCFWINDOW[WINDOW]
CTR = PRD
CTR = 0
TBCLK
EPWMxBLANK to CMPSS
DCFCTL[INVERT]
Capture
Control
Logic
DCCAPCTL[CAPE, SHDWMODE]
DCFCTL[PULSESEL]
Sync
1
0
TBCLK
DCAEVT1
00
DCAEVT2
01
DCBEVT1
10
DCBEVT2
11
async
DCEVTFILT
DCFCTL[SRCSEL]
(1)
On the F2837x/F2807x family of devices, EPWMxBLANK does not go to the CMPSS
If the blanking logic is enabled, one of the digital compare events – DCAEVT1, DCAEVT2, DCBEVT1,
DCBEVT2 – is selected for filtering. The blanking window, which filters out all event occurrences on the
signal while it is active, will be aligned to either a CTR = PRD pulse or a CTR = 0 pulse or both CTR =
PRD and CTR = 0 (configured by the DCFCTL[PULSESEL] bits). An offset value in TBCLK counts is
programmed into the DCFOFFSET register, which determines at what point after the CTR = PRD or CTR
= 0 pulse the blanking window starts. The duration of the blanking window, in number of TBCLK counts
after the offset counter expires, is written to the DCFWINDOW register by the application. During the
blanking window, all events are ignored. Before and after the blanking window ends, events can generate
soc, sync, interrupt, and force signals as before.
The diagram below illustrates several timing conditions for the offset and blanking window within an
ePWM period. Notice that if the blanking window crosses the CTR = 0 or CTR = PRD boundary, the next
window still starts at the same offset value after the CTR = 0 or CTR = PRD pulse.
1792
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Digital Compare (DC) Submodule
www.ti.com
Figure 14-55. Blanking Window Timing Diagram
Period
TBCLK
CTR = PRD
or CTR = 0
Offset(n)
BLANKWDW
Offset(n+1)
Window(n)
Window(n+1)
Offset(n)
BLANKWDW
Offset(n+1)
Window(n)
Offset(n)
Window(n+1)
Offset(n+1)
BLANKWDW
Window(n+1)
Window(n)
14.11.4.3 Valley Switching
Event filtering depicts the valley switching function along with the event filtering logic described in
Section 14.11.4.2. This function can be used to achieve programmable valley switching without any
additional external circuitry. This module provides an on-chip hardware mechanism that can:
• Capture the oscillation period
• Accurately delay the PWM switching instant
• Allow a programmable number of edges before the delay takes effect
• Provide multiple choices of triggers and events
• Allow easy adaptability for optimum performance under changing system/operating conditions
The DCxEVTy signal needs further processing to support valley switching. Here is a brief description of
how valley switching function is enabled:
1. Select one of the DCxEVTy events as input to the valley switching block (DCFCTL[SRCSEL]) with an
option to add the blanking window (Blank Control Logic). This is where the comparator output (or
external input) above is selected as an input to the valley switching block.
2. Configure the edge filter to capture ‘n’ rising, falling or both edges through the edge selection logic
(DCFCTL[EDGEMODE, EDGECOUNT]).
3. Select the correct event to reset and restart the edge filter (VCAPCTL[TRIGSEL]). Edge capturing
event is triggered or armed by this selected edge.
4. Enable valley capture logic (VCAPCTL[VCAPE]).
5. Select the start edge that will indicate the start of capture for oscillation period measurement
(VCNTCFG[STARTEDGE]). This is where the 16-bit counter starts counting.
6. Select the stop edge (VCNTCFG[STOPEDGE]) that will indicate the edge at which the 16-bit counter
stops counting. The captured counter value (CNTVAL) provides oscillation period information.
• The STOPEDGE value must always be greater than STARTEDGE value.
7. Configure and apply the captured delay (CNTVAL) to the edge filtered DCxEVTy signal. The CNTVAL
value may be applied as is or applied in conjunction with a software programmed value (useful for
offset adjustment) (SWVDELVAL) or only a fraction of the delay may be applied with or without
SWVDELVAL. This is useful to correctly apply a delay corresponding to the valley point.
(VCAPCTL[VDELAYDIV])
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1793
ePWM X-BAR
www.ti.com
8. Configure VCAPCTL[EDGEFILTDLYSEL] to apply hardware delay based on the captured value above.
Once the counter is stopped, counter value is copied into CNTVAL register and counter is reset to zero.
No further captures are done until the logic is triggered again by occurrence of event selected by
VCAPCTL[TRIGSEL]. In this implementation, the software trigger is used as the source for
VCAPCTL[TRIGSEL]. Upon occurrence of the trigger event, irrespective of the current status of the
counter, the counter is reset and starts counting from zero upon occurrence of the STARTEDGE.
Similarly, upon occurrence of the trigger event, the edge filter is reset and starts counting from zero upon
occurrence of the STARTEDGE.
Output from the valley switching block (DCEVTFILT) is then used to synchronize the PWM time-base. The
process is shown in the figure below.
NOTE: A specific application example showcasing the usage of valley switching hardware and
software is available on the controlSuite.
Figure 14-56. Valley Switching
DCCAP[15:0] Reg
TBCNT(16)
PRD_eq
CNT_zero
TBCLK
DCFCTL[BLANKE, PULSESEL]
Blank
Control
Logic
DCFOFFSET[OFFSET]
PRD_eq
CNT_zero
TBCLK
DCFWINDOW[WINDOW]
Capture
Control
Logic
DCCAPCTL[CAPE, SHDWMODE]
BLANKWDW
DCFCTL[PULSESEL]
DCFCTL[INVERT]
0
DCAEVT1
00
DCAEVT2
01
DCBEVT1
10
DCBEVT2
11
1
Sync
0
TBCLK
1
0
async
DCEVTFILT
EDGE FILTER
Reset
Edge
Selection
Logic
1
0
Edge Fiter
1
Delay
DFCTL[EDGEFILTSEL]
DCFCTL[SRCSEL]
VCAPCTL[EDGEFILTDLYSEL]
1
DCFCTL[EDGEMODE,
EDGECOUNT]
HWVDELVAL
VCAPCTL[TRIGSEL]
Software
VCAPCTL[VCAPE]
000
CNT_zero
001
PRD_eq
010
PRD_eq or
CNT_zero
DCAEVT1
DCAEVT2
DCBEVT1
DCBEVT2
SWVDELVAL
011
100
Edge Capture Trigger
101
Hardware
calculated
Delay
0
Edge
Capture
Logic
Edge Procesisng/
Delay generation
Start
CNTVAL
Stop
16 bit Counter
VCAPCTL[VDELAYDIV]
Reset
110
111
TBCLK
14.12 ePWM X-BAR
The figure below shows the architecture of the ePWM X-Bar. This module enables selection of various
trigger sources into any of the eight dedicated ETWPM trips inputs, namely the TRIP4, TRIP5, TRIP7,
TRIP8, TRIP9, TRIP10, TRIP11 and TRIP12.
1794
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM X-BAR
www.ti.com
NOTE: Please refer to the X-BAR chapter for more information on the X-BAR modules, including XBAR flags.
Figure 14-57. ePWM X-BAR
CTRIPOUTH
CTRIPOUTL
(Output X-BAR only)
CMPSSx
CTRIPH
CTRIPL
ePWM and eCAP
Sync
EXTSYNCOUT
ADCSOCAO
Select Ckt
ADCSOCAO
ADCSOCBO
Select Ckt
ADCSOCBO
eCAPx
ECAPxOUT
ADCx
Output
X-BAR
EVT1
EVT2
EVT3
EVT4
INPUT1
INPUT2
INPUT3
Input X-Bar
(ePWM X-BAR only)
OUTPUT1
OUTPUT2
OUTPUT3
OUTPUT4
OUTPUT5
OUTPUT6
OUTPUT7
OUTPUT8
GPIO
Mux
TRIP4
TRIP5
ePWM
X-BAR
INPUT4
INPUT5
INPUT6
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
All
ePWM
Modules
OTHER DESTINATIONS
(see Input X-BAR)
FLT1.COMPH
X-BAR Flags
(shared)
FLT1.COMPL
SDFMx
FLT4.COMPH
FLT4.COMPL
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1795
Applications to Power Topologies
www.ti.com
14.13 Applications to Power Topologies
An ePWM module has all the local resources necessary to operate completely as a standalone module or
to operate in synchronization with other identical ePWM modules.
14.13.1 Overview of Multiple Modules
Previously in this chapter, all discussions have described the operation of a single module. To facilitate the
understanding of multiple modules working together in a system, the ePWM module described in
reference is represented by the more simplified block diagram shown in Figure 14-58. This simplified
ePWM block shows only the key resources needed to explain how a multiswitch power topology is
controlled with multiple ePWM modules working together.
Figure 14-58. Simplified ePWM Module
SyncIn
Phase reg
EN
Φ=0°
EPWMxA
EPWMxB
CTR = 0
CTR=CMPB
X
SyncOut
14.13.2 Key Configuration Capabilities
The key configuration choices available to each module are as follows:
• Options for SyncIn
– Load own counter with phase register on an incoming sync strobe—enable (EN) switch closed
– Do nothing or ignore incoming sync strobe—enable switch open
– Sync flow-through - SyncOut connected to SyncIn
– Master mode, provides a sync at PWM boundaries—SyncOut connected to CTR = PRD
– Master mode, provides a sync at any programmable point in time—SyncOut connected to CTR =
CMPB
– Module is in standalone mode and provides No sync to other modules—SyncOut connected to X
(disabled)
• Options for SyncOut
– Sync flow-through - SyncOut connected to SyncIn
– Master mode, provides a sync at PWM boundaries—SyncOut connected to CTR = PRD
– Master mode, provides a sync at any programmable point in time—SyncOut connected to CTR =
CMPB
– Module is in standalone mode and provides No sync to other modules—SyncOut connected to X
(disabled)
For each choice of SyncOut, a module may also choose to load its own counter with a new phase value
on a SyncIn strobe input or choose to ignore it (that is, via the enable switch). Although various
combinations are possible, the two most common—master module and slave module modes—are shown
in Figure 14-59.
1796
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Applications to Power Topologies
www.ti.com
Figure 14-59. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave
Ext SyncIn
(optional)
Master
Slave
Phase reg
SyncIn
Phase reg EN
Φ=0°
EN
Φ=0°
EPWM1A
EPWM1B
CTR=0
CTR=CMPB
X
1
SyncIn
EPWM2A
2
SyncOut
EPWM2B
CTR=0
CTR=CMPB
X
SyncOut
14.13.3 Controlling Multiple Buck Converters With Independent Frequencies
One of the simplest power converter topologies is the buck. A single ePWM module configured as a
master can control two buck stages with the same PWM frequency. If independent frequency control is
required for each buck converter, then one ePWM module must be allocated for each converter stage.
Figure 14-60 shows four buck stages, each running at independent frequencies. In this case, all four
ePWM modules are configured as Masters and no synchronization is used. Figure 14-61 shows the
waveforms generated by the setup shown in Figure 14-60; note that only three waveforms are shown,
although there are four stages.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1797
Applications to Power Topologies
www.ti.com
Figure 14-60. Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4
Ext SyncIn
(optional)
Master1
Phase reg
Φ=X
SyncIn
En
Vin1
EPWM1B
CTR=zero
CTR=CMPB
X
1
Buck #1
EPWM1A
SyncOut
Master2
Phase reg
Φ=X
SyncIn
Vin2
Vout2
En
EPWM2A
2
Buck #2
EPWM2B
CTR=zero
CTR=CMPB
X
EPWM2A
SyncOut
Master3
Phase reg
Φ=X
SyncIn
Vin3
En
Vout3
EPWM3A
3
Buck #3
EPWM3B
CTR=zero
CTR=CMPB
X
EPWM3A
SyncOut
Master4
Phase reg
Φ=X
Vin4
SyncIn
Vout4
En
EPWM4A
EPWM4B
CTR=zero
CTR=CMPB
X
3
Vout1
EPWM1A
Buck #4
EPWM4A
SyncOut
NOTE: φ = X indicates value in phase register is a "don't care"
1798
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Applications to Power Topologies
www.ti.com
Figure 14-61. Buck Waveforms for Figure 14-60 (Note: Only three bucks shown here)
P
I
P
I
P
I
P
700
950
CA
CB
A
1200
P
CA
P
EPWM1A
Pulse center
P
700
1150
CA
CB
A
1400
P
CA
EPWM2A
650
500
CA
P
800
CA
P
CA
P
CB
A
EPWM3A
P
I
Indicates this event triggers an interrupt
CB
A
Indicates this event triggers an ADC start
of conversion
14.13.4 Controlling Multiple Buck Converters With Same Frequencies
If synchronization is a requirement, ePWM module 2 can be configured as a slave and can operate at
integer multiple (N) frequencies of module 1. The sync signal from master to slave ensures these modules
remain locked. Figure 14-62 shows such a configuration; Figure 14-63 shows the waveforms generated by
the configuration.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1799
Applications to Power Topologies
www.ti.com
Figure 14-62. Control of Four Buck Stages. (Note: FPWM2 = N x FPWM1)
Vin1
Buck #1
Ext SyncIn
(optional)
Master
Phase reg
Φ=0°
Vout1
EPWM1A
SyncIn
En
EPWM1A
Vin2
Vout2
EPWM1B
CTR=zero
CTR=CMPB
Buck #2
EPWM1B
X
SyncOut
Vin3
Buck #3
Slave
Phase reg
Φ=X
Vout3
EPWM2A
SyncIn
En
EPWM2A
EPWM2B
CTR=zero
CTR=CMPB
X
Vin4
Vout4
Buck #4
SyncOut
EPWM2B
NOTE: φ = X indicates value in phase register is a "don't care"
1800
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Applications to Power Topologies
www.ti.com
Figure 14-63. Buck Waveforms for Figure 14-62 (Note: FPWM2 = FPWM1))
600
Z
I
400
Z
I
Z
I
400
200
200
CA
P
(A)
A
CA
CA
P
(A)
A
CA
EPWM1A
CB
CB
CB
CB
EPWM1B
500
500
300
300
CA
CA
CA
CA
EPWM2A
CB
CB
CB
CB
EPWM2B
A
Starts ADC conversion.
14.13.5 Controlling Multiple Half H-Bridge (HHB) Converters
Topologies that require control of multiple switching elements can also be addressed with these same
ePWM modules. It is possible to control a Half-H bridge stage with a single ePWM module. This control
can be extended to multiple stages. Figure 14-64 shows control of two synchronized Half-H bridge stages
where stage 2 can operate at integer multiple (N) frequencies of stage 1. Figure 14-65 shows the
waveforms generated by the configuration shown in Figure 14-64.
Module 2 (slave) is configured for Sync flow-through; if required, this configuration allows for a third Half-H
bridge to be controlled by PWM module 3 and also, most importantly, to remain in synchronization with
master module 1.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1801
Applications to Power Topologies
www.ti.com
Figure 14-64. Control of Two Half-H Bridge Stages (FPWM2 = N x FPWM1)
VDC_bus
Ext SyncIn
(optional)
Master
Phase reg
En
Φ=0°
SyncIn
EPWM1A
EPWM1A
EPWM1B
CTR=zero
CTR=CMPB
X
EPWM1B
SyncOut
Slave
Phase reg
En
Φ=0°
Vout1
SyncIn
VDC_bus
Vout2
EPWM2A
EPWM2B
CTR=zero
CTR=CMPB
X
EPWM2A
SyncOut
EPWM2B
1802
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Applications to Power Topologies
www.ti.com
Figure 14-65. Half-H Bridge Waveforms for Figure 14-64 (Note: Here FPWM2 = FPWM1 )
Z
I
Z
I
600
400
400
200
200
Z
CB
A
Z
I
Z
CA
CB
A
CA
EPWM1A
CA
CB
A
Z
CA
CB
A
Z
CA
CB
A
Z
EPWM1B
Pulse Center
500
500
250
Z
CB
A
250
CA
Z
CB
A
CA
EPWM2A
CA
CB
A
Z
EPWM2B
Pulse Center
14.13.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
The idea of multiple modules controlling a single power stage can be extended to the 3-phase Inverter
case. In such a case, six switching elements can be controlled using three PWM modules, one for each
leg of the inverter. Each leg must switch at the same frequency and all legs must be synchronized. A
master + two slaves configuration can easily address this requirement. Figure 14-66 shows how six PWM
modules can control two independent 3-phase Inverters; each running a motor.
As in the cases shown in the previous sections, we have a choice of running each inverter at a different
frequency (module 1 and module 4 are masters as in Figure 14-66), or both inverters can be synchronized
by using one master (module 1) and five slaves. In this case, the frequency of modules 4, 5, and 6 (all
equal) can be integer multiples of the frequency for modules 1, 2, 3 (also all equal).
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1803
Applications to Power Topologies
www.ti.com
Figure 14-66. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control
Ext SyncIn
(optional)
Master
Phase reg
En
SyncIn
EPWM1A
F=0°
CTR=zero
CTR=CMPB
X
1
SyncOut
Slave
Phase reg
En
EPWM1A
SyncIn
F=0°
CTR=zero
CTR=CMPB
X
2
SyncOut
Slave
Phase reg
En
EPWM1B
Slave
EPWM2A
Phase reg
SyncIn
EPWM2B
En
F=0°
EPWM2A
EPWM3A
VAB
VCD
EPWM4A
CTR=zero
CTR=CMPB
X
4
SyncOut
EPWM4B
VEF
EPWM1B
EPWM2B
EPWM3B
3 phase motor
SyncIn
F=0°
Slave
Phase reg
EPWM3B
En
EPWM3A
CTR=zero
CTR=CMPB
X
3
SyncOut
3 phase inverter #1
SyncIn
F=0°
EPWM5A
CTR=zero
CTR=CMPB
X
5
SyncOut
Slave
Phase reg
En
EPWM5B
SyncIn
F=0°
CTR=zero
CTR=CMPB
X
6
SyncOut
EPWM6A
EPWM6B
EPWM4A
EPWM5A
EPWM6A
VAB
VCD
VEF
EPWM4B
EPWM5B
EPWM6B
3 phase motor
3 phase inverter #2
1804
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Applications to Power Topologies
www.ti.com
Figure 14-67. 3-Phase Inverter Waveforms for Figure 14-66 (Only One Inverter Shown)
Z
I
Z
I
800
500
500
CA
CA
P
A
EPWM1A
CA
CA
P
A
RED
RED
EPWM1B
FED
FED
Φ2=0
600
600
CA
CA
CA
CA
EPWM2A
RED
EPWM2B
FED
700
Φ3=0
CA
EPWM3A
700
CA
CA
CA
RED
EPWM3B
FED
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1805
Applications to Power Topologies
www.ti.com
14.13.7 Practical Applications Using Phase Control Between PWM Modules
So far, none of the examples have made use of the phase register (TBPHS). It has either been set to zero
or its value has been a don't care. However, by programming appropriate values into TBPHS, multiple
PWM modules can address another class of power topologies that rely on phase relationship between
legs (or stages) for correct operation. As described in the TB module section, a PWM module can be
configured to allow a SyncIn pulse to cause the TBPHS register to be loaded into the TBCTR register. To
illustrate this concept, the following figure shows a master and slave module with a phase relationship of
120° (that is, the slave leads the master).
Figure 14-68. Configuring Two PWM Modules for Phase Control
Ext SyncIn
(optional)
Master
Phase reg
SyncIn
En
Φ=0°
EPWM1A
EPWM1B
CTR=zero
CTR=CMPB
X
1
SyncOut
Slave
Phase reg
SyncIn
En
Φ=120°
EPWM2A
EPWM2B
CTR=zero
CTR=CMPB
X
2
SyncOut
The following figure shows the associated timing waveforms for this configuration. Here, TBPRD = 600 for
both master and slave. For the slave, TBPHS = 200 (that is, 200/600 X 360° = 120°). Whenever the
master generates a SyncIn pulse (CTR = PRD), the value of TBPHS = 200 is loaded into the slave
TBCTR register so the slave time-base is always leading the master's time-base by 120°.
1806
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Applications to Power Topologies
www.ti.com
Figure 14-69. Timing Waveforms Associated With Phase Control Between Two Modules
FFFFh
TBCTR[0-15]
Master Module
600
600
TBPRD
0000
CTR = PRD
(SycnOut)
FFFFh
time
TBCTR[0-15]
Φ2
Phase = 120°
Slave Module
TBPRD
600
600
200
200
TBPHS
0000
SyncIn
time
14.13.8 Controlling a 3-Phase Interleaved DC/DC Converter
A popular power topology that makes use of phase-offset between modules is shown in Figure 14-70. This
system uses three PWM modules, with module 1 configured as the master. To work, the phase
relationship between adjacent modules must be F = 120°. This is achieved by setting the slave TBPHS
registers 2 and 3 with values of 1/3 and 2/3 of the period value, respectively. For example, if the period
register is loaded with a value of 600 counts, then TBPHS (slave 2) = 200 and TBPHS (slave 3) = 400.
Both slave modules are synchronized to the master 1 module.
This concept can be extended to four or more phases, by setting the TBPHS values appropriately. The
following formula gives the TBPHS values for N phases:
TBPHS(N,M) = (TBPRD/N) x (M-1)
Where:
N = number of phases
M = PWM module number
For example, for the 3-phase case (N=3), TBPRD = 600,
TBPHS(3,2) = (600/3) x (2-1) = 200 (that is, Phase value for Slave module 2)
TBPHS(3,3) = 400 (that is, Phase value for Slave module 3)
Figure 14-71 shows the waveforms for the configuration in Figure 14-70.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1807
Applications to Power Topologies
www.ti.com
Figure 14-70. Control of a 3-Phase Interleaved DC/DC Converter
Ext SyncIn
(optional)
Master
Phase reg
Φ=0°
SyncIn
VIN
En
EPWM1A
EPWM1B
CTR=zero
CTR=CMPB
X
1
EPWM1A
EPWM2A
EPWM3A
EPWM1B
EPWM2B
EPWM3B
SyncOut
Slave
Phase reg
Φ=120°
SyncIn
VOUT
En
EPWM2A
EPWM2B
CTR=zero
CTR=CMPB
X
2
SyncOut
Slave
Phase reg
SyncIn
En
Φ=240°
EPWM3A
EPWM3B
CTR=zero
CTR=CMPB
X
3
1808
SyncOut
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Applications to Power Topologies
www.ti.com
Figure 14-71. 3-Phase Interleaved DC/DC Converter Waveforms for Figure 14-70
Z
I
285
CA
EPWM1A
285
P
A
CA
CA
RED
P
A
FED
Z
I
CA
CA
RED
EPWM1B
300
Z
I
Z
I
450
P
A
CA
RED
FED
FED
Φ2=120°
TBPHS
(=300)
EPWM2A
EPWM2B
300
Φ2=120°
TBPHS
(=300)
EPWM3A
EPWM3B
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1809
Applications to Power Topologies
www.ti.com
14.13.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
The example given in the figure below assumes a static or constant phase relationship between legs
(modules). In such a case, control is achieved by modulating the duty cycle. It is also possible to
dynamically change the phase value on a cycle-by-cycle basis. This feature lends itself to controlling a
class of power topologies known as phase-shifted full bridge, or zero voltage switched full bridge. Here the
controlled parameter is not duty cycle (this is kept constant at approximately 50 percent); instead it is the
phase relationship between legs. Such a system can be implemented by allocating the resources of two
PWM modules to control a single power stage, which in turn requires control of four switching elements.
Figure 14-73 shows a master/slave module combination synchronized together to control a full H-bridge.
In this case, both master and slave modules are required to switch at the same PWM frequency. The
phase is controlled by using the slave's phase register (TBPHS). The master's phase register is not used
and therefore can be initialized to zero.
Figure 14-72. Controlling a Full-H Bridge Stage (FPWM2 = FPWM1)
Ext SyncIn
(optional)
Master
Phase reg
Φ=0°
SyncIn
En
EPWM1A
CTR=zero
CTR=CMPB
X
Slave
Phase reg
Φ=Var°
Vout
VDC_bus
EPWM1B
SyncOut
EPWM1A
EPWM2A
EPWM1B
EPWM2B
SyncIn
En
CTR=zero
CTR=CMPB
X
EPWM2A
EPWM2B
SyncOut
Var = Variable
1810
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Applications to Power Topologies
www.ti.com
Figure 14-73. ZVS Full-H Bridge Waveforms
Z
I
Z
I
Z
I
1200
600
200
Z
CB
A
CA
Z
CB
A
CA
Z
RED
ZVS transition
EPWM1A
Power phase
FED
ZVS transition
EPWM1B
300
TBPHS
=(1200−Φ2)
Φ2=variable
CB
A
Z
CA
CB
A
Z
Z
CA
RED
EPWM2A
EPWM2B
FED
Power phase
14.13.10 Controlling a Peak Current Mode Controlled Buck Module
Peak current control techniques offer a number of benefits like automatic over current limiting, fast
correction for input voltage variations and reducing magnetic saturation. Figure 14-74 shows the use of
ePWM1A along with the on-chip analog comparator for buck converter topology. The output current is
sensed through a current sense resistor and fed to the positive terminal of the on-chip comparator. The
internal programmable 10-bit DAC can be used to provide a reference peak current at the negative
terminal of the comparator. Alternatively, an external reference could be connected at this input. The
comparator output is an input to the Digital compare sub-module. The ePWM module is configured in such
a way so as to trip the ePWM1A output as soon as the sensed current reaches the peak reference value.
A cycle-by-cycle trip mechanism is used. Figure 14-75 shows the waveforms generated by the
configuration.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1811
Applications to Power Topologies
www.ti.com
Figure 14-74. Peak Current Mode Control of a Buck Converter
Vin
Phase Reg
"#$#%
En
Vout
SyncIn
!
EPWM1A
EPWM1A
CNT=Zero
CNT=CMPB
EPWM1B
X
SyncOut
COMP1+/
ADCA2
Isense
Difference
Amplifier
Figure 14-75. Peak Current Mode Control Waveforms for Figure 14-74
0
R=
3
to
00
CT
TB
ePWM1
Time base
TBPRD
= 300
Increased
Load
DAC OUT/
COMP1-
Isense
DCAEVT2.force
ePWM1A
14.13.11 Controlling H-Bridge LLC Resonant Converter
Various topologies of resonant converters are well-known in the field of power electronics for many years.
In addition to these, H-bridge LLC resonant converter topology has recently gained popularity in many
consumer electronics applications where high efficiency and power density are required. In this example
single channel configuration of ePWM1 is detailed, yet the configuration can easily be extended to multi
channel. Here the controlled parameter is not duty cycle (this is kept constant at approximately 50
percent); instead it is frequency. Although the deadband is not controlled and kept constant as 300ns (that
is, 30 @100MHz TBCLK), it is up to user to update it in real time to enhance the efficiency by adjusting
enough time delay for soft switching.
1812
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Applications to Power Topologies
www.ti.com
Figure 14-76. Control of Two Resonant Converter Stages
Ext Sync In
(optional)
Master
Phase Reg
En
EPWM1A
EPWM1A
CNT=Zero
CNT=CMPB
1
LLC Resonant
Transformer
SyncIn
!"#" X
V OUT
Integrated
Magnetcis
V DC_bus
X
EPWM1B
SyncOut
EPWM1B
Cr
NOTE: Θ = X indicates value in phase register is a"don't care"
Figure 14-77. H-Bridge LLC Resonant Converter PWM Waveforms
P
P
P
I
I
I
period
period/2
period/4
P
CB
CA
P
CB
A
CA
P
A
EPWMxA
RED
ZVS
transition
EPWMxB
FED
ZVS
transition
P
I
Indicates this event triggers an interrupt
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
CB
A
Indicates this event triggers an ADC
start of conversion
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1813
High-Resolution Pulse Width Modulator (HRPWM)
www.ti.com
14.14 High-Resolution Pulse Width Modulator (HRPWM)
This module extends the time resolution capabilities of the conventionally derived digital pulse width
modulator (PWM). HRPWM is typically used when PWM resolution falls below ~ 9-10 bits. The key
features of HRPWM are:
• Extended time resolution capability
• Used in both duty cycle and phase-shift control methods
• Finer time granularity control or edge positioning using extensions to the Compare A, Compare B and
Phase registers
• Implemented using the A & B signal path of PWM, that is, on the EPWMxA and EPWMxB output.
• Dead band high-resolution control for falling and rising edge delay in half cycle clocking operation
• Self-check diagnostics software mode to check if the micro edge positioner (MEP) logic is running
optimally
• Enables high resolution output swapping on the EPWMxA and EPWMxB output
• Enables high-resolution output on EPWMxB signal output via inversion of EPWMxA signal output
• Enables high-resolution period, duty and phase control on the EPWMxA and EPWMxB output on
devices with an ePWM module. See the device-specific data manual to determine if your device has
an ePWM module for high-resolution period support.
The ePWM peripheral is used to perform a function mathematically equivalent to a digital-to-analog
converter (DAC). As shown in Figure 14-78, the effective resolution for conventionally generated PWM is
a function of PWM frequency (or period) and system clock frequency.
Figure 14-78. Resolution Calculations for Conventionally Generated PWM
TPWM
PWM resolution (%) = FPWM/FEPWMCLK x 100%
PWM resolution (bits) = Log2 (TPWM/TEPWMCLK)
PWM
t
TEPWMCLK
If the required PWM operating frequency does not offer sufficient resolution in PWM mode, you may want
to consider HRPWM. As an example of improved performance offered by HRPWM, the table below shows
resolution in bits for various PWM frequencies. These values assume a MEP step size of 180 ps. See the
device-specific data sheet for typical and maximum performance specifications for the MEP.
1814Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
High-Resolution Pulse Width Modulator (HRPWM)
www.ti.com
Table 14-13. Resolution for PWM and HRPWM
PWM Freq
Regular Resolution (PWM)
High Resolution (HRPWM)
100 MHz EPWMCLK
(kHz)
Bits
%
Bits
%
20
12.3
0.02
18.1
0.000
50
11
0.05
16.8
0.001
100
10
0.1
15.8
0.002
150
9.4
0.15
15.2
0.003
200
9
0.2
14.8
0.004
250
8.6
0.25
14.4
0.005
500
7.6
0.5
13.4
0.009
1000
6.6
1
12.4
0.018
1500
6.1
1.5
11.9
0.027
2000
5.6
2
11.4
0.036
Although each application may differ, typical low frequency PWM operation (below 250 kHz) may not
require HRPWM. HRPWM capability is most useful for high frequency PWM requirements of power
conversion topologies such as:
• Single-phase buck, boost, and flyback
• Multi-phase buck, boost, and flyback
• Phase-shifted full bridge
• Direct modulation of D-Class power amplifiers
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1815
High-Resolution Pulse Width Modulator (HRPWM)
www.ti.com
14.14.1 Operational Description of HRPWM
The HRPWM is based on micro-edge positioner (MEP) technology. MEP logic is capable of positioning an
edge very finely by sub-dividing one coarse system clock of a conventional PWM generator. The time step
accuracy is on the order of 150 ps. See the device-specific data sheet for the typical MEP step size on a
particular device. The HRPWM also has a self-check software diagnostics mode to check if the MEP logic
is running optimally, under all operating conditions. Details on software diagnostics and functions are in
Section 14.14.1.7.
The figure below shows the relationship between one coarse system clock and edge position in terms of
MEP steps, which are controlled via an 8-bit field in the Compare A extension register (CMPAHR). The
same operating logic applies to CMPBHR as well.
Figure 14-79. Operating Logic Using MEP
(1 EPWMCLK cycle)
+ 0.5 (rounding)
(upper 8 bits)
(0x0080 in Q8 format)
To generate an HRPWM waveform, configure the ePWM registers as you would to generate a
conventional PWM of a given frequency and polarity. The HRPWM works together with the ePWM
registers to extend edge resolution. Although many programming combinations are possible, only a few
are needed and practical. These methods are described in Section 14.14.1.8.
14.14.1.1 Controlling the HRPWM Capabilities
The MEP of the HRPWM is controlled by six extension registers. These HRPWM registers are
concatenated with the 16-bit TBPHS, TBPRD, CMPA, CMPBM, DBREDM & DBFEDM registers used to
control PWM operation.
• TBPHSHR - Time Base Phase High Resolution Register
• CMPAHR - Counter Compare A High Resolution Register; CMPAHR is for use with the AQ output of
Channel A, and is not related to CMPA
• TBPRDHR - Time Base Period High Resolution Register. (available on some devices)
• CMPBHR - Counter Compare B High Resolution Register; CMPBHR is for use with the AQ output of
Channel B, and is not related to CMPB
• DBREDHR - Deadband Generator Rising Edge Delay High Resolution Register
• DBFEDHR - Deadband Generator Falling Edge Delay High Resolution Register
NOTE: TBPHSHR must not be used. Instead TRREM (translator remainder register) must be used
to mimic the functionality of TBPHSHR.
1816
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
High-Resolution Pulse Width Modulator (HRPWM)
www.ti.com
Figure 14-80. HRPWM Extension Registers and Memory Configuration
31
TBPHSHR (8)
Reserved (8)
16 15
TBPHS (16)
8 7
0
Reserved(8)
TBPHSHR (8)
TBPHS (16)
Single 32-bit write
31
A
CMPAHR (8)
Reserved (8)
16 15
A
CMPA (16)
8 7
A
0
Reserved(8)
CMPAHR (8)
CMPAA (16)
Single 32-bit write
A
TBPRDHR (8)
31
Reserved (8)
16 15
TBPRD(16)
8 7
TBPRDHR (8)
0
Reserved(8)
TBPRDA (16)
Single 32-bit write
A
CMPBHR (8)
31
Reserved (8)
16 15
CMPB (16)
8 7
CMPBHR (8)
0
Reserved(8)
CMPBA (16)
Single 32-bit write
A
DBFEDHR (7)
31
Reserved (9)
9 8
16 15
DBFED(16)
DBFEDHR (7)
0
Reserved(8)
DBFEDA (16)
Single 32-bit write
A
DBREDHR (7)
31
Reserved (9)
16 15
DBRED(16)
9 8
DBREDHR(7)
0
Reserved(8)
DBREDA (16)
Single 32-bit write
A
Dependant upon your device, these registers may be mirrored and can be written to at two different memory
locations. Check the device-specific Technical Reference Manual's ePWM chapter for more details on how to read
and write to these locations.
NOTE: HRPWM capabilities on Deadband Rising Edge Delay and Falling Edge Delay is applicable
only during Dead Band half cycle clocking Operation. The number of MEP steps is half in
size [ bits 15:9 ]than duty and phase high resolution registers for the same reason
HRPWM capabilities are controlled using the Channel A & B PWM signal path. HRPWM support on the
Dead band signal path is available by properly configuring the HRCNFG2 register. The following figure
shows how the HRPWM interfaces with the 8-bit extension registers.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1817
High-Resolution Pulse Width Modulator (HRPWM)
www.ti.com
Figure 14-81. HRPWM System Interface
Time-Base (TB)
CTR=ZERO
TBPRD Shadow (24)
Sync
In/Out
Select
Mux
CTR=CMPB
TBPRDHR (8)
TBPRD Active (24)
Disabled
EPWMxSYNCO
8
CTR=PRD
TBCTL[SYNCOSEL]
TBCTL[PHSEN]
Counter
Up/Down
(16 Bit)
TBCTL[SWFSYNC]
(Software Forced
Sync)
CTR=ZERO
TBCTR
Active (16)
CTR=PRD
CTR_Dir
CTR=ZERO
TBPHSHR (8)
16
CTR=CMPA
Phase
Control
CTR=CMPB
CTR=CMPC
CTR=CMPD
Event
Trigger
and
Interrupt
(ET)
CTR_Dir
Counter Compare (CC)
CTR=CMPA
EPWMxINT
CTR=PRD or ZERO
8
TBPHS Active (24)
EPWMxSYNCI
DCAEVT1.sync
DCBEVT1.sync
Action
Qualifier
(AQ)
DCAEVT1.soc
DCBEVT1.soc
EPWMxSOCA
EPWMxSOCB
EPWMxSOCA
ADC
EPWMxSOCB
(A)
(A)
CMPAHR (8)
16
CMPA Active (24)
CMPA Shadow (24)
EPWMA
ePWMxA
Dead
Band
(DB)
CTR=CMPB
CMPBHR (8)
16
HiRes PWM (HRPWM)
CMPAHR (8)
PWM
Chopper
(PC)
Trip
Zone
(TZ)
ePWMxB
EPWMB
CMPB Active (24)
CMPB Shadow (24)
CMPBHR (8)
EPWMxTZINT
TZ1 to TZ3
TBCNT(16)
CTR=CMPC
CMPC[15-0]
16
CMPC Active (16)
EMUSTOP
CTR=ZERO
DCAEVT1.inter
DCBEVT1.inter
DCAEVT2.inter
DCBEVT2.inter
CLOCKFAIL
(B)
EQEPxERR
DCAEVT1.force
DCAEVT2.force
DCBEVT1.force
CMPC Shadow (16)
DCBEVT2.force
(A)
(A)
(A)
(A)
TBCNT(16)
CTR=CMPD
CMPD[15-0]
16
CMPD Active (16)
CMPD Shadow (16)
A
1818
These events are generated by the ePWM digital compare (DC) submodule.
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
High-Resolution Pulse Width Modulator (HRPWM)
www.ti.com
Figure 14-82. HRPWM Block Diagram
1
TBPHSHR(8)
2
CMPAHR(8)
HRPWM
Micro-edge Positioner
(MEP) Calibration Module
2
CMPBHR(8)
1
TBPRDHR(8)
Action
Qualifier
(AQ)
DBREDHR(7)
3
DBFEDHR(7)
3
HRCNFG/HRCNFG2
HRPWR
HRMSTEP
High- Resolution PWM (HRPWM)
EPWMxAO
EPWMA
Dead
band
(DB)
PWM
chopper
(PC)
Trip
zone
(TZ)
EPWMB
EPWMxBO
(1)
From ePWM Time-base (TB) submodule
(2)
From ePWM counter-compare (CC) submodule
(3)
From ePWM Deadband (DB) submodule
14.14.1.2 HRPWM Source Clock
The HRPWM module and HRCAL module are clocked from the EPWM1CLK. Therefore EPWM1CLK must
be enabled for the HRCAL or any of the HRPWM modules to be enabled. The figure Figure 14-83 shows
the HRCAL and HRPWM modules are sourced from ePWM1 clock source.
Figure 14-83. HRPWM and HRCAL Source Clock
EPWM1CLK
ePWM1
EPWM2CLK
ePWM2
CLK
HRCAL
HRMSTEP
EPWM3CLK
EPWMxCLK
ePWM3
ePWMx
CLK
HRPWM1
CLK
HRPWM2
CLK
HRPWM3
CLK
HRPWMx
14.14.1.3 Configuring the HRPWM
Once the ePWM has been configured to provide conventional PWM of a given frequency and polarity, the
HRPWM is configured by programming the HRCNFG register in that particular ePWM module's register
space. This register provides the following configuration options:
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1819
High-Resolution Pulse Width Modulator (HRPWM)
www.ti.com
Edge Mode — The MEP can be programmed to provide precise position control on the rising edge (RE),
falling edge (FE) or both edges (BE) at the same time. FE and RE are used for power topologies
requiring duty cycle control(CMPA or CMPB high-resolution control), while BE is used for topologies
requiring phase shifting, for example, phase shifted full bridge (TBPHS or TBPRD high-resolution
control).
Control Mode — The MEP is programmed to be controlled either from the CMPAHR / CMPBHR register
in case of duty cycle control or the TBPHSHR register (phase control). RE or FE control mode
should be used with CMPAHR or CMPBHR register. BE control mode should be used with
TBPHSHR register. When the MEP is controlled from the TBPRDHR register (period control) the
duty cycle and phase can also be controlled via their respective high-resolution registers.
Shadow Mode — This mode provides the same shadowing (double buffering) option as in regular PWM
mode. This option is valid only when operating from the CMPAHR, CMPBHR and TBPRDHR
registers and should be chosen to be the same as the regular load option for the CMPA, CMPB
register. If TBPHSHR is used, then this option has no effect.
High-Resolution B Signal Control — The B signal path of an ePWM channel can generate a highresolution output by outputting an inverted version of the high-resolution ePWMxA signal on the
ePWMxB pin. A Type 2, or Type 4 HRPWM module can also enable high-resolution features on the
B signal path indepedently of the A signal path as well.
Swap ePWMxA and ePWMxB Outputs — This mode enables the swapping of the high resolution A & B
outputs . The mode selection allows either A & B Outputs Unchanged or A Output Comes Out On B
and B Output Comes Out On A
Auto-conversion Mode — This mode is used in conjunction with the scale factor optimization (SFO)
software only. For a type 4 HRPWM module, below is a description of the Auto-conversion Mode
taking CMPAHR as an example. If auto-conversion is enabled, CMPAHR =
fraction(PWMduty*PWMperiod)>1+SWVDELVAL
011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL
100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL
Note: Delay value between the consecutive edge captures can
optionally be divided by using these bits.
Reset type: SYSRSn
6-5
1864
RESERVED
R-0
Enhanced Pulse Width Modulator (ePWM)
0h
Reserved
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-33. VCAPCTL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4-2
TRIGSEL
R/W
0h
Status of Numbered of Captured Events
000: Capture sequence is triggered by software via writes to
VCAPCTL[VCAPSTART].
001: Capture sequence is triggered by CNT_zero event.
010: Capture sequence is triggered by PRD_eq event.
011: Capture sequence is triggered by CNT_zero or PRD_eq event.
100: Capture sequence is triggered by DCAEVT1 event.
101: Capture sequence is triggered by DCAEVT2 event.
110: Capture sequence is triggered by DCBEVT1 event.
111: Capture sequence is triggered by DCBEVT2 event.
Note: Valley capture sequence triggered by the selected event in this
register field. Once the chosen event occurs the capture sequence is
armed. Event captures occur based of the event chosen in
DCFCTL[SRCSEL] register.
Note: Same event may not be chosen in both DCFCTL[SRCSEL]
and VCAPCTL[TRIGSEL] registers.
Note: Once the chosen event in VCAPCTL[TRIGSEL] occurs,
irrespective of the current capture status, capture sequence is
retriggered.
Reset type: SYSRSn
1
VCAPSTART
R-0/W1S
0h
Valley Capture Start
0: Writing a 0 has no effect
1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0
Note: This bit is used to start valley capture sequence through
software. VCAPCTL[TRIGSEL] has to be chosen for software trigger
for this bit to have any effect. Writing of 1 will result in one capture
sequence trigger.
Reset type: SYSRSn
0
VCAPE
R/W
0h
Valley Capture Enable/Disable
0: Disabled
1: Enabled
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1865
ePWM Registers
www.ti.com
14.15.2.13 VCNTCFG Register (Offset = 19h) [reset = 0h]
VCNTCFG is shown in Figure 14-105 and described in Table 14-34.
Return to the Summary Table.
Valley Counter Config Register
Figure 14-105. VCNTCFG Register
15
STOPEDGEST
S
R-0h
14
7
STARTEDGES
TS
R-0h
6
13
RESERVED
12
11
10
9
8
1
0
STOPEDGE
R-0-0h
R/W-0h
5
RESERVED
4
3
2
STARTEDGE
R-0-0h
R/W-0h
Table 14-34. VCNTCFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
STOPEDGESTS
R
0h
Stop Edge Status Bit
0: Stop edge has not occurred
1: Stop edge occurred
Note: This bit is set only after the trigger sequence is armed (upon
occurrence of trigger pulse selected through VCAPCTL[TRIGSEL])
and STOPEDGE occurs.
Note:This bit is reset by the occurrence of the trigger pulse selected
through VCAPCTL[TRIGSEL]
Reset type: SYSRSn
14-12
RESERVED
R-0
0h
Reserved
11-8
STOPEDGE
R/W
0h
Counter Stop Edge Selection
Once the counter operation is armed, upon occurrence of trigger
pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter
would stop counting upon the occurrence of chosen number of
events thorough this bit field. Stop counting on occurrence of:
0000: Do not stop
0001
1st edge
0010: 2nd edge
0011: 3rd edge
...
1,1,1,1: 15th edge
Reset type: SYSRSn
7
STARTEDGESTS
R
0h
Start Edge Status Bit
0: Start edge has not occurred
1: Start edge occurred
Note: This bit is set only after the trigger sequence is armed (upon
occurrence of trigger pulse selected through VCAPCTL[TRIGSEL])
and STARTEDGE occurs.
Note:This bit is reset by the occurrence of the trigger pulse selected
through VCAPCTL[TRIGSEL]
Reset type: SYSRSn
6-4
1866
RESERVED
R-0
Enhanced Pulse Width Modulator (ePWM)
0h
Reserved
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-34. VCNTCFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
STARTEDGE
R/W
0h
Counter Start Edge Selection
Once the counter operation is armed, upon occurrence of trigger
pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter
would start counting upon the occurrence of chosen number of
events thorough this bit field. Start counting on occurrence of
0000: Do not start
0001: 1st edge
0010: 2nd edge
0011: 3rd edge
...
1111: 15th edge
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1867
ePWM Registers
www.ti.com
14.15.2.14 HRCNFG Register (Offset = 20h) [reset = 0h]
HRCNFG is shown in Figure 14-106 and described in Table 14-35.
Return to the Summary Table.
HRPWM Configuration Register
This register is only accessible on EPWM modules with HRPWM capabilities.
Figure 14-106. HRCNFG Register
15
14
RESERVED
7
SWAPAB
R/W-0h
6
AUTOCONV
R/W-0h
13
RESERVED
R-0-0h
12
5
SELOUTB
R/W-0h
4
11
HRLOADB
R/W-0h
3
HRLOAD
R/W-0h
10
CTLMODEB
R/W-0h
9
2
CTLMODE
R/W-0h
1
8
EDGMODEB
R/W-0h
0
EDGMODE
R/W-0h
Table 14-35. HRCNFG Register Field Descriptions
Field
Type
Reset
Description
15-14
Bit
RESERVED
R/W
0h
Reserved
13
RESERVED
R-0
0h
Reserved
HRLOADB
R/W
0h
Shadow Mode Bit
12-11
Selects the time event that loads the CMPBHR shadow value into
the active register.
00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR
= 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period
(TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Reserved
Reset type: SYSRSn
10
CTLMODEB
R/W
0h
Control Mode Bits
Selects the register (CMP/TBPRD or TBPHS) that controls the MEP:
0: CMPBHR(8) or TBPRDHR(8) Register controls the edge position
(i.e., this is duty or period control mode). (Default on Reset)
1: TBPHSHR(8) Register controls the edge position (i.e., this is
phase control mode).
Reset type: SYSRSn
9-8
EDGMODEB
R/W
0h
Edge Mode Bits
Selects the edge of the PWM that is controlled by the micro-edge
position (MEP) logic:
00: HRPWM capability is disabled (default on reset)
01: MEP control of rising edge (CMPBHR)
10: MEP control of falling edge (CMPBHR)
11: MEP control of both edges (TBPHSHR or TBPRDHR)
Reset type: SYSRSn
7
SWAPAB
R/W
0h
Swap ePWM A & B Output Signals
This bit enables the swapping of the A & B signal outputs. The
selection is as follows:
0: ePWMxA and ePWMxB outputs are unchanged.
1: ePWMxA signal appears on ePWMxB output and ePWMxB signal
appears on ePWMxA output.
Reset type: SYSRSn
1868
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-35. HRCNFG Register Field Descriptions (continued)
Bit
6
Field
Type
Reset
Description
AUTOCONV
R/W
0h
Auto Convert Delay Line Value
Selects whether the fractional duty cycle/period/phase in the
CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by
the MEP scale factor in the HRMSTEP register or manually scaled
by calculations in application software. The SFO library function
automatically updates the HRMSTEP register with the appropriate
MEP scale factor.
0: Automatic HRMSTEP scaling is disabled.
1: Automatic HRMSTEP scaling is enabled.
If application software is manually scaling the fractional duty cycle, or
phase (i.e. software sets CMPAHR = (fraction(PWMduty *
PWMperiod) * MEP Scale Factor) High, High -> Low)
Note: This action is not qualified by counter direction (CNT_dir)
Reset type: SYSRSn
2
OTSFA
R-0/W1S
0h
One-Time Software Forced Event on Output A
0: Writing a 0 (zero) has no effect. Always reads back a 0. This bit is
auto cleared once a write to this register is complete ( i.e., a forced
event is initiated). This is a one-shot forced event. It can be
overridden by another subsequent event on output A.
1: Initiates a single software forced event
Reset type: SYSRSn
1892
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-48. AQSFRC Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1-0
ACTSFA
R/W
0h
Action When One-Time Software Force A Is Invoked
00: Does nothing (action disabled)
01: Clear (low)
10: Set (high)
11: Toggle (Low -> High, High -> Low)
Note: This action is not qualified by counter direction (CNT_dir)
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1893
ePWM Registers
www.ti.com
14.15.2.28 AQCSFRC Register (Offset = 49h) [reset = 0h]
AQCSFRC is shown in Figure 14-120 and described in Table 14-49.
Return to the Summary Table.
Action Qualifier Continuous S/W Force Register
Figure 14-120. AQCSFRC Register
15
14
13
12
11
10
9
2
1
8
RESERVED
R-0-0h
7
6
5
4
3
RESERVED
R-0-0h
CSFB
R/W-0h
0
CSFA
R/W-0h
Table 14-49. AQCSFRC Register Field Descriptions
Field
Type
Reset
Description
15-4
Bit
RESERVED
R-0
0h
Reserved
3-2
CSFB
R/W
0h
Continuous Software Force on Output B
In immediate mode, a continuous force takes effect on the next
TBCLK edge. In shadow mode, a continuous force takes effect on
the next TBCLK edge after a shadow load into the active register. To
configure shadow mode, use AQSFRC[RLDCSF].
00: Software forcing is disabled and has no effect
01: Forces a continuous low on output B
10: Forces a continuous high on output B
11: Software forcing is disabled and has no effect
Reset type: SYSRSn
1-0
CSFA
R/W
0h
Continuous Software Force on Output A
In immediate mode, a continuous force takes effect on the next
TBCLK edge. In shadow mode, a continuous force takes effect on
the next TBCLK edge after a shadow load into the active register.
00: Software forcing is disabled and has no effect
01: Forces a continuous low on output A
10: Forces a continuous high on output A
11: Software forcing is disabled and has no effect
Reset type: SYSRSn
1894
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.29 DBREDHR Register (Offset = 50h) [reset = 0h]
DBREDHR is shown in Figure 14-121 and described in Table 14-50.
Return to the Summary Table.
Dead-Band Generator Rising Edge Delay High Resolution Mirror Register
Figure 14-121. DBREDHR Register
15
14
13
12
DBREDHR
R/W-0h
11
10
9
8
RESERVED
R-0h
7
6
5
4
RESERVED
3
2
1
0
RESERVED
R-0h
Table 14-50. DBREDHR Register Field Descriptions
Field
Type
Reset
Description
15-9
Bit
DBREDHR
R/W
0h
Dead Band Rising Edge Delay High Resolution Bits
Reset type: SYSRSn
8
RESERVED
R
0h
Reserved
7-1
RESERVED
R
0h
Reserved
0
RESERVED
R
0h
Reserved
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1895
ePWM Registers
www.ti.com
14.15.2.30 DBRED Register (Offset = 51h) [reset = 0h]
DBRED is shown in Figure 14-122 and described in Table 14-51.
Return to the Summary Table.
Dead-Band Generator Rising Edge Delay High Resolution Mirror Register
Figure 14-122. DBRED Register
15
14
13
12
11
RESERVED
R-0h
7
10
9
8
2
1
0
DBRED
R/W-0h
6
5
4
3
DBRED
R/W-0h
Table 14-51. DBRED Register Field Descriptions
Field
Type
Reset
Description
15-14
Bit
RESERVED
R
0h
Reserved
13-0
DBRED
R/W
0h
Rising edge delay value
Reset type: SYSRSn
1896
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.31 DBFEDHR Register (Offset = 52h) [reset = 0h]
DBFEDHR is shown in Figure 14-123 and described in Table 14-52.
Return to the Summary Table.
Dead-Band Generator Falling Edge Delay High Resolution Register
Figure 14-123. DBFEDHR Register
15
14
13
12
DBFEDHR
R/W-0h
11
10
9
8
RESERVED
R-0h
7
6
5
4
RESERVED
3
2
1
0
RESERVED
R-0h
Table 14-52. DBFEDHR Register Field Descriptions
Bit
Field
Type
Reset
Description
DBFEDHR
R/W
0h
Dead Band Falling Edge Delay High Resolution Bits
Reset type: SYSRSn
8
RESERVED
R
0h
Reserved
7-1
RESERVED
R
0h
Reserved
0
RESERVED
R
0h
Reserved
15-9
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1897
ePWM Registers
www.ti.com
14.15.2.32 DBFED Register (Offset = 53h) [reset = 0h]
DBFED is shown in Figure 14-124 and described in Table 14-53.
Return to the Summary Table.
Dead-Band Generator Falling Edge Delay Count Register
Figure 14-124. DBFED Register
15
14
13
12
11
RESERVED
R-0h
7
10
9
8
2
1
0
DBFED
R/W-0h
6
5
4
3
DBFED
R/W-0h
Table 14-53. DBFED Register Field Descriptions
Field
Type
Reset
Description
15-14
Bit
RESERVED
R
0h
Reserved
13-0
DBFED
R/W
0h
Falling Edge Delay Count
14-bit counter
Reset type: SYSRSn
1898
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.33 TBPHS Register (Offset = 60h) [reset = 0h]
TBPHS is shown in Figure 14-125 and described in Table 14-54.
Return to the Summary Table.
Time Base Phase High
Figure 14-125. TBPHS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TBPHS
R/W-0h
9
8 7 6
TBPHSHR
R/W-0h
5
4
3
2
1
0
Table 14-54. TBPHS Register Field Descriptions
Bit
31-16
Field
Type
Reset
Description
TBPHS
R/W
0h
Phase Offset Register
These bits set time-base counter phase of the selected ePWM
relative to the time-base that is supplying the synchronization input
signal.
- If TBCTL[PHSEN] = 0, then the synchronization event is ignored
and the time-base counter is not loaded with the phase.
- If TBCTL[PHSEN] = 1, then the time-base counter (TBCTR) will be
loaded with the phase (TBPHS) when a synchronization event
occurs. The synchronization event can be initiated by the input
synchronization signal (EPWMxSYNCI) or by a software forced
synchronization.
Reset type: SYSRSn
15-0
TBPHSHR
R/W
0h
Phase Offset (High Resolution) Register.
TBPHSHR must not be used. Instead TRREM (translator remainder
register) must be used to mimic the functionality of TBPHSHR.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1899
ePWM Registers
www.ti.com
14.15.2.34 TBPRDHR Register (Offset = 62h) [reset = 0h]
TBPRDHR is shown in Figure 14-126 and described in Table 14-55.
Return to the Summary Table.
Time Base Period High Resolution Register
Figure 14-126. TBPRDHR Register
15
14
13
12
11
10
9
8
3
2
1
0
TBPRDHR
R/W-0h
7
6
5
4
TBPRDHR
R/W-0h
Table 14-55. TBPRDHR Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
TBPRDHR
R/W
0h
Period High Resolution Bits
The upper 8-bits contain the high-resolution portion of the period
value. The TBPRDHR register is not affected by the TBCTL[PRDLD]
bit. Reads from this register always reflect the shadow register.
Likewise writes are also to the shadow register. The TBPRDHR
register is only used when the high resolution period feature is
enabled. This register is only available with ePWM modules which
support high-resolution period control.
Reset type: SYSRSn
1900
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.35 TBPRD Register (Offset = 63h) [reset = 0h]
TBPRD is shown in Figure 14-127 and described in Table 14-56.
Return to the Summary Table.
Time Base Period Register
Figure 14-127. TBPRD Register
15
14
13
12
11
10
9
8
3
2
1
0
TBPRD
R/W-0h
7
6
5
4
TBPRD
R/W-0h
Table 14-56. TBPRD Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
TBPRD
R/W
0h
Time Base Period Register
These bits determine the period of the time-base counter. This sets
the PWM frequency. Shadowing of this register is enabled and
disabled by the TBCTL[PRDLD] bit. By default this register is
shadowed.
- If TBCTL[PRDLD] = 0, then the shadow is enabled and any write or
read will automatically go to the shadow register. In this case, the
active register will be loaded from the shadow register when the
time-base counter equals zero.
- If TBCTL[PRDLD] = 1, then the shadow is disabled and any write
or read will go directly to the active register, that is the register
actively controlling the hardware.
- The active and shadow registers share the same memory map
address.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1901
ePWM Registers
www.ti.com
14.15.2.36 CMPA Register (Offset = 6Ah) [reset = 0h]
CMPA is shown in Figure 14-128 and described in Table 14-57.
Return to the Summary Table.
Counter Compare A Register
Figure 14-128. CMPA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CMPA
R/W-0h
9
8 7 6
CMPAHR
R/W-0h
5
4
3
2
1
0
Table 14-57. CMPA Register Field Descriptions
Bit
Field
Type
Reset
Description
31-16
CMPA
R/W
0h
Compare A Register
The value in the active CMPA register is continuously compared to
the time-base counter (TBCTR). When the values are equal, the
counter-compare module generates a "time-base counter equal to
counter compare A" event. This event is sent to the action-qualifier
where it is qualified and converted it into one or more actions. These
actions can be applied to either the EPWMxA or the EPWMxB
output depending on the configuration of the AQCTLA and AQCTLB
registers. The actions that can be defined in the AQCTLA and
AQCTLB registers include:
- Do nothing
the event is ignored.
- Clear: Pull the EPWMxA and/or EPWMxB signal low
- Set: Pull the EPWMxA and/or EPWMxB signal high
- Toggle the EPWMxA and/or EPWMxB signal
Shadowing of this register is enabled and disabled by the
CMPCTL[SHDWAMODE] bit. By default this register is shadowed.
- If CMPCTL[SHDWAMODE] = 0, then the shadow is enabled and
any write or read will automatically go to the shadow register. In this
case, the CMPCTL[LOADAMODE] bit field determines which event
will load the active register from the shadow register.
- Before a write, the CMPCTL[SHDWAFULL] bit can be read to
determine if the shadow register is currently full.
- If CMPCTL[SHDWAMODE] = 1, then the shadow register is
disabled and any write or read will go directly to the active register,
that is the register actively controlling the hardware.
- In either mode, the active and shadow registers share the same
memory map address.
Reset type: SYSRSn
15-0
CMPAHR
R/W
0h
Compare A HRPWM Extension Register
The UPPER 8-bits contain the high-resolution portion (most
significant 8-bits) of the counter-compare A value. CMPA:CMPAHR
can be accessed in a single 32-bit read/write. Shadowing is enabled
and disabled by the CMPCTL[SHDWAMODE] bit as described for
the CMPA register.
The lower 8 bits in this register are ignored
Reset type: SYSRSn
1902
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.37 CMPB Register (Offset = 6Ch) [reset = 0h]
CMPB is shown in Figure 14-129 and described in Table 14-58.
Return to the Summary Table.
Compare B Register
Figure 14-129. CMPB Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CMPB
R/W-0h
9
8 7 6
CMPBHR
R/W-0h
5
4
3
2
1
0
Table 14-58. CMPB Register Field Descriptions
Bit
Field
Type
Reset
Description
31-16
CMPB
R/W
0h
Compare B Register
The value in the active CMPB register is continuously compared to
the time-base counter (TBCTR). When the values are equal, the
counter-compare module generates a "time-base counter equal to
counter compare B" event. This event is sent to the action-qualifier
where it is qualified and converted it into one or more actions. These
actions can be applied to either the EPWMxA or the EPWMxB
output depending on the configuration of the AQCTLA and AQCTLB
registers. The actions that can be defined in the AQCTLA and
AQCTLB registers include:
- Do nothing
the event is ignored.
- Clear: Pull the EPWMxA and/or EPWMxB signal low
- Set: Pull the EPWMxA and/or EPWMxB signal high
- Toggle the EPWMxA and/or EPWMxB signal
Shadowing of this register is enabled and disabled by the
CMPCTL[SHDWBMODE] bit. By default this register is shadowed.
- If CMPCTL[SHDWBMODE] = 0, then the shadow is enabled and
any write or read will automatically go to the shadow register. In this
case, the CMPCTL[LOADBMODE] bit field determines which event
will load the active register from the shadow register.
- Before a write, the CMPCTL[SHDWBFULL] bit can be read to
determine if the shadow register is currently full.
- If CMPCTL[SHDWBMODE] = 1, then the shadow register is
disabled and any write or read will go directly to the active register,
that is the register actively controlling the hardware.
- In either mode, the active and shadow registers share the same
memory map address.
Reset type: SYSRSn
15-0
CMPBHR
R/W
0h
Compare B High Resolution Bits
The lower 8 bits in this register are ignored
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1903
ePWM Registers
www.ti.com
14.15.2.38 CMPC Register (Offset = 6Fh) [reset = 0h]
CMPC is shown in Figure 14-130 and described in Table 14-59.
Return to the Summary Table.
Counter Compare C Register
LINK feature access should always be 16-bit
Figure 14-130. CMPC Register
15
14
13
12
11
10
9
8
3
2
1
0
CMPC
R/W-0h
7
6
5
4
CMPC
R/W-0h
Table 14-59. CMPC Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
CMPC
R/W
0h
Compare C Register
The value in the active CMPC register is continuously compared to
the time-base counter (TBCTR). When the values are equal, the
counter-compare module generates a "time-base counter equal to
counter compare C" event.
Shadowing of this register is enabled and disabled by the
CMPCTL2[SHDWCMODE] bit. By default this register is shadowed.
- If CMPCTL2[SHDWCMODE] = 0, then the shadow is enabled and
any write or read will automatically go to the shadow register. In this
case, the CMPCTL2[LOADCMODE] bit field determines which event
will load the active register from the shadow register:
- If CMPCTL2[SHDWCMODE] = 1, then the shadow register is
disabled and any write or read will go directly to the active register
that is, the register actively controlling the hardware.
- In either mode, the active and shadow registers share the same
memory map address.
Reset type: SYSRSn
1904
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.39 CMPD Register (Offset = 71h) [reset = 0h]
CMPD is shown in Figure 14-131 and described in Table 14-60.
Return to the Summary Table.
Counter Compare D Register
LINK feature access should always be 16-bit
Figure 14-131. CMPD Register
15
14
13
12
11
10
9
8
3
2
1
0
CMPD
R/W-0h
7
6
5
4
CMPD
R/W-0h
Table 14-60. CMPD Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
CMPD
R/W
0h
Compare D Register
The value in the active CMPD register is continuously compared to
the time-base counter (TBCTR). When the values are equal, the
counter-compare module generates a "time-base counter equal to
counter compare D" event.
Shadowing of this register is enabled and disabled by the
CMPCTL2[SHDWDMODE] bit. By default this register is shadowed.
- If CMPCTL2[SHDWDMODE] = 0, then the shadow is enabled and
any write or read will automatically go to the shadow register. In this
case, the CMPCTL2[LOADDMODE] bit field determines which event
will load the active register from the shadow register:
- If CMPCTL2[SHDWDMODE] = 1, then the shadow register is
disabled and any write or read will go directly to the active register
that is, the register actively controlling the hardware.
- In either mode, the active and shadow registers share the same
memory map address.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1905
ePWM Registers
www.ti.com
14.15.2.40 GLDCTL2 Register (Offset = 74h) [reset = 0h]
GLDCTL2 is shown in Figure 14-132 and described in Table 14-61.
Return to the Summary Table.
Global PWM Load Control Register 2
Figure 14-132. GLDCTL2 Register
15
14
13
12
11
10
9
8
3
2
1
GFRCLD
R-0/W1S-0h
0
OSHTLD
R-0/W1S-0h
RESERVED
R-0-0h
7
6
5
4
RESERVED
R-0-0h
Table 14-61. GLDCTL2 Register Field Descriptions
Bit
15-2
1
Field
Type
Reset
Description
RESERVED
R-0
0h
Reserved
GFRCLD
R-0/W1S
0h
Force Load Event in One Shot Mode
0: Writing of 0 will be ignored. Always reads back a 0.
1: Force one load event at the input of the event pre-scale counter
as shown in the diagram below. This bit is intended to be used for
testing and/or software force loading of the events in global load
mode.
Reset type: SYSRSn
0
OSHTLD
R-0/W1S
0h
Enable Reload Event in One Shot Mode
0: Writing of 0 will be ignored. Always reads back a 0.
1: Turns the one shot latch condition ON. Upon occurrence of a
chosen load strobe, one shadow to active reload occurs and the
latch will be cleared. Hence writing 1 to this bit would allow one load
strobe event to pass through and block further strobe events.
Reset type: SYSRSn
1906
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.41 SWVDELVAL Register (Offset = 77h) [reset = 0h]
SWVDELVAL is shown in Figure 14-133 and described in Table 14-62.
Return to the Summary Table.
Software Valley Mode Delay Register
Figure 14-133. SWVDELVAL Register
15
14
13
12
11
10
9
8
3
2
1
0
SWVDELVAL
R/W-0h
7
6
5
4
SWVDELVAL
R/W-0h
Table 14-62. SWVDELVAL Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
SWVDELVAL
R/W
0h
Software Valley Delay Value Register
This register can be optionally used define offset value for the
hardware calculated delay HWDELAYVAL as defined in
VCAPCTL[VDELAYDIV] bits.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1907
ePWM Registers
www.ti.com
14.15.2.42 TZSEL Register (Offset = 80h) [reset = 0h]
TZSEL is shown in Figure 14-134 and described in Table 14-63.
Return to the Summary Table.
Trip Zone Select Register
Figure 14-134. TZSEL Register
15
DCBEVT1
R/W-0h
14
DCAEVT1
R/W-0h
13
OSHT6
R/W-0h
12
OSHT5
R/W-0h
11
OSHT4
R/W-0h
10
OSHT3
R/W-0h
9
OSHT2
R/W-0h
8
OSHT1
R/W-0h
7
DCBEVT2
R/W-0h
6
DCAEVT2
R/W-0h
5
CBC6
R/W-0h
4
CBC5
R/W-0h
3
CBC4
R/W-0h
2
CBC3
R/W-0h
1
CBC2
R/W-0h
0
CBC1
R/W-0h
Table 14-63. TZSEL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
DCBEVT1
R/W
0h
Digital Compare Output B Event 1 Select
0: Disable DCBEVT1 as one-shot-trip source for this ePWM module.
1: Enable DCBEVT1 as one-shot-trip source for this ePWM module.
Reset type: SYSRSn
14
DCAEVT1
R/W
0h
Digital Compare Output A Event 1 Select
0: Disable DCAEVT1 as one-shot-trip source for this ePWM module.
1: Enable DCAEVT1 as one-shot-trip source for this ePWM module.
Reset type: SYSRSn
13
OSHT6
R/W
0h
Trip-zone 6 (TZ6) Select
0: Disable TZ6 as a one-shot trip source for this ePWM module
1: Enable TZ6 as a one-shot trip source for this ePWM module
Reset type: SYSRSn
12
OSHT5
R/W
0h
Trip-zone 5 (TZ5) Select
0: Disable TZ5 as a one-shot trip source for this ePWM module
1: Enable TZ5 as a one-shot trip source for this ePWM module
Reset type: SYSRSn
11
OSHT4
R/W
0h
Trip-zone 4 (TZ4) Select
0: Disable TZ4 as a one-shot trip source for this ePWM module
1: Enable TZ4 as a one-shot trip source for this ePWM module
Reset type: SYSRSn
10
OSHT3
R/W
0h
Trip-zone 3 (TZ3) Select
0: Disable TZ3 as a one-shot trip source for this ePWM module
1: Enable TZ3 as a one-shot trip source for this ePWM module
Reset type: SYSRSn
9
OSHT2
R/W
0h
Trip-zone 2 (TZ2) Select
0: Disable TZ2 as a one-shot trip source for this ePWM module
1: Enable TZ2 as a one-shot trip source for this ePWM module
Reset type: SYSRSn
8
OSHT1
R/W
0h
Trip-zone 1 (TZ1) Select
0: Disable TZ1 as a one-shot trip source for this ePWM module
1: Enable TZ1 as a one-shot trip source for this ePWM module
Reset type: SYSRSn
1908
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-63. TZSEL Register Field Descriptions (continued)
Bit
7
Field
Type
Reset
Description
DCBEVT2
R/W
0h
Digital Compare Output B Event 2 Select
0: Disable DCBEVT2 as a CBC trip source for this ePWM module
1: Enable DCBEVT2 as a CBC trip source for this ePWM module
Reset type: SYSRSn
6
DCAEVT2
R/W
0h
Digital Compare Output A Event 2 Select
0: Disable DCAEVT2 as a CBC trip source for this ePWM module
1: Enable DCAEVT2 as a CBC trip source for this ePWM module
Reset type: SYSRSn
5
CBC6
R/W
0h
Trip-zone 6 (TZ6) Select
0: Disable TZ6 as a CBC trip source for this ePWM module
1: Enable TZ6 as a CBC trip source for this ePWM module
Reset type: SYSRSn
4
CBC5
R/W
0h
Trip-zone 5 (TZ5) Select
0: Disable TZ5 as a CBC trip source for this ePWM module
1: Enable TZ5 as a CBC trip source for this ePWM module
Reset type: SYSRSn
3
CBC4
R/W
0h
Trip-zone 4 (TZ4) Select
0: Disable TZ4 as a CBC trip source for this ePWM module
1: Enable TZ4 as a CBC trip source for this ePWM module
Reset type: SYSRSn
2
CBC3
R/W
0h
Trip-zone 3 (TZ3) Select
0: Disable TZ3 as a CBC trip source for this ePWM module
1: Enable TZ3 as a CBC trip source for this ePWM module
Reset type: SYSRSn
1
CBC2
R/W
0h
Trip-zone 2 (TZ2) Select
0: Disable TZ2 as a CBC trip source for this ePWM module
1: Enable TZ2 as a CBC trip source for this ePWM module
Reset type: SYSRSn
0
CBC1
R/W
0h
Trip-zone 1 (TZ1) Select
0: Disable TZ1 as a CBC trip source for this ePWM module
1: Enable TZ1 as a CBC trip source for this ePWM module
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1909
ePWM Registers
www.ti.com
14.15.2.43 TZDCSEL Register (Offset = 82h) [reset = 0h]
TZDCSEL is shown in Figure 14-135 and described in Table 14-64.
Return to the Summary Table.
Trip Zone Digital Comparator Select Register
Figure 14-135. TZDCSEL Register
15
14
13
12
11
10
DCBEVT2
R/W-0h
9
8
DCBEVT1
R/W-0h
5
4
DCAEVT2
R/W-0h
3
2
1
DCAEVT1
R/W-0h
0
RESERVED
R-0-0h
7
6
DCBEVT1
R/W-0h
Table 14-64. TZDCSEL Register Field Descriptions
Field
Type
Reset
Description
15-12
Bit
RESERVED
R-0
0h
Reserved
11-9
DCBEVT2
R/W
0h
Digital Compare Output B Event 2 Selection
000: Event disabled
001: DCBH = low, DCBL = don't care
010: DCBH = high, DCBL = don't care
011: DCBL = low, DCBH = don't care
100: DCBL = high, DCBH = don't care
101: DCBL = high, DCBH = low
110: Reserved
111: Reserved
Reset type: SYSRSn
8-6
DCBEVT1
R/W
0h
Digital Compare Output B Event 1 Selection
000: Event disabled
001: DCBH = low, DCBL = don't care
010: DCBH = high, DCBL = don't care
011: DCBL = low, DCBH = don't care
100: DCBL = high, DCBH = don't care
101: DCBL = high, DCBH = low
110: Reserved
111: Reserved
Reset type: SYSRSn
5-3
DCAEVT2
R/W
0h
Digital Compare Output A Event 2 Selection
000: Event disabled
001: DCAH = low, DCAL = don't care
010: DCAH = high, DCAL = don't care
011: DCAL = low, DCAH = don't care
100: DCAL = high, DCAH = don't care
101: DCAL = high, DCAH = low
110: Reserved
111: Reserved
Reset type: SYSRSn
1910
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-64. TZDCSEL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
DCAEVT1
R/W
0h
Digital Compare Output A Event 1 Selection
000: Event disabled
001: DCAH = low, DCAL = don't care
010: DCAH = high, DCAL = don't care
011: DCAL = low, DCAH = don't care
100: DCAL = high, DCAH = don't care
101: DCAL = high, DCAH = low
110: Reserved
111: Reserved
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1911
ePWM Registers
www.ti.com
14.15.2.44 TZCTL Register (Offset = 84h) [reset = 0h]
TZCTL is shown in Figure 14-136 and described in Table 14-65.
Return to the Summary Table.
Trip Zone Control Register
Figure 14-136. TZCTL Register
15
14
13
12
11
RESERVED
R-0-0h
7
6
10
9
DCBEVT2
R/W-0h
5
4
DCAEVT2
R/W-0h
3
DCAEVT1
R/W-0h
8
DCBEVT1
R/W-0h
2
1
TZB
R/W-0h
0
TZA
R/W-0h
Table 14-65. TZCTL Register Field Descriptions
Field
Type
Reset
Description
15-12
Bit
RESERVED
R-0
0h
Reserved
11-10
DCBEVT2
R/W
0h
Digital Compare Output B Event 2 Action On EPWMxB
00: High-impedance (EPWMxB = High-impedance state)
01: Force EPWMxB to a high state.
10: Force EPWMxB to a low state.
11: Do Nothing, trip action is disabled
Reset type: SYSRSn
9-8
DCBEVT1
R/W
0h
Digital Compare Output B Event 1 Action On EPWMxB
00: High-impedance (EPWMxB = High-impedance state)
01: Force EPWMxB to a high state.
10: Force EPWMxB to a low state.
11: Do Nothing, trip action is disabled
Reset type: SYSRSn
7-6
DCAEVT2
R/W
0h
Digital Compare Output A Event 2 Action On EPWMxA
00: High-impedance (EPWMxA = High-impedance state)
01: Force EPWMxA to a high state.
10: Force EPWMxA to a low state.
11: Do Nothing, trip action is disabled
Reset type: SYSRSn
5-4
DCAEVT1
R/W
0h
Digital Compare Output A Event 1 Action On EPWMxA
00: High-impedance (EPWMxA = High-impedance state)
01: Force EPWMxA to a high state.
10: Force EPWMxA to a low state.
11: Do Nothing, trip action is disabled
Reset type: SYSRSn
3-2
TZB
R/W
0h
TZ1 to TZ6, DCAEVT1/2, DCBEVT1/2Trip Action On EPWMxB
When a trip event occurs the following action is taken on output
EPWMxB. Which trip-zone pins can cause an event is defined in the
TZSEL register.
00: High-impedance (EPWMxB = High-impedance state)
01: Force EPWMxB to a high state
10: Force EPWMxB to a low state
11: Do nothing, no action is taken on EPWMxB.
Reset type: SYSRSn
1912
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-65. TZCTL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1-0
TZA
R/W
0h
TZ1 to TZ6, DCAEVT1/2, DCBEVT1/2 Trip Action On EPWMxA
When a trip event occurs the following action is taken on output
EPWMxA. Which trip-zone pins can cause an event is defined in the
TZSEL register.
00: High-impedance (EPWMxA = High-impedance state)
01: Force EPWMxA to a high state
10: Force EPWMxA to a low state
11: Do nothing, no action is taken on EPWMxA.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1913
ePWM Registers
www.ti.com
14.15.2.45 TZCTL2 Register (Offset = 85h) [reset = 0h]
TZCTL2 is shown in Figure 14-137 and described in Table 14-66.
Return to the Summary Table.
Additional Trip Zone Control Register
Figure 14-137. TZCTL2 Register
15
ETZE
R/W-0h
7
14
13
RESERVED
R-0-0h
12
11
10
TZBD
R/W-0h
9
8
TZBU
R/W-0h
6
5
4
TZAD
R/W-0h
3
2
1
TZAU
R/W-0h
0
TZBU
R/W-0h
Table 14-66. TZCTL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
ETZE
R/W
0h
TZCTL2 Enable
0: Use trip action from TZCTL (legacy EPWM compatibility)
1: Use trip action defined in TZCTL2, TZCTLDCA and TZCTLDCB.
Settings in TZCTL are ignored
Reset type: SYSRSn
14-12
RESERVED
R-0
0h
Reserved
11-9
TZBD
R/W
0h
TZ1 to TZ6, DCAEVT1/2, DCBEVT1/2 Trip Action On EPWMxB
while Count direction is DOWN
000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn
8-6
TZBU
R/W
0h
TZ1 to TZ6, DCAEVT1/2, DCBEVT1/2 Trip Action On EPWMxB
while Count direction is UP
000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn
1914
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-66. TZCTL2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-3
TZAD
R/W
0h
TZ1 to TZ6, DCAEVT1/2, DCBEVT1/2 Trip Action On EPWMxA
while Count direction is DOWN
000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn
2-0
TZAU
R/W
0h
TZ1 to TZ6, DCAEVT1/2, DCBEVT1/2 Trip Action On EPWMxA
while Count direction is UP
000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1915
ePWM Registers
www.ti.com
14.15.2.46 TZCTLDCA Register (Offset = 86h) [reset = 0h]
TZCTLDCA is shown in Figure 14-138 and described in Table 14-67.
Return to the Summary Table.
Trip Zone Control Register Digital Compare A
Figure 14-138. TZCTLDCA Register
15
14
13
12
11
10
DCAEVT2D
R/W-0h
9
8
DCAEVT2U
R/W-0h
5
4
DCAEVT1D
R/W-0h
3
2
1
DCAEVT1U
R/W-0h
0
RESERVED
R-0-0h
7
6
DCAEVT2U
R/W-0h
Table 14-67. TZCTLDCA Register Field Descriptions
Field
Type
Reset
Description
15-12
Bit
RESERVED
R-0
0h
Reserved
11-9
DCAEVT2D
R/W
0h
Digital Compare Output A Event 2 Action On EPWMxA while Count
direction is DOWN
000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn
8-6
DCAEVT2U
R/W
0h
Digital Compare Output A Event 2 Action On EPWMxA while Count
direction is UP
000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn
5-3
DCAEVT1D
R/W
0h
Digital Compare Output A Event 1 Action On EPWMxA while Count
direction is DOWN
000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn
1916
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-67. TZCTLDCA Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
DCAEVT1U
R/W
0h
Digital Compare Output A Event 1 Action On EPWMxA while Count
direction is UP
000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1917
ePWM Registers
www.ti.com
14.15.2.47 TZCTLDCB Register (Offset = 87h) [reset = 0h]
TZCTLDCB is shown in Figure 14-139 and described in Table 14-68.
Return to the Summary Table.
Trip Zone Control Register Digital Compare B
Figure 14-139. TZCTLDCB Register
15
14
13
12
11
10
DCBEVT2D
R/W-0h
9
8
DCBEVT2U
R/W-0h
5
4
DCBEVT1D
R/W-0h
3
2
1
DCBEVT1U
R/W-0h
0
RESERVED
R-0-0h
7
6
DCBEVT2U
R/W-0h
Table 14-68. TZCTLDCB Register Field Descriptions
Field
Type
Reset
Description
15-12
Bit
RESERVED
R-0
0h
Reserved
11-9
DCBEVT2D
R/W
0h
Digital Compare Output A Event 2 Action On EPWMxB while Count
direction is DOWN
000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn
8-6
DCBEVT2U
R/W
0h
Digital Compare Output A Event 2 Action On EPWMxB while Count
direction is UP
000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn
5-3
DCBEVT1D
R/W
0h
Digital Compare Output A Event 1 Action On EPWMxB while Count
direction is DOWN
000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn
1918
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-68. TZCTLDCB Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
DCBEVT1U
R/W
0h
Digital Compare Output A Event 1 Action On EPWMxB while Count
direction is UP
000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1919
ePWM Registers
www.ti.com
14.15.2.48 TZEINT Register (Offset = 8Dh) [reset = 0h]
TZEINT is shown in Figure 14-140 and described in Table 14-69.
Return to the Summary Table.
Trip Zone Enable Interrupt Register
Figure 14-140. TZEINT Register
15
14
13
12
11
10
9
8
3
DCAEVT1
R/W-0h
2
OST
R/W-0h
1
CBC
R/W-0h
0
RESERVED
R-0-0h
RESERVED
R-0-0h
7
RESERVED
R-0-0h
6
DCBEVT2
R/W-0h
5
DCBEVT1
R/W-0h
4
DCAEVT2
R/W-0h
Table 14-69. TZEINT Register Field Descriptions
Bit
15-7
6
Field
Type
Reset
Description
RESERVED
R-0
0h
Reserved
DCBEVT2
R/W
0h
Digital Compare Output B Event 2 Interrupt Enable
0: Disabled
1: Enabled
Reset type: SYSRSn
5
DCBEVT1
R/W
0h
Digital Compare Output B Event 1 Interrupt Enable
0: Disabled
1: Enabled
Reset type: SYSRSn
4
DCAEVT2
R/W
0h
Digital Compare Output A Event 2 Interrupt Enable
0: Disabled
1: Enabled
Reset type: SYSRSn
3
DCAEVT1
R/W
0h
Digital Compare Output A Event 1 Interrupt Enable
0: Disabled
1: Enabled
Reset type: SYSRSn
2
OST
R/W
0h
Trip-zone One-Shot Interrupt Enable
0: Disable one-shot interrupt generation
1: Enable Interrupt generation
a one-shot trip event will cause a EPWMx_TZINT PIE interrupt.
Reset type: SYSRSn
1
CBC
R/W
0h
Trip-zone Cycle-by-Cycle Interrupt Enable
0: Disable cycle-by-cycle interrupt generation.
1: Enable interrupt generation
a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE
interrupt.
Reset type: SYSRSn
0
1920
RESERVED
R-0
Enhanced Pulse Width Modulator (ePWM)
0h
Reserved
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.49 TZFLG Register (Offset = 93h) [reset = 0h]
TZFLG is shown in Figure 14-141 and described in Table 14-70.
Return to the Summary Table.
Trip Zone Flag Register
Figure 14-141. TZFLG Register
15
14
13
12
11
10
9
8
3
DCAEVT1
R-0h
2
OST
R-0h
1
CBC
R-0h
0
INT
R-0h
RESERVED
R-0-0h
7
RESERVED
R-0-0h
6
DCBEVT2
R-0h
5
DCBEVT1
R-0h
4
DCAEVT2
R-0h
Table 14-70. TZFLG Register Field Descriptions
Bit
15-7
6
Field
Type
Reset
Description
RESERVED
R-0
0h
Reserved
DCBEVT2
R
0h
Latched Status Flag for Digital Compare Output B Event 2
0: Indicates no trip event has occurred on DCBEVT2
1: Indicates a trip event has occurred for the event defined for
DCBEVT2
Reset type: SYSRSn
5
DCBEVT1
R
0h
Latched Status Flag for Digital Compare Output B Event 1
0: Indicates no trip event has occurred on DCBEVT1
1: Indicates a trip event has occurred for the event defined for
DCBEVT1
Reset type: SYSRSn
4
DCAEVT2
R
0h
Latched Status Flag for Digital Compare Output A Event 2
0: Indicates no trip event has occurred on DCAEVT2
1: Indicates a trip event has occurred for the event defined for
DCAEVT2
Reset type: SYSRSn
3
DCAEVT1
R
0h
Latched Status Flag for Digital Compare Output A Event 1
0: Indicates no trip event has occurred on DCAEVT1
1: Indicates a trip event has occurred for the event defined for
DCAEVT1
Reset type: SYSRSn
2
OST
R
0h
Latched Status Flag for A One-Shot Trip Event
0: No one-shot trip event has occurred.
1: Indicates a trip event has occurred on a pin selected as a oneshot trip source.
This bit is cleared by writing the appropriate value to the TZCLR
register.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1921
ePWM Registers
www.ti.com
Table 14-70. TZFLG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1
CBC
R
0h
Latched Status Flag for Cycle-By-Cycle Trip Event
0: No cycle-by-cycle trip event has occurred.
1: Indicates a trip event has occurred on a signal selected as a
cycle-by-cycle trip source. The
TZFLG[CBC] bit will remain set until it is manually cleared by the
user. If the cycle-by-cycle trip event is still present when the CBC bit
is cleared, then CBC will be immediately set again. The specified
condition on the signal is automatically cleared when the ePWM
time-base counter reaches zero (TBCTR = 0x00) if the trip condition
is no longer present. The condition on the signal is only cleared
when the TBCTR = 0x00 no matter where in the cycle the CBC flag
is cleared.
This bit is cleared by writing the appropriate value to the TZCLR
register.
Reset type: SYSRSn
0
INT
R
0h
Latched Trip Interrupt Status Flag
0: Indicates no interrupt has been generated.
1: Indicates an EPWMx_TZINT PIE interrupt was generated because
of a trip condition.
No further EPWMx_TZINT PIE interrupts will be generated until this
flag is cleared. If the interrupt flag is cleared when either CBC or
OST is set, then another interrupt pulse will be generated. Clearing
all flag bits will prevent further interrupts. This bit is cleared by writing
the appropriate value to the TZCLR register.
Reset type: SYSRSn
1922
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.50 TZCBCFLG Register (Offset = 94h) [reset = 0h]
TZCBCFLG is shown in Figure 14-142 and described in Table 14-71.
Return to the Summary Table.
Trip Zone CBC Flag Register
Figure 14-142. TZCBCFLG Register
15
14
13
12
11
10
9
8
3
CBC4
R-0h
2
CBC3
R-0h
1
CBC2
R-0h
0
CBC1
R-0h
RESERVED
R-0-0h
7
DCBEVT2
R-0h
6
DCAEVT2
R-0h
5
CBC6
R-0h
4
CBC5
R-0h
Table 14-71. TZCBCFLG Register Field Descriptions
Bit
15-8
7
Field
Type
Reset
Description
RESERVED
R-0
0h
Reserved
DCBEVT2
R
0h
Latched Status Flag for Digital Compare B Output Event 2 Trip Latch
0: Reading a 0 indicates that no trip has occurred on DCBEVT2.
1: Reading a 1 indicates a trip has occured on the DCBEVT2
selected event.
Reset type: SYSRSn
6
DCAEVT2
R
0h
Latched Status Flag for Digital Compare A Output Event 2 Trip Latch
0: Reading a 0 indicates that no trip has occurred on DCAEVT2.
1: Reading a 1 indicates a trip has occured on the DCAEVT2
selected event.
Reset type: SYSRSn
5
CBC6
R
0h
Latched Status Flag for CBC6 Trip Latch
0: Reading a 0 indicates that no trip has occurred on CBC6.
1: Reading a 1 indicates a trip has occured on the CBC6 selected
event.
Reset type: SYSRSn
4
CBC5
R
0h
Latched Status Flag for CBC5 Trip Latch
0: Reading a 0 indicates that no trip has occurred on CBC5.
1: Reading a 1 indicates a trip has occured on the CBC5 selected
event.
Reset type: SYSRSn
3
CBC4
R
0h
Latched Status Flag for CBC4 Trip Latch
0: Reading a 0 indicates that no trip has occurred on CBC4.
1: Reading a 1 indicates a trip has occured on the CBC4 selected
event.
Reset type: SYSRSn
2
CBC3
R
0h
Latched Status Flag for CBC3 Trip Latch
0: Reading a 0 indicates that no trip has occurred on CBC3.
1: Reading a 1 indicates a trip has occured on the CBC3 selected
event.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1923
ePWM Registers
www.ti.com
Table 14-71. TZCBCFLG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1
CBC2
R
0h
Latched Status Flag for CBC2 Trip Latch
0: Reading a 0 indicates that no trip has occurred on CBC2.
1: Reading a 1 indicates a trip has occured on the CBC2 selected
event.
Reset type: SYSRSn
0
CBC1
R
0h
Latched Status Flag for CBC1 Trip Latch
0: Reading a 0 indicates that no trip has occurred on CBC1.
1: Reading a 1 indicates a trip has occured on the CBC1 selected
event.
Reset type: SYSRSn
1924
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.51 TZOSTFLG Register (Offset = 95h) [reset = 0h]
TZOSTFLG is shown in Figure 14-143 and described in Table 14-72.
Return to the Summary Table.
Trip Zone OST Flag Register
Figure 14-143. TZOSTFLG Register
15
14
13
12
11
10
9
8
3
OST4
R-0h
2
OST3
R-0h
1
OST2
R-0h
0
OST1
R-0h
RESERVED
R-0-0h
7
DCBEVT1
R-0h
6
DCAEVT1
R-0h
5
OST6
R-0h
4
OST5
R-0h
Table 14-72. TZOSTFLG Register Field Descriptions
Bit
15-8
7
Field
Type
Reset
Description
RESERVED
R-0
0h
Reserved
DCBEVT1
R
0h
Latched Status Flag for Digital Compare B Output Event 1 Trip Latch
0: Reading a 0 indicates that no trip has occurred on DCBEVT1.
1: Reading a 1 indicates a trip has occured on the DCBEVT1
selected event.
Reset type: SYSRSn
6
DCAEVT1
R
0h
Latched Status Flag for Digital Compare A Output Event 1 Trip Latch
0: Reading a 0 indicates that no trip has occurred on DCAEVT1.
1: Reading a 1 indicates a trip has occured on the DCAEVT1
selected event.
Reset type: SYSRSn
5
OST6
R
0h
Latched Status Flag for OST6 Trip Latch
0: Reading a 0 indicates that no trip has occurred on OST6.
1: Reading a 1 indicates a trip has occured on the OST6 selected
event.
Reset type: SYSRSn
4
OST5
R
0h
Latched Status Flag for OST5 Trip Latch
0: Reading a 0 indicates that no trip has occurred on OST5.
1: Reading a 1 indicates a trip has occured on the OST5 selected
event.
Reset type: SYSRSn
3
OST4
R
0h
Latched Status Flag for OST4 Trip Latch
0: Reading a 0 indicates that no trip has occurred on OST4.
1: Reading a 1 indicates a trip has occured on the OST4 selected
event.
Reset type: SYSRSn
2
OST3
R
0h
Latched Status Flag for OST3 Trip Latch
0: Reading a 0 indicates that no trip has occurred on OST3.
1: Reading a 1 indicates a trip has occured on the OST3 selected
event.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1925
ePWM Registers
www.ti.com
Table 14-72. TZOSTFLG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1
OST2
R
0h
Latched Status Flag for OST2 Trip Latch
0: Reading a 0 indicates that no trip has occurred on OST2.
1: Reading a 1 indicates a trip has occured on the OST2 selected
event.
Reset type: SYSRSn
0
OST1
R
0h
Latched Status Flag for OST1 Trip Latch
0: Reading a 0 indicates that no trip has occurred on OST1.
1: Reading a 1 indicates a trip has occured on the OST1 selected
event.
Reset type: SYSRSn
1926
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.52 TZCLR Register (Offset = 97h) [reset = 0h]
TZCLR is shown in Figure 14-144 and described in Table 14-73.
Return to the Summary Table.
Trip Zone Clear Register
Figure 14-144. TZCLR Register
15
14
13
12
11
CBCPULSE
R/W-0h
7
RESERVED
R-0-0h
6
DCBEVT2
R-0/W1S-0h
10
9
8
2
OST
R-0/W1S-0h
1
CBC
R-0/W1S-0h
0
INT
R-0/W1S-0h
RESERVED
R-0-0h
5
DCBEVT1
R-0/W1S-0h
4
DCAEVT2
R-0/W1S-0h
3
DCAEVT1
R-0/W1S-0h
Table 14-73. TZCLR Register Field Descriptions
Bit
15-14
Field
Type
Reset
Description
CBCPULSE
R/W
0h
Clear Pulse for Cycle-By-Cycle (CBC) Trip Latch
This bit field determines which pulse clears the CBC trip latch.
00: CTR = zero pulse clears CBC trip latch. (Same as legacy
designs.)
01: CTR = PRD pulse clears CBC trip latch.
10: CTR = zero or CTR = PRD pulse clears CBC trip latch.
11: CBC trip latch is not cleared
Reset type: SYSRSn
13-7
6
RESERVED
R-0
0h
Reserved
DCBEVT2
R-0/W1S
0h
Clear Flag for Digital Compare Output B Event 2
0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 clears the DCBEVT2 event trip condition.
Reset type: SYSRSn
5
DCBEVT1
R-0/W1S
0h
Clear Flag for Digital Compare Output B Event 1
0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 clears the DCBEVT1 event trip condition.
Reset type: SYSRSn
4
DCAEVT2
R-0/W1S
0h
Clear Flag for Digital Compare Output A Event 2
0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 clears the DCAEVT2 event trip condition.
Reset type: SYSRSn
3
DCAEVT1
R-0/W1S
0h
Clear Flag for Digital Compare Output A Event 1
0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 clears the DCAEVT1 event trip condition.
Reset type: SYSRSn
2
OST
R-0/W1S
0h
Clear Flag for One-Shot Trip (OST) Latch
0: Has no effect. Always reads back a 0.
1: Clears this Trip (set) condition.
Reset type: SYSRSn
1
CBC
R-0/W1S
0h
Clear Flag for Cycle-By-Cycle (CBC) Trip Latch
0: Has no effect. Always reads back a 0.
1: Clears this Trip (set) condition.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1927
ePWM Registers
www.ti.com
Table 14-73. TZCLR Register Field Descriptions (continued)
Bit
0
Field
Type
Reset
Description
INT
R-0/W1S
0h
Global Interrupt Clear Flag
0: Has no effect. Always reads back a 0.
1: Clears the trip-interrupt flag for this ePWM module (TZFLG[INT]).
NOTE: No further EPWMx_TZINT PIE interrupts will be generated
until the flag is cleared. If the TZFLG[INT] bit is cleared and any of
the other flag bits are set, then another interrupt pulse will be
generated. Clearing all flag bits will prevent further interrupts.
Reset type: SYSRSn
1928
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.53 TZCBCCLR Register (Offset = 98h) [reset = 0h]
TZCBCCLR is shown in Figure 14-145 and described in Table 14-74.
Return to the Summary Table.
Trip Zone CBC Clear Register
Figure 14-145. TZCBCCLR Register
15
14
13
12
11
10
9
8
3
CBC4
R-0/W1S-0h
2
CBC3
R-0/W1S-0h
1
CBC2
R-0/W1S-0h
0
CBC1
R-0/W1S-0h
RESERVED
R-0-0h
7
DCBEVT2
R-0/W1S-0h
6
DCAEVT2
R-0/W1S-0h
5
CBC6
R-0/W1S-0h
4
CBC5
R-0/W1S-0h
Table 14-74. TZCBCCLR Register Field Descriptions
Bit
15-8
7
Field
Type
Reset
Description
RESERVED
R-0
0h
Reserved
DCBEVT2
R-0/W1S
0h
Clear Flag for Digital Compare Output B Event 2 selected for CBC
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit.
Reset type: SYSRSn
6
DCAEVT2
R-0/W1S
0h
Clear Flag for Digital Compare Output A Event 2 selected for CBC
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit.
Reset type: SYSRSn
5
CBC6
R-0/W1S
0h
Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC6] bit.
Reset type: SYSRSn
4
CBC5
R-0/W1S
0h
Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC5] bit.
Reset type: SYSRSn
3
CBC4
R-0/W1S
0h
Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC4] bit.
Reset type: SYSRSn
2
CBC3
R-0/W1S
0h
Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC3] bit.
Reset type: SYSRSn
1
CBC2
R-0/W1S
0h
Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC2] bit.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1929
ePWM Registers
www.ti.com
Table 14-74. TZCBCCLR Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
CBC1
R-0/W1S
0h
Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC1] bit.
Reset type: SYSRSn
1930
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.54 TZOSTCLR Register (Offset = 99h) [reset = 0h]
TZOSTCLR is shown in Figure 14-146 and described in Table 14-75.
Return to the Summary Table.
Trip Zone OST Clear Register
Figure 14-146. TZOSTCLR Register
15
14
13
12
11
10
9
8
3
OST4
R-0/W1S-0h
2
OST3
R-0/W1S-0h
1
OST2
R-0/W1S-0h
0
OST1
R-0/W1S-0h
RESERVED
R-0-0h
7
DCBEVT1
R-0/W1S-0h
6
DCAEVT1
R-0/W1S-0h
5
OST6
R-0/W1S-0h
4
OST5
R-0/W1S-0h
Table 14-75. TZOSTCLR Register Field Descriptions
Bit
15-8
7
Field
Type
Reset
Description
RESERVED
R-0
0h
Reserved
DCBEVT1
R-0/W1S
0h
Clear Flag for Digital Compare Output B Event 1 selected for OST
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit.
Reset type: SYSRSn
6
DCAEVT1
R-0/W1S
0h
Clear Flag for Digital Compare Output A Event 1 selected for OST
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit.
Reset type: SYSRSn
5
OST6
R-0/W1S
0h
Clear Flag for Oneshot (OST6) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST6] bit.
Reset type: SYSRSn
4
OST5
R-0/W1S
0h
Clear Flag for Oneshot (OST5) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST5] bit.
Reset type: SYSRSn
3
OST4
R-0/W1S
0h
Clear Flag for Oneshot (OST4) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST4] bit.
Reset type: SYSRSn
2
OST3
R-0/W1S
0h
Clear Flag for Oneshot (OST3) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST3] bit.
Reset type: SYSRSn
1
OST2
R-0/W1S
0h
Clear Flag for Oneshot (OST2) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST2] bit.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1931
ePWM Registers
www.ti.com
Table 14-75. TZOSTCLR Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
OST1
R-0/W1S
0h
Clear Flag for Oneshot (OST1) Trip Latch
0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST1] bit.
Reset type: SYSRSn
1932
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.55 TZFRC Register (Offset = 9Bh) [reset = 0h]
TZFRC is shown in Figure 14-147 and described in Table 14-76.
Return to the Summary Table.
Trip Zone Force Register
Figure 14-147. TZFRC Register
15
14
13
12
11
10
9
8
3
DCAEVT1
R-0/W1S-0h
2
OST
R-0/W1S-0h
1
CBC
R-0/W1S-0h
0
RESERVED
R-0-0h
RESERVED
R-0-0h
7
RESERVED
R-0-0h
6
DCBEVT2
R-0/W1S-0h
5
DCBEVT1
R-0/W1S-0h
4
DCAEVT2
R-0/W1S-0h
Table 14-76. TZFRC Register Field Descriptions
Bit
15-7
6
Field
Type
Reset
Description
RESERVED
R-0
0h
Reserved
DCBEVT2
R-0/W1S
0h
Force Flag for Digital Compare Output B Event 2
0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 forces the DCBEVT2 event trip condition and sets the
TZFLG[DCBEVT2] bit.
Reset type: SYSRSn
5
DCBEVT1
R-0/W1S
0h
Force Flag for Digital Compare Output B Event 1
0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 forces the DCBEVT1 event trip condition and sets the
TZFLG[DCBEVT1] bit.
Reset type: SYSRSn
4
DCAEVT2
R-0/W1S
0h
Force Flag for Digital Compare Output A Event 2
0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 forces the DCAEVT2 event trip condition and sets the
TZFLG[DCAEVT2] bit.
Reset type: SYSRSn
3
DCAEVT1
R-0/W1S
0h
Force Flag for Digital Compare Output A Event 1
0: Writing 0 has no effect. This bit always reads back 0
1: Writing 1 forces the DCAEVT1 event trip condition and sets the
TZFLG[DCAEVT1] bit.
Reset type: SYSRSn
2
OST
R-0/W1S
0h
Force a One-Shot Trip Event via Software
0: Writing of 0 is ignored. Always reads back a 0.
1: Forces a one-shot trip event and sets the TZFLG[OST] bit.
Reset type: SYSRSn
1
CBC
R-0/W1S
0h
Force a Cycle-by-Cycle Trip Event via Software
0: Writing of 0 is ignored. Always reads back a 0.
1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit.
Reset type: SYSRSn
0
RESERVED
R-0
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
0h
Reserved
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1933
ePWM Registers
www.ti.com
14.15.2.56 ETSEL Register (Offset = A4h) [reset = 0h]
ETSEL is shown in Figure 14-148 and described in Table 14-77.
Return to the Summary Table.
Event Trigger Selection Register
Figure 14-148. ETSEL Register
15
SOCBEN
R/W-0h
14
7
RESERVED
R-0-0h
6
INTSELCMP
R/W-0h
13
SOCBSEL
R/W-0h
12
5
4
SOCBSELCMP SOCASELCMP
R/W-0h
R/W-0h
11
SOCAEN
R/W-0h
10
9
SOCASEL
R/W-0h
8
3
INTEN
R/W-0h
2
1
INTSEL
R/W-0h
0
Table 14-77. ETSEL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SOCBEN
R/W
0h
Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse
0: Disable EPWMxSOCB.
1: Enable EPWMxSOCB pulse.
Reset type: SYSRSn
14-12
SOCBSEL
R/W
0h
EPWMxSOCB Selection Options
These bits determine when a EPWMxSOCB pulse will be generated.
000: Enable DCBEVT1.soc event
001: Enable event time-base counter equal to zero. (TBCTR = 0x00)
010: Enable event time-base counter equal to period (TBCTR =
TBPRD)
011: Enable event time-base counter equal to zero or period
(TBCTR = 0x00 or TBCTR = TBPRD). This mode is useful in updown count mode.
100: Enable event time-base counter equal to CMPA when the timer
is incrementing or CMPC when the timer is incrementing
101: Enable event time-base counter equal to CMPA when the timer
is decrementing or CMPC when the timer is decrementing
110: Enable event: time-base counter equal to CMPB when the timer
is incrementing or CMPD when the timer is incrementing
111: Enable event: time-base counter equal to CMPB when the timer
is decrementing or CMPD when the timer is decrementing (*) Event
selected is determined by SOCBSELCMP bit.
Reset type: SYSRSn
11
SOCAEN
R/W
0h
Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse
0: Disable EPWMxSOCA.
1: Enable EPWMxSOCA pulse.
Reset type: SYSRSn
1934
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-77. ETSEL Register Field Descriptions (continued)
Bit
10-8
Field
Type
Reset
Description
SOCASEL
R/W
0h
EPWMxSOCA Selection Options
These bits determine when a EPWMxSOCA pulse will be generated.
000: Enable DCAEVT1.soc event
001: Enable event time-base counter equal to zero. (TBCTR = 0x00)
010: Enable event time-base counter equal to period (TBCTR =
TBPRD)
011: Enable event time-base counter equal to zero or period
(TBCTR = 0x00 or TBCTR = TBPRD). This mode is useful in updown count mode.
100: Enable event time-base counter equal to CMPA when the timer
is incrementing or CMPC when the timer is incrementing
101: Enable event time-base counter equal to CMPA when the timer
is decrementing or CMPC when the timer is decrementing
110: Enable event: time-base counter equal to CMPB when the timer
is incrementing or CMPD when the timer is incrementing
111: Enable event: time-base counter equal to CMPB when the timer
is decrementing or CMPD when the timer is decrementing (*) Event
selected is determined by SOCASELCMP bit.
Reset type: SYSRSn
7
RESERVED
R-0
0h
Reserved
6
INTSELCMP
R/W
0h
EPWMxINT Compare Register Selection Options
0: Enable event time-base counter equal to CMPA when the timer is
incrementing / Enable event time-base counter equal to CMPA when
the timer is decrementing / Enable event: time-base counter equal to
CMPB when the timer is incrementing / Enable event: time-base
counter equal to CMPB when the timer is decrementing to INTSEL
selection mux.
1: Enable event time-base counter equal to CMPC when the timer is
incrementing / Enable event time-base counter equal to CMPC when
the timer is decrementing / Enable event: time-base counter equal to
CMPD when the timer is incrementing / Enable event: time-base
counter equal to CMPD when the timer is decrementing to INTSEL
selection mux.
Reset type: SYSRSn
5
SOCBSELCMP
R/W
0h
EPWMxSOCB Compare Register Selection Options
0: Enable event time-base counter equal to CMPA when the timer is
incrementing / Enable event time-base counter equal to CMPA when
the timer is decrementing / Enable event: time-base counter equal to
CMPB when the timer is incrementing / Enable event: time-base
counter equal to CMPB when the timer is decrementing to
SOCBSEL selection mux.
1: Enable event time-base counter equal to CMPC when the timer is
incrementing / Enable event time-base counter equal to CMPC when
the timer is decrementing / Enable event: time-base counter equal to
CMPD when the timer is incrementing / Enable event: time-base
counter equal to CMPD when the timer is decrementing to
SOCBSEL selection mux.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1935
ePWM Registers
www.ti.com
Table 14-77. ETSEL Register Field Descriptions (continued)
Bit
4
Field
Type
Reset
Description
SOCASELCMP
R/W
0h
EPWMxSOCA Compare Register Selection Options
0: Enable event time-base counter equal to CMPA when the timer is
incrementing / Enable event time-base counter equal to CMPA when
the timer is decrementing / Enable event: time-base counter equal to
CMPB when the timer is incrementing / Enable event: time-base
counter equal to CMPB when the timer is decrementing to
SOCASEL selection mux.
1: Enable event time-base counter equal to CMPC when the timer is
incrementing / Enable event time-base counter equal to CMPC when
the timer is decrementing / Enable event: time-base counter equal to
CMPD when the timer is incrementing / Enable event: time-base
counter equal to CMPD when the timer is decrementing to
SOCASEL selection mux.
Reset type: SYSRSn
3
INTEN
R/W
0h
Enable ePWM Interrupt (EPWMx_INT) Generation
0: Disable EPWMx_INT generation
1: Enable EPWMx_INT generation
Reset type: SYSRSn
2-0
INTSEL
R/W
0h
ePWM Interrupt (EPWMx_INT) Selection Options
000: Reserved
001: Enable event time-base counter equal to zero. (TBCTR = 0x00)
010: Enable event time-base counter equal to period (TBCTR =
TBPRD)
011: Enable event time-base counter equal to zero or period
(TBCTR = 0x00 or TBCTR = TBPRD). This mode is useful in updown count mode.
100: Enable event time-base counter equal to CMPA when the timer
is incrementing or CMPC when the timer is incrementing
101: Enable event time-base counter equal to CMPA when the timer
is decrementing or CMPC when the timer is decrementing
110: Enable event: time-base counter equal to CMPB when the timer
is incrementing or CMPD when the timer is incrementing
111: Enable event: time-base counter equal to CMPB when the timer
is decrementing or CMPD when the timer is decrementing (*) Event
selected is determined by INTSELCMP bit.
Reset type: SYSRSn
1936
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.57 ETPS Register (Offset = A6h) [reset = 0h]
ETPS is shown in Figure 14-149 and described in Table 14-78.
Return to the Summary Table.
Event Trigger Pre-Scale Register
Figure 14-149. ETPS Register
15
14
13
SOCBCNT
R-0h
7
12
11
SOCBPRD
R/W-0h
6
RESERVED
R-0-0h
5
SOCPSSEL
R/W-0h
4
INTPSSEL
R/W-0h
10
9
SOCACNT
R-0h
3
8
SOCAPRD
R/W-0h
2
INTCNT
R-0h
1
0
INTPRD
R/W-0h
Table 14-78. ETPS Register Field Descriptions
Bit
15-14
Field
Type
Reset
Description
SOCBCNT
R
0h
ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter
Register
These bits indicate how many selected ETSEL[SOCBSEL] events
have occurred:
00: No events have occurred.
01: 1 event has occurred.
10: 2 events have occurred.
11: 3 events have occurred.
Reset type: SYSRSn
13-12
SOCBPRD
R/W
0h
ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period
Select
These bits determine how many selected ETSEL[SOCBSEL] events
need to occur before an EPWMxSOCB pulse is generated. To be
generated, the pulse must be enabled (ETSEL[SOCBEN] = 1). The
SOCB pulse will be generated even if the status flag is set from a
previous start of conversion (ETFLG[SOCB] = 1). Once the SOCB
pulse is generated, the ETPS[SOCBCNT] bits will automatically be
cleared.
00: Disable the SOCB event counter. No EPWMxSOCB pulse will be
generated
01: Generate the EPWMxSOCB pulse on the first event:
ETPS[SOCBCNT] = 0,1
10: Generate the EPWMxSOCB pulse on the second event:
ETPS[SOCBCNT] = 1,0
11: Generate the EPWMxSOCB pulse on the third event:
ETPS[SOCBCNT] = 1,1
Reset type: SYSRSn
11-10
SOCACNT
R
0h
ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter
Register
These bits indicate how many selected ETSEL[SOCASEL] events
have occurred:
00: No events have occurred.
01: 1 event has occurred.
10: 2 events have occurred.
11: 3 events have occurred.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1937
ePWM Registers
www.ti.com
Table 14-78. ETPS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
9-8
SOCAPRD
R/W
0h
ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period
Select
These bits determine how many selected ETSEL[SOCASEL] events
need to occur before an EPWMxSOCA pulse is generated. To be
generated, the pulse must be enabled (ETSEL[SOCAEN] = 1). The
SOCA pulse will be generated even if the status flag is set from a
previous start of conversion (ETFLG[SOCA] = 1). Once the SOCA
pulse is generated, the ETPS[SOCACNT] bits will automatically be
cleared.
00: Disable the SOCA event counter. No EPWMxSOCA pulse will be
generated
01: Generate the EPWMxSOCA pulse on the first event:
ETPS[SOCACNT] = 0,1
10: Generate the EPWMxSOCA pulse on the second event:
ETPS[SOCACNT] = 1,0
11: Generate the EPWMxSOCA pulse on the third event:
ETPS[SOCACNT] = 1,1
Reset type: SYSRSn
7-6
RESERVED
R-0
0h
Reserved
5
SOCPSSEL
R/W
0h
EPWMxSOC A/B Pre-Scale Selection Bits
0: Selects ETPS [SOCACNT/SOCBCNT] and
[SOCAPRD/SOCBPRD] registers to determine frequency of events
(interrupt once every 0-3 events).
1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and
[SOCAPRD2/SOCBPRD2] registers to determine frequency of
events (interrupt once every 0-15 events).
Reset type: SYSRSn
4
INTPSSEL
R/W
0h
EPWMxINTn Pre-Scale Selection Bits
0: Selects ETPS [INTCNT, and INTPRD] registers to determine
frequency of events (interrupt once every 0-3 events).
1: Selects ETINTPS [ INTCNT2, and INTPRD2 ] registers to
determine frequency of events (interrupt once every 0-15 events).
Reset type: SYSRSn
3-2
INTCNT
R
0h
ePWM Interrupt Event (EPWMx_INT) Counter Register
These bits indicate how many selected ETSEL[INTSEL] events have
occurred. These bits are automatically cleared when an interrupt
pulse is generated. If interrupts are disabled, ETSEL[INT] = 0 or the
interrupt flag is set, ETFLG[INT] = 1, the counter will stop counting
events when it reaches the period value ETPS[INTCNT] =
ETPS[INTPRD].
00: No events have occurred.
01: 1 event has occurred.
10: 2 events have occurred.
11: 3 events have occurred.
Reset type: SYSRSn
1938
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-78. ETPS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1-0
INTPRD
R/W
0h
ePWM Interrupt (EPWMx_INT) Period Select
These bits determine how many selected ETSEL[INTSEL] events
need to occur before an interrupt is generated. To be generated, the
interrupt must be enabled (ETSEL[INT] = 1). If the interrupt status
flag is set from a previous interrupt (ETFLG[INT] = 1) then no
interrupt will be generated until the flag is cleared via the
ETCLR[INT] bit. This allows for one interrupt to be pending while
another is still being serviced. Once the interrupt is generated, the
ETPS[INTCNT] bits will automatically be cleared.
Writing a INTPRD value that is the same as the current counter
value will trigger an interrupt if it is enabled and the status flag is
clear.
Writing a INTPRD value that is less than the current counter value
will result in an undefined state. If a counter event occurs at the
same instant as a new zero or non-zero INTPRD value is written, the
counter is incremented.
00: Disable the interrupt event counter. No interrupt will be
generated and ETFRC[INT] is ignored.
01: Generate an interrupt on the first event INTCNT = 01 (first event)
10: Generate interrupt on ETPS[INTCNT] = 1,0 (second event)
11: Generate interrupt on ETPS[INTCNT] = 1,1 (third event)
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1939
ePWM Registers
www.ti.com
14.15.2.58 ETFLG Register (Offset = A8h) [reset = 0h]
ETFLG is shown in Figure 14-150 and described in Table 14-79.
Return to the Summary Table.
Event Trigger Flag Register
Figure 14-150. ETFLG Register
15
14
13
12
11
10
9
8
3
SOCB
R-0h
2
SOCA
R-0h
1
RESERVED
R-0-0h
0
INT
R-0h
RESERVED
R-0-0h
7
6
5
4
RESERVED
R-0-0h
Table 14-79. ETFLG Register Field Descriptions
Bit
15-4
3
Field
Type
Reset
Description
RESERVED
R-0
0h
Reserved
SOCB
R
0h
Latched ePWM ADC Start-of-Conversion A (EPWMxSOCB) Status
Flag
Unlike the ETFLG[INT] flag, the EPWMxSOCB output will continue
to pulse even if the flag bit is set.
0: Indicates no event occurred
1: Indicates that a start of conversion pulse was generated on
EPWMxSOCB. The EPWMxSOCB output will continue to be
generated even if the flag bit is set.
Reset type: SYSRSn
2
SOCA
R
0h
Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status
Flag
Unlike the ETFLG[INT] flag, the EPWMxSOCA output will continue
to pulse even if the flag bit is set.
0: Indicates no event occurred
1: Indicates that a start of conversion pulse was generated on
EPWMxSOCA. The EPWMxSOCA output will continue to be
generated even if the flag bit is set.
Reset type: SYSRSn
1
RESERVED
R-0
0h
Reserved
0
INT
R
0h
Latched ePWM Interrupt (EPWMx_INT) Status Flag
0: Indicates no event occurred
1: Indicates that an ePWMx interrupt (EPWMx_INT) was generated.
No further interrupts will be generated until the flag bit is cleared. Up
to one interrupt can be pending while the ETFLG[INT] bit is still set.
If an interrupt is pending, it will not be generated until after the
ETFLG[INT] bit is cleared.
Reset type: SYSRSn
1940
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.59 ETCLR Register (Offset = AAh) [reset = 0h]
ETCLR is shown in Figure 14-151 and described in Table 14-80.
Return to the Summary Table.
Event Trigger Clear Register
Figure 14-151. ETCLR Register
15
14
13
12
11
10
9
8
3
SOCB
R-0/W1S-0h
2
SOCA
R-0/W1S-0h
1
RESERVED
R-0-0h
0
INT
R-0/W1S-0h
RESERVED
R-0-0h
7
6
5
4
RESERVED
R-0-0h
Table 14-80. ETCLR Register Field Descriptions
Bit
15-4
3
Field
Type
Reset
Description
RESERVED
R-0
0h
Reserved
SOCB
R-0/W1S
0h
ePWM ADC Start-of-Conversion A (EPWMxSOCB) Flag Clear Bit
0: Writing a 0 has no effect. Always reads back a 0
1: Clears the ETFLG[SOCB] flag bit
Reset type: SYSRSn
2
SOCA
R-0/W1S
0h
ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit
0: Writing a 0 has no effect. Always reads back a 0
1: Clears the ETFLG[SOCA] flag bit
Reset type: SYSRSn
1
RESERVED
R-0
0h
Reserved
0
INT
R-0/W1S
0h
ePWM Interrupt (EPWMx_INT) Flag Clear Bit
0: Writing a 0 has no effect. Always reads back a 0
1: Clears the ETFLG[INT] flag bit and enable further interrupts
pulses to be generated
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1941
ePWM Registers
www.ti.com
14.15.2.60 ETFRC Register (Offset = ACh) [reset = 0h]
ETFRC is shown in Figure 14-152 and described in Table 14-81.
Return to the Summary Table.
Event Trigger Force Register
Figure 14-152. ETFRC Register
15
14
13
12
11
10
9
8
3
SOCB
R-0/W1S-0h
2
SOCA
R-0/W1S-0h
1
RESERVED
R-0-0h
0
INT
R-0/W1S-0h
RESERVED
R-0-0h
7
6
5
4
RESERVED
R-0-0h
Table 14-81. ETFRC Register Field Descriptions
Bit
15-4
3
Field
Type
Reset
Description
RESERVED
R-0
0h
Reserved
SOCB
R-0/W1S
0h
SOCB Force Bit
The SOCB pulse will only be generated if the event is enabled in the
ETSEL register. The ETFLG[SOCB] flag bit will be set regardless.
0: Writing 0 to this bit will be ignored. Always reads back a 0.
1: Generates a pulse on EPWMxSOCB and set the SOCBFLG bit.
This bit is used for test purposes.
Reset type: SYSRSn
2
SOCA
R-0/W1S
0h
SOCA Force Bit
The SOCA pulse will only be generated if the event is enabled in the
ETSEL register. The ETFLG[SOCA] flag bit will be set regardless.
0: Writing 0 to this bit will be ignored. Always reads back a 0.
1: Generates a pulse on EPWMxSOCA and set the SOCAFLG bit.
This bit is used for test purposes.
Reset type: SYSRSn
1
RESERVED
R-0
0h
Reserved
0
INT
R-0/W1S
0h
INT Force Bit
The interrupt will only be generated if the event is enabled in the
ETSEL register. The INT flag bit will be set regardless.
0: Writing 0 to this bit will be ignored. Always reads back a 0.
1: Generates an interrupt on EPWMxINT and set the INT flag bit.
This bit is used for test purposes.
Reset type: SYSRSn
1942
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.61 ETINTPS Register (Offset = AEh) [reset = 0h]
ETINTPS is shown in Figure 14-153 and described in Table 14-82.
Return to the Summary Table.
Event-Trigger Interrupt Pre-Scale Register
Figure 14-153. ETINTPS Register
15
14
13
12
11
10
3
2
9
8
1
0
RESERVED
R-0-0h
7
6
5
4
INTCNT2
R-0h
INTPRD2
R/W-0h
Table 14-82. ETINTPS Register Field Descriptions
Field
Type
Reset
Description
15-8
Bit
RESERVED
R-0
0h
Reserved
7-4
INTCNT2
R
0h
EPWMxINT Counter 2
When ETPS[INTPSSEL]=1, these bits indicate how many selected
events have occurred:
0000: No events
0001: 1 event
0010: 2 events
0011: 3 events
0100: 4 events
...
1111: 15 events
Reset type: SYSRSn
3-0
INTPRD2
R/W
0h
EPWMxINT Period 2 Select
When ETPS[INTPSSEL] = 1, these bits select how many selected
events need to occur before an interrupt is generated:
0000: Disable counter
0001: Generate interrupt on INTCNT = 1 (first event)
0010: Generate interrupt on INTCNT = 2 (second event)
0011: Generate interrupt on INTCNT = 3 (third event)
0100: Generate interrupt on INTCNT = 4 (fourth event)
...
1111: Generate interrupt on INTCNT = 15 (fifteenth event)
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1943
ePWM Registers
www.ti.com
14.15.2.62 ETSOCPS Register (Offset = B0h) [reset = 0h]
ETSOCPS is shown in Figure 14-154 and described in Table 14-83.
Return to the Summary Table.
Event-Trigger SOC Pre-Scale Register
Figure 14-154. ETSOCPS Register
15
14
13
12
11
10
SOCBCNT2
R-0h
7
6
9
8
1
0
SOCBPRD2
R/W-0h
5
4
3
2
SOCACNT2
R-0h
SOCAPRD2
R/W-0h
Table 14-83. ETSOCPS Register Field Descriptions
Bit
15-12
Field
Type
Reset
Description
SOCBCNT2
R
0h
EPWMxSOCB Counter 2
When ETPS[SOCPSSEL] = 1, these bits indicate how many selected
events have occurred:
0000: No events
0001: 1 event
0010: 2 events
0011: 3 events
0100: 4 events
...
1111: 15 events
Reset type: SYSRSn
11-8
SOCBPRD2
R/W
0h
EPWMxSOCB Period 2 Select
When ETPS[SOCPSSEL] = 1, these bits select how many selected
event need to occur before an SOCB pulse is generated:
0000: Disable counter
0001: Generate interrupt on SOCBCNT2 = 1 (first event)
0010: Generate interrupt on SOCBCNT2 = 2 (second event)
0011: Generate interrupt on SOCBCNT2 = 3 (third event)
0100: Generate interrupt on SOCBCNT2 = 4 (fourth event)
...
1111: Generate interrupt on SOCBCNT2 = 15 (fifteenth event)
Reset type: SYSRSn
7-4
SOCACNT2
R
0h
EPWMxSOCA Counter 2
When ETPS[SOCPSSEL] = 1, these bits indicate how many selected
events have occurred:
0000: No events
0001: 1 event
0010: 2 events
0011: 3 events
0100: 4 events
...
1111: 15 events
Reset type: SYSRSn
1944
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-83. ETSOCPS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
SOCAPRD2
R/W
0h
EPWMxSOCA Period 2 Select
When ETPS[SOCPSSEL] = 1, these bits select how many selected
event need to occur before an SOCA pulse is generated:
0000: Disable counter
0001: Generate interrupt on SOCACNT2 = 1 (first event)
0010: Generate interrupt on SOCACNT2 = 2 (second event)
0011: Generate interrupt on SOCACNT2 = 3 (third event)
0100: Generate interrupt on SOCACNT2 = 4 (fourth event)
...
1111: Generate interrupt on SOCACNT2 = 15 (fifteenth event)
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1945
ePWM Registers
www.ti.com
14.15.2.63 ETCNTINITCTL Register (Offset = B2h) [reset = 0h]
ETCNTINITCTL is shown in Figure 14-155 and described in Table 14-84.
Return to the Summary Table.
Event-Trigger Counter Initialization Control Register
Figure 14-155. ETCNTINITCTL Register
15
SOCBINITEN
R/W-0h
14
SOCAINITEN
R/W-0h
13
INTINITEN
R/W-0h
12
SOCBINITFRC
R/W-0h
11
SOCAINITFRC
R/W-0h
10
INTINITFRC
R/W-0h
9
7
6
5
4
3
2
1
8
RESERVED
R-0-0h
0
RESERVED
R-0-0h
Table 14-84. ETCNTINITCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SOCBINITEN
R/W
0h
EPWMxSOCB Counter 2 Initialization Enable
0: Has no effect.
1: Enable initialization of EPWMxSOCB counter with contents of
ETCNTINIT[SOCBINIT] on a SYNC event or software force.
Reset type: SYSRSn
14
SOCAINITEN
R/W
0h
EPWMxSOCA Counter 2 Initialization Enable
0: Has no effect.
1: Enable initialization of EPWMxSOCA counter with contents of
ETCNTINIT[SOCAINIT] on a SYNC event or software force.
Reset type: SYSRSn
13
INTINITEN
R/W
0h
EPWMxINT Counter 2 Initialization Enable
0: Has no effect.
1: Enable initialization of EPWMxINT counter 2 with contents of
ETCNTINIT[INTINIT] on a SYNC event or software force.
Reset type: SYSRSn
12
SOCBINITFRC
R/W
0h
EPWMxSOCB Counter 2 Initialization Force
0: Has no effect.
1: This bit forces the ET EPWMxSOCB counter to be initialized with
the contents of ETCNTINIT[SOCBINIT].
Reset type: SYSRSn
11
SOCAINITFRC
R/W
0h
EPWMxSOCA Counter 2 Initialization Force
0: Has no effect.
1: This bit forces the ET EPWMxSOCA counter to be initialized with
the contents of ETCNTINIT[SOCAINIT].
Reset type: SYSRSn
10
INTINITFRC
R/W
0h
EPWMxINT Counter 2 Initialization Force
0: Has no effect.
1: This bit forces the ET EPWMxINT counter to be initialized with the
contents of ETCNTINIT[INTINIT].
Reset type: SYSRSn
9-0
1946
RESERVED
R-0
Enhanced Pulse Width Modulator (ePWM)
0h
Reserved
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.64 ETCNTINIT Register (Offset = B4h) [reset = 0h]
ETCNTINIT is shown in Figure 14-156 and described in Table 14-85.
Return to the Summary Table.
Event-Trigger Counter Initialization Register
Figure 14-156. ETCNTINIT Register
15
14
13
12
11
10
RESERVED
R-0h
7
6
9
8
1
0
SOCBINIT
R/W-0h
5
4
3
2
SOCAINIT
R/W-0h
INTINIT
R/W-0h
Table 14-85. ETCNTINIT Register Field Descriptions
Field
Type
Reset
Description
15-12
Bit
RESERVED
R
0h
Reserved
11-8
SOCBINIT
R/W
0h
EPWMxSOCB Counter 2 Initialization Bits
The ET EPWMxSOCB counter is initialized with the contents of this
register on an ePWM SYNC event or a software force.
Reset type: SYSRSn
7-4
SOCAINIT
R/W
0h
EPWMxSOCA Counter 2 Initialization Bits
The ET EPWMxSOCA counter is initialized with the contents of this
register on an ePWM SYNC event or a software force.
Reset type: SYSRSn
3-0
INTINIT
R/W
0h
EPWMxINT Counter 2 Initialization Bits
The ET EPWMxINT counter is initialized with the contents of this
register on an ePWM SYNC event or a software force.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1947
ePWM Registers
www.ti.com
14.15.2.65 DCTRIPSEL Register (Offset = C0h) [reset = 0h]
DCTRIPSEL is shown in Figure 14-157 and described in Table 14-86.
Return to the Summary Table.
Digital Compare Trip Select Register
Figure 14-157. DCTRIPSEL Register
15
14
13
DCBLCOMPSEL
R/W-0h
12
11
10
9
DCBHCOMPSEL
R/W-0h
8
7
6
5
DCALCOMPSEL
R/W-0h
4
3
2
1
DCAHCOMPSEL
R/W-0h
0
Table 14-86. DCTRIPSEL Register Field Descriptions
Bit
15-12
Field
Type
Reset
Description
DCBLCOMPSEL
R/W
0h
Digital Compare B Low Input Select Bits
0000: TRIPIN1 and (TZ1 input)
0001: TRIPIN2 and (TZ2 input)
0010: TRIPIN3 and (TZ3 input)
0011: TRIPIN4
...
1011: TRIPIN12
1100: Reserved
1101: TRIPIN14
1110: TRIPIN15
1111: Trip combination input (all trip inputs selected by
DCBLTRIPSEL register ORed together)
Reset type: SYSRSn
11-8
DCBHCOMPSEL
R/W
0h
Digital Compare B High Input Select Bits
0000: TRIPIN1 and (TZ1 input)
0001: TRIPIN2 and (TZ2 input)
0010: TRIPIN3 and (TZ3 input)
0011: TRIPIN4
...
1011: TRIPIN12
1100: Reserved
1101: TRIPIN14
1110: TRIPIN15
1111: Trip combination input (all trip inputs selected by
DCBHTRIPSEL register ORed together)
Reset type: SYSRSn
1948
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-86. DCTRIPSEL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
7-4
DCALCOMPSEL
R/W
0h
Digital Compare A Low Input Select Bits
0000: TRIPIN1 and (TZ1 input)
0001: TRIPIN2 and (TZ2 input)
0010: TRIPIN3 and (TZ3 input)
0011: TRIPIN4
...
1011: TRIPIN12
1100: Reserved
1101: TRIPIN14
1110: TRIPIN15
1111: Trip combination input (all trip inputs selected by
DCALTRIPSEL register ORed together)
Reset type: SYSRSn
3-0
DCAHCOMPSEL
R/W
0h
Digital Compare A High Input Select Bits
0000: TRIPIN1 and (TZ1 input)
0001: TRIPIN2 and (TZ2 input)
0010: TRIPIN3 and (TZ3 input)
0011: TRIPIN4
...
1011: TRIPIN12
1100: Reserved
1101: TRIPIN14
1110: TRIPIN15
1111: Trip combination input (all trip inputs selected by
DCAHTRIPSEL register ORed together)
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1949
ePWM Registers
www.ti.com
14.15.2.66 DCACTL Register (Offset = C3h) [reset = 0h]
DCACTL is shown in Figure 14-158 and described in Table 14-87.
Return to the Summary Table.
Digital Compare A Control Register
Figure 14-158. DCACTL Register
15
14
13
12
11
10
RESERVED
R-0-0h
7
6
5
4
3
EVT1SYNCE
2
EVT1SOCE
R/W-0h
R/W-0h
9
EVT2FRCSYN
CSEL
R/W-0h
8
EVT2SRCSEL
1
EVT1FRCSYN
CSEL
R/W-0h
0
EVT1SRCSEL
R/W-0h
R/W-0h
Table 14-87. DCACTL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R
0h
Reserved
14-13
RESERVED
R/W
0h
Reserved
12
RESERVED
R/W
0h
Reserved
11-10
RESERVED
R-0
0h
Reserved
EVT2FRCSYNCSEL
R/W
0h
DCAEVT2 Force Synchronization Signal Select
9
0: Source is passed through asynchronously
1: Source is synchronized with EPWMCLK
Reset type: SYSRSn
8
EVT2SRCSEL
R/W
0h
DCAEVT2 Source Signal Select
0: Source Is DCAEVT2 Signal
1: Source Is DCEVTFILT Signal
Reset type: SYSRSn
7
RESERVED
R
0h
Reserved
6-5
RESERVED
R/W
0h
Reserved
4
RESERVED
R/W
0h
Reserved
3
EVT1SYNCE
R/W
0h
DCAEVT1 SYNC, Enable/Disable
0: SYNC Generation Disabled
1: SYNC Generation Enabled
Reset type: SYSRSn
2
EVT1SOCE
R/W
0h
DCAEVT1 SOC, Enable/Disable
0: SOC Generation Disabled
1: SOC Generation Enabled
Reset type: SYSRSn
1
EVT1FRCSYNCSEL
R/W
0h
DCAEVT1 Force Synchronization Signal Select
0: Source is synchronized with EPWMCLK
1: Source is passed through asynchronously
Reset type: SYSRSn
1950
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-87. DCACTL Register Field Descriptions (continued)
Bit
0
Field
Type
Reset
Description
EVT1SRCSEL
R/W
0h
DCAEVT1 Source Signal Select
0: Source Is DCAEVT1 Signal
1: Source Is DCEVTFILT Signal
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1951
ePWM Registers
www.ti.com
14.15.2.67 DCBCTL Register (Offset = C4h) [reset = 0h]
DCBCTL is shown in Figure 14-159 and described in Table 14-88.
Return to the Summary Table.
Digital Compare B Control Register
Figure 14-159. DCBCTL Register
15
14
13
12
11
10
RESERVED
R-0-0h
7
6
5
4
3
EVT1SYNCE
2
EVT1SOCE
R/W-0h
R/W-0h
9
EVT2FRCSYN
CSEL
R/W-0h
8
EVT2SRCSEL
1
EVT1FRCSYN
CSEL
R/W-0h
0
EVT1SRCSEL
R/W-0h
R/W-0h
Table 14-88. DCBCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R
0h
Reserved
14-13
RESERVED
R/W
0h
Reserved
12
RESERVED
R/W
0h
Reserved
11-10
RESERVED
R-0
0h
Reserved
EVT2FRCSYNCSEL
R/W
0h
DCBEVT2 Force Synchronization Signal Select
9
0: Source is synchronized with EPWMCLK
1: Source is passed through asynchronously
Reset type: SYSRSn
8
EVT2SRCSEL
R/W
0h
DCBEVT2 Source Signal Select
0: Source Is DCBEVT2 Signal
1: Source Is DCEVTFILT Signal
Reset type: SYSRSn
7
RESERVED
R
0h
Reserved
6-5
RESERVED
R/W
0h
Reserved
4
RESERVED
R/W
0h
Reserved
3
EVT1SYNCE
R/W
0h
DCBEVT1 SYNC, Enable/Disable
0: SYNC Generation Disabled
1: SYNC Generation Enabled
Reset type: SYSRSn
2
EVT1SOCE
R/W
0h
DCBEVT1 SOC, Enable/Disable
0: SOC Generation Disabled
1: SOC Generation Enabled
Reset type: SYSRSn
1
EVT1FRCSYNCSEL
R/W
0h
DCBEVT1 Force Synchronization Signal Select
0: Source is synchronized with EPWMCLK
1: Source is passed through asynchronously
Reset type: SYSRSn
1952
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-88. DCBCTL Register Field Descriptions (continued)
Bit
0
Field
Type
Reset
Description
EVT1SRCSEL
R/W
0h
DCBEVT1 Source Signal Select
0: Source Is DCBEVT1 Signal
1: Source Is DCEVTFILT Signal
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1953
ePWM Registers
www.ti.com
14.15.2.68 DCFCTL Register (Offset = C7h) [reset = 0h]
DCFCTL is shown in Figure 14-160 and described in Table 14-89.
Return to the Summary Table.
Digital Compare Filter Control Register
Figure 14-160. DCFCTL Register
15
7
RESERVED
R-0-0h
14
EDGESTATUS
R-0h
13
6
EDGEFILTSEL
R/W-0h
5
12
4
PULSESEL
R/W-0h
11
EDGECOUNT
R/W-0h
10
3
BLANKINV
R/W-0h
2
BLANKE
R/W-0h
9
8
EDGEMODE
R/W-0h
1
0
SRCSEL
R/W-0h
Table 14-89. DCFCTL Register Field Descriptions
Bit
15-13
Field
Type
Reset
Description
EDGESTATUS
R
0h
Edge Status:
These bits reflect the total number of edges currently captured.
When the value matches the EDGECOUNT, the status bits are set
to zero. and a TBCLK wide pulse is generated which can then be
output on the DCEVTFILT signal. The edge counter can be reset by
writing 000 to the EDGECOUNT value:
Reset type: SYSRSn
12-10
EDGECOUNT
R/W
0h
Edge Count: These bits select how many edges to count before
generating a TBCLK wide pulse on the DCEVTFILT signal:
000: no edges, reset current EDGESTATUS bits to 0,0,0
001: 1 edge
010: 2 edges
011: 3 edges
100: 4 edges
101: 5 edges
110: 6 edges
111: 7 edges
Reset type: SYSRSn
9-8
EDGEMODE
R/W
0h
Edge Mode Select:
00: Low To High Edge
01: High To Low Edge
10: Both Edges
11: Reserved
Reset type: SYSRSn
7
RESERVED
R-0
0h
Reserved
6
EDGEFILTSEL
R/W
0h
Edge Filter Select:
0: Edge Filter Not Selected
1: Edge Filter Selected
Reset type: SYSRSn
5-4
PULSESEL
R/W
0h
Pulse Select For Blanking & Capture Alignment
00: Time-base counter equal to period (TBCTR = TBPRD)
01: Time-base counter equal to zero (TBCTR = 0x00)
10: Time-base counter equal to zero (TBCTR = 0x00) or period
(TBCTR = TBPRD)
11: Reserved
Reset type: SYSRSn
1954
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-89. DCFCTL Register Field Descriptions (continued)
Bit
3
Field
Type
Reset
Description
BLANKINV
R/W
0h
Blanking Window Inversion
0: Blanking window not inverted
1: Blanking window inverted
Reset type: SYSRSn
2
BLANKE
R/W
0h
Blanking Window Enable/Disable
0: Blanking window is disabled
1: Blanking window is enabled
Reset type: SYSRSn
1-0
SRCSEL
R/W
0h
Filter Block Signal Source Select
00: Source Is DCAEVT1 Signal
01: Source Is DCAEVT2 Signal
10: Source Is DCBEVT1 Signal
11: Source Is DCBEVT2 Signal
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1955
ePWM Registers
www.ti.com
14.15.2.69 DCCAPCTL Register (Offset = C8h) [reset = 0h]
DCCAPCTL is shown in Figure 14-161 and described in Table 14-90.
Return to the Summary Table.
Digital Compare Capture Control Register
Figure 14-161. DCCAPCTL Register
15
CAPMODE
R/W-0h
14
CAPCLR
R-0/W1S-0h
13
CAPSTS
R-0h
12
11
10
RESERVED
R-0-0h
9
8
7
6
5
4
3
2
1
SHDWMODE
R/W-0h
0
CAPE
R/W-0h
RESERVED
R-0-0h
Table 14-90. DCCAPCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
CAPMODE
R/W
0h
Counter Capture Mode
0: When a DCEVTFILT occurs and the counter capture is enabled,
then the current TBCNT value is captured in the active register.
When the respective trip event occurs, further trip (capture) events
are ignored until the next PRD_eq or CNT_zero event (as selected
by the PULSESEL bit in the DCFCTL register) re-triggers the capture
mechanism.
If active mode is enabled, via SHDWMODE bit in DCCAPCTL
register, CPU reads of this register will return the active register
value.
If shadow mode is enabled, via SHDWMODE bit in DCCAPCTL
register, the active register is copied to the shadow register on the
PRD_eq or CNT_zero event (whichever is selected by PULSESEL
bit in DCFCTL register). CPU reads of this register will return the
shadow register value.
1: When a DCEVTFILT occurs and the counter capture is enabled,
then the current TBCNT value is captured in the active register.
When the respective trip event occurs - it will set the CAPSTS flag
and further trip (capture) events are ignored until this bit is cleared.
CAPSTS can be cleared by writing to CAPCLR bit in DCCAPCTL
register and it re-triggers the capture mechanism.
If active mode is enabled, via SHDWMODE bit in DCCAPCTL
register, CPU reads of this register will return the active register
value.
If shadow mode is enabled, via SHDWMODE bit in DCCAPCTL
register, the active register is copied to the shadow register on the
PRD_eq or CNT_zero event (whichever is selected by PULSESEL
bit in DCFCTL register). CPU reads of this register will return the
shadow register value.
Reset type: SYSRSn
14
CAPCLR
R-0/W1S
0h
DC Capture Latched Status Clear Flag
0: Writing a 0 has no effect.
1: Writing a 1 will clear this CAPSTS (set) condition.
Reset type: SYSRSn
13
CAPSTS
R
0h
Latched Status Flag for Capture Event
0: No DC capture event occurred.
1: A DC capture event has occurred.
Reset type: SYSRSn
12-2
1956
RESERVED
R-0
Enhanced Pulse Width Modulator (ePWM)
0h
Reserved
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-90. DCCAPCTL Register Field Descriptions (continued)
Bit
1
Field
Type
Reset
Description
SHDWMODE
R/W
0h
TBCTR Counter Capture Shadow Select Mode
0: Enable shadow mode. The DCCAP active register is copied to
shadow register on a TBCTR = TBPRD or TBCTR = zero event as
defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP
register will return the shadow register contents.
1: Active Mode. In this mode the shadow register is disabled. CPU
reads from the DCCAP register will always return the active register
contents.
Reset type: SYSRSn
0
CAPE
R/W
0h
TBCTR Counter Capture Enable/Disable
0: Disable the time-base counter capture.
1: Enable the time-base counter capture.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1957
ePWM Registers
www.ti.com
14.15.2.70 DCFOFFSET Register (Offset = C9h) [reset = 0h]
DCFOFFSET is shown in Figure 14-162 and described in Table 14-91.
Return to the Summary Table.
Digital Compare Filter Offset Register
Figure 14-162. DCFOFFSET Register
15
14
13
12
11
10
9
8
3
2
1
0
DCFOFFSET
R/W-0h
7
6
5
4
DCFOFFSET
R/W-0h
Table 14-91. DCFOFFSET Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
DCFOFFSET
R/W
0h
Blanking Window Offset
These 16-bits specify the number of TBCLK cycles from the blanking
window reference to the point when the blanking window is applied.
The blanking window reference is either period or zero as defined by
the DCFCTL[PULSESEL] bit. This offset register is shadowed and
the active register is loaded at the reference point defined by
DCFCTL[PULSESEL]. The offset counter is also initialized and
begins to count down when the active register is loaded. When the
counter expires, the blanking window is applied. If the blanking
window is currently active, then the blanking window counter is
restarted.
Reset type: SYSRSn
1958
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.71 DCFOFFSETCNT Register (Offset = CAh) [reset = 0h]
DCFOFFSETCNT is shown in Figure 14-163 and described in Table 14-92.
Return to the Summary Table.
Digital Compare Filter Offset Counter Register
Figure 14-163. DCFOFFSETCNT Register
15
14
13
12
11
DCFOFFSETCNT
R-0h
10
9
8
7
6
5
4
3
DCFOFFSETCNT
R-0h
2
1
0
Table 14-92. DCFOFFSETCNT Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
DCFOFFSETCNT
R
0h
Blanking Offset Counter
These 16-bits are read only and indicate the current value of the
offset counter. The counter counts down to zero and then stops until
it is re-loaded on the next period or zero event as defined by the
DCFCTL[PULSESEL] bit. The offset counter is not affected by the
free/soft emulation bits. That is, it will always continue to count down
if the device is halted by a emulation stop.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1959
ePWM Registers
www.ti.com
14.15.2.72 DCFWINDOW Register (Offset = CBh) [reset = 0h]
DCFWINDOW is shown in Figure 14-164 and described in Table 14-93.
Return to the Summary Table.
Digital Compare Filter Window Register
Figure 14-164. DCFWINDOW Register
15
14
13
12
11
10
9
8
3
2
1
0
DCFWINDOW
R/W-0h
7
6
5
4
DCFWINDOW
R/W-0h
Table 14-93. DCFWINDOW Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
DCFWINDOW
R/W
0h
Blanking Window Width
00h: No blanking window is generated.
01-FFFFh: Specifies the width of the blanking window in TBCLK
cycles. The blanking window begins when the offset counter expires.
When this occurs, the window counter is loaded and begins to count
down. If the blanking window is currently active and the offset
counter expires, the blanking window counter is not restarted and the
blanking window is cut short prematurely. Care should be taken to
avoid this situation. The blanking window can cross a PWM period
boundary.
Reset type: SYSRSn
1960
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.73 DCFWINDOWCNT Register (Offset = CCh) [reset = 0h]
DCFWINDOWCNT is shown in Figure 14-165 and described in Table 14-94.
Return to the Summary Table.
Digital Compare Filter Window Counter Register
Figure 14-165. DCFWINDOWCNT Register
15
14
13
12
11
DCFWINDOWCNT
R-0h
10
9
8
7
6
5
4
3
DCFWINDOWCNT
R-0h
2
1
0
Table 14-94. DCFWINDOWCNT Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
DCFWINDOWCNT
R
0h
Blanking Window Counter
These 16 bits are read only and indicate the current value of the
window counter. The counter counts down to zero and then stops
until it is re-loaded when the offset counter reaches zero again.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1961
ePWM Registers
www.ti.com
14.15.2.74 DCCAP Register (Offset = CFh) [reset = 0h]
DCCAP is shown in Figure 14-166 and described in Table 14-95.
Return to the Summary Table.
Digital Compare Counter Capture Register
Figure 14-166. DCCAP Register
15
14
13
12
11
10
9
8
3
2
1
0
DCCAP
R-0h
7
6
5
4
DCCAP
R-0h
Table 14-95. DCCAP Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
DCCAP
R
0h
Digital Compare Time-Base Counter Capture
To enable time-base counter capture, set the DCCAPCLT[CAPE] bit
to 1. If enabled, reflects the value of the time-base counter (TBCTR)
on the low to high edge transition of a filtered (DCEVTFLT) event.
Further capture events are ignored until the next period or zero as
selected by the DCFCTL[PULSESEL] bit. Shadowing of DCCAP is
enabled and disabled by the DCCAPCTL[SHDWMODE] bit. By
default this register is shadowed.
- If DCCAPCTL[SHDWMODE] = 0, then the shadow is enabled. In
this mode, the active register is copied to the shadow register on the
TBCTR = TBPRD or TBCTR = zero as defined by the
DCFCTL[PULSESEL] bit. CPU reads of this register will return the
shadow register value.
- If DCCAPCTL[SHDWMODE] = 1, then the shadow register is
disabled. In this mode, CPU reads will return the active register
value. The active and shadow registers share the same memory
map address.
Reset type: SYSRSn
1962
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.75 DCAHTRIPSEL Register (Offset = D2h) [reset = 0h]
DCAHTRIPSEL is shown in Figure 14-167 and described in Table 14-96.
Return to the Summary Table.
Digital Compare AH Trip Select
Figure 14-167. DCAHTRIPSEL Register
15
RESERVED
R-0h
14
TRIPINPUT15
R/W-0h
13
TRIPINPUT14
R/W-0h
12
RESERVED
11
TRIPINPUT12
R/W-0h
10
TRIPINPUT11
R/W-0h
9
TRIPINPUT10
R/W-0h
8
TRIPINPUT9
R/W-0h
7
TRIPINPUT8
R/W-0h
6
TRIPINPUT7
R/W-0h
5
TRIPINPUT6
R/W-0h
4
TRIPINPUT5
R/W-0h
3
TRIPINPUT4
R/W-0h
2
TRIPINPUT3
R/W-0h
1
TRIPINPUT2
R/W-0h
0
TRIPINPUT1
R/W-0h
Table 14-96. DCAHTRIPSEL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R
0h
Reserved
14
TRIPINPUT15
R/W
0h
TRIP Input 15
0: Trip Input 15 not selected as combinational ORed input
1: Trip Input 15 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn
13
TRIPINPUT14
R/W
0h
TRIP Input 14
0: Trip Input 14 not selected as combinational ORed input
1: Trip Input 14 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn
12
RESERVED
R/W
0h
Reserved
11
TRIPINPUT12
R/W
0h
TRIP Input 12
0: Trip Input 12 not selected as combinational ORed input
1: Trip Input 12 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn
10
TRIPINPUT11
R/W
0h
TRIP Input 11
0: Trip Input 11 not selected as combinational ORed input
1: Trip Input 11 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn
9
TRIPINPUT10
R/W
0h
TRIP Input 10
0: Trip Input 10 not selected as combinational ORed input
1: Trip Input 10 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn
8
TRIPINPUT9
R/W
0h
TRIP Input 9
0: Trip Input 9 not selected as combinational ORed input
1: Trip Input 9 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn
7
TRIPINPUT8
R/W
0h
TRIP Input 8
0: Trip Input 8 not selected as combinational ORed input
1: Trip Input 8 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1963
ePWM Registers
www.ti.com
Table 14-96. DCAHTRIPSEL Register Field Descriptions (continued)
Bit
6
Field
Type
Reset
Description
TRIPINPUT7
R/W
0h
TRIP Input 7
0: Trip Input 7 not selected as combinational ORed input
1: Trip Input 7 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn
5
TRIPINPUT6
R/W
0h
TRIP Input 6
0: Trip Input 6 not selected as combinational ORed input
1: Trip Input 6 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn
4
TRIPINPUT5
R/W
0h
TRIP Input 5
0: Trip Input 5 not selected as combinational ORed input
1: Trip Input 5 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn
3
TRIPINPUT4
R/W
0h
TRIP Input 4
0: Trip Input 4 not selected as combinational ORed input
1: Trip Input 4 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn
2
TRIPINPUT3
R/W
0h
TRIP Input 3
0: Trip Input 3 not selected as combinational ORed input
1: Trip Input 3 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn
1
TRIPINPUT2
R/W
0h
TRIP Input 2
0: Trip Input 2 not selected as combinational ORed input
1: Trip Input 2 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn
0
TRIPINPUT1
R/W
0h
TRIP Input 1
0: Trip Input 1 not selected as combinational ORed input
1: Trip Input 1 selected as combinational ORed input to DCAH mux
Reset type: SYSRSn
1964
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.76 DCALTRIPSEL Register (Offset = D3h) [reset = 0h]
DCALTRIPSEL is shown in Figure 14-168 and described in Table 14-97.
Return to the Summary Table.
Digital Compare AL Trip Select
Figure 14-168. DCALTRIPSEL Register
15
RESERVED
R-0h
14
TRIPINPUT15
R/W-0h
13
TRIPINPUT14
R/W-0h
12
RESERVED
11
TRIPINPUT12
R/W-0h
10
TRIPINPUT11
R/W-0h
9
TRIPINPUT10
R/W-0h
8
TRIPINPUT9
R/W-0h
7
TRIPINPUT8
R/W-0h
6
TRIPINPUT7
R/W-0h
5
TRIPINPUT6
R/W-0h
4
TRIPINPUT5
R/W-0h
3
TRIPINPUT4
R/W-0h
2
TRIPINPUT3
R/W-0h
1
TRIPINPUT2
R/W-0h
0
TRIPINPUT1
R/W-0h
Table 14-97. DCALTRIPSEL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R
0h
Reserved
14
TRIPINPUT15
R/W
0h
TRIP Input 15
0: Trip Input 15 not selected as combinational ORed input
1: Trip Input 15 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
13
TRIPINPUT14
R/W
0h
TRIP Input 14
0: Trip Input 14 not selected as combinational ORed input
1: Trip Input 14 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
12
RESERVED
R/W
0h
Reserved
11
TRIPINPUT12
R/W
0h
TRIP Input 12
0: Trip Input 12 not selected as combinational ORed input
1: Trip Input 12 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
10
TRIPINPUT11
R/W
0h
TRIP Input 11
0: Trip Input 11 not selected as combinational ORed input
1: Trip Input 11 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
9
TRIPINPUT10
R/W
0h
TRIP Input 10
0: Trip Input 10 not selected as combinational ORed input
1: Trip Input 10 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
8
TRIPINPUT9
R/W
0h
TRIP Input 9
0: Trip Input 9 not selected as combinational ORed input
1: Trip Input 9 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
7
TRIPINPUT8
R/W
0h
TRIP Input 8
0: Trip Input 8 not selected as combinational ORed input
1: Trip Input 8 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1965
ePWM Registers
www.ti.com
Table 14-97. DCALTRIPSEL Register Field Descriptions (continued)
Bit
6
Field
Type
Reset
Description
TRIPINPUT7
R/W
0h
TRIP Input 7
0: Trip Input 7 not selected as combinational ORed input
1: Trip Input 7 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
5
TRIPINPUT6
R/W
0h
TRIP Input 6
0: Trip Input 6 not selected as combinational ORed input
1: Trip Input 6 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
4
TRIPINPUT5
R/W
0h
TRIP Input 5
0: Trip Input 5 not selected as combinational ORed input
1: Trip Input 5 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
3
TRIPINPUT4
R/W
0h
TRIP Input 4
0: Trip Input 4 not selected as combinational ORed input
1: Trip Input 4 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
2
TRIPINPUT3
R/W
0h
TRIP Input 3
0: Trip Input 3 not selected as combinational ORed input
1: Trip Input 3 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
1
TRIPINPUT2
R/W
0h
TRIP Input 2
0: Trip Input 2 not selected as combinational ORed input
1: Trip Input 2 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
0
TRIPINPUT1
R/W
0h
TRIP Input 1
0: Trip Input 1 not selected as combinational ORed input
1: Trip Input 1 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
1966
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.77 DCBHTRIPSEL Register (Offset = D4h) [reset = 0h]
DCBHTRIPSEL is shown in Figure 14-169 and described in Table 14-98.
Return to the Summary Table.
Digital Compare BH Trip Select
Figure 14-169. DCBHTRIPSEL Register
15
RESERVED
R-0h
14
TRIPINPUT15
R/W-0h
13
TRIPINPUT14
R/W-0h
12
RESERVED
11
TRIPINPUT12
R/W-0h
10
TRIPINPUT11
R/W-0h
9
TRIPINPUT10
R/W-0h
8
TRIPINPUT9
R/W-0h
7
TRIPINPUT8
R/W-0h
6
TRIPINPUT7
R/W-0h
5
TRIPINPUT6
R/W-0h
4
TRIPINPUT5
R/W-0h
3
TRIPINPUT4
R/W-0h
2
TRIPINPUT3
R/W-0h
1
TRIPINPUT2
R/W-0h
0
TRIPINPUT1
R/W-0h
Table 14-98. DCBHTRIPSEL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R
0h
Reserved
14
TRIPINPUT15
R/W
0h
TRIP Input 15
0: Trip Input 15 not selected as combinational ORed input
1: Trip Input 15 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn
13
TRIPINPUT14
R/W
0h
TRIP Input 14
0: Trip Input 14 not selected as combinational ORed input
1: Trip Input 14 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn
12
RESERVED
R/W
0h
Reserved
11
TRIPINPUT12
R/W
0h
TRIP Input 12
0: Trip Input 12 not selected as combinational ORed input
1: Trip Input 12 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn
10
TRIPINPUT11
R/W
0h
TRIP Input 11
0: Trip Input 11 not selected as combinational ORed input
1: Trip Input 11 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn
9
TRIPINPUT10
R/W
0h
TRIP Input 10
0: Trip Input 10 not selected as combinational ORed input
1: Trip Input 10 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn
8
TRIPINPUT9
R/W
0h
TRIP Input 9
0: Trip Input 9 not selected as combinational ORed input
1: Trip Input 9 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn
7
TRIPINPUT8
R/W
0h
TRIP Input 8
0: Trip Input 8 not selected as combinational ORed input
1: Trip Input 8 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1967
ePWM Registers
www.ti.com
Table 14-98. DCBHTRIPSEL Register Field Descriptions (continued)
Bit
6
Field
Type
Reset
Description
TRIPINPUT7
R/W
0h
TRIP Input 7
0: Trip Input 7 not selected as combinational ORed input
1: Trip Input 7 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn
5
TRIPINPUT6
R/W
0h
TRIP Input 6
0: Trip Input 6 not selected as combinational ORed input
1: Trip Input 6 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn
4
TRIPINPUT5
R/W
0h
TRIP Input 5
0: Trip Input 5 not selected as combinational ORed input
1: Trip Input 5 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn
3
TRIPINPUT4
R/W
0h
TRIP Input 4
0: Trip Input 4 not selected as combinational ORed input
1: Trip Input 4 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn
2
TRIPINPUT3
R/W
0h
TRIP Input 3
0: Trip Input 3 not selected as combinational ORed input
1: Trip Input 3 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn
1
TRIPINPUT2
R/W
0h
TRIP Input 2
0: Trip Input 2 not selected as combinational ORed input
1: Trip Input 2 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn
0
TRIPINPUT1
R/W
0h
TRIP Input 1
0: Trip Input 1 not selected as combinational ORed input
1: Trip Input 1 selected as combinational ORed input to DCBH mux
Reset type: SYSRSn
1968
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.78 DCBLTRIPSEL Register (Offset = D5h) [reset = 0h]
DCBLTRIPSEL is shown in Figure 14-170 and described in Table 14-99.
Return to the Summary Table.
Digital Compare BL Trip Select
Figure 14-170. DCBLTRIPSEL Register
15
RESERVED
R-0h
14
TRIPINPUT15
R/W-0h
13
TRIPINPUT14
R/W-0h
12
RESERVED
11
TRIPINPUT12
R/W-0h
10
TRIPINPUT11
R/W-0h
9
TRIPINPUT10
R/W-0h
8
TRIPINPUT9
R/W-0h
7
TRIPINPUT8
R/W-0h
6
TRIPINPUT7
R/W-0h
5
TRIPINPUT6
R/W-0h
4
TRIPINPUT5
R/W-0h
3
TRIPINPUT4
R/W-0h
2
TRIPINPUT3
R/W-0h
1
TRIPINPUT2
R/W-0h
0
TRIPINPUT1
R/W-0h
Table 14-99. DCBLTRIPSEL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R
0h
Reserved
14
TRIPINPUT15
R/W
0h
TRIP Input 15
0: Trip Input 15 not selected as combinational ORed input
1: Trip Input 15 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
13
TRIPINPUT14
R/W
0h
TRIP Input 14
0: Trip Input 14 not selected as combinational ORed input
1: Trip Input 14 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
12
RESERVED
R/W
0h
Reserved
11
TRIPINPUT12
R/W
0h
TRIP Input 12
0: Trip Input 12 not selected as combinational ORed input
1: Trip Input 12 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
10
TRIPINPUT11
R/W
0h
TRIP Input 11
0: Trip Input 11 not selected as combinational ORed input
1: Trip Input 11 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
9
TRIPINPUT10
R/W
0h
TRIP Input 10
0: Trip Input 10 not selected as combinational ORed input
1: Trip Input 10 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
8
TRIPINPUT9
R/W
0h
TRIP Input 9
0: Trip Input 9 not selected as combinational ORed input
1: Trip Input 9 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
7
TRIPINPUT8
R/W
0h
TRIP Input 8
0: Trip Input 8 not selected as combinational ORed input
1: Trip Input 8 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1969
ePWM Registers
www.ti.com
Table 14-99. DCBLTRIPSEL Register Field Descriptions (continued)
Bit
6
Field
Type
Reset
Description
TRIPINPUT7
R/W
0h
TRIP Input 7
0: Trip Input 7 not selected as combinational ORed input
1: Trip Input 7 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
5
TRIPINPUT6
R/W
0h
TRIP Input 6
0: Trip Input 6 not selected as combinational ORed input
1: Trip Input 6 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
4
TRIPINPUT5
R/W
0h
TRIP Input 5
0: Trip Input 5 not selected as combinational ORed input
1: Trip Input 5 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
3
TRIPINPUT4
R/W
0h
TRIP Input 4
0: Trip Input 4 not selected as combinational ORed input
1: Trip Input 4 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
2
TRIPINPUT3
R/W
0h
TRIP Input 3
0: Trip Input 3 not selected as combinational ORed input
1: Trip Input 3 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
1
TRIPINPUT2
R/W
0h
TRIP Input 2
0: Trip Input 2 not selected as combinational ORed input
1: Trip Input 2 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
0
TRIPINPUT1
R/W
0h
TRIP Input 1
0: Trip Input 1 not selected as combinational ORed input
1: Trip Input 1 selected as combinational ORed input to DCAL mux
Reset type: SYSRSn
1970
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.2.79 HWVDELVAL Register (Offset = FDh) [reset = 0h]
HWVDELVAL is shown in Figure 14-171 and described in Table 14-100.
Return to the Summary Table.
Hardware Valley Mode Delay Register
Figure 14-171. HWVDELVAL Register
15
14
13
12
11
10
9
8
3
2
1
0
HWVDELVAL
R-0h
7
6
5
4
HWVDELVAL
R-0h
Table 14-100. HWVDELVAL Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
HWVDELVAL
R
0h
Hardware Valley Delay Value Register
This read only register reflects the hardware delay value calculated
by the equations defined in VCAPCTL[VDELAYDIV]. This reflects
the latest value from the hardware calculations and can change
every time valley capture sequence is triggered and VCAP1 and
VCAP2 values are updated.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1971
ePWM Registers
www.ti.com
14.15.2.80 VCNTVAL Register (Offset = FEh) [reset = 0h]
VCNTVAL is shown in Figure 14-172 and described in Table 14-101.
Return to the Summary Table.
Hardware Valley Counter Register
Figure 14-172. VCNTVAL Register
15
14
13
12
11
10
9
8
3
2
1
0
VCNTVAL
R-0h
7
6
5
4
VCNTVAL
R-0h
Table 14-101. VCNTVAL Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
VCNTVAL
R
0h
Valley Time Base Counter Register
This register reflects the captured VCNT value upon occurrence of
STOPEDGE selected in VCNTCFG register.
Reset type: SYSRSn
1972
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.3 SYNC_SOC_REGS Registers
Table 14-102 lists the SYNC_SOC_REGS registers. All register offset addresses not listed in Table 14102 should be considered as reserved locations and the register contents should not be modified.
Table 14-102. SYNC_SOC_REGS Registers
Offset
Acronym
Register Name
Write Protection
0h
SYNCSELECT
Sync Input and Output Select Register
EALLOW
Section
Go
2h
ADCSOCOUTSELECT
External ADC (Off Chip) SOC Select Register
EALLOW
Go
4h
SYNCSOCLOCK
SYNCSEL and EXTADCSOC Select Lock
register
EALLOW
Go
Complex bit access types are encoded to fit into small table cells. Table 14-103 shows the codes that are
used for access types in this section.
Table 14-103. SYNC_SOC_REGS Access Type Codes
Access Type
Code
Description
R
R
Read
R-0
R
-0
Read
Returns 0s
W
W
Write
WSonce
W
Sonce
Write
Set once
Read Type
Write Type
Reset or Default Value
-n
Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y
When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1973
ePWM Registers
www.ti.com
14.15.3.1 SYNCSELECT Register (Offset = 0h) [reset = 0h]
SYNCSELECT is shown in Figure 14-173 and described in Table 14-104.
Return to the Summary Table.
Sync Input and Output Select Register
Figure 14-173. SYNCSELECT Register
31
23
30
RESERVED
R-0-0h
29
22
21
28
27
26
25
RESERVED
R-0-0h
24
19
18
17
16
12
11
10
ECAP1SYNCIN
9
8
EPWM10SYNC
IN
R/W-0h
4
EPWM7SYNCIN
R/W-0h
3
1
EPWM4SYNCIN
R/W-0h
0
SYNCOUT
R/W-0h
20
RESERVED
R-0-0h
15
RESERVED
14
R-0-0h
13
ECAP4SYNCIN
R/W-0h
7
6
EPWM10SYNCIN
R/W-0h
5
R/W-0h
2
Table 14-104. SYNCSELECT Register Field Descriptions
Field
Type
Reset
Description
31-29
Bit
RESERVED
R-0
0h
Reserved
28-27
SYNCOUT
R/W
0h
Select Syncout Source:
00: EPWM1SYNCOUT selected
01: EPWM4SYNCOUT selected
10: EPPW7SYNCOUT selected
11: EPWM10SYNCOUT selected
Reset type: CPU1.SYSRSn
26-16
RESERVED
R-0
0h
Reserved
15
RESERVED
R-0
0h
Reserved
ECAP4SYNCIN
R/W
0h
Selects Sync Input Source for ECAP4:
14-12
000: EPWM1SYNCOUT selected
001: EPWM4SYNCOUT selected
010: EPPW7SYNCOUT selected
011: EPWM10SYNCOUT selected
100: ECAP1SYNCOUT selected
101: EXTSYNCIN1 selected
110: EXTSYNCIN2 selected
111: Reserved
Notes:
[1] Reserved position defaults to 000 selection
Reset type: CPU1.SYSRSn
1974
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-104. SYNCSELECT Register Field Descriptions (continued)
Bit
11-9
Field
Type
Reset
Description
ECAP1SYNCIN
R/W
0h
Selects Sync Input Source for ECAP1:
000: EPWM1SYNCOUT selected
001: EPWM4SYNCOUT selected
010: EPPW7SYNCOUT selected
011: EPWM10SYNCOUT selected
100: ECAP1SYNCOUT selected (Reserved)
101: EXTSYNCIN1 selected
110: EXTSYNCIN2 selected
111: Reserved
Notes:
[1] Reserved position defaults to 000 selection
Reset type: CPU1.SYSRSn
8-6
EPWM10SYNCIN
R/W
0h
Selects Sync Input Source for EPWM10:
000: EPWM1SYNCOUT selected
001: EPWM4SYNCOUT selected
010: EPPW7SYNCOUT selected
011: EPWM10SYNCOUT selected (Reserved)
100: ECAP1SYNCOUT selected (Reserved)
101: EXTSYNCIN1 selected
110: EXTSYNCIN2 selected
111: Reserved
Notes:
[1] Reserved position defaults to 000 selection
Reset type: CPU1.SYSRSn
5-3
EPWM7SYNCIN
R/W
0h
Selects Sync Input Source for EPWM7:
000: EPWM1SYNCOUT selected
001: EPWM4SYNCOUT selected
010: EPPW7SYNCOUT selected (Reserved)
011: EPWM10SYNCOUT selected (Reserved)
100: ECAP1SYNCOUT selected (Reserved)
101: EXTSYNCIN1 selected
110: EXTSYNCIN2 selected
111: Reserved
Notes:
[1] Reserved position defaults to 000 selection
Reset type: CPU1.SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1975
ePWM Registers
www.ti.com
Table 14-104. SYNCSELECT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
EPWM4SYNCIN
R/W
0h
Selects Sync Input Source for EPWM4:
000: EPWM1SYNCOUT selected
001: EPWM4SYNCOUT selected (Reserved)
010: EPPW7SYNCOUT selected (Reserved)
011: EPWM10SYNCOUT selected (Reserved)
100: ECAP1SYNCOUT selected (Reserved)
101: EXTSYNCIN1 selected
110: EXTSYNCIN2 selected
111: Reserved
Notes:
[1] Reserved position defaults to 000 selection
Reset type: CPU1.SYSRSn
1976
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.3.2 ADCSOCOUTSELECT Register (Offset = 2h) [reset = 0h]
ADCSOCOUTSELECT is shown in Figure 14-174 and described in Table 14-105.
Return to the Summary Table.
The ADCSOCAO and ADCSOCBO signals will be active low for 32 SYSCLK cycles. They can be used to
trigger a conversion on an external ADC.
Figure 14-174. ADCSOCOUTSELECT Register
31
30
29
28
RESERVED
R-0-0h
23
PWM8SOCBE
N
R/W-0h
22
PWM7SOCBE
N
R/W-0h
21
PWM6SOCBE
N
R/W-0h
20
PWM5SOCBE
N
R/W-0h
15
14
13
12
5
PWM6SOCAE
N
R/W-0h
4
PWM5SOCAE
N
R/W-0h
RESERVED
R-0-0h
7
PWM8SOCAE
N
R/W-0h
6
PWM7SOCAE
N
R/W-0h
27
26
25
PWM12SOCBE PWM11SOCBE PWM10SOCBE
N
N
N
R/W-0h
R/W-0h
R/W-0h
24
PWM9SOCBE
N
R/W-0h
19
PWM4SOCBE
N
R/W-0h
17
PWM2SOCBE
N
R/W-0h
16
PWM1SOCBE
N
R/W-0h
11
10
9
PWM12SOCAE PWM11SOCAE PWM10SOCAE
N
N
N
R/W-0h
R/W-0h
R/W-0h
8
PWM9SOCAE
N
R/W-0h
3
PWM4SOCAE
N
R/W-0h
0
PWM1SOCAE
N
R/W-0h
18
PWM3SOCBE
N
R/W-0h
2
PWM3SOCAE
N
R/W-0h
1
PWM2SOCAE
N
R/W-0h
Table 14-105. ADCSOCOUTSELECT Register Field Descriptions
Bit
31-28
27
Field
Type
Reset
Description
RESERVED
R-0
0h
Reserved
PWM12SOCBEN
R/W
0h
ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
26
PWM11SOCBEN
R/W
0h
ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
25
PWM10SOCBEN
R/W
0h
ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
24
PWM9SOCBEN
R/W
0h
ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
23
PWM8SOCBEN
R/W
0h
ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1977
ePWM Registers
www.ti.com
Table 14-105. ADCSOCOUTSELECT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
22
PWM7SOCBEN
R/W
0h
ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
21
PWM6SOCBEN
R/W
0h
ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
20
PWM5SOCBEN
R/W
0h
ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
19
PWM4SOCBEN
R/W
0h
ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
18
PWM3SOCBEN
R/W
0h
ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
17
PWM2SOCBEN
R/W
0h
ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
16
PWM1SOCBEN
R/W
0h
ADCSOCBO source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
15-12
11
RESERVED
R-0
0h
Reserved
PWM12SOCAEN
R/W
0h
ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
10
PWM11SOCAEN
R/W
0h
ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
9
PWM10SOCAEN
R/W
0h
ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
8
PWM9SOCAEN
R/W
0h
ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
1978
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-105. ADCSOCOUTSELECT Register Field Descriptions (continued)
Bit
7
Field
Type
Reset
Description
PWM8SOCAEN
R/W
0h
ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
6
PWM7SOCAEN
R/W
0h
ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
5
PWM6SOCAEN
R/W
0h
ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
4
PWM5SOCAEN
R/W
0h
ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
3
PWM4SOCAEN
R/W
0h
ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
2
PWM3SOCAEN
R/W
0h
ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
1
PWM2SOCAEN
R/W
0h
ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
0
PWM1SOCAEN
R/W
0h
ADCSOCAO source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM)
Copyright © 2014–2019, Texas Instruments Incorporated
1979
ePWM Registers
www.ti.com
14.15.3.3 SYNCSOCLOCK Register (Offset = 4h) [reset = 0h]
SYNCSOCLOCK is shown in Figure 14-175 and described in Table 14-106.
Return to the Summary Table.
SYNCSEL and EXTADCSOC Select Lock register
Figure 14-175. SYNCSOCLOCK Register
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
ADCSOCOUTS
ELECT
R/WSonce-0h
0
SYNCSELECT
RESERVED
R-0-0h
23
22
21
20
RESERVED
R-0-0h
15
14
13
12
RESERVED
R-0-0h
7
6
5
4
RESERVED
R-0-0h
R/WSonce-0h
Table 14-106. SYNCSOCLOCK Register Field Descriptions
Field
Type
Reset
Description
31-16
Bit
RESERVED
R-0
0h
Reserved
15-2
RESERVED
R-0
0h
Reserved
ADCSOCOUTSELECT
R/WSonce
0h
ADCSOCOUTSELECT Register Lock bit:
1
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a
CPU1.SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
0
SYNCSELECT
R/WSonce
0h
SYNCSELECT Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a
CPU1.SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
1980
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
14.15.4 Register to Driverlib Function Mapping
Table 14-107. EPWM Registers to Driverlib Functions
File
Driverlib Function
TBCTL
epwm.c
EPWM_setEmulationMode
epwm.h
EPWM_setCountModeAfterSync
epwm.h
EPWM_setClockPrescaler
epwm.h
EPWM_forceSyncPulse
epwm.h
EPWM_setSyncOutPulseMode
epwm.h
EPWM_setPeriodLoadMode
epwm.h
EPWM_enablePhaseShiftLoad
epwm.h
EPWM_disablePhaseShiftLoad
epwm.h
EPWM_setTimeBaseCounterMode
epwm.h
EPWM_selectPeriodLoadEvent
epwm.h
EPWM_enableOneShotSync
epwm.h
EPWM_disableOneShotSync
epwm.h
EPWM_startOneShotSync
TBCTL2
epwm.h
EPWM_setSyncOutPulseMode
epwm.h
EPWM_selectPeriodLoadEvent
epwm.h
EPWM_enableOneShotSync
epwm.h
EPWM_disableOneShotSync
epwm.h
EPWM_startOneShotSync
TBCTR
epwm.h
EPWM_setTimeBaseCounter
epwm.h
EPWM_getTimeBaseCounterValue
TBSTS
epwm.h
EPWM_getTimeBaseCounterOverflowStatus
epwm.h
EPWM_clearTimeBaseCounterOverflowEvent
epwm.h
EPWM_getSyncStatus
epwm.h
EPWM_clearSyncEvent
epwm.h
EPWM_getTimeBaseCounterDirection
CMPCTL
epwm.h
EPWM_setCounterCompareShadowLoadMode
epwm.h
EPWM_disableCounterCompareShadowLoadMode
epwm.h
EPWM_getCounterCompareShadowStatus
CMPCTL2
epwm.h
EPWM_setCounterCompareShadowLoadMode
epwm.h
EPWM_disableCounterCompareShadowLoadMode
DBCTL
epwm.h
EPWM_setDeadBandOutputSwapMode
epwm.h
EPWM_setDeadBandDelayMode
epwm.h
EPWM_setDeadBandDelayPolarity
epwm.h
EPWM_setRisingEdgeDeadBandDelayInput
epwm.h
EPWM_setFallingEdgeDeadBandDelayInput
epwm.h
EPWM_setDeadBandControlShadowLoadMode
epwm.h
EPWM_disableDeadBandControlShadowLoadMode
epwm.h
EPWM_setRisingEdgeDelayCountShadowLoadMode
epwm.h
EPWM_disableRisingEdgeDelayCountShadowLoadMode
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM) 1981
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-107. EPWM Registers to Driverlib Functions (continued)
File
Driverlib Function
epwm.h
EPWM_setFallingEdgeDelayCountShadowLoadMode
epwm.h
EPWM_disableFallingEdgeDelayCountShadowLoadMode
epwm.h
EPWM_setDeadBandCounterClock
DBCTL2
epwm.h
EPWM_setDeadBandControlShadowLoadMode
epwm.h
EPWM_disableDeadBandControlShadowLoadMode
AQCTL
epwm.h
EPWM_setActionQualifierShadowLoadMode
epwm.h
EPWM_disableActionQualifierShadowLoadMode
epwm.h
EPWM_setActionQualifierAction
epwm.h
EPWM_setActionQualifierActionComplete
epwm.h
EPWM_setAdditionalActionQualifierActionComplete
AQTSRCSEL
epwm.h
EPWM_setActionQualifierT1TriggerSource
epwm.h
EPWM_setActionQualifierT2TriggerSource
PCCTL
epwm.h
EPWM_enableChopper
epwm.h
EPWM_disableChopper
epwm.h
EPWM_setChopperDutyCycle
epwm.h
EPWM_setChopperFreq
epwm.h
EPWM_setChopperFirstPulseWidth
VCAPCTL
epwm.h
EPWM_enableValleyCapture
epwm.h
EPWM_disableValleyCapture
epwm.h
EPWM_startValleyCapture
epwm.h
EPWM_setValleyTriggerSource
epwm.h
EPWM_enableValleyHWDelay
epwm.h
EPWM_disableValleyHWDelay
epwm.h
EPWM_setValleyDelayDivider
VCNTCFG
epwm.h
EPWM_setValleyTriggerEdgeCounts
epwm.h
EPWM_getValleyEdgeStatus
GLDCTL
epwm.h
EPWM_enableGlobalLoad
epwm.h
EPWM_disableGlobalLoad
epwm.h
EPWM_setGlobalLoadTrigger
epwm.h
EPWM_setGlobalLoadEventPrescale
epwm.h
EPWM_getGlobalLoadEventCount
epwm.h
EPWM_disableGlobalLoadOneShotMode
epwm.h
EPWM_enableGlobalLoadOneShotMode
epwm.h
EPWM_setGlobalLoadOneShotLatch
epwm.h
EPWM_forceGlobalLoadOneShotEvent
GLDCFG
epwm.h
EPWM_enableGlobalLoadRegisters
epwm.h
EPWM_disableGlobalLoadRegisters
XLINK
epwm.h
EPWM_setupEPWMLinks
1982Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-107. EPWM Registers to Driverlib Functions (continued)
File
Driverlib Function
AQCTLA
epwm.h
EPWM_setActionQualifierAction
epwm.h
EPWM_setActionQualifierActionComplete
epwm.h
EPWM_setAdditionalActionQualifierActionComplete
AQCTLA2
epwm.h
EPWM_setActionQualifierAction
epwm.h
EPWM_setAdditionalActionQualifierActionComplete
AQCTLB
-
See AQCTLA
AQCTLB2
-
See AQCTLA2
AQSFRC
epwm.h
EPWM_setActionQualifierContSWForceShadowMode
epwm.h
EPWM_setActionQualifierSWAction
epwm.h
EPWM_forceActionQualifierSWAction
AQCSFRC
epwm.h
EPWM_setActionQualifierContSWForceAction
DBRED
epwm.h
EPWM_setRisingEdgeDelayCount
DBFED
epwm.h
EPWM_setFallingEdgeDelayCount
TBPHS
epwm.h
EPWM_setPhaseShift
TBPRD
epwm.h
EPWM_setTimeBasePeriod
epwm.h
EPWM_getTimeBasePeriod
CMPA
epwm.h
EPWM_setCounterCompareValue
epwm.h
EPWM_getCounterCompareValue
CMPB
-
See CMPA
CMPC
epwm.h
EPWM_setCounterCompareShadowLoadMode
epwm.h
EPWM_disableCounterCompareShadowLoadMode
epwm.h
EPWM_getCounterCompareShadowStatus
CMPD
-
See CMPC
GLDCTL2
epwm.h
EPWM_setGlobalLoadOneShotLatch
epwm.h
EPWM_forceGlobalLoadOneShotEvent
SWVDELVAL
epwm.h
EPWM_setValleySWDelayValue
TZSEL
epwm.h
EPWM_enableTripZoneSignals
epwm.h
EPWM_disableTripZoneSignals
TZDCSEL
epwm.h
EPWM_setTripZoneDigitalCompareEventCondition
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM) 1983
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-107. EPWM Registers to Driverlib Functions (continued)
File
Driverlib Function
TZCTL
epwm.h
EPWM_enableTripZoneAdvAction
epwm.h
EPWM_disableTripZoneAdvAction
epwm.h
EPWM_setTripZoneAction
epwm.h
EPWM_setTripZoneAdvAction
epwm.h
EPWM_setTripZoneAdvDigitalCompareActionA
epwm.h
EPWM_setTripZoneAdvDigitalCompareActionB
TZCTL2
epwm.h
EPWM_enableTripZoneAdvAction
epwm.h
EPWM_disableTripZoneAdvAction
epwm.h
EPWM_setTripZoneAdvAction
epwm.h
EPWM_setTripZoneAdvDigitalCompareActionA
epwm.h
EPWM_setTripZoneAdvDigitalCompareActionB
TZCTLDCA
epwm.h
EPWM_setTripZoneAdvDigitalCompareActionA
TZCTLDCB
epwm.h
EPWM_setTripZoneAdvDigitalCompareActionB
TZEINT
epwm.h
EPWM_enableTripZoneInterrupt
epwm.h
EPWM_disableTripZoneInterrupt
TZFLG
epwm.h
EPWM_getTripZoneFlagStatus
TZCBCFLG
epwm.h
EPWM_getCycleByCycleTripZoneFlagStatus
TZOSTFLG
epwm.h
EPWM_getOneShotTripZoneFlagStatus
TZCLR
epwm.h
EPWM_selectCycleByCycleTripZoneClearEvent
epwm.h
EPWM_clearTripZoneFlag
TZCBCCLR
epwm.h
EPWM_clearCycleByCycleTripZoneFlag
TZOSTCLR
epwm.h
EPWM_clearOneShotTripZoneFlag
TZFRC
epwm.h
EPWM_forceTripZoneEvent
ETSEL
epwm.h
EPWM_enableInterrupt
epwm.h
EPWM_disableInterrupt
epwm.h
EPWM_setInterruptSource
epwm.h
EPWM_enableADCTrigger
epwm.h
EPWM_disableADCTrigger
epwm.h
EPWM_setADCTriggerSource
ETPS
epwm.h
EPWM_setInterruptEventCount
epwm.h
EPWM_setADCTriggerEventPrescale
ETFLG
epwm.h
EPWM_getEventTriggerInterruptStatus
1984Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-107. EPWM Registers to Driverlib Functions (continued)
File
epwm.h
Driverlib Function
EPWM_getADCTriggerFlagStatus
ETCLR
epwm.h
EPWM_clearEventTriggerInterruptFlag
epwm.h
EPWM_clearADCTriggerFlag
ETFRC
epwm.h
EPWM_forceEventTriggerInterrupt
epwm.h
EPWM_forceADCTrigger
ETINTPS
epwm.h
EPWM_setInterruptEventCount
epwm.h
EPWM_getInterruptEventCount
ETSOCPS
epwm.h
EPWM_setADCTriggerEventPrescale
epwm.h
EPWM_getADCTriggerEventCount
ETCNTINITCTL
epwm.h
EPWM_enableInterruptEventCountInit
epwm.h
EPWM_disableInterruptEventCountInit
epwm.h
EPWM_forceInterruptEventCountInit
epwm.h
EPWM_enableADCTriggerEventCountInit
epwm.h
EPWM_disableADCTriggerEventCountInit
epwm.h
EPWM_forceADCTriggerEventCountInit
ETCNTINIT
epwm.h
EPWM_enableInterruptEventCountInit
epwm.h
EPWM_disableInterruptEventCountInit
epwm.h
EPWM_forceInterruptEventCountInit
epwm.h
EPWM_setInterruptEventCountInitValue
epwm.h
EPWM_enableADCTriggerEventCountInit
epwm.h
EPWM_disableADCTriggerEventCountInit
epwm.h
EPWM_forceADCTriggerEventCountInit
epwm.h
EPWM_setADCTriggerEventCountInitValue
DCTRIPSEL
epwm.h
EPWM_selectDigitalCompareTripInput
epwm.h
EPWM_enableDigitalCompareTripCombinationInput
DCACTL
epwm.h
EPWM_setDigitalCompareEventSource
epwm.h
EPWM_setDigitalCompareEventSyncMode
epwm.h
EPWM_enableDigitalCompareADCTrigger
epwm.h
EPWM_disableDigitalCompareADCTrigger
epwm.h
EPWM_enableDigitalCompareSyncEvent
epwm.h
EPWM_disableDigitalCompareSyncEvent
DCBCTL
-
See DCACTL
DCFCTL
epwm.h
EPWM_enableDigitalCompareBlankingWindow
epwm.h
EPWM_disableDigitalCompareBlankingWindow
epwm.h
EPWM_enableDigitalCompareWindowInverseMode
epwm.h
EPWM_disableDigitalCompareWindowInverseMode
epwm.h
EPWM_setDigitalCompareBlankingEvent
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM) 1985
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-107. EPWM Registers to Driverlib Functions (continued)
File
Driverlib Function
epwm.h
EPWM_setDigitalCompareFilterInput
epwm.h
EPWM_enableDigitalCompareEdgeFilter
epwm.h
EPWM_disableDigitalCompareEdgeFilter
epwm.h
EPWM_setDigitalCompareEdgeFilterMode
epwm.h
EPWM_setDigitalCompareEdgeFilterEdgeCount
epwm.h
EPWM_getDigitalCompareEdgeFilterEdgeCount
epwm.h
EPWM_getDigitalCompareEdgeFilterEdgeStatus
DCCAPCTL
epwm.h
EPWM_enableDigitalCompareCounterCapture
epwm.h
EPWM_disableDigitalCompareCounterCapture
epwm.h
EPWM_setDigitalCompareCounterShadowMode
epwm.h
EPWM_getDigitalCompareCaptureStatus
DCFOFFSET
epwm.h
EPWM_setDigitalCompareWindowOffset
epwm.h
EPWM_getDigitalCompareBlankingWindowOffsetCount
DCFOFFSETCNT
epwm.h
EPWM_getDigitalCompareBlankingWindowOffsetCount
DCFWINDOW
epwm.h
EPWM_setDigitalCompareWindowLength
epwm.h
EPWM_getDigitalCompareBlankingWindowLengthCount
DCFWINDOWCNT
epwm.h
EPWM_getDigitalCompareBlankingWindowLengthCount
DCCAP
epwm.h
EPWM_enableDigitalCompareCounterCapture
epwm.h
EPWM_disableDigitalCompareCounterCapture
epwm.h
EPWM_setDigitalCompareCounterShadowMode
epwm.h
EPWM_getDigitalCompareCaptureStatus
epwm.h
EPWM_getDigitalCompareCaptureCount
DCAHTRIPSEL
epwm.h
EPWM_enableDigitalCompareTripCombinationInput
epwm.h
EPWM_disableDigitalCompareTripCombinationInput
DCALTRIPSEL
-
See DCAHTRIPSEL
DCBHTRIPSEL
-
See DCAHTRIPSEL
DCBLTRIPSEL
-
See DCAHTRIPSEL
HWVDELVAL
epwm.h
EPWM_getValleyHWDelay
VCNTVAL
epwm.h
EPWM_getValleyCount
Table 14-108. HRPWM Registers to Driverlib Functions
File
Driverlib Function
HRCNFG
hrpwm.h
HRPWM_setMEPEdgeSelect
1986Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-108. HRPWM Registers to Driverlib Functions (continued)
File
Driverlib Function
hrpwm.h
HRPWM_setMEPControlMode
hrpwm.h
HRPWM_setCounterCompareShadowLoadEvent
hrpwm.h
HRPWM_setOutputSwapMode
hrpwm.h
HRPWM_setChannelBOutputPath
hrpwm.h
HRPWM_enableAutoConversion
hrpwm.h
HRPWM_disableAutoConversion
hrpwm.h
HRPWM_setDeadbandMEPEdgeSelect
hrpwm.h
HRPWM_setRisingEdgeDelayLoadMode
hrpwm.h
HRPWM_setFallingEdgeDelayLoadMode
HRMSTEP
hrpwm.h
HRPWM_setMEPStep
HRCNFG2
hrpwm.h
HRPWM_setDeadbandMEPEdgeSelect
hrpwm.h
HRPWM_setRisingEdgeDelayLoadMode
hrpwm.h
HRPWM_setFallingEdgeDelayLoadMode
HRPCTL
hrpwm.h
HRPWM_enablePeriodControl
hrpwm.h
HRPWM_disablePeriodControl
hrpwm.h
HRPWM_enablePhaseShiftLoad
hrpwm.h
HRPWM_disablePhaseShiftLoad
hrpwm.h
HRPWM_setSyncPulseSource
TRREM
hrpwm.h
HRPWM_setTranslatorRemainder
DBREDHR
hrpwm.h
HRPWM_setRisingEdgeDelay
hrpwm.h
HRPWM_setHiResRisingEdgeDelayOnly
DBRED
hrpwm.h
HRPWM_setRisingEdgeDelay
hrpwm.h
HRPWM_setHiResRisingEdgeDelayOnly
DBFEDHR
hrpwm.h
HRPWM_setFallingEdgeDelay
hrpwm.h
HRPWM_setHiResFallingEdgeDelayOnly
DBFED
hrpwm.h
HRPWM_setFallingEdgeDelay
hrpwm.h
HRPWM_setHiResFallingEdgeDelayOnly
TBPHS
hrpwm.h
HRPWM_setPhaseShift
hrpwm.h
HRPWM_setHiResPhaseShiftOnly
TBPRDHR
hrpwm.h
HRPWM_setTimeBasePeriod
hrpwm.h
HRPWM_setHiResTimeBasePeriodOnly
hrpwm.h
HRPWM_getTimeBasePeriod
hrpwm.h
HRPWM_getHiResTimeBasePeriodOnly
TBPRD
hrpwm.h
HRPWM_setTimeBasePeriod
hrpwm.h
HRPWM_setHiResTimeBasePeriodOnly
hrpwm.h
HRPWM_getTimeBasePeriod
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Pulse Width Modulator (ePWM) 1987
Copyright © 2014–2019, Texas Instruments Incorporated
ePWM Registers
www.ti.com
Table 14-108. HRPWM Registers to Driverlib Functions (continued)
File
Driverlib Function
hrpwm.h
HRPWM_getHiResTimeBasePeriodOnly
CMPA
hrpwm.h
HRPWM_setCounterCompareValue
hrpwm.h
HRPWM_setHiResCounterCompareValueOnly
hrpwm.h
HRPWM_getCounterCompareValue
hrpwm.h
HRPWM_getHiResCounterCompareValueOnly
CMPB
1988
hrpwm.h
HRPWM_setCounterCompareValue
hrpwm.h
HRPWM_setHiResCounterCompareValueOnly
hrpwm.h
HRPWM_getCounterCompareValue
hrpwm.h
HRPWM_getHiResCounterCompareValueOnly
Enhanced Pulse Width Modulator (ePWM)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Chapter 15
SPRUHM9F – October 2014 – Revised September 2019
Enhanced Capture (eCAP)
This chapter describes the enhanced capture (eCAP) module, which is used in systems where accurate
timing of external events is important.
Topic
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
...........................................................................................................................
Introduction ...................................................................................................
Features ........................................................................................................
Description ....................................................................................................
Configuring Device Pins for the eCAP ...............................................................
Capture and APWM Operating Mode .................................................................
Capture Mode Description ...............................................................................
Application of the eCAP Module ......................................................................
Application of the APWM Mode ........................................................................
eCAP Registers ..............................................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Page
1990
1990
1990
1990
1992
1993
2002
2006
2007
Enhanced Capture (eCAP)
1989
Introduction
www.ti.com
15.1 Introduction
This eCAP module is a Type-0 eCAP. See the TMS320C28xx, 28xxx DSP Peripheral Reference Guide for
a list of all devices with an eCAP module of the same type, to determine the differences between the
types, and for a list of device-specific differences within a type.
15.2 Features
Features for eCAP include:
• Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module described in this guide includes the following features:
• 4-event time-stamp registers (each 32 bits)
• Edge polarity selection for up to four sequenced time-stamp capture events
• Interrupt on either of the four events
• Single-shot capture of up to four event time-stamps
• Continuous mode capture of time stamps in a four-deep circular buffer
• Absolute time-stamp capture
• Difference (Delta) mode time-stamp capture
• All above resources are dedicated to a single input pin
• When not used in capture mode, the eCAP module can be configured as a single-channel PWM output
15.3 Description
The eCAP module represents one complete capture channel that can be instantiated multiple times,
depending on the target device. In the context of this guide, one eCAP channel has the following
independent key resources:
• Dedicated input capture pin
• Output X-BAR is used to configure output in APWM mode
• 32-bit time base (counter)
• 4 x 32-bit time-stamp capture registers (CAP1-CAP4)
• Four-stage sequencer (modulo4 counter) that is synchronized to external events, eCAP pin
rising/falling edges.
• Independent edge polarity (rising/falling edge) selection for all four events
• Input capture signal prescaling (from 2-62 or bypass)
• One-shot compare register (two bits) to freeze captures after 1-4 time-stamp events
• Control for continuous time-stamp captures using a four-deep circular buffer (CAP1-CAP4) scheme
• Interrupt capabilities on any of the four capture events
15.4 Configuring Device Pins for the eCAP
To connect the device input pins to the module, the Input X-BAR must be used. Any GPIO on the device
can be configured as an input. The GPIO input qualification can be set to synchronous or asynchronous
mode by setting the GPxQSELn register bits. Using synchronized inputs can help with noise immunity but
will affect the eCAP's accuracy by ±2 cycles. The internal pull-ups can be configured in the GPyPUD
register. Since the GPIO mode is used, the GPyINV register can invert the signals.
1990
Enhanced Capture (eCAP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Configuring Device Pins for the eCAP
www.ti.com
The Output X-BAR must be used to connect output signals to the OUTPUTXBARx output locations. The
GPIO mux must then be configured to connect the OUTPUTXBARx lines to any of several IO pins with the
GPIO mux. To avoid glitches on the pins, the GPyGMUX bits must be configured first (while keeping the
corresponding GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the
desired value.
See the GPIO Chapter for more details on GPIO mux, GPIO settings, and XBAR configuration.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
1991
Capture and APWM Operating Mode
www.ti.com
15.5 Capture and APWM Operating Mode
You can use the eCAP module resources to implement a single-channel PWM generator (with 32-bit
capabilities) when it is not being used for input captures. The counter operates in count-up mode,
providing a time-base for asymmetrical pulse width modulation (PWM) waveforms. The CAP1 and CAP2
registers become the active period and compare registers, respectively, while CAP3 and CAP4 registers
become the period and capture shadow registers, respectively. Figure 15-1 is a high-level view of both the
capture and auxiliary pulse-width modulator (APWM) modes of operation.
Figure 15-1. Capture and APWM Modes of Operation
A
A single pin is shared between CAP and APWM functions. In capture mode, it is an input; in APWM mode, it is an
output.
B
In APWM mode, writing any value to CAP1/CAP2 active registers also writes the same value to the corresponding
shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow registers CAP3/CAP4 invokes
the shadow mode.
Figure 15-2 further descries the output of the eCAP in APWM mode based on the CMP and PRD values.
1992
Enhanced Capture (eCAP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Capture Mode Description
www.ti.com
Figure 15-2. Counter Compare and PRD Effects on the eCAP Output in APWM Mode
32
PRD [0-31]
CTR = PRD
Digital
Comparator
32
POLSEL
CTR [0-31]
set
ECAPxOUT
Q
CTR = CMP
clear
32
CMP [0-31]
Digital
Comparator
CTR [0-31]
set
FFFFFFFF
Period
Register
PRD [0-31]
clear
Compare
Register
CMP [0-31]
set
clear
0000000C
ECAPOUT
Off−time
On
time
Period
15.6 Capture Mode Description
Figure 15-3 shows the various components that implement the capture function.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
1993
Capture Mode Description
www.ti.com
Figure 15-3. eCAP Block Diagram
ECCTL2 [ SYNCI_EN, SYNCOSEL, SWSYNC]
ECCTL2[CAP/APWM]
SYNC
CTRPHS
(phase register−32 bit)
SYNCIn
APWM mode
CTR_OVF
OVF
TSCTR
(counter−32 bit)
SYNCOut
RST
CTR [0−31]
Delta−mode
PRD [0−31]
PWM
compare
logic
CMP [0−31]
32
CTR=PRD
CTR [0−31]
CTR=CMP
32
PRD [0−31]
ECCTL1 [ CAPLDEN, CTRRSTx]
LD1
CAP1
(APRD active)
APRD
shadow
32
CMP [0−31]
CAP2
(ACMP active)
LD
32
32
Polarity
select
LD
32
32
32
MODE SELECT
ECAPx
32
LD2
Polarity
select
Event
qualifier
ACMP
shadow
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
LD
Event
Prescale
Polarity
select
LD3
LD4
ECCTL1[EVTPS]
Polarity
select
4
Capture events
Edge Polarity Select
ECCTL1[CAPxPOL]
4
CEVT[1:4]
to PIE
Interrupt
Trigger
and
Flag
control
CTR_OVF
Continuous /
Oneshot
Capture Control
CTR=PRD
CTR=CMP
ECCTL2 [ RE−ARM, CONT/ONESHT, STOP_WRAP]
Registers: ECEINT, ECFLG, ECCLR, ECFRC
15.6.1 Event Prescaler
•
1994
An input capture signal (pulse train) can be prescaled by N = 2-62 (in multiples of 2) or can bypass the
prescaler.
This is useful when very high frequency signals are used as inputs. Figure 15-4 shows a functional
diagram and Figure 15-5 shows the operation of the prescale function.
Enhanced Capture (eCAP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Capture Mode Description
www.ti.com
Figure 15-4. Event Prescale Control
Event prescaler
0
PSout
1
By−pass
ECAPx pin
(from GPIO)
/n
5
ECCTL1[EVTPS]
prescaler [5 bits]
(counter)
A
When a prescale value of 1 is chosen ( ECCTL1[13:9] = 0,0,0,0,0 ), the input capture signal bypasses the prescale
logic completely.
Figure 15-5. Prescale Function Waveforms
ECAPx
PSout
div 2
PSout
div 4
PSout
div 6
PSout
div 8
PSout
div 10
15.6.2 Edge Polarity Select and Qualifier
Functionality and features include:
• Four independent edge polarity (rising edge/falling edge) selection muxes are used, one for each
capture event.
• Each edge (up to 4) is event qualified by the Modulo4 sequencer.
• The edge event is gated to its respective CAPx register by the Mod4 counter. The CAPx register is
loaded on the falling edge.
15.6.3 Continuous/One-Shot Control
Operation of eCAP in Continuous/One-Shot mode:
• The Mod4 (2-bit) counter is incremented via edge qualified events (CEVT1-CEVT4).
• The Mod4 counter continues counting (0->1->2->3->0) and wraps around unless stopped.
• A 2-bit stop register is used to compare the Mod4 counter output, and when equal, stops the Mod4
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
1995
Capture Mode Description
www.ti.com
counter and inhibits further loads of the CAP1-CAP4 registers. This occurs during one-shot operation.
The continuous/one-shot block controls the start, stop and reset (zero) functions of the Mod4 counter, via
a mono-shot type of action that can be triggered by the stop-value comparator and re-armed via software
control.
Once armed, the eCAP module waits for 1-4 (defined by stop-value) capture events before freezing both
the Mod4 counter and contents of CAP1-4 registers (time stamps).
Re-arming prepares the eCAP module for another capture sequence. Also, re-arming clears (to zero) the
Mod4 counter and permits loading of CAP1-4 registers again, providing the CAPLDEN bit is set.
In continuous mode, the Mod4 counter continues to run (0->1->2->3->0, the one-shot action is ignored,
and capture values continue to be written to CAP1-4 in a circular buffer sequence.
Figure 15-6. Details of the Continuous/One-shot Block
0 1 2 3
2:4 MUX
2
CEVT1
CEVT2
CEVT3
CEVT4
CLK
Modulo 4
counter Stop
RST
Mod_eq
One−shot
control logic
Stop value (2b)
ECCTL2[STOP_WRAP]
ECCTL2[RE−ARM]
ECCTL2[CONT/ONESHT]
15.6.4 32-Bit Counter and Phase Control
This counter provides the time-base for event captures, and is clocked via the system clock.
A phase register is provided to achieve synchronization with other counters, via a hardware and software
forced sync. This is useful in APWM mode when a phase offset between modules is needed.
On any of the four event loads, an option to reset the 32-bit counter is given. This is useful for time
difference capture. The 32-bit counter value is captured first, then it is reset to 0 by any of the LD1-LD4
signals.
1996
Enhanced Capture (eCAP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Capture Mode Description
www.ti.com
Figure 15-7. Details of the Counter and Synchronization Block
SYNC
ECCTL2[SWSYNC]
ECCTL2[SYNCOSEL]
SYNCI
CTR=PRD
Disable
Disable
ECCTL2[SYNCI_EN]
SYNCO
Sync out
select
CTRPHS
LD_CTRPHS
RST
Delta−mode
TSCTR
(counter 32b)
SYSCLK
CLK
OVF
CTR−OVF
CTR[31−0]
15.6.5 CAP1-CAP4 Registers
These 32-bit registers are fed by the 32-bit counter timer bus, CTR[0-31] and are loaded (capture a timestamp) when their respective LD inputs are strobed.
Control bit CAPLDEN can inhibit loading of the capture registers. During one-shot operation, this bit is
cleared (loading is inhibited) automatically when a stop condition occurs, StopValue = Mod4.
CAP1 and CAP2 registers become the active period and compare registers, respectively, in APWM mode.
CAP3 and CAP4 registers become the respective shadow registers (APRD and ACMP) for CAP1 and
CAP2 during APWM operation.
15.6.6 eCAP Synchronization
eCAP modules can be synchronized with each other by selecting a common SYNCIN source. SYNCIN
source for eCAP can be either software sync-in or external sync-in. The external sync-in signal can come
from EPWM or eCAP or X-Bar. The SWSYNC of the eCAP module is logical OR’d with the SYNC signal
as shown in Figure 15-7. The SYNC signal is defined by the selection of SYNCSELECT[ECAPxSYNCIN]
as shown in Figure 15-8.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
1997
Capture Mode Description
www.ti.com
Figure 15-8. Time-Base Counter Synchronization Scheme
EXTSYNCIN1
EXTSYNCIN2
EPWM1
EPWM1SYNCOUT
EPWM2
EPWM4
EPWM3
EXTSYNCOUT
EPWM4SYNCOUT
Pulse-Stretched
(8 PLLSYSCLK
Cycles)
EPWM5
SYNCSEL.EPWM4SYNCIN
EPWM6
EPWM7
EPWM7SYNCOUT
EPWM8
SYNCSEL.EPWM7SYNCIN
EPWM9
EPWM10
EPWM10SYNCOUT
EPWM11
SYNCSEL.EPWM10SYNCIN
EPWM12
ECAP1
ECAP1SYNCOUT
SYNCSEL.SYNCOUT
SYNCSEL.ECAP1SYNCIN
ECAP2
ECAP3
SYNCSEL.ECAP4SYNCIN
ECAP4
ECAP5
ECAP6
15.6.6.1 Example 1 - Using SWSYNC with ECAP Module
Implement the following steps to use SWSYNC with ECAP1 and ECAP3.
• Configure ECAP[1..3].ECCTL2.SYNCO_SEL = 0x0, to allow the sync-in event to be the sync-out signal
pass through.
• Configure ECAP[2..3].ECCTL2.SWSYNC = 0x0, to disable software synchronization for eCAP2
through eCAP3.
• The default sync signal comes from ePWM1, if TBCTL[SYNCOSEL] is not correctly configured this can
cause undesired resets of the time-stamp register (TSCTR). Select an unused GPIO in
InputXbarRegs.INPUT5SELECT. Configure this GPIO in output mode and Write ‘0’ to GPIO DAT
register. By default this is programmed to GPIO0 so any activity on this pin will cause problems with
the SWSYNC.
• Program SYNCSEL[ECAP1SYNCIN] = 0x5. This will take ECAPx.EXTSYNCIN to an inactive state.
• Configure ECAP1.ECCTL2.SWSYNC=0x1, this forces Software Synchronization of TSCTR counter
To use SWSYNC with other eCAP modules, ensure that the previous eCAP chain is not generating a
SYNCOUT signal which will interfere with the software synchronization.
1998
Enhanced Capture (eCAP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Capture Mode Description
www.ti.com
15.6.7 Interrupt Control
Operation and features of eCAP Interrupt Control include:
•
•
•
•
•
An Interrupt can be generated on capture events (CEVT1-CEVT4, CTROVF) or APWM events (CTR =
PRD, CTR = CMP).
A counter overflow event (FFFFFFFF->00000000) is also provided as an interrupt source (CTROVF).
The capture events are edge and sequencer-qualified (ordered in time) by the polarity select and Mod4
gating, respectively.
One of these events can be selected as the interrupt source (from the eCAPx module) going to the PIE
and CLA.
Seven interrupt events (CEVT1, CEVT2, CEVT3, CEVT4, CNTOVF, CTR=PRD, CTR=CMP) can be
generated. The interrupt enable register (ECEINT) is used to enable/disable individual interrupt event
sources. The interrupt flag register (ECFLG) indicates if any interrupt event has been latched and
contains the global interrupt flag bit (INT). An interrupt pulse is generated to the PIE only if any of the
interrupt events are enabled, the flag bit is 1, and the INT flag bit is 0. The interrupt service routine
must clear the global interrupt flag bit and the serviced event via the interrupt clear register (ECCLR)
before any other interrupt pulses are generated. You can force an interrupt event via the interrupt force
register (ECFRC). This is useful for test purposes.
Note: The CEVT1, CEVT2, CEVT3, CEVT4 flags are only active in capture mode (ECCTL2[CAP/APWM
== 0]). The CTR=PRD, CTR=CMP flags are only valid in APWM mode (ECCTL2[CAP/APWM == 1]).
CNTOVF flag is valid in both modes.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
1999
Capture Mode Description
www.ti.com
Figure 15-9. Interrupts in eCAP Module
ECFLG
Clear
ECCLR
ECFRC
Latch
ECEINT
Set
CEVT1
ECFLG
Clear
ECCLR
ECFRC
Latch
ECFLG
ECEINT
ECCLR
Set
ECFLG
Clear
Clear
Latch
ECEINT
Generate
interrupt
pulse when
input=1
ECCLR
ECFRC
Latch
Set
ECAPxINT
CEVT2
1
Set
CEVT3
ECFLG
0
Clear
0
ECCLR
ECFRC
Latch
ECEINT
Set
CEVT4
ECFLG
Clear
ECCLR
ECFRC
Latch
CTROVF
Set
ECEINT
ECFLG
Clear
ECCLR
ECFRC
Latch
ECEINT
PRDEQ
Set
ECFLG
Clear
Latch
ECEINT
Set
ECCLR
ECFRC
CMPEQ
15.6.8 Shadow Load and Lockout Control
In capture mode, this logic inhibits (locks out) any shadow loading of CAP1 or CAP2 from APRD and
ACMP registers, respectively.
In APWM mode, shadow loading is active and two choices are permitted:
• Immediate - APRD or ACMP are transferred to CAP1 or CAP2 immediately upon writing a new value.
• On period equal, CTR[31:0] = PRD[31:0].
15.6.9 APWM Mode Operation
Main operating highlights of the APWM section:
2000
Enhanced Capture (eCAP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Capture Mode Description
www.ti.com
•
•
•
•
•
The time-stamp counter bus is made available for comparison via 2 digital (32-bit) comparators.
When CAP1/2 registers are not used in capture mode, their contents can be used as Period and
Compare values in APWM mode.
Double buffering is achieved via shadow registers APRD and ACMP (CAP3/4). The shadow register
contents are transferred over to CAP1/2 registers, either immediately upon a write, or on a CTR = PRD
trigger.
In APWM mode, writing to CAP1/CAP2 active registers will also write the same value to the
corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow
registers CAP3/CAP4 will invoke the shadow mode.
During initialization, you must write to the active registers for both period and compare. This
automatically copies the initial values into the shadow values. For subsequent compare updates,
during run-time, you only need to use the shadow registers.
Figure 15-10. PWM Waveform Details Of APWM Mode Operation
TSCTR
FFFFFFFF
APRD
1000h
500h
ACMP
300h
0000000C
APWMx
(o/p pin)
On
time
Off−time
Period
The behavior of APWM active high mode (APWMPOL == 0) is as follows:
CMP = 0x00000000, output low for duration of period (0% duty)
CMP = 0x00000001, output high 1 cycle
CMP = 0x00000002, output high 2 cycles
CMP = PERIOD, output high except for 1 cycle ( PERIOD+1, output high for complete period
The behavior of APWM active low mode (APWMPOL == 1) is as follows:
CMP = 0x00000000, output high for duration of period (0% duty)
CMP = 0x00000001, output low 1 cycle
CMP = 0x00000002, output low 2 cycles
CMP = PERIOD, output low except for 1 cycle ( PERIOD+1, output low for complete period
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
2001
Application of the eCAP Module
www.ti.com
Figure 15-11. Time-Base Frequency and Period Calculation
TPWM
4
4
4
3
3
3
2
1
1
1
0
0
0
TPWM
2
2
FPWM
CAP1 1 u T TSCTR
1
TPWM
15.7 Application of the eCAP Module
The following sections will provide applications examples to show how to operate the eCAP module.
15.7.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger
Figure 15-12 shows an example of continuous capture operation (Mod4 counter wraps around). In this
figure, TSCTR counts-up without resetting and capture events are qualified on the rising edge only, this
gives period (and frequency) information.
On an event, the TSCTR contents (time-stamp) is first captured, then Mod4 counter is incremented to the
next state. When the TSCTR reaches FFFFFFFF (maximum value), it wraps around to 00000000 (not
shown in Figure 15-12), if this occurs, the CTROVF (counter overflow) flag is set, and an interrupt (if
enabled) occurs, CTROVF (counter overflow) Flag is set, and an Interrupt (if enabled) occurs. Captured
Time-stamps are valid at the point indicated by the diagram (after the 4th event), hence event CEVT4 can
conveniently be used to trigger an interrupt and the CPU can read data from the CAPx registers.
Figure 15-12. Capture Sequence for Absolute Time-stamp and Rising Edge Detect
CEVT1
CEVT2
CEVT3
CEVT4
CEVT1
CAPx pin
t5
t4
FFFFFFFF
t3
t2
t1
CTR[0−31]
00000000
MOD4
CTR
CAP1
0
1
2
XX
3
0
1
t5
t1
CAP2
XX
t2
XX
CAP3
t3
XX
CAP4
t4
t
Polarity selection
Capture registers [1−4]
2002
Enhanced Capture (eCAP)
All capture values valid
(can be read) at this time
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Application of the eCAP Module
www.ti.com
15.7.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger
In Figure 15-13 the eCAP operating mode is almost the same as in the previous section except capture
events are qualified as either rising or falling edge, this now gives both period and duty cycle information,
that is: Period1 = t3 – t1, Period2 = t5 – t3, …and so on. Duty Cycle1 (on-time %) = (t2 – t1) / Period1 x
100%, etc. Duty Cycle1 (off-time %) = (t3 – t2) / Period1 x 100%, and so on.
Figure 15-13. Capture Sequence for Absolute Time-stamp With Rising and Falling Edge Detect
CEVT1
CEVT2
CEVT3
CEVT4
CEVT1
CEVT2
CEVT4
CEVT1
CEVT3
CAPx pin
FFFFFFFF
t6
t5
CTR[0−31]
t3
t9
t8
t7
t4
t2
t1
00000000
MOD4
CTR
CAP1
CAP2
CAP3
CAP4
0
1
2
XX
3
0
1
t1
XX
0
t6
t3
XX
3
t5
t2
XX
2
t7
t4
t8
tt
Polarity selection
Capture registers [1−4]
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
2003
Application of the eCAP Module
www.ti.com
15.7.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger
This example Figure 15-14 shows how the eCAP module can be used to collect Delta timing data from
pulse train waveforms. Here Continuous Capture mode (TSCTR counts-up without resetting, and Mod4
counter wraps around) is used. In Delta-time mode, TSCTR is Reset back to Zero on every valid event.
Here Capture events are qualified as Rising edge only. On an event, TSCTR contents (Time-Stamp) is
captured first, and then TSCTR is reset to Zero. The Mod4 counter then increments to the next state. If
TSCTR reaches FFFFFFFF (Max value), before the next event, it wraps around to 00000000 and
continues, a CNTOVF (counter overflow) Flag is set, and an Interrupt (if enabled) occurs. The advantage
of Delta-time Mode is that the CAPx contents directly give timing data without the need for CPU
calculations, that is, Period1 = T1, Period2 = T2,…etc. As shown in the diagram, the CEVT1 event is a
good trigger point to read the timing data, T1, T2, T3, T4 are all valid here.
Figure 15-14. Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect
CEVT1
CEVT3
CEVT2
CEVT4
CEVT1
CAPx pin
T1
FFFFFFFF
T3
T2
T4
CTR[0−31]
00000000
MOD4
CTR
CAP1
0
1
2
XX
3
0
1
CTR value at CEVT1
t4
XX
CAP2
t1
XX
CAP3
t2
XX
CAP4
t3
t
Polarity selection
Capture registers [1−4]
2004
Enhanced Capture (eCAP)
All capture values valid
(can be read) at this time
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Application of the eCAP Module
www.ti.com
15.7.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger
In Figure 15-15 the eCAP operating mode is almost the same as in previous section except Capture
events are qualified as either Rising or Falling edge, this now gives both Period and Duty cycle
information, that is: Period1 = T1+T2, Period2 = T3+T4, …and so on, Duty Cycle1 (on-time %) = T1 /
Period1 x 100%, Duty Cycle1 (off-time %) = T2 / Period1 x 100%, and so on.
Figure 15-15. Capture Sequence for Delta Mode Time-stamp With Rising and Falling Edge Detect
CEVT4
CEVT2
CEVT2
CEVT3
CEVT1
CEVT4
CEVT5
CEVT3
CEVT1
CAPx pin
T1
FFFFFFFF
T3
T5
T8
T2
T6
T4
T7
CTR[0−31]
00000000
MOD4
CTR
CAP1
CAP2
CAP3
CAP4
0
1
XX
2
3
0
1
2
t5
t1
XX
t2
XX
0
t4
CTR value at CEVT1
XX
3
t6
t3
t7
t
Polarity selection
Capture registers [1−4]
During initialization, you must write to the active registers for both period and compare. This action will
automatically copy the init values into the shadow values. For subsequent compare updates during runtime, the shadow registers must be used.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
2005
Application of the APWM Mode
www.ti.com
15.8 Application of the APWM Mode
In this example, the eCAP module is configured to operate as a PWM generator. Here, a very simple
single-channel PWM waveform is generated from the APWMx output pin. The PWM polarity is active high,
which means that the compare value (CAP2 reg is now a compare register) represents the on-time (high
level) of the period. Alternatively, if the APWMPOL bit is configured for active low, then the compare value
represents the off-time.
15.8.1 Example 1 - Simple PWM Generation (Independent Channel/s)
Figure 15-16. PWM Waveform Details of APWM Mode Operation
TSCTR
FFFFFFFF
APRD
1000h
500h
ACMP
300h
0000000C
APWMx
(o/p pin)
On
time
Off−time
Period
NOTE: Values are in hexadecimal (“h”) notation.
2006
Enhanced Capture (eCAP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eCAP Registers
www.ti.com
15.9 eCAP Registers
This section describes the Enhanced Capture Registers.
15.9.1 eCAP Base Addresses
Table 15-1. eCAP Base Address Table
Device Register
Register Name
Start Address
End Address
ECap1Regs
ECAP_REGS
0x0000_5000
0x0000_501F
ECap2Regs
ECAP_REGS
0x0000_5020
0x0000_503F
ECap3Regs
ECAP_REGS
0x0000_5040
0x0000_505F
ECap4Regs
ECAP_REGS
0x0000_5060
0x0000_507F
ECap5Regs
ECAP_REGS
0x0000_5080
0x0000_509F
ECap6Regs
ECAP_REGS
0x0000_50A0
0x0000_50BF
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
2007
eCAP Registers
www.ti.com
15.9.2 ECAP_REGS Registers
Table 15-2 lists the ECAP_REGS registers. All register offset addresses not listed in Table 15-2 should be
considered as reserved locations and the register contents should not be modified.
Table 15-2. ECAP_REGS Registers
Offset
Acronym
Register Name
0h
TSCTR
Time-Stamp Counter
Write Protection
Section
Go
2h
CTRPHS
Counter Phase Offset Value Register
Go
4h
CAP1
Capture 1 Register
Go
6h
CAP2
Capture 2 Register
Go
8h
CAP3
Capture 3 Register
Go
Ah
CAP4
Capture 4 Register
Go
14h
ECCTL1
Capture Control Register 1
Go
15h
ECCTL2
Capture Control Register 2
Go
16h
ECEINT
Capture Interrupt Enable Register
Go
17h
ECFLG
Capture Interrupt Flag Register
Go
18h
ECCLR
Capture Interrupt Clear Register
Go
19h
ECFRC
Capture Interrupt Force Register
Go
Complex bit access types are encoded to fit into small table cells. Table 15-3 shows the codes that are
used for access types in this section.
Table 15-3. ECAP_REGS Access Type Codes
Access Type
Code
Description
R
R
Read
R-0
R
-0
Read
Returns 0s
W
W
Write
W1C
W
1C
Write
1 to clear
W1S
W
1S
Write
1 to set
Read Type
Write Type
Reset or Default Value
-n
Value after reset or the default
value
Register Array Variables
2008
i,j,k,l,m,n
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y
When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.
Enhanced Capture (eCAP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eCAP Registers
www.ti.com
15.9.2.1 TSCTR Register (Offset = 0h) [reset = 0h]
TSCTR is shown in Figure 15-17 and described in Table 15-4.
Return to the Summary Table.
Time-Stamp Counter
Figure 15-17. TSCTR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TSCTR
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 15-4. TSCTR Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
TSCTR
R/W
0h
Active 32-bit counter register that is used as the capture time-base
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
2009
eCAP Registers
www.ti.com
15.9.2.2 CTRPHS Register (Offset = 2h) [reset = 0h]
CTRPHS is shown in Figure 15-18 and described in Table 15-5.
Return to the Summary Table.
Counter Phase Offset Value Register
Figure 15-18. CTRPHS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CTRPHS
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 15-5. CTRPHS Register Field Descriptions
Bit
31-0
2010
Field
Type
Reset
Description
CTRPHS
R/W
0h
Counter phase value register that can be programmed for phase
lag/lead. This register CTRPHS is loaded into TSCTR upon either a
SYNCI event or S/W force via a control bit. Used to achieve phase
control synchronization with respect to other eCAP and EPWM
timebases.
Reset type: SYSRSn
Enhanced Capture (eCAP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eCAP Registers
www.ti.com
15.9.2.3 CAP1 Register (Offset = 4h) [reset = 0h]
CAP1 is shown in Figure 15-19 and described in Table 15-6.
Return to the Summary Table.
Capture 1 Register
Figure 15-19. CAP1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CAP1
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 15-6. CAP1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
CAP1
R/W
0h
This register can be loaded (written) by:
- Time-Stamp counter value (TSCTR) during a capture event
- Software - may be useful for test purposes or initialization
- ARPD shadow register (CAP3) when used in APWM mode
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
2011
eCAP Registers
www.ti.com
15.9.2.4 CAP2 Register (Offset = 6h) [reset = 0h]
CAP2 is shown in Figure 15-20 and described in Table 15-7.
Return to the Summary Table.
Capture 2 Register
Figure 15-20. CAP2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CAP2
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 15-7. CAP2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
CAP2
R/W
0h
This register can be loaded (written) by:
- Time-Stamp ( counter value) during a capture event
- Software - may be useful for test purposes
- ACMP shadow register (CAP4) when used in APWM mode
Reset type: SYSRSn
2012
Enhanced Capture (eCAP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eCAP Registers
www.ti.com
15.9.2.5 CAP3 Register (Offset = 8h) [reset = 0h]
CAP3 is shown in Figure 15-21 and described in Table 15-8.
Return to the Summary Table.
Capture 3 Register
Figure 15-21. CAP3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CAP3
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 15-8. CAP3 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
CAP3
R/W
0h
In CMP mode, this is a time-stamp capture register.
In APWM mode, this is the period shadow (APRD) register. You can
update the PWM period value through this register. CAP3 (APRD)
shadows CAP1 in this mode.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
2013
eCAP Registers
www.ti.com
15.9.2.6 CAP4 Register (Offset = Ah) [reset = 0h]
CAP4 is shown in Figure 15-22 and described in Table 15-9.
Return to the Summary Table.
Capture 4 Register
Figure 15-22. CAP4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CAP4
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 15-9. CAP4 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
CAP4
R/W
0h
In CMP mode, this is a time-stamp capture register.
In APWM mode, this is the compare shadow (ACMP) register. You
can update the PWM compare value via this register. CAP4 (ACMP)
shadows CAP2 in this mode.
Reset type: SYSRSn
2014
Enhanced Capture (eCAP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eCAP Registers
www.ti.com
15.9.2.7 ECCTL1 Register (Offset = 14h) [reset = 0h]
ECCTL1 is shown in Figure 15-23 and described in Table 15-10.
Return to the Summary Table.
Capture Control Register 1
Figure 15-23. ECCTL1 Register
15
14
13
12
11
PRESCALE
R/W-0h
10
9
8
CAPLDEN
R/W-0h
6
CAP4POL
R/W-0h
5
CTRRST3
R/W-0h
4
CAP3POL
R/W-0h
3
CTRRST2
R/W-0h
2
CAP2POL
R/W-0h
1
CTRRST1
R/W-0h
0
CAP1POL
R/W-0h
FREE_SOFT
R/W-0h
7
CTRRST4
R/W-0h
Table 15-10. ECCTL1 Register Field Descriptions
Field
Type
Reset
Description
15-14
Bit
FREE_SOFT
R/W
0h
Emulation Control
Reset type: SYSRSn
0h (R/W) = TSCTR counter stops immediately on emulation
suspend
1h (R/W) = TSCTR counter runs until = 0
2h (R/W) = TSCTR counter is unaffected by emulation suspend
(Run Free)
3h (R/W) = TSCTR counter is unaffected by emulation suspend
(Run Free)
13-9
PRESCALE
R/W
0h
Event Filter prescale select
Reset type: SYSRSn
0h (R/W) = Divide by 1 (i.e,. no prescale, by-pass the prescaler)
1h (R/W) = Divide by 2
2h (R/W) = Divide by 4
3h (R/W) = Divide by 6
4h (R/W) = Divide by 8
5h (R/W) = Divide by 10
1Eh (R/W) = Divide by 60
1Fh (R/W) = Divide by 62
8
CAPLDEN
R/W
0h
Enable Loading of CAP1-4 registers on a capture event. Note that
this bit does not disable CEVTn events from being generated.
Reset type: SYSRSn
0h (R/W) = Disable CAP1-4 register loads at capture event time.
1h (R/W) = Enable CAP1-4 register loads at capture event time.
7
CTRRST4
R/W
0h
Counter Reset on Capture Event 4
Reset type: SYSRSn
0h (R/W) = Do not reset counter on Capture Event 4 (absolute time
stamp operation)
1h (R/W) = Reset counter after Capture Event 4 time-stamp has
been captured (used in difference mode operation)
6
CAP4POL
R/W
0h
Capture Event 4 Polarity select
Reset type: SYSRSn
0h (R/W) = Capture Event 4 triggered on a rising edge (RE)
1h (R/W) = Capture Event 4 triggered on a falling edge (FE)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
2015
eCAP Registers
www.ti.com
Table 15-10. ECCTL1 Register Field Descriptions (continued)
Bit
2016
Field
Type
Reset
Description
5
CTRRST3
R/W
0h
Counter Reset on Capture Event 3
Reset type: SYSRSn
0h (R/W) = Do not reset counter on Capture Event 3 (absolute time
stamp)
1h (R/W) = Reset counter after Event 3 time-stamp has been
captured (used in difference mode operation)
4
CAP3POL
R/W
0h
Capture Event 3 Polarity select
Reset type: SYSRSn
0h (R/W) = Capture Event 3 triggered on a rising edge (RE)
1h (R/W) = Capture Event 3 triggered on a falling edge (FE)
3
CTRRST2
R/W
0h
Counter Reset on Capture Event 2
Reset type: SYSRSn
0h (R/W) = Do not reset counter on Capture Event 2 (absolute time
stamp)
1h (R/W) = Reset counter after Event 2 time-stamp has been
captured (used in difference mode operation)
2
CAP2POL
R/W
0h
Capture Event 2 Polarity select
Reset type: SYSRSn
0h (R/W) = Capture Event 2 triggered on a rising edge (RE)
1h (R/W) = Capture Event 2 triggered on a falling edge (FE)
1
CTRRST1
R/W
0h
Counter Reset on Capture Event 1
Reset type: SYSRSn
0h (R/W) = Do not reset counter on Capture Event 1 (absolute time
stamp)
1h (R/W) = Reset counter after Event 1 time-stamp has been
captured (used in difference mode operation)
0
CAP1POL
R/W
0h
Capture Event 1 Polarity select
Reset type: SYSRSn
0h (R/W) = Capture Event 1 triggered on a rising edge (RE)
1h (R/W) = Capture Event 1 triggered on a falling edge (FE)
Enhanced Capture (eCAP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eCAP Registers
www.ti.com
15.9.2.8 ECCTL2 Register (Offset = 15h) [reset = 6h]
ECCTL2 is shown in Figure 15-24 and described in Table 15-11.
Return to the Summary Table.
Capture Control Register 2
Figure 15-24. ECCTL2 Register
15
14
13
RESERVED
R-0h
12
11
10
APWMPOL
R/W-0h
9
CAP_APWM
R/W-0h
8
SWSYNC
R-0/W1S-0h
6
5
SYNCI_EN
4
TSCTRSTOP
3
REARM
2
1
SYNCO_SEL
R/W-0h
R/W-0h
R/W-0h
R-0/W1S-0h
0
CONT_ONESH
T
R/W-0h
7
STOP_WRAP
R/W-3h
Table 15-11. ECCTL2 Register Field Descriptions
Field
Type
Reset
Description
15-11
Bit
RESERVED
R
0h
Reserved
10
APWMPOL
R/W
0h
APWM output polarity select. This is applicable only in APWM
operating mode.
Reset type: SYSRSn
0h (R/W) = Output is active high (Compare value defines high time)
1h (R/W) = Output is active low (Compare value defines low time)
9
CAP_APWM
R/W
0h
CAP/APWM operating mode select
Reset type: SYSRSn
0h (R/W) = ECAP module operates in capture mode. This mode
forces the following configuration:
- Inhibits TSCTR resets via CTR = PRD event
- Inhibits shadow loads on CAP1 and 2 registers
- Permits user to enable CAP1-4 register load
- CAPx/APWMx pin operates as a capture input
1h (R/W) = ECAP module operates in APWM mode. This mode
forces the following configuration:
- Resets TSCTR on CTR = PRD event (period boundary
- Permits shadow loading on CAP1 and 2 registers
- Disables loading of time-stamps into CAP1-4 registers
- CAPx/APWMx pin operates as a APWM output
8
SWSYNC
R-0/W1S
0h
Software-forced Counter (TSCTR) Synchronizer. This provides the
user a method to generate a synchronization pulse through software.
In APWM mode, the synchronization pulse can also be sourced from
the CTR = PRD event.
Reset type: SYSRSn
0h (R/W) = Writing a zero has no effect. Reading always returns a
zero
1h (R/W) = Writing a one forces a TSCTR shadow load of current
ECAP module and any ECAP modules down-stream providing the
SYNCO_SEL bits are 0,0. After writing a 1, this bit returns to a
zero.
Note: Selection CTR = PRD is meaningful only in APWM mode
however, you can choose it in CAP mode if you find doing so
useful.
SYNCO_SEL
R/W
0h
Sync-Out Select
Reset type: SYSRSn
0h (R/W) = Select sync-in event to be the sync-out signal (pass
through)
1h (R/W) = Select CTR = PRD event to be the sync-out signal
2h (R/W) = Disable sync out signal
3h (R/W) = Disable sync out signal
7-6
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
2017
eCAP Registers
www.ti.com
Table 15-11. ECCTL2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
SYNCI_EN
R/W
0h
Counter (TSCTR) Sync-In select mode
Reset type: SYSRSn
0h (R/W) = Disable sync-in option
1h (R/W) = Enable counter (TSCTR) to be loaded from CTRPHS
register upon either a SYNCI signal or a S/W force event.
4
TSCTRSTOP
R/W
0h
Time Stamp (TSCTR) Counter Stop (freeze) Control
Reset type: SYSRSn
0h (R/W) = TSCTR stopped
1h (R/W) = TSCTR free-running
3
REARM
R-0/W1S
0h
Re-Arming Control. Note: The re-arm function is valid in one shot or
continuous mode.
Reset type: SYSRSn
0h (R/W) = Has no effect (reading always returns a 0)
1h (R/W) = Arms the one-shot sequence as follows:
1) Resets the Mod4 counter to zero
2) Unfreezes the Mod4 counter
3) Enables capture register loads
STOP_WRAP
R/W
3h
Stop value for one-shot mode. This is the number (between 1-4) of
captures allowed to occur before the CAP(1-4) registers are frozen,
that is, capture sequence is stopped.
2-1
Wrap value for continuous mode. This is the number (between 1-4)
of the capture register in which the circular buffer wraps around and
starts again.
Notes: STOP_WRAP is compared to Mod4 counter and, when
equal, 2 actions occur:
- Mod4 counter is stopped (frozen)
- Capture register loads are inhibited
In one-shot mode, further interrupt events are blocked until rearmed.
Reset type: SYSRSn
0h (R/W) = Stop after Capture Event 1 in one-shot mode
Wrap after Capture Event 1 in continuous mode.
1h (R/W) = Stop after Capture Event 2 in one-shot mode
Wrap after Capture Event 2 in continuous mode.
2h (R/W) = Stop after Capture Event 3 in one-shot mode
Wrap after Capture Event 3 in continuous mode.
3h (R/W) = Stop after Capture Event 4 in one-shot mode
Wrap after Capture Event 4 in continuous mode.
0
2018
CONT_ONESHT
Enhanced Capture (eCAP)
R/W
0h
Continuous or one-shot mode control (applicable only in capture
mode)
Reset type: SYSRSn
0h (R/W) = Operate in continuous mode
1h (R/W) = Operate in one-Shot mode
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eCAP Registers
www.ti.com
15.9.2.9 ECEINT Register (Offset = 16h) [reset = 0h]
ECEINT is shown in Figure 15-25 and described in Table 15-12.
Return to the Summary Table.
The interrupt enable bits (CEVT1, ...) block any of the selected events from generating an interrupt.
Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the
ECFRC/ECCLR registers.
The proper procedure for configuring peripheral modes and interrupts is as follows:
- Disable global interrupts
- Stop eCAP counter
- Disable eCAP interrupts
- Configure peripheral registers
- Clear spurious eCAP interrupt flags
- Enable eCAP interrupts
- Start eCAP counter
- Enable global interrupts
Figure 15-25. ECEINT Register
15
14
13
12
11
10
9
8
3
CEVT3
R/W-0h
2
CEVT2
R/W-0h
1
CEVT1
R/W-0h
0
RESERVED
R-0h
RESERVED
R-0h
7
CTR_EQ_CMP
R/W-0h
6
CTR_EQ_PRD
R/W-0h
5
CTROVF
R/W-0h
4
CEVT4
R/W-0h
Table 15-12. ECEINT Register Field Descriptions
Bit
15-8
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
7
CTR_EQ_CMP
R/W
0h
Counter Equal Compare Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Compare Equal as an Interrupt source
1h (R/W) = Enable Compare Equal as an Interrupt source
6
CTR_EQ_PRD
R/W
0h
Counter Equal Period Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Period Equal as an Interrupt source
1h (R/W) = Enable Period Equal as an Interrupt source
5
CTROVF
R/W
0h
Counter Overflow Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disabled counter Overflow as an Interrupt source
1h (R/W) = Enable counter Overflow as an Interrupt source
4
CEVT4
R/W
0h
Capture Event 4 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Capture Event 4 as an Interrupt source
1h (R/W) = Capture Event 4 Interrupt Enable
3
CEVT3
R/W
0h
Capture Event 3 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Capture Event 3 as an Interrupt source
1h (R/W) = Enable Capture Event 3 as an Interrupt source
2
CEVT2
R/W
0h
Capture Event 2 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Capture Event 2 as an Interrupt source
1h (R/W) = Enable Capture Event 2 as an Interrupt source
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
2019
eCAP Registers
www.ti.com
Table 15-12. ECEINT Register Field Descriptions (continued)
Bit
2020
Field
Type
Reset
Description
1
CEVT1
R/W
0h
Capture Event 1 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Capture Event 1 as an Interrupt source
1h (R/W) = Enable Capture Event 1 as an Interrupt source
0
RESERVED
R
0h
Reserved
Enhanced Capture (eCAP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eCAP Registers
www.ti.com
15.9.2.10 ECFLG Register (Offset = 17h) [reset = 0h]
ECFLG is shown in Figure 15-26 and described in Table 15-13.
Return to the Summary Table.
Capture Interrupt Flag Register
Figure 15-26. ECFLG Register
15
14
13
12
11
10
9
8
3
CEVT3
R-0h
2
CEVT2
R-0h
1
CEVT1
R-0h
0
INT
R-0h
RESERVED
R-0h
7
CTR_CMP
R-0h
6
CTR_PRD
R-0h
5
CTROVF
R-0h
4
CEVT4
R-0h
Table 15-13. ECFLG Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
7
CTR_CMP
R
0h
Compare Equal Compare Status Flag. This flag is active only in
APWM mode.
Reset type: SYSRSn
0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the counter (TSCTR) reached the compare
register value (ACMP)
6
CTR_PRD
R
0h
Counter Equal Period Status Flag. This flag is only active in APWM
mode.
Reset type: SYSRSn
0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the counter (TSCTR) reached the period
register value (APRD) and was reset.
5
CTROVF
R
0h
Counter Overflow Status Flag. This flag is active in CAP and APWM
mode.
Reset type: SYSRSn
0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the counter (TSCTR) has made the transition
from FFFFFFFF " 00000000
4
CEVT4
R
0h
Capture Event 4 Status Flag This flag is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the fourth event occurred at ECAPx pin
3
CEVT3
R
0h
Capture Event 3 Status Flag. This flag is active only in CAP mode.
Reset type: SYSRSn
0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the third event occurred at ECAPx pin.
2
CEVT2
R
0h
Capture Event 2 Status Flag. This flag is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the second event occurred at ECAPx pin.
1
CEVT1
R
0h
Capture Event 1 Status Flag. This flag is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates the first event occurred at ECAPx pin.
15-8
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
2021
eCAP Registers
www.ti.com
Table 15-13. ECFLG Register Field Descriptions (continued)
Bit
0
2022
Field
Type
Reset
Description
INT
R
0h
Global Interrupt Status Flag
Reset type: SYSRSn
0h (R/W) = Indicates no event occurred
1h (R/W) = Indicates that an interrupt was generated.
Enhanced Capture (eCAP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eCAP Registers
www.ti.com
15.9.2.11 ECCLR Register (Offset = 18h) [reset = 0h]
ECCLR is shown in Figure 15-27 and described in Table 15-14.
Return to the Summary Table.
Capture Interrupt Clear Register
Figure 15-27. ECCLR Register
15
14
13
12
11
10
9
8
3
CEVT3
R-0/W1C-0h
2
CEVT2
R-0/W1C-0h
1
CEVT1
R-0/W1C-0h
0
INT
R-0/W1C-0h
RESERVED
R-0h
7
CTR_CMP
R-0/W1C-0h
6
CTR_PRD
R-0/W1C-0h
5
CTROVF
R-0/W1C-0h
4
CEVT4
R-0/W1C-0h
Table 15-14. ECCLR Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
7
CTR_CMP
R-0/W1C
0h
Counter Equal Compare Status Clear
Reset type: SYSRSn
0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CTR=CMP flag.
6
CTR_PRD
R-0/W1C
0h
Counter Equal Period Status Clear
Reset type: SYSRSn
0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CTR=PRD flag.
5
CTROVF
R-0/W1C
0h
Counter Overflow Status Clear
Reset type: SYSRSn
0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CTROVF flag.
4
CEVT4
R-0/W1C
0h
Capture Event 4 Status Clear
Reset type: SYSRSn
0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CEVT4 flag.
3
CEVT3
R-0/W1C
0h
Capture Event 3 Status Clear
Reset type: SYSRSn
0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CEVT3 flag.
2
CEVT2
R-0/W1C
0h
Capture Event 2 Status Clear
Reset type: SYSRSn
0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CEVT2 flag.
1
CEVT1
R-0/W1C
0h
Capture Event 1 Status Clear
Reset type: SYSRSn
0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the CEVT1 flag.
0
INT
R-0/W1C
0h
ECAP Global Interrupt Status Clear
Reset type: SYSRSn
0h (R/W) = Writing a 0 has no effect. Always reads back a 0
1h (R/W) = Writing a 1 clears the INT flag and enable further
interrupts to be generated if any of the event flags are set to 1
15-8
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP)
2023
eCAP Registers
www.ti.com
15.9.2.12 ECFRC Register (Offset = 19h) [reset = 0h]
ECFRC is shown in Figure 15-28 and described in Table 15-15.
Return to the Summary Table.
Capture Interrupt Force Register
Figure 15-28. ECFRC Register
15
14
13
12
11
10
9
8
3
CEVT3
R-0/W1S-0h
2
CEVT2
R-0/W1S-0h
1
CEVT1
R-0/W1S-0h
0
RESERVED
R-0h
RESERVED
R-0h
7
CTR_CMP
R-0/W1S-0h
6
CTR_PRD
R-0/W1S-0h
5
CTROVF
R-0/W1S-0h
4
CEVT4
R-0/W1S-0h
Table 15-15. ECFRC Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
7
CTR_CMP
R-0/W1S
0h
Force Counter Equal Compare Interrupt. This event is only active in
APWM mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CTR=CMP flag.
6
CTR_PRD
R-0/W1S
0h
Force Counter Equal Period Interrupt. This event is only active in
APWM mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CTR=PRD flag.
5
CTROVF
R-0/W1S
0h
Force Counter Overflow.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 to this bit sets the CTROVF flag.
4
CEVT4
R-0/W1S
0h
Force Capture Event 4. This event is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CEVT4 flag.
3
CEVT3
R-0/W1S
0h
Force Capture Event 3. This event is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CEVT3 flag.
2
CEVT2
R-0/W1S
0h
Force Capture Event 2. This event is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CEVT2 flag.
1
CEVT1
R-0/W1S
0h
Force Capture Event 1. This event is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Sets the CEVT1 flag.
0
RESERVED
R
0h
Reserved
15-8
2024
Enhanced Capture (eCAP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eCAP Registers
www.ti.com
15.9.3 Register to Driverlib Function Mapping
Table 15-16. ECAP Registers to Driverlib Functions
File
Driverlib Function
TSCTR
ecap.h
ECAP_getTimeBaseCounter
CTRPHS
ecap.h
ECAP_setPhaseShiftCount
CAP1
ecap.h
ECAP_setAPWMPeriod
ecap.h
ECAP_getEventTimeStamp
CAP2
ecap.h
ECAP_setAPWMCompare
ecap.h
ECAP_getEventTimeStamp
CAP3
ecap.h
ECAP_setAPWMShadowPeriod
ecap.h
ECAP_getEventTimeStamp
CAP4
ecap.h
ECAP_setAPWMShadowCompare
ecap.h
ECAP_getEventTimeStamp
ECCTL1
ecap.c
ECAP_setEmulationMode
ecap.h
ECAP_setEventPrescaler
ecap.h
ECAP_setEventPolarity
ecap.h
ECAP_enableCounterResetOnEvent
ecap.h
ECAP_disableCounterResetOnEvent
ecap.h
ECAP_enableTimeStampCapture
ecap.h
ECAP_disableTimeStampCapture
ECCTL2
ecap.h
ECAP_setCaptureMode
ecap.h
ECAP_reArm
ecap.h
ECAP_enableCaptureMode
ecap.h
ECAP_enableAPWMMode
ecap.h
ECAP_enableLoadCounter
ecap.h
ECAP_disableLoadCounter
ecap.h
ECAP_loadCounter
ecap.h
ECAP_setSyncOutMode
ecap.h
ECAP_stopCounter
ecap.h
ECAP_startCounter
ecap.h
ECAP_setAPWMPolarity
ECEINT
ecap.h
ECAP_enableInterrupt
ecap.h
ECAP_disableInterrupt
ECFLG
ecap.h
ECAP_getInterruptSource
ecap.h
ECAP_getGlobalInterruptStatus
ECCLR
ecap.h
ECAP_clearInterrupt
ecap.h
ECAP_clearGlobalInterrupt
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Enhanced Capture (eCAP) 2025
eCAP Registers
www.ti.com
Table 15-16. ECAP Registers to Driverlib Functions (continued)
File
Driverlib Function
ECFRC
ecap.h
2026
Enhanced Capture (eCAP)
ECAP_forceInterrupt
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Chapter 16
SPRUHM9F – October 2014 – Revised September 2019
Enhanced Quadrature Encoder Pulse (eQEP)
The enhanced Quadrature Encoder Pulse (eQEP) module described here is a Type-0 eQEP. See the
TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566) for a list of all devices with a module
of the same type to determine the differences between types and for a list of device-specific differences
within a type.
The enhanced quadrature encoder pulse (eQEP) module is used for direct interface with a linear or rotary
incremental encoder to get position, direction, and speed information from a rotating machine for use in a
high-performance motion and position-control system.
Topic
...........................................................................................................................
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
16.10
Introduction ...................................................................................................
Configuring Device Pins ..................................................................................
Description ....................................................................................................
Quadrature Decoder Unit (QDU)........................................................................
Position Counter and Control Unit (PCCU) .........................................................
eQEP Edge Capture Unit ..................................................................................
eQEP Watchdog..............................................................................................
Unit Timer Base ..............................................................................................
eQEP Interrupt Structure .................................................................................
eQEP Registers .............................................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
2028
2030
2030
2033
2036
2042
2046
2046
2047
2048
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
Page
2027
Introduction
www.ti.com
16.1 Introduction
An incremental encoder disk is patterned with a track of slots along its periphery, as shown in Figure 16-1.
These slots create an alternating pattern of dark and light lines. The disk count is defined as the number
of dark and light line pairs that occur per revolution (lines per revolution). As a rule, a second track is
added to generate a signal that occurs once per revolution (index signal: QEPI), which can be used to
indicate an absolute position. Encoder manufacturers identify the index pulse using different terms such as
index, marker, home position, and zero reference
Figure 16-1. Optical Encoder Disk
QEPA
QEPB
QEPI
To derive direction information, the lines on the disk are read out by two different photo-elements that
"look" at the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift is
detected with a reticle or mask that restricts the view of the photo-element to the desired part of the disk
lines. As the disk rotates, the two photo-elements generate signals that are shifted 90° out of phase from
each other. These are commonly called the quadrature QEPA and QEPB signals. The clockwise direction
for most encoders is defined as the QEPA channel going positive before the QEPB channel and vise
versa as shown in Figure 16-2.
Figure 16-2. QEP Encoder Output Signal for Forward/Reverse Movement
T0
Clockwise shaft rotation/forward movement
0
1
2
3
4
5
6
7
N−6 N−5 N−4 N−3 N−2 N−1
0
QEPA
QEPB
QEPI
T0
Anti-clockwise shaft rotation/reverse movement
0
N−1 N−2 N−3 N−4 N−5 N−6 N−7
6
5
4
3
2
1
0
N−1 N−2
QEPA
QEPB
QEPI
Legend: N = lines per revolution
The encoder wheel typically makes one revolution for every revolution of the motor, or the wheel may be
at a geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming
from the QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a
2000-line encoder directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a
frequency of 166.6 KHz, so by measuring the frequency of either the QEPA or QEPB output, the
processor can determine the velocity of the motor.
2028
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Introduction
www.ti.com
Quadrature encoders from different manufacturers come with two forms of index pulse (gated index pulse
or ungated index pulse) as shown in Figure 16-3. A nonstandard form of index pulse is ungated. In the
ungated configuration, the index edges are not necessarily coincident with A and B signals. The gated
index pulse is aligned to any of the four quadrature edges and width of the index pulse and can be equal
to a quarter, half, or full period of the quadrature signal.
Figure 16-3. Index Pulse Example
T0
QEPA
QEPB
0.25T0 ±0.1T0
QEPI
(gated to
A and B)
0.5T0 ±0.1T0
QEPI
(gated to A)
T0 ±0.5T0
QEPI
(ungated)
Some typical applications of shaft encoders include robotics and computer input in the form of a mouse.
Inside your mouse you can see where the mouse ball spins a pair of axles (a left/right, and an up/down
axle). These axles are connected to optical shaft encoders that effectively tell the computer how fast and
in what direction the mouse is moving.
General Issues: Estimating velocity from a digital position sensor is a cost-effective strategy in motor
control. Two different first order approximations for velocity may be written as:
x(k) * x(k * 1)
v(k) [
+ DX
T
T
X
X
v(k) [
+
t(k) * t(k * 1)
DT
(2)
(3)
where
v(k): Velocity at time instant k
x(k): Position at time instant k
x(k-1): Position at time instant k-1
T: Fixed unit time or inverse of velocity calculation rate
ΔX: Incremental position movement in unit time
t(k): Time instant "k"
t(k-1): Time instant "k-1"
X: Fixed unit position
ΔT: Incremental time elapsed for unit position movement.
Equation 2 is the conventional approach to velocity estimation and it requires a time base to provide a unit
time event for velocity calculation. Unit time is basically the inverse of the velocity calculation rate.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2029
Configuring Device Pins
www.ti.com
The encoder count (position) is read once during each unit time event. The quantity [x(k) - x(k-1)] is
formed by subtracting the previous reading from the current reading. Then the velocity estimate is
computed by multiplying by the known constant 1/T (where T is the constant time between unit time
events and is known in advance).
Estimation based on Equation 2 has an inherent accuracy limit directly related to the resolution of the
position sensor and the unit time period T. For example, consider a 500-line per revolution quadrature
encoder with a velocity calculation rate of 400 Hz. When used for position, the quadrature encoder gives a
four-fold increase in resolution; in this case, 2000 counts per revolution. The minimum rotation that can be
detected is therefore 0.0005 revolutions, which gives a velocity resolution of 12 rpm when sampled at 400
Hz. While this resolution may be satisfactory at moderate or high speeds, for example 1% error at 1200
rpm, it would clearly prove inadequate at low speeds. In fact, at speeds below 12 rpm, the speed estimate
would erroneously be zero much of the time.
At low speed, Equation 3 provides a more accurate approach. It requires a position sensor that outputs a
fixed interval pulse train, such as the aforementioned quadrature encoder. The width of each pulse is
defined by motor speed for a given sensor resolution. Equation 3 can be used to calculate motor speed by
measuring the elapsed time between successive quadrature pulse edges. However, this method suffers
from the opposite limitation, as does Equation 2. A combination of relatively large motor speeds and high
sensor resolution makes the time interval ΔT small, and thus more greatly influenced by the timer
resolution. This can introduce considerable error into high-speed estimates.
For systems with a large speed range (that is, speed estimation is needed at both low and high speeds),
one approach is to use Equation 3 at low speed and have the DSP software switch over to Equation 2
when the motor speed rises above some specified threshold.
16.2 Configuring Device Pins
The GPIO mux registers must be configured to connect this peripheral to the device pins. To avoid
glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding
GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value.
For proper operation of the eQEP module, input GPIO pins must be configured via the GPxQSELn
registers for synchronous input mode (with or without qualification). The asynchronous mode should not
be used for eQEP input pins. The internal pullups can be configured in the GPyPUD register.
See the GPIO chapter for more details on GPIO mux and settings.
16.3 Description
This section provides the eQEP inputs, memory map, and functional description.
16.3.1 EQEP Inputs
The eQEP inputs include two pins for quadrature-clock mode or direction-count mode, an index (or 0
marker), and a strobe input. The eQEP module requires that the QEPA, QEPB, and QEPI inputs are
synchronized to SYSCLK prior to entering the module. The application code should enable the
synchronous GPIO input feature on any eQEP-enabled GPIO pins (see the General-Purpose Input/Output
(GPIO) chapter for more details).
• QEPA/XCLK and QEPB/XDIR
These two pins can be used in quadrature-clock mode or direction-count mode.
– Quadrature-clock Mode
The eQEP encoders provide two square wave signals (A and B) 90 electrical degrees out of phase.
This phase relationship is used to determine the direction of rotation of the input shaft and number
of eQEP pulses from the index position to derive the relative position information. For forward or
clockwise rotation, QEPA signal leads QEPB signal and vice versa. The quadrature decoder uses
these two inputs to generate quadrature-clock and direction signals.
– Direction-count Mode
In direction-count mode, direction and clock signals are provided directly from the external source.
Some position encoders have this type of output instead of quadrature output. The QEPA pin
provides the clock input and the QEPB pin provides the direction input.
2030
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Description
www.ti.com
•
•
QEPI: Index or Zero Marker
The eQEP encoder uses an index signal to assign an absolute start position from which position
information is incrementally encoded using quadrature pulses. This pin is connected to the index
output of the eQEP encoder to optionally reset the position counter for each revolution. This signal can
be used to initialize or latch the position counter on the occurrence of a desired event on the index pin.
QEPS: Strobe Input
This general-purpose strobe signal can initialize or latch the position counter on the occurrence of a
desired event on the strobe pin. This signal is typically connected to a sensor or limit switch to notify
that the motor has reached a defined position.
16.3.2 Functional Description
The eQEP peripheral contains the following major functional units (as shown in Figure 16-4):
• Programmable input qualification for each pin (part of the GPIO MUX)
• Quadrature decoder unit (QDU)
• Position counter and control unit for position measurement (PCCU)
• Quadrature edge-capture unit for low-speed measurement (QCAP)
• Unit time base for speed/frequency measurement (UTIME)
• Watchdog timer for detecting stalls (QWDOG)
Figure 16-4. Functional Block Diagram of the eQEP Peripheral
System
control registers
To CPU
EQEPxENCLK
Data bus
SYSCLKOUT
QCPRD
QCTMR
QCAPCTL
16
16
16
Quadrature
capture unit
(QCAP)
QCTMRLAT
QCPRDLAT
QWDTMR
QWDPRD
QUTMR
QUPRD
Registers
used by
multiple units
32
QEPCTL
QEPSTS
QFLG
UTIME
16
UTOUT
QWDOG
QDECCTL
16
WDTOUT
PIE
QCLK
QDIR
QI
QS
PHE
EQEPxINT
32
Position counter/
control unit
(PCCU)
QPOSLAT
QPOSSLAT
QPOSILAT
Quadrature
decoder
(QDU)
PCSOUT
32
QPOSCNT
QPOSINIT
QPOSMAX
32
QPOSCMP
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
EQEPxA/XCLK
EQEPxB/XDIR
GPIO
MUX
EQEPxI
EQEPxS
16
QEINT
QFRC
QCLR
QPOSCTL
Enhanced QEP (eQEP) peripheral
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2031
Description
www.ti.com
16.3.3 eQEP Memory Map
Table 16-1 lists the registers with their memory locations, sizes, and reset values.
Table 16-1. EQEP Memory Map
Offset
Size(x16)/
#shadow
Reset
Register Description
QPOSCNT
0x00
2/0
0x00000000
eQEP Position Counter
QPOSINIT
0x02
2/0
0x00000000
eQEP Initialization Position Count
QPOSMAX
0x04
2/0
0x00000000
eQEP Maximum Position Count
QPOSCMP
0x06
2/1
0x00000000
eQEP Position-compare
QPOSILAT
0x08
2/0
0x00000000
eQEP Index Position Latch
QPOSSLAT
0x0A
2/0
0x00000000
eQEP Strobe Position Latch
QPOSLAT
0x0C
2/0
0x00000000
eQEP Position Latch
QUTMR
0x0E
2/0
0x00000000
QEP Unit Timer
QUPRD
0x10
2/0
0x00000000
eQEP Unit Period Register
QWDTMR
0x12
1/0
0x0000
eQEP Watchdog Timer
QWDPRD
0x13
1/0
0x0000
eQEP Watchdog Period Register
QDECCTL
0x14
1/0
0x0000
eQEP Decoder Control Register
QEPCTL
0x15
1/0
0x0000
eQEP Control Register
QCAPCTL
0x16
1/0
0x0000
eQEP Capture Control Register
QPOSCTL
0x17
1/0
0x00000
eQEP Position-compare Control Register
QEINT
0x18
1/0
0x0000
eQEP Interrupt Enable Register
QFLG
0x19
1/0
0x0000
eQEP Interrupt Flag Register
QCLR
0x1A
1/0
0x0000
eQEP Interrupt Clear Register
QFRC
0x1B
1/0
0x0000
eQEP Interrupt Force Register
QEPSTS
0x1C
1/0
0x0000
eQEP Status Register
QCTMR
0x1D
1/0
0x0000
eQEP Capture Timer
QCPRD
0x1E
1/0
0x0000
eQEP Capture Period Register
QCTMRLAT
0x1F
1/0
0x0000
eQEP Capture Timer Latch
QCPRDLAT
0x20
1/0
0x0000
eQEP Capture Period Latch
reserved
0x21
to
0x3F
31/0
Name
2032
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Quadrature Decoder Unit (QDU)
www.ti.com
16.4 Quadrature Decoder Unit (QDU)
Figure 16-5 shows a functional block diagram of the QDU.
Figure 16-5. Functional Block Diagram of Decoder Unit
QFLG:PHE
QEPSTS:QDF
QDECCTL:SWAP
QDECCTL:QAP
PHE
00
01
QCLK
10
11
iCLK
xCLK
xCLK
xCLK
QA
QDIR
10
11
EQEPxAIN
0
1
1
Quadrature
decoder
EQEPB
QB
00
01
0
EQEPA
EQEPxBIN
0
0
1
iDIR
xDIR
1
QDECCTL:QBP
1
0
x1
x2
x1, x2
2
QDECCTL:XCR
QDECCTL:QSRC
QDECCTL:QIP
EQEPxIIN
0
0
QI
1
1
QDECCTL:IGATE
EQEPxSIN
0
QS
1
QDECCTL:QSP
QDECCTL:SPSEL
EQEPxIOUT
0
PCSOUT
EQEPxSOUT
1
QDECCTL:SPSEL
EQEPxIOE
0
QDECCTL:SOEN
EQEPxSOE
1
16.4.1 Position Counter Input Modes
Clock and direction input to the position counter is selected using QDECCTL[QSRC] bits, based on
interface input requirement as follows:
• Quadrature-count mode
• Direction-count mode
• UP-count mode
• DOWN-count mode
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2033
Quadrature Decoder Unit (QDU)
www.ti.com
16.4.1.1 Quadrature Count Mode
The quadrature decoder generates the direction and clock to the position counter in quadrature count
mode.
Direction Decoding— The direction decoding logic of the eQEP circuit determines which one of the
sequences (QEPA, QEPB) is the leading sequence and accordingly updates the direction
information in the QEPSTS[QDF] bit. Table 16-2 and Figure 16-6 show the direction decoding logic
in truth table and state machine form. Both edges of the QEPA and QEPB signals are sensed to
generate count pulses for the position counter. Therefore, the frequency of the clock generated by
the eQEP logic is four times that of each input sequence. Figure 16-7 shows the direction decoding
and clock generation from the eQEP input signals.
Table 16-2. Quadrature Decoder Truth Table
.
Previous Edge
Present Edge
QDIR
QPOSCNT
QA↑
QB↑
UP
Increment
QB↓
DOWN
Decrement
QA↓
TOGGLE
QB↓
UP
Increment
QB↑
DOWN
Decrement
QA↑
TOGGLE
QA↑
DOWN
Increment
QA↓
UP
Decrement
QB↓
TOGGLE
QA↓
DOWN
Increment
QA↑
UP
Decrement
QB↑
TOGGLE
QA↓
QB↑
QB↓
Increment or Decrement
Increment or Decrement
Increment or Decrement
Increment or Decrement
Figure 16-6. Quadrature Decoder State Machine
(A,B)=
(00)
Increment
counter
(11)
(10)
Increment
counter
10
(01)
Decrement
counter
QEPA
Decrement
counter
00
QEPB
11
Decrement
counter
Decrement
counter
01
eQEP signals
Increment
counter
2034
Enhanced Quadrature Encoder Pulse (eQEP)
Increment
counter
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Quadrature Decoder Unit (QDU)
www.ti.com
Figure 16-7. Quadrature-clock and Direction Decoding
QA
QB
QCLK
QDIR
QPOSCNT
+1 +1 +1 +1 +1 +1
+1
−1 −1 −1 −1 −1 −1 −1 −1 −1 −1
−1
+1 +1 +1
−1 −1 −1 −1 −1 −1
−1
+1 +1 +1 +1 +1 +1 +1 +1 +1 +1
+1
−1 −1 −1
QA
QB
QCLK
QDIR
QPOSCNT
Phase Error Flag— In normal operating conditions, quadrature inputs QEPA and QEPB will be 90
degrees out of phase. The phase error flag (PHE) is set in the QFLG register and the QPOSCNT
value can be incorrect and offset by multiples of 1 or 3. That is, when edge transition is detected
simultaneously on the QEPA and QEPB signals to optionally generate interrupts. State transitions
marked by dashed lines in Figure 16-6 are invalid transitions that generate a phase error.
Count Multiplication— The eQEP position counter provides 4x times the resolution of an input clock by
generating a quadrature-clock (QCLK) on the rising/falling edges of both eQEP input clocks (QEPA
and QEPB) as shown in Figure 16-7 .
Reverse Count— In normal quadrature count operation, QEPA input is fed to the QA input of the
quadrature decoder and the QEPB input is fed to the QB input of the quadrature decoder. Reverse
counting is enabled by setting the SWAP bit in the QDECCTL register. This will swap the input to
the quadrature decoder, thereby reversing the counting direction.
16.4.1.2 Direction-Count Mode
Some position encoders provide direction and clock outputs, instead of quadrature outputs. In such cases,
direction-count mode can be used. QEPA input will provide the clock for the position counter and the
QEPB input will have the direction information. The position counter is incremented on every rising edge
of a QEPA input when the direction input is high, and decremented when the direction input is low.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2035
Quadrature Decoder Unit (QDU)
www.ti.com
16.4.1.3 Up-Count Mode
The counter direction signal is hard-wired for up-count and the position counter is used to measure the
frequency of the QEPA input. Clearing the QDECCTL[XCR] bit enables clock generation to the position
counter on both edges of the QEPA input, thereby increasing the measurement resolution by a factor of
2x. In up-count mode, it is recommended that the application not configure QEPB as a GPIO mux option,
or ensure that a signal edge is not generated on the QEPB input.
16.4.1.4 Down-Count Mode
The counter direction signal is hardwired for a down-count and the position counter is used to measure the
frequency of the QEPA input. Setting the QDECCTL[XCR] bit enables clock generation to the position
counter on both edges of a QEPA input, thereby increasing the measurement resolution by a factor of 2x.
In down-count mode, it is recommended that the application not configure QEPB as a GPIO mux option,
or ensure that a signal edge is not generated on the QEPB input.
16.4.2 eQEP Input Polarity Selection
Each eQEP input can be inverted using QDECCTL[8:5] control bits. As an example, setting the
QDECCTL[QIP] bit will invert the index input.
16.4.3 Position-Compare Sync Output
The enhanced eQEP peripheral includes a position-compare unit that is used to generate the positioncompare sync signal on compare match between the position-counter register (QPOSCNT) and the
position- compare register (QPOSCMP). This sync signal can be output using an index pin or strobe pin of
the EQEP peripheral.
Setting the QDECCTL[SOEN] bit enables the position-compare sync output and the QDECCTL[SPSEL] bit
selects either an eQEP index pin or an eQEP strobe pin.
16.5 Position Counter and Control Unit (PCCU)
The position-counter and control unit provides two configuration registers (QEPCTL and QPOSCTL) for
setting up position-counter operational modes, position-counter initialization/latch modes and positioncompare logic for sync signal generation.
16.5.1 Position Counter Operating Modes
Position-counter data may be captured in different manners. In some systems, the position counter is
accumulated continuously for multiple revolutions and the position-counter value provides the position
information with respect to the known reference. An example of this is the quadrature encoder mounted on
the motor controlling the print head in the printer. Here the position counter is reset by moving the print
head to the home position and then the position counter provides absolute position information with
respect to home position.
In other systems, the position counter is reset on every revolution using index pulse, and the position
counter provides a rotor angle with respect to the index pulse position.
The position counter can be configured to operate in following four modes
• Position-Counter Reset on Index Event
• Position-Counter Reset on Maximum Position
• Position-Counter Reset on the first Index Event
• Position-Counter Reset on Unit Time Out Event (Frequency Measurement)
In all the above operating modes, the position counter is reset to 0 on overflow and to the QPOSMAX
register value on underflow. Overflow occurs when the position counter counts up after the QPOSMAX
value. Underflow occurs when the position counter counts down after "0". The Interrupt flag is set to
indicate overflow/underflow in QFLG register.
2036
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Position Counter and Control Unit (PCCU)
www.ti.com
16.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
If the index event occurs during the forward movement, then the position counter is reset to 0 on the next
eQEP. If the index event occurs during the reverse movement, then the position counter is reset to the
value in the QPOSMAX register on the next eQEP clock.
First index marker is defined as the quadrature edge following the first index edge. The eQEP peripheral
records the occurrence of the first index marker (QEPSTS[FIMF]) and direction on the first index event
marker (QEPSTS[FIDF]) in QEPSTS registers, it also remembers the quadrature edge on the first index
marker so that same relative quadrature transition is used for index event reset operation.
For example, if the first reset operation occurs on the falling edge of QEPB during the forward direction,
then all the subsequent reset must be aligned with the falling edge of QEPB for the forward rotation and
on the rising edge of QEPB for the reverse rotation as shown in Figure 16-8.
The position-counter value is latched to the QPOSILAT register and direction information is recorded in
the QEPSTS[QDLF] bit on every index event marker. The position-counter error flag (QEPSTS[PCEF])
and error interrupt flag (QFLG[PCE]) are set if the latched value is not equal to 0 or QPOSMAX. The
position-counter error flag (QEPSTS[PCEF]) is updated on every index event marker and an interrupt flag
(QFLG[PCE]) will be set on error that can be cleared only through software.
The index event latch configuration QEPCTL[IEL] must be configured to '00' or '11' when pcrm=0 and the
position counter error flag/interrupt flag are generated only in index event reset mode. The position
counter value is latched into the IPOSLAT register on every index marker.
Figure 16-8. Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or 0xF9F)
NOTE: In case of boundary condition where time period between Index Event and previous QCLK
edge is less than SYSCLK period, then QPOSCNT gets reset to zero or QPOSMAX in the
same SYSCLK cycle and does not wait for next QCLK edge to occur.
16.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
If the position counter is equal to QPOSMAX, then the position counter is reset to 0 on the next eQEP
clock for forward movement and position counter overflow flag is set. If the position counter is equal to
ZERO, then the position counter is reset to QPOSMAX on the next QEP clock for reverse movement and
position-counter underflow flag is set. Figure 16-9 shows the position-counter reset operation in this mode.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2037
Position Counter and Control Unit (PCCU)
www.ti.com
The first index marker fields (QEPSTS[FIDF] and QEPSTS[FIMF]) are not applicable in this mode.
Figure 16-9. Position Counter Underflow/Overflow (QPOSMAX = 4)
QA
QB
QCLK
QDIR
QPOSCNT
1
2
3
4
0
1
2
1
0
4
3
2
1
0
4
3
2
1
2
3
4
1
0
4
3
2
1
0
1
2
3
4
0
1
2
3
4
0
1
0
4
3
0
OV/UF
QA
QB
QCLK
QDIR
QPOSCNT
OV/UF
16.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
If the index event occurs during forward movement, then the position counter is reset to 0 on the next
eQEP clock. If the index event occurs during the reverse movement, then the position counter is reset to
the value in the QPOSMAX register on the next eQEP clock. Note that this is done only on the first
occurrence and subsequently the position-counter value is not reset on an index event; rather, it is reset
based on maximum position as described in Section 16.5.1.2.
The first index marker fields (QEPSTS[FIDF] and QEPSTS[FIMF]) are not applicable in this mode.
16.5.1.4 Position Counter Reset on Unit Time out Event (QEPCTL[PCRM] = 11)
In this mode, QPOSCNT is set to 0 or QPOMAX, depending on the direction mode selected by
QDECCTL[QSRC] bits on a unit time event. This is useful for frequency measurement.
16.5.2 Position Counter Latch
The eQEP index and strobe input can be configured to latch the position counter (QPOSCNT) into
QPOSILAT and QPOSSLAT, respectively, on occurrence of a definite event on these pins.
2038
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Position Counter and Control Unit (PCCU)
www.ti.com
16.5.2.1 Index Event Latch
In some applications, it may not be desirable to reset the position counter on every index event and
instead it may be required to operate the position counter in full 32-bit mode (QEPCTL[PCRM] = 01 and
QEPCTL[PCRM] = 10 modes).
In such cases, the eQEP position counter can be configured to latch on the following events and direction
information is recorded in the QEPSTS[QDLF] bit on every index event marker.
• Latch on Rising edge (QEPCTL[IEL]=01)
• Latch on Falling edge (QEPCTL[IEL]=10)
• Latch on Index Event Marker (QEPCTL[IEL]=11)
This is particularly useful as an error checking mechanism to check if the position counter accumulated
the correct number of counts between index events. As an example, the 1000-line encoder must count
4000 times when moving in the same direction between the index events.
The index event latch interrupt flag (QFLG[IEL]) is set when the position counter is latched to the
QPOSILAT register. The index event latch configuration bits (QEPCTZ[IEL]) are ignored when
QEPCTL[PCRM] = 00.
Latch on Rising Edge (QEPCTL[IEL]=01)— The position-counter value (QPOSCNT) is latched to the
QPOSILAT register on every rising edge of an index input.
Latch on Falling Edge (QEPCTL[IEL] = 10)— The position-counter value (QPOSCNT) is latched to the
QPOSILAT register on every falling edge of index input.
Latch on Index Event Marker/Software Index Marker (QEPCTL[IEL] = 11— The first index marker is
defined as the quadrature edge following the first index edge. The eQEP peripheral records the
occurrence of the first index marker (QEPSTS[FIMF]) and direction on the first index event marker
(QEPSTS[FIDF]) in the QEPSTS registers. It also remembers the quadrature edge on the first
index marker so that same relative quadrature transition is used for latching the position counter
(QEPCTL[IEL]=11).
Figure 16-10 shows the position counter latch using an index event marker.
Figure 16-10. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2039
Position Counter and Control Unit (PCCU)
www.ti.com
16.5.2.2 Strobe Event Latch
The position-counter value is latched to the QPOSSLAT register on the rising edge of the strobe input by
clearing the QEPCTL[SEL] bit.
If the QEPCTL[SEL] bit is set, then the position-counter value is latched to the QPOSSLAT register on the
rising edge of the strobe input for forward direction, and on the falling edge of the strobe input for reverse
direction as shown in Figure 16-11.
The strobe event latch interrupt flag (QFLG[SEL) is set when the position counter is latched to the
QPOSSLAT register.
Figure 16-11. Strobe Event Latch (QEPCTL[SEL] = 1)
QA
QB
QS
QCLK
QEPST:QDF
F9D
F9F
FA1
FA3
FA4
QPOSCNT F9C
FA2
FA0
F9E
F9C
F9A
F98
FA5
F9E
FA0
FA2
QIPOSSLAT
FA4
F97
FA3
FA1
F9F
F9F
F9D
F9B
F99
F9F
16.5.3 Position Counter Initialization
The position counter can be initialized using following events:
• Index event
• Strobe event
• Software initialization
Index Event Initialization (IEI)— The QEPI index input can be used to trigger the initialization of the
position counter at the rising or falling edge of the index input. If the QEPCTL[IEI] bits are 10, then
the position counter (QPOSCNT) is initialized with a value in the QPOSINIT register on the rising
edge of index input. Conversely, if the QEPCTL[IEI] bits are 11, initialization will be on the falling
edge of the index input.
Strobe Event Initialization (SEI)— If the QEPCTL[SEI] bits are 10, then the position counter is initialized
with a value in the QPOSINIT register on the rising edge of strobe input.
If QEPCTL[SEL] bits are 11, then the position counter is initialized with a value in the QPOSINIT
register on the rising edge of strobe input for forward direction and on the falling edge of strobe
input for reverse direction.
Software Initialization (SWI)— The position counter can be initialized in software by writing a 1 to the
QEPCTL[SWI] bit. This bit is not automatically cleared. While the bit is still set, if a 1 is written to it
again, the position counter will be re-initialized.
2040
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Position Counter and Control Unit (PCCU)
www.ti.com
16.5.4 eQEP Position-compare Unit
The eQEP peripheral includes a position-compare unit that is used to generate a sync output and/or
interrupt on a position-compare match. Figure 16-12 shows a diagram. The position-compare
(QPOSCMP) register is shadowed and shadow mode can be enabled or disabled using the
QPOSCTL[PSSHDW] bit. If the shadow mode is not enabled, the CPU writes directly to the active position
compare register.
Figure 16-12. eQEP Position-compare Unit
QPOSCTL:PCSHDW
QPOSCTL:PCLOAD
QPOSCMP
QFLG:PCR
QFLG:PCM
QPOSCTL:PCSPW
QPOSCTL:PCPOL
12
32
PCEVENT
Pulse
stretcher
0
PCSOUT
32
1
QPOSCNT
In shadow mode, you can configure the position-compare unit (QPOSCTL[PCLOAD]) to load the shadow
register value into the active register on the following events, and to generate the position-compare ready
(QFLG[PCR]) interrupt after loading.
• Load on compare match
• Load on position-counter zero event
The position-compare match (QFLG[PCM]) is set when the position-counter value (QPOSCNT) matches
with the active position-compare register (QPOSCMP) and the position-compare sync output of the
programmable pulse width is generated on compare-match to trigger an external device.
For example, if QPOSCMP = 2, the position-compare unit generates a position-compare event on 1 to 2
transitions of the eQEP position counter for forward counting direction and on 3 to 2 transitions of the
eQEP position counter for reverse counting direction (see Figure 16-13).
See the register section for the layout of the eQEP Position-Compare Control Register (QPOSCTL) and
description of the QPOSCTL bit fields.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2041
eQEP Edge Capture Unit
www.ti.com
Figure 16-13. eQEP Position-compare Event Generation Points
4
3
2
eQEP counter
4
3
3
2
1
1
0
3
2
2
1
POSCMP=2
1
0
0
PCEVNT
PCSOUT (active HIGH)
PCSPW
PCSOUT (active LOW)
The pulse stretcher logic in the position-compare unit generates a programmable position-compare sync
pulse output on the position-compare match. In the event of a new position-compare match while a
previous position-compare pulse is still active, then the pulse stretcher generates a pulse of specified
duration from the new position-compare event as shown in Figure 16-14.
Figure 16-14. eQEP Position-compare Sync Output Pulse Stretcher
DIR
QPOSCMP
QPOSCNT
PCEVNT
PCSPW
PCSPW
PCSPW
PCSOUT (active HIGH)
16.6 eQEP Edge Capture Unit
The eQEP peripheral includes an integrated edge capture unit to measure the elapsed time between the
unit position events as shown in Figure 16-15. This feature is typically used for low speed measurement
using the following equation:
X
v(k) +
+ X
t(k) * t(k * 1)
DT
(4)
where,
2042
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Edge Capture Unit
www.ti.com
•
•
•
X - Unit position is defined by integer multiple of quadrature edges (see Figure 16-16)
ΔT - Elapsed time between unit position events
v(k) - Velocity at time instant "k"
The eQEP capture timer (QCTMR) runs from prescaled SYSCLKOUT and the prescaler is programmed
by the QCAPCTL[CCPS] bits. The capture timer (QCTMR) value is latched into the capture period register
(QCPRD) on every unit position event and then the capture timer is reset, a flag is set in
QEPSTS:UPEVNT to indicate that new value is latched into the QCPRD register. Software can check this
status flag before reading the period register for low speed measurement, and clear the flag by writing 1.
Time measurement (ΔT) between unit position events will be correct if the following conditions are met:
• No more than 65,535 counts have occurred between unit position events.
• No direction change between unit position events.
The capture unit sets the eQEP overflow error flag (QEPSTS[COEF]) in the event of capture timer
overflow between unit position events. If a direction change occurs between the unit position events, then
an error flag is set in the status register (QEPSTS[CDEF]).
The Capture Timer (QCTMR) and Capture Period register (QCPRD) can be configured to latch on
following events.
• CPU read of QPOSCNT register
• Unit time-out event
If the QEPCTL[QCLM] bit is cleared, then the capture timer and capture period values are latched into the
QCTMRLAT and QCPRDLAT registers, respectively, when the CPU reads the position counter
(QPOSCNT).
If the QEPCTL[QCLM] bit is set, then the position counter, capture timer, and capture period values are
latched into the QPOSLAT, QCTMRLAT and QCPRDLAT registers, respectively, on unit time out.
Figure 16-17 shows the capture unit operation along with the position counter.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2043
eQEP Edge Capture Unit
www.ti.com
Figure 16-15. eQEP Edge Capture Unit
16
0xFFFF
QEPSTS:COEF
16
QCTMR
QCPRD
QCAPCTL:CCPS
16
3
3-bit binary
divider
x1, 1/2, 1/4...,
1/128
SYSCLKOUT
CAPCLK
16
Capture timer
control unit
(CTCU)
QCAPCTL:CEN
QCAPCTL:UPPS
QCTMRLAT
QCPRDLAT
QEPSTS:UPEVNT
UPEVNT
QEPSTS:CDEF
4
4-bit binary
divider
x1, 1/2, 1/4...,
1/2048
Rising/falling
edge detect
QCLK
QDIR
UTIME
QEPCTL:UTE
SYSCLKOUT
QFLG:UTO
QUTMR
UTOUT
QUPRD
NOTE:
The QCAPCTL[UPPS] prescaler should not be modified dynamically (such as switching the
unit event prescaler from QCLK/4 to QCLK/8). Doing so may result in undefined behavior.
The QCAPCTL[CPPS] prescaler can be modified dynamically (such as switching CAPCLK
prescaling mode from SYSCLK/4 to SYSCLK/8) only after the capture unit is disabled.
Figure 16-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)
P
QA
QB
QCLK
UPEVNT
X=N x P
A
2044
N - Number of quadrature periods selected using QCAPCTL[UPPS] bits
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Edge Capture Unit
www.ti.com
Figure 16-17. eQEP Edge Capture Unit - Timing Details
QEPA
QEPB
QCLK
QPOSCNT
x(k)
∆X
x(k−1)
UPEVNT
t(k)
∆T
QCTMR
t(k−1)
T
UTOUT
Velocity calculation equations:
x(k) * x(k * 1)
v(k) +
+ DX o
T
T
(5)
where
v(k): Velocity at time instant k
x(k): Position at time instant k
x(k-1): Position at time instant k-1
T: Fixed unit time or inverse of velocity calculation rate
ΔX: Incremental position movement in unit time
X: Fixed unit position
ΔT: Incremental time elapsed for unit position movement
t(k): Time instant "k"
t(k-1): Time instant "k-1"
Unit time (T) and unit period(X) are configured using the QUPRD and QCAPCTL[UPPS] registers.
Incremental position output and incremental time output is available in the QPOSLAT and QCPRDLAT
registers.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2045
eQEP Watchdog
www.ti.com
Parameter
T
ΔX
X
ΔT
Relevant Register to Configure or Read the Information
Unit Period Register (QUPRD)
Incremental Position = QPOSLAT(k) - QPOSLAT(K-1)
Fixed unit position defined by sensor resolution and ZCAPCTL[UPPS] bits
Capture Period Latch (QCPRDLAT)
16.7 eQEP Watchdog
The eQEP peripheral contains a 16-bit watchdog timer that monitors the quadrature-clock to indicate
proper operation of the motion-control system. The eQEP watchdog timer is clocked from
SYSCLKOUT/64 and the quadrate clock event (pulse) resets the watchdog timer. If no quadrature-clock
event is detected until a period match (QWDPRD = QWDTMR), then the watchdog timer will time out and
the watchdog interrupt flag will be set (QFLG[WTO]). The time-out value is programmable through the
watchdog period register (QWDPRD).
Figure 16-18. eQEP Watchdog Timer
QWDOG
QEPCTL:WDE
SYSCLKOUT
/64
SYSCLKOUT
QWDTMR
16
QCLK
RESET
WDTOUT
16
QWDPRD
QFLG:WTO
16.8 Unit Timer Base
The eQEP peripheral includes a 32-bit timer (QUTMR) that is clocked by SYSCLKOUT to generate
periodic interrupts for velocity calculations. Whenever the unit timer (QUTMR) matches the unit period
register (QUPRD), it resets the unit timer (QUPRD) it resets the unit timer (QUTMR) and also generates
the unit time out interrupt flag (QFLG[UTO]). The unit timer gets reset whenever timer value equals to
configured period value.
The eQEP peripheral can be configured to latch the position counter, capture timer, and capture period
values on a unit time out event so that latched values are used for velocity calculation as described in
Section 16.6.
2046
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Interrupt Structure
www.ti.com
Figure 16-19. eQEP Unit Time Base
UTIME
QEPCTL:UTE
SYSCLKOUT
QUTMR
32
UTOUT
32
QUPRD
QFLG:UTO
16.9 eQEP Interrupt Structure
Figure 16-20 shows how the interrupt mechanism works in the EQEP module.
Figure 16-20. EQEP Interrupt Generation
Set
Clr
Latch
QEINT:PCE
QCLR:INT
Clr
QFLG:INT
QCLR:PCE
Latch
Set
EQEPxINT
Pulse
generator
when
input=1
0
0
QFRC:PCE
PCE
QFLG:PCE
1
QEINT:UTO
clr
QCLR:UTO
Latch
set
QFRC:UTO
UTO
QFLG:UTO
Eleven interrupt events (PCE, PHE, QDC, WTO, PCU, PCO, PCR, PCM, SEL, IEL and UTO) can be
generated. The interrupt control register (QEINT) is used to enable/disable individual interrupt event
sources. The interrupt flag register (QFLG) indicates if any interrupt event has been latched and contains
the global interrupt flag bit (INT).
An Interrupt pulse is generated to PIE when:
a. Interrupt is enabled for eQEP event inside QEINT register
b. Interrupt flag for eQEP event inside QFLG register is set, and
c. Global interrupt status flag bit QFLG[INT] had been cleared for previously generated interrupt event.
The interrupt service routine will need to clear the global interrupt flag bit and the serviced event, via
the interrupt clear register (QCLR), before any other interrupt pulses are generated.If either flags inside
the QFLG register are not cleared, further interrupt event will not generate interrupt to PIE. You can
force an interrupt event by way of the interrupt force register (QFRC), which is useful for test purposes.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2047
eQEP Registers
www.ti.com
16.10 eQEP Registers
This section describes the Enhanced Quadrature Encoder Pulse Registers.
16.10.1 eQEP Base Addresses
Device Registers
2048
Register Name
Start Address
End Address
EQep1Regs
EQEP_REGS
0x0000_5100
0x0000_513F
EQep2Regs
EQEP_REGS
0x0000_5140
0x0000_517F
EQep3Regs
EQEP_REGS
0x0000_5180
0x0000_51BF
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
16.10.2 EQEP_REGS Registers
Table 16-3 lists the EQEP_REGS registers. All register offset addresses not listed in Table 16-3 should be
considered as reserved locations and the register contents should not be modified.
Table 16-3. EQEP_REGS Registers
Offset
Acronym
Register Name
0h
QPOSCNT
Position Counter
Write Protection
Section
Go
2h
QPOSINIT
Position Counter Init
Go
4h
QPOSMAX
Maximum Position Count
Go
6h
QPOSCMP
Position Compare
Go
8h
QPOSILAT
Index Position Latch
Go
Ah
QPOSSLAT
Strobe Position Latch
Go
Ch
QPOSLAT
Position Latch
Go
Eh
QUTMR
QEP Unit Timer
Go
10h
QUPRD
QEP Unit Period
Go
12h
QWDTMR
QEP Watchdog Timer
Go
13h
QWDPRD
QEP Watchdog Period
Go
14h
QDECCTL
Quadrature Decoder Control
Go
15h
QEPCTL
QEP Control
Go
16h
QCAPCTL
Qaudrature Capture Control
Go
17h
QPOSCTL
Position Compare Control
Go
18h
QEINT
QEP Interrupt Control
Go
19h
QFLG
QEP Interrupt Flag
Go
1Ah
QCLR
QEP Interrupt Clear
Go
1Bh
QFRC
QEP Interrupt Force
Go
1Ch
QEPSTS
QEP Status
Go
1Dh
QCTMR
QEP Capture Timer
Go
1Eh
QCPRD
QEP Capture Period
Go
1Fh
QCTMRLAT
QEP Capture Latch
Go
20h
QCPRDLAT
QEP Capture Period Latch
Go
Complex bit access types are encoded to fit into small table cells. Table 16-4 shows the codes that are
used for access types in this section.
Table 16-4. EQEP_REGS Access Type Codes
Access Type
Code
Description
R
R
Read
R-0
R
-0
Read
Returns 0s
W
W
Write
W1S
W
1S
Write
1 to set
Read Type
Write Type
Reset or Default Value
-n
Value after reset or the default
value
Register Array Variables
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2049
eQEP Registers
www.ti.com
Table 16-4. EQEP_REGS Access Type
Codes (continued)
Access Type
2050
Code
Description
i,j,k,l,m,n
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y
When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
16.10.2.1 QPOSCNT Register (Offset = 0h) [reset = 0h]
QPOSCNT is shown in Figure 16-21 and described in Table 16-5.
Return to the Summary Table.
Position Counter
Figure 16-21. QPOSCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QPOSCNT
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 16-5. QPOSCNT Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
QPOSCNT
R/W
0h
Position Counter
This 32-bit position counter register counts up/down on every eQEP
pulse based on direction input. This counter acts as a position
integrator whose count value is proportional to position from a give
reference point. This Register acts as a Read ONLY register while
counter is counting up/down.
Note: It is recommended to only write to the position counter register
(QPOSCNT) during initialization, i.e. when the eQEP position
counter is disabled (QPEN bit of QEPCTL is zero). Once the position
counter is enabled (QPEN bit is one), writing to the eQEP position
counter register (QPOSCNT) may cause unexpected results.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2051
eQEP Registers
www.ti.com
16.10.2.2 QPOSINIT Register (Offset = 2h) [reset = 0h]
QPOSINIT is shown in Figure 16-22 and described in Table 16-6.
Return to the Summary Table.
Position Counter Init
Figure 16-22. QPOSINIT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QPOSINIT
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 16-6. QPOSINIT Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
QPOSINIT
R/W
0h
Position Counter Init
This register contains the position value that is used to initialize the
position counter based on external strobe or index event. The
position counter can be initialized through software. Writes to this
register should always be full 32-bit writes.
Reset type: SYSRSn
2052
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
16.10.2.3 QPOSMAX Register (Offset = 4h) [reset = 0h]
QPOSMAX is shown in Figure 16-23 and described in Table 16-7.
Return to the Summary Table.
Maximum Position Count
Figure 16-23. QPOSMAX Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QPOSMAX
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 16-7. QPOSMAX Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
QPOSMAX
R/W
0h
Maximum Position Count
This register contains the maximum position counter value. Writes to
this register should always be full 32-bit writes.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2053
eQEP Registers
www.ti.com
16.10.2.4 QPOSCMP Register (Offset = 6h) [reset = 0h]
QPOSCMP is shown in Figure 16-24 and described in Table 16-8.
Return to the Summary Table.
Position Compare
Figure 16-24. QPOSCMP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QPOSCMP
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 16-8. QPOSCMP Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
QPOSCMP
R/W
0h
Position Compare
The position-compare value in this register is compared with the
position counter (QPOSCNT) to generate sync output and/or
interrupt on compare match.
Reset type: SYSRSn
2054
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
16.10.2.5 QPOSILAT Register (Offset = 8h) [reset = 0h]
QPOSILAT is shown in Figure 16-25 and described in Table 16-9.
Return to the Summary Table.
Index Position Latch
Figure 16-25. QPOSILAT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QPOSILAT
R-0h
9
8
7
6
5
4
3
2
1
0
Table 16-9. QPOSILAT Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
QPOSILAT
R
0h
Index Position Latch
The position-counter value is latched into this register on an index
event as defined by the QEPCTL[IEL] bits.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2055
eQEP Registers
www.ti.com
16.10.2.6 QPOSSLAT Register (Offset = Ah) [reset = 0h]
QPOSSLAT is shown in Figure 16-26 and described in Table 16-10.
Return to the Summary Table.
Strobe Position Latch
Figure 16-26. QPOSSLAT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QPOSSLAT
R-0h
9
8
7
6
5
4
3
2
1
0
Table 16-10. QPOSSLAT Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
QPOSSLAT
R
0h
Strobe Position Latch
The position-counter value is latched into this register on a strobe
event as defined by the QEPCTL[SEL] bits.
Reset type: SYSRSn
2056
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
16.10.2.7 QPOSLAT Register (Offset = Ch) [reset = 0h]
QPOSLAT is shown in Figure 16-27 and described in Table 16-11.
Return to the Summary Table.
Position Latch
Figure 16-27. QPOSLAT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QPOSLAT
R-0h
9
8
7
6
5
4
3
2
1
0
Table 16-11. QPOSLAT Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
QPOSLAT
R
0h
Position Latch
The position-counter value is latched into this register on a unit time
out event.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2057
eQEP Registers
www.ti.com
16.10.2.8 QUTMR Register (Offset = Eh) [reset = 0h]
QUTMR is shown in Figure 16-28 and described in Table 16-12.
Return to the Summary Table.
QEP Unit Timer
Figure 16-28. QUTMR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QUTMR
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 16-12. QUTMR Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
QUTMR
R/W
0h
QEP Unit Timer
This register acts as time base for unit time event generation. When
this timer value matches the unit time period value a unit time event
is generated.
Reset type: SYSRSn
2058
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
16.10.2.9 QUPRD Register (Offset = 10h) [reset = 0h]
QUPRD is shown in Figure 16-29 and described in Table 16-13.
Return to the Summary Table.
QEP Unit Period
Figure 16-29. QUPRD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
QUPRD
R/W-0h
9
8
7
6
5
4
3
2
1
0
Table 16-13. QUPRD Register Field Descriptions
Bit
31-0
Field
Type
Reset
Description
QUPRD
R/W
0h
QEP Unit Period
This register contains the period count for the unit timer to generate
periodic unit time events. These events latch the eQEP position
information at periodic intervals and optionally generate an interrupt.
Writes to this register should always be full 32-bit writes.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2059
eQEP Registers
www.ti.com
16.10.2.10 QWDTMR Register (Offset = 12h) [reset = 0h]
QWDTMR is shown in Figure 16-30 and described in Table 16-14.
Return to the Summary Table.
QEP Watchdog Timer
Figure 16-30. QWDTMR Register
15
14
13
12
11
10
9
8
3
2
1
0
QWDTMR
R/W-0h
7
6
5
4
QWDTMR
R/W-0h
Table 16-14. QWDTMR Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
QWDTMR
R/W
0h
QEP Watchdog Timer
This register acts as time base for the watchdog to detect motor
stalls. When this timer value matches with the watchdog's period
value a watchdog timeout interrupt is generated. This register is
reset upon edge transition in quadrature-clock indicating the motion.
Reset type: SYSRSn
2060
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
16.10.2.11 QWDPRD Register (Offset = 13h) [reset = 0h]
QWDPRD is shown in Figure 16-31 and described in Table 16-15.
Return to the Summary Table.
QEP Watchdog Period
Figure 16-31. QWDPRD Register
15
14
13
12
11
10
9
8
3
2
1
0
QWDPRD
R/W-0h
7
6
5
4
QWDPRD
R/W-0h
Table 16-15. QWDPRD Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
QWDPRD
R/W
0h
QEP Watchdog Period
This register contains the time-out count for the eQEP peripheral
watch dog timer.
When the watchdog timer value matches the watchdog period value,
a watchdog timeout interrupt is generated.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2061
eQEP Registers
www.ti.com
16.10.2.12 QDECCTL Register (Offset = 14h) [reset = 0h]
QDECCTL is shown in Figure 16-32 and described in Table 16-16.
Return to the Summary Table.
Quadrature Decoder Control
Figure 16-32. QDECCTL Register
15
14
13
SOEN
R/W-0h
12
SPSEL
R/W-0h
11
XCR
R/W-0h
10
SWAP
R/W-0h
9
IGATE
R/W-0h
8
QAP
R/W-0h
6
QIP
R/W-0h
5
QSP
R/W-0h
4
3
2
RESERVED
R-0h
1
0
QSRC
R/W-0h
7
QBP
R/W-0h
Table 16-16. QDECCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
15-14
QSRC
R/W
0h
Position-counter source selection
Reset type: SYSRSn
0h (R/W) = Quadrature count mode (QCLK = iCLK, QDIR = iDIR)
1h (R/W) = Direction-count mode (QCLK = xCLK, QDIR = xDIR)
2h (R/W) = UP count mode for frequency measurement (QCLK =
xCLK, QDIR = 1)
3h (R/W) = DOWN count mode for frequency measurement (QCLK
= xCLK, QDIR = 0)
13
SOEN
R/W
0h
Sync output-enable
Reset type: SYSRSn
0h (R/W) = Disable position-compare sync output
1h (R/W) = Enable position-compare sync output
12
SPSEL
R/W
0h
Sync output pin selection
Reset type: SYSRSn
0h (R/W) = Index pin is used for sync output
1h (R/W) = Strobe pin is used for sync output
11
XCR
R/W
0h
External Clock Rate
Reset type: SYSRSn
0h (R/W) = 2x resolution: Count the rising/falling edge
1h (R/W) = 1x resolution: Count the rising edge only
10
SWAP
R/W
0h
CLK/DIR Signal Source for Position Counter
Reset type: SYSRSn
0h (R/W) = Quadrature-clock inputs are not swapped
1h (R/W) = Quadrature-clock inputs are swapped
9
IGATE
R/W
0h
Index pulse gating option
Reset type: SYSRSn
0h (R/W) = Disable gating of Index pulse
1h (R/W) = Gate the index pin with strobe
8
QAP
R/W
0h
QEPA input polarity
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Negates QEPA input
7
QBP
R/W
0h
QEPB input polarity
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Negates QEPB input
2062
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
Table 16-16. QDECCTL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6
QIP
R/W
0h
QEPI input polarity
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Negates QEPI input
5
QSP
R/W
0h
QEPS input polarity
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Negates QEPS input
RESERVED
R
0h
Reserved
4-0
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2063
eQEP Registers
www.ti.com
16.10.2.13 QEPCTL Register (Offset = 15h) [reset = 0h]
QEPCTL is shown in Figure 16-33 and described in Table 16-17.
Return to the Summary Table.
QEP Control
Figure 16-33. QEPCTL Register
15
14
13
12
FREE_SOFT
R/W-0h
7
SWI
R/W-0h
6
SEL
R/W-0h
11
PCRM
R/W-0h
10
9
SEI
R/W-0h
5
4
IEL
R/W-0h
3
QPEN
R/W-0h
8
IEI
R/W-0h
2
QCLM
R/W-0h
1
UTE
R/W-0h
0
WDE
R/W-0h
Table 16-17. QEPCTL Register Field Descriptions
Field
Type
Reset
Description
15-14
Bit
FREE_SOFT
R/W
0h
Emulation mode
Reset type: SYSRSn
0h (R/W) = QPOSCNT behavior
Position counter stops immediately on emulation suspend
0h (R/W) = QWDTMR behavior
Watchdog counter stops immediately
0h (R/W) = QUTMR behavior
Unit timer stops immediately
0h (R/W) = QCTMR behavior
Capture Timer stops immediately
1h (R/W) = QPOSCNT behavior
Position counter continues to count until the rollover
1h (R/W) = QWDTMR behavior
Watchdog counter counts until WD period match roll over
1h (R/W) = QUTMR behavior
Unit timer counts until period rollover
1h (R/W) = QCTMR behavior
Capture Timer counts until next unit period event
2h (R/W) = QPOSCNT behavior
Position counter is unaffected by emulation suspend
2h (R/W) = QWDTMR behavior
Watchdog counter is unaffected by emulation suspend
2h (R/W) = QUTMR behavior
Unit timer is unaffected by emulation suspend
2h (R/W) = QCTMR behavior
Capture Timer is unaffected by emulation suspend
3h (R/W) = Same as FREE_SOFT_2
13-12
PCRM
R/W
0h
Postion counter reset
Reset type: SYSRSn
0h (R/W) = Position counter reset
1h (R/W) = Position counter reset
2h (R/W) = Position counter reset
3h (R/W) = Position counter reset
11-10
2064
SEI
R/W
Enhanced Quadrature Encoder Pulse (eQEP)
0h
on
on
on
on
an index event
the maximum position
the first index event
a unit time event
Strobe event initialization of position counter
Reset type: SYSRSn
0h (R/W) = Does nothing (action disabled)
1h (R/W) = Does nothing (action disabled)
2h (R/W) = Initializes the position counter on rising edge of the
QEPS signal
3h (R/W) = Clockwise Direction:
Initializes the position counter on the rising edge of QEPS strobe
Counter Clockwise Direction:
Initializes the position counter on the falling edge of QEPS strobe
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
Table 16-17. QEPCTL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
9-8
IEI
R/W
0h
Index event init of position count
Reset type: SYSRSn
0h (R/W) = Do nothing (action disabled)
1h (R/W) = Do nothing (action disabled)
2h (R/W) = Initializes the position counter on the rising edge of the
QEPI signal (QPOSCNT = QPOSINIT)
3h (R/W) = Initializes the position counter on the falling edge of
QEPI signal (QPOSCNT = QPOSINIT)
7
SWI
R/W
0h
Software init position counter
Reset type: SYSRSn
0h (R/W) = Do nothing (action disabled)
1h (R/W) = Initialize position counter (QPOSCNT=QPOSINIT). This
bit is not cleared automatically
6
SEL
R/W
0h
Strobe event latch of position counter
Reset type: SYSRSn
0h (R/W) = The position counter is latched on the rising edge of
QEPS strobe (QPOSSLAT = POSCCNT). Latching on the falling
edge can be done by inverting the strobe input using the QSP bit in
the QDECCTL register
1h (R/W) = Clockwise Direction:
Position counter is latched on rising edge of QEPS strobe
Counter Clockwise Direction:
Position counter is latched on falling edge of QEPS strobe
5-4
IEL
R/W
0h
Index event latch of position counter (software index marker)
Reset type: SYSRSn
0h (R/W) = Reserved
1h (R/W) = Latches position counter on rising edge of the index
signal
2h (R/W) = Latches position counter on falling edge of the index
signal
3h (R/W) = Software index marker. Latches the position counter
and quadrature direction flag on index event marker. The position
counter is latched to the QPOSILAT register and the direction flag
is latched in the QEPSTS[QDLF] bit. This mode is useful for
software index marking.
3
QPEN
R/W
0h
Quadrature position counter enable/software reset
Reset type: SYSRSn
0h (R/W) = Reset the eQEP peripheral internal operating
flags/read-only registers. Control/configuration registers are not
disturbed by a software reset.
When QPEN is disabled, some flags in the QFLG register do not
get reset or cleared and show the actual state of that flag.
1h (R/W) = eQEP position counter is enabled
2
QCLM
R/W
0h
QEP capture latch mode
Reset type: SYSRSn
0h (R/W) = Latch on position counter read by CPU. Capture timer
and capture period values are latched into QCTMRLAT and
QCPRDLAT registers when CPU reads the QPOSCNT register.
1h (R/W) = Latch on unit time out. Position counter, capture timer
and capture period values are latched into QPOSLAT, QCTMRLAT
and QCPRDLAT registers on unit time out.
1
UTE
R/W
0h
QEP unit timer enable
Reset type: SYSRSn
0h (R/W) = Disable eQEP unit timer
1h (R/W) = Enable unit timer
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2065
eQEP Registers
www.ti.com
Table 16-17. QEPCTL Register Field Descriptions (continued)
2066
Bit
Field
Type
Reset
Description
0
WDE
R/W
0h
QEP watchdog enable
Reset type: SYSRSn
0h (R/W) = Disable the eQEP watchdog timer
1h (R/W) = Enable the eQEP watchdog timer
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
16.10.2.14 QCAPCTL Register (Offset = 16h) [reset = 0h]
QCAPCTL is shown in Figure 16-34 and described in Table 16-18.
Return to the Summary Table.
Qaudrature Capture Control
Figure 16-34. QCAPCTL Register
15
CEN
R/W-0h
14
13
12
11
RESERVED
R-0h
10
7
RESERVED
R-0h
6
5
CCPS
R/W-0h
4
3
2
9
8
1
0
UPPS
R/W-0h
Table 16-18. QCAPCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
CEN
R/W
0h
Enable eQEP capture
Reset type: SYSRSn
0h (R/W) = eQEP capture unit is disabled
1h (R/W) = eQEP capture unit is enabled
14-7
RESERVED
R
0h
Reserved
6-4
CCPS
R/W
0h
eQEP capture timer clock prescaler
Reset type: SYSRSn
0h (R/W) = CAPCLK = SYSCLKOUT/1
1h (R/W) = CAPCLK = SYSCLKOUT/2
2h (R/W) = CAPCLK = SYSCLKOUT/4
3h (R/W) = CAPCLK = SYSCLKOUT/8
4h (R/W) = CAPCLK = SYSCLKOUT/16
5h (R/W) = CAPCLK = SYSCLKOUT/32
6h (R/W) = CAPCLK = SYSCLKOUT/64
7h (R/W) = CAPCLK = SYSCLKOUT/128
3-0
UPPS
R/W
0h
Unit position event prescaler
Reset type: SYSRSn
0h (R/W) = UPEVNT = QCLK/1
1h (R/W) = UPEVNT = QCLK/2
2h (R/W) = UPEVNT = QCLK/4
3h (R/W) = UPEVNT = QCLK/8
4h (R/W) = UPEVNT = QCLK/16
5h (R/W) = UPEVNT = QCLK/32
6h (R/W) = UPEVNT = QCLK/64
7h (R/W) = UPEVNT = QCLK/128
8h (R/W) = UPEVNT = QCLK/256
9h (R/W) = UPEVNT = QCLK/512
Ah (R/W) = UPEVNT = QCLK/1024
Bh (R/W) = UPEVNT = QCLK/2048
Ch (R/W) = Reserved
Dh (R/W) = Reserved
Eh (R/W) = Reserved
Fh (R/W) = Reserved
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2067
eQEP Registers
www.ti.com
16.10.2.15 QPOSCTL Register (Offset = 17h) [reset = 0h]
QPOSCTL is shown in Figure 16-35 and described in Table 16-19.
Return to the Summary Table.
Position Compare Control
Figure 16-35. QPOSCTL Register
15
PCSHDW
R/W-0h
14
PCLOAD
R/W-0h
13
PCPOL
R/W-0h
12
PCE
R/W-0h
7
6
5
4
11
10
9
8
1
0
PCSPW
R/W-0h
3
2
PCSPW
R/W-0h
Table 16-19. QPOSCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
PCSHDW
R/W
0h
Position compare of shadow enable
Reset type: SYSRSn
0h (R/W) = Shadow disabled, load Immediate
1h (R/W) = Shadow enabled
14
PCLOAD
R/W
0h
Position compare of shadow load
Reset type: SYSRSn
0h (R/W) = Load on QPOSCNT = 0
1h (R/W) = Load when QPOSCNT = QPOSCMP
13
PCPOL
R/W
0h
Polarity of sync output
Reset type: SYSRSn
0h (R/W) = Active HIGH pulse output
1h (R/W) = Active LOW pulse output
12
PCE
R/W
0h
Position compare enable/disable
Reset type: SYSRSn
0h (R/W) = Disable position compare unit
1h (R/W) = Enable position compare unit
PCSPW
R/W
0h
Select-position-compare sync output pulse width
Reset type: SYSRSn
0h (R/W) = 1 * 4 * SYSCLKOUT cycles
1h (R/W) = 2 * 4 * SYSCLKOUT cycles
FFFh (R/W) = 4096 * 4 * SYSCLKOUT cycles
11-0
2068
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
16.10.2.16 QEINT Register (Offset = 18h) [reset = 0h]
QEINT is shown in Figure 16-36 and described in Table 16-20.
Return to the Summary Table.
QEP Interrupt Control
Figure 16-36. QEINT Register
15
14
13
12
11
UTO
R/W-0h
10
IEL
R/W-0h
9
SEL
R/W-0h
8
PCM
R/W-0h
5
PCU
R/W-0h
4
WTO
R/W-0h
3
QDC
R/W-0h
2
QPE
R/W-0h
1
PCE
R/W-0h
0
RESERVED
R-0h
RESERVED
R-0h
7
PCR
R/W-0h
6
PCO
R/W-0h
Table 16-20. QEINT Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
11
UTO
R/W
0h
Unit time out interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled
10
IEL
R/W
0h
Index event latch interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled
9
SEL
R/W
0h
Strobe event latch interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled
8
PCM
R/W
0h
Position-compare match interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled
7
PCR
R/W
0h
Position-compare ready interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled
6
PCO
R/W
0h
Position counter overflow interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled
5
PCU
R/W
0h
Position counter underflow interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled
4
WTO
R/W
0h
Watchdog time out interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled
15-12
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2069
eQEP Registers
www.ti.com
Table 16-20. QEINT Register Field Descriptions (continued)
2070
Bit
Field
Type
Reset
Description
3
QDC
R/W
0h
Quadrature direction change interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled
2
QPE
R/W
0h
Quadrature phase error interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled
1
PCE
R/W
0h
Position counter error interrupt enable
Reset type: SYSRSn
0h (R/W) = Interrupt is disabled
1h (R/W) = Interrupt is enabled
0
RESERVED
R
0h
Reserved
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
16.10.2.17 QFLG Register (Offset = 19h) [reset = 0h]
QFLG is shown in Figure 16-37 and described in Table 16-21.
Return to the Summary Table.
QEP Interrupt Flag
Figure 16-37. QFLG Register
15
14
13
12
11
UTO
R-0h
10
IEL
R-0h
9
SEL
R-0h
8
PCM
R-0h
5
PCU
R-0h
4
WTO
R-0h
3
QDC
R-0h
2
PHE
R-0h
1
PCE
R-0h
0
INT
R-0h
RESERVED
R-0h
7
PCR
R-0h
6
PCO
R-0h
Table 16-21. QFLG Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
11
UTO
R
0h
Unit time out interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated
10
IEL
R
0h
Index event latch interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated
9
SEL
R
0h
Strobe event latch interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated
8
PCM
R
0h
eQEP compare match event interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated
7
PCR
R
0h
Position-compare ready interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated
6
PCO
R
0h
Position counter overflow interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated
5
PCU
R
0h
Position counter underflow interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated
4
WTO
R
0h
Watchdog timeout interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated
15-12
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2071
eQEP Registers
www.ti.com
Table 16-21. QFLG Register Field Descriptions (continued)
2072
Bit
Field
Type
Reset
Description
3
QDC
R
0h
Quadrature direction change interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated
2
PHE
R
0h
Quadrature phase error interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated
1
PCE
R
0h
Position counter error interrupt flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated
0
INT
R
0h
Global interrupt status flag
Reset type: SYSRSn
0h (R/W) = No interrupt generated
1h (R/W) = Interrupt was generated
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
16.10.2.18 QCLR Register (Offset = 1Ah) [reset = 0h]
QCLR is shown in Figure 16-38 and described in Table 16-22.
Return to the Summary Table.
QEP Interrupt Clear
Figure 16-38. QCLR Register
15
14
13
12
11
UTO
R-0/W1S-0h
10
IEL
R-0/W1S-0h
9
SEL
R-0/W1S-0h
8
PCM
R-0/W1S-0h
5
PCU
R-0/W1S-0h
4
WTO
R-0/W1S-0h
3
QDC
R-0/W1S-0h
2
PHE
R-0/W1S-0h
1
PCE
R-0/W1S-0h
0
INT
R-0/W1S-0h
RESERVED
R-0h
7
PCR
R-0/W1S-0h
6
PCO
R-0/W1S-0h
Table 16-22. QCLR Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
11
UTO
R-0/W1S
0h
Clear unit time out interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag
10
IEL
R-0/W1S
0h
Clear index event latch interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag
9
SEL
R-0/W1S
0h
Clear strobe event latch interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag
8
PCM
R-0/W1S
0h
Clear eQEP compare match event interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag
7
PCR
R-0/W1S
0h
Clear position-compare ready interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag
6
PCO
R-0/W1S
0h
Clear position counter overflow interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag
5
PCU
R-0/W1S
0h
Clear position counter underflow interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag
4
WTO
R-0/W1S
0h
Clear watchdog timeout interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag
15-12
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2073
eQEP Registers
www.ti.com
Table 16-22. QCLR Register Field Descriptions (continued)
2074
Bit
Field
Type
Reset
Description
3
QDC
R-0/W1S
0h
Clear quadrature direction change interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag
2
PHE
R-0/W1S
0h
Clear quadrature phase error interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag
1
PCE
R-0/W1S
0h
Clear position counter error interrupt flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag
0
INT
R-0/W1S
0h
Global interrupt clear flag
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Clears the interrupt flag
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
16.10.2.19 QFRC Register (Offset = 1Bh) [reset = 0h]
QFRC is shown in Figure 16-39 and described in Table 16-23.
Return to the Summary Table.
QEP Interrupt Force
Figure 16-39. QFRC Register
15
14
13
12
11
UTO
R/W-0h
10
IEL
R/W-0h
9
SEL
R/W-0h
8
PCM
R/W-0h
5
PCU
R/W-0h
4
WTO
R/W-0h
3
QDC
R/W-0h
2
PHE
R/W-0h
1
PCE
R/W-0h
0
RESERVED
R-0h
RESERVED
R-0h
7
PCR
R/W-0h
6
PCO
R/W-0h
Table 16-23. QFRC Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
11
UTO
R/W
0h
Force unit time out interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt
10
IEL
R/W
0h
Force index event latch interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt
9
SEL
R/W
0h
Force strobe event latch interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt
8
PCM
R/W
0h
Force position-compare match interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt
7
PCR
R/W
0h
Force position-compare ready interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt
6
PCO
R/W
0h
Force position counter overflow interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt
5
PCU
R/W
0h
Force position counter underflow interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt
4
WTO
R/W
0h
Force watchdog time out interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt
15-12
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2075
eQEP Registers
www.ti.com
Table 16-23. QFRC Register Field Descriptions (continued)
2076
Bit
Field
Type
Reset
Description
3
QDC
R/W
0h
Force quadrature direction change interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt
2
PHE
R/W
0h
Force quadrature phase error interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt
1
PCE
R/W
0h
Force position counter error interrupt
Reset type: SYSRSn
0h (R/W) = No effect
1h (R/W) = Force the interrupt
0
RESERVED
R
0h
Reserved
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
16.10.2.20 QEPSTS Register (Offset = 1Ch) [reset = 0h]
QEPSTS is shown in Figure 16-40 and described in Table 16-24.
Return to the Summary Table.
QEP Status
Figure 16-40. QEPSTS Register
15
14
13
12
11
10
9
8
3
COEF
R/W-0h
2
CDEF
R/W-0h
1
FIMF
R/W-0h
0
PCEF
R-0h
RESERVED
R-0h
7
UPEVNT
R/W-0h
6
FIDF
R-0h
5
QDF
R-0h
4
QDLF
R-0h
Table 16-24. QEPSTS Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
7
UPEVNT
R/W
0h
Unit position event flag
Reset type: SYSRSn
0h (R/W) = No unit position event detected
1h (R/W) = Unit position event detected. Write 1 to clear
6
FIDF
R
0h
Direction on the first index marker
15-8
Status of the direction is latched on the first index event marker.
Reset type: SYSRSn
0h (R/W) = Counter-clockwise rotation (or reverse movement) on
the first index event
1h (R/W) = Clockwise rotation (or forward movement) on the first
index event
5
QDF
R
0h
Quadrature direction flag
Reset type: SYSRSn
0h (R/W) = Counter-clockwise rotation (or reverse movement)
1h (R/W) = Clockwise rotation (or forward movement)
4
QDLF
R
0h
eQEP direction latch flag
Reset type: SYSRSn
0h (R/W) = Counter-clockwise rotation (or reverse movement) on
index event marker
1h (R/W) = Clockwise rotation (or forward movement) on index
event marker
3
COEF
R/W
0h
Capture overflow error flag
Reset type: SYSRSn
0h (R/W) = Overflow has not occurred.
1h (R/W) = Overflow occurred in eQEP Capture timer (QEPCTMR).
2
CDEF
R/W
0h
Capture direction error flag
Reset type: SYSRSn
0h (R/W) = Capture direction error has not occurred.
1h (R/W) = Direction change occurred between the capture
position event.
1
FIMF
R/W
0h
First index marker flag
Note: Once this flag has been set, if the flag is cleared the flag will
not be set again until the module is reset by a peripheral or system
reset.
Reset type: SYSRSn
0h (R/W) = First index pulse has not occurred.
1h (R/W) = Set by first occurrence of index pulse.
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2077
eQEP Registers
www.ti.com
Table 16-24. QEPSTS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
PCEF
R
0h
Position counter error flag.
This bit is not sticky and it is updated for every index event.
Reset type: SYSRSn
0h (R/W) = No error occurred during the last index transition
1h (R/W) = Position counter error
2078
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
16.10.2.21 QCTMR Register (Offset = 1Dh) [reset = 0h]
QCTMR is shown in Figure 16-41 and described in Table 16-25.
Return to the Summary Table.
QEP Capture Timer
Figure 16-41. QCTMR Register
15
14
13
12
11
10
9
8
3
2
1
0
QCTMR
R/W-0h
7
6
5
4
QCTMR
R/W-0h
Table 16-25. QCTMR Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
QCTMR
R/W
0h
This register provides time base for edge capture unit.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2079
eQEP Registers
www.ti.com
16.10.2.22 QCPRD Register (Offset = 1Eh) [reset = 0h]
QCPRD is shown in Figure 16-42 and described in Table 16-26.
Return to the Summary Table.
QEP Capture Period
Figure 16-42. QCPRD Register
15
14
13
12
11
10
9
8
3
2
1
0
QCPRD
R/W-0h
7
6
5
4
QCPRD
R/W-0h
Table 16-26. QCPRD Register Field Descriptions
Bit
15-0
2080
Field
Type
Reset
Description
QCPRD
R/W
0h
This register holds the period count value between the last
successive eQEP position events
Reset type: SYSRSn
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
16.10.2.23 QCTMRLAT Register (Offset = 1Fh) [reset = 0h]
QCTMRLAT is shown in Figure 16-43 and described in Table 16-27.
Return to the Summary Table.
QEP Capture Latch
Figure 16-43. QCTMRLAT Register
15
14
13
12
11
10
9
8
3
2
1
0
QCTMRLAT
R-0h
7
6
5
4
QCTMRLAT
R-0h
Table 16-27. QCTMRLAT Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
QCTMRLAT
R
0h
The eQEP capture timer value can be latched into this register on
two events viz., unit timeout event, reading the eQEP position
counter.
Reset type: SYSRSn
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP)
Copyright © 2014–2019, Texas Instruments Incorporated
2081
eQEP Registers
www.ti.com
16.10.2.24 QCPRDLAT Register (Offset = 20h) [reset = 0h]
QCPRDLAT is shown in Figure 16-44 and described in Table 16-28.
Return to the Summary Table.
QEP Capture Period Latch
Figure 16-44. QCPRDLAT Register
15
14
13
12
11
10
9
8
3
2
1
0
QCPRDLAT
R-0h
7
6
5
4
QCPRDLAT
R-0h
Table 16-28. QCPRDLAT Register Field Descriptions
Bit
15-0
2082
Field
Type
Reset
Description
QCPRDLAT
R
0h
eQEP capture period value can be latched into this register on two
events viz., unit timeout event, reading the eQEP position counter.
Reset type: SYSRSn
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
16.10.3 Register to Driverlib Function Mapping
Table 16-29. EQEP Registers to Driverlib Functions
File
Driverlib Function
QPOSCNT
eqep.h
EQEP_getPosition
eqep.h
EQEP_setPosition
QPOSINIT
eqep.h
EQEP_setInitialPosition
QPOSMAX
eqep.h
EQEP_setPositionCounterConfig
QPOSCMP
eqep.c
EQEP_setCompareConfig
QPOSILAT
eqep.h
EQEP_getIndexPositionLatch
QPOSSLAT
eqep.h
EQEP_getStrobePositionLatch
QPOSLAT
eqep.h
EQEP_getPositionLatch
QUPRD
eqep.h
EQEP_loadUnitTimer
eqep.h
EQEP_enableUnitTimer
QWDTMR
eqep.h
EQEP_setWatchdogTimerValue
eqep.h
EQEP_getWatchdogTimerValue
QWDPRD
eqep.h
EQEP_enableWatchdog
QDECCTL
eqep.c
EQEP_setCompareConfig
eqep.c
EQEP_setInputPolarity
eqep.h
EQEP_setDecoderConfig
QEPCTL
eqep.h
EQEP_enableModule
eqep.h
EQEP_disableModule
eqep.h
EQEP_setPositionCounterConfig
eqep.h
EQEP_enableUnitTimer
eqep.h
EQEP_disableUnitTimer
eqep.h
EQEP_enableWatchdog
eqep.h
EQEP_disableWatchdog
eqep.h
EQEP_setPositionInitMode
eqep.h
EQEP_setSWPositionInit
eqep.h
EQEP_setLatchMode
eqep.h
EQEP_setEmulationMode
QCAPCTL
eqep.h
EQEP_setCaptureConfig
eqep.h
EQEP_enableCapture
eqep.h
EQEP_disableCapture
QPOSCTL
eqep.c
EQEP_setCompareConfig
eqep.h
EQEP_enableCompare
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Enhanced Quadrature Encoder Pulse (eQEP) 2083
Copyright © 2014–2019, Texas Instruments Incorporated
eQEP Registers
www.ti.com
Table 16-29. EQEP Registers to Driverlib Functions (continued)
File
Driverlib Function
eqep.h
EQEP_disableCompare
eqep.h
EQEP_setComparePulseWidth
QEINT
eqep.h
EQEP_enableInterrupt
eqep.h
EQEP_disableInterrupt
QFLG
eqep.h
EQEP_getInterruptStatus
eqep.h
EQEP_getError
QCLR
eqep.h
EQEP_clearInterruptStatus
QFRC
eqep.h
EQEP_forceInterrupt
QEPSTS
eqep.h
EQEP_getDirection
eqep.h
EQEP_getStatus
eqep.h
EQEP_clearStatus
QCTMR
eqep.h
EQEP_getCaptureTimer
eqep.h
EQEP_getCaptureTimerLatch
QCPRD
eqep.h
EQEP_getCapturePeriod
eqep.h
EQEP_getCapturePeriodLatch
QCTMRLAT
eqep.h
EQEP_getCaptureTimerLatch
QCPRDLAT
eqep.h
2084
EQEP_getCapturePeriodLatch
Enhanced Quadrature Encoder Pulse (eQEP)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Chapter 17
SPRUHM9F – October 2014 – Revised September 2019
Serial Peripheral Interface (SPI)
This chapter describes the serial peripheral interface (SPI) which is a high-speed synchronous serial input
and output (I/O) port that allows a serial bit stream of programmed length (one to 16 bits) to be shifted into
and out of the device at a programmed bit-transfer rate. The SPI is normally used for communications
between the MCU controller and external peripherals or another controller. Typical applications include
external I/O or peripheral expansion via devices such as shift registers, display drivers, and analog-todigital converters (ADCs). Multi-device communications are supported by the master or slave operation of
the SPI. The port supports a 16-level, receive and transmit FIFO for reducing CPU servicing overhead.
Topic
17.1
17.2
17.3
17.4
17.5
...........................................................................................................................
Introduction ...................................................................................................
System-Level Integration .................................................................................
SPI Operation .................................................................................................
Programming Procedure ..................................................................................
SPI Registers..................................................................................................
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Page
2086
2087
2090
2100
2105
Serial Peripheral Interface (SPI)
2085
Introduction
www.ti.com
17.1 Introduction
17.1.1 Features
The SPI module features include:
• SPISOMI: SPI slave-output/master-input pin
• SPISIMO: SPI slave-input/master-output pin
• SPISTE: SPI slave transmit-enable pin
• SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO if the SPI module is not used.
•
•
•
•
•
•
•
•
•
•
•
•
17.1.2
Two operational modes: Master and Slave
Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited
by the maximum speed of the I/O buffers used on the SPI pins. See the device-specific data manual
for more details.
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt- driven or polled
algorithm
16-level transmit/receive FIFO
DMA support
High-speed mode
Delayed transmit control
3-wire SPI mode
SPISTE inversion for digital audio interface receive mode on devices with two SPI modules
Block Diagram
Figure 17-1 shows the SPI CPU interfaces.
2086
Serial Peripheral Interface (SPI)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System-Level Integration
www.ti.com
Figure 17-1. SPI CPU Interface
PCLKCR8
LSPCLK
Low-Speed
Prescaler
SYSCLK
CPU
Bit Clock
Peripheral Bus
SYSRS
SPISIMO
SPISOMI
SPI
GPIO MUX
SPICLK
SPIINT
PIE
SPITXINT
SPISTE
SPIRXDMA
DMA
SPITXDMA
17.2 System-Level Integration
This section describes the various functionality that is applicable to the device integration. These features
require configuration of other modules in the device that are not within the scope of this chapter.
17.2.1 SPI Module Signals
Table 17-1 classifies and provides a summary of the SPI module signals.
Table 17-1. SPI Module Signal Summary
Signal Name
Description
External Signals
SPICLK
SPI clock
SPISIMO
SPI slave in, master out
SPISOMI
SPI slave out, master in
SPISTE
SPI slave transmit enable
Control
SPI Clock Rate
LSPCLK
Interrupt Signals
SPIINT/SPIRXINT
Transmit interrupt/ Receive Interrupt in non FIFO mode (referred to as SPIINT)
Receive interrupt in FIFO mode
SPITXINT
Transmit interrupt in FIFO mode
DMA Triggers
SPITXDMA
Transmit request to DMA
SPIRXDMA
Receive request to DMA
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Serial Peripheral Interface (SPI)
2087
System-Level Integration
www.ti.com
Special Considerations
The SPISTE signal provides the ability to gate any spurious clock and data pulses when the SPI is in
slave mode. An active SPISTE will not allow the slave to receive data. This prevents the SPI slave from
losing synchronization with the master. It is this reason that TI does not recommend that the SPISTE
always be tied to the active state.
If the SPI slave does ever lose synchronization with the master, toggling SPISWRESET will reset internal
bit counter as well as the various status flags in the module. By resetting the bit counter, the SPI will
interpret the next clock transition as the first bit of a new transmission. The register bit fields which are
reset by SPISWRESET can be found in Section 17.5
Configuring a GPIO to emulate SPISTE
In many systems, a SPI master may be connected to multiple SPI slaves using multiple instances of
SPISTE. Though this SPI module does not natively support multiple SPISTE signals, it is possible to
emulate this behavior in software using GPIOs. In this configuration, the SPI must be configured as the
master. Rather than using the GPIO Mux to select SPISTE, the application would configure pins to be
GPIO outputs, one GPIO per SPI slave. Before transmitting any data, the application would drive the
desired GPIO to the active state. Immediately after the transmission has been completed, the GPIO chip
select would be driven to the inactive state. This process can be repeated for many slaves which share
the SPICLK, SPISIMO, and SPISOMI lines.
17.2.2 Configuring Device Pins
The GPIO mux registers must be configured to connect this peripheral to the device pins. To avoid
glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding
GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value.
Some IO functionality is defined by GPIO register settings independent of this peripheral. For input
signals, the GPIO input qualification should be set to asynchronous mode by setting the appropriate
GPxQSELn register bits to 11b. The internal pullups can be configured in the GPyPUD register.
See the GPIO chapter for more details on GPIO mux and settings.
17.2.2.1 GPIOs Required for High-Speed Mode
The high-speed mode of the SPI is available on the specified GPIO mux options in the device datasheet.
To enable the high-speed enhancements, set SPICCR.HS_MODE to 1. Ensure that the capacitive loading
on the pin does not exceed the value stated in the device Data Manual.
When not operating in high-speed mode, or if the capacitive loading on the pins exceed the value stated in
the device Data Manual, SPICCR.HS_MODE should be set to 0.
17.2.3 SPI Interrupts
This section includes information on the available interrupts present in the SPI module.
The SPI module contains two interrupt lines: SPIINT/SPIRXINT and SPITXINT. When the SPI is operating
in non-FIFO mode, all available interrupts are routed together to generate the single SPIINT interrupt.
When FIFO mode is used, both SPIRXINT and SPITXINT can be generated.
SPIINT/SPIRXINT
When the SPI is operating in non-FIFO mode, the interrupt generated is called SPIINT. If FIFO
enhancements are enabled, the interrupt is called SPIRXINT. These interrupts share the same interrupt
vector in the Peripheral Interrupt Expansion (PIE) block.
In non-FIFO mode, two conditions can trigger an interrupt: a transmission is complete (INT_FLAG), or
there is overrun in the receiver (OVERRUN_FLAG). Both of these conditions share the same interrupt
vector: SPIINT.
The transmission complete flag (INT_FLAG) indicates that the SPI has completed sending or receiving the
last bit and is ready to be serviced. At the same time this bit is set, the received character is placed in the
receiver buffer (SPIRXBUF). The INT_FLAG will generate an interrupt on the SPIINT vector if the
SPIINTENA bit is set.
2088
Serial Peripheral Interface (SPI)
SPRUHM9F – October 2014 – Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
System-Level Integration
www.ti.com
The receiver overrun flag (OVERRUN_FLAG) indicates that a transmit or receive operation has completed
before the previous character has been read from the buffer. The OVERRUN_FLAG will generate an
interrupt on the SPIINT vector if the OVERRUNINTENA bit is set and OVERRUN_FLAG was previously
cleared.
In FIFO mode, the SPI can interrupt the CPU upon a match condition between the current receive FIFO
status (RXFFST) and the receive FIFO interrupt level (RXFFIL). If RXFFST is greater than or equal to
RXFFIL, the receive FIFO interrupt flag (RXFFINT) will be set. SPIRXINT will be triggered in the PIE block
if RXFFINT is set and the receive FIFO interrupt is enabled (RXFFIENA = 1).
SPITXINT
The SPITXINT interrupt is not available when the SPI is operating in non-FIFO mode.
In FIFO mode, the SPITXINT behavior is similar to the SPIRXINT. SPITXINT is generated upon a match
condition between the current transmit FIFO status (TXFFST) and the transmit FIFO interrupt level
(TXFFIL). If TXFFST is less than or equal to TXFFIL, the transmit FIFO interrupt flag (TXFFINT) will be
set. SPITXINT will be triggered in the PIE block if TXFFINT is set and the transmit FIFO interrupt is
enabled in the SPI module (TXFFIENA = 1).
Figure 17-2 and Table 17-2 show how these control bits influence the SPI interrupt generation.
Figure 17-2. SPI Interrupt Flags and Enable Logic Generation
RXFFOVF
16
RX FIFO_15
…
RX FIFO_1
RX FIFO_0
>?
RXFFIENA
RXFFST
=?
RXFFIL
1
SPIRXINT
0
OVRNINTENA
SPISOMI
SPISIMO
SPIRXBUF
SPIDAT
SPITXBUF
OVERRUN_FLAG
SPIFFENA
INT_FLAG
SPIINTENA
TX FIFO_0
TX FIFO_1
...
TX FIFO_15
TXFFST
工商网监
湘ICP备2023018690号
