TMP100MDBVREP

TMP100−EP DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE SGLS254B − JULY 2005 − REVISED OCTOBER 2013 D Controlled Baseline D Low Quiescent Current: 45 mA, 0.1-mA D D Wide Supply Range: 2.7 V to 5.5 V D Small SOT23-6 Package D D D D D † − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† Digital Output: I2C Serial 2-Wire Resolution: 9- to 12-Bits, User Selectable Accuracy: +25C from −255C to +855C (MAX), +35C from −555C to +1255C (MAX) Standby applications D D D D D D D Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. Power-Supply Temperature Monitoring Computer Peripheral Thermal Protection Notebook Computers Battery Management Thermostat Controls Environmental Monitoring Electromechanical Device Temperature DBV PACKAGE (TOP VIEW) description/ordering information SCL GND ADD1 The TMP100 and TMP101 are 2-wire, serial output temperature sensors available in SOT23−6 packages. Requiring no external components, the TMP100 and TMP101 are capable of reading temperatures with a resolution of 0.0625°C. 1 6 2 5 3 4 SDA ADD0 V+ TMP100 The TMP100 and TMP101 feature SMBus and I2C™ interface compatibility, with the TMP100 allowing up to eight devices on one bus. The TMP100 and TMP101 are ideal for extended temperature measurement in a variety of communication, computer, consumer, environmental, industrial, and instrumentation applications. The TMP100M and TMP101M are specified for operation over a temperature range of −55°C to +125°C. ORDERING INFORMATION −55°C to 125°C ORDERABLE PART NUMBER PACKAGE† TA SOT23-6 (DBV) Reel of 3000 TMP100MDBVREP TOP-SIDE MARKING 100E † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ Product Preview This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a registered trademark of Philips Incorporated. Copyright © 2004 Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TMP100−EP DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE SGLS254B − JULY 2005 − REVISED OCTOBER 2013 functional block diagram Temperature SCL 1 2 GND Diode Temp. Sensor ΔΣ A/D Converter 3 ADD1 Control Logic 6 Serial Interface 5 Config. and Temp. Register OSC SDA ADD0 4 V+ TMP100 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −60°C to 150°C Maximum Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Thermal impedance, θJA (See Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W Lead temperature soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The thermal impedance, θJA, for the DBV package is determined for JEDEC high−K PCB (JESD 51−7). recommended operating conditions MIN NOM MAX UNIT Supply voltage, V+ 2.7 5.5 V Operating free-air temperature, TA −55 125 °C electrical characteristics over recommended operating free-air temperature range, VDD = 2.7 V to 5.5 V (unless otherwise noted) temperature input PARAMETER TEST CONDITIONS Range Accuracy (temperature error) Resolution 2 MIN TYP −55 −25°C to 85°C −55°C to 125°C Selectable POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT 125 °C ±0.5 ±2 ±1 ±3 ±0.0625 °C °C TMP100−EP DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE SGLS254B − JULY 2005 − REVISED OCTOBER 2013 digital input/output PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage 0.7(V+) (V+) + 0.5 V VIL Low-level input voltage −0.5 0.3(V+) V IIN Input current 1 μA VOL Low level output voltage Low-level Resolution Conversion time Conversion rate VIN = 0 V to 6 V IOL = 3 mA SDA 0 0.15 0.4 IOL = 4 mA ALERT 0 0.15 0.4 Selectable 9 to 12 V bits 9-bit 40 75 10-bit 80 150 11-bit 160 300 12-bit 320 600 9-bit 25 10-bit 12 11-bit 6 12-bit 3 ms s/s power supply PARAMETER TEST CONDITIONS Serial bus inactive IQ Quiescent current Q Serial bus active Shutdown current Serial bus active POST OFFICE BOX 655303 TYP MAX 45 75 SCL = 400 kHz 70 SCL = 3.4 MHz 150 Serial bus inactive ISD MIN 0.1 SCL = 400 kHz 20 SCL = 3.4 MHz 100 • DALLAS, TEXAS 75265 UNIT μA μ 1 μA μ 3 TMP100−EP DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE SGLS254B − JULY 2005 − REVISED OCTOBER 2013 APPLICATION INFORMATION The TMP100 and TMP101 are digital temperature sensors optimal for thermal management and thermal protection applications. The TMP100 and TMP101 are I2C and SMBus interface compatible and are specified over a temperature range of −55°C to +125°C. The TMP100 and TMP101 require no external components for operation except for pullup resistors on SCL, SDA, and ALERT although a 0.1-μF bypass capacitor is recommended, as shown in Figure 1. V+ 0.1 μF 4 I2C To Controller SCL 1 SDA 6 3 ADD1 (Input) 5 ADD0 (Input) TMP100 2 GND NOTE 2: SCL and SDA require pullup resistors for I2C bus applications. Figure 1. Typical Connections of the TMP100 The die flag of the lead frame is connected to pin 2. The sensing device of the TMP100 and TMP101 is the chip itself. Thermal paths run through the package leads as well as the plastic package. The lower thermal resistance of metal causes the leads to provide the primary thermal path. The GND pin of the TMP100 or TMP101 is directly connected to the metal lead frame and is the best choice for thermal input. To maintain the accuracy in applications requiring air or surface temperature measurement, care should be taken to isolate the package and leads from ambient air temperature. A thermally conductive adhesive assists in achieving accurate surface temperature measurement. pointer register Figure 2 shows the internal register structure of the TMP100 and TMP101. The 8-bit pointer register of the TMP100 and TMP101 is used to address a given data register. The pointer register uses the two LSBs to identify which of the data registers should respond to a read or write command. Table 1 identifies the bits of the pointer register byte. Table 2 describes the pointer address of the registers available in the TMP100 and TMP101. Power-up reset value of P1/P0 is 00. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMP100−EP DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE SGLS254B − JULY 2005 − REVISED OCTOBER 2013 Pointer Register Temperature Register SCL Configuration Register I/O Control Interface TLOW Register SDA THIGH Register Figure 2. Internal Register Structure of TMP100 and TMP101 P7 P6 P5 P4 P3 P2 0 0 0 0 0 0 P1 P0 Register Bits Table 1. Pointer Register Byte P1 P0 0 0 Temperature Register (READ Only) REGISTER 0 1 Configuration Register (READ/WRITE) 1 0 TLOW Register (READ/WRITE) 1 1 THIGH Register (READ/WRITE) Table 2. Pointer Addresses of the TMP100 Registers POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TMP100−EP DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE SGLS254B − JULY 2005 − REVISED OCTOBER 2013 APPLICATION INFORMATION temperature register The temperature register of the TMP100 or TMP101 is a 12-bit read-only register that stores the output of the most recent conversion. Two bytes must be read to obtain data and are described in Table 3 and Table 4. The first 12 bits are used to indicate temperature with all remaining bits equal to zero. Data format for temperature is summarized in Table 5. Following power-up or reset, the temperature register reads 0°C until the first conversion is complete. D7 D6 D5 D4 D3 D2 D1 D0 T11 T10 T9 T8 T7 T6 T5 T4 Table 3. Byte 1 of the Temperature Register D7 D6 D5 D4 D3 D2 D1 D0 T3 T2 T1 T0 0 0 0 0 Table 4. Byte 2 of the Temperature Register TEMPERATURE (5C) DIGITAL OUTPUT (BINARY) HEX 128 0111 1111 1111 7FF 127.9375 0111 1111 1111 7FF 100 0110 0100 0000 640 80 0101 0000 0000 500 75 0100 1011 0000 4B0 50 0011 0010 0000 320 25 0001 1001 0000 190 0.25 0000 0000 0100 004 0.0 0000 0000 0000 000 −0.25 1111 1111 1100 FFC −25 1110 0111 0000 E70 −55 1100 1001 0000 C90 −128 1000 0000 0000 800 Table 5. Temperature Data Format The user can obtain 9, 10, 11, or 12 bits of resolution by addressing the configuration register and setting the resolution bits accordingly. For 9, 10, or 11 bit resolution, the most significant bits in the temperature register are used with the unused LSBs set to zero. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMP100−EP DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE SGLS254B − JULY 2005 − REVISED OCTOBER 2013 APPLICATION INFORMATION configuration register The configuration register is an 8-bit read/write register used to store bits that control the operational modes of the temperature sensor. Read/write operations are performed MSB first. The format of the configuration register for the TMP100 and TMP101 is shown in Table 6, followed by a breakdown of the register bits. The power-up/reset value of the configuration register is all bits equal to 0. The OS/ALERT bit will read as 1 after power-up/reset. Byte D7 D6 D5 D4 D3 D2 D1 D0 1 OS/ALERT R1 R0 F1 F0 POL TM SD Table 6. Configuration Register Format shutdown mode (SD) The shutdown mode of the TMP100 and TMP101 allows the user to save maximum power by shutting down all device circuitry other than the serial interface, which reduces current consumption to less than 1 μA. For the TMP100 and TMP101, shutdown mode is enabled when the SD bit is 1. The device shutdowns once the current conversion is completed. For SD equal to 0, the device maintains continuous conversion. thermostat mode (TM) The thermostat mode bit of the TMP101 indicates to the device whether to operate in comparator mode (TM = 0) or interrupt mode (TM = 1). For more information on comparator and interrupt modes, see the high and low limit registers and SMBus alert function sections. polarity (POL) The polarity bit of the TMP101 allows the user to adjust the polarity of the ALERT pin output. If POL = 0, the ALERT pin will be active low as shown in Figure 3. For POL = 1, the ALERT pin will be active high and the state of the ALERT pin is inverted. THIGH Measured Temperature TLOW TMP101 ALERT PIN (Comparator Mode) POL = 0 TMP101 ALERT PIN (Interrupt Mode) POL = 0 TMP101 ALERT PIN (Comparator Mode) POL = 1 TMP101 ALERT PIN (Interrupt Mode) POL = 1 Read Read Time Read Figure 3. Output Transfer Function Diagrams POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TMP100−EP DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE SGLS254B − JULY 2005 − REVISED OCTOBER 2013 APPLICATION INFORMATION fault queue (F1/F0) A fault condition occurs when the measured temperature exceeds the limits set in the THIGH and TLOW registers. Additionally, the number of fault conditions required to generate an alert may be programmed using the fault queue. The fault queue is provided to prevent a false alert due to environmental noise and requires consecutive fault measurements to trigger the alert function. Table 7 defines the number of measured faults that may be programmed to trigger an alert condition. F1 F0 CONSECUTIVE FAULTS 0 0 1 0 1 2 1 0 4 1 1 6 Table 7. Fault Settings of the TMP100 and TMP101 converter resolution (R1/R0) The converter resolution bits control the resolution of the internal analog-to-digital (A/D) converter. This allows the user to maximize efficiency by programming for higher resolution or faster conversion time. Table 8 identifies the resolution bits and relationship between resolution and conversion time. R1 R0 RESOLUTION CONVERSION TIME (Typical) 0 0 9 Bits (0.5°C) 40 ms 0 1 10 Bits (0.25°C) 80 ms 1 0 11 Bits (0.125°C) 160 ms 1 1 12 Bits (0.0625°C) 320 ms Table 8. Resolution of the TMP100 os/alert (OS) The TMP100 and TMP101 feature a one-shot temperature measurement mode. When the device is in shutdown mode, writing a 1 to the OS/ALERT bit starts a single temperature conversion. The device returns to the shutdown state at the completion of the single conversion. This is useful to reduce power consumption in the TMP100 and TMP101 when continuous monitoring of temperature is not required. Reading the OS/ALERT bit provides information about the comparator mode status. The state of the POL bit will invert the polarity of data returned from the OS/ALERT bit. For POL = 0, the OS/ALERT reads as 1 until the temperature equals or exceeds THIGH for the programmed number of consecutive faults, causing the OS/ALERT bit to read as 0. The OS/ALERT bit continues to read as 0 until the temperature falls below TLOW for the programmed number of consecutive faults when it again reads as 1. The status of the TM bit does not affect the status of the OS/ALERT bit. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMP100−EP DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE SGLS254B − JULY 2005 − REVISED OCTOBER 2013 APPLICATION INFORMATION high and low limit registers In comparator mode (TM = 0), the ALERT pin of the TMP101 becomes active when the temperature equals or exceeds the value in THIGH and generates a consecutive number of faults according to fault bits F1 and F0. The ALERT pin remains active until the temperature falls below the indicated TLOW value for the same number of faults. In Interrupt Mode (TM = 1) the ALERT Pin becomes active when the temperature equals or exceeds THIGH for a consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register occurs or the device successfully responds to the SMBus Alert Response Address. The ALERT pin will also be cleared if the device is placed in Shutdown Mode. Once the ALERT pin is cleared, it will only become active again by the temperature falling below TLOW. When the temperature falls below TLOW, the ALERT pin becomes active and remains active until cleared by a read operation of any register or a successful response to the SMBus Alert Response Address. Once the ALERT pin is cleared, the above cycle repeats with the ALERT pin becoming active when the temperature equals or exceeds THIGH. The ALERT pin can also be cleared by resetting the device with the General Call Reset command. This also clears the state of the internal registers in the device returning the device to Comparator Mode (TM = 0). The ALERT pin function for both operational modes is represented in Figure 3. Table 9 and Table 10 describe the format for the THIGH and TLOW registers. Power-up reset values for THIGH and TLOW are: THIGH = 80°C and TLOW = 75°C. The format of the data for THIGH and TLOW is the same as for the temperature register. All 12 bits for the temperature, THIGH, and TLOW registers are used in the comparisons for the ALERT function for all converter resolutions. The three LSBs in THIGH and TLOW can affect the ALERT output even if the converter is configured for 9-bit resolution. Byte D7 D6 D5 D4 D3 D2 D1 D0 1 H11 H10 H9 H8 H7 H6 H5 H4 Byte D7 D6 D5 D4 D3 D2 D1 D0 2 H3 H2 H1 H0 0 0 0 0 Table 9. Bytes 1 and 2 of THIGH Register Byte D7 D6 D5 D4 D3 D2 D1 D0 1 L11 L10 L9 L8 L7 L6 L5 L4 Byte D7 D6 D5 D4 D3 D2 D1 D0 2 L3 L2 L1 L0 0 0 0 0 Table 10. Bytes 1 and 2 of TLOW Register POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TMP100−EP DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE SGLS254B − JULY 2005 − REVISED OCTOBER 2013 APPLICATION INFORMATION serial interface The TMP100 and TMP101 operate only as slave devices on the I2C bus and SMBus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The TMP100 and TMP101 support the transmission protocol for fast (up to 400 kHz) and high-speed (up to 3.4 MHz) modes. All data bytes are transmitted most significant bit first. serial bus address To program the TMP100 and TMP101, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits and a direction bit indicating the intent of executing a read or write operation. The TMP100 features two address pins to allow up to eight devices to be addressed on a single I2C interface. Table 11 describes the pin logic levels used to properly connect up to eight devices. Float indicates the pin is left unconnected. The state of pins ADD0 and ADD1 is sampled on the first I2C bus communication and should be set prior to any activity on the interface. ADD1 ADD0 SLAVE ADDRESS 0 0 1001000 0 Float 1001001 0 1 1001010 1 0 1001100 1 Float 1001101 1 1 1001110 Float 0 1001011 Float 1 1001111 Table 11. Address Pins and Slave Addresses for TMP100 The address pins of the TMP100 and TMP101 are read after reset or in response to an I2C address acquire request. Following a read, the state of the address pins is latched to minimize power dissipation associated with detection. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMP100−EP DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE SGLS254B − JULY 2005 − REVISED OCTOBER 2013 APPLICATION INFORMATION bus overview The device that initiates the transfer is called a master and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a high-to-low logic level while SCL is high. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an acknowledge and pulling SDA low. Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data transfer, SDA must remain stable while SCL is high, as any change in SDA while SCL is high will be interpreted as a control signal. Once all data has been transferred, the master generates a STOP condition indicated by pulling SDA from low-to-high, while SCL is high. writing/reading to the TMP100 and TMP101 Accessing a particular register on the TMP100 and TMP101 is accomplished by writing the appropriate value to the pointer register. The value for the pointer register is the first byte transferred after the I2C slave address byte with the R/W bit low. Every write operation to the TMP100 and TMP101 requires a value for the pointer register. (See Figure 5.) When reading from the TMP100 and TMP101, the last value stored in the pointer register by a write operation is used to determine which register is read by a read operation. To change the register pointer for a read operation, a new value must be written to the pointer register. This is accomplished by issuing an I2C slave address byte with the R/W bit low, followed by the pointer register byte. No additional data is required. The master can then generate a START condition and send the I2C slave address byte with the R/W bit high to initiate the read command. See Figure 6 for details of this sequence. If repeated reads from the same register are desired, it is not necessary to continually send the pointer register bytes as the TMP100 and TMP101 remembers the pointer register value until it is changed by the next write operation. slave mode operations The TMP100 and TMP101 can operate as slave receivers or slave transmitters. slave receiver mode The first byte transmitted by the master is the slave address, with the R/W bit low. The TMP100 or TMP101 then acknowledges reception of a valid address. The next byte transmitted by the master is the pointer register. The TMP100 or TMP101 then acknowledges reception of the pointer register byte. The next byte or bytes are written to the register addressed by the pointer register. The TMP100 and TMP101 acknowledge reception of each data byte. The master may terminate data transfer by generating a START or STOP condition. slave transmitter mode The first byte is transmitted by the master and is the slave address, with the R/W bit high. The slave acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the pointer register. The master acknowledges reception of the data byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The master may terminate data transfer by generating a not-acknowledge on reception of any data byte, or generating a START or STOP condition. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TMP100−EP DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE SGLS254B − JULY 2005 − REVISED OCTOBER 2013 APPLICATION INFORMATION SMBus alert function The TMP101 supports the SMBus Alert function. When the TMP101 is operating in Interrupt Mode (TM = 1), the ALERT pin of the TMP101 may be connected as an SMBus Alert signal. When a master senses that an ALERT condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP101 is active, the TMP101 acknowledges the SMBus Alert command and responds by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates if the temperature exceeding THIGH or falling below TLOW caused the ALERT condition. For POL = 0, this bit will be LOW if the temperature is greater than or equal to THIGH. This bit will be HIGH if the temperature is less than TLOW. The polarity of this bit will be inverted if POL = 1. See Figure 7 for details of this sequence. If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion of the SMBus alert command determines which device clears its ALERT status. If the TMP101 wins the arbitration, its ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP101 loses the arbitration, its ALERT pin remains active. The TMP100 also responds to the SMBus ALERT command if its TM bit is set to 1. Since it does not have an ALERT pin, the master needs to periodically poll the device by issuing an SMBus Alert command. If the TMP100 has generated an ALERT, it acknowledges the SMBus Alert command and returns its slave address in the next byte. general call The TMP100 and TMP101 respond to the I2C General Call address (0000000) if the eighth bit is 0. The device acknowledges the general call address and responds to commands in the second byte. If the second byte is 00000100, the TMP100 and TMP101 latch the status of their address pins, but will not reset. If the second byte is 00000110, the TMP100 and TMP101 latch the status of their address pins and reset their internal registers. high-speed mode In order for the I2C bus to operate at frequencies above 400 kHz, the master device must issue an Hs-mode master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The TMP100 and TMP101 will not acknowledge this byte as required by the I2C specification, but switch their input filters on SDA and SCL and their output filters on SDA to operate in Hs-mode, allowing transfers at up to 3.4 MHz. After the Hs-mode master code has been issued, the master transmits an I2C slave address to initiate a data transfer operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP100 and TMP101 switch their input and output filters back to fast-mode operation. timing diagrams The TMP100 and TMP101 are I2C and SMBus compatible. Figure 4 through Figure 7 describe the various operations on the TMP100 and TMP101. Bus definitions are given below. Parameters for Figure 4 are defined in Table 12. Bus Idle: Both SDA and SCL lines remain high. Start Data Transfer: A change in the state of the SDA line, from high-to-low, while the SCL line is high, defines a START condition. Each data transfer is initiated with a START condition. Stop Data Transfer: A change in the state of the SDA line from low-to-high while the SCL line is high defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition. Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMP100−EP DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE SGLS254B − JULY 2005 − REVISED OCTOBER 2013 APPLICATION INFORMATION Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data transfer can be signaled by the master generating a not-acknowledge on the last byte that has been transmitted by the slave. FAST MODE PARAMETER MIN HIGH-SPEED MODE MAX MIN 0.4 UNIT MAX f(SCLK) SLCK operating frequency t(BUF) Bus free time between STOP and START condition 600 160 3.4 MHz ns th(STA) Hold time after repeated START condition. After this period, the first clock is generated. 600 160 ns tsu(STA) Repeated START condition setup time 600 160 ns tsu(STO) STOP condition setup time 600 160 ns th(DAT) Data hold time 0 0 ns tsu(DAT) Data setup time 100 10 ns t(LOW) SCLK clock low period 1300 160 ns t(HIGH) SCLK clock high period 600 tf Clock/data fall time 300 160 ns tr Clock/data rise time 300 160 ns 60 ns Table 12. Timing Diagram Definitions t(LOW) tr tf th(STA) SCL th(STA) t(HIGH) th(DAT) tsu(STO) tsu(STA) tsu(DAT) SDA t(BUF) P S S P Figure 4. I2C Timing Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TMP100−EP DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE SGLS254B − JULY 2005 − REVISED OCTOBER 2013 APPLICATION INFORMATION 1 9 1 9 SCL ... 1 SDA 0 0 1 A2 A1 A0 0 R/W Start By Master 0 0 0 0 0 P1 ACK By TMP100 or TMP101 ... P0 ACK By TMP100 or TMP101 Frame 1 I2C Slave Address Byte Frame 2 Pointer Register Byte 1 9 1 9 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 ACK By TMP100 or TMP101 Frame 3 Data Byte 1 POST OFFICE BOX 655303 D1 D0 ACK By TMP100 or TMP101 Frame 4 Data Byte 2 Figure 5. I2C Timing Diagram for Write Word Format 14 D2 • DALLAS, TEXAS 75265 Stop By Master TMP100−EP DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE SGLS254B − JULY 2005 − REVISED OCTOBER 2013 APPLICATION INFORMATION 1 9 1 9 SCL SDA 1 0 0 1 A2 A1 R/W A0 Start By Master 0 0 0 0 0 0 P1 ACK By TMP100 or TMP101 P0 ACK By TMP100 or TMP101 Frame 1 I2C Slave Address Byte Frame 2 Pointer Register Byte 1 9 1 9 SCL (Continued) SDA (Continued) 1 0 0 1 A2 A1 A0 Start By Master D7 R/W D6 D5 D4 D3 ACK By TMP100 or TMP101 D1 D0 From TMP100 or TMP101 Frame 3 I2C Slave Address Byte 1 D2 ACK By Master Frame 4 Data Byte 1 Read Register 9 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 From TMP100 or TMP101 ACK By Master Stop By Master Frame 5 Data Byte 2 Read Register Figure 6. I2C Timing Diagram for Read Word Format ALERT 9 1 1 9 SCL SDA 0 Start By Master 0 0 1 1 0 0 R/W 1 0 0 ACK By TMP100 or TMP101 Frame 1 SMBus ALERT Response Address Byte 1 A2 A1 A0 Status From TMP100 or TMP101 NACK By Master Stop By Master Frame 2 Slave Address From TMP100 Figure 7. Timing Diagram for SMBus ALERT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TMP100−EP DIGITAL TEMPERATURE SENSOR WITH I2C INTERFACE SGLS254B − JULY 2005 − REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS, at TA = 255C, V+ = 5 V, UNLESS OTHERWISE NOTED QUIESCENT CURRENT vs TEMPERATURE SHUTDOWN CURRENT vs TEMPERATURE 70 1.0 0.9 ISD − Shutdown Current − μA IQ − Quiescent Current − μA Serial Bus Inactive 60 V+ = 5 V 50 40 V+ = 2.7 V 30 −60 −40 −20 0 20 40 60 80 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 −0.1 −60 −40 −20 100 120 140 40 60 80 TA − Free-Air Temperature − °C Figure 8 Figure 9 100 120 140 TEMPERATURE ACCURACY vs TEMPERATURE CONVERSION TIME vs TEMPERATURE 2.0 350 T − Temperature Accuracy − °C Note: 12-Bit Resolution V+ = 5 V 300 V+ = 2.7 V 250 −60 −40 −20 0 20 40 60 80 100 120 140 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 3 Typical Units −2.0 −60 −40 −20 0 Note: 12-Bit Resolution 20 40 60 80 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 10 Figure 11 QUIESCENT CURRENT WITH BUS ACTIVITY vs FREQUENCY IQ − Quiescent Current − μA 180 160 125°C 140 120 100 125°C 25°C 25°C 80 60 40 20 0 10k −55°C −55°C Fast Mode 100k Hs Mode 1M SCL Frequency − Hz Figure 12 16 20 TA − Free-Air Temperature − °C 400 t − Conversion Time − ms 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10M 100 120 140 Revision History DATE REV PAGE SECTION 10−04−13 B 10 serial bus address 09−30−13 B Document Multiple sections throughout document DESCRIPTION deleted Table 12 and first 2 sentences in paragraph above the table Changed to Rev B October 2013. Corrected only what was marked in red. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TMP100MDBVREP ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 100E V62/05618-01XE ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 100E (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of