TMP102

Burr Brown Products from Texas Instruments TMP102 SBOS397 – AUGUST 2007 Low Power Digital Temperature Sensor With SMBus™/Two-Wire Serial Interface in SOT563 FEATURES • • • TINY SOT563 PACKAGE ACCURACY: 0.5°C (–25°C to +85°C) LOW QUIESCENT CURRENT: 10μA Active (max) 1μA Shutdown (max) SUPPLY RANGE: 1.4V to 3.6V RESOLUTION: 12 Bits DIGITAL OUTPUT: Two-Wire Serial Interface DESCRIPTION The TMP102 is a two-wire, serial output temperature sensor available in a tiny SOT563 package. Requiring no external components, the TMP102 is capable of reading temperatures to a resolution of 0.0625°C. The TMP102 features SMBus and two-wire interface compatibility, and allows up to four devices on one bus. It also features an SMB alert function. The TMP102 is ideal for extended temperature measurement in a variety of communication, computer, consumer, environmental, industrial, and instrumentation applications. The device is specified for operation over a temperature range of –40°C to +125°C. Temperature 1 Diode Temp. Sensor Control Logic 6 • • • • • • • • • • • • APPLICATIONS PORTABLE AND BATTERY-POWERED APPLICATIONS POWER-SUPPLY TEMPERATURE MONITORING COMPUTER PERIPHERAL THERMAL PROTECTION NOTEBOOK COMPUTERS BATTERY MANAGEMENT OFFICE MACHINES THERMOSTAT CONTROLS ELECTROMECHANICAL DEVICE TEMPERATURES GENERAL TEMPERATURE MEASUREMENTS: Industrial Controls Test Equipment Medical Instrumentations SCL SDA GND 2 DS A/D Converter Serial Interface 5 V+ ALERT 3 OSC Config. and Temp. Register 4 ADD0 TMP102 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SMBus is a trademark of Intel, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TMP102 www.ti.com SBOS397 – AUGUST 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT TMP102 (1) PACKAGE-LEAD SOT563 PACKAGE DESIGNATOR DRL PACKAGE MARKING CBZ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) PARAMETER Supply Voltage Input Voltage (2) Operating Temperature Storage Temperature Junction Temperature Human Body Model (HBM) ESD Rating Charged Device Model (CDM) Machine Model (MM) (1) (2) TMP102 3.6 –0.5 to +3.6 –55 to +150 –60 to +150 +150 2000 1000 200 UNIT V V °C °C °C V V V Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. Input voltage rating applies to all TMP102 input voltages. PIN CONFIGURATION DRL Package SOT563 Top View SCL GND ALERT 1 2 3 6 5 4 SDA V+ ADD0 CBZ 2 Submit Documentation Feedback TMP102 www.ti.com SBOS397 – AUGUST 2007 ELECTRICAL CHARACTERISTICS At TA = +25°C and VS = +1.4V to +3.6V, unless otherwise noted. TMP102 PARAMETER TEMPERATURE INPUT Range Accuracy (Temperature Error) –25°C to +85°C –40°C to +125°C vs Supply Resolution DIGITAL INPUT/OUTPUT Input Logic Levels: VIH VIL Input Current Output Logic Levels: VOL SDA VOL ALERT Resolution Conversion Time Conversion Modes CR1 = 0, CR0 = 0 CR1 = 0, CR0 = 1 CR1 = 1, CR0 = 0 (default) CR1 = 1, CR0 = 1 Timeout Time POWER SUPPLY Operating Supply Range Quiescent Current IQ Serial Bus Inactive, CR1 = 1, CR0 = 0 (default) Serial Bus Active, SCL Frequency = 400kHz Serial Bus Active, SCL Frequency = 3.4MHz Shutdown Current ISD Serial Bus Inactive Serial Bus Active, SCL Frequency = 400kHz Serial Bus Active, SCL Frequency = 3.4MHz TEMPERATURE RANGE Specified Range Operating Range Thermal Resistance, SOT563 θJA –40 –55 142 +125 +150 °C °C °C/W +1.4 7 15 85 0.5 10 80 1 +3.6 10 V μA μA μA μA μA μA V+ > 2V, IOL = 3mA V+ < 2V, IOL = 3mA V+ > 2V, IOL = 3mA V+ < 2V, IOL = 3mA 0 0 0 0 12 26 0.25 1 4 8 30 40 35 0.4 0.2 (V+) 0.4 0.2 (V+) V V V V Bit ms Conv/s Conv/s Conv/s Conv/s ms IIN 0 < VIN < 3.6V 0.7 (V+) –0.5 3.6 0.3 (V+) 1 V V μA –40 0.5 1 0.2 0.0625 +125 2 3 0.5 °C °C °C °C/V °C CONDITIONS MIN TYP MAX UNIT Submit Documentation Feedback 3 TMP102 www.ti.com SBOS397 – AUGUST 2007 TYPICAL CHARACTERISTICS At TA = +25°C and V+ = 3.3V, unless otherwise noted. QUIESCENT CURRENT vs TEMPERATURE (4 Conversions per Second) 20 18 16 14 10 9 8 7 SHUTDOWN CURRENT vs TEMPERATURE 10 8 6 4 2 0 -60 -40 -20 0 20 ISD (mA) IQ (mA) 12 3.6V Supply 6 5 4 3 1.4V Supply 3.6V Supply 1.4V Supply 2 1 0 40 60 80 100 120 140 160 -60 -40 -20 0 20 40 60 80 100 120 140 160 Temperature (°C) Temperature (°C) Figure 1. Figure 2. QUIESCENT CURRENT vs BUS FREQUENCY (Temperature at 3.3V Supply) 100 90 80 70 CONVERSION TIME vs TEMPERATURE 40 38 Conversion Time (ms) 36 34 1.4V Supply IQ (mA) 32 30 28 26 24 22 20 60 50 40 +125°C +25°C -55°C 3.6V Supply 30 20 10 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 1k 10k 100k Bus Frequency (Hz) 1M 10M Temperature (°C) Figure 3. TEMPERATURE ERROR vs TEMPERATURE 2.0 1.5 Figure 4. TEMPERATURE ERROR AT +25°C Temperature Error (°C) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 Population -0.05 0.05 0.15 0.25 0.35 -0.45 -60 -40 -20 0 20 40 60 80 100 120 140 160 Temperature (°C) -0.35 -0.25 Temperature Error (°C) Figure 5. -0.15 Figure 6. 4 Submit Documentation Feedback 0.45 TMP102 www.ti.com SBOS397 – AUGUST 2007 APPLICATION INFORMATION The TMP102 is a digital temperature sensor that is optimal for thermal-management and thermalprotection applications. The TMP102 is two-wire- and SMBus interface-compatible, and is specified over a temperature range of –40°C to +125°C. Pull-up resistors are required on SCL, SDA, and ALERT. A 0.01μF bypass capacitor is recommended, as shown in Figure 7. V+ POINTER REGISTER Figure 8 shows the internal register structure of the TMP102. The 8-bit Pointer Register of the device is used to address a given data register. The Pointer Register uses the two LSBs (see Table 11) to identify which of the data registers should respond to a read or write command. Table 1 identifies the bits of the Pointer Register byte. During a write command, P2 through P7 must always be '0'. Table 2 describes the pointer address of the registers available in the TMP102. Power-up reset value of P1/P0 is '00'. By default, the TMP102 reads the temperature on power-up. Pointer Register 5 To Two-Wire Controller SCL SDA 1 6 TMP102 4 3 0.01mF ADD0 ALERT (Output) 2 NOTE: SCL, SDA, and ALERT pins require pull-up resistors. GND Temperature Register Configuration Register SCL I/O Control Interface SDA Figure 7. Typical Connections The temperature sensor in the TMP102 is the chip itself. Thermal paths run through the package leads, as well as the plastic package. The lower thermal resistance of metal causes the leads to provide the primary thermal path. To maintain accuracy in applications requiring air or surface temperature measurement, care should be taken to isolate the package and leads from ambient air temperature. A thermally-conductive adhesive is helpful in achieving accurate surface temperature measurement. TLOW Register THIGH Register Figure 8. Internal Register Structure Table 1. Pointer Register Byte P7 0 P6 0 P5 0 P4 0 P3 0 P2 0 P1 P0 Register Bits Table 2. Pointer Addresses P1 0 0 1 1 P0 0 1 0 1 REGISTER Temperature Register (Read Only) Configuration Register (Read/Write) TLOW Register (Read/Write) THIGH Register (Read/Write) Submit Documentation Feedback 5 TMP102 www.ti.com SBOS397 – AUGUST 2007 TEMPERATURE REGISTER The Temperature Register of the TMP102 is configured as a 12-bit, read-only register (Configuration Register EM bit = '0', see the Extended Mode section), or as a 13-bit, read-only register (Configuration Register EM bit = '1') that stores the output of the most recent conversion. Two bytes must be read to obtain data, and are described in Table 3 and Table 4. Note that byte 1 is the most significant byte, followed by byte 2, the least significant byte. The first 12 bits (13 bits in Extended mode) are used to indicate temperature. The least significant byte does not have to be read if that information is not needed. The data format for temperature is summarized in Table 5 and Table 6. One LSB equals 0.0625°C. Negative numbers are represented in binary two's complement format. Following power-up or reset, the Temperature Register will read 0°C until the first conversion is complete. Bit D0 of byte 2 indicates Normal mode (EM bit = '0') or Extended mode (EM bit = '1') and can be used to distinguish between the two temperature register data formats. The unused bits in the Temperature Register always read '0'. Table 3. Byte 1 of Temperature Register(1) D7 T11 (T12) D6 T10 (T11) D5 T9 (T10) D4 T8 (T9) D3 T7 (T8) D2 T6 (T7) D1 T5 (T6) D0 T4 (T5) (1) Extended mode 13-bit configuration shown in parenthesis. Table 4. Byte 2 of Temperature Register(1) D7 T3 (T4) D6 T2 (T3) D5 T1 (T2) D4 T0 (T1) D3 0 (T0) D2 0 (0) D1 0 (0) D0 0 (1) (1) Extended mode 13-bit configuration shown in parenthesis. Table 5. 12-Bit Temperature Data Format (1) TEMPERATURE (°C) 128 127.9375 100 80 75 50 25 0.25 0 –0.25 –25 –55 (1) DIGITAL OUTPUT (BINARY) 0111 1111 1111 0111 1111 1111 0110 0100 0000 0101 0000 0000 0100 1011 0000 0011 0010 0000 0001 1001 0000 0000 0000 0100 0000 0000 0000 1111 1111 1100 1110 0111 0000 1100 1001 0000 HEX 7FF 7FF 640 500 4B0 320 190 004 000 FFC E70 C90 The resolution for the Temp ADC in Internal Temperature mode is 0.0625°C/count. For positive temperatures (for example, +50°C): Two's complement is not performed on positive numbers. Therefore, simply convert the number to binary code with the 12-bit, left-justified format, and MSB = 0 to denote a positive sign. Example: (+50°C)/(0.0625°C/count) = 800 = 320h = 0011 0010 0000 For negative temperatures (for example, –25°C): Generate the Two's Complement of a negative number by complementing the absolute value binary number and adding 1. Denote a negative number with MSB = 1. Example: (|–25°C|)/(0.0625°C/count) = 400 = 190h = 0001 1001 0000 Two's complement format: 1110 0110 1111 + 1 = 1110 0111 0000 6 Submit Documentation Feedback TMP102 www.ti.com SBOS397 – AUGUST 2007 Table 6. 13-Bit Temperature Data Format TEMPERATURE (°C) 150 128 127.9375 100 80 75 50 25 0.25 0 –0.25 –25 –55 DIGITAL OUTPUT (BINARY) 0 1001 0110 0000 0 1000 0000 0000 0 0111 1111 1111 0 0110 0100 0000 0 0101 0000 0000 0 0100 1011 0000 0 0011 0010 0000 0 0001 1001 0000 0 0000 0000 0100 0 0000 0000 0000 1 1111 1111 1100 1 1110 0111 0000 1 1100 1001 0000 HEX 0960 0800 07FF 0640 0500 04B0 0320 0190 0004 0000 1FFC 1E70 1C90 CONFIGURATION REGISTER The Configuration Register is a 16-bit read/write register used to store bits that control the operational modes of the temperature sensor. Read/write operations are performed MSB first. The format and power-up/reset value of the Configuration Register is shown in Table 7. For compatability, the first byte corresponds to the Configuration Register in the TMP75 and TMP275. All registers are updated byte by byte. Table 7. Configuration and Power-Up/Reset Format BYTE 1 2 D7 OS 0 CR1 1 D6 R1 1 CR0 0 D5 R0 1 AL 1 D4 F1 0 EM 0 D3 F0 0 0 0 D2 POL 0 0 0 D1 TM 0 0 0 D0 SD 0 0 0 ALERT (AL Bit) The AL bit is a read-only function. Reading the AL bit will provide information about the comparator mode status. The state of the POL bit inverts the polarity of data returned from the AL bit. For POL = 0, the AL bit will read as '1' until the temperature equals or exceeds THIGH for the programmed number of consecutive faults, causing the AL bit to read as '0'. The AL bit will continue to read as '0' until the temperature falls below TLOW for the programmed number of consecutive faults, when it will again read as '1'. The status of the TM bit does not affect the status of the AL bit. CONVERSION RATE The conversion rate bits, CR1 and CR0, configure the TMP102 for conversion rates of 8Hz, 4Hz, 1Hz, or 0.25Hz. The default rate is 4Hz. The TMP102 has a typical conversion time of 26ms. To achieve different conversion rates, the TMP102 makes a conversion and after that powers down and waits for the appropriate delay set by CR1 and CR0. Table 8 shows the settings for CR1 and CR0. Table 8. Conversion Rate Settings CR1 0 0 1 1 CR0 0 1 0 1 CONVERSION RATE 0.25Hz 1Hz 4Hz (default) 8Hz EXTENDED MODE (EM) The Extended mode bit configures the device for Normal mode operation (EM = 0) or Extended mode operation (EM = 1). In Normal mode, the Temperature Register and high- and low-limit registers use a 12-bit data format. Normal mode is used to make the TMP102 compatible with the TMP75. Extended mode (EM = 1) allows measurement of temperatures above +128°C by configuring the Temperature Register, and high- and low-limit registers, for 13-bit data format. Submit Documentation Feedback 7 TMP102 www.ti.com SBOS397 – AUGUST 2007 After power-up or general-call reset, the TMP102 immediately starts a conversion, as shown in Figure 9. The first result is available after 26ms (typical). The active quiescent current during conversion is 40μA (typical at +27°C). The quiescent current during delay is 2.2μA (typical at +27°C). Measured Temperature THIGH TLOW Delay (1) TMP102 ALERT PIN (Comparator Mode) POL = 0 TMP102 ALERT PIN (Interrupt Mode) POL = 0 TMP102 ALERT PIN (Comparator Mode) POL = 1 TMP102 ALERT PIN (Interrupt Mode) POL = 1 26ms 26ms Startup Start of Conversion NOTE: (1) Delay is set by CR1 and CR0. Figure 9. Conversion Start Read Read Time Read SHUTDOWN MODE (SD) The Shutdown mode bit saves maximum power by shutting down all device circuitry other than the serial interface, reducing current consumption to typically less than 0.5μA. Shutdown mode is enabled when the SD bit is '1'; the device shuts down when current conversion is completed. When SD is equal to '0', the device maintains a continuous conversion state. Figure 10. Output Transfer Function Diagrams FAULT QUEUE (F1/F0) A fault condition exists when the measured temperature exceeds the user-defined limits set in the THIGH and TLOW registers. Additionally, the number of fault conditions required to generate an alert may be programmed using the fault queue. The fault queue is provided to prevent a false alert as a result of environmental noise. The fault queue requires consecutive fault measurements in order to trigger the alert function. Table 9 defines the number of measured faults that may be programmed to trigger an alert condition in the device. For THIGH and TLOW register format and byte order, see the Highand Low-Limit Registers section. Table 9. TMP102 Fault Settings F1 0 0 1 1 F0 0 1 0 1 CONSECUTIVE FAULTS 1 2 4 6 THERMOSTAT MODE (TM) The Thermostat mode bit indicates to the device whether to operate in Comparator mode (TM = 0) or Interrupt mode (TM = 1). For more information on comparator and interrupt modes, see the High- and Low-Limit Registers section. POLARITY (POL) The Polarity bit allows the user to adjust the polarity of the ALERT pin output. If POL = 0, the ALERT pin will be active low, as shown in Figure 10. For POL = 1, the ALERT pin will be active high, and the state of the ALERT pin is inverted. 8 Submit Documentation Feedback TMP102 www.ti.com SBOS397 – AUGUST 2007 CONVERTER RESOLUTION (R1/R0) R1/R0 are read-only bits. The TMP102 converter resolution is set on start up to '11'. This sets the temperature register to a 12 bit-resolution. ONE-SHOT/CONVERSION READY (OS) The TMP102 features a One-Shot Temperature Measurement mode. When the device is in Shutdown mode, writing a ‘1’ to the OS bit starts a single temperature conversion. During the conversion, the OS bit reads '0'. The device returns to the shutdown state at the completion of the single conversion. After the conversion, the OS bit reads '1'. This feature is useful for reducing power consumption in the TMP102 when continuous temperature monitoring is not required. As a result of the short conversion time, the TMP102 can achive a higher conversion rate. A single conversion typically takes 26ms and a read can take place in less than 20μs. When using One-Shot mode, 30 or more conversions per second are possible. Both operational modes are represented in Figure 10. Table 10 and Table 11 describe the format for the THIGH and TLOW registers. Note that the most significant byte is sent first, followed by the least significant byte. Power-up reset values for THIGH and TLOW are: THIGH = +80°C and TLOW = +75°C. The format of the data for THIGH and TLOW is the same as for the Temperature Register. Table 10. Bytes 1 and 2 of THIGH Register(1) BYTE 1 BYTE 2 D7 H11 (H12) D7 H3 (H4) D6 H10 (H11) D6 H2 (H3) D5 H9 (H10) D5 H1 (H2) D4 H8 (H9) D4 H0 (H1) D3 H7 (H8) D3 0 (H0) D2 H6 (H7) D2 0 (0) D1 H5 (H6) D1 0 (0) D0 H4 (H5) D0 0 (0) (1) Extended mode 13-bit configuration shown in parenthesis. Table 11. Bytes 1 and 2 of TLOW Register(1) BYTE 1 BYTE 2 D7 L11 (L12) D7 L3 (L4) D6 L10 (L11) D6 L2 (L3) D5 L9 (L10) D5 L1 (L2) D4 L8 (L9) D4 L0 (L1) D3 L7 (L8) D3 0 (L0) D2 L6 (L7) D2 0 (0) D1 L5 (L6) D1 0 (0) D0 L4 (L5) D0 0 (0) HIGH- AND LOW-LIMIT REGISTERS In Comparator mode (TM = 0), the ALERT pin becomes active when the temperature equals or exceeds the value in THIGH and generates a consecutive number of faults according to fault bits F1 and F0. The ALERT pin remains active until the temperature falls below the indicated TLOW value for the same number of faults. In Interrupt mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds the value in THIGH for a consecutive number of fault conditions (as shown in Table 9). The ALERT pin remains active until a read operation of any register occurs, or the device successfully responds to the SMBus Alert Response address. The ALERT pin will also be cleared if the device is placed in Shutdown mode. Once the ALERT pin is cleared, it becomes active again only when temperature falls below TLOW, and remains active until cleared by a read operation of any register or a successful response to the SMBus Alert Response address. Once the ALERT pin is cleared, the above cycle repeats, with the ALERT pin becoming active when the temperature equals or exceeds THIGH. The ALERT pin can also be cleared by resetting the device with the General Call Reset command. This action also clears the state of the internal registers in the device, returning the device to Comparator mode (TM = 0). (1) Extended mode 13-bit configuration shown in parenthesis. BUS OVERVIEW The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a high to low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge of the clock, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA low. Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data transfer SDA must remain stable while SCL is high, because any change in SDA while SCL is high will be interpreted as a START or STOP signal. Once all data have been transferred, the master generates a STOP condition indicated by pulling SDA from low to high, while SCL is high. Submit Documentation Feedback 9 TMP102 www.ti.com SBOS397 – AUGUST 2007 SERIAL INTERFACE The TMP102 operates as a slave device only on the two-wire bus and SMBus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP102 supports the transmission protocol for both fast (1kHz to 400kHz) and high-speed (1kHz to 3.4MHz) modes. All data bytes are transmitted MSB first. Register. This action is accomplished by issuing a slave address byte with the R/W bit low, followed by the Pointer Register byte. No additional data are required. The master can then generate a START condition and send the slave address byte with the R/W bit high to initiate the read command. See Figure 14 for details of this sequence. If repeated reads from the same register are desired, it is not necessary to continually send the Pointer Register bytes, because the TMP102 remembers the Pointer Register value until it is changed by the next write operation. Note that register bytes are sent with the most significant byte first, followed by the least significant byte. SERIAL BUS ADDRESS To communicate with the TMP102, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation. The TMP102 features an address pin to allow up to four devices to be addressed on a single bus. Table 12 describes the pin logic levels used to properly connect up to four devices. Table 12. Address Pin and Slave Addresses DEVICE TWO-WIRE ADDRESS 1001000 1001001 1001010 1001011 A0 PIN CONNECTION Ground V+ SDA SCL SLAVE MODE OPERATIONS The TMP102 can operate as a slave receiver or slave transmitter. As a slave device, the TMP102 never drives the SCL line. Slave Receiver Mode: The first byte transmitted by the master is the slave address, with the R/W bit low. The TMP102 then acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer Register. The TMP102 then acknowledges reception of the Pointer Register byte. The next byte or bytes are written to the register addressed by the Pointer Register. The TMP102 acknowledges reception of each data byte. The master can terminate data transfer by generating a START or STOP condition. Slave Transmitter Mode: The first byte transmitted by the master is the slave address, with the R/W bit high. The slave acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the Pointer Register. The master acknowledges reception of the data byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The master can terminate data transfer by generating a Not-Acknowledge on reception of any data byte, or generating a START or STOP condition. WRITING/READING OPERATION Accessing a particular register on the TMP102 is accomplished by writing the appropriate value to the Pointer Register. The value for the Pointer Register is the first byte transferred after the slave address byte with the R/W bit low. Every write operation to the TMP102 requires a value for the Pointer Register (see Figure 13). When reading from the TMP102, the last value stored in the Pointer Register by a write operation is used to determine which register is read by a read operation. To change the register pointer for a read operation, a new value must be written to the Pointer 10 Submit Documentation Feedback TMP102 www.ti.com SBOS397 – AUGUST 2007 SMBus ALERT FUNCTION The TMP102 supports the SMBus Alert function. When the TMP102 operates in Interrupt mode (TM = '1'), the ALERT pin may be connected as an SMBus Alert signal. When a master senses that an ALERT condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) to the bus. If the ALERT pin is active, the device acknowledges the SMBus Alert command and responds by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates if the ALERT condition was caused by the temperature exceeding THIGH or falling below TLOW. For POL = '0', this bit is low if the temperature is greater than or equal to THIGH; this bit is high if the temperature is less than TLOW. The polarity of this bit is inverted if POL = '1'. Refer to Figure 15 for details of this sequence. If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion of the SMBus Alert command determines which device will clear its ALERT status. The device with the lowest two-wire address wins the arbitration. If the TMP102 wins the arbitration, its ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP102 loses the arbitration, its ALERT pin remains active. HIGH-SPEED (Hs) MODE In order for the two-wire bus to operate at frequencies above 400kHz, the master device must issue an Hs-mode master code (00001xxx) as the first byte after a START condition to switch the bus to high-speed operation. The TMP102 does not acknowledge this byte, but switches its input filters on SDA and SCL and its output filters on SDA to operate in Hs-mode, allowing transfers at up to 3.4MHz. After the Hs-mode master code has been issued, the master transmits a two-wire slave address to initiate a data transfer operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP102 switches the input and output filters back to fast-mode operation. TIMEOUT FUNCTION The TMP102 resets the serial interface if SCL is held low for 30ms (typ). The TMP102 releases the bus if it is pulled low and waits for a START condition. To avoid activating the timeout function, it is necessary to maintain a communication speed of at least 1kHz for SCL operating frequency. NOISE The TMP102 is a very low-power device and generates very low noise on the supply bus. Applying an RC filter to the V+ pin of the TMP102 can further reduce any noise the TMP102 might propagate to other components. RF in Figure 11 should be less than 5kΩ and CF should be greater than 10nF. Supply Voltage GENERAL CALL The TMP102 responds to a two-wire General Call address (0000000) if the eighth bit is '0'. The device acknowledges the General Call address and responds to commands in the second byte. If the second byte is 00000110, the TMP102 internal registers are reset to power-up values. The TMP102 does not support the General Address acquire command. TMP102 SCL SDA RF £ 5kW GND V+ CF ³ 10nF ALERT ADD0 Figure 11. Noise Reduction Submit Documentation Feedback 11 TMP102 www.ti.com SBOS397 – AUGUST 2007 TIMING DIAGRAMS The TMP102 is two-wire and SMBus compatible. Figure 12 to Figure 15 describe the various operations on the TMP102. Parameters for Figure 12 are defined in Table 13. Bus definitions are: Bus Idle: Both SDA and SCL lines remain high. Start Data Transfer: A change in the state of the SDA line, from high to low, while the SCL line is high, defines a START condition. Each data transfer is initiated with a START condition. Stop Data Transfer: A change in the state of the SDA line from low to high while the SCL line is high defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition. Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. It is also possible to use the TMP102 for single byte updates. To update only the MS byte, terminate the communication by issuing a START or STOP communication on the bus. Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data transfer can be signaled by the master generating a Not-Acknowledge ('1') on the last byte that has been transmitted by the slave. Table 13. Timing Diagram Definitions FAST MODE PARAMETER f(SCL) f(SCL) t(BUF) t(HDSTA) t(SUSTA) t(SUSTO) t(HDDAT) t(SUDAT) t(LOW) t(LOW) t(HIGH) tF tR tR TEST CONDITIONS SCL Operating Frequency, VS > 1.7V SCL Operating Frequency, VS < 1.7V Bus Free Time Between STOP and START Condition Hold time after repeated START condition. After this period, the first clock is generated. Repeated START Condition Setup Time STOP Conditon Setup Time Data Hold Time Data Setup Time SCL Clock Low Period, VS > 1.7V SCL Clock Low Period, VS < 1.7V SCL Clock High Period Clock/Data Fall Time Clock/Data Rise Time Clock/Data Rise Time for SCLK ≤ 100kHz MIN 0.001 0.001 600 100 100 100 0 100 1300 1300 600 300 300 1000 160 MAX 0.4 0.4 HIGH-SPEED MODE MIN 0.001 0.001 160 100 100 100 0 10 160 200 60 MAX 3.4 2.75 UNIT MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns 12 Submit Documentation Feedback TMP102 www.ti.com SBOS397 – AUGUST 2007 TWO-WIRE TIMING DIAGRAMS t(LOW) tR tF t(HDSTA) SCL t(HDSTA) t(HDDAT) SDA t(BUF) P S S P t(HIGH) t(SUSTA) t(SUDAT) t(SUSTO) Figure 12. Two-Wire Timing Diagram 1 SCL 9 1 9 ¼ SDA Start By Master 1 0 0 1 0 A1(1) A0(1) R/W ACK By TMP102 0 0 0 0 0 0 P1 P0 ACK By TMP102 ¼ Frame 1 Two-Wire Slave Address Byte 1 SCL (Continued) 9 1 Frame 2 Pointer Register Byte 9 SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 ACK By TMP102 D7 D6 D5 D4 D3 D2 D1 D0 ACK By TMP102 Stop By Master Frame 3 Data Byte 1 NOTE: (1) The value of A0 and A1 are determined by the ADD0 pin. Frame 4 Data Byte 2 Figure 13. Two-Wire Timing Diagram for Write Word Format Submit Documentation Feedback 13 TMP102 www.ti.com SBOS397 – AUGUST 2007 1 SCL 9 1 9 ¼ SDA Start By Master 1 0 0 1 0 A1 (1) A0 (1) R/W ACK By TMP102 0 0 0 0 0 0 P1 P0 ACK By TMP102 Stop By Master Frame 1 Two-Wire Slave Address Byte 1 SCL (Continued) 9 1 Frame 2 Pointer Register Byte 9 ¼ ¼ ACK By Master (2) SDA (Continued) Start By Master 1 0 0 1 0 A1 (1) A0 (1) R/W ACK By TMP102 D7 D6 D5 D4 D3 D2 D1 D0 From TMP102 Frame 4 Data Byte 1 Read Register Frame 3 Two-Wire Slave Address Byte 1 SCL (Continued) 9 SDA (Continued) D7 D6 D5 D4 D3 From TMP102 D2 D1 D0 ACK By Master (3) Stop By Master Frame 5 Data Byte 2 Read Register NOTE: (1) The value of A0 and A1 are determined by the ADD0 pin. (2) Master should leave SDA high to terminate a single-byte read operation. (3) Master should leave SDA high to terminate a two-byte read operation. Figure 14. Two-Wire Timing Diagram for Read Word Format ALERT 1 SCL 9 1 9 SDA Start By Master 0 0 0 1 1 0 0 R/W ACK By TMP102 1 0 0 1 A1 A0 Status From TMP102 NACK By Master Stop By Master Frame 1 SMBus ALERT Response Address Byte NOTE: (1) The value of A0 and A1 are determined by the ADD0 pin. Frame 2 Slave Address From TMP100 Figure 15. Timing Diagram for SMBus ALERT 14 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 15-Aug-2007 PACKAGING INFORMATION Orderable Device TMP102AIDRLR TMP102AIDRLT (1) Status (1) ACTIVE ACTIVE Package Type SOT-553 SOT-553 Package Drawing DRL DRL Pins Package Eco Plan (2) Qty 6 6 4000 Green (RoHS & no Sb/Br) 250 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Aug-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Aug-2007 Device Package Pins Site Reel Diameter (mm) 180 180 Reel Width (mm) 9 9 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 4 4 W Pin1 (mm) Quadrant 8 8 Q3 Q3 TMP102AIDRLR TMP102AIDRLT DRL DRL 6 6 HNT HNT 1.78 1.78 1.78 1.78 0.69 0.69 TAPE AND REEL BOX INFORMATION Device TMP102AIDRLR TMP102AIDRLT Package DRL DRL Pins 6 6 Site HNT HNT Length (mm) 202.0 202.0 Width (mm) 201.0 201.0 Height (mm) 28.0 28.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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