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TMP103
SBOS545D – FEBRUARY 2011 – REVISED DECEMBER 2018
TMP103 Low-Power, Digital Temperature Sensor With Two-Wire Interface in WCSP
1 Features
3 Description
•
The TMP103 is a digital output temperature sensor in
a four-ball wafer chip-scale package (WCSP). The
TMP103 is capable of reading temperatures to a
resolution of 1°C.
1
•
•
•
•
•
•
•
Multiple Device Access (MDA):
– Global Read/Write Operations
I2C™ and SMBus™-Compatible Interface
Resolution: 8 Bits
Accuracy: ±1°C Typical (–10°C to 100°C)
Low Quiescent Current:
– 3-μA Active IQ at 0.25 Hz
– 1-μA Shutdown
Supply Range: 1.4 V to 3.6 V
Digital Output
4-Ball WCSP (DSBGA) Package
2 Applications
•
•
•
•
•
•
•
•
Handsets
Notebooks
SSDs
Servers
Telecom
Set Top Boxes
Low Power Environmental
Sensors
The TMP103 features a two-wire interface that is
compatible with both I2C and SMBus interfaces. In
addition, the interface supports multiple device
access (MDA) commands that allow the master to
communicate with multiple devices on the bus
simultaneously, eliminating the need to send
individual commands to each TMP103 on the bus.
Up to eight TMP103s can be tied together in parallel
and easily read by the host. The TMP103 is
especially suitable for space-constrained, powersensitive applications with multiple temperature
measurement zones that must be monitored.
The TMP103 is specified for operation over a
temperature range of –40°C to 125°C.
Device Information(1)
PART NUMBER
TMP103
PACKAGE
DSBGA (4)
BODY SIZE (NOM)
0.76 mm × 0.76 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
V+
V+
MCU
Out
SCL
IO
SDA
TMP103A
SCL
TMP103B
SDA
SCL
TMP103C
SDA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMP103
SBOS545D – FEBRUARY 2011 – REVISED DECEMBER 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
3
3
4
4
5
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 11
7.5 Programming........................................................... 11
7.6 Register Maps ......................................................... 16
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application ................................................. 19
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2018) to Revision D
•
Page
Changed input voltage maximum value in the Absolute Maximum Ratings table from: (V+) + 0.5) and ≤ 4 to (V+) +
0.3) and ≤ 4 ............................................................................................................................................................................ 3
Changes from Revision A (March 2011) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
•
Added SSDs, Servers, Telecom, Set Top Boxes, Low Power Environmental, and Sensors to Applications section............ 1
Changes from Original (February 2011) to Revision A
•
2
Page
Changed Package-Lead from WCSP-4 to DSBGA-4 in Device Information table ................................................................ 1
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SBOS545D – FEBRUARY 2011 – REVISED DECEMBER 2018
5 Pin Configuration and Functions
YFF Package
4-Ball DSBGA
Top View
B2
B1
SDA
SCL
A2
A1
GND
V+
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
A1
V+
I
Supply voltage
A2
GND
I
Ground
B1
SDA
I/O
B2
SCL
I
Input/output data pin
Input clock pin
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
V+
UNIT
4
V
V
Voltage at SCL and SDA
–0.3
((V+) + 0.3)
and ≤ 4
Operating temperature
–55
150
°C
150
°C
150
°C
TJ
Junction temperature
Tstg
Storage temperature
(1)
MAX
Supply voltage
–60
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±1000
Machine model (MM)
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
+
MAX
UNIT
V
Supply voltage
1.4
3.6
V
TA
Operating free-air temperature
–40
125
°C
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6.4 Thermal Information
TMP103
THERMAL METRIC (1)
YFF (DSBGA)
UNIT
4 BALLS
RθJA
Junction-to-ambient thermal resistance
160
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
75
°C/W
RθJB
Junction-to-board thermal resistance
76
°C/W
ψJT
Junction-to-top characterization parameter
3
°C/W
ψJB
Junction-to-board characterization parameter
74
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
at TA = 25°C and V+ = 1.4 V to 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
125
°C
TEMPERATURE INPUT
Range
Accuracy (temperature
error)
–40
–10°C to 100°C, V+ = 1.8 V
–2
0
2
–40°C to 125°C, V+ = 1.8 V
–3
±1
3
–0.5
±0.2
0.5
°C
vs supply
Resolution
1
°C/V
°C
DIGITAL INPUT/OUTPUT
VIH
0.7 (V+)
V+
–0.5
0.3 (V+)
V > 2 V, IOL = 2 mA
0
0.4
V+ < 2 V, IOL = 2 mA
0
0.2 (V+)
Input logic levels
VIL
IIN
Input current
0 < VIN < (V+) + 0.3 V
1
+
VOL SDA
Output logic levels
Resolution
8
Conversion time
26
CR1 = 0, CR0 = 0 (default)
Conversion modes
V
μA
V
Bit
35
ms
0.25
CR1 = 0, CR0 = 1
1
CR1 = 1, CR0 = 0
4
CR1 = 1, CR0 = 1
Conv/s
8
Timeout time
30
40
ms
3.6
V
POWER SUPPLY
Operating supply range
1.4
+
IQ
ISD
Quiescent current
Shutdown current
Serial bus inactive, CR1 = 0, CR0 = 0 (default), V = 1.8 V
1.5
Serial bus active, SCL frequency = 400 kHz
15
Serial bus active, SCL frequency = 3.4 MHz
85
Serial bus inactive, V+ = 1.8 V
0.5
Serial bus active, SCL frequency = 400 kHz
10
Serial bus active, SCL frequency = 3.4 MHz
80
3
μA
1
μA
TEMPERATURE
4
Specified range
–40
125
°C
Operating range
–55
150
°C
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6.6 Timing Requirements
See
(1)
FAST MODE
HIGH-SPEED MODE
MIN
MAX
MIN
MAX
UNIT
f(SCL)
SCL operating frequency, VS > 1.7 V
0.001
0.4
0.001
3.4
MHz
f(SCL)
SCL operating frequency, VS < 1.7 V
0.001
0.4
0.001
2.75
MHz
t(BUF)
Bus free time between STOP and START condition
600
160
ns
t(HDSTA)
Hold time after repeated START condition.
After this period, the first clock is generated.
100
100
ns
t(SUSTA)
Repeated START condition setup time
100
100
ns
t(SUSTO)
STOP condition setup Time
100
t(HDDAT)
Data hold time
20
t(SUDAT)
Data setup time
100
10
ns
t(LOW)
SCL clock low period, VS > 1.7 V
1300
160
ns
t(LOW)
SCL clock low period, VS < 1.7 V
1300
200
ns
t(HIGH)
SCL clock high period
600
60
ns
tF
Clock/data fall time
tR
Clock/data rise time
tR
Clock/data rise time for SCLK ≤ 100 kHz
(1)
100
400
10
ns
125
300
300
ns
ns
160
1000
ns
ns
Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not guaranteed and not
production tested.
The TMP103 is two-wire and SMBus compatible. Figure 1 to Figure 5 describe the various operations on the
TMP103. Parameters for Figure 1 are defined in Timing Requirements. Bus definitions are:
Bus Idle: Both SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the SDA line, from high to low, while the SCL line is high, defines
a START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from low to high while the SCL line is high defines a
STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and
is determined by the master device.
Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device
that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA
line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into
account. On a master receive, the termination of the data transfer can be signaled by the master generating a
Not-Acknowledge (1) on the last byte transmitted by the slave.
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t(LOW)
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tF
tR
t(HDSTA)
SCL
t(HDSTA)
t(HIGH)
t(SUSTO)
t(SUSTA)
t(HDDAT)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
NOTE: P = STOP, S = START.
Figure 1. Two-Wire Timing Diagram
1
9
1
9
SCL
¼
1
SDA
1
1
0
A2(1)
A1(1)
A0(1)
0
R/W
Start By
Master
0
0
0
0
0
P1
ACK By
TMP103
P0
¼
ACK By
TMP103
Frame 2 Pointer Register Byte
Frame 1 Two-Wire Slave Address Byte
9
1
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
ACK By
TMP103
Stop By
Master
Frame 3 Data Byte
(1)
The value of A0, A1, and A2 are determined by the TMP103 version; see Table 2.
Figure 2. Two-Wire Timing Diagram for Write Word Format
6
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1
9
1
9
SCL
¼
SDA
1
1
1
0
A2
(1)
A1
(1)
A0
(1)
R/W
Start By
Master
0
0
0
0
0
0
P1
P0
ACK By
TMP103
ACK By
TMP103
Frame 1 Two-Wire Slave Address Byte
Stop By
Master
Frame 2 Pointer Register Byte
1
9
1
9
SCL
(Continued)
¼
SDA
(Continued)
1
1
1
0
A2
(1)
A1
(1)
A0
(1)
D7
R/W
Start By
Master
D6
D5
D3
ACK By
TMP103
D2
D1
D0
From
TMP103
Frame 3 Two-Wire Slave Address Byte
(1)
D4
¼
ACK By Stop By
Master Master
Frame 4 Data Byte Read Register
The value of A0, A1, and A2 are determined by the TMP103 version; see Table 2.
Figure 3. Two-Wire Timing Diagram for Read Word Format
1
9
1
9
SCL
¼
0
SDA
0
0
0
0
0
0
0
R/W
Start By
Master
0
0
0
0
0
P1
ACK By
TMP103(1)
P0
¼
ACK By
TMP103(1)
Frame 2 Pointer Register Byte
Frame 1 Two-Wire MDA Write Address Byte
9
1
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
ACK By
TMP103(1)
Stop By
Master
Frame 3 Data Byte
(1)
All TMP103 devices on the bus acknowledge the byte.
Figure 4. Two-Wire Timing Diagram MDA Write Word Format
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1
9
1
9
SCL
¼
SDA
0
0
0
0
0
0
0
R/W
Start By
Master
0
0
0
0
0
0
P1
P0
ACK By
TMP103(1)
ACK By
TMP103(1)
Frame 1 Two-Wire MDA Write Address Byte
Stop By
Master
Frame 2 Pointer Register Byte
1
9
1
9
SCL
(Continued)
¼
SDA
(Continued)
0
0
0
0
0
0
0
D7
R/W
Start By
Master
D6
D5
D4
D2
D1
Frame 3 Two-Wire MDA Read Address Byte
¼
ACK By
Master
(2)
Frame 4 Data Byte Read Register
1
9
D0
From
TMP103A(3)
ACK By
TMP103(1)
1
D3
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
D7
ACK By
From
TMP103B(3)
Master
Frame 5 Data Byte Read Register
(2)
D6
D5
D4
Stop By
Master
D3
D2
D1
D0
From
TMP103C(3)
ACK By
Master
(2)
Stop By
Master
Frame 6 Data Byte Read Register
(1)
All TMP103 devices on the bus acknowledge the byte.
(2)
The master must issue an acknowledge for each byte read to read all of the TMP103 devices on the bus.
(3)
Three TMP103 devices used in this case; up to eight devices can be used (see Table 2).
Figure 5. Two-Wire Timing Diagram MDA Read Word Format Using Figure 16 (Typical Application)
8
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6.7 Typical Characteristics
At TA = 25°C and V+ = 1.8 V, unless otherwise noted.
16
10
14
9
8
12
7
ISD (μA)
IQ (mA)
10
8
6
0
20
40
60
80
1.4 V Supply
1
1.4V Supply
0
-60 -40 -20
3.6 V Supply
4
2
1.8V Supply
2
5
3
3.6V Supply
4
6
0
100 120 140 160
-60
-40 -20
0
Temperature (°C)
60
80
100 120 140 160
Figure 7. Shutdown Current vs Temperature
40
100
38
90
36
80
34
70
32
IQ (μA)
Conversion Time (ms)
40
Temperature (°C)
Figure 6. Quiescent Current vs Temperature
(0.25 Conversions Per Second)
1.4 V Supply
30
20
60
50
28
40
26
30
3.6 V Supply
24
20
22
10
+125 °C
+25 °C
-55 °C
0
20
-60
-40 -20
0
20
40
60
80
1k
100 120 140 160
10k
100k
1M
10M
Bus Frequency (Hz)
Temperature (°C)
Figure 8. Conversion Time vs Temperature
Figure 9. Quiescent Current vs Bus Frequency
(Temperature at 3.3-V Supply)
2.0
Temperature Error (°C)
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-60 -40 -20
0
20
40
60
80
100 120 140 160
Temperature (°C)
Figure 10. Temperature Error vs Temperature
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7 Detailed Description
7.1 Overview
The TMP103 is a digital output temperature sensor in a wafer chip-scale package (WCSP) that is optimal for
thermal management and thermal profiling. The TMP103 includes a two-wire interface that is compatible with
both I2C and SMBus interfaces. In addition, the TMP103 has the capability of executing multiple device access
(MDA) commands that allow multiple TMP103 devices to respond to a single global bus command. MDA
commands reduce communication time and power in a bus that contains multiple TMP103 devices. The TMP103
is specified over a temperature range of –40ºC to 125ºC.
The TMP103 serial interface is designed to support up to eight TMP103 devices on a single bus. The TMP103 is
offered with eight internal interface addresses. Each unique address option can be used as a location or
temperature zone designator. The TMP103 responds to standard I2C and SMBus slave protocols that allow the
internal registers to be written to or read from on an individual basis. The TMP103 also responds to MDA
commands that allow all the devices on the bus to be written to or read from, without having to send the
individual address and commands to each device.
Pullup resistors are required on SCL and SDA. TI also recommends a 0.01-μF bypass capacitor, as shown in
Figure 11.
V+
0.01mF
5
To
Two-Wire
Controller
SCL
1
SDA
6
TMP103
2
GND
NOTE: SCL and SDA pins require pullup resistors.
Figure 11. Typical Connections
The temperature sensor in the TMP103 is the chip itself. Thermal paths run through the package bumps as well
as the package. The lower thermal resistance of metal causes the bumps to provide the primary thermal path.
To maintain accuracy in applications that require air or surface temperature measurement, take care to isolate
the package from ambient air temperature.
7.2 Functional Block Diagram
SCL
SDA
Diode Temp.
Sensor
Control Logic
A/D
Converter
Serial
Interface
Oscillator
Registers
Temperature
GND
10
TMP103
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7.3 Feature Description
The TMP103 is a 1°C resolution digital output temperature sensor offered in a four-ball wafer chip-scale package
(WCSP). The TMP103 features a two-wire interface that is compatible with both I2C and SMBus interfaces.
The serial interface supports multiple device access (MDA) commands that allow the master to communicate
with multiple devices on the bus simultaneously, eliminating the need to send individual commands to each
TMP103 device on the bus. Up to eight TMP103 devices can be tied together in parallel and easily read by the
host.
The TMP103 is an ideal choice for space-constrained and power-sensitive applications with multiple temperature
measurement zones to be monitored.
7.4 Device Functional Modes
7.4.1 Shutdown Mode
Shutdown mode saves maximum power by shutting down all device circuitry other than the serial interface,
reducing current consumption to typically less than 0.5 μA. For details on how to enter shutdown mode, see
Shutdown Mode (M1 = 0, M0 = 0) in Programming.
7.4.2 One-Shot Mode
The TMP103 features a One-Shot Temperature Measurement mode. When the device is in Shutdown mode, the
device can be instructed to complete a one-time temperature measurement before returning to the shutdown
state. This feature is useful for reducing power consumption in the TMP103 when continuous temperature
monitoring is not required.
As a result of the short conversion time, the TMP103 can achieve a higher conversion rate. A single conversion
typically takes 26 ms and a read can take place in less than 20 μs. When using One-Shot mode, 30 or more
conversions per second are possible.
For details on how to enter One-Shot mode, see One-Shot (M1 = 0, M0 = 1) in Programming.
7.4.3 Continuous Conversion Mode
In Continuous Conversion mode, the TMP103 performs temperature conversion at a rate determined by the
conversion rate bits (CR1 and CR0) set in the configuration register. Because the actual temperature conversion
takes only 26 mS, the TMP103 powers down in between conversions and waits for the appropriate delay. For
details on how to enter One-Shot mode, see Continuous Conversion Mode (M1 = 1) and Conversion Rate in
Programming.
7.5 Programming
7.5.1 Temperature Watchdog Function
The TMP103 contains a watchdog function that monitors device temperature and compares the result to the
values stored in the temperature limit registers (THIGH and TLOW) to determine if the device temperature is within
these set limits. If the temperature of the TMP103 becomes greater than the value in the THIGH register, then the
flag-high bit (FH) in the configuration register is set to 1. If the temperature falls below the value in the TLOW
register, then the flag-low bit (FL) is set to 1. If both flag bits remain 0, then the temperature is within the
temperature window set by the temperature limit registers, as shown in Figure 12.
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Programming (continued)
THIGH
Measured
Temperature
TLOW
FH Bit
(Transparent Mode)
FL Bit
(Transparent Mode)
FH Bit
(Latch Mode)
FL Bit
(Latch Mode)
Read
Read
Read
Time
Figure 12. Temperature Flag Functional Diagram
The latch bit (LC) in the configuration register is used to latch the value of the flag bits (FH and FL) until the
master issues a read command to the configuration register. The flag bits are set to 0 if a read command is
received by the TMP103, or if LC = 0 and the temperature is within the temperature limits. The power-on default
values for these bits are FH = 0, FL = 0, and LC = 0.
7.5.2 Conversion Rate
The conversion rate bits, CR1 and CR0 located in the Configuration Register, configure the TMP103 for
conversion rates of 8 Hz, 4 Hz, 1 Hz, or 0.25 Hz (default). The TMP103 has a typical conversion time of 26 ms.
To achieve different conversion rates, the TMP103 performs a single conversion and then powers down and
waits for the appropriate delay set by CR1 and CR0. Table 1 lists the settings for CR1 and CR0.
Table 1. Conversion Rate Settings
12
CR1
CR0
CONVERSION RATE
0
0
0.25 Hz (default)
0
1
1 Hz
1
0
4 Hz
1
1
8 Hz
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After power up or general-call reset, the TMP103 immediately starts a conversion, as shown in Figure 13. The
first result is available after 26 ms (typical). The active quiescent current during conversion is 40 μA (typical at
27°C, V+ = 1.8 V). The quiescent current during delay is 1 μA (typical at 27°C, V+ = 1.8 V).
Delay
(1)
26ms
26ms
Startup
(1)
Start of
Conversion
Delay is set by CR1 and CR0.
Figure 13. Conversion Start
7.5.3 Shutdown Mode (M1 = 0, M0 = 0)
Shutdown mode saves maximum power by shutting down all device circuitry other than the serial interface,
reducing current consumption to typically less than 0.5 μA. Shutdown mode is enabled when bits M1 and M0 (in
the Configuration Register) = 00. The device shuts down when the current conversion is completed.
7.5.4 One-Shot (M1 = 0, M0 = 1)
The TMP103 features a One-Shot Temperature Measurement mode. When the device is in Shutdown mode,
writing a 01 to bits M1 and M0 starts a single temperature conversion. During the conversion, bits M1 and M0
read 01. The device returns to the shutdown state at the completion of the single conversion. After the
conversion, bits M1 and M0 read 00. This feature is useful for reducing power consumption in the TMP103 when
continuous temperature monitoring is not required.
As a result of the short conversion time, the TMP103 can achieve a higher conversion rate. A single conversion
typically takes 26 ms and a read can take place in less than 20 μs. When using One-Shot mode, 30 or more
conversions per second are possible.
7.5.5 Continuous Conversion Mode (M1 = 1)
When the TMP103 is in Continuous Conversion mode (M1 = 1), a single conversion is performed at a rate
determined by the conversion rate bits, CR1 and CR0 (in the Configuration Register). The TMP103 performs a
single conversion and then powers down and waits for the appropriate delay set by CR1 and CR0. See Table 1
for CR1 and CR0 settings.
7.5.6 Bus Overview
The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The
bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions.
To address a specific device, a START condition is initiated, indicated by pulling the data line (SDA) from a high
to low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge of the
clock, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the
slave being addressed responds to the master by generating an Acknowledge and pulling SDA low.
Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data
transfer, SDA must remain stable while SCL is high, because any change in SDA while SCL is high is interpreted
as a START or STOP signal.
Once all data have been transferred, the master generates a STOP condition indicated by pulling SDA from low
to high, while SCL is high.
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7.5.7 Serial Interface
The TMP103 operates as a slave device only on the two-wire bus and SMBus. Connections to the bus are made
through the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression
filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP103 supports the
transmission protocol for both fast (1 kHz to 400 kHz) and high-speed (1 kHz to 3.4 MHz) modes. All data bytes
are transmitted MSB first.
7.5.8 Serial Bus Address
To communicate with the TMP103, the master must first address slave devices through a slave address byte.
The slave address byte consists of seven address bits, and a direction bit that indicates the intent of executing a
read or write operation.
The TMP103 is available in eight versions, each with a different slave address, as shown in Table 2. These
addresses can be used as either a location or a temperature zone designator.
Table 2. Device Slave Addresses
PRODUCT
TWO-WIRE ADDRESS
TEMPERATURE ZONE
TMP103A
1110000
Zone1
TMP103B
1110001
Zone2
TMP103C
1110010
Zone3
TMP103D
1110011
Zone4
TMP103E
1110100
Zone5
TMP103F
1110101
Zone6
TMP103G
1110110
Zone7
TMP103H
1110111
Zone8
7.5.9 Writing and Reading Operation
Accessing a particular register on the TMP103 is accomplished by writing the appropriate value to the Pointer
Register. The value for the Pointer Register is the first byte transferred after the slave address byte with the R/W
bit low. Every write operation to the TMP103 requires a value for the Pointer Register (see Figure 2).
When reading from the TMP103, the last value stored in the Pointer Register by a write operation is used to
determine which register is read by a read operation. To change the register pointer for a read operation, a new
value must be written to the Pointer Register. This action is accomplished by issuing a slave address byte with
the R/W bit low, followed by the Pointer Register byte. No additional data are required. The master can then
generate a START condition and send the slave address byte with the R/W bit high to initiate the read command.
See Figure 3 for details of this sequence. If repeated reads from the same register are desired, it is not
necessary to continually send the Pointer Register bytes; the TMP103 remembers the Pointer Register value
until it is changed by the next write operation, or the TMP103 is reset.
7.5.10 Slave Mode Operations
The TMP103 can operate as a slave receiver or slave transmitter. As a slave device, the TMP103 never drives
the SCL line.
7.5.10.1 Slave Receiver Mode
The first byte transmitted by the master is the slave address, with the R/W bit low. The TMP103 then
acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer Register. The
TMP103 then acknowledges reception of the Pointer Register byte. The next byte is written to the register
addressed by the Pointer Register. The TMP103 acknowledges reception of the data byte. The master can
terminate data transfer by generating a START or STOP condition.
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7.5.10.2 Slave Transmitter Mode
The first byte transmitted by the master is the slave address, with the R/W bit high. The slave acknowledges
reception of a valid slave address. The next byte is transmitted by the slave of the register indicated by the
Pointer Register. The master acknowledges reception of the data byte. The master can terminate data transfer
by generating a Not-Acknowledge on reception of the data byte, or generating a START or STOP condition.
7.5.11 General Call
The TMP103 responds to a two-wire General Call address (0000000) if the eighth bit is 0. The device
acknowledges the General Call address and responds to commands in the second byte. If the second byte is
00000110, the TMP103 internal registers are reset to power-up values. The TMP103 does not support the
General Address acquire command.
7.5.12 High-Speed (Hs) Mode
For the two-wire bus to operate at frequencies greater than 400 kHz, the master device must issue an Hs-mode
master code (00001xxx) as the first byte after a START condition to switch the bus to high-speed operation. The
TMP103 does not acknowledge this byte, but switches its input filters on SDA and SCL and its output filters on
SDA to operate in Hs-mode, allowing transfers at up to 3.4 MHz. After the Hs-mode master code has been
issued, the master transmits a START condition followed by a two-wire slave address to initiate a data transfer
operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving
the STOP condition, the TMP103 switches the input and output filters back to the default fast-mode operation.
7.5.13 Timeout Function
The TMP103 resets the serial interface if SCL is held low for 30 ms (typical). The TMP103 releases the bus if it is
pulled low and waits for a START condition. To avoid activating the timeout function, it is necessary to maintain a
communication speed of at least 1 kHz for SCL operating frequency.
7.5.14 Multiple Device Access
The TMP103 supports Multiple Device Access (MDA), which allows the master to communicate with multiple
TMP103 devices on the same bus interface with one interface transaction. MDA commands consist of an MDA
read address (00000001) and an MDA write address (00000000). The device acknowledges the MDA address
and responds to the command accordingly. For the MDA to function correctly, different product versions of the
TMP103 must be used in the system; see Table 2.
7.5.14.1 Multiple Device Access Write
The master transmits an MDA write address followed by the pointer address of the register to be accessed; see
Table 4. Following the pointer, all of the TMP103 devices on the bus acknowledge and wait for the next byte of
data to be written to the addressed registers. When the data byte is received by the TMP103 devices, they store
and acknowledge the transmitted byte. The TMP103 devices store the same data on all devices on the bus in
one transaction; see Figure 4.
7.5.14.2 Multiple Device Access Read
Before an MDA read transaction can begin, the master must first send an MDA write transaction to set the
appropriate pointer address of the register to be accessed, as stated in the previous section. The master can
then transmit an MDA read address followed by a read byte for each TMP103 used on the bus. For example, if a
TMP103A and TMP103B are used on the same bus and an MDA read address is sent, the address must be
followed by two bytes of data and two master acknowledges. The TMP103A sends data on the first byte and the
TMP103B sends data on the second byte. The master must issue an acknowledge for each byte read to read all
of the TMP103 devices on the bus; see Figure 5. If the master does not acknowledge each byte of data, the
TMP103s stop sending subsequent data for any remaining devices.
Up to eight TMP103 devices can be on the same bus and respond to MDA commands; see Table 2.
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NOTE
If the bus contains an incomplete sequence of TMP103 device addresses, the master
must transmit all required dummy bytes for the missing device address to allow for normal
MDA read operation. For example, if the TMP103A, TMP103B, and TMP103D devices are
on the bus, the master must transmit an MDA read address followed by four bytes and
four acknowledges to complete the MDA read transaction.
7.5.15 NOISE
The TMP103 is a very low-power device and generates very low noise on the supply bus. Applying an RC filter
to the V+ pin of the TMP103 can further reduce any noise the TMP103 might propagate to other components. RF
in Figure 14 should be less than 5 kΩ and CF should be greater than 10 nF.
Supply Voltage
RF £ 5kW
SCL
SDA
TMP103
GND
V+
CF ³ 10nF
Figure 14. Noise Reduction
7.6 Register Maps
7.6.1 Pointer Register
Figure 15 shows the internal register structure of the TMP103. The 8-bit Pointer Register of the device is used to
address a given data register. The Pointer Register uses the two LSBs to identify which of the data registers
should respond to a read or write command. Table 3 identifies the bits of the Pointer Register byte. During a
write command, P2 through P7 must always be 0. Table 4 describes the pointer address of the registers
available in the TMP103. Power-up reset value of P1/P0 is 00. By default, the TMP103 reads the temperature on
power up.
Pointer
Register
Temperature
Register
Configuration
Register
TLOW
Register
SCL
I/O
Control
Interface
SDA
THIGH
Register
Figure 15. Internal Register Structure
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Register Maps (continued)
Table 3. Pointer Register Byte
P7
P6
P5
P4
P3
P2
0
0
0
0
0
0
P1
P0
Register Bits
Table 4. Pointer Addresses
P1
P0
REGISTER
0
0
Temperature Register (Read Only)
0
1
Configuration Register (Read/Write)
1
0
TLOW Register (Read/Write)
1
1
THIGH Register (Read/Write)
7.6.2 Temperature Register
The Temperature Register of the TMP103 device is configured as an eight-bit, read-only register that stores the
output of the most recent conversion. A single byte must be read to obtain data, and is described in Table 5. The
data format for temperature is summarized in Table 6. One LSB equals 1°C.
Table 5. Temperature Register
D7
D6
D5
D4
D3
D2
D1
D0
T7
T6
T5
T4
T3
T2
T1
T0
Negative numbers are represented in binary twos complement format. Following power up or reset, the
Temperature Register reads 0°C until the first conversion is complete.
Table 6. 8-Bit Temperature Data Format (1)
(1)
TEMPERATURE (°C)
DIGITAL OUTPUT (BINARY)
HEX
128
0111 1111
7F
127
0111 1111
7F
100
0110 0100
64
80
0101 0000
50
75
0100 1011
4B
50
0011 0010
32
25
0001 1001
19
0
0000 0000
00
–1
1111 1111
FF
–25
1110 0111
E7
–55
1100 1001
C9
The resolution for the ADC is 1°C/count, where count is equal to the digital output of the ADC.
For positive temperatures (for example, 50°C):
Twos complement is not performed on positive numbers. Therefore, simply convert the number to binary
code, left-justified format. Denote a positive number with MSB = 0.
Example: (50°C)/(1°C/count) = 50 = 32h = 0011 0010
For negative temperatures (for example, –25°C):
Generate the twos complement of a negative number by complementing the absolute value binary number
and adding 1. Denote a negative number with MSB = 1.
Example: (|–25°C|)/(1°C/count) = 25 = 19h = 0001 1001
Twos complement format: 1110 0110 + 1 = 1110 0111
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7.6.3 Configuration Register
The Configuration Register is an eight-bit read/write register used to store bits that control the operational modes
of the temperature sensor. Read/write operations are performed MSB first. The format and power-up and reset
value of the Configuration Register is shown in Table 7. All registers are updated at the end of the data byte.
Table 7. Configuration and Power-Up and Reset Format
D7
D6
D5
D4
D3
D2
D1
D0
ID
CR1
CR0
FH
FL
LC
M1
M0
0
0
0
0
0
0
1
0
7.6.4 Temperature Limit Registers
The THIGH and TLOW registers are used to store the temperature limit thresholds for the TMP103 watchdog
function. At the end of each temperature measurement, the TMP103 compares the temperature results to each
of these limits. If the temperature result is greater than the THIGH limit, then the FH bit in the configuration register
is set to 1. If the temperature result is less than the TLOW limit, then the FL bit in the configuration register is set
to 1; see Figure 12.
Table 8 and Table 9 describe the format for the THIGH and TLOW registers. Power-up reset values for THIGH and
TLOW are: THIGH = 60°C and TLOW = –10°C. The format of the data for THIGH and TLOW is the same as for the
Temperature Register.
Table 8. THIGH Register
D7
D6
D5
D4
D3
D2
D1
D0
H7
H6
H5
H4
H3
H2
H1
H0
Table 9. TLOW Register
18
D7
D6
D5
D4
D3
D2
D1
D0
L7
L6
L5
L4
L3
L2
L1
L0
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TMP103 is a digital output temperature sensor in a DSBGA package that is optimal for thermal management
and thermal profiling. The TMP103 includes a two-wire interface that is compatible with both I2C and SMBus
interfaces. In addition, the TMP103 has the capability of executing multiple device access (MDA) commands that
allows multiple TMP103 devices to respond to a single global bus command. MDA commands reduce
communication time and power in a bus that contains multiple TMP103 devices. The TMP103 is specified over a
temperature range of –40ºC to 125ºC.
The TMP103 serial interface is designed to support up to eight TMP103 devices on a single bus. The TMP103 is
offered with eight internal interface addresses. Each unique address option can be used as a location or
temperature zone designator. The TMP103 responds to standard I2C and SMBus slave protocols that allow the
internal registers to be written to or read from on an individual basis. The TMP103 also responds to MDA
commands that allow all the devices on the bus to be written to or read from, without having to send the
individual address and commands to each device.
8.2 Typical Application
V+
V+
MCU
Out
SCL
IO
SDA
SCL
TMP103A
TMP103B
SDA
SCL
TMP103C
SDA
Figure 16. Typical Application Diagram
8.2.1 Design Requirements
The TMP103 device requires pullup resistors on the SCL and SDA pins. The pullup resistor values must be
selected such that the maximum current sinking capability of I/O pins is not violated. TI recommends a 0.01-μF
bypass capacitor on the supply.
8.2.2 Detailed Design Procedure
The TMP103 devices must be placed in close proximity to the heat source that must be monitored, with a proper
layout for good thermal coupling. This placement ensures that temperature changes are captured within the
shortest possible time interval. To maintain accuracy in applications that require air or surface temperature
measurement, take care to isolate the package and leads from ambient air temperature. The TMP103 device is a
very low-power device and generates very low noise on the supply bus. Applying an RC filter to the V+ pin of the
TMP103 device can further reduce any noise that the TMP103 device might propagate to other components.
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Typical Application (continued)
8.2.3 Application Curve
Table 9 shows the step response of the TMP103 device to a submersion in an oil bath of 100ºC from room
temperature (25ºC). The time-constant, or the time for the output to reach 63% of the input step, is 1.4 s. The
time-constant result depends on the printed-circuit-board (PCB) that the TMP103 device is mounted. For this
test, there are eight TMP103 devices soldered to a two-layer PCB that measured 2 in × 2 in, and the PCB
thickness is 64 mils.
100
Temperature(°C)
80
60
40
20
-5
0
5
10
15
20
25
30
Time (S)
Figure 17. Temperature vs Time
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9 Power Supply Recommendations
The TMP103 device operates with power supply in the range of 1.4 V to 3.6 V. The device is optimized for
operation at 3.3-V supply but can measure temperature accurately in the full supply range. A power-supply
bypass capacitor is required for proper operation. Place this capacitor as close as possible to the supply and
ground pins of the device. A typical value for this supply bypass capacitor is 0.01 μF. Applications with noisy or
high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise.
10 Layout
10.1 Layout Guidelines
Place the power-supply bypass capacitor as close as possible to the supply pin. The recommended value of this
bypass capacitor is 0.01 μF. Additional decoupling capacitance can be added to compensate for noisy or highimpedance power supplies. Pull up the SDA and SCL pins through 5-kΩ pullup resistors.
10.2 Layout Example
Via to Power and Ground Plane
Via to other signal layers
SDA
SCL
TMP103A
V+
GND
SDA
SCL
TMP103B
V+
GND
Supply Voltage
SDA
SCL
TMP103H
V+
GND
Figure 18. Recommended Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
SMBus is a trademark of Intel.
I2C is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMP103AYFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TA
TMP103AYFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TA
TMP103BYFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TB
TMP103BYFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TB
TMP103CYFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TC
TMP103CYFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TC
TMP103DYFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TD
TMP103DYFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TD
TMP103EYFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TE
TMP103EYFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TE
TMP103FYFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TF
TMP103FYFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TF
TMP103GYFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TG
TMP103GYFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TG
TMP103HYFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TH
TMP103HYFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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10-Dec-2020
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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