TMP103
ZHCS095A – MARCH 2011 – REVISED MARCH 2011
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采用晶圆级芯片规模封装 (WCSP) 并具有两线式接口的
低功耗、数字温度传感器
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特性
说明
• 多器件存取 (MDA)：
– 全局读/写操作
• I2C™/ SMBus™ 兼容型接口
• 分辨率： 8 位
• 准确度： 典型值为 ±1℃ （―40℃ 至 +100℃）
• 低静态电流：
– 运行模式中的 IQ 为 3μA （在 0.25Hz 频率条件
下）
– 停机模式中为 IQ 为 1μA
• 电源范围： 1.4V 至 3.6V
• 数字输出
• 封装： 4 焊球 WCSP （晶圆级芯片规模封装）
(DSBGA)
TMP103 是一款采用 4 焊球晶圆级芯片规模封装
(WCSP) 的数字输出温度传感器。 TMP103 读取温度
的分辨率能够达到 1℃。
1
234
TMP103 具有一个与 I2C 和 SMBus 接口均兼容的两线
式接口。 此外，该接口还支持多器件存取 (MDA) 命
令，允许主控器与总线上的多个器件同时进行通信，从
而不必向总线上的每个 TMP103 个别发送命令。
最多可以把 8 个 TMP103 并联连接起来，并由主机轻
松地对其进行读取。 对于那些具有多个必须加以监视
的温度测量区域的空间受限、功耗敏感型应用而
言，TMP103 是特别理想的选择。
TMP103 的规定工作温度范围为－40℃ 至 +125℃。
应用
•
•
手机
笔记本电脑
典型应用
V+
V+
MCU
Out
SCL
TMP103A
IO
SDA
SCL
TMP103B
SDA
SCL
TMP103C
SDA
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SMBus is a trademark of Intel.
I2C is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
English Data Sheet: SBOS545A
TMP103
ZHCS095A – MARCH 2011 – REVISED MARCH 2011
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
ADDRESS
PACKAGE-LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
TMP103A
1110000
DSBGA-4
YFF
TA
TMP103B
1110001
DSBGA-4
YFF
TB
TMP103C
1110010
DSBGA-4
YFF
TC
TMP103D
1110011
DSBGA-4
YFF
TD
TMP103E
1110100
DSBGA-4
YFF
TE
TMP103F
(1)
(1)
1110101
DSBGA-4
YFF
TF
TMP103G
1110110
DSBGA-4
YFF
TG
TMP103H
1110111
DSBGA-4
YFF
TH
ORDERING
NUMBER
TMP103AYFFR
TMP103AYFFT
TMP103BYFFR
TMP103BYFFT
TMP103CYFFR
TMP103CYFFT
TMP103DYFFR
TMP103DYFFT
TMP103EYFFR
TMP103EYFFT
TMP103FYFFR
TMP103FYFFT
TMP103GYFFR
TMP103GYFFT
TMP103HYFFR
TMP103HYFFT
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device prodict folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
TMP103
UNIT
Supply Voltage
3.6
V
Input Voltage (2)
–0.3 to (V+) + 0.3
V
Operating Temperature
–55 to +150
°C
Storage Temperature
–60 to +150
°C
Junction Temperature
+150
°C
Human Body Model (HBM)
2000
V
Charged Device Model (CDM)
1000
V
Machine Model (MM)
200
V
ESD Rating
(1)
(2)
2
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
Input voltage rating applies to all TMP103 input voltages.
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THERMAL INFORMATION
TMP103
THERMAL METRIC (1)
YFF
UNITS
4
θJA
Junction-to-ambient thermal resistance
160
θJCtop
Junction-to-case (top) thermal resistance
75
θJB
Junction-to-board thermal resistance
76
ψJT
Junction-to-top characterization parameter
3
ψJB
Junction-to-board characterization parameter
74
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
(1)
°C/W
有关传统和新的热度量的更多信息，请参阅 IC 封装热度量 应用报告 SPRA953。
ELECTRICAL CHARACTERISTICS
At TA = +25°C and V+ = +1.4V to +3.6V, unless otherwise noted.
TMP103
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEMPERATURE INPUT
+125
°C
–10°C to +100°C, V+ = 1.8V
–40
0
±2
°C
–40°C to +125°C, V+ = 1.8V
±1
±3
±0.2
±0.5
Range
Accuracy (Temperature Error)
vs Supply
Resolution
°C
°C/V
°C
1.0
DIGITAL INPUT/OUTPUT
Input Logic Levels
Input Current
Output Logic Levels
VIH
0.7 (V+)
V+
VIL
–0.5
0.3 (V+)
V
1
μA
V
0 < VIN < (V+) + 0.3V
IIN
VOL SDA
V+ > 2V, IOL = 2mA
0
0.4
V+ < 2V, IOL = 2mA
0
0.2 (V+)
Resolution
V
V
8
Conversion Time
26
CR1 = 0, CR0 = 0 (default)
Conversion Modes
Bit
35
ms
0.25
Conv/s
CR1 = 0, CR0 = 1
1
Conv/s
CR1 = 1, CR0 = 0
4
Conv/s
CR1 = 1, CR0 = 1
8
Timeout Time
30
Conv/s
40
ms
POWER SUPPLY
Operating Supply Range
Quiescent Current
Shutdown Current
+1.4
Serial Bus Inactive, CR1 = 0, CR0 = 0 (default), V+ = 1.8V
1.5
IQ
ISD
+3.6
V
3
μA
μA
Serial Bus Active, SCL Frequency = 400kHz
15
Serial Bus Active, SCL Frequency = 3.4MHz
85
Serial Bus Inactive, V+ = 1.8V
0.5
Serial Bus Active, SCL Frequency = 400kHz
10
μA
Serial Bus Active, SCL Frequency = 3.4MHz
80
μA
μA
1
μA
TEMPERATURE
Specified Range
–40
+125
°C
Operating Range
–55
+150
°C
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PIN CONFIGURATION
YFF PACKAGE
WCSP-4 (DSBGA-4)
(TOP VIEW)
B2
B1
SDA
SCL
A2
A1
GND
V+
PIN DESCRIPTIONS
PIN
NO.
4
NAME
DESCRIPTION
A1
V+
Supply voltage
A2
GND
Ground
B1
SDA
Input/output data pin
B2
SCL
Input clock pin
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TYPICAL CHARACTERISTICS
At TA = +25°C and V+ = 1.8V, unless otherwise noted.
QUIESCENT CURRENT vs TEMPERATURE
(0.25 Conversions per Second)
SHUTDOWN CURRENT vs TEMPERATURE
16
10
14
9
8
12
7
ISD (mA)
IQ (mA)
10
8
6
1.4V Supply
1
1.4V Supply
0
0
-60 -40 -20
0
20
40
60
80
100 120 140 160
-60 -40 -20
40
60
80
100 120 140 160
Figure 1.
Figure 2.
CONVERSION TIME vs TEMPERATURE
QUIESCENT CURRENT vs BUS FREQUENCY
(Temperature at 3.3V Supply)
100
38
90
36
80
34
70
30
20
Temperature (°C)
40
32
0
Temperature (°C)
IQ (mA)
Conversion Time (ms)
3.6V Supply
4
2
1.8V Supply
2
5
3
3.6V Supply
4
6
1.4V Supply
60
50
40
28
26
+125°C
30
3.6V Supply
24
20
22
10
+25°C
-55°C
0
20
-60 -40 -20
0
20
40
60
80
1k
100 120 140 160
10k
100k
1M
10M
Bus Frequency (Hz)
Temperature (°C)
Figure 3.
Figure 4.
TEMPERATURE ERROR vs TEMPERATURE
2.0
Temperature Error (°C)
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-60 -40 -20
0
20
40
60
80
100 120 140 160
Temperature (°C)
Figure 5.
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APPLICATION INFORMATION
GENERAL DESCRIPTION
The TMP103 is a digital output temperature sensor in
a wafer chip-scale package (WCSP) that is optimal
for thermal management and thermal profiling. The
TMP103 includes a two-wire interface that is
compatible with both I2C and SMBus interfaces. In
addition, the TMP103 has the capability of executing
multiple device access (MDA) commands that allow
multiple TMP103s to respond to a single global bus
command. MDA commands reduce communication
time and power in a bus that contains multiple
TMP103 devices. The TMP103 is specified over a
temperature range of –40ºC to +125 ºC.
The TMP103 serial interface is designed to support
up to eight TMP103 devices on a single bus. The
TMP103 is offered with eight internal interface
addresses. Each unique address option can be used
as a location or temperature zone designator. The
TMP103 responds to standard I2C/SMBus slave
protocols that allow the internal registers to be written
to or read from on an individual basis. The TMP103
also responds to MDA commands that allow all the
devices on the bus to be written to or read from,
without having to send the individual address and
commands to each device.
To maintain accuracy in applications that require air
or surface temperature measurement, care should be
taken to isolate the package from ambient air
temperature.
POINTER REGISTER
Figure 7 shows the internal register structure of the
TMP103. The 8-bit Pointer Register of the device is
used to address a given data register. The Pointer
Register uses the two LSBs to identify which of the
data registers should respond to a read or write
command. Table 1 identifies the bits of the Pointer
Register byte. During a write command, P2 through
P7 must always be '0'. Table 2 describes the pointer
address of the registers available in the TMP103.
Power-up reset value of P1/P0 is '00'. By default, the
TMP103 reads the temperature on power-up.
Pointer
Register
Temperature
Register
Pull-up resistors are required on SCL and SDA. A
0.01μF bypass capacitor is also recommended, as
shown in Figure 6.
0.01mF
1
SDA
6
SDA
THIGH
Register
5
SCL
I/O
Control
Interface
TLOW
Register
V+
To
Two-Wire
Controller
SCL
Configuration
Register
TMP103
Figure 7. Internal Register Structure
2
Table 1. Pointer Register Byte
GND
P7
P6
P5
P4
P3
P2
0
0
0
0
0
0
P0
Register Bits
Table 2. Pointer Addresses
NOTE: SCL and SDA pins require pull-up resistors.
Figure 6. Typical Connections
The temperature sensor in the TMP103 is the chip
itself. Thermal paths run through the package bumps
as well as the package. The lower thermal resistance
of metal causes the bumps to provide the primary
thermal path.
6
P1
P1
P0
REGISTER
0
0
Temperature Register (Read Only)
0
1
Configuration Register (Read/Write)
1
0
TLOW Register (Read/Write)
1
1
THIGH Register (Read/Write)
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Table 3. Temperature Register
TEMPERATURE REGISTER
The Temperature Register of the TMP103 is
configured as an eight-bit, read-only register that
stores the output of the most recent conversion. A
single byte must be read to obtain data, and is
described in Table 3. The data format for temperature
is summarized in Table 4. One LSB equals 1°C.
D7
D6
D5
D4
D3
D2
D1
D0
T7
T6
T5
T4
T3
T2
T1
T0
Negative numbers are represented in binary twos
complement format. Following power-up or reset, the
Temperature Register reads 0°C until the first
conversion is complete.
Table 4. 8-Bit Temperature Data Format (1)
(1)
TEMPERATURE (°C)
DIGITAL OUTPUT (BINARY)
HEX
128
0111 1111
7F
127
0111 1111
7F
100
0110 0100
64
80
0101 0000
50
75
0100 1011
4B
50
0011 0010
32
25
0001 1001
19
0
0000 0000
00
FF
–1
1111 1111
–25
1110 0111
E7
–55
1100 1001
C9
The resolution for the ADC is 1°C/count, where count is equal to the digital output of the ADC.
For positive temperatures (for example, +50°C):
Twos complement is not performed on positive numbers. Therefore, simply convert the number to binary
code, left-justified format. Denote a positive number with MSB = '0'.
Example: (+50°C)/(1°C/count) = 50 = 32h = 0011 0010
For negative temperatures (for example, –25°C):
Generate the twos complement of a negative number by complementing the absolute value binary number
and adding 1. Denote a negative number with MSB = '1'.
Example: (|–25°C|)/(1°C/count) = 25 = 19h = 0001 1001
Twos complement format: 1110 0110 + 1 = 1110 0111
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CONFIGURATION REGISTER
The Configuration Register is an eight-bit read/write
register used to store bits that control the operational
modes of the temperature sensor. Read/write
operations are performed MSB first. The format and
power-up/reset value of the Configuration Register is
shown in Table 5. All registers are updated at the end
of the data byte.
Table 5. Configuration and Power-Up/Reset
Format
D7
D6
D5
D4
D3
D2
D1
D0
ID
CR1
CR0
FH
FL
LC
M1
M0
0
0
0
0
0
0
1
0
TEMPERATURE WATCHDOG FUNCTION
The TMP103 contains a watchdog function that
monitors device temperature and compares the result
to the values stored in the temperature limit registers
(THIGH and TLOW) in order to determine if the device
temperature is within these set limits. If the
temperature of the TMP103 becomes greater than
the value in the THIGH register, then the flag-high bit
(FH) in the configuration register is set to '1'. If the
temperature falls below value in the TLOW register,
then the flag-low bit (FL) is set to '1'. If both flag bits
remain '0', then the temperature is within the
temperature window set by the temperature limit
registers, as shown in Figure 8.
THIGH
Measured
Temperature
The latch bit (LC) in the configuration register is used
to latch the value of the flag bits (FH and FL) until the
master issues a read command to the configuration
register. The flag bits are set to '0' if a read command
is received by the TMP103, or if LC = '0' and the
temperature is within the temperature limits. The
power-on default values for these bits are FH = '0',
FL = '0', and LC = '0'.
CONVERSION RATE
The conversion rate bits, CR1 and CR0 located in the
Configuration Register, configure the TMP103 for
conversion
rates
of
8Hz,
4Hz, 1Hz,
or
0.25Hz (default). The TMP103 has a typical
conversion time of 26ms. To achieve different
conversion rates, the TMP103 performs a single
conversion and then powers down and waits for the
appropriate delay set by CR1 and CR0. Table 6
shows the settings for CR1 and CR0.
Table 6. Conversion Rate Settings
CR1
CR0
CONVERSION RATE
0
0
0.25Hz (default)
0
1
1Hz
1
0
4Hz
1
1
8Hz
After power-up or general-call reset, the TMP103
immediately starts a conversion, as shown in
Figure 9. The first result is available after 26ms
(typical). The active quiescent current during
conversion is 40μA (typical at +27°C, V+ = 1.8V). The
quiescent current during delay is 1.0μA (typical at
+27°C, V+ = 1.8V).
TLOW
Delay
(1)
26ms
FH Bit
(Transparent Mode)
26ms
FL Bit
(Transparent Mode)
Startup
FH Bit
(Latch Mode)
Start of
Conversion
(1) Delay is set by CR1 and CR0.
Figure 9. Conversion Start
FL Bit
(Latch Mode)
SHUTDOWN MODE (M1 = '0', M0 = '0')
Read
Read
Read
Time
Figure 8. Temperature Flag Functional Diagram
8
Shutdown mode saves maximum power by shutting
down all device circuitry other than the serial
interface, reducing current consumption to typically
less than 0.5μA. Shutdown mode is enabled when
bits M1 and M0 (in the Configuration Register) = '00'.
The device shuts down when the current conversion
is completed.
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Table 7. THIGH Register
ONE-SHOT (M1 = '0', M0 = '1')
The TMP103 features a One-Shot Temperature
Measurement mode. When the device is in Shutdown
mode, writing a '01' to bits M1 and M0 starts a single
temperature conversion. During the conversion, bits
M1 and M0 read '01'. The device returns to the
shutdown state at the completion of the single
conversion. After the conversion, bits M1 and M0
read '00'. This feature is useful for reducing power
consumption in the TMP103 when continuous
temperature monitoring is not required.
As a result of the short conversion time, the TMP103
can achieve a higher conversion rate. A single
conversion typically takes 26ms and a read can take
place in less than 20μs. When using One-Shot mode,
30 or more conversions per second are possible.
CONTINUOUS CONVERSION MODE (M1 = '1')
When the TMP103 is in Continuous Conversion mode
(M1 = '1'), a single conversion is performed at a rate
determined by the conversion rate bits, CR1 and CR0
(in the Configuration Register). The TMP103
performs a single conversion and then powers down
and waits for the appropriate delay set by CR1 and
CR0. See Table 6 for CR1 and CR0 settings.
TEMPERATURE LIMIT REGISTERS
The THIGH and TLOW registers are used to store the
temperature limit thresholds for the TMP103
watchdog function. At the end of each temperature
measurement,
the
TMP103
compares
the
temperature results to each of these limits. If the
temperature result is greater than the THIGH limit, then
the FH bit in the configuration register is set to '1'. If
the temperature result is less than the TLOW limit, then
the FL bit in the configuration register is set to '1'; see
Figure 8.
Table 7 and Table 8 describe the format for the THIGH
and TLOW registers. Power-up reset values for THIGH
and TLOW are: THIGH = +60°C and TLOW = –10°C. The
format of the data for THIGH and TLOW is the same as
for the Temperature Register.
D7
D6
D5
D4
D3
D2
D1
D0
H7
H6
H5
H4
H3
H2
H1
H0
Table 8. TLOW Register
D7
D6
D5
D4
D3
D2
D1
D0
L7
L6
L5
L4
L3
L2
L1
L0
BUS OVERVIEW
The device that initiates the transfer is called a
master, and the devices controlled by the master are
slaves. The bus must be controlled by a master
device that generates the serial clock (SCL), controls
the bus access, and generates the START and STOP
conditions.
To address a specific device, a START condition is
initiated, indicated by pulling the data line (SDA) from
a high to low logic level while SCL is high. All slaves
on the bus shift in the slave address byte on the
rising edge of the clock, with the last bit indicating
whether a read or write operation is intended. During
the ninth clock pulse, the slave being addressed
responds to the master by generating an
Acknowledge and pulling SDA low.
Data transfer is then initiated and sent over eight
clock pulses followed by an Acknowledge Bit. During
data transfer, SDA must remain stable while SCL is
high, because any change in SDA while SCL is high
is interpreted as a START or STOP signal.
Once all data have been transferred, the master
generates a STOP condition indicated by pulling SDA
from low to high, while SCL is high.
SERIAL INTERFACE
The TMP103 operates as a slave device only on the
two-wire bus and SMBus. Connections to the bus are
made via the open-drain I/O lines SDA and SCL. The
SDA and SCL pins feature integrated spike
suppression filters and Schmitt triggers to minimize
the effects of input spikes and bus noise. The
TMP103 supports the transmission protocol for both
fast (1kHz to 400kHz) and high-speed (1kHz to
3.4MHz) modes. All data bytes are transmitted MSB
first.
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SERIAL BUS ADDRESS
SLAVE MODE OPERATIONS
To communicate with the TMP103, the master must
first address slave devices via a slave address byte.
The slave address byte consists of seven address
bits, and a direction bit that indicates the intent of
executing a read or write operation.
The TMP103 can operate as a slave receiver or slave
transmitter. As a slave device, the TMP103 never
drives the SCL line.
The TMP103 is available in eight versions, each with
a different slave address, as shown in Table 9. These
addresses can be used as either a location or a
temperature zone designator.
The first byte transmitted by the master is the slave
address, with the R/W bit low. The TMP103 then
acknowledges reception of a valid address. The next
byte transmitted by the master is the Pointer
Register. The TMP103 then acknowledges reception
of the Pointer Register byte. The next byte is written
to the register addressed by the Pointer Register. The
TMP103 acknowledges reception of the data byte.
The master can terminate data transfer by generating
a START or STOP condition.
Table 9. Device Slave Addresses
PRODUCT
TWO-WIRE
ADDRESS
TEMPERATURE
ZONE
TMP103A
1110000
Zone1
TMP103B
1110001
Zone2
TMP103C
1110010
Zone3
TMP103D
1110011
Zone4
TMP103E
1110100
Zone5
TMP103F
1110101
Zone6
TMP103G
1110110
Zone7
TMP103H
1110111
Zone8
WRITING/READING OPERATION
Accessing a particular register on the TMP103 is
accomplished by writing the appropriate value to the
Pointer Register. The value for the Pointer Register is
the first byte transferred after the slave address byte
with the R/W bit low. Every write operation to the
TMP103 requires a value for the Pointer Register
(see Figure 12).
When reading from the TMP103, the last value stored
in the Pointer Register by a write operation is used to
determine which register is read by a read operation.
To change the register pointer for a read operation, a
new value must be written to the Pointer Register.
This action is accomplished by issuing a slave
address byte with the R/W bit low, followed by the
Pointer Register byte. No additional data are
required. The master can then generate a START
condition and send the slave address byte with the
R/W bit high to initiate the read command. See
Figure 13 for details of this sequence. If repeated
reads from the same register are desired, it is not
necessary to continually send the Pointer Register
bytes; the TMP103 remembers the Pointer Register
value until it is changed by the next write operation,
or the TMP103 is reset.
10
Slave Receiver Mode
Slave Transmitter Mode
The first byte transmitted by the master is the slave
address, with the R/W bit high. The slave
acknowledges reception of a valid slave address. The
next byte is transmitted by the slave of the register
indicated by the Pointer Register. The master
acknowledges reception of the data byte. The master
can terminate data transfer by generating a
Not-Acknowledge on reception of the data byte, or
generating a START or STOP condition.
GENERAL CALL
The TMP103 responds to a two-wire General Call
address (0000000) if the eighth bit is '0'. The device
acknowledges the General Call address and
responds to commands in the second byte. If the
second byte is 00000110, the TMP103 internal
registers are reset to power-up values. The TMP103
does not support the General Address acquire
command.
HIGH-SPEED (Hs) MODE
In order for the two-wire bus to operate at frequencies
above 400kHz, the master device must issue an
Hs-mode master code (00001xxx) as the first byte
after a START condition to switch the bus to
high-speed operation. The TMP103 does not
acknowledge this byte, but switches its input filters on
SDA and SCL and its output filters on SDA to operate
in Hs-mode, allowing transfers at up to 3.4MHz. After
the Hs-mode master code has been issued, the
master transmits a START condition followed by a
two-wire slave address to initiate a data transfer
operation. The bus continues to operate in Hs-mode
until a STOP condition occurs on the bus. Upon
receiving the STOP condition, the TMP103 switches
the input and output filters back to the default
fast-mode operation.
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TIMEOUT FUNCTION
The TMP103 resets the serial interface if SCL is held
low for 30ms (typ). The TMP103 releases the bus if it
is pulled low and waits for a START condition. To
avoid activating the timeout function, it is necessary
to maintain a communication speed of at least 1kHz
for SCL operating frequency.
The TMP103A sends data on the first byte and the
TMP103B sends data on the second byte. The
master must issue an acknowledge for each byte
read in order to read all of the TMP103 devices on
the bus; see Figure 15. If the master does not
acknowledge each byte of data, the TMP103s stop
sending subsequent data for any remaining devices.
Up to eight TMP103 devices can be on the same bus
and respond to MDA commands; see Table 9.
MULTIPLE DEVICE ACCESS
The TMP103 supports Multiple Device Access
(MDA), which allows the master to communicate with
multiple TMP103 devices on the same bus interface
with one interface transaction. MDA commands
consist of an MDA read address (00000001) and an
MDA write address (00000000). The device
acknowledges the MDA address and responds to the
command accordingly. In order for MDA to function
correctly, different product versions of the TMP103
must be used in the system; see Table 9.
NOTE: If the bus contains an incomplete sequence of
TMP103 device addresses, the master must transmit
all required dummy bytes for the missing device
address to allow for normal MDA read operation. For
example, if the TMP103A, TMP103B, and TMP103D
devices are on the bus, the master must transmit an
MDA read address followed by four bytes and four
acknowledges in order to complete the MDA read
transaction.
NOISE
Multiple Device Access Write
The master transmits an MDA write address followed
by the pointer address of the register to be accessed;
see Table 2. Following the pointer, all of the TMP103
devices on the bus acknowledge and wait for the next
byte of data to be written to the addressed registers.
When the data byte is received by the TMP103
devices, they store and acknowledge the transmitted
byte. The TMP103s store the same data on all
devices on the bus in one transaction; see Figure 14.
The TMP103 is a very low-power device and
generates very low noise on the supply bus. Applying
an RC filter to the V+ pin of the TMP103 can further
reduce any noise the TMP103 might propagate to
other components. RF in Figure 10 should be less
than 5kΩ and CF should be greater than 10nF.
Supply Voltage
RF £ 5kW
Multiple Device Access Read
Note that before an MDA read transaction can begin,
the master must first send an MDA write transaction
in order to set the appropriate pointer address of the
register to be accessed, as stated in the previous
section. The master can then transmit an MDA read
address followed by a read byte for each TMP103
used on the bus. For example, if a TMP103A and
TMP103B are used on the same bus and an MDA
read address is sent, the address must be followed
by two bytes of data and two master acknowledges.
SCL
SDA
TMP103
GND
V+
CF ³ 10nF
Figure 10. Noise Reduction
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TIMING DIAGRAMS
The TMP103 is two-wire and SMBus compatible.
Figure 11 to Figure 15 describe the various
operations on the TMP103. Parameters for Figure 11
are defined in Table 10. Bus definitions are:
Bus Idle: Both SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the
SDA line, from high to low, while the SCL line is high,
defines a START condition. Each data transfer is
initiated with a START condition.
Stop Data Transfer: A change in the state of the
SDA line from low to high while the SCL line is high
defines a STOP condition. Each data transfer is
terminated with a repeated START or STOP
condition.
t(LOW)
Data Transfer: The number of data bytes transferred
between a START and a STOP condition is not
limited and is determined by the master device.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an Acknowledge
bit. A device that acknowledges must pull down the
SDA line during the Acknowledge clock pulse in such
a way that the SDA line is stable low during the high
period of the Acknowledge clock pulse. Setup and
hold times must be taken into account. On a master
receive, the termination of the data transfer can be
signaled
by
the
master
generating
a
Not-Acknowledge ('1') on the last byte that has been
transmitted by the slave.
tF
tR
t(HDSTA)
SCL
t(HDSTA)
t(HIGH)
t(HDDAT)
t(SUSTO)
t(SUSTA)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
NOTE: P = STOP, S = START.
Figure 11. Two-Wire Timing Diagram
Table 10. Timing Diagram Definitions
FAST MODE
PARAMETER
HIGH-SPEED MODE
MIN
MAX
MIN
MAX
UNIT
f(SCL)
SCL Operating Frequency, VS > 1.7V
0.001
0.4
0.001
3.4
MHz
f(SCL)
SCL Operating Frequency, VS < 1.7V
0.001
0.4
0.001
2.75
MHz
t(BUF)
Bus Free Time Between STOP and START Condition
600
160
ns
t(HDSTA)
Hold time after repeated START condition.
After this period, the first clock is generated.
100
100
ns
t(SUSTA)
Repeated START Condition Setup Time
100
100
ns
t(SUSTO)
STOP Condition Setup Time
100
100
ns
t(HDDAT)
Data Hold Time
0
0
ns
t(SUDAT)
Data Setup Time
100
10
ns
t(LOW)
SCL Clock Low Period, VS > 1.7V
1300
160
ns
t(LOW)
SCL Clock Low Period, VS < 1.7V
1300
200
ns
t(HIGH)
SCL Clock High Period
600
60
ns
tF
Clock/Data Fall Time
300
tR
Clock/Data Rise Time
300
tR
Clock/Data Rise Time for SCLK ≤ 100kHz
1000
12
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ns
160
ns
ns
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1
9
1
9
¼
SCL
1
SDA
1
1
A1(1)
A2(1)
0
A0(1)
0
R/W
Start By
Master
0
0
0
0
0
P1
P0
ACK By
TMP103
¼
ACK By
TMP103
Frame 2 Pointer Register Byte
Frame 1 Two-Wire Slave Address Byte
9
1
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
ACK By
TMP103
Stop By
Master
Frame 3 Data Byte
(1)
The value of A0, A1, and A2 are determined by the TMP103 version; see Table 9.
Figure 12. Two-Wire Timing Diagram for Write Word Format
1
9
1
9
¼
SCL
SDA
1
1
1
0
A2
(1)
A1
(1)
A0
(1)
R/W
Start By
Master
0
0
0
0
0
0
P1
P0
ACK By
TMP103
ACK By
TMP103
Frame 1 Two-Wire Slave Address Byte
1
Frame 2 Pointer Register Byte
9
1
9
¼
SCL
(Continued)
SDA
(Continued)
1
1
1
0
A2
(1)
A1
(1)
A0
(1)
D7
R/W
Start By
Master
D6
D5
D4
ACK By
TMP103
Frame 3 Two-Wire Slave Address Byte
(1)
Stop By
Master
D3
D2
D1
D0
From
TMP103
¼
ACK By Stop By
Master Master
Frame 4 Data Byte Read Register
The value of A0, A1, and A2 are determined by the TMP103 version; see Table 9.
Figure 13. Two-Wire Timing Diagram for Read Word Format
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1
9
1
9
¼
SCL
0
SDA
0
0
0
0
0
0
0
R/W
Start By
Master
0
0
0
0
0
P1
ACK By
TMP103(1)
P0
¼
ACK By
TMP103(1)
Frame 2 Pointer Register Byte
Frame 1 Two-Wire MDA Write Address Byte
9
1
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
ACK By
TMP103(1)
Stop By
Master
Frame 3 Data Byte
(1)
All TMP103 devices on the bus acknowledge the byte.
Figure 14. Two-Wire Timing Diagram MDA Write Word Format
14
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1
9
1
9
¼
SCL
SDA
0
0
0
0
0
0
0
R/W
Start By
Master
0
0
0
0
0
0
P1
P0
ACK By
TMP103(1)
ACK By
TMP103(1)
Frame 1 Two-Wire MDA Write Address Byte
Stop By
Master
Frame 2 Pointer Register Byte
1
9
1
9
¼
SCL
(Continued)
SDA
(Continued)
0
0
0
0
0
0
0
D7
R/W
Start By
Master
D6
D5
D4
D2
D1
Frame 3 Two-Wire MDA Read Address Byte
¼
ACK By
Master
(2)
Frame 4 Data Byte Read Register
1
9
D0
From
TMP103A(3)
ACK By
TMP103(1)
1
D3
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
D7
ACK By
From
TMP103B(3)
Master
Frame 5 Data Byte Read Register
(2)
D6
D5
D4
Stop By
Master
D3
D2
D1
D0
ACK By
From
TMP103C(3)
Master
(2)
Stop By
Master
Frame 6 Data Byte Read Register
(1)
All TMP103 devices on the bus acknowledge the byte.
(2)
The master must issue an acknowledge for each byte read in order to read all of the TMP103 devices on the bus.
(3)
Three TMP103 devices used in this case; up to eight devices can be used (see Table 9).
Figure 15. Two-Wire Timing Diagram MDA Read Word Format Using Typical Application (Front Page)
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2011) to Revision A
•
16
Page
Changed Package-Lead from WCSP-4 to DSBGA-4 in Package/Ordering Information table ............................................. 2
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http://www.ti.com.cn/dsp
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http://www.ti.com.cn/interface
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http://www.ti.com.cn/logic
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http://www.ti.com.cn/power
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http://www.ti.com.cn/microcontrollers
应用
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http://www.ti.com.cn/audio
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http://www.ti.com.cn/automotive
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http://www.ti.com.cn/broadband
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http://www.ti.com.cn/control
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http://www.ti.com.cn/opticalnetwork
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http://www.ti.com.cn/security
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Copyright © 2006, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMP103AYFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TA
TMP103AYFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TA
TMP103BYFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TB
TMP103BYFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TB
TMP103CYFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TC
TMP103CYFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TC
TMP103DYFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TD
TMP103DYFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TD
TMP103EYFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TE
TMP103EYFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TE
TMP103FYFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TF
TMP103FYFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TF
TMP103GYFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TG
TMP103GYFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TG
TMP103HYFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TH
TMP103HYFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
TH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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