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TMP104
SBOS564B – NOVEMBER 2011 – REVISED DECEMBER 2018
TMP104 Low-Power, Digital Temperature Sensor
With SMAART Wire™ Interface
1 Features
3 Description
•
The TMP104 device is a digital output temperature
sensor in a four-ball wafer chip-scale package
(WCSP). The TMP104 is capable of reading
temperatures to a resolution of 1°C.
1
•
•
•
•
•
•
•
Multiple Device Access (MDA):
– Global Read/Write Operations
SMAART Wire™ Interface
Resolution: 8 Bits
Accuracy: ±0.5°C Typical (–10°C to +100°C)
Low Quiescent Current:
– 3-μA Active IQ at 0.25 Hz
– 1-μA Shutdown
Supply Range: 1.4 V to 3.6 V
Digital Output
Package: 0.8-mm (±5%) × 1-mm (±5%) 4-Ball
WCSP (DSBGA)
The TMP104 features a SMAART wire™ interface
that supports daisy-chain configurations. In addition,
the interface supports multiple device access (MDA)
commands that allow the master to communicate with
multiple devices on the bus simultaneously,
eliminating the need to send individual commands to
each TMP104 on the bus.
Up to 16 TMP104s can be tied together in parallel
and easily read by the host. The TMP104 is
especially ideal for space-constrained, powersensitive applications with multiple temperature
measurement zones that must be monitored.
2 Applications
•
•
The TMP104 is specified for operation over a
temperature range of –40°C to +125°C.
Handsets
Notebooks
Device Information(1)
PART NUMBER
TMP104
PACKAGE
DSBGA (4)
BODY SIZE (NOM)
1.20 mm × 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
VCC
VCC
VCC
VCC
Host
RX_1
RX_2
RX_N
RX_(N - 1)
TX
TX_1
Device(1)
TX_2
Device(2)
Device(N -1)
TX_(N - 1)
TX_(N)
Device(N)
RX
Daisy-Chain
Configuration
Up to 16 TMP104 Devices in Daisy-Chain
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMP104
SBOS564B – NOVEMBER 2011 – REVISED DECEMBER 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
3
3
3
4
5
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 6
7.1
7.2
7.3
7.4
8
Device and Documentation Support.................. 16
8.1
8.2
8.3
8.4
8.5
9
Overview ................................................................... 6
Feature Description................................................... 6
Programming............................................................. 7
Register Maps ......................................................... 10
Receiving Notification of Documentation Updates.. 16
Community Resources............................................ 16
Trademarks ............................................................. 16
Electrostatic Discharge Caution .............................. 16
Glossary .................................................................. 16
Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2011) to Revision B
Page
•
Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .............................. 1
•
Changed supply voltage maximum value from: 3.6 V to: 4 V ............................................................................................... 3
•
Changed input voltage maximum value from: (V+) + 0.3 to:(V+) + 0.5 and ≤ 4 V ................................................................. 3
•
Moved the content in Package/Ordering Information table to the Mechanical, Packaging, and Orderable Information
section .................................................................................................................................................................................. 16
Changes from Original (November 2011) to Revision A
Page
•
Changed one-wire UART-style interface to SMAART wire interface throughout document .................................................. 1
•
Changed description of protocol in Communication Protocol section .................................................................................... 7
•
Updated Figure 7.................................................................................................................................................................... 7
2
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5 Pin Configuration and Functions
YFF PACKAGE
WCSP-4 (DSBGA-4)
(TOP VIEW)
B2
B1
TX
RX
A2
GND
A1
V+
Pin Functions
PIN
NO.
DESCRIPTION
NAME
A1
V+
A2
GND
Supply voltage
Ground
B1
TX
Serial data output pin (push-pull output)
B2
RX
Serial data input pin
6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
4
V
(V+) + 0.5
and ≤ 4
V
Supply voltage
Input voltage
–0.3
Operating temperature
–55
Junction temperature
Storage temperature, Tstg
(1)
–60
150
°C
+150
°C
150
°C
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±100
Machine model (MM)
200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Thermal Information
TMP104
THERMAL METRIC (1)
YFF (DSBGA)
UNIT
4 PINS
RθJA
Junction-to-ambient thermal resistance
188.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
2.1
°C/W
RθJB
Junction-to-board thermal resistance
35.1
°C/W
ψJT
Junction-to-top characterization parameter
10.6
°C/W
ψJB
Junction-to-board characterization parameter
35.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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Thermal Information (continued)
TMP104
THERMAL METRIC (1)
YFF (DSBGA)
UNIT
4 PINS
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
6.4 Electrical Characteristics
At TA = +25°C and V+ = +1.4 V to +3.6 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEMPERATURE INPUT
Range
Accuracy (temperature error)
+125
°C
–10°C to +100°C, V+ = 1.8 V
–40
±0.5
±2
°C
–40°C to +125°C, V+ = 1.8 V
±1
±3
±0.2
±0.5
vs supply
Resolution
1.0
°C
°C/V
°C
DIGITAL INPUT/OUTPUT
VIH
VIL
IIN
Input logic levels
Input current
VOL
Output logic levels
VOH
0.7 × (V+)
V+
–0.5
0.3 × (V+)
V
1
μA
0 < VIN < (V+) + 0.3 V
V+ > 2 V, IOL = 1 mA
0
0.4
V
V+ < 2 V, IOL = 1 mA
0
0.2 × (V+)
V
V+ > 2 V, IOH = 1 mA
(V+) – 0.4
V+
V
V+ < 2 V, IOH = 1 mA
0.8 × (V+)
V+
Resolution
8
Conversion time
26
CR1 = 0, CR0 = 0 (default)
Conversion modes
V
V
Bit
35
ms
0.25
Conv/s
CR1 = 0, CR0 = 1
1
Conv/s
CR1 = 1, CR0 = 0
4
Conv/s
CR1 = 1, CR0 = 1
8
Conv/s
Timeout time
Interface
28
SMAART wire interface
Serial baud rate
ms
4.8
114
kbps
+1.4
+3.6
V
3
μA
POWER SUPPLY
Operating supply range
IQ
Quiescent current
ISD
Shutdown current
Serial bus inactive, CR1 = 0,
CR0 = 0 (default), V+ = 1.8 V
1.5
Serial bus active, CR1 = 0, CR0 = 0, V+ = 1.8 V
20
Serial bus inactive, V+ = 1.8 V
0.5
μA
1
μA
TEMPERATURE
4
Specified range
–40
+125
°C
Operating range
–55
+150
°C
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6.5 Typical Characteristics
At TA = +25°C and V+ = 1.8 V, unless otherwise noted.
9
12
V+ = 1.4 V
V+ = 1.8 V
V+ = 3.6 V
10
7
6
ISD (mA)
8
IQ (mA)
V+ = 1.8 V
V+ = 3.6 V
8
6
5
4
3
4
2
2
1
0
0
-60 -40 -20
0
20
40
60
80
-60 -40 -20
100 120 140 160
20
40
60
80
100 120 140 160
Temperature (°C)
Figure 1. Quiescent Current vs Temperature
(0.25 Conversions per Second)
Figure 2. Shutdown Current vs Temperature
27.5
2
26.5
26
25.5
25
24.5
24
1.5
Temperature Error (°C)
V+ = 1.4 V
V+ = 1.8 V
V+ = 3.6 V
27
Conversion Time (ms)
0
Temperature (°C)
1
0.5
0
-0.5
-1
-1.5
-2
23.5
-60 -40 -20
0
20
40
60
80
100 120 140 160
-60 -40 -20
Temperature (°C)
0
20
40
60
80
100 120 140 160
Temperature (°C)
Figure 3. Conversion Time vs Temperature
Figure 4. Temperature Error vs Temperature
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7 Detailed Description
7.1 Overview
The TMP104 is a digital output temperature sensor in a wafer chip-scale package (WCSP) that is optimal for
thermal management and thermal profiling. The TMP104 includes a SMAART wire interface that is capable of
communicating in a daisy-chain with up to 16 devices on a single bus. The interface requires two pins from the
host; the first device in the daisy-chain receives data from the host and the last device in the daisy-chain returns
data to the host. In addition, the TMP104 has the capability of executing multiple device access (MDA)
commands that allow multiple TMP104s to respond to a single global bus command. MDA commands reduce
communication time and power in a bus that contains multiple TMP104 devices. The TMP104 is specified over a
temperature range of –40ºC to +125ºC.
The TMP104 also has the capability of configuring the bus in a transparent mode, where the input from the host
is sent directly to the next device in the chain without delay. Additionally, the TMP104 can disconnect the chain
and create a serial communication controlled by each TMP104 on the bus, thereby allowing each device to have
configurable addressing and interrupt capabilities. The input pin, RX, is a high-impedance node. The output pin,
TX, has an internal push-pull output stage that can drive the host to GND or V+.
After an initialization sequence, each device on the bus is programmed with its own interface address that allows
it to respond to its own address and also respond to general commands that permit the user to read or write to all
of the devices on the bus without having to send its individual address and command to each individual device.
The temperature sensor in the TMP104 is the chip itself. Thermal paths run through the package bumps as well
as the package. The lower thermal resistance of metal causes the bumps to provide the primary thermal path. To
maintain accuracy in applications that require air or surface temperature measurement, take care to isolate the
package from ambient air temperature. A thermally-conductive adhesive can help to achieve accurate surface
temperature measurement.
7.2 Feature Description
7.2.1 Timeout Function
A timeout mechanism is implemented on the TMP104 to allow for re-synchronization of the SMAART wire
interface if synchronization between the host and the TMP104 is lost for 28 ms (typical). If the timeout period
expires between the calibration byte and the command byte, or between the command byte and any data byte,
or between any data bytes, the TMP104 resets the SMAART wire interface circuitry so that it expects the baud
rate calibration command to restart. Every time a byte is transmitted on the SMAART wire interface, this timeout
period restarts.
7.2.2 Noise
The TMP104 is a very low-power device and generates very low noise on the supply bus. Applying a bypass
capacitor to the V+ pin of the TMP104 can further reduce any noise the TMP104 might propagate to other
components. CF in Figure 5 should be greater than 0.1 μF.
Supply Voltage
TX
RX
GND
V+
CF ³ 0.1 mF
Figure 5. Noise Reduction
6
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Feature Description (continued)
7.2.3 SMAART Wire™ Interface Timing Specifications
Figure 6 shows the key timing and jitter considerations for the SMAART wire interface. Table 1 lists the timing
specifications for ensured, reliable operation. During a transaction, the baud rate must remain within ±1% of its
initialization byte value; however, the baud rate can change from transaction to transaction. There is an allowed
delay between each byte transfer of less than 28 ms, which is the bus inactivity timeout check for the TMP104
SMAART wire interface.
BaudTYP
Jitter tR
tF
Jitter +
Figure 6. SMAART Wire™ Timing Diagram
Table 1. Timing Diagram Definitions
PARAMETER
Baud
MIN
MAX
4.8 k
UNIT
114 k
Bits/s
tR
Clock/data rise time
0.5
%Baud
tF
Clock/data fall time
0.5
%Baud
±1
%Baud
Jitter
7.3 Programming
7.3.1 Communication Protocol
Each communication of the SMAART wire protocol consists of 8-bit words, transferred least significant bit (LSB)
first. Each 8-bit word begins with a Start bit that is logic low, and ends with a Stop bit that is logic high. By using
a Start bit and Stop bit for each 8-bit word, the TMP104 can calibrate each word and maintain synchronous
communication throughout the process. The host commences the communication by sending a Start bit followed
by the calibration byte (55h), allowing the TMP104 to sync to the baud rate of the host, followed by the Stop bit.
Then, another Start bit is sent, followed by the command register byte and a Stop bit. Finally, a third Start bit is
sent followed by the data byte, where master sends data if the instruction is a write command, or the TMP104
breaks the chain and sends data if the instruction is a read command. The process finishes with a Stop bit. The
sequence is shown in Table 2 and Figure 7.
Table 2. Communication Format
Start bit
Calibration
Stop bit
Start bit
Command
byte
Stop bit
Start bit
Data
byte
Stop bit
Driven by TMP104
S
1
0
1
0
1
0
1
0
P
S P0 P1 P2 P3 P4 P5 P6 P7 P
S D0 D1 D2 D3 D4 D5 D6 D7 P
Command with Address Pointer
Register Data (8 LSBs)
Calibration Byte (55h)
S = Start Condition of SMAART Wire Protocol
P = Stop Condition of SMAART Wire Protocol
1-bit default delay
for bus direction change.
Figure 7. Generic Communication BitStream
The TMP104 has two dedicated pins for communication: TX and RX. Usually, these two pins are connected
internally and the signal on the RX propagates to the TX; that is, the TMP104 works in a transparent mode. The
TMP104 breaks this buffer configuration only when it must send data on the bus or during address assignment
and alert procedures.
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The TMP104 supports unique address assignment and alert interrupt procedures. There are general-call read
and write commands that allow simultaneous reads or writes to all devices in the daisy-chain. The interface has
built-in time-outs (typically 28 ms) that return the interface to a known state if communication is disrupted.
7.3.2 Command Register
Figure 8 shows the internal register structure of the TMP104. Communications between the registers are
transferred through the interface in LSB-first order. The 8-bit Command Register, as shown in Table 3, is used to
determine the type of instruction being addressed. These eight bits could either interpret a global instruction or
an individual instruction, which is determined by the value of P7. When P7 = 0, the command byte interprets an
individual instruction; when P7 = 1, the command byte interprets a global instruction.
Command
Register
Temperature
Register
RX
Configuration
Register
I/O
Control
Interface
TLOW
Register
TX
THIGH
Register
Figure 8. Internal Register Structure
Table 3. Command Register Byte
P7
P6
P5
P4
P3
P2
P1
P0
GLB
IN3/ID3
IN2/ID2
IN1/ID1
IN0/ID0
P1
P0
R/W
7.3.3 Global Initialization and Address Assignment Sequence
At device power-up, every TMP104 in the daisy-chain is connected in transparent mode, as shown in Figure 9.
The host must send the initialization command (P7-P0 = 10001100) in order for the bus to program its internal
address depending on the number of devices on the bus.
RX
TX
RX
TX
RX
TX
RX
TX
Host
Interface Logic
Interface Logic
Interface Logic
Device(1)
Device(2)
Device(N)
Figure 9. TMP104 Daisy-Chain: Bus Status at Start of Global Initialization
8
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Each TMP104 in the chain interprets the initialization command byte and disconnects the chain, as shown in
Figure 10. The host must then send the address assignment command, consisting of P7-P4 = 1001 and P3-P0 =
0000, where P3-P0 represents the address of the first device in the chain; this word is stored internally as its
device ID. The first device increments the unit in the device address and then reconnects the bus, as shown in
Figure 11. This address is then sent to the next device in the chain. Once all devices on the chain have received
the respective addresses, the host receives the last programmed address on the chain + 1. The host can use
this information to determine the total number of devices in the chain and the respective address of each device.
After the initialization sequence, every device can be addressed individually or through global commands. This
global initialization sequence is a requirement and must be performed before any other communication.
RX
RX
TX
TX
RX
TX
RX
TX
Host
Interface Logic
Interface Logic
Interface Logic
Device(1)
Device(2)
Device(N)
Figure 10. TMP104 Daisy-Chain: Bus Status at Start of Address Assignment
RX
RX
TX
TX
RX
TX
RX
TX
Host
Interface Logic
Interface Logic
Interface Logic
Device(1)
Device(2)
Device(N)
Figure 11. TMP104 Daisy-Chain: Bus Status After First Device Address Assignment
7.3.4 Global Read and Write
The host can initiate a global read or write command to all TMP104s in the daisy-chain by sending the read/write
command, consisting of P7-P3 = 11110. P2-P1 indicate the data register pointer, as shown in Table 4, and P0
indicates read/write control. P0 = 0 indicates a global write command. The host must transfer one more byte of
data for the register (indicated by bits P2-P1), and every TMP104 in the daisy-chain updates the appropriate
register. P0 = 1 indicates a global read command. The TMP104 with the device ID of '0000' then breaks the bus
connection, transmits the data from the register indicated by bits P2-P1, and then reconnects the bus. The
TMP104 with the device ID of '0001' then repeats the same sequence, followed by the rest of the TMP104
devices in the daisy-chain.
Table 4. Pointer Addresses
P0
P0
REGISTER
0
0
Temperature register (read-only)
0
1
Configuration register (read/write)
1
0
TLOW register (read/write)
1
1
THIGH register (read/write)
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7.3.5 Global Clear Interrupt
The host can initiate a global clear interrupt command (P7-P0 = 10101001) to all TMP104s in the daisy-chain.
Upon receiving this command, the TMP104 disables future interrupts (D7 in the Configuration Register is set to
'0'). If a TMP104 has previously broken the bus connection and sent an interrupt (logic low on the bus), it now
stops holding the bus low. The device sends the baud rate calibration command and clear interrupt command to
the next TMP104 in the chain, and then reconnects the bus. In the case of multiple devices having active
interrupts, the clear interrupt command propagates through the daisy-chain, disables all interrupts, and
reconnects the bus across all devices.
7.3.6 Global Software Reset
The host can initiate a global software reset command (P7-P0 = 10110100) to all TMP104s in the daisy-chain.
Upon receiving this command, the TMP104 resets its internal registers except for the device ID, which is not
reset, and reconnects the bus. If the bus is broken before the initiation of this command, all TMP104s before the
broken bus point receive the command. If the host intends to initiate a global software reset across all TMP104s
in the chain, this command must be transmitted multiple times until it echoes back to the host.
7.3.7 Individual Read and Write
The host can initiate an individual read/write command to a particular TMP104 in the daisy-chain by sending the
read/write command. The read/write command consists of these parameters:
• P7 = 0
• P6-P3 = the device ID
• P2-P1 = the data register pointer; see Table 4
• P0 = indicates read/write control
P0 = 0 indicates an individual write command; the host must transfer one more byte of data for the register
indicated by bits P2-P1. The TMP104 in the daisy-chain that corresponds to the device ID noted by bits P6-P3
then updates the appropriate register. P0 = 1 indicates an individual read command; as shown in Figure 12, the
TMP104 in the daisy-chain that corresponds to the device ID pointed by bits P6-P3 then breaks the bus,
transmits the data from the register pointed by bits P2-P1, and reconnects the bus.
RX
TX
RX
TX
RX
TX
RX
TX
Host
Interface Logic
Interface Logic
Interface Logic
Device(1)
Device(2)
Device(N)
Figure 12. TMP104 Daisy-Chain: Bus Status During Individual Read Operation of Second Device
7.4 Register Maps
7.4.1 Temperature Register
The Temperature Register of the TMP104 is configured as an 8-bit, read-only register that stores the output of
the most recent conversion. A single byte must be read to obtain data, and is described in Table 5. The data
format for temperature is summarized in Table 6. One LSB equals 1°C.
10
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Table 5. Temperature Register
D7
D6
D5
D4
D3
D2
D1
D0
T7
T6
T5
T4
T3
T2
T1
T0
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Negative numbers are represented in binary twos complement format. Following power-up or reset, the
Temperature Register reads 0°C until the first conversion is complete.
Table 6. 8-Bit Temperature Data Format (1)
DIGITAL OUTPUT
(1)
TEMPERATURE (°C)
BINARY
HEX
128
0111 1111
7F
127
0111 1111
7F
100
0110 0100
64
80
0101 0000
50
75
0100 1011
4B
50
0011 0010
32
25
0001 1001
19
0
0000 0000
00
–1
1111 1111
FF
–25
1110 0111
E7
–55
1100 1001
C9
The resolution for the analog-to-digital converter (ADC) is 1°C/count, where count is equal to the digital
output of the ADC.
For positive temperatures (for example, +50°C):
Twos complement is not performed on positive numbers. Therefore, simply convert the number to binary
code, left-justified format. Denote a positive number with most significant bit (MSB) = 0.
Example: (+50°C)/(1°C/count) = 50 = 32h = 0011 0010
For negative temperatures (for example, –25°C):
Generate the twos complement of a negative number by complementing the absolute value binary number
and adding 1. Denote a negative number with MSB = 1.
Example: (|–25°C|)/(1°C/count) = 25 = 19h = 0001 1001
Twos complement format: 1110 0110 + 1 = 1110 0111
7.4.2 Configuration Register
The Configuration Register is an 8-bit read/write register used to store bits that control the operational modes of
the temperature sensor. Read/write operations are performed LSB first. The format and power-up/reset value of
the Configuration Register is shown in Table 7.
Table 7. Configuration and Power-Up/Reset Format
D7
D6
D5
D4
D3
D2
D1
D0
INT_EN
CR1
CR0
FH
FL
LC
M1
M0
0
0
0
0
0
0
1
0
7.4.2.1 Temperature Watchdog Function (FH, FL)
The TMP104 contains a watchdog function that monitors device temperature and compares the result to the
values stored in the temperature limit registers (THIGH and TLOW) in order to determine if the device temperature
is within these set limits. If the temperature of the TMP104 becomes greater than the value in the THIGH register,
then the flag-high bit (FH) in the Configuration Register is set to '1'. If the temperature falls below value in the
TLOW register, then the flag-low bit (FL) is set to '1'. If both flag bits remain '0', then the temperature is within the
temperature window set by the temperature limit registers, as shown in Figure 13.
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THIGH
Measured
Temperature
TLOW
FH Bit
(Transparent Mode)
FL Bit
(Transparent Mode)
FH Bit
(Latch Mode)
FL Bit
(Latch Mode)
Read of Configuration Register
Time
Figure 13. Temperature Flag Functional Diagram
The latch bit (LC) in the Configuration Register is used to latch the value of the flag bits (FH and FL) until the
master issues a read command to the Configuration Register. The flag bits are set to '0' if a read command is
received by the TMP104, or if LC = 0 and the temperature is within the temperature limits. The power-on default
values for these bits are FH = 0, FL = 0, and LC = 0.
7.4.2.2 Conversion Rate (CR1, CR0)
The conversion rate bits (CR1 and CR0), located in the Configuration Register, configure the TMP104 for
conversion rates of 8 Hz, 4 Hz, 1 Hz, or 0.25 Hz (default). The TMP104 has a typical conversion time of 26 ms.
To achieve different conversion rates, the TMP104 performs a single conversion and then powers down and
waits for the appropriate delay set by CR1 and CR0. Table 8 shows the settings for CR1 and CR0.
Table 8. Conversion Rate Settings
CR1
CR0
CONVERSION RATE
0
0
0.25 Hz (default)
0
1
1 Hz
1
0
4 Hz
1
1
8 Hz
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After power-up or general-call reset, the TMP104 immediately starts a conversion, as shown in Figure 14. The
first result is available after 26 ms (typical). The active quiescent current during conversion is 40 μA (typical at
+25°C, V+ = 1.8 V). The quiescent current during delay is 1.0 μA (typical at +25°C, V+ = 1.8 V).
Delay
(1)
26 ms
26 ms
Startup
Start of
Conversion
(1) Delay is set by CR1 and CR0.
Figure 14. Conversion Start
7.4.2.3 Conversion Modes
7.4.2.3.1 Shutdown Mode (M1 = 0, M0 = 0)
Shutdown mode saves maximum power by shutting down all device circuitry other than the serial interface,
reducing current consumption to typically less than 0.5 μA. Shutdown mode is enabled when bits M1 and M0 (in
the Configuration Register) read '00'. The device shuts down when the current conversion is completed.
7.4.2.3.2 One-Shot Mode (M1 = 0, M0 = 1)
The TMP104 features a One-Shot Temperature Measurement mode. When the device is in Shutdown mode,
writing '01' to bits M1 and M0 starts a single temperature conversion. During the conversion, bits M1 and M0
read '01'. The device returns to the shutdown state at the completion of the single conversion. After the
conversion, bits M1 and M0 read '00'. This feature is useful for reducing power consumption in the TMP104
when continuous temperature monitoring is not required.
As a result of the short conversion time, the TMP104 can achieve a higher conversion rate. A single conversion
typically takes 26 ms and an individual read can take place in less than 300 μs. When using One-Shot mode, 30
or more conversions per second are possible.
7.4.2.3.3 Continuous Conversion Mode (M1 = 1)
When the TMP104 is in Continuous Conversion mode (M1 = 1), continuous conversions are performed at a rate
determined by the conversion rate bits, CR1 and CR0 (in the Configuration Register). The TMP104 performs a
single conversion, and then powers down and waits for the appropriate delay set by CR1 and CR0. See Table 8
for CR1 and CR0 settings.
7.4.2.4 Interrupt Functionality (INT_EN)
The TMP104 interrupts the host by disconnecting the bus and issuing an interrupt request by holding the bus low
if all of these conditions are met, as shown in Figure 15:
• INT_EN in the Configuration Register is set to '1';
• The temperature result is higher than the value in the THIGH register or lower than the value in the TLOW
register (as indicated by a '1' in either FL or FH);
• The bus is logic high and idle for more than 28 ms.
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RX
RX
TX
TX
RX
TX
RX
TX
Host
Interface Logic
Interface Logic
Interface Logic
Device(1)
Device(2)
Device(N)
Figure 15. TMP104 Daisy-Chain:
Bus Status During an Interrupt Request (Logic Low) From Second Device
The interrupt on the bus is latched regardless of the status of LC. Writing a '1' to INT_EN automatically sets the
LC bit. The TMP104 holds the bus low until one of the following events happen:
• Global Interrupt Clear command received;
• Global Software Reset command received;
• A power-on reset event occurs.
Each of these events clears INT_EN; the TMP104 does not issue future interrupts until the host writes '1' to bit
D7 in the Configuration Register to re-enable future interrupts.
In a system with enabled interrupts, it is possible for a TMP104 on the bus to issue an interrupt at the same time
that the host starts a communication sequence. To avoid this scenario, it is recommended that the host should
check the status on the receiving side of the bus after transmitting the calibration byte. If it is '1', then the host
can continue with the communication. If it is '0', one of the TMP104 devices on the bus is issuing an alert and the
host must transmit a Global Interrupt Clear command.
7.4.3 Temperature Limit Registers
The THIGH and TLOW registers are used to store the temperature limit thresholds for the TMP104 watchdog
function. At the end of each temperature measurement, the TMP104 compares the temperature results to each
of these limits. If the temperature result is greater than the THIGH limit, then the FH bit in the Configuration
Register is set to '1'. If the temperature result is less than the TLOW limit, then the FL bit in the Configuration
Register is set to '1'; see Figure 13.
Table 9 and Table 10 describe the format for the THIGH and TLOW registers. Power-up reset values for THIGH and
TLOW are: THIGH = +60°C and TLOW = –10°C. The format of the data for THIGH and TLOW is the same as for the
Temperature Register.
Table 9. THIGH Register
D7
D6
D5
D4
D3
D2
D1
D0
H7
H6
H5
H4
H3
H2
H1
H0
Table 10. TLOW Register
D7
D6
D5
D4
D3
D2
D1
D0
L7
L6
L5
L4
L3
L2
L1
L0
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8 Device and Documentation Support
8.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
8.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.3 Trademarks
SMAART Wire, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMP104YFFR
ACTIVE
DSBGA
YFF
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
T4
TMP104YFFT
ACTIVE
DSBGA
YFF
4
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
T4
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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