TMP105YZCTG4

TMP105 Chip-Scale Package SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 Digital Temperature Sensor with Two-Wire Interface FEATURES D D D D D D D SUPPORTS 1.8V I2C BUS TWO ADDRESSES DIGITAL OUTPUT: Two-Wire Serial Interface RESOLUTION: 9- to 12-Bits, User-Selectable ACCURACY: ±2.0°C (max) from −25°C to +85°C ±3.0°C (max) from −40°C to +125°C LOW QUIESCENT CURRENT: 50µA, 1.5µA Standby NO POWER-UP SEQUENCE REQUIRED, I2C PULLUPS CAN BE ENABLED PRIOR TO V+ DESCRIPTION The TMP105 is a two-wire, serial output temperature sensor available in a WCSP package. Requiring no external components, the TMP105 is capable of reading temperatures with a resolution of 0.0625°C. The TMP105 features a Two-Wire interface that is SMBus-compatible, with the TMP105 allowing up to two devices on one bus. The TMP105 features an SMBus Alert function. The TMP105 is ideal for extended temperature measurement in a variety of communication, computer, consumer, environmental, industrial, and instrumentation applications. The TMP105 is specified for operation over a temperature range of −40°C to +125°C. APPLICATIONS D CELL PHONES D COMPUTER PERIPHERAL THERMAL D D D D PROTECTION NOTEBOOK COMPUTERS BATTERY MANAGEMENT THERMOSTAT CONTROLS ENVIRONMENTAL MONITORING AND HVAC YZC LEAD FREE 2 X 3 ARRAY (TOP VIEW) Temperature A1 Diode Temp. Sensor Control Logic A2 SDA GND SDA 1,65 mm 1,50 mm A1 B1 C1 A2 B2 C2 GND ALERT A0 V+ C1 OSC Config. and Temp. Register C2 A0 SCL B1 ∆Σ A/D Converter Serial Interface B2 ALERT SCL V+ 1,15 mm 1,00 mm (Bump Side Down) Note: Pin A1 is marked with a ’0” for Pb−free (YZC) TMP105 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2005−2006, Texas Instruments Incorporated www.ti.com TMP105 www.ti.com SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 ABSOLUTE MAXIMUM RATINGS(1) Power Supply, V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V Input Voltage(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to 7.0V Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Operating Temperature Range . . . . . . . . . . . . . . . −55°C to +127°C Storage Temperature Range . . . . . . . . . . . . . . . . . −60°C to +130°C Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . . . . . +150°C ESD Rating: Human Body Model (HBM)(3) . . . . . . . . . . . . . . . . . . . . . 2000V Charged-Device Model (CDM)(4) . . . . . . . . . . . . . . . . . . . . 500V Machine Model (MM)(5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Input voltage rating applies to all TMP105 input voltages. (3) HBM testing has been tested to TI specifications JEDEC JESD22-A114C.01. (4) CDM testing has been tested to TI specifications JEDEC EIA/JESD22-A115A. (5) MM testing has been tested to TI specifications JEDEC JESD22-C101C. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION(1) PACKAGE Wafer chip-scale package (YZC) PART NUMBER TMP105YZC SYMBOL EY (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. PIN ASSIGNMENTS WCSP-6 PACKAGE (TOP VIEW) SDA SCL V+ A1 B1 A2 B2 C2 GND ALERT A0 C1 (Bump Side Down) NOTE: Pin 1 is determined by orienting the package marking as indicated in the diagram. 2 TMP105 www.ti.com SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 ELECTRICAL CHARACTERISTICS At TA = −40°C to +125°C, and V+ = 2.6V to 3.3V, unless otherwise noted. TMP105 PARAMETER TEMPERATURE INPUT Range Accuracy (Temperature Error) vs Supply Resolution(1) DIGITAL INPUT/OUTPUT Input Capacitance Input Logic Levels: VIH VIL Leakage Input Current, IIN Input Voltage Hysteresis Output Logic Levels: VOL SDA VOL ALERT Resolution Conversion Time IOL = 3mA IOL = 4mA Selectable 9-Bit 10-Bit 11-Bit 12-Bit Timeout Time POWER SUPPLY Operating Range Quiescent Current Shutdown Current TEMPERATURE RANGE Specified Range Operating Range Thermal Resistance (1) Specified for 12-bit resolution. qJA −40 −55 240 +125 +127 °C °C °C/W IQ ISD Serial Bus Inactive Serial Bus Active, SCL Freq = 400kHz Serial Bus Inactive Serial Bus Active, SCL Freq = 400kHz 2.6 50 100 1.5 60 3 3.3 85 V µA µA µA µA 25 0 0 0.15 0.15 9 to 12 27.5 55 110 220 54 37.5 75 150 300 74 0.4 0.4 V V Bits ms ms ms ms ms 0V ≤ VIN ≤ 6V SCL and SDA Pins 100 1.2 −0.5 6.0 0.6 1 V V µA mV 3 pF −25°C to +85°C −40°C to +125°C Selectable −40 ±0.5 ±1.0 0.2 0.0625 +125 ±2.0 ±3.0 ±0.5 °C °C °C °C/V °C CONDITION MIN TYP MAX UNITS 3 TMP105 www.ti.com SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 TYPICAL CHARACTERISTICS At TA = +25°C and V+ = 2.8V, unless otherwise noted. QUIESCENT CURRENT vs TEMPERATURE 100 V+ = 2.6V Shutdown Current (µ A) 80 2.5 2.0 3.0 SHUTDOWN CURRENT vs TEMPERATURE IQ (µA) 60 V+ = 3.3V 1.5 1.0 0.5 V+ = 2.6V 0 40 20 0 − 50 − 25 0 25 50 75 100 125 Temperature (_ C) − 50 − 25 0 25 50 75 100 125 Temperature (_ C) CONVERSION TIME vs TEMPERATURE 225 2.0 1.5 Temperature Error (_ C) 220 Conversion Time (ms) V+ = 2.6V 215 1.0 0.5 0.0 − 0.5 − 1.0 − 1.5 12−Bit Resolution 200 − 50 − 25 0 25 50 75 100 125 Temperature (_ C) − 2.0 − 55 TEMPERATURE ACCURACY vs TEMPERATURE 210 V+ = 3.3V 205 3 typical units 12−bit resolution. − 35 − 15 5 25 45 65 85 105 125 130 Temperature (_ C) QUIESCENT CURRENT WITH BUS ACTIVITY vs TEMPERATURE 500 450 400 350 IQ (µA) 300 250 200 150 100 50 0 1k 10k 100k Frequency (Hz) +25_ C − 55_ C 1M 10M +125_ C 4 TMP105 www.ti.com SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 APPLICATIONS INFORMATION The TMP105 is a digital temperature sensor that is optimal for thermal management and thermal protection applications. The TMP105 is Two-Wire and SMBus interface-compatible, and is specified over a temperature range of −40°C to +125°C. The TMP105 requires no external components for operation except for pull-up resistors on SCL, SDA, and ALERT, although a 0.1µF bypass capacitor is recommended, as shown in Figure 1. Pointer Register Temperature Register Configuration Register SCL I/O Control Interface SDA TLOW Register V+ THIGH Register C1 To Two−Wire Controller SCL SDA B1 TMP105 A1 A2 C2 B2 0.1µ F A0 ALERT (Output) Figure 2. Internal Register Structure of the TMP105 P1 P0 0 1 0 1 REGISTER Temperature Register (Read Only) Configuration Register (Read/Write) TLOW Register (Read/Write) THIGH Register (Read/Write) GND NOTE: SCL, SDA, and ALERT pins require pull−up resistors. 0 0 1 1 Figure 1. Typical Connections of the TMP105 The sensing device of the TMP105 is the chip itself. Thermal paths run through the package leads. The lower thermal resistance of metal causes the leads to provide the primary thermal path. To maintain accuracy in applications requiring air or surface temperature measurement, care should be taken to isolate the package and leads from ambient air temperature. Table 2. Pointer Addresses of the TMP105 TEMPERATURE REGISTER The Temperature Register of the TMP105 is a 12-bit, read-only register that stores the output of the most recent conversion. Two bytes must be read to obtain data, and are described in Table 3 and Table 4. Note that byte 1 is the most significant byte; byte 2 is the least significant byte (sent in this order). The first 12 bits are used to indicate temperature, with all remaining bits equal to zero. The least significant byte does not have to be read if that information is not needed. Data format for temperature is summarized in Table 5. Following power-up or reset, the Temperature Register will read 0°C until the first conversion is complete. POINTER REGISTER Figure 2 shows the internal register structure of the TMP105. The 8-bit Pointer Register of the devices is used to address a given data register. The Pointer Register uses the two LSBs to identify which of the data registers should respond to a read or write command. Table 1 identifies the bits of the Pointer Register byte. Table 2 describes the pointer address of the registers available in the TMP105. Power-up reset value of P1/P0 is 00. D7 T11 D6 T10 D5 T9 D4 T8 D3 T7 D2 T6 D1 T5 D0 T4 Table 3. Byte 1 of Temperature Register D7 T3 D6 T2 D5 T1 D4 T0 D3 0 D2 0 D1 0 D0 0 P7 0 P6 0 P5 0 P4 0 P3 0 P2 0 P1 P0 Register Bits Table 1. Pointer Register Byte Table 4. Byte 2 of Temperature Register 5 TMP105 www.ti.com SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 TEMPERATURE (°C) 128 127.9375 100 80 75 50 25 0.25 0 −0.25 −25 −55 DIGITAL OUTPUT (BINARY) 0111 1111 1111 0111 1111 1111 0110 0100 0000 0101 0000 0000 0100 1011 0000 0011 0010 0000 0001 1001 0000 0000 0000 0100 0000 0000 0000 1111 1111 1100 1110 0111 0000 1100 1001 0000 POLARITY (POL) HEX 7FF 7FF 640 500 4B0 320 190 004 000 FFC E70 C90 TMP105 ALERT PIN (Comparator Mode) POL = 0 TMP105 ALERT PIN (Interrupt Mode) POL = 0 TMP105 ALERT PIN (Comparator Mode) POL = 1 TMP105 ALERT PIN (Interrupt Mode) POL = 1 Measured Temperature THIGH The Polarity Bit of the TMP105 allows the user to adjust the polarity of the ALERT pin output. If POL = 0, the ALERT pin will be active LOW, as shown in Figure 3. For POL = 1, the ALERT pin will be active HIGH, and the state of the ALERT pin is inverted. TLOW Table 5. Temperature Data Format The user can obtain 9, 10, 11, or 12 bits of resolution by addressing the Configuration Register and setting the resolution bits accordingly. For 9-, 10-, or 11-bit resolution, the most significant bits in the Temperature Register are used with the unused LSBs set to zero. CONFIGURATION REGISTER The Configuration Register is an 8-bit read/write register used to store bits that control the operational modes of the temperature sensor. Read/write operations are performed MSB first. The format of the Configuration register for the TMP105 is shown in Table 6, followed by a breakdown of the register bits. The power-up/reset value of the Configuration Register is all bits equal to 0. BYTE 1 D7 OS D6 R1 D5 R0 D4 F1 D3 F0 D2 POL D1 TM D0 SD Read Read Time Read Figure 3. Output Transfer Function Diagrams FAULT QUEUE (F1/F0) A fault condition is defined as when the measured temperature exceeds the user-defined limits set in the THIGH and TLOW Registers. Additionally, the number of fault conditions required to generate an alert may be programmed using the fault queue. The fault queue is provided to prevent a false alert as a result of environmental noise. The fault queue requires consecutive fault measurements in order to trigger the alert function. Table 7 defines the number of measured faults that may be programmed to trigger an alert condition in the device. For THIGH and TLOW register format and byte order, see the High and Low Limit Registers section. F1 0 0 1 1 F0 0 1 0 1 CONSECUTIVE FAULTS 1 2 4 6 Table 6. Configuration Register Format SHUTDOWN MODE (SD) The Shutdown Mode of the TMP105 allows the user to save maximum power by shutting down all device circuitry other than the serial interface, which reduces current consumption to typically 1.5µA. Shutdown Mode is enabled when the SD bit is 1; the device will shut down once the current conversion is completed. When SD is equal to 0, the device will maintain a continuous conversion state. THERMOSTAT MODE (TM) The Thermostat Mode bit of the TMP105 indicates to the device whether to operate in Comparator Mode (TM = 0) or Interrupt Mode (TM = 1). For more information on comparator and interrupt modes, see the High and Low Limit Registers section. Table 7. Fault Settings of the TMP105 6 TMP105 www.ti.com SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 CONVERTER RESOLUTION (R1/R0) The Converter Resolution bits control the resolution of the internal analog-to-digital (A/D) converter. This control allows the user to maximize efficiency by programming for higher resolution or faster conversion time. Table 8 identifies the resolution bits and the relationship between resolution and conversion time. CONVERSION TIME (typical) 27.5ms 55ms 110ms 220ms register or a successful response to the SMBus Alert Response address. When the ALERT pin clears, the above cycle will repeat, with the ALERT pin becoming active when the temperature equals or exceeds THIGH. The ALERT pin can also be cleared by resetting the device with the General Call Reset command. This reset also clears the state of the internal registers in the device returning the device to Comparator Mode (TM = 0). Both operational modes are represented in Figure 3. Table 9 and Table 10 describe the format for the THIGH and TLOW Registers. Note that the most significant byte is sent first, followed by the least significant byte. Power-up reset values for THIGH and TLOW are: THIGH = 80°C and TLOW = 75°C The format of the data for THIGH and TLOW is the same as for the Temperature Register. BYTE 1 BYTE 2 D7 H11 D7 H3 D6 H10 D6 H2 D5 H9 D5 H1 D4 H8 D4 H0 D3 H7 D3 0 D2 H6 D2 0 D1 H5 D1 0 D0 H4 D0 0 R1 0 0 1 1 R0 0 1 0 1 RESOLUTION 9 Bits (0.5°C) 10 Bits (0.25°C) 11 Bits (0.125°C) 12 Bits (0.0625°C) Table 8. Resolution of the TMP105 ONE-SHOT (OS) The TMP105 features a One-Shot Temperature Measurement Mode. When the device is in Shutdown Mode, writing a ‘1’ to the OS bit starts a single temperature conversion. The device will return to the shutdown state at the completion of the single conversion. This option is useful to reduce power consumption in the TMP105 when continuous temperature monitoring is not required. When the Configuration Register is read, the OS always reads zero. Table 9. Bytes 1 and 2 of THIGH Register BYTE 1 BYTE 2 D7 L11 D7 L3 D6 L10 D6 L2 D5 L9 D5 L1 D4 L8 D4 L0 D3 L7 D3 0 D2 L6 D2 0 D1 L5 D1 0 D0 L4 D0 0 HIGH AND LOW LIMIT REGISTERS In Comparator Mode (TM = 0), the ALERT pin of the TMP105 becomes active when the temperature equals or exceeds the value in THIGH and generates a consecutive number of faults according to fault bits F1 and F0. The ALERT pin remains active until the temperature falls below the indicated TLOW value for the same number of faults. In Interrupt Mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds THIGH for a consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register occurs, or until the device successfully responds to the SMBus Alert Response address. The ALERT pin clears if the device is placed in Shutdown Mode. Once the ALERT pin is cleared, it will only become active again by the temperature falling below TLOW. When the temperature falls below TLOW, the ALERT pin becomes active and remains active until cleared by a read operation of any Table 10. Bytes 1 and 2 of TLOW Register All 12 bits for the Temperature, THIGH, and TLOW Registers are used in the comparisons for the ALERT function for all converter resolutions. The three LSBs in THIGH and TLOW can affect the ALERT output even if the converter is configured for 9-bit resolution. SERIAL INTERFACE The TMP105 operates only as a slave device on the Two-Wire bus and SMBus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP105 supports the transmission protocol for fast (1kHz to 400kHz) mode. All data bytes are transmitted MSB first. 7 TMP105 www.ti.com SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 SERIAL BUS ADDRESS To communicate with the TMP105, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation. The TMP105 features one address pin allowing up to two devices to be connected per bus. Pin logic levels are described in Table 11. The address pin of the TMP105 is read after reset, at start of communication, or in response to a Two-Wire address acquire request. Following reading of the state of the pin, the address is latched to minimize power dissipation associated with detection. A0 0 1 SLAVE ADDRESS 1001000 1001001 Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data transfer SDA must remain stable while SCL is HIGH, as any change in SDA while SCL is HIGH will be interpreted as a control signal. Once all data has been transferred, the master generates a STOP condition, indicated by pulling SDA from LOW to HIGH while SCL is HIGH. WRITING/READING TO THE TMP105 Accessing a particular register on the TMP105 is accomplished by writing the appropriate value to the Pointer Register. The value for the Pointer Register is the first byte transferred after the slave address byte with the R/W bit LOW. Every write operation to the TMP105 requires a value for the Pointer Register. (Refer to Figure 5.) When reading from the TMP105, the last value stored in the Pointer Register by a write operation is used to determine which register is read by a read operation. To change the register pointer for a read operation, a new value must be written to the Pointer Register. This is accomplished by issuing a slave address byte with the R/W bit LOW, followed by the Pointer Register byte. No additional data are required. The master can then generate a START condition and send the slave address byte with the R/W bit HIGH to initiate the read command. See Figure 6 for details of this sequence. If repeated reads from the same register are desired, it is not necessary to continually send the Pointer Register byte, as the TMP105 remembers the Pointer Register value until it is changed by the next write operation. Note that register bytes are sent most significant byte first, followed by the least significant byte. Table 11. Address Pin and Slave Addresses for the TMP105 BUS OVERVIEW The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a HIGH to LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA LOW. 8 TMP105 www.ti.com SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 SLAVE MODE OPERATIONS The TMP105 can operate as a slave receiver or slave transmitter. Slave Receiver Mode: The first byte transmitted by the master is the slave address, with the R/W bit LOW. The TMP105 then acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer Register. The TMP105 then acknowledges reception of the Pointer Register byte. The next byte or bytes are written to the register addressed by the Pointer Register. The TMP105 acknowledges reception of each data byte. The master may terminate data transfer by generating a START or STOP condition. acknowledge the SMBus Alert command and respond by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte will indicate if the temperature exceeding THIGH or falling below TLOW caused the ALERT condition. This bit will be HIGH if the temperature is greater than or equal to THIGH. This bit will be LOW if the temperature is less than TLOW. Refer to Figure 7 for details of this sequence. If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion of the SMBus Alert command will determine which device will clear its ALERT status. If the TMP105 wins the arbitration, its ALERT pin will become inactive at the completion of the SMBus Alert command. If the TMP105 loses the arbitration, its ALERT pin will remain active. Slave Transmitter Mode: The first byte is transmitted by the master and is the slave address, with the R/W bit HIGH. The slave acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the Pointer Register. The master acknowledges reception of the data byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The master may terminate data transfer by generating a Not-Acknowledge on reception of any data byte, or generating a START or STOP condition. GENERAL CALL The TMP105 responds to a Two-Wire General Call address (0000000) if the eighth bit is 0. The device will acknowledge the General Call address and respond to commands in the second byte. If the second byte is 00000100, the TMP105 will latch the status of the address pin, but will not reset. If the second byte is 00000110, the TMP105 will latch the status of the address pin and reset the internal registers to their power-up values. TIMEOUT FUNCTION The TMP105 will reset the serial interface if either SCL or SDA are held LOW for 54ms (typ) between a START and STOP condition. The TMP105 will release the bus if it is pulled LOW and will wait for a START condition. To avoid activating the timeout function, it is necessary to maintain a communication speed of at least 1kHz for SCL operating frequency. SMBus ALERT FUNCTION The TMP105 supports the SMBus Alert function. When the TMP105 is operating in Interrupt Mode (TM = 1), the ALERT pin of the TMP105 may be connected as an SMBus Alert signal. When a master senses that an ALERT condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP105 is active, the devices will 9 TMP105 www.ti.com SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 TIMING DIAGRAMS The TMP105 is Two-Wire and SMBus-compatible. Figure 4 to Figure 7 describe the various operations on the TMP105. Bus definitions are given below. Parameters for Figure 4 are defined in Table 12. Bus Idle: Both SDA and SCL lines remain HIGH. Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START condition. Each data transfer is initiated with a START condition. Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition. Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data. Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data transfer can be signaled by the master generating a Not-Acknowledge on the last byte that has been transmitted by the slave. PARAMETER SCL Operating Frequency Bus Free Time Between STOP and START Condition Hold time after repeated START condition. After this period, the first clock is generated. Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Data Setup Time SCL Clock LOW Period SCL Clock HIGH Period Clock/Data Fall Time Clock/Data Rise Time for SCLK ≤ 100kHz f(SCL) t(BUF) t(HDSTA) t(SUSTA) t(SUSTO) t(HDDAT) t(SUDAT) t(LOW) t(HIGH) tF tR FAST MODE MIN 1 600 100 100 100 0 100 1300 600 300 300 1000 MAX 400 UNITS kHz ns ns ns ns ns ns ns ns ns ns ns Table 12. Timing Diagram Definitions for the TMP105 TWO-WIRE TIMING DIAGRAMS t(LOW) tR tF t(HDSTA) SCL t(HDSTA) t(HDDAT) SDA t(BU F ) P S S P t(HIGH) t(SUSTA) t(SUDAT) t(SUSTO) Figure 4. Two-Wire Timing Diagram 10 TMP105 www.ti.com SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 1 SCL 9 1 9 … 1 Start By Master Frame 1 Two−Wire Slave Address Byte 1 9 1 0 0 1 0 0 A0 R/W ACK By TMP105 Frame 2 Pointer Register Byte 9 0 0 0 0 0 0 P1 P0 ACK By TMP105 SDA … SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 ACK By TMP105 D7 D6 D5 D4 D3 D2 D1 D0 ACK By TMP105 Stop By Master Frame 3 Data Byte 1 Frame 4 Data Byte 2 Figure 5. Two-Wire Timing Diagram for TMP105 Write Word Format 1 SCL 9 1 9 … … ACK By TMP105 Frame 2 Pointer Register Byte 9 1 9 SDA Start By Master 1 0 0 0 0 A0 R/W ACK By TMP105 0 0 0 0 0 0 P1 P0 Frame 1 Two−Wire Slave Address Byte 1 SCL (Continued) … … ACK By Master SDA (Continued) Start By Master 1 0 0 1 0 0 A0 R/W ACK By TMP105 D7 D6 D5 D4 D3 D2 D1 D0 From TMP105 Frame 4 Data Byte 1 Read Register Frame 3 Two−Wire Slave Address Byte 1 SCL (Continued) 9 SDA (Continued) D7 D6 D5 D4 D3 From TMP105 D2 D1 D0 ACK By Master Stop By Master Frame 5 Data Byte 2 Read Register Figure 6. Two-Wire Timing Diagram for Read Word Format 11 TMP105 www.ti.com SLLS648B − FEBRUARY 2005 − REVISED JANUARY 2006 ALERT 1 SCL 9 1 9 SDA Start By Master 0 0 0 1 1 0 0 R/W ACK By TMP105 1 0 0 1 0 0 A0 Status From TMP105 Frame 2 Slave Address Byte NACK By Master Stop By Master Frame 1 SMBus ALERT Response Address Byte Figure 7. Timing Diagram for SMBus ALERT 12 13 PACKAGE OPTION ADDENDUM www.ti.com 31-Jul-2006 PACKAGING INFORMATION Orderable Device TMP105YZCR TMP105YZCRG4 TMP105YZCT TMP105YZCTG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE Package Type DSBGA DSBGA DSBGA DSBGA Package Drawing YZC YZC YZC YZC Pins Package Eco Plan (2) Qty 6 6 6 6 250 3000 Green (RoHS & no Sb/Br) TBD Green (RoHS & no Sb/Br) TBD Lead/Ball Finish Call TI Call TI Call TI Call TI MSL Peak Temp (3) Level-1-260C-UNLIM Call TI Level-1-260C-UNLIM Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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