TMP1075
SBOS854E – MARCH 2018 – REVISED AUGUST 2021
TMP1075 Temperature Sensor With I2C and SMBus Interface in Industry Standard
LM75 Form Factor and Pinout
1 Features
3 Description
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The TMP1075 is the most accurate and lowest
power replacement to the industry standard LM75
and TMP75 digital temperature sensors. Available
in SOIC-8, VSSOP-8, WSON-8, and SOT563-6
packages, the TMP1075 offers pin-to-pin and
software compatibility to quickly upgrade any existing
xx75 design. The TMP1075 additional new packages
are a 2.0 × 2.0 mm DFN and a 1.6 × 1.6 mm
SOT563-6 reducing the printed circuit board (PCB)
footprint by 82% and 89% compared to the SOIC
package, respectively.
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2 Applications
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Power-supply temperature monitoring
Computer peripheral thermal protection
Notebook computers
Cell phones
Battery management
Office machines
Thermostat controls
Environmental monitoring and HVAC
Electro mechanical device temperature
The TMP1075 has a ±1°C accuracy over a
wide temperature range and offers an on-chip 12bit analog-to-digital converter (ADC) providing a
temperature resolution of 0.0625°C.
Compatible with two-wire SMBus and I2C interfaces,
the TMP1075 support up to 32 device addresses and
provides SMBus Reset and Alert function.
Device Information(1)
PART NUMBER
TMP1075
PACKAGE
(1)
(2)
BODY SIZE (NOM)
VSSOP / DGK (8)
3.00 mm × 3.00 mm
SOIC / D (8)
4.90 mm × 3.91 mm
WSON / DSG (8)
SOT563 / DRL
(6)(2)
2.00 mm × 2.00 mm
1.20 mm × 1.60 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Available as the TMP1075N orderable.
3
Supply Voltage
1.7 V to 5.5 V (TMP1075)
1.62 V to 3.6 V (TMP1075N)
Average
2.5
Average r3V
Min/Max Limit
2
Pullup Resistors
5 k
SDA
Supply Bypass
Capacitor
0.01 µF
V+
A0
Two-Wire
Host Controller
SCL
A1*
Temperature Error (qC)
•
Temperature accuracy:
– ±0.25°C (typical) from −55°C to +125°C
– ±1°C (maximum) from −40 °C to +110°C
– ±2°C (maximum) from −55°C to +125°C
Low power consumption:
– 2.7-μA Average current
– 0.37-μA Shutdown current
Supply range options from: 1.62 V to 5.5 V
Temperature independent of supply
Digital interface: SMBus, I2C
Software compatibility with industry standard LM75
and TMP75
Can coexist in I3C mixed fast mode bus
Resolution: 12 Bits
Supports up to 32 I2C addresses
ALERT pin function
NIST traceability
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
ALERT
A2*
GND
*Pin is not available on
TMP1075N
Simplified Schematic
-3
-55
-35
-15
5
25
45
65
Temperature (qC)
85
105
125
D00X
DGK and D packages
Temperature Accuracy
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMP1075
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 4
6 Device Comparison......................................................... 4
7 Pin Configuration and Functions...................................5
8 Specifications.................................................................. 6
8.1 Absolute Maximum Ratings ....................................... 6
8.2 ESD Ratings .............................................................. 6
8.3 Recommended Operating Conditions ........................6
8.4 Thermal Information ...................................................7
8.5 Electrical Characteristics:TMP1075 ........................... 7
8.6 Electrical Characteristics: TMP1075N ....................... 8
8.7 Timing Requirements:TMP1075 ................................ 9
8.8 Timing Requirements: TMP1075N ...........................10
8.9 Switching Characteristics .........................................10
8.10 Typical Characteristics............................................ 11
9 Detailed Description......................................................13
9.1 Overview................................................................... 13
9.2 Functional Block Diagram......................................... 13
9.3 Feature Description...................................................14
9.4 Device Functional Modes..........................................20
9.5 Register Map.............................................................22
10 Application and Implementation................................ 26
10.1 Application Information........................................... 26
10.2 Typical Application.................................................. 26
11 Power Supply Recommendations..............................27
12 Layout...........................................................................28
12.1 Layout Guidelines................................................... 28
12.2 Layout Example...................................................... 28
13 Device and Documentation Support..........................31
13.1 Receiving Notification of Documentation Updates..31
13.2 Support Resources................................................. 31
13.3 Trademarks............................................................. 31
13.4 Electrostatic Discharge Caution..............................31
13.5 Glossary..................................................................31
14 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (October 2019) to Revision E (August 2021)
Page
• Added TMP1075N features to list.......................................................................................................................1
• Added typical accuracy specification to features list...........................................................................................1
• Added the SOT563 (TMP1075N orderable) package.........................................................................................1
• Added TMP1075N temperature range to description (continued section)..........................................................4
• Added Device Comparison Section.................................................................................................................... 4
• Added figures for different package options....................................................................................................... 5
• Added column for TMP1075N pin numbers........................................................................................................5
• Added TMP1075N Specifications....................................................................................................................... 6
• Added TMP1075NDRL Temperature Error vs. Temperature graph ................................................................. 11
• Added TMP1075N information in Overview Section.........................................................................................13
• Changed the Functional Block Diagram to apply to TMP1075N...................................................................... 13
• Added number of I2C addresses available on TMP1075N to Serial Bus Address Section. ............................ 15
• Added table for TMP1075N address options. ..................................................................................................15
• Updated internal register structure figure to apply to TMP1075N.....................................................................15
• Added typical specification for TMP1075N timeout ......................................................................................... 17
• Added clarification on timeout function to include SCL.....................................................................................17
• Removed redundant information to accurate describe all packages................................................................ 20
• Added TMP1075N OS bit behavior.................................................................................................................. 20
• Added TMP1075N Continuous Conversion Mode information......................................................................... 20
• Updated Conversion Rate Diagram to reflect all TMP1075 and TMP1075N....................................................20
• Clarified what TM bit behavior for TMP1075 and TMP1075N ......................................................................... 21
• Added table note to indicate Device ID register is not available on TMP1075N...............................................22
• Added TMP1075N configuration register information ......................................................................................23
• Updated text to indicate that device ID register does not apply to TMP1075N................................................ 25
• Added number of I2C addresses available on TMP1075N...............................................................................26
• Changed Typical Connections figure to apply to TMP1075N........................................................................... 26
• Removed redundant Application Curve section................................................................................................26
• Updated text to include TMP1075N information............................................................................................... 26
2
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SBOS854E – MARCH 2018 – REVISED AUGUST 2021
Updated Migrating From the xx75 Device Family section to specify TMP1075 compatible packages ............27
Included TMP1075N information to Power Supply Recommendations............................................................ 27
Added figures to the Layout Example section for each package......................................................................28
Changes from Revision C (January 2019) to Revision D (October 2019)
Page
• Added software compatibility to feature list........................................................................................................ 1
• Updated absolute max for Power supply V+ to 6.5V from 6V.............................................................................6
• Updated absolute max for Input voltage on SCL, SDA, A1, A0 to 6.5V from 6V................................................6
• Updated pointer register to be part of the serial interface description.............................................................. 15
• Updated the register map table to new format..................................................................................................22
• Added access type codes for register bits........................................................................................................ 22
• Updated temperature register format and bit definition table............................................................................22
• Updated configuration register format and bit definition table ......................................................................... 23
• Updated low limit register format and bit definition table ................................................................................. 24
• Updated high limit register format and bit definition table ................................................................................24
• Updated device ID register format and bit definition table ............................................................................... 25
Changes from Revision B (December 2018) to Revision C (January 2019)
Page
• Changed TMP1075DSG package moved from Preview to Production Data......................................................1
• Changed min/max limit from 1.5°C to 1°C in the Temperature Accuracy (DGK & D) graph...............................1
• Changed min/max limit from 1.5°C to 1°C in the DGK & D Temperature Error vs. Temperature graph........... 11
• Added DSG Temperature Error vs. Temperature graph ...................................................................................11
Changes from Revision A (June 2018) to Revision B (December 2018)
Page
• Added TMP1075DSG package ......................................................................................................................... 1
• Updated description section of the data sheet and added a Description (continued) section............................ 1
• Added TMP1075 configuration register support for single byte read and write................................................ 23
• Added Software support section for migrating from xx75 to TMP1075 ........................................................... 27
Changes from Revision * (March 2018) to Revision A (June 2018)
Page
• Changed the TMP1075DGK orderable status from Advanced Information to Production Data......................... 1
• Added SOIC and DFN packages........................................................................................................................1
• Changed the Functional Block Diagram .......................................................................................................... 13
• Changed Digital Temperature Output crossreference from: Temperature Register (0x00) to: Temperature
Data Format .....................................................................................................................................................14
• Changed the Temperature Data Format table ................................................................................................. 14
• Changed and renamed the Address Pins and Slave Addresses for the TMP1075 table to Address Pins State
..........................................................................................................................................................................15
• Changed the Two-Wire Timing Diagrams section ............................................................................................18
• Added content to the Device Functional Modes section ..................................................................................20
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5 Description (continued)
The TMP1075 is designed for accurate and cost-effective temperature measurement in virtually any
telecommunication, enterprise, industrial and personal electronics equipment.
The TMP1075 D, DGK, and DSG packages are specified for operation over a temperature range of −55°C to
+125°C and the TMP1075N DRL package is specified over the −40°C to +125°C temperature range.
The TMP1075 units are 100% tested on a production setup that is NIST traceable and verified with equipment
that is calibrated to ISO/IEC 17025 accredited standards.
6 Device Comparison
Table 6-1 lists the key specification and feature differences between the different TMP1075 packages.
Table 6-1. Package Feature and Spec Comparison
TMP1075
SPEC/FEATURE
4
TMP1075N
D
DGK
DSG
DRL
Supply Voltage
1.7 V to 5.5 V
1.7 V to 5.5 V
1.7 V to 5.5 V
1.62 V to 3.6V
Temperature Range
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–40°C to +125°C
Body Size
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
2.00 mm × 2.00 mm
1.60 mm × 1.20 mm
Accuracy
±1.0°C: –40°C to +110°C
±2.0°C: –55°C to +125°C
±1.0°C: –40°C to +110°C
±2.0°C: –55°C to +125°C
±1.0°C : –40°C to +75°C
±2.0°C: –55°C to +125°C
±1.0°C: –10°C to +60°C
±2.0°C: –40°C to +125°C
I2C Addresses
32
32
32
4
Conversion Rate
Settings
Yes
Yes
Yes
No
Device ID
Yes
Yes
Yes
No
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7 Pin Configuration and Functions
SDA
1
8
V+
SCL
2
7
A0
ALERT
3
6
A1
GND
4
5
A2
Figure 7-1. D Package 8-Pin SOIC Top View
SDA
1
8
V+
SCL
2
7
A0
ALERT
GND
3
6
4
5
SDA
1
8
V+
SCL
2
7
A0
ALERT
3
6
A1
GND
4
5
A2
.
Figure 7-2. DGK Package 8-Pin VSSOP Top View
SCL
1
6
SDA
GND
2
5
V+
ALERT
3
4
A0
A1
A2
1. Pin 1 is determined by orienting the package
marking as indicated in the diagram.
2. Referred to as the TMP1075N orderable
throughout the document.
.
.
Figure 7-3. DSG Package 8-Pin WSON Top View
Figure 7-4. DRL Package 6-Pin SOT563 Top View
Table 7-1. Pin Functions
PIN
SOIC /
VSSOP /
WSON
SOT563
A0
7
4
I
Address select A0: Connect to GND, V+, SDA, or SCL
A1
6
—
I
Address select A1: Connect to GND, V+, SDA, or SCL
A2
5
—
I
Address select A2: Connect to GND or V+
ALERT
3
3
O
Overtemperature alert; Open-drain output that requires a pullup resistor
GND
4
2
—
Ground
SCL
2
1
I
SDA
1
6
I/O
V+
8
5
I
NAME
I/O
DESCRIPTION
Serial clock
Serial data. Open-drain output that requires a pullup resistor
Supply voltage, 1.7 V to 5.5 V (TMP1075); 1.62 V to 3.6 V
(TMP1075N)
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
TMP1075
Power supply, V+
6.5
TMP1075N
UNIT
V
4
Input voltage SCL, SDA, A1, A0
TMP1075
–0.3
6.5
V
Input voltage SCL, SDA, A0
TMP1075N
–0.3
4
V
(V+)+0.3 and
≤4
V
–0.3
(V+) + 0.3
V
–55
150
°C
150
°C
130
°C
Input voltage ALERT
TMP1075N
Input voltage A2 pin
TMP1075
Operating temperature
Junction temperature, TJ
Storage temperature, Tstg
(1)
–60
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
2000
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
Operating free-air temperature, TA
6
TMP1075
NOM
1.7
TMP1075N
1.62
TMP1075
TMP1075N
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MAX
5.5
3.3
UNIT
V
3.6
V
–55
125
°C
-40
125
°C
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8.4 Thermal Information
THERMAL
METRIC(1)
TMP1075
TMP1075
TMP1075
TMP1075N
DGK (VSSOP)
D (SOIC)
DSG (WSON)
DRL (SOT)
8 PINS
8 PINS
8 PINS
6 PINS
202.5
130.4
87.4
210.3
°C/W
82
76.9
111.1
105.0
°C/W
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal
resistance
RθJB
Junction-to-board thermal resistance
124.4
72.3
54
87.5
°C/W
ΨJT
Junction-to-top characterization
parameter
17.9
32
9.8
6.1
°C/W
ΨJB
Junction-to-board characterization
parameter
122.6
71.9
54.4
87.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
__
__
28.1
__
°C/W
MT
Thermal mass
16.6
64.2
5.0
__
mJ/°C
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics:TMP1075
at TA = –55°C to +125°C and V+ = 1.7 V to 5.5 V (unless noted); typical specification are at TA = 25°C and V+=3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
125
°C
TEMPERATURE INPUT
Range
–55
Accuracy
(temperature
error)
DGK, D
DSG
–40°C to +110°C
±0.25
±1
–55°C to +125°C
±0.25
±2
–40°C to +75°C
±0.25
±1
°C
–55°C to +125°C
±0.25
±2
°C
Accuracy (temperature error)
PSRR
vs. supply
±0.03
°C
°C/V
Resolution
1 LSB (12 bit)
0.0625
°C
Repeatability(1)
25°C, V+= 3.3 V(2)
0.0625
°C
500 hours at 150°C, 5.5V
0.0625
°C
5
pF
Long-term
drift(3)
DIGITAL INPUT/OUTPUT
Input capacitance
VIH
High-level input logic
VIL
Low-level input logic
IIN
Leakage input current
VOL
0.7(V+)
Input voltage hysteresis
SCL and SDA pins
Low-level output logic
IOL = -3 mA, SDA and ALERT pins
ADC Conversion time
one-shot mode
Conversion Time
Reset time
V
0.25
µA
0
0
0.15
0.4
5.5
7
600
4.5
mV
V
ms
27.5
R1 = 0, R0 = 1
55
R1 = 1, R0 = 0
110
R1 = 1, R0 = 1
220
The time between reset till ADC conversion start
0.3
Conversion Rate Variation
0.3(V+)
–0.25
R1 = 0, R0 = 0 (default)
TC
V
ms
ms
–10
0
10
%
1.7
3.3
5.5
V
POWER SUPPLY
Operating voltage range
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at TA = –55°C to +125°C and V+ = 1.7 V to 5.5 V (unless noted); typical specification are at TA = 25°C and V+=3.3 V
PARAMETER
TEST CONDITIONS
MIN
R1 = 0, R0 = 0 (default)
R1 = 0, R0 = 1
Quiescent current (serial bus
R1 = 1, R0 = 0
inactive)
R1 = 1, R0 = 1
IQ
ISD
Shutdown current
Power supply thresholds
(1)
(2)
(3)
TYP
MAX
10
20
5.5
9
4
6
2.7
4
During 5.5 ms active conversion
52
85
Serial bus active, SCL frequency = 400 kHz,
A0=A1=A2=GND
13
UNIT
µA
µA
µA
µA
Serial bus inactive, A0=A1=A2=SCL=SDA=V+,
25°C
0.37
0.65
µA
Serial bus inactive, A0=A1=A2=SCL=SDA=V+
0.37
3.5
µA
Supply rising, Power-on Reset
1.22
Supply failing, Brown-out Detect
V
1.1
Repeatability is the ability to reproduce a reading when the measured temperature is applied consecutively, under the same conditions.
One-shot mode setup, 1 sample per minute for 24 hours.
Long-term drift is determined using accelerated operational life testing at a junction temperature of 150°C.
8.6 Electrical Characteristics: TMP1075N
At TA = 25°C and V+ = 1.62 to 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
125
°C
TEMPERATURE SENSOR
Temperature Operating
Range
TERR
Temperature accuracy
PSR
DC power supply rejection
TRES
Temperature resolution
tCONV
Conversion time
-40
-10°C to 60°C
0.25
±1
-40°C to 125°C
0.5
±2
0.2
0.5
Including sign bit
LSB
°C
°C/V
12
Bits
62.5
m°C
26
35
ms
DIGITAL INPUT/OUTPUT
CIN
Input capacitance
3
VIH
Input logic high level
VIL
Input logic low level
IIN
Input leakage current
0 V< V+ < 3.6 V
VOL
Output low level
SDA, ALERT (V+ > 2 V, IOL = 3 mA)
0
VOL
Output low level
SDA, ALERT (V+ < 2 V, IOL = 3 mA)
0
0.2 x V+
V
3.6
V
0.7 x V+
pF
3.6
V
0.3 x V+
V
1
μA
0.4
V
POWER SUPPLY
V+
Operating supply range
1.62
Serial bus inactive
IDD_AVG
IDD_SD
8
Average current
consumption
Shutdown current
7
10
μA
Serial bus active, SCL frequency = 400 kHz
15
Serial bus active, SCL frequency = 2.85 MHz
85
Serial bus inactive
0.5
Serial bus active, SCL frequency = 400 kHz
10
μA
Serial bus active, SCL frequency = 2.85 MHz
80
μA
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8.7 Timing Requirements:TMP1075
minimum and maximum specifications are over –55°C to 125°C and V+ = 1.7 V to 5.5 V (unless otherwise noted)(1)
FAST MODE
HIGH-SPEED MODE
MIN
MAX
MIN
MAX
0.4
0.001
2.56
UNIT
f(SCL)
SCL operating frequency
0.001
t(BUF)
Bus-free time between STOP and START conditions
1300
160
ns
t(HDSTA)
Hold time after repeated START condition.
After this period, the first clock is generated.
600
160
ns
t(SUSTA)
Repeated START condition setup time
600
160
ns
t(SUSTO)
STOP condition setup time
600
160
t(HDDAT)
Data hold time(2)
0
0
t(SUDAT)
Data setup time
100
20
ns
t(LOW)
SCL clock low period
1300
250
ns
t(HIGH)
SCL clock high period
600
t(VDAT)
Data valid time (data response time)(3)
900
130
ns
tFDA
Data fall time
300
100
ns
tR
Clock rise time
300
40
ns
tF
Clock fall time
300
40
ns
ttimeout
Timeout (SCL = SDA = GND)
30
ms
tRC
Clock/ data rise time for SCL = 100 kHz
(1)
(2)
(3)
20
ns
130
60
30
1000
20
MHz
ns
ns
ns
The host and device have the same V+ value. Values are based on statistical analysis of samples tested during initial release.
The maximum t(HDDAT) can be 0.9 µs for fast mode, and is less than the maximum t(VDAT) by a transition time.
t(VDAT) = time for data signal from SCL LOW to SDA output (HIGH to LOW, depending on which is worse). = time for data signal from
SCL LOW to SDA output (HIGH to LOW, depending on which is worse).
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8.8 Timing Requirements: TMP1075N
minimum and maximum specifications are over –40°C to 125°C and V+ = 1.62 V to 3.6 V (unless otherwise noted)(1)
FAST MODE
HIGH-SPEED MODE
MIN
MAX
MIN
MAX
0.001
0.4
0.001
2.85
UNIT
f(SCL)
SCL operating frequency
t(BUF)
Bus-free time between STOP and START conditions
600
160
ns
t(HDSTA)
Hold time after repeated START condition.
After this period, the first clock is generated.
600
160
ns
t(SUSTA)
Repeated START condition setup time
600
160
ns
t(SUSTO)
STOP condition setup time
600
160
t(HDDAT)
Data hold time(2)
100
t(SUDAT)
Data setup time
100
25
ns
t(LOW)
SCL clock low period
1300
210
ns
t(HIGH)
SCL clock high period
600
tFD
Data fall time
tRD
Data rise time
tRC
Clock rise time
tFC
Clock fall time
ttimeout
Timeout (SCL = SDA = GND)
(1)
(2)
900
25
ns
105
60
300
MHz
ns
ns
80
ns
40
ns
300
SCLK ≤100 kHz
1000
300
300
30
40
30
40
ns
40
ms
The host and device have the same V+ value. Values are based on statistical analysis of samples tested during initial release.
The maximum t(HDDAT) can be 0.9 µs for fast mode, and is less than the maximum t(VDAT) by a transition time.
8.9 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
MIN
tLPF
10
Spike filter for I3C compatibility
SCL= 12.5 MHz
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8.10 Typical Characteristics
at TA = 25°C, V+ = 3.3 V, and apply to D, DGK, and DSG packages (unless otherwise noted)
3
3
Average
Average r3V
Min/Max Limit
2
2
1.5
1.5
1
0.5
0
-0.5
-1
-1.5
1
0
-0.5
-1
-1.5
-2
-2
-2.5
-35
-15
5
25
45
65
Temperature (qC)
85
105
-3
-55
125
-35
-15
5
D00X
Figure 8-1. DGK & D Temperature Error vs.
Temperature
Min/Max Limit
Average r3V
0.5
-2.5
-3
-55
Average
2.5
Temperature Error (qC)
Temperature Error (qC)
2.5
25
45
65
Temperature (qC)
85
105
125
D00X
Figure 8-2. DSG Temperature Error vs.
Temperature
1.5
Supply Current (PA)
V+ = 5.5 V
V+ = 3.3 V
V+ = 1.7 V
1
0.5
0
-55
Figure 8-3. TMP1075NDRL Temperature Error vs.
Temperature
27.5 mSec
55 mSec
110 mSec
220 mSec
Supply Current (PA)
Supply Current (PA)
10
8
6
4
2
0
-55
-35
-15
5
25
45
65
Temperature (qC)
85
105
125
5
25
45
65
Temperature (qC)
650
600
550
500
450
400
350
300
250
200
150
100
50
0
85
105
125
D002
V+ = 5.5 V
V+ = 4.5 V
V+ = 3.3 V
V+ = 2.5 V
V+ = 1.7 V
Limit
0
10
D002
Figure 8-5. Average Current vs. Conversion Rates
and Temperature
-15
Figure 8-4. Shutdown Current vs. Temperature
14
12
-35
20
30
40
50
60
VIN/VSupply (%)
70
80
90
100
D004
Figure 8-6. Supply Current vs. Input Cell Voltage
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1
90
80
0.8
60
50
40
30
0.7
0.6
0.5
0.4
20
0.3
10
0.2
0
0.1
-10
1.5
V+ = 1.7 V
V+ = 2.5 V
V+ = 3.3 V
V+ = 5.5 V
0.9
Pin Voltage (V)
Supply Current (PA)
70
1 MHz
400 KHz
100 KHz
No I2C
0
2
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
6
0
1
2
3
4
D005
Figure 8-7. Supply Current vs. I2C Bus Clock and
Supply Voltage in Shutdown Mode
5
6 7 8 9 10 11 12 13 14 15 16 17
Pin Sink Current (mA)
D006
Figure 8-8. ALERT Pin Output Voltage vs. Sink
Current
6
5
4
Change in %
3
2
1
0
-1
-2
-3
-4
-5
-6
-55
-35
-15
5
25
45
65
Temperature (qC)
85
105
125
D007
Figure 8-9. Sampling Period Change vs. Temperature (1.7 V to 5.5 V)
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9 Detailed Description
9.1 Overview
The TMP1075 device is a digital temperature sensor that is optimal for thermal management and thermal
protection applications. The TMP1075 is a SMBus and is I2C interface-compatible. It is also capable of
coexisting in an I3C bus when in Mixed Fast Mode. The TMP1075 non-N orderables are specified over a
temperature range of −55°C to +125°C and the TMP1075N orderable is specified over the −40°C to +125°C
temperature range. The Figure 9-1 section shows an internal block diagram of TMP1075 device.
The temperature sensor thermal path runs through the package leads as well as the plastic package. The leads
provide the primary thermal path due to the lower thermal resistance of the metal.
9.2 Functional Block Diagram
V+
A2*
A0, A1*
Serial
Interface
SCL
V+
SDA
**
Register
Bank
ALERT
Oscillator
Control
Logic
Internal
Thermal
BJT Sensor
Temperature
Sensor
Circuitry
*Pin is not available on TMP1075N
** ESD Diode only in TMP1075N
ADC
GND
Figure 9-1. Functional Block Diagram
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9.3 Feature Description
9.3.1 Digital Temperature Output
The digital output from each temperature measurement conversion is stored in the read-only temperature
register. Which is a 12-bit, read-only register that stores the output of the most recent conversion. Two bytes
must be read to obtain data. However, only the first 12 MSBs are used to indicate temperature while the
remaining 4 LSB are set to zero. Table 9-1 lists the data format for the temperature. Negative numbers are
represented in binary two's-complement format. After power-up or reset, the temperature register reads 0°C until
the first conversion is complete.
Table 9-1. Temperature Data Format
TEMPERATURE
(°C)
DIGITAL OUTPUT
BINARY
HEX
127.9375
0111 1111 1111 0000
7FF0
100
0110 0100 0000 0000
6400
80
0101 0000 0000 0000
5000
75
0100 1011 0000 0000
4B00
50
0011 0010 0000 0000
3200
25
0001 1001 0000 0000
1900
0.25
0000 0000 0100 0000
0040
0.0625
0000 0000 0001 0000
0010
0
0000 0000 0000 0000
0000
–0.0625
1111 1111 1111 0000
FFF0
–0.25
1111 1111 1100 0000
FFC0
–25
1110 0111 0000 0000
E700
–50
1100 1110 0000 0000
CE00
–128
1000 000 0000 0000
8000
9.3.2 I2C and SMBus Serial Interface
The TMP1075 operates as a target device on the two-wire, SMBus and I2C interface-compatible bus.
Connections to the bus are made through the open-drain I/O line SDA and SCL input pin. The SDA and SCL
pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and
bus noise. The TMP1075 supports the transmission protocol for fast mode up to 400 kHz and high-speed mode
up to 2.56 MHz. All data bytes are transmitted MSB first.
9.3.2.1 Bus Overview
The device that initiates the data transfer is called a host, and the devices controlled by the host are the target.
The bus must be controlled by a host device that generates the SCL that controls the bus access and generates
the START and STOP conditions.
To address a specific device, a START condition is initiated. This is indicated by the host pulling the data line
SDA from a high to low logic level when SCL is high. All target devices on the bus shift in the device address
byte on the rising edge of the clock with the last bit indicating whether a read or write operation is intended.
During the ninth clock pulse, the device being addressed responds to the host by generating an Acknowledge
and pulling SDA low.
Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge bit. During data
transfer, SDA must remain stable when SCL is high because any change in SDA when SCL is high is interpreted
as a control signal.
When all data are transferred, the host generates a STOP condition indicated by pulling SDA from low to high
logic level when SCL is high.
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9.3.2.2 Serial Bus Address
To communicate with the TMP1075, the host must first address devices through an address byte. The device
address byte consists of seven address bits and a direction bit indicating the intent of executing a read or write
operation.
The TMP1075 features three address pins to allow up to 32 devices (TMP1075N: 4) to be addressed on a single
bus interface. Table 9-2 and Table 9-3 describe the pin logic levels used to configure the TMP1075 I2C address.
The state of pins A0, A1, and A2 is sampled on every bus communication and must be set prior to any activity on
the interface.
Table 9-2. TMP1075 Address Pins State
A2
A1
A0
7-BIT ADDRESS
A2
A1
A0
7-BIT ADDRESS
0
0
SDA
1000000
0
SDA
SDA
1010000
0
0
SCL
1000001
0
SDA
SCL
1010001
0
1
SDA
1000010
0
SCL
SDA
1010010
0
1
SCL
1000011
0
SCL
SCL
1010011
1
0
SDA
1000100
1
SDA
SDA
1010100
1
0
SCL
1000101
1
SDA
SCL
1010101
1
1
SDA
1000110
1
SCL
SDA
1010110
1
1
SCL
1000111
1
SCL
SCL
1010111
0
0
0
1001000
0
SDA
0
1011000
0
0
1
1001001
0
SDA
1
1011001
0
1
0
1001010
0
SCL
0
1011010
0
1
1
1001011
0
SCL
1
1011011
1
0
0
1001100
1
SDA
0
1011100
1
0
1
1001101
1
SDA
1
1011101
1
1
0
1001110
1
SCL
0
1011110
1
1
1
1001111
1
SCL
1
1011111
Table 9-3. TMP1075N Address Pins State
A0
7-BIT ADDRESS
0
1001000
1
1001001
SDA
1001010
SCL
1001011
9.3.2.3 Pointer Register
Figure 9-2 shows the internal register structure of the TMP1075, and Table 9-5 lists the pointer addresses of the
register map. Table 9-4 shows that the register map reset value of the pointer register is 00h.
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Pointer
Register
Temperature
Register
SCL
Conguraon
Register
I/O
Control
Interface
TLOW
Register
SDA
THIGH
Register
Device ID*
* Not available on TMP1075N package
Figure 9-2. Internal Register Structure
9.3.2.3.1 Pointer Register Byte [reset = 00h]
Table 9-4. Pointer Register Byte
P7
P6
P5
P4
0
0
0
0
P3
P2
P1
P0
Register Bits
9.3.2.4 Writing and Reading to the TMP1075
Accessing a particular register on the TMP1075 device is accomplished by writing the appropriate value to the
pointer register. After Reset, the register value is set to zero. The value for the pointer register is the first byte
transferred after the device address byte with the R/W bit low. Every write operation to the TMP1075 requires a
value for the pointer register (see Figure 9-3).
When reading from the TMP1075 device, the last value stored in the pointer register by a write operation is used
to determine which register is read by a read operation. To change the register pointer for a read operation,
a new value must be written to the pointer register. This action is accomplished by issuing a device address
byte with the R/ W bit low, followed by the pointer register byte. No additional data are required. The host can
then generate a START condition and send the device address byte with the R/ W bit high to initiate the read
command. See Figure 9-5 for details of this sequence. If repeated reads from the same register are desired, the
pointer register bytes do not have to be continually sent because the TMP1075 remembers the pointer register
value until the value is changed by the next write operation.
Register bytes are sent MSB first.
9.3.2.5 Operation Mode
The TMP1075 can operate as a receiver or transmitter. As a target device, the TMP1075 never drives the SCL
line.
9.3.2.5.1 Receiver Mode
The first byte transmitted by the host is the device address with the R/W bit low. The TMP1075 then
acknowledges reception of a valid address. The next byte transmitted by the host is the pointer register. The
TMP1075 then acknowledges reception of the pointer register byte. The next byte or bytes are written to the
register addressed by the pointer register. The TMP1075 acknowledges reception of each data byte. The host
can terminate data transfer by generating a START or STOP condition.
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9.3.2.5.2 Transmitter Mode
The first byte is transmitted by the host and is the device address, with the R/W bit high. The target device
acknowledges reception of a valid device address. The next byte is transmitted by the device and is the most
significant byte of the register indicated by the Pointer register. The host acknowledges reception of the data
byte. The next byte transmitted by the device is the least significant byte. The host acknowledges reception of
the data byte. The host can terminate data transfer by generating a Not-Acknowledge on reception of any data
byte, or generating a START or STOP condition.
9.3.2.6 SMBus Alert Function
The TMP1075 supports the SMBus Alert function. When the TMP1075 is operating in interrupt mode (TM = 1),
the ALERT pin of the TMP1075 can be connected as an SMBus Alert signal. When a host senses that an alert
condition is present on the ALERT line, the host sends an SMBus Alert command (00011001) on the bus. If
the ALERT pin of the TMP1075 is active, the devices acknowledge the SMBus Alert command and respond by
returning the device address on the SDA line. The eighth bit (LSB) of the device address byte indicates if the
temperature exceeding THIGH or falling below TLOW caused the alert condition. This bit is equal to POL if the
temperature is greater than or equal to THIGH. This bit is equal to POL if the temperature is less than TLOW. See
Figure 9-8 for details of this sequence.
If multiple devices on the bus respond to the SMBus Alert command, arbitration during the device address
portion of the SMBus Alert command determines which device clears the alert status. If the TMP1075 wins the
arbitration, the ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP1075
loses the arbitration, the ALERT pin remains active.
9.3.2.7 General Call- Reset Function
The TMP1075 responds to the two-wire general call address (0000 000) if the eighth bit is 0. The device
acknowledges the general call address and responds to commands in the second byte. If the second byte is
00000 110, the TMP1075 resets the internal registers to the power-up reset values.
9.3.2.8 High-Speed Mode (HS)
For the two-wire bus to operate at frequencies above 400 kHz, the host device must issue an HS mode host
code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The
TMP1075 device does not acknowledge this byte, but it does switch the input filters on the SDA and SCL and
the output filters on the SDA to operate in HS mode. After the HS mode host code is issued, the host transmits
a two-wire device address to initiate a data transfer operation. The bus continues to operate in HS mode until
a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP1075 switches the input and
output filters back to fast-mode operation.
9.3.2.9 Coexists in I3C Mixed Fast Mode
A bus with both I3C and I2C interfaces is referred to as a mixed fast mode with clock speeds up to 12.5 MHz.
In order for the TMP1075, which is an I2C device, to coexist in the same bus, the device incorporated a spike
suppression filter of 50 ns on the SDA and SCL pins to avoid any interference to the bus when communicating
with I3C devices.
9.3.2.10 Time-Out Function
The TMP1075 resets the serial interface if SCL is held low by the host or SDA is held low by the TMP1075 for 25
ms (TMP1075N: 30 ms) (typical) between a START and STOP condition. The TMP1075 releases the SDA bus
and waits for a START condition. To avoid activating the time-out function, a communication speed of at least 1
kHz must be maintained.
9.3.3 Timing Diagrams
The TMP1075 is two-wire SMBus and I2C interface-compatible. Figure 9-3 to Figure 9-8 describe the various
operations on the TMP1075. The following list provides bus definitions.
Bus Idle: Both SDA and SCL lines remain high.
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Start Data Transfer: A change in the state of the SDA line from high to low when the SCL line is high defines a
START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a
STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and
is determined by the host device. The receiver acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device
that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA
line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken
into account. On a host receive, the termination of the data transfer can be signaled by the host generating a
Not-Acknowledge on the last byte that is transmitted by the target device.
9.3.4 Two-Wire Timing Diagrams
1
9
9
1
«
SCL
SDA
0
1
A4
A3
A2
A1
A0
R/W
Start By
Host
0
0
0
0
P3
P2
P1
«
P0
ACK By
Device
ACK By
Device
Frame 1 Two Wire Device Address Byte
Frame 2 Pointer Register Byte
9
1
1
9
SCL
(Continued)
SDA
(Continued)
D15 D14 D13 D12 D11 D10
D9
D7
D8
D6
D5
D4
D3
D2
D1
D0
ACK By
Device
ACK By
Device
Stop By
Host
Frame 4 Data Byte 2
Frame 3 Data Byte 1
Figure 9-3. Two-Wire Timing Diagram for Write Word Format
1
9
9
1
…
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
R/W
Start By
Master
0
0
0
0
0
0
P1
ACK By
Device
…
ACK By
Device
Frame 2 Pointer Register Byte
Frame 1 Two-Wire Device Address Byte
9
1
P0
9
SCL
(Continued)
SDA
(Continued)
D15
D14
D13 D12 D11 D10
D9
D8
ACK By
Device
StopBy
Master
Frame 3 Data Byte 1
Figure 9-4. Two-Wire Timing Diagram for Write Single Byte Format
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1
9
1
9
«
SCL
SDA
1
0
A4
A3
A2
A1
A0
0
R /W
Start By
Host
0
0
0
P3
P2
P1
«
P0
ACK By
Device
ACK By
Device
Frame 1 Two-Wire Device Address Byte
Frame 2 Pointer Register Byte
1
9
1
9
SCL
(Continued)
«
SDA
(Continued)
1
0
A4
A3
A2
A1
R/W
A0
D15
Start By
Host
D14
D13
D12
D11
D10
ACK By
Device
«
D8
From
Device
Frame 3 Two-Wire Device Address Byte
1
D9
ACK By
Host
Frame 4 Data Byte 1 Read Register
9
SCL
(Continued)
SDA
D7
(Continued)
D6
D5
D4
D3
D2
D1
D0
From
Device
ACK By
Host
Stop By
Host
Frame 5 Data Byte 2 Read Register
Figure 9-5. Two-Wire Timing Diagram for Read Word Format
1
9
1
9
«
SCL
SDA
1
0
A4
A3
A2
A1
A0
0
R /W
Start By
Host
0
0
0
P3
P2
P1
ACK By
Device
ACK By
Device
Frame 1 Two-Wire Device Address Byte
1
«
P0
Frame 2 Pointer Register Byte
9
1
9
SCL
(Continued)
SDA
(Continued)
1
0
A4
A3
A2
A1
A0
R/W
Start By
Host
D15
D14
D13
ACK By
Device
Frame 3 Two-Wire Device Address Byte
D12
D11
D10
D9
D8
From
Device
NACK By
Host
Stop By
Host
Frame 4 Data Byte 1 Read Register
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Figure 9-6. Two-Wire Timing Diagram for Read Single Byte Format
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1
9
1
9
SCL
SDA
0
0
0
0
0
0
0
Start By
Host
1
R/W
0
0
0
0
0
1
ACK By
Device
1
0
From
Host
Frame 1 Address Byte
ACK By
Device
Stop By
Host
Frame 2 Command Byte
Figure 9-7. General-Call Reset Command Timing Diagram
ALERT
1
9
1
9
SCL
SDA
0
0
0
1
1
0
0
1
R/W
Start By
Host
0
A4
A3
A2
A1
ACK By
Device
A0
Status
From
Device
NACK By Stop By
Host
Host
Frame 2 Device Address Byte
Frame 1 SMBus ALERT Response Address Byte
Figure 9-8. Timing Diagram for SMBus Alert
9.4 Device Functional Modes
9.4.1 Shutdown Mode (SD)
Shutdown mode (SD) of the TMP1075 device allows the user to conserve power by shutting down all device
circuitry except the serial interface, which significantly reduces the current consumption. SD is initiated when the
SD bit in the configuration register is set to 1. When SD is equal to 0, the device stays in continuous conversion
mode.
9.4.2 One-Shot Mode (OS)
The TMP1075 features a one-shot mode (OS) temperature measurement. When the device is in shutdown
mode, writing 1 to the OS bit starts a single temperature conversion. The device returns to the shutdown state
at the completion of the single conversion. This feature is useful to reduce power consumption in the TMP1075
when continuous temperature monitoring is not required.
When the configuration register is read, the OS bit always reads 0 on TMP1075 non-N orderables. On the
TMP1075N orderable, the OS bit reads back 0 during the one-shot conversion and 1 after the conversion cycle.
9.4.3 Continuous Conversion Mode (CC)
When the device is operating in continuous conversion mode (SD=0), every conversion cycle consists of an
active conversion, followed by a standby (see Figure 9-9). The device consumes a higher current during an
active conversion, and lower current during standby. Active conversion time is 5.5 ms (TMP1075N: 23 ms)
before the part goes in standby. Table 9-8 shows the list of conversion cycle configured using [R1:R0] bits in the
configuration register.
1 Conversion Cycle
Acve Conversion
Standby
Ac ve
Conversion me
Acve
Conversion me
Start-Up
Start of
Conversion
Figure 9-9. Conversion Rate Diagram
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9.4.4 Thermostat Mode (TM)
The thermostat mode bit indicates whether ALERT pin operates in comparator mode (TM = 0) or interrupt mode
(TM = 1). ALERT pin mode is controlled by TM (bit 9) of the configuration register. Any write to the TM bit
changes the ALERT pin to a none active condition, clears the faults count, and clears the alert interrupt history
on the TMP1075 non-N orderables. The ALERT pin can be disabled in both comparator and interrupt modes if
both limit registers are set to the rail values TLOW = –128°C and THIGH = +127.9375°C on the TMP1075 non-N
orderables.
9.4.4.1 Comparator Mode (TM = 0)
In comparator mode (TM = 0), the ALERT pin becomes active when the temperature equals or exceeds the
value in THIGH for a consecutive number of Fault Queue bits [F1:F0]. The ALERT pin remains active until the
temperature falls below the indicated TLOW value for the same number of faults.
The difference between the two limits acts as a hysteresis on the comparator output, and a fault counter
prevents false alerts as a result of system noise. The SMBus Alert response function is ignored in the
comparator mode.
9.4.4.2 Interrupt Mode (TM = 1)
In interrupt mode (TM = 1), the device starts to compare temperature readings with the high limit register value.
The ALERT pin becomes active when the temperature equals or exceeds THIGH for a consecutive number of
conversions as set by the Fault Queue bits [F1:F0]. The ALERT pin remains active until it is cleared by one
of three events: a read of any register, a successful SMBus Alert response, or a shutdown command. After
the ALERT pin is cleared, the device starts to compare temperature readings with the TLOW. The ALERT pin
becomes active again only when the temperature drops below TLOW for a consecutive number of conversions
as set by the Fault Queue bits. The ALERT pin remains active until cleared by any of the same three clearing
events. After the ALERT pin is cleared by one of the events, the cycle repeats and the device resumes to
compare the temperature to T HIGH. The interrupt mode history is cleared by a change in the TM=0 bit, setting the
device to SD mode, or resetting the device on the TMP1075 non-N orderables.
9.4.4.3 Polarity Mode (POL)
The polarity bit allows the user to adjust the polarity of the ALERT pin output. If the POL bit is set to 0 (default),
the ALERT pin becomes active low. When POL bit is set to 1, the ALERT pin becomes active high and the state
of the ALERT pin is inverted. Figure 9-10 shows the operation of the ALERT pin in various modes.
T HIGH
Measured
Temperature
T LOW
ALERT PIN
(ComparatorMode)
POL=0
ALERT PIN
(InterruptMode)
POL=0
ALERT PIN
(ComparatorMode)
POL=1
ALERT PIN
(InterruptMode)
POL=1
Rea d
Read
Read
Time
Figure 9-10. Output Transfer Function Diagrams
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9.5 Register Map
Table 9-5. TMP1075 Register Map
ADDRESS
RESET
ACRONYM
REGISTER NAME
SECTION
00h
R
0000h
TEMP
Temperature result register
Go
01h
R/W
00FFh
CFGR
Configuration register
Go
02h
R/W
4B00h
LLIM
Low limit register
Go
03h
R/W
5000h
HLIM
High limit register
Go
R
7500h
DIEID
Device ID register
Go
0Fh
(1)
TYPE
(1)
Device ID register not available on TMP1075N
Note
TMP1075 Configuration register supports single byte read and write for software compatibility with
xx75 standard temperature sensors.
9.5.1 Register Descriptions
Table 9-6. TMP1075 Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default value
9.5.1.1 Temperature Register (address = 00h) [default reset = 0000h]
The temperature register of the TMP1075 is a 12-bit, read-only register that stores the result of the most recent
conversion (see Figure 9-11). Data is represented in binary two's complement format. The first 12 bits are used
to indicate temperature, with all remaining bits equal to zero. The least significant byte does not have to be read
if that information is not needed. Following power-up or reset, the temperature register value is 0°C until the first
conversion is complete.
Figure 9-11. Temperature Register
15
14
13
12
11
10
9
8
T11
T10
T9
T8
T7
T6
T5
T4
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
7
6
5
4
3
2
1
0
T3
T2
T1
T0
0
0
0
0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
Table 9-7. Temperature Register Field Description
22
BIT
FIELD
TYPE
RESET
DESCRIPTION
15:4
T[11:0]
R
000h
12-bit, read-only register that stores the most recent
temperature conversion results.
3:0
—
R
0h
Not used
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9.5.1.2 Configuration Register (address = 01h) [default reset = 00FFh (60A0h TMP1075N)]
The configuration register is an 16-bit read/write register used to store bits that control the operational modes
of the temperature sensor. Read and write operations are performed MSB first. Figure 9-12 shows the format of
the configuration register for the TMP1075, followed by a breakdown of the register bits. The power-up or reset
value of the configuration register are all bits equal to 00FFh (TMP1075N: 60A0h). Only single byte writes and
reads must be used when pointing to the configuration register for proper operation on the TMP1075N orderable.
Figure 9-12. Configuration Register: TMP1075
15
14
13
12
11
10
9
8
OS
R1
R0
F1
F0
POL
TM
SD
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
15
14
13
12
11
10
9
8
OS
R1
R0
F1
F0
POL
TM
SD
R/W-0
R-1
R-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
Figure 9-13. Configuration Register: TMP1075N
1
0
x
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 9-8. Configuration Register Field Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
15
OS
R/W
0
One-shot conversion mode. Writing 1, starts a single
temperature conversion. Read returns 0.
14:13
R[1:0]
R/W
R (TMP1075N)
0
11 (TMP1075N)
Conversion rate setting when device is in continuous
conversion mode
00: 27.5 ms conversion rate
01: 55 ms conversion rate
10: 110 ms conversion rate
11: 220 ms conversion rate (35 ms TMP1075N)
12:11
F[1:0]
R/W
0
Consecutive fault measurements to trigger the alert
function
00: 1 fault
01: 2 faults
10: 3 faults (4 faults TMP1075N)
11: 4 faults (6 faults TMP1075N)
10
POL
R/W
0
Polarity of the output pin
0: Active low ALERT pin
1: Active high ALERT pin
9
TM
R/W
0
Selects the function of the ALERT pin
0: ALERT pin functions in comparator mode
1: ALERT pin functions in interrupt mode
8
SD
R/W
0
Sets the device in shutdown mode to conserve power
0: Device is in continuous conversion
1: Device is in shutdown mode
7:0
—
R/W
FFh
A0h (TMP1075N)
Not used
Reserved on TMP1075N package
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Note
The configuration register supports single-byte read and write over I2C bus to ensure software
compatibility with other xx75 standard temperature sensors like TMP75 and LM75. When a single
byte write is performed, the data byte on the I2C bus updates the register bits 15-8. Similarly when a
single byte read is performed, the data bits 15-8 is transferred over the I2C bus.
9.5.1.3 Low Limit Register (address = 02h) [default reset = 4B00h]
The register is configured as a 12-bit, read/write register and data is represented in two's complement format.
Figure 9-14 shows the layout for TLOW is the same as the temperature register. The default reset value is 4B00h
and corresponds to 75°C.
Figure 9-14. Low Limit Register
15
14
13
12
11
10
9
8
L11
L10
L9
L8
L7
L6
L5
L4
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-1
7
6
5
4
3
2
1
0
L3
L2
L1
L0
0
0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 9-9. Low Limit Register Field Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
15:4
L[11:0]
R/W
4B0h
12-bit, read-write register that stores the low limit for comparison
with temperature results.
3:0
—
R/W
0h
Not used
9.5.1.4 High Limit Register (address = 03h) [default reset = 5000h]
The register is configured as a 12-bit, read/write register and data is represented in two's complement format.
Figure 9-15 show the layout for THIGH is the same as the temperature register. The default reset value is 5000h
and corresponds to 80°C.
Figure 9-15. High Limit Register
15
14
13
12
11
10
9
8
H11
H10
H9
H8
H7
H6
H5
H4
R/W-0
R/W-1
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
H3
H2
H1
H0
0
0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 9-10. High Limit Register Field Description
24
BIT
FIELD
TYPE
RESET
DESCRIPTION
15:4
H[11:0]
R/W
500h
12-bit, read-write register that stores the high limit for
comparison with temperature results.
3:0
—
R/W
0h
Not used
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9.5.1.5 Device ID Register (address = 0Fh) [default reset = 7500]
Figure 9-16 shows this read-only register reads the device ID, and this register only available on the TMP1075
non-N orderables.
Figure 9-16. Device ID Register
15
14
13
12
11
10
9
8
DID15
DID14
DID13
DID12
DID11
DID10
DID9
DID8
R-0
R-1
R-1
R-1
R-0
R-1
R-0
R-1
7
6
5
4
3
2
1
0
DID7
DID6
DID5
DID4
DID3
DID2
DID1
DID0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
Table 9-11. Device ID Register Field Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
15:0
DID[15:0]
R/W
7500h
16-bit, read-only register that stores the die ID for the device.
The MSB reads the static value 75h to indicate the device name
for TMP1075
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The TMP1075 can measure the PCB temperature of the location where the user mounts the device. The
TMP1075 features two-wire SMBus and I2C interface compatibility, with the TMP1075 allowing up to 32
(TMP1075N: 4) devices on one bus. The TMP1075 requires a pullup resistor on the SDA pin, and if needed, on
the SCL and ALERT pins. A 0.01-μF bypass capacitor is also required (see Figure 10-1 ).
10.2 Typical Application
Supply Voltage
1.7 V to 5.5 V (TMP1075)
1.62 V to 3.6 V (TMP1075N)
Pullup Resistors
5 k
SDA
Supply Bypass
Capacitor
0.01 µF
V+
A0
Two-Wire
Host Controller
SCL
ALERT
GND
Figure 10-1. Typical Connections
10.2.1 Design Requirements
The recommended value for the pullup resistor is 5 kΩ. In some applications, the pullup resistor can be lower
or higher than 5 kΩ, but the maximum current through the pullup current is recommended to not exceed 3 mA
on the SCL and SDA pins. The SCL, SDA, A0, and A1, lines can be pulled up to a supply that is higher than
V+. The ALERT line can be pulled up to a supply higher than V+ on the TMP1075 non-N orderables. The A2 pin
can only be connected to GND or V+. When the ALERT pin is not used, it can either be connected GND or left
floating.
10.2.2 Detailed Design Procedure
Place the TMP1075 device in close proximity to the heat source that must be monitored with a proper layout
for good thermal coupling. This placement ensures that temperature changes are captured within the shortest
possible time interval. To maintain accuracy in applications that require air or surface temperature measurement,
take care to isolate the package and leads from ambient air temperature. A thermally-conductive adhesive is
helpful in achieving accurate surface temperature measurement.
26
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10.2.2.1 Migrating From the xx75 Device Family
The TMP1075 is designed specifically to be a pin-to-pin compatible replacement with xx75 family of devices.
This includes considerations for software compatibility. The two byte registers of the TMP1075 dynamically
support single byte read or write, meaning that replacing older xx75 standard temperature sensors should not
require any updates to existing code.
10.2.3 Application Curve
For application curves, see Table 10-1:
Table 10-1. Table of Graphs
FIGURE
TITLE
Figure 8-9
Sampling Period Change vs. Temperature (1.7 V to 5.5 V)
11 Power Supply Recommendations
The TMP1075 D, DGK, and DSG packages operate with a power supply in the range of 1.7 V to 5.5 V
(TMP1075N DRL package operates from 1.62 V to 3.6 V). A power-supply bypass capacitor is required for
precision and stability. Place this power-supply bypass capacitor as close to the supply and ground pins of
the device as possible. A typical value for this supply bypass capacitor is 0.01 μF. Applications with noisy or
high-impedance power supplies can require a bigger bypass capacitor to reject power-supply noise.
To minimize device self-heating and improve temperature precision, it is recommended to:
• Use the minimum supply voltage rail available
• Avoid communication over I2C bus during ADC conversion
• Use one-shot mode to minimize power consumption
• Set I2C signal levels VIL close to ground and VIH above 90% of V+
• Maintain the I2C bus signals positive edge less than 1 µs by using a pull-up resistor < 10 kΩ
• Connect the address pins A0 and A1 to either ground or V+
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12 Layout
12.1 Layout Guidelines
Place the power-supply bypass capacitor as close to the supply and ground pins as possible. The recommended
value of this bypass capacitor is 0.01 μF. Pullup the open-drain output pins SDA and ALERT through 5-kΩ pullup
resistors. The SCL requires a pullup resistor only if the microprocessor output is open drain.
12.2 Layout Example
Via to Power or Ground Plane
Via to Internal Layer
Supply Bypass
Capacitor
Pull-Up Resistors
Supply Voltage
SDA
V+
SCL
A0
ALERT
A1
GND
A2
Serial Bus Traces
Ground Plane for
Thermal Coupling
to Heat Source
Heat Source
Figure 12-1. Layout Example (D Package)
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Via to Power or Ground Plane
Via to Internal Layer
Pull-Up Resistors
Supply Bypass
Capacitor
Supply Voltage
SDA
V+
SCL
A0
ALERT
A1
GND
A2
Ground Plane for
Thermal Coupling
to Heat Source
Serial Bus Traces
Heat Source
Figure 12-2. Layout Example (DGK Package)
Via to Power or Ground Plane
Via to Internal Layer
Pull-Up Resistors
Supply Bypass
Capacitor
Supply Voltage
SDA
V+
SCL
A0
ALERT
A1
GND
A2
Ground Plane for
Thermal Coupling
to Heat Source
Serial Bus Traces
Heat Source
Figure 12-3. Layout Example (DSG Package)
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Via to Power or Ground Plane
Via to Internal Layer
Pull-Up Resistors
SCL
SDA
GND
V+
Supply Voltage
ALERT
ADD0
Supply Bypass
Capacitor
Ground Plane for
Thermal Coupling
to Heat Source
Serial Bus Traces
Heat Source
Figure 12-4. Layout Example (DRL Package)
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13 Device and Documentation Support
13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TMP1075DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG | SN
Level-2-260C-1 YEAR
-55 to 125
1075
Samples
TMP1075DGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG | SN
Level-2-260C-1 YEAR
-55 to 125
1075
Samples
TMP1075DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
1075
Samples
TMP1075DSGR
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
1AE
Samples
TMP1075DSGT
ACTIVE
WSON
DSG
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
1AE
Samples
TMP1075NDRLR
ACTIVE
SOT-5X3
DRL
6
4000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
N75
Samples
TMP1075NDRLT
ACTIVE
SOT-5X3
DRL
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
N75
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of