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TMP275
ZHCSA58F – JUNE 2006 – REVISED MAY 2018
TMP275 具有 I2C 和 SMBus 接口的 ±0.5°C 温度传感器（采用行业标准
LM75 尺寸和引脚）
1 特性
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3 说明
高精度：
– −20°C 至 100°C 范围内为 ±0.5°C（最大值）
– −40°C 至 125°C 范围内为 ±1°C（最大值）
低静态电流：
– 50μA（典型值）
– 0.1μA（待机状态）
分辨率：9 至 12 位，用户可选
数字输出： SMBus™、两线制和 I2C 接口兼容性
8 个 I2C/系统管理总线 (SMBus) 地址
宽电源电压范围：2.7V 至 5.5V
小型 VSSOP-8 和 SOIC-8 封装
无需指定上电序列，可在 V+ 之前使能双线制总线
上拉
2 应用
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电源温度监控
计算机外设过热保护
电池管理
办公机器
服务器
恒温器控制
环境监测和供热通风与空气调节 (HVAC)
机电器件温度
数据记录器
简化电路原理图
TMP275 器件 特有 系统管理总线 (SMBus) 和两线制
接口兼容性，并且可在同一总线上，借助 SMBus 过热
报警功能支持多达 8 个器件。厂家校准的温度精度和
抗扰数字接口使得 TMP275 成为其他传感器和电子元
器件温度补偿的首选解决方案，而且无需针对分布式温
度感测进行额外的系统级校准或复杂的电路板布局布
线。
器件信息(1)
器件型号
封装
TMP275
SDA
1
0.01 µF
SCL
2
3
4
SDA
SCL
TMP275
V+
A0
3.00mm × 3.00mm
ALERT
Diode
Temp.
Sensor
Control
Logic
2
8
7
VSSOP (8)
Temperature
5k
1
4.90mm × 3.91mm
内部框图
Supply Bypass
Capacitor
Two-Wire
Host Controller
封装尺寸（标称值）
SOIC (8)
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
Supply Voltage
2.7V to 5.5V
Pullup Resistors
TMP275是一款具有 12 位模数转换器 (ADC) 的
±0.5°C 精密集成数字温度传感器，可在低至 2.7V 的
电源电压下运行，并且可与德州仪器 (TI) 的 LM75、
TMP75、TMP75B 和 TMP175 器件实现引脚和寄存器
兼容。此器件采用 SOIC-8 和 VSSOP-8 两种封装，不
需要外部组件便可测温。TMP275 能够以最高
0.0625°C（12 位），最低 0.5°C（9 位）的分辨率读
取温度，从而允许用户编程更高的分辨率或更短的转换
时间来最大限度地提升效率。器件的额定工作温度范围
为 –40°C 至 125°C。
3
8
7
ΔΣ
A/D
Converter
V+
A0
Serial
Interface
6
A1
6
ALERT
A1
GND
A2
5
GND
4
OSC
Config.
and Temp.
Register
5
A2
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS363
TMP275
ZHCSA58F – JUNE 2006 – REVISED MAY 2018
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes........................................ 14
7.5 Programming .......................................................... 15
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Applications ................................................ 19
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
11 器件和文档支持 ..................................................... 24
11.1
11.2
11.3
11.4
11.5
文档支持................................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
术语表 ...................................................................
24
24
24
24
24
12 机械、封装和可订购信息 ....................................... 24
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision E (November 2015) to Revision F
Page
•
Added repeatability parameter to the Electrical Characteristics table .................................................................................... 5
•
Added long-term drift parameter to the Electrical Characteristics table ................................................................................. 5
Changes from Revision D (August 2007) to Revision E
Page
•
已添加 处理额定值表，特性 说明部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文档
支持部分以及机械、封装和可订购信息部分 .......................................................................................................................... 1
•
Changed the Timing Requirements table with new I2C data. Updated affected values throughout the data sheet .............. 6
2
Copyright © 2006–2018, Texas Instruments Incorporated
TMP275
www.ti.com.cn
ZHCSA58F – JUNE 2006 – REVISED MAY 2018
5 Pin Configuration and Functions
D and DGK Packages
8-Pin SOIC and 8-Pin VSSOP
Top View
SDA
1
8
V+
SCL
2
7
A0
ALERT
3
6
A1
GND
4
5
A2
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
Serail data. Open-drain output; requires a pullup resistor.
1
SDA
I/O
2
SCL
I
Serial clock. Open-drain output; requires a pullpup resistor.
3
ALERT
O
Overtemperature alert. Open-drain output; requires a pullup resistor.
4
GND
—
Ground
5
A2
I
Address select. Connect to GND or V+.
6
A1
I
Address select. Connect to GND or V+.
7
A0
I
Address select. Connect to GND or V+.
8
V+
I
Supply voltage, 2.7 to 5.5 V
Copyright © 2006–2018, Texas Instruments Incorporated
3
TMP275
ZHCSA58F – JUNE 2006 – REVISED MAY 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
Power supply, V+
Input voltage
(2)
–0.5
Input current
Operating temperature
–55
Junction temperature, TJ max,
Storage temperature, Tstg
(1)
(2)
–60
MAX
UNIT
7
V
7
V
10
mA
127
°C
150
°C
130
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
V(ESD)
(1)
(2)
UNIT
±4000
Electrostatic
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
discharge
Machine Model (MM)
±1000
V
±300
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM MAX
Supply voltage
2.7
5.5
UNIT
V
Operating free-air temperature, TA
–40
125
°C
6.4 Thermal Information
TMP275
THERMAL METRIC
(1)
D (SOIC) AND DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
120
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
66.7
°C/W
RθJB
Junction-to-board thermal resistance
60.4
°C/W
ψJT
Junction-to-top characterization parameter
17.8
°C/W
ψJB
Junction-to-board characterization parameter
59.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2006–2018, Texas Instruments Incorporated
TMP275
www.ti.com.cn
ZHCSA58F – JUNE 2006 – REVISED MAY 2018
6.5 Electrical Characteristics
at TA = −40°C to +125°C, and V+ = 2.7 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
125
°C
–20°C to 100°C, V+ = 3.3 V
±0.0625
±0.5
°C
0°C to 100°C, V+ = 3 V to 3.6 V
±0.0625
±0.75
°C
–40°C to 125°C, V+ = 3 V to 3.6 V
±0.0625
±1
°C
25°C to 100°C, V+ = 3.3 V to 5.5 V
0.2
±1.5
°C
TEMPERATURE INPUT
Range
–40
Accuracy (Temperature Error)
Resolution (1)
Selectable
Repeatability (2)
Long-term drift
(4)
0.0625
°C
25°C, V+= 3.3 V (3)
±0.0625
°C
500 hours at 150°C
±0.0625
°C
DIGITAL INPUT/OUTPUT
Input Capacitance
3
Input logic level, HIGH, VIH
Input logic level, LOW, VIL
pF
0.7(V+)
6
−0.5
0.3(V+)
V
1
µA
Leakage Input Current, IIN
0 V ≤ VIN ≤ 6 V
Input Voltage Hysteresis
SCL and SDA pins
SDA Output logic level, LOW, VOL
IOL = 3 mA
0
0.15
0.4
ALERT Output logic level, HIGH, VOL
IOL = 4 mA
0
0.15
0.4
Resolution
Selectable
500
Coversion Time
mV
9 to 12
9-Bit
V
V
V
Bits
27.5
37.5
ms
10-Bit
55
75
ms
11-Bit
110
150
ms
12-Bit
220
300
ms
54
74
ms
Time-out time
25
POWER SUPPLY
Operating range
2.7
Serial bus inactive
Quiescent Current, IQ
Shutdown Current, ISD
50
5.5
V
85
µA
Serial bus active, SCL freq = 400 kHz
100
Serial bus active, SCL freq = 3.4 MHz
410
µA
Serial bus inactive
0.1
Serial bus active, SCL freq = 400 kHz
60
µA
Serial bus active, SCL freq = 3.4 MHz
380
µA
µA
3
µA
TEMPERATURE RANGE
Specified Range
–40
125
°C
Operating Range
–55
127
°C
(1)
(2)
(3)
(4)
Specified for 12-bit resolution.
Repeatability is the ability to reproduce a reading when the measured temperature is applied consecutively, under the same conditions.
One-shot mode setup, 1 sample per minute for 24 hours.
Long-term drift is determined using accelerated operational life testing at a junction temperature of 150°C.
Copyright © 2006–2018, Texas Instruments Incorporated
5
TMP275
ZHCSA58F – JUNE 2006 – REVISED MAY 2018
www.ti.com.cn
6.6 Timing Requirements
See the Timing Diagrams section for timing diagrams. (1)
FAST MODE
UNIT
MIN
MAX
MIN
MAX
0.001
0.4
0.001
2.38
ƒ(SCL)
SCL operating frequency
t(BUF)
Bus-free time between STOP and START
condition
t(HDSTA)
Hold time after repeated START condition.
After this period, the first clock is generated.
t(SUSTA)
Repeated start condition setup time
t(SUSTO)
STOP condition setup time
t(HDDAT)
Data hold time
t(SUDAT)
Data setup time
t(LOW)
SCL-clock low period
V+ , see Timing Diagrams
t(HIGH)
SCL-clock high period
See Timing Diagrams
tFD
Data fall time
See Timing Diagrams
300
150
ns
See Timing Diagrams
300
40
ns
tRC
Clock rise time
SCLK ≤ 100 kHz, See Timing
Diagrams
tFC
Clock fall time
See Timing Diagrams
(1)
6
V+
HIGH-SPEED
MODE
See Timing Diagrams
MHz
1300
160
ns
600
160
ns
600
160
ns
600
4
160
900
4
ns
120
ns
100
10
ns
1300
280
ns
600
60
ns
1000
300
ns
40
ns
Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not specified and not
production tested.
Copyright © 2006–2018, Texas Instruments Incorporated
TMP275
www.ti.com.cn
ZHCSA58F – JUNE 2006 – REVISED MAY 2018
6.7 Typical Characteristics
at TA = 25°C and V+ = 5 V (unless otherwise noted)
85
1.0
0.9
75
0.8
0.7
0.6
V+ = 5 V
ISD (μA)
IQ (μA)
65
55
0.5
0.4
0.3
45
0.2
V+ = 2..7V
0.1
35
0.0
Serial Bus Inactive
−0.1
25
−55
−35
−15
5
25
45
65
85
105
125 130
−55
−35
−15
5
25
Temperature (°C)
45
65
85
105 125 130
Te mperature (°C)
Figure 1. Quiescent Current vs Temperature
Figure 2. Shutdown Current vs Temperature
0.500
300
250
200
Tempe rature Error (°C)
Conversion Time (ms)
0.375
V+ = 5 V
V+ = 2..7 V
150
0.250
0.125
0
−0.125
−0.250
−0.375
12-bit resolution
−0.500
100
−55
−35
−15
5
25
45
65
85
105
−55
125 130
−35
−15
5
25
45
65
85
105
125 130
Temperature (° C)
Te mperature (°C)
Figure 4. Temperature Error vs Temperature
Figure 3. Conversion Time vs Temperature
500
Hs MODE
FAST MODE
450
400
Population
IQ (μA)
350
300
250
200
125°C
150
25°C
100
50
Figure 5. Quiescent Current with Bus Activity
vs Temperature
Copyright © 2006–2018, Texas Instruments Incorporated
0.50
0.40
0.30
0.20
0.10
0.00
10M
−0.10
1M
−0.20
100k
Frequency (Hz)
−0.30
10k
−0.40
1k
−0.50
−55°C
0
Temperature Error (° C)
Figure 6. Temperature Error at 25°C
7
TMP275
ZHCSA58F – JUNE 2006 – REVISED MAY 2018
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TMP275 is a digital temperature sensor that is optimal for thermal management and thermal protection
applications. The TMP275 is Two-Wire, SMBus, and I2C interface-compatible, and is specified over a
temperature range of −40°C to 125°C. The temperature sensor in the TMP275 is the chip itself. Thermal paths
run through the package leads as well as the plastic package. The package leads provide the primary thermal
path because of the lower thermal resistance of the metal. See Functional Block Diagram for the internal block
diagram of TMP275 device.
7.2 Functional Block Diagram
Temperature
SDA
SCL
ALERT
GND
1
Diode
Temp.
Sensor
Control
Logic
2
3
4
8
7
ΔΣ
A/D
Converter
OSC
V+
A0
Serial
Interface
6
Config.
and Temp.
Register
5
A1
A2
7.3 Feature Description
7.3.1 Digital Temperature Output
The temperature register of the TMP275 is a 12-bit, read-only register that stores the output of the most recent
conversion. Two bytes must be read to obtain data, and are described in Figure 13 and Figure 14. Note that byte
1 is the most significant byte, followed by byte 2, the least significant byte. The first 12 bits are used to indicate
temperature, with all remaining bits equal to zero. The least significant byte does not have to be read if that
information is not needed. Data format for temperature is summarized in Table 1. Following power up or reset,
the Temperature Register reads 0°C until the first conversion is complete. The user can obtain 9, 10, 11, or 12
bits of resolution by addressing the Configuration Register and setting the resolution bits accordingly. For 9-, 10-,
or 11-bit resolution, the most significant bits in the Temperature Register are used with the unused LSBs set to
zero
Table 1. Temperature Data Format
8
TEMPERATURE
(°C)
DIGITAL OUTPUT
(BINARY)
HEX
128
0111 1111 1111
7FF
127.9375
0111 1111 1111
7FF
100
0110 0100 0000
640
80
0101 0000 0000
500
75
0100 1011 0000
4B0
50
0011 0010 0000
320
25
0001 1001 0000
190
0.25
0000 0000 0100
004
0
0000 0000 0000
000
–0.25
1111 1111 1100
FFC
–25
1110 0111 0000
E70
–55
1100 1001 0000
C90
Copyright © 2006–2018, Texas Instruments Incorporated
TMP275
www.ti.com.cn
ZHCSA58F – JUNE 2006 – REVISED MAY 2018
7.3.2 Serial Interface
The TMP275 operates only as slave devices on the SMBus, Two-Wire, and I2C interface-compatible bus.
Connections to the bus are made through the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature
integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise.
The TMP275 supports the transmission protocol for fast (up to 400 kHz) and high-speed (up to 2.38 MHz)
modes. All data bytes are transmitted MSB first.
7.3.3 Bus Overview
The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The
bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions.
To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a
HIGH to LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit
indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed
responds to the master by generating an Acknowledge and pulling SDA LOW.
Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data
transfer SDA must remain stable while SCL is HIGH, as any change in SDA while SCL is HIGH will be
interpreted as a control signal.
Once all data has been transferred, the master generates a STOP condition indicated by pulling SDA from LOW
to HIGH, while SCL is HIGH.
7.3.4 Serial Bus Address
To communicate with the TMP275, the master must first address slave devices through a slave address byte.
The slave address byte consists of 7 address bits, and a direction bit indicating the intent of executing a read or
write operation.
The TMP275 features three address pins, allowing up to eight devices to be connected per bus. Pin logic levels
are described in Table 2. The address pins of the TMP275 are read after reset, at start of communication, or in
response to a Two-Wire address acquire request. Following reading the state of the pins the address is latched
to minimize power dissipation associated with detection.
Table 2. Address Pins and Slave Addresses for the TMP275
A2
A1
A0
SLAVE ADDRESS
0
0
0
1001000
0
0
1
1001001
0
1
0
1001010
0
1
1
1001011
1
0
0
1001100
1
0
1
1001101
1
1
0
1001110
1
1
1
1001111
7.3.4.1 Writing and Reading to the TMP275
Accessing a particular register on the TMP275 is accomplished by writing the appropriate value to the Pointer
Register. The value for the Pointer Register is the first byte transferred after the slave address byte with the R/W
bit LOW. Every write operation to the TMP275 requires a value for the Pointer Register (see Figure 8).
Copyright © 2006–2018, Texas Instruments Incorporated
9
TMP275
ZHCSA58F – JUNE 2006 – REVISED MAY 2018
www.ti.com.cn
When reading from the TMP275, the last value stored in the Pointer Register by a write operation is used to
determine which register is read by a read operation. To change the register pointer for a read operation, a new
value must be written to the Pointer Register. This is accomplished by issuing a slave address byte with the R/W
bit LOW, followed by the Pointer Register Byte. No additional data is required. The master can then generate a
START condition and send the slave address byte with the R/W bit HIGH to initiate the read command. See
Figure 9 for details of this sequence. If repeated reads from the same register are desired, it is not necessary to
continually send the Pointer Register bytes, as the TMP275 remembers the Pointer Register value until it is
changed by the next write operation.
Note that register bytes are sent most-significant byte first, followed by the least significant byte.
7.3.4.2 Slave Mode Operations
The TMP275 can operate as a slave receiver or slave transmitter.
7.3.4.2.1 Slave Receiver Mode
The first byte transmitted by the master is the slave address, with the R/W bit LOW. The TMP275 then
acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer Register. The
TMP275 then acknowledges reception of the Pointer Register byte. The next byte or bytes are written to the
register addressed by the Pointer Register. The TMP275 acknowledges reception of each data byte. The master
may terminate data transfer by generating a START or STOP condition.
7.3.4.2.2 Slave Transmitter Mode
The first byte is transmitted by the master and is the slave address, with the R/W bit HIGH. The slave
acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most
significant byte of the register indicated by the Pointer Register. The master acknowledges reception of the data
byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of
the data byte. The master may terminate data transfer by generating a Not-Acknowledge on reception of any
data byte, or generating a START or STOP condition.
7.3.4.3 SMBus Alert Function
The TMP275 supports the SMBus Alert function. When the TMP275 is operating in Interrupt Mode (TM = 1), the
ALERT pin of the TMP275 may be connected as an SMBus Alert signal. When a master senses that an ALERT
condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If
the ALERT pin of the TMP275 is active, the device acknowledges the SMBus Alert command and responds by
returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates if the
temperature exceeding THIGH or falling below TLOW caused the ALERT condition. This bit will be HIGH if the
temperature is greater than or equal to THIGH. This bit will be LOW if the temperature is less than TLOW. Refer to
Figure 10 for details of this sequence.
If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion
of the SMBus Alert command determines which device clears its ALERT status. If the TMP275 wins the
arbitration, its ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP275 loses
the arbitration, its ALERT pin remains active.
7.3.4.4 General Call
The TMP275 responds to a Two-Wire General Call address (0000000) if the eighth bit is 0. The device
acknowledges the General Call address and responds to commands in the second byte. If the second byte is
00000100, the TMP275 latches the status of their address pins, but will not reset. If the second byte is
00000110, the TMP275 latches the status of their address pins and reset their internal registers to their power-up
values.
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7.3.4.5 High-Speed Mode
For the Two-Wire bus to operate at frequencies above 400 kHz, the master device must issue an Hs-mode
master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation.
The TMP1275 device will not acknowledge this byte, but will switch their input filters on SDA and SCL and their
output filters on SDA to operate in Hs-mode, allowing transfers at up to 2.38 MHz. After the Hs-mode master
code has been issued, the master will transmit a Two-Wire slave address to initiate a data transfer operation.
The bus will continue to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP
condition, the TMP275 switches the input and output filter back to fast-mode operation.
7.3.4.6 Time-Out Function
The TMP275 resets the serial interface if either SCL or SDA is held LOW for 54 ms (typical) between a START
and STOP condition. The TMP275 releases the bus if it is pulled LOW and waits for a START condition. To
avoid activating the time-out function, it is necessary to maintain a communication speed of at least 1 kHz for
SCL operating frequency.
7.3.5 Timing Diagrams
The TMP275 is Two-Wire, SMBUs, and I2C interface-compatible. Figure 7 to Figure 10 describe the various
operations on the TMP275. Bus definitions are given below. Parameters for Figure 7 are defined in Timing
Requirements.
Bus Idle: Both SDA and SCL lines remain HIGH.
Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH,
defines a START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH
defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and
is determined by the master device. The receiver acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device
that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA
line is stable LOW during the HIGH period of the Acknowledge clock pulse. Setup and hold times must be taken
into account. On a master receive, the termination of the data transfer can be signaled by the master generating
a Not-Acknowledge on the last byte that has been transmitted by the slave.
7.3.6 Two-Wire Timing Diagrams
t(LOW)
tF
tR
t(HDSTA)
SCL
t(HDSTA)
t(HIGH)
t(HDDAT)
t(SUSTO)
t(SUSTA)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
Figure 7. Two-Wire Timing Diagram
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1
9
1
9
…
SCL
SDA
1
0
0
1
A2
A1
A0
R/W
Start By
Master
0
0
0
0
0
0
P1
ACK By
TMP275
…
P0
ACK By
TMP275
Frame 2 Pointer Register Byte
Frame 1Two–Wire Slave Address Byte
1
9
1
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
ACK By
TMP275
Frame 3 Data Byte 1
D0
ACK By
TMP275
Stop By
Master
Frame 4 Data Byte 2
Figure 8. Two-Wire Timing Diagram for TMP275 Write Word Format
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1
9
1
9
…
SCL
SDA
1
0
0
1
0
0
0
R/W
Start By
Master
0
0
0
0
0
0
P1
…
P0
ACK By
TMP275
ACK By
TMP275
Frame 2 Pointer Register Byte
Frame 1 Two–Wire Slave Address Byte
1
9
1
9
…
SCL
(Continued)
SDA
(Continued)
1
0
0
0
1
0
0
D7
R/W
Start By
Master
D6
D5
D4
D3
D2
ACK By
TMP275
…
D0
From
TMP275
ACK By
Master
Frame 4 Data Byte 1 Read Register
Frame 3 Two–Wire Slave Address Byte
1
D1
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
From
TMP275
ACK By
Master
Stop By
Master
Frame 5 Data Byte 2 Read Register
NOTE: Address Pins A0, A1, A2 = 0
Figure 9. Two-Wire Timing Diagram for Read Word Format
ALERT
1
9
1
9
SCL
SDA
0
0
0
1
1
Start By
Master
0
0
R/W
1
0
0
1
0
ACK By
TMP275
0
0
S ta t u s
From
TMP275
NACK By
Master
Stop By
Master
Frame 1 SMBus ALERT Response Address Byte
NOTE: Address Pins A0, A1, A2 =0
Figure 10. Timing Diagram for SMBus ALERT
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7.4 Device Functional Modes
7.4.1 Shutdown Mode (SD)
The Shutdown Mode of the TMP275 allows the user to save maximum power by shutting down all device
circuitry other than the serial interface, which reduces current consumption to typically less than 0.1 μA.
Shutdown Mode is enabled when the SD bit is 1; the device will shut down once the current conversion is
completed. When SD is equal to 0, the device maintains a continuous conversion state.
7.4.2 Thermostat Mode (TM)
The Thermostat Mode bit of the TMP275 indicates to the device whether to operate in Comparator Mode (TM =
0) or Interrupt Mode (TM = 1). For more information on comparator and interrupt modes, see the High and Low
Limit Registers section.
7.4.2.1 Comparator Mode (TM = 0)
In Comparator mode (TM = 0), the ALERT pin is activated when the temperature equals or exceeds the value in
the T(HIGH) register and it remains active until the temperature falls below the value in the T(LOW) register. For
more information on the comparator mode, see the High and Low Limit Registers section.
7.4.2.2 Interrupt Mode (TM = 1)
In Interrupt mode (TM = 1), the ALERT pin is activated when the temperature exceeds T(HIGH) or goes below
T(LOW) registers. The ALERT pin is cleared when the host controller reads the temperature register. For more
information on the interrupt mode, see the High and Low Limit Registers section.
7.4.3 One-Shot (OS)
The TMP275 features a One-Shot Temperature Measurement Mode. When the device is in Shutdown Mode,
writing a ‘1’ to the OS bit starts a single temperature conversion. The device returns to the shutdown state at the
completion of the single conversion. This mode is useful for reducing power consumption in the TMP275 when
continuous temperature monitoring is not required. When the configuration register is read, the OS always reads
zero.
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7.5 Programming
7.5.1 Pointer Register
Figure 11 shows the internal register structure of the TMP275. The 8-bit Pointer Register of the devices is used
to address a given data register. The Pointer Register uses the two LSBs to identify which of the data registers
should respond to a read or write command. Figure 12 identifies the bits of the Pointer Register byte. Table 3
describes the pointer address of the registers available in the TMP275. Power-up reset value of P1/P0 is 00.
Pointer
Register
Temperature
Register
SCL
Configuration
Register
I/O
Control
Interface
TLOW
Register
SDA
THIGH
Register
Figure 11. Internal Register Structure of the TMP275
7.5.1.1 Pointer Register Byte (offset = N/A) [reset = 00h]
Figure 12. Pointer Register Byte
P7
0
P6
0
P5
0
P4
0
P3
0
P2
0
P1
P0
Register Bits
7.5.1.2 Pointer Addresses of the TMP275
Table 3. Pointer Addresses of the TMP275 Field Description
P1
P0
TYPE
REGISTER
0
0
R only, default
Temperature Register
0
1
R/W
Configuration Register
1
0
R/W
TLOW Register
1
1
R/W
THIGH Register
7.5.2 Temperature Register
The Temperature Register of the TMP275 is a 12-bit, read-only register that stores the output of the most recent
conversion. Two bytes must be read to obtain data, and are described in Figure 13 and Figure 14. Note that byte
1 is the most significant byte, followed by byte 2, the least significant byte. The first 12 bits are used to indicate
temperature, with all remaining bits equal to zero. The least significant byte does not have to be read if that
information is not needed. Data format for temperature is summarized in Table 1. Following power up or reset,
the Temperature Register reads 0°C until the first conversion is complete.
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Figure 13. Byte 1 of Temperature Register
D7
T11
D6
T10
D5
T9
D4
T8
D3
T7
D2
T6
D1
T5
D0
T4
D1
0
D0
0
Figure 14. Byte 2 of Temperature Register
D7
T3
D6
T2
D5
T1
D4
T0
D3
0
D2
0
7.5.3 Configuration Register
The Configuration Register is an 8-bit read/write register used to store bits that control the operational modes of
the temperature sensor. Read/write operations are performed MSB first. The format of the Configuration Register
for the TMP275 is shown in Table 4, followed by a breakdown of the register bits. The power-up/reset value of
the Configuration Register is all bits equal to 0.
Table 4. Configuration Register Format
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
1
OS
R1
R0
F1
F0
POL
TM
SD
7.5.4 Shutdown Mode (SD)
The Shutdown Mode of the TMP275 allows the user to save maximum power by shutting down all device
circuitry other than the serial interface, which reduces current consumption to typically less than 0.1 μA.
Shutdown Mode is enabled when the SD bit is 1; the device shuts down once the current conversion is
completed. When SD is equal to 0, the device maintains a continuous conversion state.
7.5.5 Thermostat Mode (TM)
The Thermostat Mode bit of the TMP275 indicates to the device whether to operate in Comparator Mode (TM =
0) or Interrupt Mode (TM = 1). For more information on Comparator and Interrupt modes, see the High and Low
Limit Registers section.
7.5.6 Polarity (POL)
The Polarity Bit of the TMP275 allows the user to adjust the polarity of the ALERT pin output. If POL = 0, the
ALERT pin is active LOW, as shown in Figure 15. For POL = 1, the ALERT pin is active HIGH, and the state of
the ALERT pin is inverted.
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T HIG H
Measured
Temperature
TL O W
TMP275 ALER T PIN
(Comparator Mode)
POL =0
TMP275 ALER T PIN
(Interrupt Mode)
POL =0
TMP275 ALER T PIN
(Comparator Mode)
POL =1
TMP275 ALER T PIN
(Interrupt Mode)
POL =1
Read
Read
Read
Time
Figure 15. Output Transfer Function Diagrams
7.5.7 Fault Queue (F1/F0)
A fault condition is defined as when the measured temperature exceeds the user-defined limits set in the THIGH
and TLOW Registers. Additionally, the number of fault conditions required to generate an alert may be
programmed using the fault queue. The fault queue is provided to prevent a false alert as a result of
environmental noise. The fault queue requires consecutive fault measurements to trigger the alert function.
Table 5 defines the number of measured faults that may be programmed to trigger an alert condition in the
device. For THIGH and TLOW register format and byte order, see the section High and Low Limit Registers.
Table 5. Fault Settings
F1
F0
CONSECUTIVE FAULTS
0
0
1
0
1
2
1
0
4
1
1
6
7.5.8 Converter Resolution (R1/R0)
The converter resolution bits control the resolution of the internal analog-to-digital (A/D) converter. This control
allows the user to maximize efficiency by programming for higher resolution or faster conversion time. Table 6
identifies the Resolution Bits and the relationship between resolution and conversion time.
Table 6. Resolution of the TMP275
RESOLUTION
CONVERSION TIME
(typical)
0
9 Bits (0.5°C)
27.5ms
1
10 Bits (0.25°C)
55ms
0
11 Bits (0.125°C)
110ms
1
12 Bits (0.0625°C)
220ms
R1
R0
0
0
1
1
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7.5.9 One-Shot (OS)
The TMP275 features a One-Shot Temperature Measurement Mode. When the device is in Shutdown Mode,
writing a ‘1’ to the OS bit starts a single temperature conversion. The device returns to the shutdown state at the
completion of the single conversion. This mode is useful for reducing power consumption in the TMP275 when
continuous temperature monitoring is not required. When the configuration register is read, the OS always reads
zero.
7.5.10 High and Low Limit Registers
In Comparator Mode (TM = 0), the ALERT pin of the TMP275 becomes active when the temperature equals or
exceeds the value in THIGH and generates a consecutive number of faults according to fault bits F1 and F0. The
ALERT pin remains active until the temperature falls below the indicated TLOW value for the same number of
faults.
In Interrupt Mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds THIGH for a
consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register
occurs, or the device successfully responds to the SMBus Alert Response Address. The ALERT pin is also
cleared if the device is placed in Shutdown Mode. Once the ALERT pin is cleared, it only becomes active again
by the temperature falling below TLOW. When the temperature falls below TLOW, the ALERT pin becomes active
and remain active until cleared by a read operation of any register or a successful response to the SMBus Alert
Response Address. Once the ALERT pin is cleared, the above cycle repeats, with the ALERT pin becoming
active when the temperature equals or exceeds THIGH. The ALERT pin can also be cleared by resetting the
device with the General Call Reset command. This command also clears the state of the internal registers in the
device, returning the device to Comparator Mode (TM = 0).
Both operational modes are represented in Figure 15. Table 7, Table 8, Table 9, and Table 10 describe the
format for the THIGH and TLOW registers. Note that the most significant byte is sent first, followed by the least
significant byte. Power-up reset values for THIGH and TLOW are:
THIGH = 80°C and TLOW = 75°C
The format of the data for THIGH and TLOW is the same as for the Temperature Register.
Table 7. Byte 1 THIGH Register
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
1
H11
H10
H9
H8
H7
H6
H5
H4
Table 8. Byte 2 of THIGH Register
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
2
H3
H2
H1
H0
0
0
0
0
Table 9. Byte 1 TLOW Register
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
1
L11
L10
L9
L8
L7
L6
L5
L4
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
2
L3
L2
L1
L0
0
0
0
0
Table 10. Byte 2 of TLOW Register
All 12 bits for the Temperature, THIGH, and TLOW registers are used in the comparisons for the ALERT function for
all converter resolutions. The three LSBs in THIGH and TLOW can affect the ALERT output even if the converter is
configured for 9-bit resolution.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TMP275 is digital output temperature sensor with SMBus, Two-Wire, and I2C compatible interfaces. This
device features three address pins (A0, A1, A2) allowing up to eight devices to be connected per bus. The
TMP275 require no external components for operation except for pullup resistors on SCL, SDA, and ALERT,
although TI recommends a 0.1-μF bypass capacitor. The TMP275 measures the PCB temperature of the location
it is mounted. The sensing device of the device is the chip itself. Thermal paths run through the package leads
as well as the plastic package. The lower thermal resistance of metal causes the leads to provide the primary
thermal path.
8.2 Typical Applications
8.2.1 Typical Connections of the TMP275
Supply Voltage
2.7V to 5.5V
Supply Bypass
Capacitor
Pullup Resistors
0.01 µF
5k
1
Two-Wire
Host Controller
2
3
4
SDA
TMP275
V+
SCL
A0
ALERT
A1
GND
A2
8
7
6
5
Figure 16. Typical Connections of the TMP275 Schematic
8.2.1.1 Design Requirements
Figure 16 shows TMP275 typical connections. The TMP275 device requires pullup resistors on the SCL, SDA,
and ALERT pins. The recommended value for the pullup resistor is 5 kΩ. In some applications the pullup resistor
can be lower or higher than 5 kΩ but must not exceed 3 mA of current on SCL and SDA pins, must not exceed 4
mA on ALERT pin. If the resistors are missing, the SCL and SDA lines will always be low (nearly 0 V) and the
I2C bus will not work. TI recommends a 0.1-μF bypass capacitor, as shown in Figure 16. The SCL, SDA, and
ALERT lines can be pulled up to a supply that is equal to or higher than V+ through the pullup resistors.
The ALERT pin can be configured to respond to one of the two alert functions available, Comparator Mode and
Interrupt Mode. To configure one of eight different addresses on the bus, connect A0, A1, and A2 to either a
GND pin or V+ pin. In the circuit shown in Figure 16 the comparator mode is selected and the address pins (A0,
A1, A2) are connected to ground.
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Typical Applications (continued)
8.2.1.2 Detailed Design Procedure
The TMP275 device should be placed in close proximity to the heat source that must be monitored, with a proper
layout for good thermal coupling. This placement ensures that temperature changes are captured within the
shortest possible time interval. To maintain accuracy in applications that require air or surface temperature
measurement, take care to isolate the package and leads from ambient air temperature. A thermally conductive
adhesive is helpful in achieving accurate surface temperature measurement.
8.2.1.3 Application Curve
Temperature (qC)
Figure 17 shows the step response of the TMP275 device to a submersion in an oil bath of 100ºC from room
temperature (27ºC). The time-constant, or the time for the output to reach 63% of the input step, is 1.5 s. The
time-constant result depends on the printed-circuit board (PCB) that the TMP275 devices are mounted. For this
test, the TMP275 device was soldered to a two-layer PCB that measured 0.375 inches × 0.437 inches.
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
-1
1
3
5
7
9
11
Time (s)
13
15
17
19
Figure 17. Temperature Step Response
8.2.2 Connecting Multiple Devices on a Single Bus
The TMP275 features three address pins allowing up to eight devices to be connected per bus. When the
TMP275 is operating in Interrupt mode (TM = 1) , the ALERT pin of the TMP275 may be connected as an
SMBus Alert signal. Figure 18 shows eight TMP275 devices connected to a MCU (master) using one single bus.
Each device that exists as a slave on the SMBus has one unique seven bit address, see Table 2 for TMP275
address options. When a master senses that an ALERT condition is present on the ALERT line, the master
sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP275 is active, the device
acknowledges the SMBus Alert command and responds by returning its slave address on the SDA line. The
eighth bit (LSB) of the slave address byte indicates if the temperature exceeding THIGH or falling below TLOW
caused the ALERT condition. This bit will be HIGH if the temperature is greater than or equal to THIGH. This bit
will be LOW if the temperature is less than TLOW.
This application have eight devices connected to the bus. If multiple devices on the bus respond to the SMBus
Alert command, arbitration during the slave address portion of the SMBus Alert command determines which
device clears its ALERT status. If the TMP275 wins the arbitration, its ALERT pin becomes inactive at the
completion of the SMBus Alert command. If the TMP275 loses the arbitration, its ALERT pin remains active.
NOTE
Make sure you configure the device to operate in Interrupt Mode to enable the SMBus
feature.
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Typical Applications (continued)
Supply Voltage
2.7 V to 5.5 V
0.01 µF
5k
V+
SDA
SCL
ALERT
1 SDA TMP275
MCU
2 SCL
3 ALERT
1
4 GND
A0 7
6
A1
1 SDA TMP275
2 SCL
2
3 ALERT
A0 7
6
A1
1 SDA TMP275
2 SCL
3
3 ALERT
A0 7
6
A1
1 SDA TMP275
2 SCL
4
3 ALERT
A0 7
A2 5
4 GND
A2 5
4 GND
A2 5
4 GND
A2 5
V+
8
Slave Address
1001000
V+
8
Slave Address
1001001
V+
8
Slave Address
1001010
V+
A1
8
6
Slave Address
1001011
V+
SDA
SCL
ALERT
1 SDA TMP275
2 SCL
3 ALERT
5
4 GND
V+
8
A0 7
6
A1
A2 5
Slave Address
1001100
1 SDA TMP275
2 SCL
V+
8
3 ALERT 6
A0 7
6
A1
4 GND
A2 5
Slave Address
1001101
1 SDA TMP275
2 SCL
V+
8
3 ALERT 7
A0 7
6
A1
4 GND
A2 5
Slave Address
1001110
1 SDA TMP275
2 SCL
3 ALERT
8
4 GND
V+
8
A0 7
A1
6
A2 5
Slave Address
1001111
Figure 18. Connecting Multiple Devices on a Single Bus
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Typical Applications (continued)
8.2.3 Temperature Data Logger for Cold Chain Management Applications
Cold chain management includes all of the means used to ensure a constant temperature for a product that is
not heat stable from the time it is manufactured or farmed until the time it is used. This includes industries such
as food, retail, medical, and pharmaceutical. Figure 19 implements a cold chain monitoring system that
measures temperature, then logs the sensor data to nonvolatile (FRAM) memory in the MCU. Figure 19 uses a
Near Field Communication (NFC) interface for wireless communication and is powered from a CR2032 coin cell
battery with a focus on low power to maximize the battery lifetime.
The microcontroller communicates with all of the sensor devices through an I2C-compatible interface. The MCU
also communicates with the NFC transponder through this interface. An NFC enabled smartphone can be used
to send configuration to the application board. For a detailed design procedure and requirements of this
application, see Ultralow Power Multi-Sensor Data Logger with NFC Interface Reference Design (TIDU821).
Coin Cell Battery
(CR2032)
3.0 Volts
5k
NFC
Enabled
Smartphone
Dynamic NFC
Transponder
(RF430CL331H)
2
IC
MCU
(MSP430FR5969)
FRAM
5k
5k
1
DATA
2
CLOCK
3
4
SDA
TMP275
V+
SCL
A0
ALERT
A1
GND
A2
8
7
0.01 µF
6
5
Figure 19. Temperature Data Logger
9 Power Supply Recommendations
The TMP275 device operates with power supply in the range of 2.7 V to 5.5 V. A power-supply bypass capacitor
is required for stability. Place this capacitor as close as possible to the supply and ground pins of the device. A
typical value for this supply bypass capacitor is 0.01 μF. Applications with noisy or high impedance power
supplies may require additional decoupling capacitors to reject power-supply noise.
10 Layout
10.1 Layout Guidelines
Mount the TMP275 to a PCB as shown in Figure 20. For this example the A0, A1, and A2 address pins are
connected directly to ground. Connecting these pins to ground configures the device for slave address
1001000b.
• Bypass the VS pin to ground with a low-ESR ceramic bypass-capacitor. The typical recommended bypass
capacitance is a 0.1-μF ceramic capacitor with a X5R or X7R dielectric. The optimum placement is closest to
the VS and GND pins of the device. Take care in minimizing the loop area formed by the bypass-capacitor
connection, the VS pin, and the GND pin of the IC. Additional bypass capacitance can be added to
compensate for noisy or high-impedance power supplies.
• Pull up the open-drain output pins SDA , SCL and ALERT through 5-kΩ pullup resistors.
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10.2 Layout Example
Via to Power or Ground Plane
Via to Internal Layer
Pull-Up Resistors
Supply Bypass
Capacitor
Supply Voltage
SDA
VS
SCL
A0
ALERT
A1
GND
A2
Ground Plane for
Thermal Coupling
to Heat Source
Serial Bus Traces
Heat Source
Figure 20. TMP275 Layout Example
版权 © 2006–2018, Texas Instruments Incorporated
23
TMP275
ZHCSA58F – JUNE 2006 – REVISED MAY 2018
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
• 《具有 NFC 接口的超低功耗多传感器数据记录器参考设计》(TIDU821)
• 《了解 I2C 总线》(SLVA704)
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.3 商标
E2E is a trademark of Texas Instruments.
SMBus is a trademark of Intel Corporation.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
24
版权 © 2006–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMP275AID
ACTIVE
SOIC
D
8
75
TMP275AIDGKR
ACTIVE
VSSOP
DGK
8
2500
TMP275AIDGKRG4
ACTIVE
VSSOP
DGK
8
TMP275AIDGKT
ACTIVE
VSSOP
DGK
TMP275AIDGKTG4
ACTIVE
VSSOP
TMP275AIDR
ACTIVE
TMP275AIDRG4
ACTIVE
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TMP275
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
T275
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T275
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
T275
DGK
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
T275
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TMP275
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TMP275
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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