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TMP275-Q1
SBOS760B – NOVEMBER 2015 – REVISED APRIL 2017
TMP275-Q1 Automotive Grade ±0.75°C Temperature Sensor with I2C and SMBus Interface
in Industry-Standard LM75 Form Factor and Pinout
1 Features
3 Description
•
The TMP275-Q1 is a ±0.75°C, accurate integrated
digital temperature sensor with a 12-bit, analog-todigital converter (ADC) that can operate on a supply
voltage as low as 2.7 V and is pin- and registercompatible with the Texas Instruments' LM75,
TMP75, TMP75B, and TMP175 devices. The
TMP275-Q1 device is available in 8-pin SOIC and
VSSOP packages and requires no external
components to sense temperature. The device is
capable of reading temperatures with a maximum
resolution of 0.0625°C (12 bits) and as low as 0.5°C
(9 bits), thus allowing the user to maximize efficiency
by programming for higher resolution or faster
conversion time. The device is specified over the
temperature range of –40°C to +125°C.
1
•
•
•
•
•
•
•
•
AEC-Q100 Qualified with:
– Temperature Grade 1: –40°C to +125°C
Ambient Operation Temperature Range
– HBM ESD Classification Level 2
– CDM ESD Classification Level C6
High Accuracy:
– ±0.75°C (Maximum) from −10°C to +85°C
– ±1.5°C (Maximum) from −40°C to +125°C
Low Quiescent Current:
– 50 μA (Typical)
– 0.1 μA (Standby)
Resolution: 9 to 12 Bits, User-Selectable
Digital Output: SMBus™, Two-Wire, and I2C
Interface Compatibility
8 I2C, SMBus Addresses
Wide Supply Range: 2.7 V to 5.5 V
Small 8-Pin VSSOP and SOIC Packages
No Specified Power-Up Sequence Required, TwoWire Bus Pullups Can Be Enabled Before V+
2 Applications
•
•
•
•
•
•
•
•
•
The TMP275-Q1 device features SMBus and twowire interface compatibility and allows up to eight
devices on the same bus with the SMBus
overtemperature alert function. The factory-calibrated
temperature accuracy and the noise-immune digital
interface make the TMP275-Q1 the preferred solution
for temperature compensation of other sensors and
electronic components, without the need for
additional system-level calibration or elaborate board
layout for distributed temperature sensing.
Device Information(1)
Climate Controls
Infotainment Processor Management
Airflow Sensors
Battery Control Units
Engine Control Units
UREA Sensors
Water Pumps
HID Lamps
Airbag Control Units
PART NUMBER
TMP275-Q1
3.00 mm × 3.00 mm
Temperature
2.7-V to 5.5-V
Supply Voltage
1
SCL
Diode
Temp.
Sensor
8
7
ΔΣ
ADC
ALERT
Control
Logic
2
0.01-µF
Supply Bypass
Capacitor
1
VSSOP (8)
Internal Block Diagram
Simplified Schematic
Two-Wire
Host
Controller
BODY SIZE (NOM)
4.90 mm × 3.91 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
SDA
5-k
Pullup Resistors
PACKAGE
SOIC (8)
V+
A0
Serial
Interface
3
6
A1
8
SCL
V
+
A0
ALERT
A1
GND
A2
SDA
2
7
6
3
4
GND
4
OSC
Config.
and Temp.
Register
5
A2
5
TMP275-Q1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMP275-Q1
SBOS760B – NOVEMBER 2015 – REVISED APRIL 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 14
7.5 Programming .......................................................... 15
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Applications ................................................ 19
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Revision A (January 2016) to Revision B
Page
•
Changed temperature (maximum) in title, Features and Description from "±0.5°C" to "±0.75°C"; change temperature
range under "High Accuracy" row for ±0.75°C from "–20°C to 100°C" to "–10°C to 85°C" ................................................... 1
•
Changed first test condition temperature range in "Accuracy" row from "–20°C to 100°C" to "–10°C to 85°C"; change
MAX value in same row from "±0.5°C" to "±0.75°C" .............................................................................................................. 5
Changes from Original (November 2015) to Revision A
•
2
Page
Changed Thermal Information table specifications ................................................................................................................ 4
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SBOS760B – NOVEMBER 2015 – REVISED APRIL 2017
5 Pin Configuration and Functions
D, DGK Packages
8-Pin SOIC, VSSOP
Top View
SDA
1
8
V+
SCL
2
7
A0
ALERT
3
6
A1
GND
4
5
A2
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
SDA
I/O
Serial data. Open-drain output; requires a pullup resistor.
2
SCL
I
Serial clock. Open-drain output; requires a pullup resistor.
3
ALERT
O
Overtemperature alert. Open-drain output; requires a pullup resistor.
4
GND
—
Ground
5
A2
I
6
A1
I
7
A0
I
8
V+
I
Address select. Connect to GND or V+.
Supply voltage, 2.7 V to 5.5 V
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Power supply, V+
Input voltage
(2)
–0.5
Input current
Operating temperature
–55
Junction temperature, TJ max
Storage temperature, Tstg
(1)
(2)
–60
MAX
UNIT
7
V
7
V
10
mA
127
°C
150
°C
130
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input voltage rating applies to all TMP275-Q1 input voltages.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2500
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply voltage
2.7
5.5
V
Operating free-air temperature, TA
–40
125
°C
6.4 Thermal Information
TMP275-Q1
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
121.6
185
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
70.5
76.1
°C/W
RθJB
Junction-to-board thermal resistance
62
106.4
°C/W
ψJT
Junction-to-top characterization parameter
23
14.1
°C/W
ψJB
Junction-to-board characterization parameter
61.5
104.8
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS760B – NOVEMBER 2015 – REVISED APRIL 2017
6.5 Electrical Characteristics
at TA = –40°C to +125°C and V+ = 2.7 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
125
°C
–10°C to 85°C, V+ = 3.3 V
±0.125
±0.75
0°C to 100°C, V+ = 3 V to 3.6 V
±0.125
±1
–40°C to 125°C, V+ = 3 V to 3.6 V
±0.125
±1.5
±0.2
±2
TEMPERATURE INPUT
Range
–40
Accuracy (temperature error)
25°C to 100°C, V+ = 3.3 V to 5.5 V
Resolution (1)
Selectable
0.0625
°C
°C
DIGITAL INPUT/OUTPUT
Input capacitance
VIH
High-level input logic
VIL
Low-level input logic
IIN
Leakage input current
3
VOL
Low-level output logic
6
–0.5
0.3 (V+)
V
1
µA
0 V ≤ VIN ≤ 6 V
Input voltage hysteresis
pF
0.7 (V+)
SCL and SDA pins
500
mV
SDA
IOL = 3 mA
0
0.15
0.4
ALERT
IOL = 4 mA
0
0.15
0.4
Resolution
Selectable
9 to 12
9 bits
Conversion time
27.5
V
V
Bits
37.5
10 bits
55
75
11 bits
110
150
220
300
54
74
ms
5.5
V
12 bits
Time-out time
25
ms
POWER SUPPLY
Operating range
2.7
Serial bus inactive
IQ
ISD
Quiescent current
Shutdown current
50
Serial bus active, SCL frequency = 400 kHz
100
Serial bus active, SCL frequency = 3.4 MHz
410
Serial bus inactive
0.1
Serial bus active, SCL frequency = 400 kHz
60
Serial bus active, SCL frequency = 3.4 MHz
380
85
µA
3
µA
TEMPERATURE RANGE
(1)
Specified range
–40
125
°C
Operating range
–55
127
°C
Specified for 12-bit resolution.
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6.6 Timing Requirements
see the Timing Diagrams section for timing diagrams (1)
HIGH-SPEED
MODE
FAST MODE
V+
UNIT
MIN
MAX
MIN
MAX
0.001
0.4
0.001
2.38
ƒ(SCL)
SCL operating frequency
t(BUF)
Bus-free time between STOP and START
condition
t(HDSTA)
Hold time after repeated START condition.
After this period, the first clock is generated.
t(SUSTA)
repeated start condition setup time
t(SUSTO)
STOP condition setup time
t(HDDAT)
Data hold time
t(SUDAT)
Data setup time
t(LOW)
SCL-clock low period
V+ , see the Timing Diagrams section
t(HIGH)
SCL-clock high period
See the Timing Diagrams section
tFD
Data fall time
See the Timing Diagrams section
300
150
ns
See the Two-Wire Timing Diagrams section
300
40
ns
See the Timing Diagrams section
1300
160
ns
600
160
ns
600
160
ns
600
160
4
900
ns
120
ns
10
ns
1300
280
ns
600
60
ns
Clock rise time
SCLK ≤ 100 kHz, see the Timing Diagrams
section
1000
tFC
Clock fall time
See the Two-Wire Timing Diagrams section
300
6
4
100
tRC
(1)
MHz
ns
40
ns
Values are based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not specified and are not
production tested.
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6.7 Typical Characteristics
at TA = 25°C and V+ = 5 V (unless otherwise noted)
85
1
0.9
75
0.8
0.7
0.6
V+ = 5 V
ISD (μA)
IQ (μA)
65
55
0.5
0.4
0.3
45
0.2
V+ = 2..7V
0.1
35
0
−0.1
−55
25
−55
−35
−15
5
25
45
65
85
105
125 130
−35
−15
5
Temperature (°C)
25
45
65
85
105 125 130
Te mperature (°C)
Serial bus inactive
Figure 1. Quiescent Current vs Temperature
Figure 2. Shutdown Current vs Temperature
300
1
V+ = 5 V
250
200
0.6
Temperature Error (qC)
Conversion Time (ms)
0.8
V+ = 2..7 V
150
0.4
0.2
0
-0.2
-0.4
-0.6
100
-0.8
−55
−35
−15
5
25
45
65
85
105
125 130
-1
-40
Te mperature (°C)
-20
0
12-bit resolution
Figure 3. Conversion Time vs Temperature
80
100
120
tc_t
Figure 4. Temperature Error vs Temperature
10
500
Hs Mode
Fast Mode
450
9
400
8
350
7
Population
300
250
200
125°C
150
5
4
3
25°C
100
6
2
1
50
−55°C
Frequency (Hz)
Figure 5. Quiescent Current with Bus Activity
vs Temperature
0.5
10M
0.25
0
1M
0.1875
100k
0.125
10k
0.0625
1k
0
0
-0.5
IQ (μA)
20
40
60
Temperature (qC)
Figure 6. Temperature Error at 25°C
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tc_t
Temperature Error (qC)
7
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SBOS760B – NOVEMBER 2015 – REVISED APRIL 2017
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7 Detailed Description
7.1 Overview
The TMP275-Q1 is a digital temperature sensor that is optimal for thermal management and thermal protection
applications. The TMP275-Q1 is two-wire, SMBus, and I2C interface compatible, and is specified over the
temperature range of –40°C to +125°C. The temperature sensor in the TMP275-Q1 is the device itself. Thermal
paths run through the package leads as well as the plastic package. The package leads provide the primary
thermal path because of the lower thermal resistance of the metal; see the Functional Block Diagram section for
the internal block diagram of the TMP275-Q1 device.
7.2 Functional Block Diagram
Temperature
SDA
SCL
1
Diode
Temp.
Sensor
2
GND
8
6
OSC
V+
A0
Serial
Interface
3
4
8
7
ΔΣ
ADC
ALERT
Control
Logic
Config.
and Temp.
Register
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5
A1
A2
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7.3 Feature Description
7.3.1 Digital Temperature Output
The temperature register of the TMP275-Q1 is a 12-bit, read-only register that stores the output of the most
recent conversion. Two bytes must be read to obtain data, and are described in Table 5 and Table 6. Note that
byte 1 is the most significant byte and is followed by byte 2, the least significant byte. The first 12 bits are used to
indicate temperature, with all remaining bits equal to zero. The least significant byte does not have to be read if
that information is not needed. The data format for temperature is summarized in Table 1. Following power-up or
reset, the Temperature register reads 0°C until the first conversion is complete. The user can obtain 9, 10, 11, or
12 bits of resolution by addressing the Configuration register and setting the resolution bits accordingly. For 9-,
10-, or 11-bit resolution, the most significant bits (MSBs) in the Temperature register are used with the unused
least significant bits (LSBs) set to zero.
Table 1. Temperature Data Format
DIGITAL OUTPUT
TEMPERATURE
(°C)
BINARY
HEX
128
0111 1111 1111
7FF
127.9375
0111 1111 1111
7FF
100
0110 0100 0000
640
80
0101 0000 0000
500
75
0100 1011 0000
4B0
50
0011 0010 0000
320
25
0001 1001 0000
190
0.25
0000 0000 0100
004
0
0000 0000 0000
000
–0.25
1111 1111 1100
FFC
–25
1110 0111 0000
E70
–55
1100 1001 0000
C90
7.3.2 Serial Interface
The TMP275-Q1 operates only as a slave device on the SMBus, two-wire, and I2C interface-compatible bus.
Connections to the bus are made through the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature
integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise.
The TMP275-Q1 supports the transmission protocol for fast (up to 400 kHz) and high-speed (up to 2.38 MHz)
modes. All data bytes are transmitted most significant bit (MSB) first.
7.3.3 Bus Overview
The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The
bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions.
To address a specific device a START condition is initiated, indicated by pulling the data line (SDA) from a high
to a low logic level when SCL is high. All slaves on the bus shift in the slave address byte, with the last bit
indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed
responds to the master by generating an Acknowledge bit and pulling SDA low.
Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge bit. During data
transfer, SDA must remain stable when SCL is high because any change in SDA when SCL is high is interpreted
as a control signal.
When all data are transferred, the master generates a STOP condition indicated by pulling SDA from low to high
when SCL is high.
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7.3.4 Serial Bus Address
To communicate with the TMP275-Q1, the master must first address slave devices through a slave address byte.
The slave address byte consists of seven address bits and a direction bit indicating the intent of executing a read
or write operation.
The TMP275-Q1 features three address pins, allowing up to eight devices to be connected per bus. Pin logic
levels are described in Table 2. The address pins of the TMP275-Q1 are read after reset, at the start of
communication, or in response to a two-wire address acquire request. Following reading the state of the pins, the
address is latched to minimize power dissipation associated with detection.
Table 2. Address Pins and Slave Addresses for the TMP275-Q1
A2
A1
A0
SLAVE ADDRESS
0
0
0
1001000
0
0
1
1001001
0
1
0
1001010
0
1
1
1001011
1
0
0
1001100
1
0
1
1001101
1
1
0
1001110
1
1
1
1001111
7.3.4.1 Writing and Reading to the TMP275-Q1
Accessing a particular register on the TMP275-Q1 is accomplished by writing the appropriate value to the Pointer
register. The value for the Pointer register is the first byte transferred after the slave address byte with the R/W
bit low. Every write operation to the TMP275-Q1 requires a value for the Pointer register; see Figure 8.
When reading from the TMP275-Q1, the last value stored in the Pointer register by a write operation is used to
determine which register is read by a read operation. To change the register pointer for a read operation, a new
value must be written to the Pointer register. This action is accomplished by issuing a slave address byte with the
R/W bit low, followed by the Pointer register byte. No additional data are required. The master can then generate
a START condition and send the slave address byte with the R/W bit high to initiate the read command; see
Figure 9 for details of this sequence. If repeated reads from the same register are desired, the Pointer register
bytes do not have to be continually sent because the TMP275-Q1 remembers the Pointer register value until it is
changed by the next write operation.
Note that register bytes are sent most-significant byte first, followed by the least significant byte.
7.3.4.2 Slave Mode Operations
The TMP275-Q1 can operate as a slave receiver or slave transmitter.
7.3.4.2.1 Slave Receiver Mode
The first byte transmitted by the master is the slave address, with the R/W bit low. The TMP275-Q1 then
acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer register. The
TMP275-Q1 then acknowledges reception of the Pointer register byte. The next byte or bytes are written to the
register addressed by the Pointer register. The TMP275-Q1 acknowledges reception of each data byte. The
master can terminate data transfer by generating a START or STOP condition.
7.3.4.2.2 Slave Transmitter Mode
The first byte is transmitted by the master and is the slave address, with the R/W bit high. The slave
acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most
significant byte of the register indicated by the Pointer register. The master acknowledges reception of the data
byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of
the data byte. The master can terminate data transfer by generating a Not-Acknowledge bit on reception of any
data byte, or by generating a START or STOP condition.
10
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7.3.4.3 SMBus Alert Function
The TMP275-Q1 supports the SMBus alert function. When the TMP275-Q1 is operating in interrupt mode (TM =
1), the ALERT pin of the TMP275-Q1 can be connected as an SMBus alert signal. When a master senses that
an Alert condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the
bus. If the ALERT pin of the TMP275-Q1 is active, the device acknowledges the SMBus Alert command and
responds by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates
if the temperature exceeding THIGH or falling below TLOW caused the Alert condition. This bit is high if the
temperature is greater than or equal to THIGH. This bit is low if the temperature is less than TLOW; see Figure 10
for details of this sequence.
If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion
of the SMBus Alert command determines which device clears its Alert status. If the TMP275-Q1 wins the
arbitration, its ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP275-Q1
loses the arbitration, its ALERT pin remains active.
7.3.4.4 General Call
The TMP275-Q1 responds to a two-wire, general-call address (0000000) if the eighth bit is 0. The device
acknowledges the general-call address and responds to commands in the second byte. If the second byte is
00000100, the TMP275-Q1 latches the status of its address pins but does not reset. If the second byte is
00000110, the TMP275-Q1 latches the status of its address pins and resets its internal registers to their powerup values.
7.3.4.5 High-Speed Mode
For the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an Hs-mode master
code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The
TMP1275 device does not acknowledge this byte, but does switch its input filters on SDA and SCL and its output
filters on SDA to operate in Hs-mode, thus allowing transfers at up to 2.38 MHz. After the Hs-mode master code
is issued, the master transmits a two-wire slave address to initiate a data transfer operation. The bus continues
to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the
TMP275-Q1 switches the input and output filter back to fast-mode operation.
7.3.4.6 Time-Out Function
The TMP275-Q1 resets the serial interface if either SCL or SDA is held low for 54 ms (typical) between a START
and STOP condition. The TMP275-Q1 releases the bus if it is pulled low and waits for a START condition. To
avoid activating the time-out function, a communication speed of at least 1 kHz must be maintained for the SCL
operating frequency.
7.3.5 Timing Diagrams
The TMP275-Q1 is two-wire, SMBus, and I2C interface compatible. Figure 7 to Figure 10 describe the various
operations on the TMP275-Q1. The following list provides bus definitions. Parameters for Figure 7 are defined in
the Timing Requirements table.
Bus Idle: Both the SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the SDA line, from high to low when the SCL line is high defines a
START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a
STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and
is determined by the master device. The receiver acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device
that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA
line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into
account. On a master receive, the termination of the data transfer can be signaled by the master generating a
Not-Acknowledge bit on the last byte that is transmitted by the slave.
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7.3.5.1 Two-Wire Timing Diagrams
t(LOW)
tF
tR
t(HDSTA)
SCL
t(HDSTA)
t(HIGH)
t(SUSTO)
t(SUSTA)
t(HDDAT)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
Figure 7. Two-Wire Timing Diagram
1
9
1
9
…
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
R/W
Start By
Master
0
0
0
0
0
0
P1
…
P0
ACK By
Device
ACK By
Device
Frame 1 Two-Wire Slave Address Byte
Frame 2 Pointer Register Byte
1
9
1
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
ACK By
Device
Frame 3 Data Byte 1
D0
ACK By
Device
Stop By
Master
Frame 4 Data Byte 2
Figure 8. Two-Wire Timing Diagram for TMP275-Q1 Write Word Format
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1
9
1
9
…
SCL
1
SDA
0
0
1
0
0
0
R/W
0
Start By
Master
0
0
0
0
0
P1
…
P0
ACK By
Device
ACK By
Device
Frame 2 Pointer Register Byte
Frame 1 Two-Wire Slave Address Byte
1
9
1
9
…
SCL
(Continued)
SDA
(Continued)
1
0
0
0
1
0
0
D7
R/W
Start By
Master
D6
D5
D4
D3
D2
ACK By
Device
…
D0
From
Device
Frame 3 Two-Wire Slave Address Byte
1
D1
ACK By
Master
Frame 4 Data Byte 1Read Register
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
From
Device
ACK By
Master
Stop By
Master
Frame 5 Data Byte 2 Read Register
NOTE: Address pins A0, A1, and A2 = 0.
Figure 9. Two-Wire Timing Diagram for Read Word Format
ALERT
1
9
1
9
SCL
SDA
0
0
0
1
1
Start By
Master
0
0
R/W
1
0
0
1
0
0
ACK By
Device
Frame 1 SMBus ALERT Response Address Byte
0
From
Device
S ta tu s
NACK By
Master
Stop By
Master
Frame 2 Slave Address Byte
NOTE: Address pins A0, A1, and A2 = 0.
Figure 10. Timing Diagram for SMBus ALERT
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7.4 Device Functional Modes
7.4.1 Shutdown Mode (SD)
The shutdown mode of the TMP275-Q1 allows the user to save maximum power by shutting down all device
circuitry other than the serial interface, thus reducing current consumption to typically less than 0.1 μA. Shutdown
mode is enabled when the SD bit is 1; the device shuts down when the current conversion is completed. When
SD is equal to 0, the device maintains a continuous conversion state.
7.4.2 Thermostat Mode (TM)
The thermostat mode bit of the TMP275-Q1 indicates to the device whether to operate in comparator mode (TM
= 0) or interrupt mode (TM = 1). For more information on comparator and interrupt modes, see the High- and
Low-Limit Registers section.
7.4.2.1 Comparator Mode (TM = 0)
In comparator mode (TM = 0), the ALERT pin is activated when the temperature equals or exceeds the value in
the THIGH register and remains active until the temperature falls below the value in the TLOW register. For more
information on the comparator mode, see the High- and Low-Limit Registers section.
7.4.2.2 Interrupt Mode (TM = 1)
In interrupt mode (TM = 1), the ALERT pin is activated when the temperature exceeds THIGH or goes below the
TLOW register. The ALERT pin is cleared when the host controller reads the temperature register. For more
information on the interrupt mode, see the High- and Low-Limit Registers section.
7.4.3 One-Shot (OS)
The TMP275-Q1 features a one-shot temperature measurement mode. When the device is in shutdown mode,
writing a 1 to the OS bit starts a single temperature conversion. The device returns to the shutdown state at the
completion of the single conversion. This feature is useful for reducing power consumption in the TMP275-Q1
when continuous temperature monitoring is not required. When the configuration register is read, OS always
reads zero.
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7.5 Programming
7.5.1 Pointer Register
Figure 11 shows the internal register structure of the TMP275-Q1. The 8-bit Pointer register of the device is used
to address a given data register. The Pointer register uses the two LSBs to identify which of the data registers
must respond to a read or write command. Table 3 identifies the bits of the Pointer register byte. Table 4
describes the pointer address of the registers available in the TMP275-Q1. The power-up reset value of P1/P0 is
00.
Pointer
Register
Temperature
Register
SCL
Configuration
Register
I/O
Control
Interface
TLOW
Register
SDA
THIGH
Register
Figure 11. Internal Register Structure of the TMP275-Q1
Table 3. Pointer Register Byte (pointer = N/A) [reset = 00h]
P7
P6
P5
P4
P3
P2
0
0
0
0
0
0
P1
P0
Register Bits
Table 4. Pointer Addresses of the TMP275-Q1
P1
P0
TYPE
REGISTER
0
0
R only, default
Temperature register
0
1
R/W
Configuration register
1
0
R/W
TLOW register
1
1
R/W
THIGH register
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7.5.2 Temperature Register
The Temperature register of the TMP275-Q1 is a 12-bit, read-only register that stores the output of the most
recent conversion. Two bytes must be read to obtain data and are described in Table 5 and Table 6. Note that
byte 1 is the most significant byte and is followed by byte 2, the least significant byte. The first 12 bits are used to
indicate temperature, with all remaining bits equal to zero. The least significant byte does not have to be read if
that information is not needed. The data format for temperature is summarized in Table 1. Following power-up or
reset, the Temperature register reads 0°C until the first conversion is complete.
Table 5. Byte 1 of the Temperature Register
D7
D6
D5
D4
D3
D2
D1
D0
T11
T10
T9
T8
T7
T6
T5
T4
Table 6. Byte 2 of the Temperature Register
D7
D6
D5
D4
D3
D2
D1
D0
T3
T2
T1
T0
0
0
0
0
7.5.3 Configuration Register
The Configuration register is an 8-bit read/write register used to store bits that control the operational modes of
the temperature sensor. Read and write operations are performed MSB first. The format of the Configuration
register for the TMP275-Q1 is shown in Table 7, followed by a breakdown of the register bits. The power-up or
reset value of the Configuration register is all bits equal to 0.
Table 7. Configuration Register Format
16
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
1
OS
R1
R0
F1
F0
POL
TM
SD
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7.5.4 Polarity (POL)
The Polarity bit of the TMP275-Q1 allows the user to adjust the polarity of the ALERT pin output. If POL = 0, the
ALERT pin is active low, as shown in Figure 12. For POL = 1, the ALERT pin is active high and the state of the
ALERT pin is inverted.
THIGH
Measured
Temperature
TLOW
Device ALERT Pin
(Compara tor Mode)
POL =0
Device ALERT Pin
(Interrupt Mode)
POL =0
Device ALERT Pin
(Compara tor Mode)
POL =1
Device ALERT Pin
(Interrupt Mode)
POL =1
Read
Read
Read
Time
Figure 12. Output Transfer Function Diagrams
7.5.5 Fault Queue (F1/F0)
A fault condition is defined as when the measured temperature exceeds the user-defined limits set in the THIGH
and TLOW registers. Additionally, the number of fault conditions required to generate an alert can be programmed
using the fault queue. The fault queue is provided to prevent a false alert resulting from environmental noise. The
fault queue requires consecutive fault measurements to trigger the Alert function. Table 8 defines the number of
measured faults that can be programmed to trigger an Alert condition in the device. For the THIGH and TLOW
register format and byte order, see the High- and Low-Limit Registers section.
Table 8. Fault Settings
F1
F0
CONSECUTIVE FAULTS
0
0
1
0
1
2
1
0
4
1
1
6
7.5.6 Converter Resolution (R1/R0)
The converter resolution bits control the resolution of the internal analog-to-digital converter (ADC). This control
allows the user to maximize efficiency by programming for higher resolution or faster conversion time. Table 9
identifies the resolution bits and the relationship between resolution and conversion time.
Table 9. Resolution of the TMP275-Q1
R1
R0
RESOLUTION
CONVERSION TIME
(Typical)
0
0
9 bits (0.5°C)
27.5 ms
0
1
10 bits (0.25°C)
55 ms
1
0
11 bits (0.125°C)
110 ms
1
1
12 bits (0.0625°C)
220 ms
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7.5.7 High- and Low-Limit Registers
In comparator mode (TM = 0), the ALERT pin of the TMP275-Q1 becomes active when the temperature equals
or exceeds the value in THIGH and generates a consecutive number of faults according to fault bits F1 and F0.
The ALERT pin remains active until the temperature falls below the indicated TLOW value for the same number of
faults.
In interrupt mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds THIGH for a
consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register
occurs, or the device successfully responds to the SMBus alert response address. The ALERT pin is also
cleared if the device is placed in shutdown mode. When cleared, the ALERT pin only becomes active again by
the temperature falling below TLOW. When the temperature falls below TLOW, the ALERT pin becomes active and
remains active until cleared by a read operation of any register or a successful response to the SMBus alert
response address. When the ALERT pin is cleared, the above cycle repeats, with the ALERT pin becoming
active when the temperature equals or exceeds THIGH. The ALERT pin can also be cleared by resetting the
device with the General-Call Reset command. This action also clears the state of the internal registers in the
device, returning the device to comparator mode (TM = 0).
Both operational modes are represented in Figure 12. Table 10, Table 11, Table 12, and Table 13 describe the
format for the THIGH and TLOW registers. Note that the most significant byte is sent first, followed by the least
significant byte. Power-up reset values for THIGH and TLOW are:
THIGH = 80°C and TLOW = 75°C
The format of the data for THIGH and TLOW is the same as for the Temperature register.
Table 10. Byte 1 the THIGH Register
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
1
H11
H10
H9
H8
H7
H6
H5
H4
Table 11. Byte 2 of the THIGH Register
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
2
H3
H2
H1
H0
0
0
0
0
Table 12. Byte 1 the TLOW Register
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
1
L11
L10
L9
L8
L7
L6
L5
L4
Table 13. Byte 2 of the TLOW Register
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
2
L3
L2
L1
L0
0
0
0
0
All 12 bits for the Temperature, THIGH, and, TLOW registers are used in the comparisons for the Alert function for
all converter resolutions. The three LSBs in THIGH and TLOW can affect the Alert output even if the converter is
configured for 9-bit resolution.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TMP275-Q1 is a digital output temperature sensor with SMBus, two-wire, and I2C compatible interfaces. The
device features three address pins (A0, A1, A2), allowing up to eight devices to be connected per bus. The
TMP275-Q1 requires no external components for operation except for pullup resistors on SCL, SDA, and
ALERT, although a 0.1-μF bypass capacitor is recommended. The TMP275-Q1 measures the printed circuit
board (PCB) temperature of where the device is mounted. The sensing device of the TMP275-Q1 is the device
itself. Thermal paths run through the package leads as well as the plastic package. The lower thermal resistance
of metal causes the leads to provide the primary thermal path.
8.2 Typical Applications
8.2.1 Typical Connections of the TMP275-Q1
2.7-V to 5.5-V
Supply Voltage
0.01-µF
Supply Bypass Capacitor
5-k
Pullup Resistors
1
Two-Wire
Host Controller
2
3
4
SDA
TMP275-Q1
V+
SCL
A0
ALERT
A1
GND
A2
8
7
6
5
Figure 13. Typical Connections of the TMP275-Q1 Schematic
8.2.1.1 Design Requirements
Figure 13 shows the TMP275-Q1 typical connections. The TMP275-Q1 device requires pullup resistors on the
SCL, SDA, and ALERT pins. The recommended value for the pullup resistor is 5 kΩ. In some applications the
pullup resistor can be lower or higher than 5 kΩ, but must not exceed 3 mA of current on the SCL and SDA pins
and must not exceed 4 mA on the ALERT pin. If the resistors are missing, the SCL and SDA lines are always low
(nearly 0 V) and the I2C bus does not work. A 0.1-μF bypass capacitor is recommended, as shown in Figure 13.
The SCL, SDA, and ALERT lines can be pulled up to a supply that is equal to or higher than V+ through the
pullup resistors.
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Typical Applications (continued)
The ALERT pin can be configured to respond to one of the two Alert functions available: comparator mode and
interrupt mode. To configure one of eight different addresses on the bus, connect A0, A1, and A2 to either the
GND or V+ pin. In the circuit shown in Figure 13, the comparator mode is selected and the address pins (A0, A1,
A2) are connected to ground.
8.2.1.2 Detailed Design Procedure
Place the TMP275-Q1 device in close proximity to the heat source that must be monitored with a proper layout
for good thermal coupling. This placement ensures that temperature changes are captured within the shortest
possible time interval. To maintain accuracy in applications that require air or surface temperature measurement,
take care to isolate the package and leads from ambient air temperature. A thermally-conductive adhesive is
helpful in achieving accurate surface temperature measurement.
8.2.1.3 Application Curve
Temperature (qC)
Figure 14 shows the step response of the TMP275-Q1 device to a submersion in an oil bath of 100ºC from room
temperature (27ºC). The time-constant, or the time for the output to reach 63% of the input step, is 1.5 s. The
time-constant result depends on the PCB where the TMP275-Q1 devices are mounted. For this test, the
TMP275-Q1 device was soldered to a two-layer PCB that measured 0.375 inches × 0.437 inches.
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
-1
1
3
5
7
9
11
Time (s)
13
15
17
19
Figure 14. Temperature Step Response
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Typical Applications (continued)
8.2.2 Connecting Multiple Devices on a Single Bus
The TMP275-Q1 features three address pins, allowing up to eight devices to be connected per bus. When the
TMP275-Q1 is operating in interrupt mode (TM = 1) , the ALERT pin of the TMP275-Q1 can be connected as an
SMBus Alert signal. Figure 15 shows eight TMP275-Q1 devices connected to an MCU (master) using one single
bus. Each device that exists as a slave on the SMBus has one unique 7-bit address; see Table 2 for the
TMP275-Q1 address options. When a master senses that an Alert condition is present on the ALERT line, the
master sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP275-Q1 is active,
the device acknowledges the SMBus Alert command and responds by returning its slave address on the SDA
line. The eighth bit (LSB) of the slave address byte indicates if the temperature exceeding THIGH or falling below
TLOW caused the ALERT condition. This bit is high if the temperature is greater than or equal to THIGH. This bit is
low if the temperature is less than TLOW.
This application has eight devices connected to the bus. If multiple devices on the bus respond to the SMBus
Alert command, arbitration during the slave address portion of the SMBus Alert command determines which
device clears its ALERT status. If the TMP275-Q1 wins the arbitration, its ALERT pin becomes inactive at the
completion of the SMBus Alert command. If the TMP275-Q1 loses the arbitration, its ALERT pin remains active.
NOTE
Make sure you device is configured to operate in interrupt mode to enable the SMBus
feature.
Supply Voltage
2.7 V to 5.5 V
0.01 µF
5k
V+
SDA
SCL
ALERT
1 SDA TMP275
MCU
2 SCL
3 ALERT
1
4 GND
A0 7
6
A1
1 SDA TMP275
2 SCL
2
3 ALERT
A0 7
6
A1
1 SDA TMP275
2 SCL
3
3 ALERT
A0 7
6
A1
1 SDA TMP275
2 SCL
4
3 ALERT
A0 7
A2 5
4 GND
A2 5
4 GND
A2 5
4 GND
A2 5
V+
8
Slave Address
1001000
V+
8
Slave Address
1001001
V+
8
Slave Address
1001010
V+
A1
8
6
Slave Address
1001011
V+
SDA
SCL
ALERT
1 SDA TMP275
2 SCL
3 ALERT
5
4 GND
V+
8
A0 7
6
A1
A2 5
Slave Address
1001100
1 SDA TMP275
2 SCL
3 ALERT 6
4 GND
V+
8
A0 7
6
A1
A2 5
Slave Address
1001101
1 SDA TMP275
2 SCL
V+
8
3 ALERT 7
A0 7
6
A1
4 GND
A2 5
Slave Address
1001110
1 SDA TMP275
2 SCL
3 ALERT
8
4 GND
V+
8
A0 7
A1
6
A2 5
Slave Address
1001111
Figure 15. Connecting Multiple Devices on a Single Bus
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Typical Applications (continued)
8.2.3 Temperature Data Logger for Cold Chain Management Applications
Cold chain management includes all of the means used to ensure a constant temperature for a product that is
not heat stable from the time it is manufactured or farmed until the time it is used. This cold chain management
includes industries such as food, retail, medical, and pharmaceutical. Figure 16 implements a cold chain
monitoring system that measures temperature, then logs the sensor data to nonvolatile (FRAM) memory in the
MCU. Figure 16 uses a near field communication (NFC) interface for wireless communication and is powered
from a CR2032 coin cell battery with a focus on low power to maximize the battery lifetime.
The microcontroller communicates with all of the sensor devices through an I2C compatible interface. The MCU
also communicates with the NFC transponder through this interface. An NFC-enabled smartphone can be used
to send configurations to the application board. For a detailed design procedure and requirements of this
application, see Ultralow Power Multi-sensor Data Logger with NFC Interface Reference Design.
Coin Cell Battery
(CR2032)
3.0 Volts
5k
NFC
Enabled
Smartphone
Dynamic NFC
Transponder
(RF430CL331H)
2
IC
MCU
(MSP430FR5969)
FRAM
5k
5k
1
DATA
2
CLOCK
3
4
SDA
TMP275
V+
SCL
A0
ALERT
A1
GND
A2
8
7
0.01 µF
6
5
Figure 16. Temperature Data Logger
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9 Power Supply Recommendations
The TMP275-Q1 device operates with power supplies in the range of 2.7 V to 5.5 V. A power-supply bypass
capacitor is required for stability; place this capacitor as close as possible to the supply and ground pins of the
device. A typical value for this supply bypass capacitor is 0.01 μF. Applications with noisy or high-impedance
power supplies can require additional decoupling capacitors to reject power-supply noise.
10 Layout
10.1 Layout Guidelines
Mount the TMP275-Q1 to a PCB as shown in Figure 17. For this example the A0, A1, and A2 address pins are
connected directly to ground. Connecting these pins to ground configures the device for slave address
1001000b.
• Bypass the V+ pin to ground with a low-ESR ceramic bypass capacitor. The typical recommended bypass
capacitance is a 0.1-μF ceramic capacitor with a X5R or X7R dielectric. The optimum placement is closest to
the V+ and GND pins of the device. Take care in minimizing the loop area formed by the bypass-capacitor
connection, the V+ pin, and the GND pin of the device. Additional bypass capacitance can be added to
compensate for noisy or high-impedance power supplies.
• Pull up the open-drain output pins SDA, SCL, and ALERT through 5-kΩ pullup resistors.
10.2 Layout Example
Via to Power or Ground Plane
Via to Internal Layer
Pull-Up Resistors
Supply Bypass
Capacitor
Supply Voltage
SDA
V+
SCL
A0
ALERT
A1
GND
A2
Ground Plane for
Thermal Coupling
to Heat Source
Serial Bus Traces
Heat Source
Figure 17. TMP275-Q1 Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• LM75 Data Sheet
• TMP75, TMP175 Data Sheet
• TMP75B Data Sheet
• Ultralow Power Multi-sensor Data Logger with NFC Interface Reference Design
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
SMBus is a trademark of Intel Corporation.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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Copyright © 2015–2017, Texas Instruments Incorporated
Product Folder Links: TMP275-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMP275AQDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
275Q
TMP275AQDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T275Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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