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TMP431, TMP432
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
具有串联电阻、
η 因数和自动 Beta 补偿的 TMP43x ±1°C 温度传感器
1 特性
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1
3 说明
TMP431 和 TMP432 均是具有内置本地温度传感器的
远程温度传感器监视器。远程温度传感器二极管连接的
晶体管通常是低成本、NPN 或 PNP 类型的晶体管或
二极管，这些器件是微控制器、微处理器或 FPGA 必
不可少的组成部分。
±1°C 远程二极管传感器
±1°C 本地温度传感器
自动 Beta 补偿
η 因数校正
可编程阈值限制
两线制， SMBus™串行接口
最小和最大温度监控器
多接口地址
ALERT/THERM2 引脚配置
二极管故障检测
针对多个器件制造商的远程精度均为 ±1°C，无需校
准。两线制串行接口可接受 SMBus 写入字节、读取字
节、发送字节和接收字节命令，以便对警报阈值进行编
程并读取温度数据。
TMP43X 包括 Beta 补偿（校正）、串联电阻抵消、可
编程非理想性因子、可编程分辨率、可编程阈值限制、
最小和最大温度监视器、宽远程温度测量范围（高达
150°C）、二极管故障检测和温度报警功能。
2 应用
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•
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LCD、 DLP、®LCOS 投影仪
服务器
工业控制器
中央办公电信设备
台式机和笔记本电脑
存储区域网络 (SAN)
工业用和医疗用设备
处理器和 FPGA 温度监视
TMP431 采用 VSSOP-8 封装，TMP432 采用
VSSOP-10 封装。
器件信息(1)
器件型号
封装
封装尺寸（标称值）
TMP431
VSSOP (8)
3.00mm × 3.00mm
TMP432
VSSOP (10)
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
典型应用电路原理图
+5V
+5V
TMP431
TMP432
1
1
V+
SCL
2
3
V+
8
2
SDA
DXN
SCL
DXN1
SDA
10
3
7
9
SMBus
Controller
SMBus
Controller
4
4
DXP2
THERM
5
DXP1
DXP
5
GND
ALERT/ 8
THERM2
DXN2
7
THERM
GND
ALERT/THERM2
6
One Channel Local
One Channel Remote
6
One Channel Local
Two Channels Remote
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS441
TMP431, TMP432
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
www.ti.com.cn
目录
1
2
3
4
5
6
7
8
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
5
5
5
6
7
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 14
8.5 Programming........................................................... 15
8.6 Register Maps ......................................................... 20
9
Application and Implementation ........................ 33
9.1 Application Information............................................ 33
9.2 Typical Application ................................................. 33
10 Power Supply Recommendations ..................... 36
11 Layout................................................................... 36
11.1 Layout Guidelines ................................................. 36
11.2 Layout Examples................................................... 37
12 器件和文档支持 ..................................................... 39
12.1
12.2
12.3
12.4
12.5
相关链接................................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
Glossary ................................................................
39
39
39
39
39
13 机械、封装和可订购信息 ....................................... 39
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision H (March 2016) to Revision I
Page
•
Added acknowledgement information to the SMBus Alert Function section ....................................................................... 19
•
Added register comparison information to the Limit Registers section ................................................................................ 23
•
Removed sentence from the TMP432 Status Register section: Clearing the Status Register bits does not clear the
state of the ALERT pin; an SMBus alert response address command must be used to clear the ALERT pin. ................. 26
•
Added new ALERT pin information to the Configuration Register 1 section........................................................................ 26
•
Changed extended measurement range from: (–55°C to 150°C) to: (–64°C to 191°C) ..................................................... 26
•
Added Conversion Rate Timing Diagram ............................................................................................................................ 28
•
Split the η table column into η = 1.008 and η = 1.000 in the η-Factor Range table ............................................................. 30
Changes from Revision G (December 2015) to Revision H
Page
•
Changed row 1B in Table 4 ................................................................................................................................................. 22
•
Changed 7th paragraph of TMP432 Status Register section .............................................................................................. 26
•
Changed Open Status Register section ............................................................................................................................... 31
•
Added last sentence to High Limit Status Register section.................................................................................................. 32
•
Added last sentence to Low Limit Status Register section ................................................................................................. 32
Changes from Revision F (August 2013) to Revision G
Page
•
添加了 ESD 额定值表、特性 说明部分、器件功能模式、应用和实施部分、电源相关建议部分、布局部分、器件和文
档支持部分以及机械、封装和可订购信息部分 ........................................................................................................................ 1
•
Changed the Timing Requirements table with new I2C data. Updated affected values throughout the data sheet ............. 7
2
版权 © 2009–2019, Texas Instruments Incorporated
TMP431, TMP432
www.ti.com.cn
Changes from Revision E (December 2012) to Revision F
•
Page
通篇将 MSOP-10 更改为 VSSOP-10...................................................................................................................................... 1
Changes from Revision C (February 2011) to Revision D
•
Page
Added five new register descriptions.................................................................................................................................... 31
Changes from Revision D (November 2012) to Revision E
•
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
Page
通篇将 MSOP-8 更改为 VSSOP-8.......................................................................................................................................... 1
Changes from Revision B (April 2010) to Revision C
Page
•
Revised Figure 14 ................................................................................................................................................................ 16
•
Updated Figure 15................................................................................................................................................................ 17
•
Changed Figure 16............................................................................................................................................................... 18
•
Revised Figure 17 ................................................................................................................................................................ 18
•
Updated Serial Bus Address section for TMP431C, TMP431D device versions ................................................................. 19
•
Added footnote (3) to TMP431 Register Map....................................................................................................................... 21
•
Revised information about power-on reset value of THERM limit registers in Limit Registers section ............................... 24
Changes from Revision A (November 2009) to Revision B
•
Page
Corrected Equation 7............................................................................................................................................................ 34
Changes from Original (September 2009) to Revision A
Page
•
已更改 通篇更改了 TMP432 的器件状态 ................................................................................................................................ 1
•
Corrected bit D6 value in Configuration Register 1 in TMP431 Register Map..................................................................... 21
Copyright © 2009–2019, Texas Instruments Incorporated
3
TMP431, TMP432
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
www.ti.com.cn
5 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
DGS Package
10-Pin VSSOP
Top View
V+
1
8
SCL
DXP
2
7
SDA
DXN
3
6
ALERT/THERM2
THERM
4
5
GND
V+
10 SCL
1
DXP1 2
TMP431
DXN1 3
TMP432
9
SDA
8
ALERT/THERM2
DXP2
4
7
THERM
DXN2
5
6
GND
Pin Functions
PIN
NAME
I/O
DESCRIPTION
TMP432
TMP431
ALERT/THERM2
8
6
O
Digital alert (reconfigurable as second thermal flag), active low, open-drain;
requires pullup resistor to V+
DXN
—
3
I
Analog negative connection to remote temperature sensor
DXN1
3
—
I
Analog channel 1 negative connection to remote temperature sensor
DXN2
5
—
I
Analog channel 2 negative connection to remote temperature sensor
DXP
—
2
I
Analog positive connection to remote temperature sensor
DXP1
2
—
I
Analog channel 1 positive connection to remote temperature sensor
DXP2
4
—
I
Analog channel 2 positive connection to remote temperature sensor
GND
6
5
—
SCL
10
8
I
SDA
9
7
I/O
Bidirectional digital, serial data line for SMBus, open-drain; requires pullup resistor
to V+
THERM
7
4
O
Digital, thermal flag, active low, open-drain; requires pullup resistor to V+
V+
1
1
—
Power supply, positive (2.7 V to 5.5 V)
Ground
Digital serial clock line for SMBus, open-drain; requires pullup resistor to V+
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Power supply, VS
TMP431 input voltage
TMP432 input voltage
(1)
4
V
V+ + 0.5
V
–0.5
Pins 4, 7, and 8
–0.5
7
V
Pins 2, 3, 4, 5, and 8
–0.5
V+ + 0.5
V
Pins 7, 9, and 10
–0.5
7
V
10
mA
–55
127
°C
150
°C
130
°C
Junction temperature, TJ
Storage temperature, Tstg
UNIT
7
Pins 2, 3, and 6
Input current
Operating temperature
MAX
–60
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2009–2019, Texas Instruments Incorporated
TMP431, TMP432
www.ti.com.cn
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model (MM)
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
Supply voltage
2.7
3.3
5.5
UNIT
V
Operating free-air temperature, TA
–40
125
ºC
6.4 Thermal Information
THERMAL METRIC (1)
TMP431
TMP432
DGK (VSSOP)
DGS (VSSOP)
UNIT
8 PINS
10 PINS
RθJA
Junction-to-ambient thermal resistance
168.2
164.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
59.7
39
°C/W
RθJB
Junction-to-board thermal resistance
90.1
85.9
°C/W
ψJT
Junction-to-top characterization parameter
7.7
1.6
°C/W
ψJB
Junction-to-board characterization parameter
88.4
84.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2009–2019, Texas Instruments Incorporated
5
TMP431, TMP432
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
www.ti.com.cn
6.5 Electrical Characteristics
at TA = –40°C to 125°C and V+ = 2.7 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TA = –40°C to 125°C
±1.25
±2.5
TA = 0°C to 100°C, V+ = 3.3 V
±0.25
±1
TA = 0°C to 100°C, TDIODE = –40°C to 150°C, V+ = 3.3 V
±0.25
±1
±0.5
±1.5
±3
±5
±0.2
±0.5
UNIT
TEMPERATURE ERROR
TELOCAL
Local temperature sensor
TEREMOTE
Remote temperature sensor
(1)
TA = –40°C to 100°C, TDIODE = –40°C to 150°C, V+ = 3.3 V
TA = –40°C to 125°C, TDIODE = –40°C to 150°C
vs supply (local, remote)
V+ = 2.7 V to 5.5 V
°C
°C
°C/V
TEMPERATURE MEASUREMENT CONVERSION TIME (PER CHANNEL)
Local channel
12
15
17
Remote channel,
beta correction enabled (2)
RC = 1
97
126
137
RC = 0
36
47
52
Remote channel,
beta correction disabled (3)
RC = 1
72
93
100
RC = 0
33
44
47
ms
ms
ms
TEMPERATURE MEASUREMENT RESOLUTION
Local channel
12
Bits
Remote channel
12
Bits
TEMPERATURE MEASUREMENT REMOTE SENSOR SOURCE CURRENTS
High
120
μA
Medium-high
60
μA
Medium-low
12
μA
6
μA
Series resistance (beta correction) (4)
Low
η
Remote transistor ideality factor
β
Beta correction range
1.000 (2)
TMP43x optimized ideality factor
1.008 (3)
0.1
27
SMBus INTERFACE
VIH
Logic input high voltage
(SCL, SDA)
VIL
Logic input low voltage (SCL, SDA)
2.1
0.8
Hysteresis
500
SMBus output low sink current
VOL
V
6
SDA output low voltage
IOUT = 6 mA
Logic input current
0 ≤ VIN ≤ 6 V
mA
0.15
–1
SMBus input capacitance
(SCL, SDA)
0.4
V
1
μA
3
SMBus clock frequency
SMBus timeout
25
V
mV
32
SCL falling edge to SDA valid time
pF
3.4
MHz
35
ms
1
μs
DIGITAL OUTPUTS
VOL
Output low voltage
IOUT = 6 mA
IOH
High-level output leakage current
VOUT = V+
ALERT/THERM2 output low
sink current
ALERT/THERM2 forced to 0.4 V
6
mA
THERM output low sink current
THERM2 forced to 0.4 V
6
mA
(1)
(2)
(3)
(4)
6
0.15
0.4
V
0.1
1
μA
Tested with less than 5-Ω effective series resistance and 100-pF differential input capacitance. TA is the ambient temperature of the
TMP43x. TDIODE is the temperature at the remote diode sensor.
Beta correction configuration set to 1000 and sensor is GND collector-connected (PNP collector to ground).
Beta correction configuration set to 0111 or sensor is diode-connected (base shorted to collector).
If beta correction is disabled (0111), then up to 1-kΩ of series line resistance is cancelled; if beta correction is enabled (1xxx), up to
300 Ω is cancelled.
Copyright © 2009–2019, Texas Instruments Incorporated
TMP431, TMP432
www.ti.com.cn
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
Electrical Characteristics (continued)
at TA = –40°C to 125°C and V+ = 2.7 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
V+
Specified voltage range
2.7
5.5
V
45
μA
0.7
1
mA
3
10
0.0625 conversions per second, V+ = 3.3 V
Eight conversions per second, V+ = 3.3 V
IQ
Quiescent current
UVLO
Undervoltage lockout
POR
Power-on reset threshold
(5)
35
(5)
Serial bus inactive, shutdown mode
Serial bus active, fS = 400 kHz, shutdown mode
90
Serial bus active, fS = 3.4 MHz, shutdown mode
350
2.3
2.4
1.6
μA
2.6
V
2.3
V
Specified temperature range
–40
125
°C
Storage temperature range
–60
130
°C
Beta correction disabled.
6.6 Timing Requirements (1)
FAST MODE
V+
HIGH-SPEED MODE
MIN
MAX
MIN
MAX
0.001
0.4
0.001
2.5
UNIT
f(SCL)
SCL operating frequency
t(BUF)
Bus free time between STOP and START condition
600
160
ns
t(HDSTA)
Hold time after repeated START condition.
After this period, the first clock is generated.
100
100
ns
t(SUSTA)
Repeated START condition setup time
100
100
ns
t(SUSTO)
STOP condition setup time
100
100
ns
(2)
(3)
t(HDDAT)
Data hold time
0
t(SUDAT)
Data setup time
100
25
ns
t(LOW)
SCL clock LOW period
1300
265
ns
t(HIGH)
SCL clock HIGH period
tFD
Data fall time
tRC
Clock rise time
tFC
Clock fall time
(1)
(2)
(3)
V+
900
600
SCLK ≤ 100 kHz
0
80
MHz
60
ns
300
160
300
40
1000
300
ns
40
ns
ns
ns
Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not specified and not
production tested.
For cases with a fall time of SCL less than 20 ns or where the rise time or fall time of SDA is less than 20 ns, the hold time must be
greater than 20 ns.
For cases with a fall time of SCL less than 10 ns or where the rise or fall time of SDA is less than 10 ns, the hold time must be greater
than 10 ns.
Copyright © 2009–2019, Texas Instruments Incorporated
7
TMP431, TMP432
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
www.ti.com.cn
6.7 Typical Characteristics
At TA = 25°C and V+ = 3.3 V, unless otherwise noted.
3
Local Temperature Error (°C)
Remote Temperature Error (°C)
3
2
1
0
-1
-2
Beta Compensation Disabled.
GND Collector-Connected Transistor with n-Factor = 1.008.
-3
2
1
0
-1
-2
-3
-50
75
0
25
50
Ambient Temperature, TA (°C)
-25
100
125
-50
Figure 1. Remote Temperature Error vs Temperature
-25
75
0
25
50
Ambient Temperature, TA (°C)
100
125
Figure 2. Local Temperature Error vs Temperature
150
700
100
600
RGND (Low Beta)
50
500
RGND
IQ (mA)
Remote Temperature Error (°C)
V+ = 3.3V
0
-50
-100
-150
10
TMP431
100
RVs (Low Beta)
5
TMP432
300
200
RVs
0
400
15
20
25
0
0.0625 0.125
30
0.25
0.5
1
4
2
8
Conversion Rate (conversions/s)
Leakage Resistance (MW)
Figure 4. Quiescent Current vs Conversion Rate
Figure 3. Remote Temperature Error vs Leakage Resistance
500
4.0
450
3.5
400
3.0
V+ = 5.5V
300
2.5
IQ (mA)
IQ (mA)
350
250
200
2.0
1.5
150
1.0
100
50
0.5
V+ = 3.3V
0
0
1k
8
10k
100k
1M
10M
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SCL Clock Frequency (Hz)
VS (V)
Figure 5. Shutdown Quiescent Current
vs SCL Clock Frequency
Figure 6. Shutdown Quiescent Current vs Supply Voltage
Copyright © 2009–2019, Texas Instruments Incorporated
TMP431, TMP432
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ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
Typical Characteristics (continued)
At TA = 25°C and V+ = 3.3 V, unless otherwise noted.
2.5
GND Collector-Connected Transistor, 2N3906 (PNP)
(1)(2)
2
1
0
Diode-Connected Transistor, 2N3906 (PNP)
(2)
-1
NOTES (1): Temperature offset is the result of
h-factor being automatically set to 1.000.
Approximate h-factor of 2N3906 is 1.008.
(2) See Figure 11 for schematic configuration.
-2
2.0
Remote Temperature Error (°C)
Remote Temperature Error (°C)
3
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3
0
100 200 300 400 500 600 700 800 900
0
1k
100
200
Figure 7. Remote Temperature Error vs Series Resistance
2
Low-Beta Transistor (Disabled)
GND CollectorConnected
Transistor (Disabled)
0
-1
Diode-Connected
Transistor (Auto, Disabled)
-2
500
3
GND Collector-Connected Transistor (Auto)
1
400
Figure 8. Remote Temperature Error vs Series Resistance
(Low-Beta Transistor)
Remote Temperature Error (°C)
Remote Temperature Error (°C)
3
300
RS (W)
RS (W)
2
1
0
Low-Beta Transistor (Auto)
-1
-2
NOTE: See Figure 12 for schematic configuration.
-3
-3
0
0.2
0.4
0.6
0.8
1.0
1.2 1.4
1.6
1.8
Capacitance (nF)
At 25°C, V+ = 3.3 V, RS = 0 Ω
Figure 9. Remote Temperature Error
vs Differential Capacitance
Copyright © 2009–2019, Texas Instruments Incorporated
2.0
2.2
0
0.2
0.4
0.6
0.8
1.0
1.2 1.4
1.6
1.8
2.0
2.2
Capacitance (nF)
At 25°C, V+ = 3.3 V, RS = 0 Ω, Beta = 011 (AUTO)
Figure 10. Remote Temperature Error
vs Differential Capacitance With 45-nm CPU
9
TMP431, TMP432
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
www.ti.com.cn
7 Parameter Measurement Information
(a) GND Collector-Connected Transistor
RS1
RS2
(b) Diode-Connected Transistor
RS1
DXP
DXN
RS2
(1)
The total series resistance RS = RS1 + RS2 must be less than 1 kΩ; see Filtering.
Figure 11. Series Resistance Configuration
(a) GND Collector-Connected Transistor
DXP
CDIFF
(1)
DXN
(b) Diode-Connected Transistor
DXP
CDIFF
(1)
DXN
(1)
CDIFF must be less than 2200 pF; see Filtering.
Figure 12. Differential Capacitance Configuration
10
Copyright © 2009–2019, Texas Instruments Incorporated
TMP431, TMP432
www.ti.com.cn
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
8 Detailed Description
8.1 Overview
The TMP431 (two-channel) and TMP432 (three-channel) are digital temperature sensors that combine a local die
temperature measurement channel and a remote junction temperature measurement channel in a single
VSSOP-8 (TMP431) or VSSOP-10 (TMP432) package. They are Two-Wire- and SMBus interface-compatible
and are specified over a temperature range of –40°C to 125°C. The TMP43x contain multiple registers for
holding configuration information, temperature measurement results, temperature comparator maximum and
minimum limits, and status information. User-programmed high and low temperature limits stored in the TMP43x
can be used to trigger an overtemperature and undertemperature alarm (ALERT) on local and remote
temperatures. Additional thermal limits can be programmed into the TMP43x and used to trigger another flag
(THERM) that can be used to initiate a system response to rising temperatures.
For proper remote temperature sensing operation, the TMP431 requires only a transistor connected between
DXP and DXN; the TMP432 requires transistors conncected between DXP1 and DXN1, and between DXP2 and
DXN2.
The SCL and SDA interface pins require pullup resistors as part of the communication bus; ALERT and THERM
are open-drain outputs that also need pullup resistors. ALERT and THERM can be shared with other devices if
desired for a wired-OR implementation. TI recommends a 0.1-μF power-supply bypass capacitor for good local
bypassing.
8.2 Functional Block Diagram
V+
Voltage Regulator
Register Bank
Oscillator
Serial Interface
Current Sources
Control Logic
SCL
SDA
ALERT/THERM2
DXP
Signal
Conditioning
ADC
DXN
THERM
Local
Temperature
Sensor
GND
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8.3 Feature Description
8.3.1 Temperature Measurement Data
Temperature measurement data are taken over a default range of 0°C to 127°C for both local and remote
locations. However, measurements from –55°C to 150°C can be made both locally and remotely by reconfiguring
the TMP43x for the extended temperature range, as described in this section. Temperature data resulting from
conversions within the default measurement range are represented in binary form, as shown in Table 1,
Standard Binary column. Note that any temperature below 0°C results in a data value of zero (00h). Likewise,
temperatures above 127°C result in a value of 127 (7Fh). The device can be set to measure over an extended
temperature range by changing bit 2 of Configuration Register 1 from low to high. The change in measurement
range and data format from standard binary to extended binary occurs at the next temperature conversion.
For data captured in the extended temperature range configuration, an offset of 64 (40h) is added to the
standard binary value, as shown in Table 1, Extended Binary column. This configuration allows measurement of
temperatures as low as –64°C, and as high as 191°C; however, most temperature-sensing diodes only measure
with the range of –55°C to 150°C.
Additionally, the TMP43x are rated only for ambient local temperatures ranging from –40°C to 125°C.
Parameters in Absolute Maximum Ratings must be observed.
Both local and remote temperature data use two bytes for data storage. The high byte stores the temperature
with 1°C resolution. The second or low byte stores the decimal fraction value of the temperature and allows a
higher measurement resolution; see Table 2.
The measurement resolution for both the local and remote channels is 0.0625°C, and cannot be adjusted.
Table 1. Temperature Data Format (Local and Remote Temperature High Bytes)
LOCAL/REMOTE TEMPERATURE REGISTER
HIGH BYTE VALUE (1°C RESOLUTION)
TEMP (°C)
(1)
(2)
12
STANDARD BINARY (1)
EXTENDED BINARY (2)
BINARY
HEX
BINARY
−64
0000 0000
00
0000 0000
HEX
00
−50
0000 0000
00
0000 1110
0E
−25
0000 0000
00
0010 0111
27
0
0000 0000
00
0100 0000
40
1
0000 0001
01
0100 0001
41
5
0000 0101
05
0100 0101
45
10
0000 1010
0A
0100 1010
4A
25
0001 1001
19
0101 1001
59
50
0011 0010
32
0111 0010
72
75
0100 1011
4B
1000 1011
8B
100
0110 0100
64
1010 0100
A4
125
0111 1101
7D
1011 1101
BD
127
0111 1111
7F
1011 1111
BF
150
0111 1111
7F
1101 0110
D6
175
0111 1111
7F
1110 1111
EF
191
0111 1111
7F
1111 1111
FF
Resolution is 1°C per count. Negative numbers are represented in twos complement format.
Resolution is 1°C per count. All values are unsigned with a –64°C offset.
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Table 2. Decimal Fraction Temperature Data Format (Local and Remote Temperature Low Bytes)
TEMP (°C)
(1)
TEMPERATURE REGISTER LOW BYTE VALUE (0.0625°C RESOLUTION) (1)
STANDARD AND EXTENDED BINARY
HEX
0
0000 0000
00
0.0625
0001 0000
10
0.1250
0010 0000
20
0.1875
0011 0000
30
0.2500
0100 0000
40
0.3125
0101 0000
50
0.3750
0110 0000
60
0.4375
0111 0000
70
0.5000
1000 0000
80
0.5625
1001 0000
90
0.6250
1010 0000
A0
0.6875
1011 0000
B0
0.7500
1100 0000
C0
0.8125
1101 0000
D0
0.8750
1110 0000
E0
0.9375
1111 0000
F0
Resolution is 0.0625°C per count. All possible values are shown.
8.3.2 Beta Compensation
Previous generations of remote junction temperature sensors were operated by controlling the emitter current of
the sensing transistor. However, examination of the physics of a transistor shows that VBE is actually a function
of the collector current. If beta is independent of the collector current, then VBE can be calculated from the emitter
current. In earlier generations of processors that contained PNP transistors connected to these temperature
sensors, controlling the emitter current provided acceptable temperature measurement results. At 90-nm process
geometry and below, however, the beta factor continues to decrease and the premise that it is independent of
collector current becomes less certain.
To manage this increasing temperature measurement error, the TMP43x control the collector current instead of
the emitter current. The TMP43x automatically detect and choose the correct range depending on the beta factor
of the external transistor. This auto-ranging is performed at the beginning of each temperature conversion in
order to correct for any changes in the beta factor as a result of temperature variation. The device can operate a
PNP transistor with a beta factor as low as 0.1. See Beta Compensation Configuration Register for further
information.
8.3.3
Series Resistance Cancellation
Series resistance in an application circuit that typically results from printed circuit-board (PCB) trace resistance
and remote line length is automatically cancelled by the TMP43x, preventing what would otherwise result in a
temperature offset. A total of up to 1-kΩ of series line resistance is cancelled by the TMP43x if beta correction is
disabled and up to 300 Ω of series line resistance is cancelled if beta correction is enabled, eliminating the need
for additional characterization and temperature offset correction. See Figure 7 and Figure 8 for details on the
effects of series resistance on sensed remote temperature error.
8.3.4 Differential Input Capacitance
The TMP43x can tolerate differential input capacitance of up to 2200 pF with minimal change in temperature
error. The effect of capacitance on sensed remote temperature error is illustrated in Figure 9 and Figure 10. See
Filtering for suggested component values where filtering unwanted coupled signals is needed.
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8.3.5 Filtering
Remote junction temperature sensors are usually implemented in noisy environments. Noise is frequently
generated by fast digital signals and if not filtered properly can induce errors that corrupt temperature
measurements. The TMP43x have a built-in 65-kHz filter on the inputs of DXP and DXN to minimize the effects
of noise. However, a differential low-pass filter can help attenuate unwanted coupled signals. Exact component
values are application-specific. TI also recommends that the capacitor value remains from 0 pF to 2200 pF with a
series resistance less than 1 kΩ.
8.3.6 Sensor Fault
The TMP43x can sense a fault at the DXP input that results from an incorrect diode connection or an open
circuit. The detection circuitry consists of a voltage comparator that trips when the voltage at DXP exceeds
(V+) – 0.6 V (typical). The comparator output is continuously checked during a conversion. If a fault is detected,
the last valid measured temperature is used for the temperature measurement result, the OPEN bit (Status
Register, bit 2) is set high, and, if the alert function is enabled, ALERT asserts low.
When not using the remote sensor with the TMP43x, the DXP and DXN inputs must be connected together to
prevent meaningless fault warnings.
8.3.7
THERM and ALERT/THERM2
The TMP43x have two pins dedicated to alarm functions, the THERM and ALERT/THERM2 pins. Both pins are
open-drain outputs that each require a pullup resistor to V+. These pins can be wire-ORed together with other
alarm pins for system monitoring of multiple sensors. The THERM pin provides a thermal interrupt that cannot be
software disabled. The ALERT pin is intended for use as an earlier warning interrupt, and can be software
disabled, or masked. The ALERT/THERM2 pin can also be configured for use as THERM2, a second THERM
pin (Configuration Register 1: AL/TH bit = 1). The default setting configures pin 6 for the TMP431 and pin 8 for
the TMP432 to function as ALERT (AL/TH = 0).
The THERM pin asserts low when either the measured local or remote temperature is outside of the temperature
range programmed in the corresponding Local/Remote THERM Limit Register. The THERM temperature limit
range can be programmed with a wider range than that of the limit registers, which allows ALERT to provide an
earlier warning than THERM. The THERM alarm resets automatically when the measured temperature returns to
within the THERM temperature limit range minus the hysteresis value stored in the THERM Hysteresis Register.
The allowable values of hysteresis are listed in Table 13. The default hysteresis is 10°C. When the
ALERT/THERM2 pin is configured as a second thermal alarm (Configuration Register: bit 7 = x, bit 5 = 1), it
functions the same as THERM, but uses the temperatures stored in the Local/Remote Temperature High Limit
Registers to set its comparison range.
When ALERT/THERM2 is configured as ALERT (Configuration Register 1: bit 7 = 0, bit 5 = 0), the pin asserts
low when either the measured local or remote temperature violates the range limit set by the corresponding
Local/Remote Temperature High/Low Limit Registers. This alert function can be configured to assert only if the
range is violated a specified number of consecutive times (1, 2, 3, or 4). The consecutive violation limit is set in
the Consecutive Alert Register. False alerts that occur as a result of environmental noise can be prevented by
requiring consecutive faults. ALERT also asserts low if the remote temperature sensor is open-circuit. When the
MASK function is enabled (Configuration Register 1: bit 7 = 1), ALERT is disabled (that is, masked). ALERT
resets when the master reads the device address, as long as the condition that caused the alert no longer
persists, and the Status Register has been reset.
8.4 Device Functional Modes
8.4.1 Shutdown Mode (SD)
The TMP43x shutdown mode allows the user to save maximum power by shutting down all device circuitry other
than the serial interface, reducing current consumption to typically less than 3 µA; see Figure 6. Shutdown mode
is enabled when the SD bit of the Configuration Register 1 is high; the device shuts down immediately, aborting
the current conversion. When SD is low, the device maintains a continuous conversion state.
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Device Functional Modes (continued)
8.4.2 One-Shot Mode
When the TMP43x are in shutdown mode (SD = 1 in the Configuration Register 1), a single conversion on both
channels is started by writing any value to the One-Shot Start Register, pointer address 0Fh. This write operation
starts one conversion; the TMP43x return to shutdown mode when that conversion completes. The value of the
data sent in the write command is irrelevant and is not stored by the TMP43x. When the TMP43x are in
shutdown mode, an initial 200 ps is required before a one-shot command can be given. (Note: When a shutdown
command is issued, the TMP43x shut down immediately, aborting the current conversion.) This wait time only
applies to the 200 ps immediately following shutdown. One-shot commands can be issued without delay
thereafter.
8.5 Programming
8.5.1 Serial Interface
The TMP43x operate only as slave devices on either the Two-Wire bus or the SMBus. Connections to either bus
are made via the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike
suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP43x
support the transmission protocol for fast (1 kHz to 400 kHz) and high-speed (1 kHz to 2.5 MHz) modes. All data
bytes are transmitted MSB first.
8.5.2 Bus Overview
The TMP43x are SMBus interface-compatible. In SMBus protocol, the device that initiates the transfer is called a
master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that
generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions.
To address a specific device, a START condition is initiated. START is indicated by pulling the data line (SDA)
from a high to low logic level when SCL is high. All slaves on the bus shift in the slave address byte, with the last
bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being
addressed responds to the master by generating an Acknowledge and pulling SDA low.
Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge bit. During data
transfer SDA must remain stable when SCL is high because any change in SDA when SCL is high is interpreted
as a control signal.
When all data are transferred, the master generates a STOP condition. STOP is indicated by pulling SDA from
low to high when SCL is high.
8.5.3 Timing Diagrams
The TMP43x are Two-Wire and SMBus-compatible. Figure 13 to Figure 17 describe the various operations on
the TMP43x. Parameters for Figure 13 are defined in Figure 14. Bus definitions are given below:
Bus Idle: Both SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the SDA line from high to low when the SCL line is high defines a
START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a
STOP condition. Each data transfer terminates with a STOP or a repeated START condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and
is determined by the master device. The receiver acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device
that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA
line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into
account. On a master receive, data transfer termination can be signaled by the master generating a NotAcknowledge on the last byte that has been transmitted by the slave.
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Programming (continued)
t(LOW)
tF
tR
t(HDSTA)
SCL
t(HDSTA)
t(HIGH)
t(HDDAT)
t(SUSTO)
t(SUSTA)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
Figure 13. Two-Wire Timing Diagram
1
9
9
1
¼
SCL
1
SDA
0
0
1
1
0
0(1)
Start By
Master
P7
R/W
P6
P5
P4
P3
P2
P1
ACK By
TMP431A/32A/31C
ACK By
TMP431A/32A/31C
Frame 2 Pointer Register Byte
Frame 1 Two- Wire Slave Address Byte
9
1
¼
P0
1
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
ACK By
Stop By
TMP431A/32A/ Master
31C
ACK By
TMP431A/32A/31C
Frame 3 Data Byte 1
(1)
D0
Frame 4 Data Byte 2
Slave address 1001100 (TMP431A, 32A, and 31C) shown. Slave address changes for TMP431B, 32B, and 31D. See
机械、封装和可订购信息 for more details.
Figure 14. Two-Wire Timing Diagram for Write Word Format
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Programming (continued)
1
9
1
9
SCL
SDA
1
0
0
1
1
0
0(1)
Start By
Master
R/W
P7
P6
P5
P4
P3
P2
P1
ACK By
TMP431A/32A/31C
ACK By
TMP431A/32A/31C
Frame 1 Two-Wire Slave Address Byte
1
P0
Frame 2 Pointer Register Byte
9
1
9
SCL
(Continued)
SDA
(Continued)
1
0
0
1
Start By
Master
1
0
0(1)
R/W
D7
ACK By
TMP431A/32A/31C
Frame 3 Two-Wire Slave Address Byte
D6
D5
D4
D3
D2
D1
D0
From
TMP431A/32A/31C
NACK By
Master(2)
Frame 4 Data Byte 1 Read Register
(1)
Slave address 1001100 (TMP431A, 32A, and 31C) shown. Slave address changes for TMP431B, 32B, and 31D. See
机械、封装和可订购信息 for more details.
(2)
Master must leave SDA high to terminate a single-byte read operation.
Figure 15. Two-Wire Timing Diagram for Single-Byte Read Format
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Programming (continued)
1
9
1
9
SCL
SDA
0
1
0
1
1
0
0(1)
Start By
Master
R/W
P7
P6
P5
P4
P3
P2
P1
ACK By
TMP431A/32A/31C
P0
ACK By
TMP431A/32A/31C
Frame 1 Two-Wire Slave Address Byte
Frame 2 Pointer Register Byte
1
9
1
9
SCL
(Continued)
SDA
(Continued)
1
0
0
1
1
0
0(1)
Start By
Master
D7
R/W
D6
D5
D4
ACK By
TMP431A/32A/31C
D2
D1
D0
From
TMP431A/32A/31C
Frame 3 Two-Wire Slave Address Byte
1
D3
ACK By
Master
Frame 4 Data Byte 1 Read Register
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
From
TMP431A/32A/31C
NACK By
Master (2)
Stop By
Master
Frame 5 Data Byte 2 Read Register
(1)
Slave address 1001100 (TMP431A, 32A, and 31C) shown. Slave address changes for TMP431B, 32B, and 31D. See
机械、封装和可订购信息 for more details.
(2)
Master must leave SDA high to terminate a two-byte read operation.
Figure 16. Two-Wire Timing Diagram for Two-Byte Read Format
ALERT
1
9
1
9
SCL
SDA
0
Start By
Master
0
0
1
1
0
0
R/W
ACK By
TMP431A/32A/31C
Frame 1 SMBus ALERT Response Address Byte
(1)
1
0
0
1
1
0
0
(1)
Status
From
NACK By
TMP431A/32A/31C Master
Stop By
Master
Frame 2 Slave Address Byte
Slave address 1001100 (TMP431A, 32A, and 31C) shown. Slave address changes for TMP431B, 32B, and 31D. See
机械、封装和可订购信息 for more details.
Figure 17. Timing Diagram for SMBus ALERT
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Programming (continued)
8.5.4 Serial Bus Address
To communicate with the TMP43x, the master must first address slave devices via a slave address byte. The
slave address byte consists of seven address bits, and a direction bit that indicates the intent of executing a read
or write operation.
The address of the TMP431A, 32A, and 31C is 4Ch (1001100b). The address of the TMP431B, 32B, and 31D is
4Dh (1001101b).
8.5.5 Read and Write Operations
Accessing a particular register on the TMP43x is accomplished by writing the appropriate value to the Pointer
Register. The value for the Pointer Register is the first byte transferred after the slave address byte with the R/W
bit low. Every write operation to the TMP43x require a value for the Pointer Register (see Figure 14).
When reading from the TMP43x, the last value stored in the Pointer Register by a write operation is used to
determine which register is read by a read operation. To change the register pointer for a read operation, a new
value must be written to the Pointer Register. This transaction is accomplished by issuing a slave address byte
with the R/W bit low, followed by the Pointer Register byte. No additional data are required. The master can then
generate a START condition and send the slave address byte with the R/W bit high to initiate the read command.
See Figure 15 for details of this sequence. If repeated reads from the same register are desired, it is not
necessary to continually send the Pointer Register bytes, because the TMP43x retain the Pointer Register value
until it is changed by the next write operation. Note that register bytes are sent MSB first, followed by the LSB.
8.5.6 Undervoltage Lockout
The TMP43x sense when the power-supply voltage has reached a minimum voltage level for the ADC to
function. The detection circuitry consists of a voltage comparator that enables the ADC after the power supply
(V+) exceeds 2.45 V (typical). The comparator output is continuously checked during a conversion. The TMP43x
do not perform a temperature conversion if the power supply is not valid. The last valid measured temperature is
used for the temperature measurement result.
8.5.7 Timeout Function
The serial interface of the TMP43x resets if either SCL or SDA are held low for 32 ms (typical) between a START
and STOP condition. If the TMP43x are holding the bus low, it releases the bus and waits for a START condition.
8.5.8 High-Speed Mode
For the Two-Wire bus to operate at frequencies above 400 kHz, the master device must issue a High-speed
mode (Hs-mode) master code (00001XXX) as the first byte after a START condition to switch the bus to highspeed operation. The TMP43x do not acknowledge this byte, but switch the input filters on SDA and SCL and the
output filter on SDA to operate in Hs-mode, allowing transfers at up to 2.5 MHz. After the Hs-mode master code
has been issued, the master transmits a Two-Wire slave address to initiate a data transfer operation. The bus
continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition,
the TMP43x switch the input and output filter back to fast-mode operation.
8.5.9 General Call Reset
The TMP43x support reset through the Two-Wire General Call address 00h (0000 0000b). The TMP43x
acknowledge the General Call address and respond to the second byte. If the second byte is 06h (0000 0110b),
the TMP43x execute a software reset. This software reset restores the power-on reset state to all TMP43x
registers, aborts any conversion in progress, and clears the ALERT and THERM pins. The TMP43x take no
action in response to other values in the second byte.
8.5.10 SMBus Alert Function
The TMP43x support the SMBus Alert function. When pin 6 (for the TMP431) or pin 8 (for the TMP432) is
configured as an alert output, the ALERT pin of the TMP43x can be connected as an SMBus Alert signal. When
a master detects an alert condition on the ALERT line, the master sends an SMBus Alert command (00011001)
on the bus. If the ALERT pin of the TMP43x is active, the devices acknowledge the SMBus Alert command and
respond by returning the slave address on the SDA line and release the SMBus alert line after the
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Programming (continued)
acknowledgement of their address. The eighth bit (LSB) of the slave address byte indicates whether the
temperature exceeding one of the temperature high limit settings or falling below one of the temperature low limit
settings caused the alert condition. This bit is high if the temperature is greater than or equal to one of the
temperature high limit settings; this bit is low if the temperature is less than one of the temperature low limit
settings. After acknowledging the slave address, the device disengages its ALERT pulldown. The TMP43x
disengages the ALERT pulldown by setting the ALERT Mask Bit in the Configuration Register after sending out
its address in response to an ARA and releases the ALERT output pin. This command will not clear the previous
alert. Once the ALERT Mask bit is activated, the ALERT output pin will be disabled until enabled by software. In
order to enable the ALERT, the master must read the ALERT Status Register during the interrupt service routine,
and then reset the ALERT Mask bit in the Configuration Register to 0 at the end of the interrupt service. routine.
See Figure 18 for details of this sequence.
THERM Limit and ALERT High Limit
Measured
Temperature
ALERT Low Limit and THERM Limit Hysteresis
THERM
ALERT
SMBus ALERT
Read
Read
Read
Time
Figure 18. SMBus Alert Timing Diagram
If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion
of the SMBus Alert command determines which device clears its alert status. If the TMP43x win the arbitration,
the ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP43x lose the
arbitration, the ALERT pin remains active.
8.6 Register Maps
The TMP43x contain multiple registers for holding configuration information, temperature measurement results,
temperature comparator maximum, minimum, limits, and status information. These registers are described in
Figure 19 and in Table 3 for the TMP431, and in Table 4 for the TMP432.
Pointer Register
Local and Remote Temperature Registers
Local and Remote Limit Registers
THERM Hysteresis Register
SDA
Status Register
Configuration Register
Beta Correction Register
I/O
Control
Interface
Conversion Rate Register
SCL
Consecutive Alert Register
Identification Registers
Figure 19. Internal Register Structure
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Register Maps (continued)
Table 3. TMP431 Register Map
POINTER ADDRESS
(HEX)
READ
00
(1)
(2)
(3)
(4)
WRITE
NA
(1)
BIT DESCRIPTIONS
POWER-ON
RESET (HEX)
REGISTER
DESCRIPTIONS
D7
D6
D5
D4
D3
D2
D1
D0
00
LT11
LT10
LT9
LT8
LT7
LT6
LT5
LT4
Local temperature
(high byte)
RT11
RT10
RT9
RT8
RT7
RT6
RT5
RT4
Remote
temperature (high
byte)
01
NA
00
02
NA
80
BUSY
LHIGH
LLOW
RHIGH
RLOW
OPEN
RTHRM
LTHRM
Status register
03
09
00
MASK
SD
AL/TH
0
0
RANGE
0
0
Configuration
register 1
04
0A
07
0
0
0
0
R3
R2
R1
R0
Conversion rate
register
05
0B
55
LTH11
LTH10
LTH9
LTH8
LTH7
LTH6
LTH5
LTH4
Local temperature
high limit (high
byte)
06
0C
00
LTL11
LTL10
LTL9
LTL8
LTL7
LTL6
LTL5
LTL4
Local temperature
low limit (high byte)
07
0D
55
RTH11
RTH10
RTH9
RTH8
RTH7
RTH6
RTH5
RTH4
Remote
temperature high
limit (high byte)
08
0E
00
RTL11
RTL10
RTL9
RTL8
RTL7
RTL6
RTL5
RTL4
Remote
temperature low
limit (high byte)
NA
0F
X
X
X
X
X
X
X
X
One-shot start
10
NA
00
RT3
RT2
RT1
RT0
0
0
0
0
Remote
temperature (low
byte)
13
13
00
RTH3
RTH2
RTH1
RTH0
0
0
0
0
Remote
temperature high
limit (low byte)
14
14
00
RTL3
RTL2
RTL1
RTL0
0
0
0
0
Remote
temperature low
limit (low byte)
15
NA
00
LT3
LT2
LT1
LT0
0
0
0
0
Local temperature
(low byte)
16
16
00
LTH3
LTH2
LTH1
LTH0
0
0
0
0
Local temperature
high limit (low byte)
17
17
00
LTL3
LTL2
LTL1
LTL0
0
0
0
0
Local temperature
low limit (low byte)
18
18
00
NC7
NC6
NC5
NC4
NC3
NC2
NC1
NC0
N-factor correction
RTHL7
RTHL6
RTHL5
RTHL4
RTHL3
RTHL2
RTHL1
RTHL0
Remote THERM
limit
0
0
0
REN
LEN
RC
0
0
Configuration
register 2
19
19
1A
1A
1F
1F
20
20
21
21
22
X
55
(2)
(3)
1C
00
0
0
0
0
0
0
RIMASK
LMASK
Channel mask
LTHL7
LTHL6
LTHL5
LTHL4
LTHL3
LTHL2
LTHL1
LTHL0
Local THERM limit
0A
TH7
TH6
TH5
TH4
TH3
TH2
TH1
TH0
THERM hysteresis
22
70
0
CTH2
CTH1
CTH0
CALT2
CALT1
CALT0
0
Consecutive alert
register
Beta range register
55
(3)
25
25
08
NA
FC
00
FD
NA
31
FE
NA
55
0
0
0
0
BC3
BC2
BC1
BC0
X
X
X
X
X
X
X
Software reset
0
0
1
1
0
0
0
1
TMP431 device ID
0
1
0
1
0
1
0
1
Manufacturer ID
X
(4)
NA = Not applicable; register is write- or read-only.
X = Indeterminate state.
TMP431C and TMP431D versions have a power-on reset value of 69h.
X = Undefined. Writing any value to this register initiates a software reset; see Software Reset
Copyright © 2009–2019, Texas Instruments Incorporated
21
TMP431, TMP432
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
www.ti.com.cn
Table 4. TMP432 Register Map
POINTER ADDRESS
READ
00
(1)
(2)
22
WRITE
NA
(1)
BIT DESCRIPTIONS
POWER-ON
RESET (HEX)
D7
D6
D5
D4
D3
D2
D1
D0
REGISTER
DESCRIPTIONS
00
LT11
LT10
LT9
LT8
LT7
LT6
LT5
LT4
Local temperature
(high byte)
01
NA
00
RT11
RT10
RT9
RT8
RT7
RT6
RT5
RT4
Remote
temperature1 (high
byte)
02
NA
80
BUSY
0
0
HIGH
LOW
OPEN
THERM
0
Status register
03
09
00
MASK
SD
AL/TH
0
0
RANGE
0
0
Configuration
register1
04
0A
07
0
0
0
0
R3
R2
R1
R0
Conversion rate
register
05
0B
55
LTH11
LTH10
LTH9
LTH8
LTH7
LTH6
LTH5
LTH4
Local temperature
high limit (high
byte)
06
0C
00
LTL11
LTL10
LTL9
LTL8
LTL7
LTL6
LTL5
LTL4
Local temperature
low limit (high byte)
07
0D
55
RTH11
RTH10
RTH9
RTH8
RTH7
RTH6
RTH5
RTH4
Remote
temperature1 high
limit (high byte)
08
0E
00
RTL11
RTL10
RTL9
RTL8
RTL7
RTL6
RTL5
RTL4
Remote
temperature1 low
limit (high byte)
NA
0F
X
X
X
X
X
X
X
X
One-shot start
10
NA
00
RT3
RT2
RT1
RT0
0
0
0
0
Remote
temperature1 (low
byte)
13
13
00
RTH3
RTH2
RTH1
RTH0
0
0
0
0
Remote
temperature1 high
limit (low byte)
14
14
00
RTL3
RTL2
RTL1
RTL0
0
0
0
0
Remote
temperature1 low
limit (low byte)
15
15
55
RTH11
RTH10
RTH9
RTH8
RTH7
RTH6
RTH5
RTH4
Remote
temperature2 high
limit (high byte)
16
16
00
RTL11
RTL10
RTL9
RTL8
RTL7
RTL6
RTL5
RTL4
Remote
temperature2 low
limit (high byte)
17
17
00
RTH3
RTH2
RTH1
RTH0
0
0
0
0
Remote
temperature2 high
limit (low byte)
18
18
00
RTL3
RTL2
RTL1
RTL0
0
0
0
0
Remote
temperature2 low
limit (low byte)
19
19
55
RTHL7
RTHL6
RTHL5
RTHL4
RTHL3
RTHL2
RTHL1
RTHL0
Remote therm limit
1A
1A
55
RTHL7
RTHL6
RTHL5
RTHL4
RTHL3
RTHL2
RTHL1
RTHL0
Remote2 therm
limit
1B
1B
00
0
0
0
0
0
R2OPEN
R1OPEN
0
Open status
1F
1F
00
0
0
0
0
0
R2MASK
R1MASK
LMASK
Channel mask
20
20
55
LTHL7
LTHL6
LTHL5
LTHL4
LTHL3
LTHL2
LTHL1
LTHL0
Local therm limit
21
21
0A
TH7
TH6
TH5
TH4
TH3
TH2
TH1
TH0
Therm limit
hysteresis
22
22
70
0
CTH2
CTH1
CTH0
CALT2
CALT1
CALT0
0
Consecutive alert
register
23
NA
00
RT11
RT10
RT9
RT8
RT7
RT6
RT5
RT4
Remote
temperature2 (high
byte)
24
NA
00
RT3
RT2
RT1
RT0
0
0
0
0
Remote
temperature2 (low
byte)
25
25
08
0
0
0
0
BC3
BC2
BC1
BC0
Ch. 1 beta range
selection
26
26
08
0
0
0
0
BC3
BC2
BC1
BC0
Ch. 2 beta range
selection
27
27
00
NC7
NC6
NC5
NC4
NC3
NC2
NC1
NC0
N-factor correction
remote1
28
28
00
NC7
NC6
NC5
NC4
NC3
NC2
NC1
NC0
N-factor correction
remote2
X
(2)
NA = Not applicable; register is write- or read-only.
Indeterminate state.
Copyright © 2009–2019, Texas Instruments Incorporated
TMP431, TMP432
www.ti.com.cn
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
Table 4. TMP432 Register Map (continued)
POINTER ADDRESS
(3)
BIT DESCRIPTIONS
READ
WRITE
POWER-ON
RESET (HEX)
D7
D6
D5
D4
D3
D2
D1
D0
REGISTER
DESCRIPTIONS
29
NA
00
T3
T2
T1
T0
0
0
0
0
Local temperature
(low byte)
35
35
00
0
0
0
0
0
R2HIGH
R1HIGH
LHIGH
High limit status
36
36
00
0
0
0
0
0
R2LOW
R1LOW
LLOW
Low limit status
37
37
00
0
0
0
0
0
R2THERM
R1THERM
LTHERM
Therm status
3D
3D
00
LTH3
LTH2
LTH1
LTH0
0
0
0
0
Local temperature
high limit (low byte)
3E
3E
00
LTL3
LTL2
LTL1
LTL0
0
0
0
0
Local temperature
low limit (low byte)
3F
3F
3C
0
0
REN2
REN
LEN
RC
0
0
Configuration
register2
NA
FC
00
X (3)
X
X
X
X
X
X
X
Software reset
FD
NA
32
0
0
1
1
0
0
1
0
TMP432 device ID
FE
NA
55
0
1
0
1
0
1
0
1
Manufacturer ID
X = Undefined. Writing any value to this register initiates a software reset; see Software Reset.
8.6.1 Pointer Register
Figure 19 illustrates the internal register structure of the TMP43x. The 8-bit Pointer Register is used to address a
given data register. The Pointer Register identifies which of the data registers must respond to a read or write
command on the Two-Wire bus. This register is set with every write command. A write command must be issued
to set the proper value in the Pointer Register before executing a read command. Table 3 describes the pointer
address of the registers available in the TMP431. Table 4 describes the address of the registers available in the
TMP432. The power-on reset (POR) value of the Pointer Register is 00h (0000 0000b).
8.6.2 Temperature Registers
The TMP431 has four 8-bit registers that hold temperature measurement results. The TMP432 has six 8-bit
registers that hold temperature measurement results. Both the local channel and the remote channel have a high
byte register that contains the most significant bits (MSBs) of the temperature analog-to-digital converter (ADC)
result and a low byte register that contains the least significant bits (LSBs) of the temperature ADC result. The
local channel high byte address for the TMP43x is 00h; the local channel low byte address is 15h for the
TMP431 and 29h for the TMP432. The remote channel high byte is at address 01h; the remote channel low byte
address is 10h. For the TMP432, the second remote channel high byte address is 23h; the second remote
channel low byte is 24h. These registers are read-only and are updated by the ADC each time a temperature
measurement is completed.
The TMP43x contain circuitry to assure that a low byte register read command returns data from the same ADC
conversion as the immediately preceding high byte read command. This assurance remains valid only until
another register is read. For proper operation, the high byte of a temperature register must be read first. The low
byte register must be read in the next read command. The low byte register can be left unread if the LSBs are
not needed. Alternatively, the temperature registers can be read as a 16-bit register by using a single two-byte
read command from address 00h for the local channel result, or from address 01h for the remote channel result
(23h for the second remote channel result). The high byte is output first, followed by the low byte. Both bytes of
this read operation are from the same ADC conversion. The power-on reset value of both temperature registers
is 00h.
8.6.3 Limit Registers
The TMP43x have registers for setting comparator limits for both the local and remote measurement channels.
These registers have read and write capability. The High and Low Limit Registers for both channels span two
registers, as do the temperature registers. These registers are only compared to at the end of every conversion
cycle, and not immediately after updating the register value. The local temperature high limit is set by writing the
high byte to pointer address 0Bh and writing the low byte to pointer address 16h for the TMP431 and 3Dh for the
TMP432, or by using a single two-byte write command (high byte first) to pointer address 0Bh.
Copyright © 2009–2019, Texas Instruments Incorporated
23
TMP431, TMP432
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
www.ti.com.cn
The local temperature high limit is obtained by reading the high byte from pointer address 05h and the low byte
from pointer address 16h for the TMP4341 and 3Dh for the TMP432, or by using a two-byte read command from
pointer address 05h. The power-on reset value of the local temperature high limit is 55h, 00h (85°C in standard
temperature mode; 21°C in extended temperature mode).
Similarly, the local temperature low limit is set by writing the high byte to pointer address 0Ch and writing the low
byte to pointer address 17h for the TMP431 and 3Eh for the TMP432, or by using a single two-byte write
command to pointer address 0Ch. The local temperature low limit is read by reading the high byte from pointer
address 06h and the low byte from pointer address 17h and 3Eh for the TMP432, or by using a two-byte read
from pointer address 06h. The power-on reset value of the local temperature low limit register is 00h, 00h (0°C in
standard temperature mode; –64°C in extended mode).
The remote temperature high limit for the TMP431 (remote temperature1 high limit for the TMP432) is set by
writing the high byte to pointer address 0Dh and writing the low byte to pointer address 13h, or by using a twobyte write command to pointer address 0Dh. The remote temperature high limit is obtained by reading the high
byte from pointer address 07h and the low byte from pointer address 13h, or by using a two-byte read command
from pointer address 07h. The power-on reset value of the Remote Temperature High Limit Register is 55h, 00h
(85°C in standard temperature mode; 21°C in extended temperature mode).
The remote temperature low limit for the TMP431 (remote temperature1 low limit for the TMP432) is set by
writing the high byte to pointer address 0Eh and writing the low byte to pointer address 14h, or by using a twobyte write to pointer address 0Eh. The remote temperature low limit is read by reading the high byte from pointer
address 08h and the low byte from pointer address 14h, or by using a two-byte read from pointer address 08h.
The power-on reset value of the Remote Temperature Low Limit Register is 00h, 00h (0°C in standard
temperature mode; –64°C in extended mode).
The remote temperature2 high limit for the TMP432 is set by writing the high byte to pointer address 15h and
writing the low byte to pointer address 17h, or by using a two-byte write command to pointer address 15h. The
remote temperature high limit is obtained by reading the high byte from pointer address 15h and the low byte
from pointer address 17h, or by using a two-byte read command from pointer address 15h. The power-on reset
value of the Remote Temperature High Limit Register is 55h, 00h (85°C in standard temperature mode; 21°C in
extended temperature mode).
The remote temperature2 low limit for the TMP432 is set by writing the high byte to pointer address 16h and
writing the low byte to pointer address 18h, or by using a two-byte write to pointer address 16h. The remote
temperature low limit is read by reading the high byte from pointer address 16h and the low byte from pointer
address 18h, or by using a two-byte read from pointer address 16h. The power-on reset value of the Remote
Temperature Low Limit Register is 00h, 00h (0°C in standard temperature mode; –64°C in extended mode).
The TMP43x also have a THERM limit register for both the local and the remote channels. These registers are
eight bits and allow for THERM limits set to 1°C resolution. The local channel THERM limit is set by writing to
pointer address 20h. The remote channel THERM limit is set by writing to pointer address 19h. The remote
channel THERM2 limit for the TMP432 is set by writing to pointer address 1Ah.
The local channel THERM limit is obtained by reading from pointer address 20h; the remote channel THERM
limit is read by reading from pointer address 19h. The remote channel THERM2 limit is read by reading from
pointer address 1Ah. The power-on reset value of the THERM limit registers is 55h for the TMP431A, TMP431B,
TMP432A, and TMP432B (85°C in standard temperature mode; 21°C in extended temperature mode). The
power-on reset value of the THERM limit registers is 69h for the TMP431C and TMP431D (105°C in standard
temperature mode; 41°C in extended temperature mode). The THERM limit comparators also have hysteresis.
The hysteresis of both comparators is set by writing to pointer address 21h. The hysteresis value is obtained by
reading from pointer address 21h. The value in the Hysteresis Register is an unsigned number (always positive).
The power-on reset value of this register is 0Ah (+10°C).
NOTE
Whenever changing between standard and extended temperature ranges, be aware that
the temperatures stored in the temperature limit registers are not automatically reformatted
to correspond to the new temperature range format. These values must be reprogrammed
in the appropriate binary or extended binary format.
24
Copyright © 2009–2019, Texas Instruments Incorporated
TMP431, TMP432
www.ti.com.cn
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
8.6.4 Status Registers
8.6.4.1 TMP431 Status Register
Table 5. TMP431 Status Register Format
TMP431 STATUS REGISTER (Read = 02h, Write = NA)
BIT #
D7
D6
D5
D4
D3
D2
D1
D0
BIT NAME
BUSY
LHIGH
LLOW
RHIGH
RLOW
OPEN
RTHRM
LTHRM
POR VALUE
0 (1)
0
0
0
0
0
0
0
(1)
The BUSY bit changes to 1 almost immediately ( 0.25 V at 6 μA, at the highest sensed temperature
2. Base-emitter voltage < 0.95 V at 120 μA, at the lowest sensed temperature
3. Base resistance < 100 Ω
4. Tight control of VBE characteristics indicated by small variations in hFE (that is, 50 to 150)
Based on these criteria, two recommended small-signal transistors are the 2N3904 (NPN) or 2N3906 (PNP).
9.2.2 Detailed Design Procedure
The temperature measurement accuracy of the TMP43x depends on the remote and local temperature sensor
being at the same temperature as the system point being monitored. Clearly, if the temperature sensor is not in
good thermal contact with the part of the system being monitored, then there will be a delay in the response of
the sensor to a temperature change in the system. For remote temperature sensing applications that use a
substrate transistor (or a small, SOT23 transistor) placed close to the device being monitored, this delay is
usually not a concern.
The local temperature sensor inside the TMP43x monitors the ambient air around the device. The thermal time
constant for the TMP43x is approximately 2 s. This constant implies that if the ambient air changes quickly by
100°C, it would take the TMP43x about 10 seconds (that is, five thermal time constants) to settle to within 1°C of
the final value. In most applications, the TMP43x package is in thermal contact with the printed circuit board
(PCB), as well as subjected to forced airflow. The accuracy of the measured temperature directly depends on
how accurately the PCB and forced airflow temperatures represent the temperature that the TMP43x is
measuring. Additionally, the internal power dissipation of the TMP43x can cause the temperature to rise above
the ambient or PCB temperature. The internal power dissipated as a result of exciting the remote temperature
sensor is negligible because of the small currents used. For a 5.5-V supply and maximum conversion rate of
eight conversions per second, the TMP43x dissipate 1.82 mW (PDIQ = 5.5 V × 330 μA). If both the
ALERT/THERM2 and THERM pins are each sinking 1 mA, an additional 0.8 mW is dissipated (PDOUT = 1 mA ×
0.4 V + 1 mA × 0.4 V = 0.8 mW). Total power dissipation is then 2.62 mW (PDIQ + PDOUT) and, with an θJA of
150°C/W, causes the junction temperature to rise approximately 0.393°C above the ambient.
9.2.3 Application Curve
Temperature (ƒC)
Figure 23 shows the typical step response to a submerging of a sensor in an oil bath with temperature of 100ºC.
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
±1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Time (s)
C007
Figure 23. Temperature Step Response
Copyright © 2009–2019, Texas Instruments Incorporated
35
TMP431, TMP432
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
www.ti.com.cn
10 Power Supply Recommendations
The TMP43x devices operates with a power supply range of 2.7 V to 5.5 V. The device is optimized for operation
at 3.3-V supply but can measure temperature accurately in the full supply range.
TI recommends placing a power-supply bypass capacitor as close as possible to the supply and ground pins of
the device. A typical value for this supply bypass capacitor is 0.1 μF. Applications with noisy or high-impedance
power supplies can require additional decoupling capacitors to reject power-supply noise.
11 Layout
11.1 Layout Guidelines
Remote temperature sensing on the TMP43x measures very small voltages using very low currents; therefore,
noise at the IC inputs must be minimized. Most applications using the TMP43x have high digital content, with
several clocks and logic level transitions creating a noisy environment. Layout must conform to the following
guidelines:
1. Place the TMP43x as close to the remote junction sensor as possible.
2. Route the DXP and DXN traces next to each other and shield them from adjacent signals through the use of
ground guard traces; see Figure 25. If a multilayer PCB is used, bury these traces between ground or VDD
planes to shield them from extrinsic noise sources. TI recommends 5 mil (0.127 mm) PCB traces.
3. Minimize additional thermocouple junctions caused by copper-to-solder connections. If these junctions are
used, make the same number and approximate locations of copper-to-solder connections in both the DXP
and DXN connections to cancel any thermocouple effects.
4. Use a 0.1-μF local bypass capacitor directly between the V+ and GND of the TMP43x. Figure 26 illustrates
the suggested bypass capacitor placement for the TMP43x. This capacitance includes any cable capacitance
between the remote temperature sensor and TMP43x.
5. If the connection between the remote temperature sensor and the TMP43x is less than 8 inches
(20.32 cm), use a twisted-wire pair connection. Beyond 8 inches, use a twisted, shielded pair with the shield
grounded as close to the TMP43x as possible. Leave the remote sensor connection end of the shield wire
open to avoid ground loops and 60-Hz pickup.
6. Thoroughly clean and remove all flux residue in and around the pins of the TMP43x to avoid temperature
offset readings as a result of leakage paths between DXP or DXN and GND, or between DXP or DXN and
V+.
36
Copyright © 2009–2019, Texas Instruments Incorporated
TMP431, TMP432
www.ti.com.cn
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
11.2 Layout Examples
VIA to Power or Ground Plane
VIA to Internal Layer
Pull-Up Resistors
Ground Plane
Supply Voltage
Supply Bypass
Capacitor
1
RS
SCL
8
2 DXP
SDA
7
3 DXN
ALERT /
THERM2
6
V+
CDIFF
RS
4
THERM
Thermal
Shutdown
GND 5
Serial Bus Traces
Figure 24. TMP431 Layout Example
V+
DXP
Ground or V+ layer
on bottom and/or
top, if possible.
DXN
GND
Note:
Use 5 mil (0.005 in, or 0.127 mm) traces with 5 mil (0.005 in, or 0.127 mm) spacing.
Figure 25. Example Signal Traces
Copyright © 2009–2019, Texas Instruments Incorporated
37
TMP431, TMP432
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
www.ti.com.cn
Layout Examples (continued)
0.1mF Capacitor
V+
GND
PCB Via
1
8
DXP
2
7
DXN
3
6
4
5
PCB Via
TMP431
0.1mF Capacitor
V+
GND
PCB Via
1
10
9
DXP1
2
DXN1
3
8
DXP2
4
7
DXN2
5
6
PCB Via
TMP432
Figure 26. Suggested Bypass Capacitor Placement
38
版权 © 2009–2019, Texas Instruments Incorporated
TMP431, TMP432
www.ti.com.cn
ZHCSKD0I – SEPTEMBER 2009 – REVISED OCTOBER 2019
12 器件和文档支持
12.1 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
表 16. 相关链接
器件
产品文件夹
样片与购买
技术文档
工具与软件
支持和社区
TMP431
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TMP432
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12.2 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 商标
E2E is a trademark of Texas Instruments.
DLP、 is a registered trademark of Texas Instruments.
SMBus is a trademark of Intel Corporation.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2009–2019, Texas Instruments Incorporated
39
重要声明和免责声明
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Copyright © 2020 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMP431ADGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DRTI
TMP431ADGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DRTI
TMP431BDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DRUI
TMP431BDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DRUI
TMP431CDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DUEC
TMP431CDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DUEC
TMP431DDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DUFC
TMP431DDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DUFC
TMP432ADGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DSCI
TMP432ADGST
ACTIVE
VSSOP
DGS
10
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DSCI
TMP432BDGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DSDI
TMP432BDGST
ACTIVE
VSSOP
DGS
10
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DSDI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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