www.ti.com
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28346, TMS320C28343-Q1,
TMS320C28346-Q1, TMS320C28342,
TMS320C28345, TMS320C28341
TMS320C28344
TMS320C28343,
TMS320C28343, TMS320C28343-Q1,
TMS320C28342,
TMS320C28341
SPRS516F – MARCH
2009 – REVISED
FEBRUARY 2021
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
TMS320C2834x Delfino Microcontrollers
1 Features
•
•
•
•
•
•
•
•
•
High-Performance Static CMOS Technology
– Up to 300 MHz (3.33-ns Cycle Time)
– 1.1-V/1.2-V Core, 3.3-V I/O, 1.8-V PLL/
Oscillator Design
High-Performance 32-Bit CPU (TMS320C28x)
– IEEE 754 Single-Precision Floating-Point Unit
(FPU)
– 16 × 16 and 32 × 32 MAC Operations
– 16 × 16 Dual MAC
– Harvard Bus Architecture
– Fast Interrupt Response and Processing
– Code-Efficient (in C/C++ and Assembly)
Six-Channel DMA Controller (for McBSP, XINTF,
and SARAM)
16-Bit or 32-Bit External Interface (XINTF)
– More Than 2M × 16 Address Reach
On-Chip Memory
– Up to 258K × 16 SARAM
– 8K × 16 Boot ROM
Clock and System Control
– On-Chip Oscillator
– Watchdog Timer Module
Peripheral Interrupt Expansion (PIE) Block That
Supports All 64 Peripheral Interrupts
Endianness: Little Endian
Enhanced Control Peripherals
– Eighteen Enhanced Pulse Width Modulator
(ePWM) Outputs
• Dedicated 16-Bit Time-Based Counter With
Period and Frequency Control
• Single-Edge, Dual-Edge Symmetric, or
Dual-Edge Asymmetric Outputs
• Dead-Band Generation
• PWM Chopping by High-Frequency Carrier
• Trip Zone Input
• Up to 9 HRPWM Outputs With 55-ps MEP
Resolution at VDD = 1.1 V (65 ps at 1.2 V)
•
•
•
•
•
•
•
– Six 32-Bit Enhanced Capture (eCAP) Modules
• Configurable as 3 Capture Inputs or
3 Auxiliary Pulse Width Modulator Outputs
• Single-Shot Capture of up to Four Event
Timestamps
– Three 32-Bit Quadrature Encoder Pulse (QEP)
Modules
– Six 32-Bit Timers and Nine 16-Bit Timers
Three 32-Bit CPU Timers
Serial Port Peripherals
– Up to 2 CAN Modules
– Up to 3 SCI (UART) Modules
– Up to 2 McBSP Modules (Configurable as SPI)
– Up to 2 SPI Modules
– One Inter-Integrated Circuit (I2C) Bus
External ADC Interface
Up to 88 Individually Programmable, Multiplexed
GPIO Pins With Input Filtering
Advanced Emulation Features
– Analysis and Breakpoint Functions
– Real-Time Debug Using Hardware
Package Options:
– 256-Ball Plastic Ball Grid Array (BGA) (ZFE)
– 179-Ball MicroStar BGA™ (ZHH)
Temperature Options:
– T: –40°C to 105°C (ZFE, ZHH)
– S: –40°C to 125°C (ZFE)
– Q: –40°C to 125°C (ZFE)
(AEC Q100 Qualification for Automotive
Applications)
2 Applications
•
•
•
•
•
•
Industrial AC Inverter Drives
Industrial Servo Amplifiers and Controllers
Computer Numerical Control (CNC) Machining
Uninterruptible and Server Power Supplies
Telecom Equipment Power
Solar Inverters
3 Description
The TMS320C2834x (C2834x) Delfino™ microcontroller unit (MCU) devices build on TI's existing F2833x highperformance floating-point microcontrollers. The C2834x delivers up to 300 MHz of floating-point performance,
and has up to 516KB of on-chip RAM. Designed for real-time control applications, the C2834x is based on the
C28x core, making it code-compatible with all C28x microcontrollers. The on-chip peripherals and low-latency
core make the C2834x an excellent solution for performance-hungry real-time control applications.
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2021 Texas Instruments
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Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
1
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
www.ti.com
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
The TMS320C28346, TMS320C28345, TMS320C28344, TMS320C28343, TMS320C28342, and
TMS320C28341 devices, members of the Delfino™ MCU generation, are highly integrated, high-performance
solutions for demanding control applications.
Throughout this document, the devices are abbreviated as C28346, C28345, C28344, C28343, C28342, and
C28341, respectively. Device Comparison provides a summary of features for each device.
Device Information (1)
PACKAGE
BODY SIZE
TMS320C28346ZFE
PART NUMBER
BGA (256)
17.0 mm × 17.0 mm
TMS320C28345ZFE
BGA (256)
17.0 mm × 17.0 mm
TMS320C28344ZFE
BGA (256)
17.0 mm × 17.0 mm
TMS320C28343ZFE
BGA (256)
17.0 mm × 17.0 mm
TMS320C28342ZFE
BGA (256)
17.0 mm × 17.0 mm
TMS320C28341ZFE
BGA (256)
17.0 mm × 17.0 mm
TMS320C28346ZEP
BGA (256)
17.0 mm × 17.0 mm
TMS320C28345ZEP
BGA (256)
17.0 mm × 17.0 mm
TMS320C28344ZEP
BGA (256)
17.0 mm × 17.0 mm
TMS320C28343ZEP
BGA (256)
17.0 mm × 17.0 mm
TMS320C28342ZEP
BGA (256)
17.0 mm × 17.0 mm
TMS320C28341ZEP
BGA (256)
17.0 mm × 17.0 mm
TMS320C28345ZHH
BGA MicroStar (179)
12.0 mm × 12.0 mm
TMS320C28343ZHH
BGA MicroStar (179)
12.0 mm × 12.0 mm
TMS320C28341ZHH
BGA MicroStar (179)
12.0 mm × 12.0 mm
(1)
2
For more information on these devices, see Mechanical, Packaging, and Orderable Information.
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Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
www.ti.com
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
DMA Bus
3.1 Functional Block Diagram
L0 SARAM 8K x 16
(0-Wait)
M1 SARAM 1K x 16
(0-Wait)
L1 SARAM 8K x 16
(0-Wait)
H0 SARAM 32K x 16
(1 Wait, Prefetch)
L2 SARAM 8K x 16
(0-Wait)
H1 SARAM 32K x 16
(1 Wait, Prefetch)
L3 SARAM 8K x 16
(0-Wait)
H2 SARAM 32K x 16
(1 Wait, Prefetch)
L4 SARAM 8K x 16
(0-Wait)
H3 SARAM 32K x 16
(1 Wait, Prefetch)
L5 SARAM 8K x 16
(0-Wait)
H4 SARAM 32K x 16
(1 Wait, Prefetch)
L6 SARAM 8K x 16
(1-Wait)
H5 SARAM 32K x 16
(1 Wait, Prefetch)
Memory Bus
M0 SARAM 1K x 16
(0-Wait)
Boot ROM
8K x 16
L7 SARAM 8K x 16
(1-Wait)
Memory Bus
XD31:0
FPU
TCK
XHOLDA
TDI
XHOLD
TMS
XREADY
XZCS0
EMU0
EMU1
XWE0
XA19:1
XCLKOUT
DMA Bus
Memory Bus
XZCS6
XCLKIN
CPU Timer 0
DMA
6 Ch
CPU Timer 1
Memory Bus
EXTADCCLK
ADC
SoC
DMA Bus
32-Bit Peripheral Bus
(DMA accessible)
16-Bit Peripheral Bus
FIFO
(16 Levels)
ePWM-1/../9
eCAP-1/../6
eQEP-1/2/3
CAN-A/B
(32-mbox)
CANTXx
CANRXx
EQEPxI
EQEPxS
EQEPxB
EQEPxA
ESYNCI
ESYNCO
EPWMxB
TZx
EPWMxA
MFSRx
MFSXx
MCLKRx
MRXx
MCLKXx
HRPWM-1/../9
MDXx
SCLx
SDAx
I2C
SPISTEx
SPICLKx
SPISIMOx
SCIRXDx
SPISOMIx
SPI-A/D
ECAPx
FIFO
(16 Levels)
32-Bit Peripheral Bus
McBSP-A/B
SCITXDx
XRS
8 External Interrupts
GPIO
MUX
SCI-A/B/C
X1
X2
PIE
(Interrupts)
XWE1
FIFO
(16 Levels)
OSC,
PLL,
LPM,
WD
CPU Timer 2
XRD
EXTSOC
TRST
XINTF
XZCS7
88 GPIOs
TDO
32-Bit CPU
(300 MHz @ 1.2 V
200 MHz @ 1.1 V)
XR/W
GPIO
MUX
88 GPIOs
GPIO MUX
88 GPIOs
Figure 3-1. Functional Block Diagram
Copyright © 2021 Texas Instruments Incorporated
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TMS320C28343-Q1 TMS320C28342 TMS320C28341
3
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
www.ti.com
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
3.1 Functional Block Diagram........................................... 3
4 Revision History.............................................................. 5
5 Device Comparison......................................................... 6
5.1 Related Products........................................................ 6
6 Terminal Configuration and Functions..........................8
6.1 Pin Diagrams.............................................................. 8
6.2 Signal Descriptions................................................... 16
7 Specifications................................................................ 29
7.1 Absolute Maximum Ratings (1) (2) .............................29
7.2 ESD Ratings – Automotive....................................... 29
7.3 ESD Ratings – Commercial...................................... 29
7.4 Recommended Operating Conditions.......................30
7.5 Power Consumption Summary................................. 31
7.6 Electrical Characteristics...........................................34
7.7 Thermal Resistance Characteristics......................... 35
7.8 Thermal Design Considerations................................36
7.9 Timing and Switching Characteristics....................... 37
8 Detailed Description......................................................86
8.1 Brief Descriptions......................................................86
4
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8.2 Peripherals................................................................92
8.3 Memory Maps......................................................... 130
8.4 Register Map...........................................................136
8.5 Interrupts.................................................................139
8.6 System Control....................................................... 144
8.7 Low-Power Modes Block........................................ 151
9 Applications, Implementation, and Layout............... 152
9.1 TI Design or Reference Design...............................152
10 Device and Documentation Support........................153
10.1 Getting Started......................................................153
10.2 Device and Development Support Tool
Nomenclature............................................................ 153
10.3 Tools and Software............................................... 155
10.4 Documentation Support........................................ 156
10.5 Support Resources............................................... 158
10.6 Trademarks........................................................... 158
10.7 Electrostatic Discharge Caution............................158
10.8 Glossary................................................................159
11 Mechanical, Packaging, and Orderable
Information.................................................................. 160
11.1 Packaging Information.......................................... 160
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
www.ti.com
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
4 Revision History
Changes from August 22, 2018 to February 1, 2021 (from Revision E (August 2018) to Revision
F (February 2021))
Page
• Added Q1 Part Numbers................................................................................................................................ 0
• Table 5-1: Added Q1 Part Numbers....................................................................................................................6
• Section 7.9.4.5.1.1 (SPI Master Mode External Timing (Clock Phase = 0)): Updated MIN value (for both BRR
EVEN and BRR ODD) for Parameter 23, td(SPC)M............................................................................................ 56
• Section 7.9.4.5.1.2 (SPI Master Mode External Timing (Clock Phase = 1)): Updated MIN value (for both BRR
EVEN and BRR ODD) for Parameter 23, td(SPC)M............................................................................................ 58
• Figure 10-1: Added GPN information............................................................................................................. 153
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TMS320C28343-Q1 TMS320C28342 TMS320C28341
5
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
www.ti.com
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
5 Device Comparison
Table 5-1. Device Comparison
TYPE(1)
C28346
C28346-Q1
(300 MHz)
Package type
–
256-ball ZFE
BGA(2)
Instruction cycle
–
3.33 ns
5 ns
3.33 ns
5 ns
3.33 ns
5 ns
Floating-point unit
–
Yes
Yes
Yes
Yes
Yes
Yes
Single-access RAM (SARAM)
(16-bit word)
–
258K
258K
130K
130K
98K
98K
Code security for on-chip SARAM
blocks
–
No
No
No
No
No
No
Boot ROM (8K ×16)
–
Yes
Yes
Yes
Yes
Yes
Yes
16-/32-bit External Interface
(XINTF)
1
Yes
Yes
Yes
Yes
Yes
Yes
6-channel Direct Memory Access
(DMA)
0
Yes
Yes
Yes
Yes
Yes
Yes
PWM channels
0
ePWM1/2/3/
4/5/6/7/8/9
ePWM1/2/3/
4/5/6/7/8/9
ePWM1/2/3/
4/5/6/7/8/9
ePWM1/2/3/
4/5/6/7/8/9
ePWM1/2/3/
4/5/6
ePWM1/2/3/
4/5/6
HRPWM channels
0
ePWM1A/2A/
3A/4A/5A/6A/
7A/8A/9A
ePWM1A/2A/
3A/4A/5A/6A/
7A/8A/9A
ePWM1A/2A/
3A/4A/5A/6A/
7A/8A/9A
ePWM1A/2A/
3A/4A/5A/6A/
7A/8A/9A
ePWM1A/2A/
3A/4A/5A/6A
ePWM1A/2A/
3A/4A/5A/6A
32-bit capture inputs or auxiliary
PWM outputs
0
6
6
6
6
4
4
32-bit QEP channels (four inputs/
channel)
0
3
3
3
3
2
2
Watchdog timer
–
Yes
Yes
Yes
Yes
Yes
Yes
External ADC interface
–
Yes
Yes
Yes
Yes
Yes
Yes
32-bit CPU timers
–
3
3
3
3
3
3
Multichannel Buffered Serial Port
(McBSP)/SPI
1
2
2
2
2
1
1
Serial Peripheral Interface (SPI)
0
2
2
2
2
2
2
Serial Communications Interface
(SCI)
0
3
3
3
3
3
3
Enhanced Controller Area
Network (eCAN)
0
2
2
2
2
2
2
Inter-Integrated Circuit (I2C)
0
1
1
1
1
1
1
General-Purpose Input/Output
(GPIO) pins (shared)
–
88
88
88
88
88
88
External interrupts
8
8
8
8
8
FEATURE
Temperature
options
(1)
(2)
C28345
(200 MHz)
256-ball ZFE
BGA(2)
C28344
(300 MHz)
179-ball ZHH
BGA
256-ball ZFE
BGA(2)
C28343
C28343-Q1
(200 MHz)
256-ball ZFE
BGA(2)
C28342
(300 MHz)
179-ball ZHH
BGA
256-ball ZFE
BGA(2)
C28341
(200 MHz)
256-ball ZFE
BGA(2)
179-ball ZHH
BGA
–
8
T: –40°C to
105°C
–
ZFE
ZFE
ZHH
ZFE
ZFE
ZHH
ZFE
ZFE
ZHH
S: –40°C to
125°C
–
ZFE
ZFE
–
ZFE
ZFE
–
ZFE
ZFE
–
Q: –40°C to
125°C
(AEC Q100
qualification)
–
ZFE
ZFE
–
ZFE
ZFE
–
ZFE
ZFE
–
A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
C2000 Real-Time Control Peripherals Reference Guide and in the peripheral reference guides.
TMX samples will come with the ZEP designator. The designator will change to ZFE after TMS.
5.1 Related Products
For information about other devices in the Delfino family of products, see the following links:
Original Delfino™ series:
TMS320F2833x Delfino™ Microcontrollers
The F2833x series is the original Delfino MCU. It is the first C2000™ MCU that is offered with a floating-point unit
(FPU). It has the first-generation ePWM timers that are used throughout the rest of the Delfino and Piccolo™
families. The 12.5-MSPS, 12-bit ADC is still class-leading for an integrated analog-to-digital converter. The
6
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TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
www.ti.com
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
F2833x has a 150-MHz CPU and up to 512KB of on-chip Flash. It is available in a 176-pin QFP or 179-ball BGA
package.
TMS320C2834x Delfino™ Microcontrollers
The C2834x series removes the on-chip Flash memory and integrated ADC to enable the fastest available clock
speeds of up to 300 MHz. It is available in a 179-ball BGA or 256-ball BGA package.
Newest Delfino™ series:
TMS320F2837xD Delfino™ Microcontrollers
The F2837xD series sets a new standard for performance with dual subsystems. Each subsystem consists of a
C28x CPU and a parallel control law accelerator (CLA), each running at 200 MHz. Enhancing performance are
TMU and VCU accelerators. New capabilities include multiple 16-bit/12-bit mode ADCs, DAC, Sigma-Delta
filters, USB, configurable logic block (CLB), on-chip oscillators, and enhanced versions of all peripherals. The
F2837xD is available with up to 1MB of Flash. It is available in a 176-pin QFP or 337-pin BGA package.
TMS320F2837xS Delfino™ Microcontrollers
The F2837xS series is a pin-to-pin compatible version of F2837xD but with only one C28x-CPU-and-CLA
subsystem enabled. It is also available in a 100-pin QFP to enable compatibility with the Piccolo™
TMS320F2807x series.
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7
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
6 Terminal Configuration and Functions
6.1 Pin Diagrams
The 179-ball ZHH ball grid array (BGA) terminal assignments are shown in Figure 6-1 through Figure 6-4. The
256-ball ZFE plastic BGA terminal assignments are shown in Figure 6-5 through Figure 6-8. Table 6-1 describes
the function(s) of each pin.
2
3
4
5
6
7
EXTSOC3B
GPIO19/
SPISTEA/
SCIRXDB/
CANTXA
GPIO23/
EQEP1I/
MFSXA/
SCIRXDB
GPIO24/
ECAP1/
EQEP2A/
MDXB
GPIO32/
SDAA/
EPWMSYNCI/
ADCSOCAO
VDD
P
EXTADCCLK
GPIO22/
EQEP1S/
MCLKXA/
SCITXDB
VDD
GPIO33/
SCLA/
EPWMSYNCO/
ADCSOCBO
TDO
N
GPIO25/
ECAP2/
EQEP2B/
MDRB
GPIO27/
ECAP4/
EQEP2S/
MFSXB
TRST
M
1
P
N
EXTSOC2B
EXTSOC1A
EXTSOC3A
M
VDD
EXTSOC2A
EXTSOC1B
GPIO21/
EQEP1B/
MDRA/
CANRXB
L
GPIO18/
SPICLKA/
SCITXDB/
CANRXA
VDDIO
VSS
GPIO20/
EQEP1A/
MDXA/
CANTXB
VSS
TDI
VSS
L
K
VSS
GPIO15/
TZ4/XHOLDA/
SCIRXDB/
MFSXB
VDD
GPIO16/
SPISIMOA/
CANTXB/
TZ5
VDDIO
GPIO26/
ECAP3/
EQEP2I/
MCLKXB
VDDIO
K
6
7
J
H
J
VDDIO
VSS
VDD
VDD
GPIO17/
SPISOMIA/
CANRXB/
TZ6
H
VSS
GPIO12/
TZ1/
CANTXB/
MDXB
GPIO11/
EPWM6B/
SCIRXDB/
ECAP4
GPIO13/
TZ2/
CANRXB/
MDRB
GPIO14/
TZ3/XHOLD/
SCITXDB/
MCLKXB
1
2
3
4
5
Figure 6-1. C2834x 179-Ball ZHH MicroStar BGA Upper-Left Quadrant (Bottom VIew)
8
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TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
www.ti.com
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
P
8
9
10
11
12
13
14
XRS
TCK
GPIO49/
ECAP6/
XD30/
SPISOMID
VDDIO
GPIO54/
SPISIMOA/
XD25/
EQEP3A
GPIO56/
SPICLKA/
XD23/
EQEP3S
GPIO58/
MCLKRA/
XD21/
EPWM7A
P
GPIO50/
EQEP1A/
XD29/
SPICLKD
GPIO51/
EQEP1B/
XD28/
SPISTED
GPIO55/
SPISOMIA/
XD24/
EQEP3B
GPIO57/
SPISTEA/
XD22/
EQEP3I
VDD
N
N
XRSIO
EMU0
M
TMS
VSS
GPIO48/
ECAP5/
XD31/
SPISIMOD
GPIO52/
EQEP1S/
XD27
VSS
GPIO59/
MFSRA/
XD20/
EPWM7B
GPIO60/
MCLKRB/
XD19/
EPWM8A
M
L
VSS
EMU1
VDD
GPIO53/
EQEP1I/
XD26
GPIO61/
MFSRB/
XD18/
EPWM8B
GPIO62/
SCIRXDC/
XD17/
EPWM9A
VDDIO
L
K
VDDIO
VDD
VSS
VDD
GPIO64/
XD15
GPIO63/
SCITXDC/
XD16/
EPWM9B
GPIO65/
XD14
K
8
9
J
VSS
GPIO66/
XD13
GPIO67/
XD12
GPIO68/
XD11
VDDIO
J
H
VSS
VDD
GPIO70/
XD9
GPIO69/
XD10
VDD
H
10
11
12
13
14
Figure 6-2. C2834x 179-Ball ZHH MicroStar BGA Upper-Right Quadrant (Bottom View)
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1
2
3
4
5
G
VDD
GPIO9/
EPWM5B/
SCITXDB/
ECAP3
GPIO10/
EPWM6A/
CANRXB/
ADCSOCBO
GPIO8/
EPWM5A/
CANTXB/
ADCSOCAO
VSS
G
F
VDDIO
GPIO7/
EPWM4B/
MCLKRA/
ECAP2
GPIO6/
EPWM4A/
EPWMSYNCI/
EPWMSYNCO
VSS
GPIO2/
EPWM2A
F
E
VDD
GPIO4/
EPWM3A
GPIO5/
EPWM3B/
MFSRA/
ECAP1
GPIO3/
EPWM2B/
ECAP5/
MCLKRB
D
VDD
VSS
VDDIO
C
GPIO1/
EPWM1B/
ECAP6/
MFSRB
GPIO30/
CANRXA/
XA18
GPIO29/
SCITXDA/
XA19
B
GPIO0/
EPWM1A
GPIO31/
CANTXA/
XA17
A
6
7
VDD
GPIO80/
XA8
GPIO46/
XA6
E
GPIO85/
XA13
GPIO84/
XA12
GPIO47/
XA7
VDDIO
D
VDD
GPIO81/
XA9
VDD
VDD18
C
GPIO87/
XA15
VDDIO
GPIO83/
XA11
VDDIO
VDD
B
GPIO39/
XA16
GPIO86/
XA14
VSS
GPIO82/
XA10
VSS
VSS
A
2
3
4
5
6
7
1
Figure 6-3. C2834x 179-Ball ZHH MicroStar BGA Lower-Left Quadrant (Bottom View)
10
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
10
11
12
13
14
G
VDD
VSS
GPIO71/
XD8
GPIO72/
XD7
VSS
G
F
GPIO78/
XD1
VDDIO
GPIO75/
XD4
GPIO74/
XD5
GPIO73/
XD6
F
8
9
E
VDD18
VSS
GPIO40/
XA0
GPIO77/
XD2
VDD
GPIO76/
XD3
VSS
E
D
VSS
XCLKIN
GPIO41/
XA1
GPIO37/
ECAP2/
XZCS7
VDD
VSS
VDDIO
D
C
X1
VDDIO
VDD
VDD
GPIO38/
XWE0
XWE1
GPIO79/
XD0
C
B
VSSK
GPIO45/
XA5
GPIO42/
XA2
VSS
GPIO36/
SCIRXDA/
XZCS0
GPIO35/
SCITXDA/
XR/W
XCLKOUT
B
A
X2
GPIO44/
XA4
GPIO43/
XA3
VDDIO
GPIO28/
SCIRXDA/
XZCS6
GPIO34/
ECAP1
XREADY
XRD
A
8
9
10
11
12
13
14
Figure 6-4. C2834x 179-Ball ZHH MicroStar BGA Lower-Right Quadrant (Bottom View)
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
1
T
VSS
2
VSS
3
4
5
6
7
8
VDDIO
GPIO19/
SPISTEA/
SCIRXDB/
CANTXA
GPIO21/
EQEP1B/
MDRA/
CANRXB
GPIO24/
ECAP1/
EQEP2A/
MDXB
GPIO27/
ECAP4/
EQEP2S/
MFSXB
TDI
GPIO22/
EQEP1S/
MCLKXA/
SCITXDB
GPIO25/
ECAP2/
EQEP2B/
MDRB
GPIO32/
SDAA/
EPWMSYNCI/
ADCSOCAO
TRST
R
VSS
VSS
EXTADCCLK
GPIO20/
EQEP1A/
MDXA/
CANTXB
P
VDD
EXTSOC3B
VSS
VSS
GPIO23/
EQEP1I/
MFSXA/
SCIRXDB
GPIO26/
ECAP3/
EQEP2I/
MCLKXB
GPIO33/
SCLA/
EPWMSYNCO/
ADCSOCBO
TDO
N
EXTSOC2A EXTSOC2B EXTSOC3A
VSS
VDDIO
VDDIO
VSS
VDDIO
M
GPIO18/
SPICLKA/
EXTSOC1A EXTSOC1B
SCITXDB/
CANRXA
VDDIO
VSS
VDD
VDD
VDD
L
GPIO16/
GPIO17/
SPISIMOA/ SPISOMIA/
CANTXB/
CANRXB/
TZ5
TZ6
VDD
VDDIO
VDD
VSS
VSS
VSS
VSS
GPIO15/
TZ4/XHOLDA/
SCIRXDB/
MFSXB
VDD
VSS
VDD
VSS
VSS
VSS
VDDIO
GPIO13/
TZ2/
CANRXB/
MDRB
GPIO14/
TZ3/XHOLD/
SCITXDB/
MCLKXB
VDDIO
VDD
VSS
VSS
VSS
K
J
Figure 6-5. C2834x 256-Ball ZFE Plastic BGA Upper-Left Quadrant (Bottom View)
12
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
9
11
12
13
14
15
16
XRS
TCK
GPIO50/
EQEP1A/
XD29/
SPICLKD
GPIO53/
EQEP1I/
XD26
VDDIO
VSS
VSS
T
EMU1
GPIO48/
ECAP5/
XD31/
SPISIMOD
GPIO51/
EQEP1B/
XD28/
SPISTED
GPIO54/
SPISIMOA/
XD25/
EQEP3A
VSS
VSS
R
TMS
EMU0
GPIO49/
ECAP6/
XD30/
SPISOMID
GPIO52/
EQEP1S/
XD27
GPIO55/
SPISOMIA/
XD24/
EQEP3B
VSS
GPIO57/
SPISTEA/
XD22/
EQEP3I
VDD
P
VSS
VSS
VDDIO
VDDIO
VSS
VSS
GPIO59/
MFSRA/
XD20/
EPWM7B
GPIO61/
MFSRB/
XD18/
EPWM8B
GPIO60/
MCLKRB/
XD19/
EPWM8A
M
XRSIO
VDDIO
10
GPIO56/
SPICLKA/
XD23/
EQEP3S
GPIO58/
MCLKRA/
N
XD21/
EPWM7A
VDD
VDD
VDD
VSS
VDDIO
GPIO62/
SCIRXDC/
XD17/
EPWM9A
VSS
VSS
VSS
VDD
VDDIO
GPIO65/
XD14
GPIO64/
XD15
GPIO63/
SCITXDC/
XD16/
EPWM9B
L
VSS
VSS
VSS
VDD
VSS
GPIO67/
XD12
GPIO66/
XD13
VSS
K
VSS
VSS
VSS
VDD
VDDIO
GPIO68/
XD11
VDDIO
J
GPIO69/
XD10
Figure 6-6. C2834x 256-Ball ZFE Plastic BGA Upper-Right Quadrant (Bottom View)
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
H
GPIO10/
GPIO11/
EPWM6A/ EPWM6B/
CANRXB/ SCIRXDB/
ADCSOCBO ECAP4
G
GPIO7/
EPWM4B/
MCLKRA/
ECAP2
F
GPIO4/
EPWM3A
GPIO5/
GPIO6/
EPWM3B/
EPWM4A/
MFSRA/ EPWMSYNCI/
ECAP1
EPWMSYNCO
E
GPIO1/
EPWM1B/
ECAP6/
MFSRB
GPIO2/
EPWM2A
D
GPIO29/
SCITXDA/
XA19
C
GPIO12/
TZ1/
CANTXB/
MDXB
VSS
VDD
VSS
VSS
VSS
GPIO9/
GPIO8/
EPWM5B/
EPWM5A/
SCITXDB/
CANTXB/
ECAP3
ADCSOCAO
VSS
VDD
VSS
VSS
VSS
VDDIO
VDD
VSS
VSS
VSS
GPIO3/
EPWM2B/
ECAP5/
MCLKRB
VDDIO
VSS
VDD
VDD
VDD
GPIO0/
EPWM1A
VSS
VSS
VDDIO
VDDIO
VSS
VDDIO
VDD
GPIO30/
CANRXA/
XA18
VSS
VSS
GPIO86/
XA14
GPIO83/
XA11
GPIO81/
XA9
GPIO47/
XA7
B
VSS
VSS
GPIO31/
CANTXA/
XA17
GPIO39/
XA16
GPIO85/
XA13
GPIO82/
XA10
GPIO80/
XA8
GPIO46/
XA6
A
VSS
VSS
VDDIO
GPIO87/
XA15
GPIO84/
XA12
VDD18
X1
1
2
3
4
5
6
7
VSSK
8
Figure 6-7. C2834x 256-Ball ZFE Plastic BGA Lower-Left Quadrant (Bottom View)
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
VSS
VSS
VDD
VSS
GPIO72/
XD7
GPIO71/
XD8
GPIO70/
XD9
H
VSS
VSS
VDD
VSS
GPIO75/
XD4
GPIO74/
XD5
GPIO73/
XD6
G
VSS
VSS
VSS
VDD
VDDIO
GPIO78/
XD1
GPIO77/
XD2
GPIO76/
XD3
F
VDD
VDD
VDD
VSS
VDDIO
XWE1
GPIO38/
XWE0
GPIO79/
XD0
E
VSS
VSS
VDDIO
VDDIO
VSS
VSS
XRD
XCLKOUT
D
GPIO45/
XA5
GPIO44/
XA4
GPIO42/
XA2
GPIO40/
XA0
VSS
VSS
GPIO35/
SCITXDA/
XR/W
VDD
C
VDDIO
GPIO43/
XA3
GPIO41/
XA1
GPIO37/
ECAP2/
XZCS7
GPIO28/
SCIRXDA/
XZCS6
GPIO34/
ECAP1/
XREADY
VSS
VSS
B
X2
VSS
VDD18
XCLKIN
GPIO36/
SCIRXDA/
XZCS0
VDDIO
VSS
VSS
A
9
10
11
12
13
14
15
16
VSS
VSS
Figure 6-8. C2834x 256-Ball ZFE Plastic BGA Lower-Right Quadrant (Bottom View)
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
6.2 Signal Descriptions
Table 6-1 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral
signals that are listed under them are alternate functions. Some peripheral functions may not be available in all
devices. See Table 5-1 for details. Inputs are not 5-V tolerant. All XINTF pins have a drive strength of 4 mA
(typical). All GPIO pins are I/O/Z, 4-mA drive typical and have an internal pullup, which can be selectively
enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on GPIO0–
GPIO11 and GPIO58–GPIO63 pins are not enabled at reset. The pullups on GPIO12–GPIO57 and GPIO64–
GPIO87 are enabled upon reset.
Table 6-1. Signal Descriptions
NAME
ZHH
BALL #
ZFE
BALL #
DESCRIPTION
JTAG
TRST
M7
R8
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of
the operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during normal
device operation. An external pulldown resistor is recommended on this pin. The value of this
resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ
resistor generally offers adequate protection. Because this is application-specific, TI recommends
validating each target board for proper operation of the debugger and the application. (I, ↓)
TCK
P9
T11
JTAG test clock. An external pullup resistor is required on this pin. A 2.2-kΩ resistor generally offers
adequate protection.(I)
TMS
M8
P9
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. (I, ↑)
TDI
L6
T8
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
or data) on a rising edge of TCK. (I, ↑)
TDO
N7
P8
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)
are shifted out of TDO on the falling edge of TCK.
P10
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Because this is application-specific, TI recommends validating each
each target board for proper operation of the debugger and the application.
R10
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Because this is application-specific, TI recommends validating each
target board for proper operation of the debugger and the application.
EMU0
EMU1
N9
L9
Clock
XCLKOUT
B14
D16
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, one-fourth the frequency, or one-eighth the frequency of SYSCLKOUT. This is controlled
by bit 19 (BY4CLKMODE), bits 18:16 (XTIMCLK), and bit 2 (CLKMODE) in the XINTCNF2 register.
At reset, XCLKOUT = SYSCLKOUT/8. The XCLKOUT signal can be turned off by setting
XINTCNF2[CLKOFF] to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in highimpedance state during a reset.
XCLKIN
D9
A12
External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case,
the X1 pin must be tied to VSSK. If a crystal/resonator is used (or if an external 1.8-V oscillator is
used to feed clock to X1 pin), this pin must be tied to VSS. (I)
A7
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal may be connected
across X1 and X2. The X1 pin is referenced to the 1.8-V core digital power supply. A 1.8-V external
oscillator may be connected to the X1 pin. In this case, the XCLKIN pin must be connected to VSS.
If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to VSSK. (I)
X1
16
C8
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
NAME
X2
ZHH
BALL #
ZFE
BALL #
DESCRIPTION
A8
A9
Internal Oscillator Output. A quartz crystal may be connected across X1 and X2. If X2 is not used it
must be left unconnected. (O)
Reset
XRS
P8
T10
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
location pointed to by the PC. This pin is driven low by the MCU when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑)
The output buffer of this pin is an open drain with an internal pullup. It is recommended that this pin
be driven by an open-drain device.
XRSIO
N8
T9
XRS I/O Control (I) - This pin must be connected to the XRS pin on the target board. When XRS is
low (reset), the level detected on this pin puts all output buffers on the device in high-impedance
mode.
N1
M2
External ADC SOC Group 1 A Output. Trigger for external ADC, this signal is logical OR of
ePWM1/2/3 SOCA internal signals (O)
M3
M3
External ADC SOC Group 1 B Output. Trigger for external ADC, this signal is logical OR of
ePWM1/2/3 SOCB internal signals (O)
M2
N1
External ADC SOC Group 2 A Output. Trigger for external ADC, this signal is logical OR of
ePWM4/5/6 SOCA internal signals (O)
P1
N2
External ADC SOC Group 2 B Output. Trigger for external ADC, this signal is logical OR of
ePWM4/5/6 SOCB internal signals (O)
N2
N3
External ADC SOC Group 3 A Output. Trigger for external ADC, this signal is logical OR of
ePWM7/8/9 SOCA internal signals (O)
P2
P2
External ADC SOC Group3 B Output. Trigger for external ADC, this signal is logical OR of
ePWM7/8/9 SOCB internal signals (O)
N3
R3
External ADC Clock Signal. Clock for external ADC support, derived from SYSCLK (O)
D2
General-purpose input/output 0 (I/O/Z)
Enhanced PWM1 Output A and HRPWM channel (O)
-
External ADC Interface Signals
EXTSOC1A
EXTSOC1B
EXTSOC2A
EXTSOC2B
EXTSOC3A
EXTSOC3B
EXTADCCLK
GPIO and Peripheral Signals
GPIO0
EPWM1A
-
B1
GPIO1
EPWM1B
ECAP6
MFSRB
C1
E1
General-purpose input/output 1 (I/O/Z)
Enhanced PWM1 Output B (O)
Enhanced Capture 6 input/output (I/O)
McBSP-B receive frame synch (I/O)
GPIO2
EPWM2A
-
F5
E2
General-purpose input/output 2 (I/O/Z)
Enhanced PWM2 Output A and HRPWM channel (O)
-
GPIO3
EPWM2B
ECAP5
MCLKRB
E4
E3
General-purpose input/output 3 (I/O/Z)
Enhanced PWM2 Output B (O)
Enhanced Capture 5 input/output (I/O)
McBSP-B receive clock (I/O)
F1
General-purpose input/output 4 (I/O/Z)
Enhanced PWM3 output A and HRPWM channel (O)
-
F2
General-purpose input/output 5 (I/O/Z)
Enhanced PWM3 output B (O)
McBSP-A receive frame synch (I/O)
Enhanced Capture input/output 1 (I/O)
GPIO4
EPWM3A
GPIO5
EPWM3B
MFSRA
ECAP1
E2
E3
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
NAME
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO
GPIO7
EPWM4B
MCLKRA
ECAP2
ZHH
BALL #
ZFE
BALL #
F3
F3
General-purpose input/output 6 (I/O/Z)
Enhanced PWM4 output A and HRPWM channel (O)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
G1
General-purpose input/output 7 (I/O/Z)
Enhanced PWM4 output B (O)
McBSP-A receive clock (I/O)
Enhanced capture input/output 2 (I/O)
F2
DESCRIPTION
GPIO8
EPWM5A
CANTXB
ADCSOCAO
G4
G2
General-purpose input/output 8 (I/O/Z)
Enhanced PWM5 output A and HRPWM channel (O)
Enhanced CAN-B transmit (O)
ADC start-of-conversion A (O)
GPIO9
EPWM5B
SCITXDB
ECAP3
G2
G3
General-purpose input/output 9 (I/O/Z)
Enhanced PWM5 output B (O)
SCI-B transmit data(O)
Enhanced capture input/output 3 (I/O)
GPIO10
EPWM6A
CANRXB
ADCSOCBO
G3
H1
General-purpose input/output 10 (I/O/Z)
Enhanced PWM6 output A and HRPWM channel (O)
Enhanced CAN-B receive (I)
ADC start-of-conversion B (O)
GPIO11
EPWM6B
SCIRXDB
ECAP4
H3
H2
General-purpose input/output 11 (I/O/Z)
Enhanced PWM6 output B (O)
SCI-B receive data (I)
Enhanced CAP Input/Output 4 (I/O)
GPIO12
TZ1
CANTXB
MDXB
H2
H3
General-purpose input/output 12 (I/O/Z)
Trip Zone input 1 (I)
Enhanced CAN-B transmit (O)
McBSP-B transmit serial data (O)
GPIO13
TZ2
CANRXB
MDRB
H4
J2
General-purpose input/output 13 (I/O/Z)
Trip Zone input 2 (I)
Enhanced CAN-B receive (I)
McBSP-B receive serial data (I)
GPIO14
General-purpose input/output 14 (I/O/Z)
TZ3/ XHOLD
Trip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external interface
(XINTF) to release the external bus and place all buses and strobes into a high-impedance state. To
prevent this from happening when TZ3 signal goes active, disable this function by writing
XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus will go into high impedance anytime TZ3
goes low. On the ePWM side, TZn signals are ignored by default, unless they are enabled by the
code. The XINTF will release the bus when any current access is complete and there are no
pending accesses on the XINTF. (I)
H5
J3
SCITXDB
MCLKXB
SCI-B Transmit (O)
McBSP-B transmit clock (I/O)
GPIO15
General-purpose input/output 15 (I/O/Z)
TZ4/ XHOLDA
Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on the
direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4 function is
chosen. If the pin is configured as an output, then XHOLDA function is chosen. XHOLDA is driven
active (low) when the XINTF has granted an XHOLD request. All XINTF buses and strobe signals
will be in a high-impedance state. XHOLDA is released when the XHOLD signal is released.
External devices should only drive the external bus when XHOLDA is active (low). (I/O)
K2
K2
SCIRXDB
MFSXB
SCI-B receive (I)
McBSP-B transmit frame synch (I/O)
GPIO16
SPISIMOA
CANTXB
TZ5
General-purpose input/output 16 (I/O/Z)
SPI slave in, master out (I/O)
Enhanced CAN-B transmit (O)
Trip Zone input 5 (I)
18
K4
L1
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
NAME
GPIO17
SPISOMIA
CANRXB
TZ6
GPIO18
SPICLKA
SCITXDB
CANRXA
ZHH
BALL #
ZFE
BALL #
J5
L2
General-purpose input/output 17 (I/O/Z)
SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (I)
Trip zone input 6 (I)
M1
General-purpose input/output 18 (I/O/Z)
SPI-A clock input/output (I/O)
SCI-B transmit (O)
Enhanced CAN-A receive (I)
L1
DESCRIPTION
GPIO19
SPISTEA
SCIRXDB
CANTXA
P3
T4
General-purpose input/output 19 (I/O/Z)
SPI-A slave transmit enable input/output (I/O)
SCI-B receive (I)
Enhanced CAN-A transmit (O)
GPIO20
EQEP1A
MDXA
CANTXB
L4
R4
General-purpose input/output 20 (I/O/Z)
Enhanced QEP1 input A (I)
McBSP-A transmit serial data (O)
Enhanced CAN-B transmit (O)
GPIO21
EQEP1B
MDRA
CANRXB
M4
T5
General-purpose input/output 21 (I/O/Z)
Enhanced QEP1 input B (I)
McBSP-A receive serial data (I)
Enhanced CAN-B receive (I)
GPIO22
EQEP1S
MCLKXA
SCITXDB
N4
R5
General-purpose input/output 22 (I/O/Z)
Enhanced QEP1 strobe (I/O)
McBSP-A transmit clock (I/O)
SCI-B transmit (O)
GPIO23
EQEP1I
MFSXA
SCIRXDB
P4
P5
General-purpose input/output 23 (I/O/Z)
Enhanced QEP1 index (I/O)
McBSP-A transmit frame synch (I/O)
SCI-B receive (I)
GPIO24
ECAP1
EQEP2A
MDXB
P5
T6
General-purpose input/output 24 (I/O/Z)
Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I)
McBSP-B transmit serial data (O)
R6
General-purpose input/output 25 (I/O/Z)
Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I)
McBSP-B receive serial data (I)
GPIO25
ECAP2
EQEP2B
MDRB
M5
GPIO26
ECAP3
EQEP2I
MCLKXB
K6
P6
General-purpose input/output 26 (I/O/Z)
Enhanced capture 3 (I/O)
Enhanced QEP2 index (I/O)
McBSP-B transmit clock (I/O)
GPIO27
ECAP4
EQEP2S
MFSXB
M6
T7
General-purpose input/output 27 (I/O/Z)
Enhanced capture 4 (I/O)
Enhanced QEP2 strobe (I/O)
McBSP-B transmit frame synch (I/O)
GPIO28
SCIRXDA
XZCS6
A12
B13
General-purpose input/output 28 (I/O/Z)
SCI receive data (I)
External Interface zone 6 chip select (O)
GPIO29
SCITXDA
XA19
C3
D1
General-purpose input/output 29. (I/O/Z)
SCI transmit data (O)
External Interface Address Line 19 (O)
GPIO30
CANRXA
XA18
C2
C2
General-purpose input/output 30 (I/O/Z)
Enhanced CAN-A receive (I)
External Interface Address Line 18 (O)
GPIO31
CANTXA
XA17
B2
B3
General-purpose input/output 31 (I/O/Z)
Enhanced CAN-A transmit (O)
External Interface Address Line 17 (O)
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
NAME
GPIO32
SDAA
EPWMSYNCI
ADCSOCAO
ZHH
BALL #
ZFE
BALL #
P6
R7
General-purpose input/output 32 (I/O/Z)
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion A (O)
DESCRIPTION
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO
N6
P7
General-purpose input/output 33 (I/O/Z)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion B (O)
GPIO34
ECAP1
XREADY
A13
B14
General-purpose input/output 34 (I/O/Z)
Enhanced Capture input/output 1 (I/O)
External Interface Ready signal
GPIO35
SCITXDA
XR/ W
B13
C15
General-purpose input/output 35 (I/O/Z)
SCI-A transmit data (O)
External Interface read, not write strobe
GPIO36
SCIRXDA
XZCS0
B12
A13
General-purpose input/output 36 (I/O/Z)
SCI-A receive data (I)
External Interface zone 0 chip select (O)
GPIO37
ECAP2
XZCS7
D11
B12
General-purpose input/output 37 (I/O/Z)
Enhanced Capture input/output 2 (I/O)
External Interface zone 7 chip select (O)
GPIO38
XWE0
C12
E15
General-purpose input/output 38 (I/O/Z)
External Interface Write Enable 0 (O). XWE0 defaults back to GPIO38 upon reset, during which
time it will be high-impedance.
GPIO39
XA16
A2
B4
General-purpose input/output 39 (I/O/Z)
External Interface Address Line 16 (O)
GPIO40
XA0
E10
C12
General-purpose input/output 40 (I/O/Z)
External Interface Address Line 0
GPIO41
XA1
D10
B11
General-purpose input/output 41 (I/O/Z)
External Interface Address Line 1 (O)
GPIO42
XA2
B10
C11
General-purpose input/output 42 (I/O/Z)
External Interface Address Line 2 (O)
GPIO43
XA3
A10
B10
General-purpose input/output 43 (I/O/Z)
External Interface Address Line 3 (O)
GPIO44
XA4
A9
C10
General-purpose input/output 44 (I/O/Z)
External Interface Address Line 4 (O)
GPIO45
XA5
B9
C9
General-purpose input/output 45 (I/O/Z)
External Interface Address Line 5 (O)
GPIO46
XA6
E7
B8
General-purpose input/output 46 (I/O/Z)
External Interface Address Line 6 (O)
GPIO47
XA7
D6
C8
General-purpose input/output 47 (I/O/Z)
External Interface Address Line 7 (O)
M10
R11
General-purpose input/output 48 (I/O/Z)
Enhanced Capture input/output 5 (I/O)
External Interface Data Line 31 (O)
SPI-D slave in, master out (I/O)
GPIO48
ECAP5
XD31
SPISIMOD
20
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TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
NAME
GPIO49
ECAP6
XD30
SPISOMID
GPIO50
EQEP1A
XD29
SPICLKD
ZHH
BALL #
ZFE
BALL #
P10
P11
General-purpose input/output 49 (I/O/Z)
Enhanced Capture input/output 6 (I/O)
External Interface Data Line 30 (O)
SPI-D slave out, master in (I/O)
T12
General-purpose input/output 50 (I/O/Z)
Enhanced QEP 1input A (I)
External Interface Data Line 29 (O)
SPI-D Clock input/output (I/O)
N10
DESCRIPTION
GPIO51
EQEP1B
XD28
SPISTED
N11
R12
General-purpose input/output 51 (I/O/Z)
Enhanced QEP 1input B (I)
External Interface Data Line 28 (O)
SPI-D slave transmit enable input/output (I/O)
GPIO52
EQEP1S
XD27
M11
P12
General-purpose input/output 52 (I/O/Z)
Enhanced QEP 1Strobe (I/O)
External Interface Data Line 27 (O)
GPIO53
EQEP1I
XD26
L11
T13
General-purpose input/output 53 (I/O/Z)
Enhanced QEP1 lndex (I/O)
External Interface Data Line 26 (O)
R13
General-purpose input/output 54 (I/O/Z)
SPI-A slave in, master out (I/O)
External Interface Data Line 25 (O)
Enhanced QEP3 input A (I)
GPIO54
SPISIMOA
XD25
EQEP3A
P12
GPIO55
SPISOMIA
XD24
EQEP3B
N12
P13
General-purpose input/output 55 (I/O/Z)
SPI-A slave out, master in (I/O)
External Interface Data Line 24 (O)
Enhanced QEP3 input B (I)
GPIO56
SPICLKA
XD23
EQEP3S
P13
R14
General-purpose input/output 56 (I/O/Z)
SPI-A clock (I/O)
External Interface Data Line 23 (O)
Enhanced QEP3 strobe (I/O)
P15
General-purpose input/output 57 (I/O/Z)
SPI-A slave transmit enable (I/O)
External Interface Data Line 22 (O)
Enhanced QEP3 index (I/O)
GPIO57
SPISTEA
XD22
EQEP3I
N13
GPIO58
MCLKRA
XD21
EPWM7A
P14
N16
General-purpose input/output 58 (I/O/Z)
McBSP-A receive clock (I/O)
External Interface Data Line 21 (O)
Enhanced PWM 7 output A and HRPWM channel (O)
GPIO59
MFSRA
XD20
EPWM7B
M13
N15
General-purpose input/output 59 (I/O/Z)
McBSP-A receive frame synch (I/O)
External Interface Data Line 20 (O)
Enhanced PWM 7 output B (O)
GPIO60
MCLKRB
XD19
EPWM8A
M14
M16
General-purpose input/output 60 (I/O/Z)
McBSP-B receive clock (I/O)
External Interface Data Line 19 (O)
Enhanced PWM 8 output A and HRPWM channel (O)
GPIO61
MFSRB
XD18
EPWM8B
L12
M15
General-purpose input/output 61 (I/O/Z)
McBSP-B receive frame synch (I/O)
External Interface Data Line 18 (O)
Enhanced PWM8 output B (O)
GPIO62
SCIRXDC
XD17
EPWM9A
L13
M14
General-purpose input/output 62 (I/O/Z)
SCI-C receive data (I)
External Interface Data Line 17 (O)
Enhanced PWM9 output A and HRPWM channel (O)
GPIO63
SCITXDC
XD16
EPWM9B
K13
L16
General-purpose input/output 63 (I/O/Z)
SCI-C transmit data (O)
External Interface Data Line 16 (O)
Enhanced PWM9 output B (O)
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
ZHH
BALL #
ZFE
BALL #
GPIO64
XD15
K12
L15
General-purpose input/output 64 (I/O/Z)
External Interface Data Line 15 (O)
GPIO65
XD14
K14
L14
General-purpose input/output 65 (I/O/Z)
External Interface Data Line 14 (O)
GPIO66
XD13
J11
K15
General-purpose input/output 66 (I/O/Z)
External Interface Data Line 13 (O)
GPIO67
XD12
J12
K14
General-purpose input/output 67 (I/O/Z)
External Interface Data Line 12 (O)
GPIO68
XD11
J13
J15
General-purpose input/output 68 (I/O/Z)
External Interface Data Line 11 (O)
GPIO69
XD10
H13
J14
General-purpose input/output 69 (I/O/Z)
External Interface Data Line 10 (O)
GPIO70
XD9
H12
H16
General-purpose input/output 70 (I/O/Z)
External Interface Data Line 9 (O)
GPIO71
XD8
G12
H15
General-purpose input/output 71 (I/O/Z)
External Interface Data Line 8 (O)
GPIO72
XD7
G13
H14
General-purpose input/output 72 (I/O/Z)
External Interface Data Line 7 (O)
GPIO73
XD6
F14
G16
General-purpose input/output 73 (I/O/Z)
External Interface Data Line 6 (O)
GPIO74
XD5
F13
G15
General-purpose input/output 74 (I/O/Z)
External Interface Data Line 5 (O)
GPIO75
XD4
F12
G14
General-purpose input/output 75 (I/O/Z)
External Interface Data Line 4 (O)
GPIO76
XD3
E13
F16
General-purpose input/output 76 (I/O/Z)
External Interface Data Line 3 (O)
GPIO77
XD2
E11
F15
General-purpose input/output 77 (I/O/Z)
External Interface Data Line 2 (O)
GPIO78
XD1
F10
F14
General-purpose input/output 78 (I/O/Z)
External Interface Data Line 1 (O)
GPIO79
XD0
C14
E16
General-purpose input/output 79 (I/O/Z)
External Interface Data Line 0 (O)
GPIO80
XA8
E6
B7
General-purpose input/output 80 (I/O/Z)
External Interface Address Line 8 (O)
GPIO81
XA9
C5
C7
General-purpose input/output 81 (I/O/Z)
External Interface Address Line 9 (O)
GPIO82
XA10
A5
B6
General-purpose input/output 82 (I/O/Z)
External Interface Address Line 10 (O)
NAME
22
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DESCRIPTION
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TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
www.ti.com
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
ZHH
BALL #
ZFE
BALL #
GPIO83
XA11
B5
C6
General-purpose input/output 83 (I/O/Z)
External Interface Address Line 11 (O)
GPIO84
XA12
D5
A5
General-purpose input/output 84 (I/O/Z)
External Interface Address Line 12 (O)
GPIO85
XA13
D4
B5
General-purpose input/output 85 (I/O/Z)
External Interface Address Line 13 (O)
GPIO86
XA14
A3
C5
General-purpose input/output 86 (I/O/Z)
External Interface Address Line 14 (O)
GPIO87
XA15
B3
A4
General-purpose input/output 87 (I/O/Z)
External Interface Address Line 15 (O)
XRD
A14
D15
External Interface Read Enable (O). The XRD pin is high-impedance on reset. It stays that way as
long as the XINTF clock is turned off (which happens on reset).
XWE1
C13
E14
External Memory Interface Write Enable for Upper 16-bits (O). The XWE1 pin is high-impedance on
reset. It stays that way as long as the XINTF clock is turned off (which happens on reset).
VDD18
E8
A6
VDD18
C7
A11
VSSK
B8
A8
NAME
DESCRIPTION
CPU and I/O Power Pins
Oscillator and PLL Power Pin (1.8 V)
Oscillator Kelvin Reference Ground. This pin should not be connected to Vss. See Figure 8-29
through Figure 8-31 for proper application board connections.
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
NAME
ZHH
BALL #
ZFE
BALL #
VDD
D1
C1
VDD
E1
C16
VDD
G1
E6
VDD
K3
E7
VDD
M1
E8
VDD
N5
E9
VDD
P7
E10
VDD
J3
E11
VDD
J4
F5
VDD
K9
F12
VDD
L10
G5
VDD
N14
G12
VDD
K11
H5
VDD
H11
H12
VDD
H14
J5
VDD
G10
J12
VDD
E12
K3
VDD
D12
K5
VDD
C11
K12
VDD
C10
L3
VDD
B7
L5
VDD
C6
L12
VDD
E5
M6
VDD
C4
M7
VDD
CPU and logic digital power pins (1.1 V/1.2 V)
M8
VDD
M9
VDD
M10
VDD
M11
VDD
P1
VDD
P16
VDDIO
D3
A3
VDDIO
F1
A14
VDDIO
J1
B9
VDDIO
L2
D5
VDDIO
K5
D6
VDDIO
K7
D8
VDDIO
K8
D11
VDDIO
P11
D12
VDDIO
L14
E4
24
DESCRIPTION
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Digital I/O power pins (3.3 V)
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TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
ZHH
BALL #
ZFE
BALL #
VDDIO
J14
E13
VDDIO
F11
F4
VDDIO
D14
F13
VDDIO
A11
J1
VDDIO
C9
J4
VDDIO
D7
J13
VDDIO
B6
J16
VDDIO
B4
L4
NAME
VDDIO
L13
VDDIO
M4
VDDIO
M13
VDDIO
N5
VDDIO
N6
VDDIO
N8
VDDIO
N11
VDDIO
N12
VDDIO
R9
VDDIO
T3
VDDIO
T14
DESCRIPTION
Digital I/O power pins
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
NAME
ZHH
BALL #
ZFE
BALL #
VSS
D2
A1
VSS
F4
A2
VSS
G5
A10
VSS
H1
A15
VSS
J2
A16
VSS
K1
B1
VSS
L3
B2
VSS
L5
B15
VSS
L7
B16
VSS
L8
C3
VSS
M9
C4
VSS
K10
C13
VSS
M12
C14
VSS
J10
D3
VSS
H10
D4
VSS
G14
D7
VSS
G11
D9
VSS
E14
D10
VSS
D13
D13
VSS
B11
D14
VSS
E9
E5
VSS
D8
E12
VSS
A7
F6
VSS
A6
F7
VSS
A4
F8
VSS
F9
VSS
F10
26
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DESCRIPTION
Digital ground pins
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TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
NAME
ZHH
BALL #
ZFE
BALL #
VSS
F11
VSS
G4
VSS
G6
VSS
G7
VSS
G8
VSS
G9
VSS
G10
VSS
G11
VSS
G13
VSS
H4
VSS
H6
VSS
H7
VSS
H8
VSS
H9
VSS
H10
VSS
H11
VSS
H13
VSS
J6
VSS
J7
VSS
J8
VSS
J9
VSS
J10
VSS
J11
VSS
K1
VSS
K4
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
K10
VSS
K11
VSS
K13
VSS
K16
VSS
L6
VSS
L7
VSS
L8
VSS
L9
VSS
L10
VSS
L11
VSS
M5
VSS
M12
VSS
N4
VSS
N7
VSS
N9
VSS
N10
VSS
N13
DESCRIPTION
Digital ground pins
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TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
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Table 6-1. Signal Descriptions (continued)
NAME
ZHH
BALL #
ZFE
BALL #
VSS
N14
VSS
P3
VSS
P4
VSS
P14
VSS
R1
VSS
R2
VSS
R15
VSS
R16
VSS
T1
VSS
T2
VSS
T15
VSS
T16
28
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DESCRIPTION
Digital ground pins
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TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
7 Specifications
This section provides the absolute maximum ratings and the recommended operating conditions.
7.1 Absolute Maximum Ratings (1) (2)
MIN
Supply voltage
Input voltage
Output voltage
MAX
VDDIO with respect to VSS
–0.3
4
VDD with respect to VSS
–0.3
1.5
VDD18 with respect to VSS
–0.3
2.4
VIN (3.3 V)
–0.3
4
VIN (1.8 V)
–0.3
2.4
–0.3
4
VO
)(3)
UNIT
V
V
V
Input clamp current
IIK (VIN < 0 or VIN > VDDIO
–20
20
mA
Output clamp current
IOK (VO < 0 or VO > VDDIO)
–20
20
mA
Junction temperature
TJ (4)
–40
150
°C
Storage temperature
Tstg (4)
–65
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
Continuous clamp current per pin is ±2 mA.
One or both of the following conditions may result in a reduction of overall device life:
• long-term high-temperature storage
• extended use at maximum temperature
For additional information, see Semiconductor and IC Package Thermal Metrics.
7.2 ESD Ratings – Automotive
VALUE
UNIT
TMS320C2834x in ZFE Package
Human body model (HBM), per AEC Q100-002(1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per AEC Q100-011
±2000
All pins
±500
Corner pins on 256-ball
ZFE: A1, A16, T1, T16
±750
V
AEC Q100-002 indicates HBM stressing is done in accordance wit hthe ANSI/ESDA/JEDEC JS-001 specification.
7.3 ESD Ratings – Commercial
VALUE
UNIT
TMS320C2834x in ZHH Package
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.4 Recommended Operating Conditions
Device supply voltage, I/O, VDDIO
Device supply voltage CPU, VDD
MIN
NOM
MAX
UNIT
V
3.14
3.3
3.46
300-MHz devices
1.14
1.2
1.26
200-MHz devices
1.05
1.1
1.16
Supply ground, VSS, VSSIO
0
Oscillator supply ground, VSSK
Device clock frequency (system clock),
fSYSCLKOUT
V
0
PLL/oscillator supply, VDD18
1.71
1.8
V
1.89
C28346/C28344/C28342
(VDD = 1.2 V ± 5%)
2
300
C28345/C28343/C28341
(VDD = 1.1 V ± 5%)
2
200
High-level input voltage, VIH (3.3 V)
2
VDDIO + 0.3
High-level input voltage, VIH (1.8 V)
0.7 * VDD18
Low-level input voltage, VIL (3.3 V)
VSS – 0.3
Low-level input voltage, VIL (1.8 V)
V
0.8
V
V
–4
Low-level output sink current,
VOL = VOL MAX, IOL
All I/Os
4
30
MHz
0.3 * VDD18
All I/Os
(1)
V
V
High-level output source current,
VOH = 2.4 V, IOH
Junction temperature, TJ (1)
V
T version
–40
105
S version
–40
125
Q version
(AEC Q100 Qualification)
–40
125
mA
mA
°C
TA (Ambient temperature) is product- and application-dependent and can go up to the specified TJ maximum of the device. See
Section 7.8, Thermal Design Considerations.
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7.5 Power Consumption Summary
7.5.1 TMS320C28346/C28344 (1) Current Consumption by Power-Supply Pins at 300-MHz SYSCLKOUT
MODE
TEST CONDITIONS
The following peripheral clocks are
enabled:
•
ePWM1, ePWM2, ePWM3,
ePWM4, ePWM5, ePWM6,
ePWM7, ePWM8, ePWM9
•
eCAP1, eCAP2, eCAP3
•
eQEP1, eQEP2, eQEP3
•
eCAN-A
•
SCI-A, SCI-B (FIFO mode)
•
SPI-A (FIFO mode)
•
McBSP-A
Typical Operational
•
I2C
•
XINTF
•
DMA
•
CPU-Timer 0, CPU-Timer 1,
CPU-Timer 2
IDDIO (2)
IDD
IDD18
25°C
105°C
125°C
25°C
105°C
125°C
25°C
105°C
125°C
335 mA
555 mA
740 mA
75 mA
75 mA
80 mA
50 mA
47 mA
45 mA
All PWM pins are toggled at
300 kHz.
All I/O pins are left unconnected.
XCLKOUT is turned off. Pullups on
output pins and XINTF pins are
disabled.(3)
IDLE
XCLKOUT is turned off.
Peripheral clocks are off.
205 mA
425 mA
610 mA
15 mA
15 mA
18 mA
50 mA
47 mA
45 mA
STANDBY
Peripheral clocks are off.
140 mA
360 mA
545 mA
15 mA
15 mA
18 mA
50 mA
47 mA
45 mA
HALT
Peripheral clocks are off.
Input clock is disabled.(4)
135 mA
355 mA
540 mA
15 mA
15 mA
18 mA
550 μA
550 μA
550 μA
(1)
(2)
(3)
(4)
The IDD numbers in this table are valid for the TMS320C28346 and TMS320C28344 devices only. For the TMS320C28342 device,
subtract the IDD current numbers for those peripherals that do not exist on this device (see Table 7-1) from the IDD current numbers
shown in this table.
IDDIO current is dependent on the electrical loading on the I/O pins.
The following is done in a loop:
• Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
• Floating-point multiplication and addition are performed.
• 32-bit read/write of the XINTF is performed.
• DMA channels 1 and 2 transfer data from SARAM to SARAM.
• GPIO19 is toggled.
If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
Note
The IDD numbers in Section 7.5.1 are valid for the TMS320C28346 and TMS320C28344 devices only.
For the TMS320C28342 device, subtract the IDD current numbers for those peripherals that do not
exist on this device (see Table 7-1) from the IDD current numbers shown in Section 7.5.1.
Note
The peripheral - I/O multiplexing implemented in the device prevents all available peripherals from
being used at the same time. This is because more than one peripheral function may share an I/O pin.
It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a
configuration is not useful. If this is done, the current drawn by the device will be more than the
numbers specified in the current consumption tables.
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7.5.2 TMS320C28345/C28343 (1) Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT
MODE
Typical operation
TEST CONDITIONS
The following peripheral clocks are
enabled:
•
ePWM1, ePWM2, ePWM3,
ePWM4, ePWM5, ePWM6,
ePWM7, ePWM8, ePWM9
•
eCAP1, eCAP2, eCAP3
•
eQEP1, eQEP2, eQEP3
•
eCAN-A
•
SCI-A, SCI-B (FIFO mode)
•
SPI-A (FIFO mode)
•
McBSP-A
•
I2C
•
XINTF
•
DMA
•
CPU-TImers 0, CPU-Timer 1,
CPU-Timer 2
IDDIO (2)
IDD
IDD18
25°C
105°C
125°C
25°C
105°C
125°C
25°C
105°C
125°C
200 mA
380 mA
500 mA
45 mA
45 mA
45 mA
45 mA
43 mA
40 mA
95 mA
275 mA
395 mA
15 mA
15 mA
18 mA
45 mA
43 mA
40 mA
All PWM pins are toggled at 200 kHz.
All I/O pins are left unconnected.
XCLKOUT is turned off. Pullups on
output pins and XINTF pins are
disabled.(3)
IDLE
Peripheral clocks are off. XCLKOUT is
turned off.
STANDBY
Peripheral clocks are off.
45 mA
225 mA
345 mA
15 mA
15 mA
18 mA
45 mA
43 mA
40 mA
HALT
Peripheral clocks are off. Input clock is
disabled.(4)
40 mA
220 mA
340 mA
15 mA
15 mA
18 mA
550 μA
550 μA
550 μA
(1)
(2)
(3)
(4)
The IDD numbers in this table are valid for the TMS320C28345 and TMS320C28343 devices only. For the TMS320C28341 device,
subtract the IDD current numbers for those peripherals that do not exist on this device (see Table 7-1) from the IDD current numbers
shown in this table.
IDDIO current is dependent on the electrical loading on the I/O pins.
The following is done in a loop:
• Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
• Floating-point multiplication and addition are performed.
• 32-bit read/write of the XINTF is performed.
• DMA channels 1 and 2 transfer data from SARAM to SARAM.
• GPIO19 is toggled.
If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
Note
The IDD numbers in Section 7.5.2 are valid for the TMS320C28345 and TMS320C28343 devices only.
For the TMS320C28341 device, subtract the IDD current numbers for those peripherals that do not
exist on this device (see Table 7-1) from the IDD current numbers shown in Section 7.5.2.
32
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TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
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7.5.3 Reducing Current Consumption
Methods of reducing current consumption include the following:
• Turn off the clock to any peripheral module that is not used in a given application because each peripheral
unit has an individual clock-enable bit. Table 7-1 indicates the typical reduction in current consumption
achieved by turning off the clocks.
• Use any one of the three low-power modes to reduce current even further.
• Turn off XCLKOUT, reducing IDDIO current consumption by 15 mA (typical).
• Disable the pullups on pins that assume an output function and on XINTF pins for significant savings in IDDIO.
Note
The TMS320C2834x devices are manufactured in a high-performance process node. Compared to
the previous generation of the C28x devices, this process has more leakage current. Leakage current
is significantly impacted by the operating temperature, and the increase in current with temperature is
nonlinear. The total power for a given operating condition includes switching/active power plus
leakage power. Low-power HALT mode power is due to the leakage current alone.
Figure 7-1 shows the typical leakage current across temperature.
Temperature (°C) Vs Leakage current (mA)
600
Leakage current (mA)
500
400
300
200
100
0
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Figure 7-1. Temperature Versus Leakage Current (Typical)
Table 7-1. Typical Current Consumption by Various
Peripherals (1)
Copyright © 2021 Texas Instruments Incorporated
PERIPHERAL
MODULE
IDD CURRENT
REDUCTION (mA)
I2C
5
eQEP
5
ePWM
3
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Table 7-1. Typical Current Consumption by Various
Peripherals (1) (continued)
(1)
(2)
PERIPHERAL
MODULE
IDD CURRENT
REDUCTION (mA)
eCAP
1
SCI
4
SPI
4
eCAN
2
McBSP
8
CPU-Timer
1
XINTF
4(2)
DMA
7
FPU
8
All peripheral clocks (except CPU timer clocks) are disabled
upon reset. Writing to or reading from peripheral registers is
possible only after the peripheral clocks are turned on.
Operating the XINTF bus has a significant effect on IDDIO
current. It will increase considerably based on the following:
• How many address/data pins toggle from one cycle to
another
• How fast they toggle
• Whether 16-bit or 32-bit interface is used and
• The load on these pins.
• Whether internal pullups are enabled on the XINTF pins.
7.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
IIL
IIH
Input current
(low level)
Input current
(high level)
TEST CONDITIONS
IOH = IOH MAX
VDDIO = 3.3 V, VIN = 0 V
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = 0 V
Pin with pullup
enabled
VDDIO = 3.3 V, VIN = VDDIO
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = VDDIO
MAX
0.4
All I/Os (including XRS)
UNIT
V
VDDIO – 0.2
IOL = IOL MAX
Pin with pullup
enabled
–190
V
–100
μA
±15
±3
μA
Output current, pullup or pulldown
VO = VDDIO or 0 V
disabled
CI
Input capacitance
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TYP
2.4
IOH = 50 μA
IOZ
34
MIN
100
175
±15
2
μA
pF
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7.7 Thermal Resistance Characteristics
7.7.1 ZHH Package
°C/W(1) (2)
AIR FLOW (lfm)(3)
RΘJC
Junction-to-case
10.3
0
RΘJB
Junction-to-board
21.2
0
RΘJA
(High k PCB)
PsiJT
Junction-to-package top
PsiJB
(1)
(2)
(3)
Junction-to-free air
Junction-to-board
40.8
0
32.4
150
31.0
250
29.1
500
0.4
0
0.5
150
0.6
250
0.8
500
21.0
0
20.4
150
20.2
250
19.9
500
°C/W = degrees Celsius per watt
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
7.7.2 ZFE Package
°C/W(1) (2)
AIR FLOW (lfm)(3)
RΘJC
Junction-to-case
14
0
RΘJB
Junction-to-board
13.9
0
30
0
21.8
150
20.6
250
RΘJA
(High k PCB)
PsiJT
PsiJB
(1)
(2)
Junction-to-free air
Junction-to-package top
Junction-to-board
19.1
500
1.24
0
2.63
150
3.15
250
4.05
500
14
0
13.6
150
13.5
250
13.4
500
°C/W = degrees Celsius per watt
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
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(3)
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
7.8 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that
exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application report Semiconductor and IC package thermal metrics helps to understand the thermal metrics and
definitions.
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7.9 Timing and Switching Characteristics
7.9.1 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
f
fall time
X
Unknown, changing, or don't care level
h
hold time
Z
High impedance
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
7.9.1.1 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For
actual cycle examples, see the appropriate cycle description section of this document.
7.9.1.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
42 Ω
3.5 nH
Transmission Line
Data Sheet Timing Reference Point
Output
Under
Test
Z0 = 50 Ω(Α)
Device Pin(B)
4.0 pF
1.85 pF
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line
effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer)
from the data sheet timing.
Figure 7-2. 3.3-V Test Load Circuit
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7.9.1.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available. Section 7.9.1.3.1 and Section 7.9.1.3.2 list the cycle times of various clocks.
7.9.1.3.1 Clocking and Nomenclature (300-MHz Devices)
MIN
On-chip oscillator clock (crystal/resonator–X1/X2)
PLL enabled
XCLKIN(5)
PLL disabled
PLL enabled
X1(5)
PLL disabled
Frequency
tc(CI), Cycle time (C8)
Frequency
tc(CI), Cycle time (C8)
Frequency
tc(CI), Cycle time (C8)
Frequency
Frequency
HSPCLK/EXTADCCLK(2)
MAX
UNIT
33.3
NOM
125
ns
8
30
MHz
6.67
50
ns
2
150
MHz
6.67
250
ns
4
150
MHz
10
50
ns
2
100
MHz
10
250
ns
4
100
MHz
3.33
500
ns
2
300
MHz
13.3
2000
ns
Frequency
0.5
75(4)
MHz
tc(HCO), Cycle time
25
ns
Frequency
tc(LCO), Cycle time
LSPCLK(1)
38
tc(CI), Cycle time (C8)
tc(XCO), Cycle time
XCLKOUT
(5)
Frequency
tc(SCO), Cycle time
SYSCLKOUT
(1)
(2)
(3)
(4)
tc(OSC), Cycle time
Frequency
40
6.67
13.3(3)
75(3)
MHz
ns
150
MHz
Lower LSPCLK and HSPCLK will reduce device power consumption.
This frequency is limited by GPIO switching characteristics.
This is the value if SYSCLKOUT = 300 MHz.
Although the maximum XCLKOUT frequency is 75 MHz, this value may not be attainable depending on SYSCLKOUT and available
prescalers.
The input clock frequency and PLLCR[DIV] values should be chosen such that the output frequency of the PLL(VCOCLK) lies between
400 MHz to 600 MHz.
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7.9.1.3.2 Clocking and Nomenclature (200-MHz Devices)
MIN
On-chip oscillator clock (crystal/resonator–X1/X2)
PLL enabled
XCLKIN(5)
PLL disabled
PLL enabled
X1(5)
PLL disabled
SYSCLKOUT
tc(CI), Cycle time (C8)
Frequency
tc(CI), Cycle time (C8)
Frequency
tc(CI), Cycle time (C8)
Frequency
tc(CI), Cycle time (C8)
NOM
UNIT
125
ns
8
30
MHz
6.67
50
ns
2
150
MHz
6.67
250
ns
4
150
MHz
10
50
ns
2
100
MHz
10
250
ns
Frequency
4
100
MHz
5
500
ns
Frequency
tc(HCO), Cycle time
2
200
MHz
13.3
2000
ns
0.5
75(4)
MHz
8
ns
Frequency
tc(LCO), Cycle time
LSPCLK(2)
MAX
33.3
tc(SCO), Cycle time
Frequency
HSPCLK/EXTADCCLK(1)
(5)
Frequency
tc(XCO), Cycle time
XCLKOUT
(1)
(2)
(3)
(4)
tc(OSC), Cycle time
Frequency
40
10
20(3)
50(3)
MHz
ns
100
MHz
This frequency is limited by GPIO switching characteristics.
Lower LSPCLK and HSPCLK will reduce device power consumption.
This is the value if SYSCLKOUT = 200 MHz.
Although the maximum XCLKOUT frequency is 75 MHz, this value may not be attainable depending on SYSCLKOUT and available
prescalers.
The input clock frequency and PLLCR[DIV] values should be chosen such that the output frequency of the PLL(VCOCLK) lies between
400 MHz to 600 MHz.
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7.9.2 Power Sequencing
No special requirements are placed on the power up/down sequence of the various power pins to ensure the
correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers of the
I/O pins are powered prior to the 1.1-V/1.2-V transistors, it is possible for the output buffers to turn on, causing a
glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins prior to or simultaneously
with the VDDIO pins, ensuring that the VDD pins have reached 0.7-V before the VDDIO pins reach 0.7 V. The 1.8-V
rail for the PLL and oscillator logic can be powered up along with VDD/VDDIO rails. The 1.8-V rail must be
powered even if the PLL is not used. It should never be left unpowered. In any configuration, all the rails should
ramp up within tpup (5 ms, typical) to allow early stability of clocks and IOs.
There is a requirement on the XRS pin:
• During power up, the XRS pin must be held low for tw(RSL1) after the input clock is stable. This is to enable the
entire device to start from a known condition.
No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin before powering up
the device. Voltages applied to pins on an unpowered device can bias internal P-N junctions in unintended ways
and produce unpredictable results.
7.9.2.1 Power Management and Supervisory Circuit Solutions
LDO selection depends on the total power consumed in the end application. Go to the Power Management page
for a list of TI power management ICs. Click the Reference designs tab for specific power management
reference designs.
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VDDIO (3.3 V)
VDD18 (1.8 V)
VDD (1.2 V/1.1 V)
tpup
XCLKIN
X1/X2
OSCCLK/64 (A)
XCLKOUT
tOSCST
OSCCLK/16
User-Code Dependent
tw(RSL1)
XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/Data/
Control
(Internal)
td(EX)
th(boot-mode)(B)
Boot-Mode
Pins
User-Code Execution Phase
User-Code Dependent
GPIO Pins as Input
Peripheral/GPIO Function
Based on Boot Code
Boot-ROM Execution Starts
I/O Pins (C)
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. Upon power up, SYSCLKOUT is OSCCLK/8. Because the XTIMCLK, CLKMODE, and BY4CLKMODE bits in the XINTFCNF2 register
come up with a reset state of 1, SYSCLKOUT is further divided by 8 before it applies to XCLKOUT. This explains why XCLKOUT =
OSCCLK/64 during this phase. Subsequently, boot ROM changes SYSCLKOUT to OSCLK/2. Because the XTIMCLK register is
unchanged by the boot ROM, XCLKOUT is OSCCLK/16 during this phase.
B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
C. See Section 7.9.2 for requirements to ensure a high-impedance state for GPIO pins during power up.
Figure 7-3. Power-on Reset
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7.9.2.2 Reset ( XRS) Timing Requirements
MIN
tw(RSL1)
(1)
Pulse duration, stable input clock to XRS high
tw(RSL2)
Pulse duration, XRS low
tw(WDRS)
Pulse duration, reset pulse generated by
watchdog
td(EX)
Delay time, address/data valid after XRS high
tOSCST
(2)
Hold time for boot-mode pins
tpup
Power-up time
MAX
UNIT
64tc(OSCCLK)
cycles
64tc(OSCCLK)
cycles
Oscillator start-up time
th(boot-mode)
(1)
(2)
Warm reset
NOM
512tc(OSCCLK)
cycles
32tc(OSCCLK)
cycles
1
10
200tc(OSCCLK)
ms
cycles
5
ms
In addition to the tw(RSL1) requirement, XRS must be low until VDD has reached the minimum operating voltage.
Dependent on crystal/resonator and board design.
XCLKIN
X1/X2
OSCCLK/8
XCLKOUT
User-Code Dependent
OSCCLK * 5
tw(RSL2)
XRS
Address/Data/
Control
(Internal)
td(EX)
User-Code Execution
(Don’t Care)
Boot-ROM Execution Starts
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Execution Phase
GPIO Pins as Input
th(boot-mode)(A)
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
Figure 7-4. Warm Reset
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Figure 7-5 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0003
and SYSCLKOUT = OSCCLK × 2. The PLLCR is then written with 0x0007 (setting for OSCCLK × 8). Right after
the PLLCR register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2.
After the PLL lock-up is complete (which takes 2600 OSCCLK cycles), SYSCLKOUT reflects the new operating
frequency, OSCCLK × 4.
OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
OSCCLK/2
OSCCLK * 4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, tp) is
2600 OSCCLK Cycles Long.)
(Changed CPU Frequency)
Figure 7-5. Example of Effect of Writing Into PLLCR Register
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7.9.3 Clock Requirements and Characteristics
7.9.3.1 XCLKIN/X1 Timing Requirements – PLL Enabled
NO.
C9
MIN
MAX UNIT
Fall time, XCLKIN(1)
tf(CI)
XCLKIN(1)
4
ns
4
ns
C10
tr(CI)
Rise time,
C11
tw(CIL)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) (1)
40%
60%
C12
tw(CIH)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) (1)
40%
60%
MIN
MAX UNIT
(1)
This applies to the X1 pin also.
7.9.3.2 XCLKIN/X1 Timing Requirements – PLL Disabled
NO.
XCLKIN(1)
C9
tf(CI)
Fall time,
C10
tr(CI)
Rise time, XCLKIN(1)
(1)
C11
tw(CIL)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
C12
tw(CIH)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) (1)
(1)
2
ns
2
ns
45%
55%
45%
55%
This applies to the X1 pin also.
The possible configuration modes are shown in Table 8-34.
7.9.3.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2)
NO.
PARAMETER
MIN
C1
tc(XCO)
Cycle time, XCLKOUT
C3
tf(XCO)
Fall time, XCLKOUT
C4
tr(XCO)
Rise time, XCLKOUT
C5
tw(XCOL)
Pulse duration, XCLKOUT low
H–2
tw(XCOH)
Pulse duration, XCLKOUT high
H–2
tp
PLL lock time
C6
(1)
(2)
(3)
TYP
MAX
13.3
UNIT
ns
2
ns
2
ns
H+2
H+2
2600tc(OSCCLK) (3)
ns
ns
cycles
A load of 40 pF is assumed for these parameters.
H = 0.5tc(XCO)
OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
7.9.3.4 Timing Diagram
C10
C9
C8
XCLKIN(A)
C1
C6
C3
C4
C5
XCLKOUT(B)
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate
the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 7-6. Clock Timing
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7.9.4 Peripherals
7.9.4.1 General-Purpose Input/Output (GPIO)
7.9.4.1.1 GPIO - Output Timing
7.9.4.1.1.1 General-Purpose Output Switching Characteristics
PARAMETER
tr(GPO)
MIN
Rise time, GPIO switching low to high
All GPIOs
tf(GPO)
Fall time, GPIO switching high to low
All GPIOs
tfGPO
Toggling frequency, GPO pins
MAX
11
UNIT
ns
11
ns
40
MHz
GPIO
tf(GPO)
tr(GPO)
Figure 7-7. General-Purpose Output Timing
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7.9.4.1.2 GPIO - Input Timing
7.9.4.1.2.1 General-Purpose Input Timing Requirements
MIN
tw(SP)
Sampling period
tw(IQSW)
Input qualifier sampling window
tw(GPI) (2)
(1)
(2)
QUALPRD = 0
1tc(SCO)
QUALPRD ≠ 0
2tc(SCO) * QUALPRD
MAX
UNIT
cycles
tw(SP) * (n(1) – 1)
Synchronous mode
Pulse duration, GPIO low/high
cycles
2tc(SCO)
With input qualifier
cycles
tw(IQSW) + tw(SP) + 1tc(SCO)
"n" represents the number of qualification samples as defined by GPxQSELn register.
For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
tw(SP)
0
0
0
1
1
1
1
1
1
1
1
1
Sampling Period determined
by GPxCTRL[QUALPRD](B)
tw(IQSW)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5(C))
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in
2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other
words, the inputs should be stable for (5 × QUALPRD × 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to
occur. Because external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 7-8. Sampling Mode
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7.9.4.1.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using three samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using six samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 5, if QUALPRD = 0
SYSCLK
GPIOxn
tw(GPI)
Figure 7-9. General-Purpose Input Timing
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7.9.4.1.4 Low-Power Mode Wakeup Timing
The wakeup signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of
the device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses.
Section 7.9.4.1.4.1 shows the timing requirements, Section 7.9.4.1.4.2 shows the switching characteristics, and
Figure 7-10 shows the timing diagram for IDLE mode.
7.9.4.1.4.1 IDLE Mode Timing Requirements (1)
MIN
tw(WAKE-INT)
(1)
Pulse duration, external wake-up signal
Without input qualifier
MAX
2tc(SCO)
With input qualifier
UNIT
cycles
5tc(SCO) + tw(IQSW)
For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.1.4.2 IDLE Mode Switching Characteristics (1)
PARAMETER
Delay time, external wake signal to
program execution resume (2)
• Wake-up from SARAM
td(WAKE-IDLE)
(1)
(2)
TEST CONDITIONS
MIN
Without input qualifier
With input qualifier
MAX
UNIT
20tc(SCO)
20tc(SCO) + tw(IQSW)
cycles
For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
7.9.4.1.4.3 IDLE Mode Timing Diagram
td(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE−INT)
WAKE INT(A)
A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 7-10. IDLE Entry and Exit Timing
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7.9.4.1.4.4 STANDBY Mode Timing Requirements
MIN
Pulse duration, external
wake-up signal
tw(WAKE-INT)
(1)
Without input qualification
With input qualification(1)
MAX
3tc(OSCCLK)
UNIT
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
QUALSTDBY is a 6-bit field in the LPMCR0 register.
7.9.4.1.4.5 STANDBY Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
td(IDLE-XCOL)
Delay time, IDLE instruction
executed to XCLKOUT low
td(WAKE-STBY)
Delay time, external wake signal to Without input qualifier
program execution resume(1)
With input qualifier
• Wake up from SARAM
(1)
MIN
MAX
UNIT
32tc(SCO)
45tc(SCO)
cycles
100tc(SCO)
100tc(SCO) + tw(WAKE-INT)
cycles
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
7.9.4.1.4.6 STANDBY Mode Timing Diagram
(A)
(C)
(B)
Device
Status
STANDBY
(E)
(D)
(F)
STANDBY
Normal Execution
Flushing Pipeline
Wake-up
Signal
tw(WAKE-INT)
td(WAKE-STBY)
X1/X2 or
X1 or
XCLKIN
XCLKOUT
td(IDLE−XCOL)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for 32 cycles before being turned off. This delay enables the CPU
pipeline and any other pending operations to flush properly. If an access to XINTF is in progress and its access time is longer than this
number then it will fail. TI recommends entering STANDBY mode from SARAM without an XINTF access in progress.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode.
D. The external wake-up signal is driven active.
E. After a latency period, the STANDBY mode is exited.
F. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 7-11. STANDBY Entry and Exit Timing Diagram
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7.9.4.1.4.7 HALT Mode Timing Requirements
MIN
tw(WAKE-GPIO)
Pulse duration, GPIO wake-up signal
tw(WAKE-XRS)
Pulse duration, XRS wakeup signal
(1)
MAX
UNIT
toscst + 2tc(OSCCLK) (1)
cycles
toscst + 8tc(OSCCLK)
cycles
See Section 7.9.2.2 for an explanation of toscst.
7.9.4.1.4.8 HALT Mode Switching Characteristics
PARAMETER
td(IDLE-XCOL)
Delay time, IDLE instruction executed to XCLKOUT low
tp
PLL lock-up time
td(WAKE-HALT)
Delay time, PLL lock to program execution resume
• Wake up from SARAM
MIN
MAX
UNIT
32tc(SCO)
45tc(SCO)
cycles
2600tc(OSCCLK)
cycles
35tc(SCO)
cycles
7.9.4.1.4.9 HALT Mode Timing Diagram
(A)
(C)
Device
Status
HALT
Flushing Pipeline
(H)
(F)
(D)(E)
(B)
(G)
HALT
PLL Lock-up Time
Wake-up Latency
Normal
Execution
GPIOn
td(WAKE−HALT)
tw(WAKE-GPIO)
tp
X1/X2
or XCLKIN
Oscillator Start-up Time
XCLKOUT
td(IDLE−XCOL)
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for 32 cycles before oscillator is turned off and the CLKIN to the core is
stopped. This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in progress
and its access time is longer than this number then it will fail. It is recommended to enter HALT mode from SARAM without an XINTF
access in progress.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence
is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal
during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wakeup process, care should be
taken to maintain a low noise environment prior to entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wake-up pulses.
F. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 2,600 OSCCLK (X1/X2 or X1 or XCLKIN) cycles.
G. Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the interrupt (if enabled), after
a latency.
H. Normal operation resumes.
Figure 7-12. HALT Wakeup Using GPIOn
50
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7.9.4.2 Enhanced Control Peripherals
7.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
PWM refers to PWM outputs on ePWM1–6. Section 7.9.4.2.1.1 shows the ePWM timing requirements and
Section 7.9.4.2.1.2, ePWM switching characteristics.
7.9.4.2.1.1 ePWM Timing Requirements (1)
MIN
tw(SYCIN)
Sync input pulse width
Asynchronous
2tc(SCO)
Synchronous
2tc(SCO)
With input qualifier
(1)
MAX
UNIT
cycles
1tc(SCO) + tw(IQSW)
For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.2.1.2 ePWM Switching Characteristics
PARAMETER
TEST CONDITIONS
tw(PWM)
Pulse duration, PWMx output high/low
tw(SYNCOUT)
Sync output pulse width
td(PWM)tza
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
MIN
MAX
20
ns
8tc(SCO)
no pin load
UNIT
cycles
25
ns
20
ns
7.9.4.2.2 Trip-Zone Input Timing
SYSCLK
tw(TZ)
(A)
TZ
td(TZ-PWM)HZ
(B)
PWM
A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.
Figure 7-13. PWM Hi-Z Characteristics
7.9.4.2.2.1 Trip-Zone Input Timing Requirements (1)
MIN
tw(TZ)
Pulse duration, TZx input low
Asynchronous
1tc(SCO)
Synchronous
2tc(SCO)
With input qualifier
(1)
MAX
UNIT
cycles
1tc(SCO) + tw(IQSW)
For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
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7.9.4.2.3 High-Resolution PWM Timing
Section 7.9.4.2.3.1 shows the high-resolution PWM switching characteristics.
7.9.4.2.3.1 High-Resolution PWM Characteristics at SYSCLKOUT = (150–300 MHz)
MIN
Micro Edge Positioning (MEP) step size(1)
(1)
TYP
MAX UNIT
VDD = 1.2 V
55
120
ps
VDD = 1.1 V
65
140
ps
The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
7.9.4.2.4 Enhanced Capture (eCAP) Timing
Section 7.9.4.2.4.1 shows the eCAP timing requirement and Section 7.9.4.2.4.2 shows the eCAP switching
characteristics.
7.9.4.2.4.1 Enhanced Capture (eCAP) Timing Requirements (1)
MIN
Asynchronous
tw(CAP)
Capture input pulse width
Synchronous
With input qualifier
(1)
MAX
UNIT
2tc(SCO)
2tc(SCO)
cycles
1tc(SCO) + tw(IQSW)
For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.2.4.2 eCAP Switching Characteristics
PARAMETER
tw(APWM)
TEST CONDITIONS
MIN
Pulse duration, APWMx output high/low
MAX
20
UNIT
ns
7.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
Section 7.9.4.2.5.1 shows the eQEP timing requirement and Section 7.9.4.2.5.2 shows the eQEP switching
characteristics.
7.9.4.2.5.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements (1)
MIN
tw(QEPP)
QEP input period
tw(INDEXH)
QEP Index Input High time
tw(INDEXL)
QEP Index Input Low time
tw(STROBH)
QEP Strobe High time
tw(STROBL)
QEP Strobe Input Low time
(1)
(2)
Asynchronous(2)/synchronous
With input qualifier
With input qualifier
2tc(SCO)
cycles
2tc(SCO) + tw(IQSW)
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO)
cycles
2tc(SCO) + tw(IQSW)
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO)
cycles
2tc(SCO) + tw(IQSW)
Asynchronous(2)/synchronous
UNIT
cycles
2[1tc(SCO) + tw(IQSW)]
Asynchronous(2)/synchronous
With input qualifier
MAX
2tc(SCO)
2tc(SCO)
cycles
2tc(SCO) + tw(IQSW)
For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
Refer to the TMS320C2834x Delfino™ MCUs Silicon Errata for limitations in the asynchronous mode.
7.9.4.2.5.2 eQEP Switching Characteristics
PARAMETER
td(CNTR)xin
52
Delay time, external clock to counter increment
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TEST CONDITIONS
MIN
MAX
UNIT
4tc(SCO)
cycles
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PARAMETER
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync
output
Copyright © 2021 Texas Instruments Incorporated
TEST CONDITIONS
MIN
MAX
UNIT
6tc(SCO)
cycles
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7.9.4.2.6 ADC Start-of-Conversion Timing
7.9.4.2.6.1 External ADC Start-of-Conversion Switching Characteristics
PARAMETER
tw(ADCSOCL)
MIN
Pulse duration, ADCSOCxO low
MAX
32tc(HCO )
UNIT
cycles
7.9.4.2.6.2 ADCSOCAO or ADCSOCBO Timing
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 7-14. ADCSOCAO or ADCSOCBO Timing
7.9.4.3 External Interrupt Timing
7.9.4.3.1 External Interrupt Timing Requirements (1)
MIN
tw(INT) (2)
(1)
(2)
Pulse duration, INT input low/high
Synchronous
1tc(SCO)
With qualifier
1tc(SCO) + tw(IQSW)
MAX
UNIT
cycles
For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
This timing is applicable to any GPIO pin configured for ADCSOC functionality.
7.9.4.3.2 External Interrupt Switching Characteristics (1)
PARAMETER
td(INT)
(1)
Delay time, INT low/high to interrupt-vector fetch
MIN
MAX
UNIT
tw(IQSW) + 12tc(SCO)
cycles
For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.3.3 External Interrupt Timing Diagram
tw(INT)
XNMI, XINT1, XINT2
td(INT)
Address bus
(internal)
Interrupt Vector
Figure 7-15. External Interrupt Timing
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7.9.4.4 I2C Electrical Specification and Timing
7.9.4.4.1 I2C Timing
TEST CONDITIONS
fSCL
SCL clock frequency
vil
Low level input voltage
Vih
High level input voltage
MIN
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
MAX
UNIT
400
kHz
0.3 VDDIO
0.7 VDDIO
V
V
Vhys
Input hysteresis
Vol
Low level output voltage
3-mA sink current
tLOW
Low period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
1.3
μs
tHIGH
High period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
0.6
μs
lI
Input current with an input voltage
between 0.1 VDDIO and 0.9 VDDIO MAX
Copyright © 2021 Texas Instruments Incorporated
0.05 VDDIO
0
V
0.4
–10
10
V
μA
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7.9.4.5 Serial Peripheral Interface (SPI) Timing
This section contains both Master Mode and Slave Mode timing data.
7.9.4.5.1 Master Mode Timing
Section 7.9.4.5.1.1 lists the master mode timing (clock phase = 0) and Section 7.9.4.5.1.2 lists the master mode
timing (clock phase = 1). Figure 7-16 and Figure 7-17 show the timing waveforms.
7.9.4.5.1.1 SPI Master Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5)
PARAMETER
NO.
1
(1)
(2)
(3)
(4)
(5)
56
tc(SPC)M
Cycle time, SPICLK
2
tw(SPC1)M
Pulse duration, SPICLK first
pulse
3
tw(SPC2)M
Pulse duration, SPICLK second
pulse
4
td(SIMO)M
Delay time, SPICLK to
SPISIMO valid
5
tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK
8
tsu(SOMI)M
Setup time, SPISOMI before
SPICLK
9
th(SOMI)M
Hold time, SPISOMI valid after
SPICLK
23
td(SPC)M
Delay time, SPISTE active to
SPICLK
24
td(STE)M
Delay time, SPICLK to SPISTE
inactive
BRR EVEN
BRR ODD
MIN
MAX
MIN
MAX
4tc(LSPCLK)
128tc(LSPCLK)
UNIT
5tc(LSPCLK)
127tc(LSPCLK)
ns
0.5tc(SPC)M – 10
0.5tc(SPC)M + 0.5tc(LSPCLK)
0.5tc(SPC)M + 10
– 10
0.5tc(SPC)M +
0.5tc(LSPCLK) + 10
ns
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M –
0.5tc(LSPCLK) + 10
ns
10
ns
10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
ns
20
20
ns
0
0
ns
tc(SPC)M – 10
0.5tc(SPC)M –
0.5tc(LSPCLK) – 10
ns
0.5tc(SPC)M – 10
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
ns
The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
tc(LCO) = LSPCLK cycle time
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
23
24
SPISTE
Figure 7-16. SPI Master Mode External Timing (Clock Phase = 0)
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7.9.4.5.1.2 SPI Master Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5)
NO.
1
(1)
(2)
(3)
(4)
(5)
BRR EVEN
PARAMETER
BRR ODD
MIN
MAX
4tc(LSPCLK)
UNIT
MIN
MAX
128tc(LSPCLK)
5tc(LSPCLK)
127tc(LSPCLK)
ns
0.5tc(SPC)M –
0.5tc(LSPCLK) + 10
ns
0.5tc(SPC)M +
0.5tc(LSPCLK) + 10
ns
tc(SPC)M
Cycle time, SPICLK
2
tw(SPC1)M
Pulse duration, SPICLK first
pulse
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M –
0.5tc(LSPCLK) – 10
3
tw(SPC2)M
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M +
0.5tc(LSPCLK) – 10
6
td(SIMO)M
Delay time, SPISIMO valid to
SPICLK
0.5tc(SPC)M – 10
0.5tc(SPC)M +
0.5tc(LSPCLK) – 10
ns
7
tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M – 10
0.5tc(SPC)M –
0.5tc(LSPCLK) – 10
ns
10
tsu(SOMI)M
Setup time, SPISOMI before
SPICLK
20
20
ns
11
th(SOMI)M
Hold time, SPISOMI valid after
SPICLK
0
0
ns
23
td(SPC)M
Delay time, SPISTE active to
SPICLK
tc(SPC) – 10
tc(SPC) – 10
ns
24
td(STE)M
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC) – 10
0.5tc(SPC) –
0.5tc(LSPCLK) – 10
ns
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
Master Out Data Is Valid
SPISIMO
10
11
Master In Data Must
Be Valid
SPISOMI
24
23
SPISTE
Figure 7-17. SPI Master Mode External Timing (Clock Phase = 1)
58
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7.9.4.5.2 Slave Mode Timing
Section 7.9.4.5.2.1 lists the slave mode timing (clock phase = 0) and Section 7.9.4.5.2.2 lists the slave mode
timing (clock phase = 1). Figure 7-18 and Figure 7-19 show the timing waveforms.
7.9.4.5.2.1 SPI Slave Mode External Timing (Clock Phase = 0) (1) (2) (4) (3) (5)
NO.
PARAMETER
MIN
MAX
UNIT
12
tc(SPC)S
Cycle time, SPICLK
4tc(SYSCLK)
ns
13
tw(SPC1)S
Pulse duration, SPICLK first pulse
2tc(SYSCLK) – 1
ns
2tc(SYSCLK) – 1
14
tw(SPC2)S
Pulse duration, SPICLK second pulse
15
td(SOMI)S
Delay time, SPICLK to SPISOMI valid
ns
20
ns
16
tv(SOMI)S
Valid time, SPISOMI data valid after SPICLK
0
ns
19
tsu(SIMO)S
Setup time, SPISIMO valid before SPICLK
1.5tc(SYSCLK)
ns
20
th(SIMO)S
Hold time, SPISIMO data valid after SPICLK
1.5tc(SYSCLK)
ns
25
tsu(STE)S
Setup time, SPISTE active before SPICLK
1.5tc(SYSCLK)
ns
26
th(STE)S
Hold time, SPISTE inactive after SPICLK
1.5tc(SYSCLK)
ns
(1)
(2)
(3)
(4)
(5)
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
tc(LCO) = LSPCLK cycle time
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
SPISOMI
16
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
25
26
SPISTE
Figure 7-18. SPI Slave Mode External Timing (Clock Phase = 0)
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
7.9.4.5.2.2 SPI Slave Mode External Timing (Clock Phase = 1) (1) (2) (3) (4)
NO.
PARAMETER
MIN
12
tc(SPC)S
Cycle time, SPICLK
13
tw(SPC1)S
14
tw(SPC2)S
17
td(SOMI)S
Delay time, SPICLK to SPISOMI valid
18
tv(SOMI)S
Valid time, SPISOMI data valid after SPICLK
21
tsu(SIMO)S
22
th(SIMO)S
25
26
(1)
(2)
(3)
(4)
MAX
UNIT
4tc(SYSCLK)
ns
Pulse duration, SPICLK first pulse
2tc(SYSCLK) – 1
ns
Pulse duration, SPICLK second pulse
2tc(SYSCLK) – 1
ns
20
ns
0
ns
Setup time, SPISIMO valid before SPICLK
1.5tc(SYSCLK)
ns
Hold time, SPISIMO data valid after SPICLK
1.5tc(SYSCLK)
ns
tsu(STE)S
Setup time, SPISTE active before SPICLK
1.5tc(SYSCLK)
ns
th(STE)S
Hold time, SPISTE inactive after SPICLK
1.5tc(SYSCLK)
ns
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
SPISOMI
Data Valid
SPISOMI Data Is Valid
Data Valid
18
21
22
SPISIMO Data
Must Be Valid
SPISIMO
26
25
SPISTE
Figure 7-19. SPI Slave Mode External Timing (Clock Phase = 1)
60
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
7.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
7.9.4.6.1 McBSP Transmit and Receive Timing
7.9.4.6.1.1 McBSP Timing Requirements (1) (2)
NO.
MIN
McBSP module clock (CLKG, CLKX, CLKR) range
Cycle time, CLKR/X
CLKR/X ext
2P
P–4
M12
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
tr(CKRX)
Rise time, CLKR/X
CLKR/X ext
M14
tf(CKRX)
Fall time, CLKR/X
CLKR/X ext
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
M16
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
M17
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
M18
th(CKRL-DRV)
Hold time, DR valid after CLKR low
M19
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
M20
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
(1)
(2)
(3)
CLKR int
20
CLKR ext
2
CLKR int
0
CLKR ext
6
CLKR int
20
CLKR ext
2
CLKR int
0
CLKR ext
6
CLKX int
20
CLKX ext
2
CLKX int
0
CLKX ext
6
MHz
ns
1
tc(CKRX)
M13
(3)
25
M11
UNIT
kHz
40
McBSP module cycle time (CLKG, CLKX, CLKR) range
M15
MAX
1
ms
ns
ns
4
ns
4
ns
ns
ns
ns
ns
ns
ns
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
CLKSRG
2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = (1 ) CLKGDV) CLKSRG can be LSPCLK, CLKX,
CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (40 MHz).
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7.9.4.6.1.2 McBSP Switching Characteristics (1) (2)
NO.
M1
PARAMETER
tc(CKRX)
MIN
Cycle time, CLKR/X
ns
ns
C + 2 (3)
ns
Pulse duration, CLKR/X high
CLKR/X int
D–2
tw(CKRXL)
Pulse duration, CLKR/X low
CLKR/X int
C – 2 (3)
M4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
M5
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
M6
tdis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance
following last data bit
CLKX int
8
CLKX ext
14
Delay time, CLKX high to DX valid.
CLKX int
4
This applies to all bits except the first bit transmitted.
CLKX ext
20
td(CKXH-DXV)
Delay time, CLKX high to DX valid
DXENA = 0
M8
ten(CKXH-DX)
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or DXENA = 1
10b) modes
Delay time, FSX high to DX valid
M9
td(FXH-DXV)
ten(FXH-DX)
DXENA = 0
Only applies to first bit transmitted when
DXENA = 1
in Data Delay 0 (XDATDLY=00b) mode.
Enable time, FSX high to DX driven
M10
DXENA = 0
DXENA = 0
Only applies to first bit transmitted when
DXENA = 1
in Data Delay 0 (XDATDLY=00b) mode
D+2
CLKR int
0
4
CLKR ext
3
20
CLKX int
0
4
CLKX ext
3
20
CLKX int
4
CLKX ext
20
CLKX int
P+4
CLKX ext
P + 20
CLKX int
0
CLKX ext
10
CLKX int
P
CLKX ext
P + 10
UNIT
(3)
tw(CKRXH)
Enable time, CLKX high to DX driven
62
(3)
MAX
M3
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or DXENA = 1
10b) modes
(2)
(3)
2P
M2
M7
(1)
CLKR/X int
ns
ns
ns
ns
ns
FSX int
4
FSX ext
16
FSX int
P+4
FSX ext
ns
P + 16
FSX int
0
FSX ext
6
FSX int
P
FSX ext
P+6
ns
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
2P = 1/CLKG in ns.
C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
M1, M11
M2, M12
M13
M3, M12
CLKR
M4
M4
M14
FSR (int)
M15
M16
FSR (ext)
M18
M17
DR
(RDATDLY=00b)
Bit (n−1)
(n−2)
(n−3)
M17
(n−4)
M18
DR
(RDATDLY=01b)
Bit (n−1)
(n−2)
(n−3)
M17
M18
DR
(RDATDLY=10b)
Bit (n−1)
(n−2)
Figure 7-20. McBSP Receive Timing
M1, M11
M2, M12
M13
M3, M12
CLKX
M5
M5
FSX (int)
M19
M20
FSX (ext)
M9
M7
M10
DX
(XDATDLY=00b)
Bit 0
Bit (n−1)
(n−2)
(n−3)
M7
M8
DX
(XDATDLY=01b)
Bit 0
Bit (n−1)
M7
M6
DX
(XDATDLY=10b)
(n−2)
M8
Bit 0
Bit (n−1)
Figure 7-21. McBSP Transmit Timing
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
7.9.4.6.2 McBSP as SPI Master or Slave Timing
7.9.4.6.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1)
NO.
M30
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
M31
th(CKXL-DRV)
Hold time, DR valid after CLKX low
M32
tsu(BFXL-CKXH)
Setup time, FSX low before CLKX high
M33
tc(CKX)
Cycle timez, CLKX
(1)
(2)
MASTER
SLAVE
MIN
MIN
MAX
30
MAX
8P – 10
1
UNIT
ns
8P – 10
ns
8P + 10
ns
16P
ns
2P(2)
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
2P = 1/CLKG
7.9.4.6.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
NO.
(1)
MASTER
PARAMETER
MIN
SLAVE
MAX
MIN
MAX
2P(1)
UNIT
M24
th(CKXL-FXL)
Hold time, FSX low after CLKX low
ns
M25
td(FXL-CKXH)
Delay time, FSX low to CLKX high
P
M26
td(CLKXH-DXV)
Delay time, CLKX low to DX valid
–2
M28
tdis(FXH-DXHZ)
Disable time, DX high impedance following
last data bit from FSX high
6
6P + 6
ns
M29
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
ns
0
3P + 6
5P + 20
ns
2P = 1/CLKG
M32
LSB
M33
MSB
CLKX
M25
M24
FSX
M28
M29
M26
DX
Bit 0
Bit(n-1)
M30
DR
Bit 0
(n-2)
(n-3)
(n-4)
M31
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 7-22. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
64
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
7.9.4.6.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) (1)
MASTER
NO.
MIN
M39
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
M40
th(CKXH-DRV)
Hold time, DR valid after CLKX high
M41
tsu(FXL-CKXH)
Setup time, FSX low before CLKX high
M42
tc(CKX)
Cycle time, CLKX
(1)
(2)
SLAVE
MAX
MIN
MAX
UNIT
30
8P – 10
ns
1
8P – 10
ns
16P + 10
ns
16P
ns
2P(2)
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
2P = 1/CLKG
7.9.4.6.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
NO.
MASTER
PARAMETER
MIN
SLAVE
MAX
MIN
MAX
UNIT
M34
th(CKXL-FXL)
Hold time, FSX low after CLKX low
P
ns
M35
td(FXL-CKXH)
Delay time, FSX low to CLKX high
2P(1)
ns
M36
td(CLKXL-DXV)
Delay time, CLKX low to DX valid
M37
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX low
M38
td(FXL-DXV)
Delay time, FSX low to DX valid
(1)
–2
0
3P + 6
5P + 20
ns
P+6
7P + 6
ns
6
4P + 6
ns
2P = 1/CLKG
LSB
M42
MSB
M41
CLKX
M34
M35
FSX
M37
DX
M38
Bit 0
M36
Bit(n-1)
M39
DR
Bit 0
(n-2)
(n-3)
(n-4)
M40
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 7-23. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
7.9.4.6.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) (1)
NO.
M49
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
M50
th(CKXH-DRV)
Hold time, DR valid after CLKX high
M51
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
M52
tc(CKX)
Cycle time, CLKX
(1)
(2)
MASTER
SLAVE
MIN
MIN
MAX
MAX
UNIT
30
8P – 10
ns
1
8P – 10
ns
8P + 10
ns
16P
ns
2P(2)
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
2P = 1/CLKG
7.9.4.6.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
NO.
PARAMETER
MASTER
SLAVE
MIN
MIN
MAX
MAX
UNIT
2P(1)
ns
Delay time, FSX low to CLKX low
P
ns
td(CLKXL-DXV)
Delay time, CLKX low to DX valid
–2
M47
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
M48
td(FXL-DXV)
Delay time, FSX low to DX valid
M43
th(CKXH-FXL)
Hold time, FSX low after CLKX high
M44
td(FXL-CKXL)
M45
(1)
0
3P + 6 5P + 20
ns
6
6P + 6
ns
6
4P + 6
ns
2P = 1/CLKG
M51
LSB
M52
MSB
CLKX
M43
M44
FSX
M47
M48
M45
DX
Bit 0
Bit(n-1)
M49
DR
Bit 0
(n-2)
(n-3)
(n-4)
M50
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 7-24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
66
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
7.9.4.6.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) (1)
MASTER
NO.
MIN
M58
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
M59
th(CKXL-DRV)
Hold time, DR valid after CLKX low
M60
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
M61
tc(CKX)
Cycle time, CLKX
(1)
(2)
SLAVE
MAX
MIN
MAX
UNIT
30
8P – 10
ns
1
8P – 10
ns
16P + 10
ns
16P
ns
2P(2)
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
2P = 1/CLKG
7.9.4.6.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) (1)
NO.
MASTER(2)
PARAMETER
MIN
M53
th(CKXH-FXL)
Hold time, FSX low after CLKX high
M54
td(FXL-CKXL)
Delay time, FSX low to CLKX low
M55
td(CLKXH-DXV)
Delay time, CLKX high to DX valid
M56
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data
bit from CLKX high
M57
td(FXL-DXV)
Delay time, FSX low to DX valid
(1)
(2)
SLAVE
MAX
MIN
MAX
UNIT
P
ns
2P(1)
ns
–2
0
3P + 6
5P + 20
ns
P+6
7P + 6
ns
6
4P + 6
ns
2P = 1/CLKG
C = CLKX low pulse width = P
D = CLKX high pulse width = P
M60
LSB
M61
MSB
CLKX
M53
M54
FSX
M56
DX
M55
M57
Bit 0
Bit(n-1)
M58
DR
Bit 0
(n-2)
(n-3)
(n-4)
M59
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 7-25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
7.9.5 Emulator Connection Without Signal Buffering for the MCU
Figure 7-26 shows the connection between the MCU and JTAG header for a single-processor configuration. If
the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals must be
buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 7-26 shows the simpler,
no-buffering situation. For the pullup/pulldown resistor values, see the pin description section. For details on
buffering JTAG signals and multiple processor connections, see the TMS320F/C24x DSP controllers CPU and
instruction set reference guide.
6 inches or less
VDDIO
VDDIO
5
13
EMU0
EMU0
PD
14
EMU1
EMU1
4
2
TRST
TRST
GND
TMS
GND
TDI
GND
TDO
GND
TCK
GND
6
1
TMS
8
3
TDI
10
7
TDO
12
11
TCK
9
TCK_RET
MCU
JTAG Header
Figure 7-26. Emulator Connection Without Signal Buffering for the MCU
68
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
7.9.6 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail
wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 7-2 shows the
relationship between the parameters configured in the XTIMING register and the duration of the pulse in terms of
XTIMCLK cycles.
Table 7-2. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DURATION (ns)(1) (2)
DESCRIPTION
X2TIMING = 0
X2TIMING = 1
LR
Lead period, read access
XRDLEAD × tc(XTIM)
(XRDLEAD × 2) × tc(XTIM)
AR
Active period, read access
(XRDACTIVE + WS + 1) × tc(XTIM)
(XRDACTIVE × 2 + WS + 1) × tc(XTIM)
TR
Trail period, read access
XRDTRAIL × tc(XTIM)
(XRDTRAIL × 2) × tc(XTIM)
LW
Lead period, write access
XWRLEAD × tc(XTIM)
(XWRLEAD × 2) × tc(XTIM)
AW
Active period, write access
(XWRACTIVE + WS + 1) × tc(XTIM)
(XWRACTIVE × 2 + WS + 1) × tc(XTIM)
TW
Trail period, write access
XWRTRAIL × tc(XTIM)
(XWRTRAIL × 2) × tc(XTIM)
(1)
(2)
tc(XTIM) − Cycle time, XTIMCLK
WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY = 0), then WS = 0.
Minimum wait-state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No internal
device hardware is included to detect illegal settings.
7.9.6.1 USEREADY = 0
If the XREADY signal is ignored (USEREADY = 0), then:
Lead:
LR ≥ 2 × tc(XTIM)
Active:
AR ≥ 6 × tc(XTIM)
Trail:
TW ≥ 3 × tc(XTIM)
LW ≥ 3 × tc(XTIM)
AW ≥ 1 × tc(XTIM)
These requirements result in the following XTIMING register configuration restrictions:
XRDLEAD
XRDACTIVE
≥2
(1)
(2)
XRDTRAIL
≥6
XWRLEAD
≥0
≥
XWRACTIVE
3(2)
≥1
XWRTRAIL
≥
X2TIMING
3(2)
0(1)
If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
Lead and trail write must be at least 7.5 ns.
Examples of valid and invalid timing when not sampling XREADY:
(1)
(2)
(3)
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid(1)
0
0
0
0
0
0
0, 1
Valid(2)
2
6
0
3
1
3
0(3)
No hardware to detect illegal XTIMING configurations
Based on 300-MHz system clock speed.
If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
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7.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then:
1
Lead:
LR ≥ 2 × tc(XTIM)
LW ≥ 3 × tc(XTIM)
2
Active:
3
Trail:
AR ≥ 6 × tc(XTIM)
AW ≥ 2 × tc(XTIM)
TW ≥ 3 × tc(XTIM)
Note
Restriction does not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions (based on 300-MHz
system clock speed):
(1)
(2)
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥2
≥6
≥0
≥ 3(2)
≥2
≥ 3(2)
0(1)
If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
Lead and trail write must be at least 7.5 ns.
Examples of valid and invalid timing when using synchronous XREADY:
(1)
(2)
(3)
70
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid(1)
0
0
0
0
0
0
0, 1
Invalid(1)
1
0
0
1
0
0
0, 1
Valid(2)
2
6
0
3
2
3
0(3)
No hardware to detect illegal XTIMING configurations
Based on 300-MHz system clock speed
If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
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7.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1, READYMODE = 1), then:
1
Lead:
LR ≥ 2 × tc(XTIM)
LW ≥ 3 × tc(XTIM)
2
Active:
3
Trail:
AR ≥ 6 × tc(XTIM)
AW ≥ 4 × tc(XTIM)
TW ≥ 3 × tc(XTIM)
Note
Restrictions do not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions (based on 300-MHz
system clock speed):
(1)
(2)
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥2
≥6
0
≥ 3(2)
≥4
≥3(2)
0(1)
If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
Lead and trail write must be at least 7.5 ns.
Examples of valid and invalid timing when using asynchronous XREADY:
(1)
(2)
(3)
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid(1)
0
0
0
0
0
0
0, 1
Invalid(1)
1
0
0
1
0
0
0, 1
Invalid(1)
1
1
0
1
1
0
0
Valid(2)
2
6
0
3
4
3
0(3)
No hardware to detect illegal XTIMING configurations
Based on 300-MHz system clock speed
If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
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Unless otherwise specified, all XINTF timing is applicable for the clock configurations listed in Table 7-3.
Table 7-3. XINTF Clock Configurations for SYSCLKOUT = 300 MHz
MODE
1
Example:
XCLKOUT(1)
SYSCLKOUT
SYSCLKOUT
300 MHz
300 MHz
SYSCLKOUT
1/2 SYSCLKOUT
300 MHz
150 MHz
SYSCLKOUT
1/2 SYSCLKOUT
300 MHz
150 MHz
SYSCLKOUT
1/4 SYSCLKOUT
300 MHz
2
Example:
300 MHz
3
Example:
300 MHz
4
Example:
300 MHz
5
Example:
300 MHz
75 MHz
1/2 SYSCLKOUT
1/2 SYSCLKOUT
300 MHz
6
Example:
150 MHz
150 MHz
1/2 SYSCLKOUT
1/4 SYSCLKOUT
300 MHz
7
Example:
150 MHz
75 MHz
1/2 SYSCLKOUT
1/4 SYSCLKOUT
300 MHz
8
Example:
(1)
XTIMCLK
SYSCLKOUT
150 MHz
75 MHz
1/2 SYSCLKOUT
1/8 SYSCLKOUT
150 MHz
37.5 MHz
300 MHz
The XCLKOUT signal is limited to a maximum frequency of 75 MHz.
The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 7-27.
PCLKR3[XINTFENCLK]
XTIMING0
0
XTIMING6
0
1
LEAD/ACTIVE/TRAIL
XTIMING7
XBANK
C28x
CPU
SYSCLKOUT
/2
1
0
XTIMCLK
XINTCNF2 (XTIMCLK)
/2
1
0
XINTCNF2
(CLKMODE)
/2
XCLKOUT
1
0
XINTCNF2
(BY4CLKMODE)
XINTCNF2
(CLKOFF)
Figure 7-27. Relationship Between SYSCLKOUT and XTIMCLK
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7.9.6.4 XINTF Signal Alignment to XCLKOUT
For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock XTIMCLK.
Strobes such as XRD, XWE0, XWE1, and zone chip-select ( XZCS) change state in relationship to the rising
edge of XTIMCLK. The external clock, XCLKOUT, can be configured to be equal to, one-half, or one-fourth the
frequency of XTIMCLK.
For the case where XCLKOUT = XTIMCLK, all of the XINTF strobes will change state with respect to the rising
edge of XCLKOUT. For the case where XCLKOUT = one-half or one-fourth XTIMCLK, some strobes will change
state either on the rising edge of XCLKOUT or the falling edge of XCLKOUT. In the XINTF timing tables, the
notation XCOHL is used to indicate that the parameter is with respect to either case; XCLKOUT rising edge
(high) or XCLKOUT falling edge (low). If the parameter is always with respect to the rising edge of XCLKOUT,
the notation XCOH is used.
For the case where XCLKOUT = one-half XTIMCLK, the XCLKOUT edge with which the change will be aligned
can be determined based on the number of XTIMCLK cycles from the start of the access to the point at which
the signal changes. If this number of XTIMCLK cycles is even, the alignment will be with respect to the rising
edge of XCLKOUT. If this number is odd, then the signal will change with respect to the falling edge of
XCLKOUT. Examples include the following:
• Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT. This is
because all XINTF accesses begin with respect to the rising edge of XCLKOUT.
Examples:
•
XRNWL
XR/ W active low
XRDL
XRD active low
XWEL
XWE1 or XWE0 active low
Strobes that change at the beginning of the trail period will align to the rising edge of XCLKOUT if the total
number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If the
number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will be
with respect to the falling edge of XCLKOUT.
Examples:
•
Zone chip-select active low
Strobes that change at the beginning of the active period will align to the rising edge of XCLKOUT if the total
number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK cycles is odd, then
the alignment will be with respect to the falling edge of XCLKOUT.
Examples:
•
XZCSL
XRDH
XRD inactive high
XWEH
XWE1 or XWE0 inactive high
Strobes that change at the end of the access will align to the rising edge of XCLKOUT if the total number of
lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number of lead + active +
trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will be with respect to the
falling edge of XCLKOUT.
Examples:
XZCSH
Zone chip-select inactive high
XRNWH
XR/ W inactive high
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7.9.6.5 External Interface Read Timing
7.9.6.5.1 External Interface Read Timing Requirements
MIN
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active low
tsu(XD)XRD
Setup time, read data valid before XRD strobe inactive high
th(XD)XRD
Hold time, read data valid after XRD inactive high
(1)
MAX
UNIT
(LR + AR) – 13.5 (1)
ns
AR – 13 (1)
ns
13
ns
0
ns
LR = Lead period, read access. AR = Active period, read access. See Table 7-2.
7.9.6.5.2 External Interface Read Switching Characteristics
PARAMETER
td(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low
MIN
MAX
0
2
UNIT
–0.2
0.9
ns
1.5
ns
ns
td(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive high
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
td(XCOHL-XRDL)
Delay time, XCLKOUT high/low to XRD active low
–0.2
0.8
ns
td(XCOHL-XRDH)
Delay time, XCLKOUT high/low to XRD inactive high
–0.4
0.8
ns
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
(1)
th(XA)XRD
Hold time, address valid after XRD inactive high
(1)
(1)
ns
ns
During inactive cycles, the XINTF address bus always holds the last address put out on the bus . This includes alignment cycles.
(A)(B)
Trail
Active
Lead
(C)
(D)
XCLKOUT = XTIMCLK
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
XZCS0, XZCS6, XZCS7
td(XCOH-XA)
XA[0:19]
XRD
td(XCOHL-XRDH)
td(XCOHL-XRDL)
(E)
XWE, XWE1
tsu(XD)XRD
XR/W
ta(A)
th(XD)XRD
ta(XRD)
XD[0:31], XD[0:15]
XREADY
DIN
(F)
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before
an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which remains high.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is used in 32-bit data bus mode.
F. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 7-28. Example Read Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
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(1)
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XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥2
≥5
≥0
0
0
N/A(1)
N/A(1)
N/A(1)
N/A(1)
N/A = Not applicable (or “Don’t care”) for this example
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7.9.6.6 External Interface Write Timing
7.9.6.6.1 External Interface Write Switching Characteristics
PARAMETER
td(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low
td(XCOHL-XZCSH)
Delay time, XCLKOUT high or low to zone chip-select inactive high
MIN
MAX
0
2
ns
–0.2
0.9
ns
1.5
ns
0.7
ns
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
td(XCOHL-XWEL)
Delay time, XCLKOUT high/low to XWE0, XWE1 low
–0.3
UNIT
td(XCOHL-XWEH)
Delay time, XCLKOUT high/low to XWE0, XWE1 high
–0.5
0.5
ns
td(XCOH-XRNWL)
Delay time, XCLKOUT high to XR/ W low
–0.2
1.5
ns
td(XCOHL-XRNWH)
Delay time, XCLKOUT high/low to XR/ W high
0.3
0.6
ns
ten(XD)XWEL
Enable time, data bus driven from XWE0, XWE1 low
–7.5
td(XWEL-XD)
Delay time, data valid after XWE0, XWE1 active low
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
(1)
th(XD)XWE
Hold time, write data valid after XWE0, XWE1 inactive high
TW – 7.5 (2)
tdis(XD)XRNW
Maximum time for processor to release the data bus after XR/ W inactive high
(1)
(2)
ns
0
4
ns
ns
ns
0
ns
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which remains high.
This includes alignment cycles.
TW = Trail period, write access. See Table 7-2.
(A) (B)
Lead
Active
Trail
(C)
(D)
XCLKOUT = XTIMCLK
XZCS0, XZCS6, XZCS7
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
td(XCOH-XA)
XA[0:19]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
(E)
XWE0, XWE1
XR/W
XD[0:31], XD[0:15]
XREADY
td(XCOHL-XRNWH)
td(XCOH-XRNWL)
tdis(XD)XRNW
th(XD)XWEH
td(XWEL-XD)
ten(XD)XWEL
DOUT
(F)
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before
an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which remains high.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is used in 32-bit data bus mode.
F. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 7-29. Example Write Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
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XRDLEAD
N/A(1)
(1)
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XRDACTIVE
N/A(1)
XRDTRAIL
N/A(1)
USEREADY
0
X2TIMING
0
XWRLEAD
≥3
XWRACTIVE
≥1
XWRTRAIL
READYMODE
≥3
N/A(1)
N/A = Not applicable (or “Don’t care”) for this example
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7.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
7.9.6.7.1 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
PARAMETER
td(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low
td(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive high
MIN
MAX
0
2
UNIT
ns
–0.2
0.9
ns
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
1.5
ns
td(XCOHL-XRDL)
Delay time, XCLKOUT high/low to XRD active low
–0.2
0.8
ns
td(XCOHL-XRDH)
Delay time, XCLKOUT high/low to XRD inactive high
–0.4
0.8
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
(1)
ns
th(XA)XRD
Hold time, address valid after XRD inactive high
(1)
ns
(1)
ns
During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
7.9.6.7.2 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
MIN
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active low
tsu(XD)XRD
Setup time, read data valid before XRD strobe inactive high
th(XD)XRD
Hold time, read data valid after XRD inactive high
(1)
MAX
UNIT
(1)
ns
AR – 13 (1)
ns
(LR + AR) – 13.5
13
ns
0
ns
LR = Lead period, read access. AR = Active period, read access. See Table 7-2.
7.9.6.7.3 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State) (1)
MIN
tsu(XRDYsynchL)XCOHL
Setup time, XREADY (synchronous) low before XCLKOUT high/low
th(XRDYsynchL)
Hold time, XREADY (synchronous) low
MAX
UNIT
8
ns
1tc(XTIM)
ns
tsu(XRDYsynchH)XCOHL
Setup time, XREADY (synchronous) high before XCLKOUT high/low
8
ns
th(XRDYsynchH)XZCSH
Hold time, XREADY (synchronous) held high after zone chip select high
0
ns
(1)
The first XREADY (synchronous) sample occurs with respect to E in Figure 7-30:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will finish. If XREADY (synchronous) is found to be
low, it is sampled again each tc(XTIM) until it is found to be high.
For each sample (n) the setup time (F) with respect to the beginning of the access can be calculated as:
F = (XRDLEAD + XRDACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
7.9.6.7.4 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
MIN
tsu(XRDYAsynchL)XCOHL
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
MAX
8
UNIT
ns
th(XRDYAsynchL)
Hold time, XREADY (asynchronous) low
1tc(XTIM)
ns
tsu(XRDYAsynchH)XCOHL
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
8
ns
th(XRDYasynchH)XZCSH
Hold time, XREADY (asynchronous) held high after zone chip select high
0
ns
78
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WS (Synch)
(A) (B)
Active
Lead
(C)
Trail
(D)
XCLKOUT = XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0, XZCS6, XZCS7
td(XCOH-XA)
XA[0:19]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
XWE0, XWE1 (E)
ta(XRD)
XR/W
ta(A)
th(XD)XRD
XD[0:31], XD[0:15]
DIN
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
th(XRDYsynchH)XZCSH
tsu(XRDHsynchH)XCOHL
XREADY(Synch)
(F)
(G)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before
an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is valid only in 32-bit data bus mode.
F. For each sample, setup time from the beginning of the access (E) can be calculated as: D = (XRDLEAD + XRDACTIVE +n - 1) tc(XTIM) –
tsu(XRDYsynchL)XCOHL
G. Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE) tc(XTIM) where n is the sample number: n = 1,
2, 3, and so forth.
Figure 7-30. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD
≥2
(1)
XRDACTIVE
5
XRDTRAIL
≥0
USEREADY
1
X2TIMING
0
XWRLEAD
N/A(1)
XWRACTIVE
N/A(1)
XWRTRAIL
READYMODE
N/A(1)
0 = XREADY
(Synch)
N/A = “Don’t care” for this example
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WS (Async)
(A) (B)
Active
Lead
Trail
(C)
(D)
XCLKOUT = XTIMCLK
td(XCOH-XZCSL)
XZCS0, XZCS6, XZCS7
td(XCOHL-XZCSH)
td(XCOH-XA)
XA[0:19]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
XWE0, XWE1 (E)
ta(XRD)
XR/W
ta(A)
th(XD)XRD
DIN
XD[0:31], XD[0:15]
tsu(XRDYasynchL)XCOHL
th(XRDYasynchH)XZCSH
th(XRDYasynchL)
tsu(XRDYasynchH)XCOHL
XREADY(Asynch)
(F)
(G)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle
before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is valid only in 32-bit data bus mode.
F. For each sample, setup time from the beginning of the access can be calculated as: E = (XRDLEAD + XRDACTIVE -3 +n) tc(XTIM) –
tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth.
G. Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE –2) tc(XTIM)
Figure 7-31. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD
≥2
(1)
80
XRDACTIVE
XRDTRAIL
5
≥0
USEREADY
1
X2TIMING
0
XWRLEAD
N/A(1)
XWRACTIVE
N/A(1)
XWRTRAIL
READYMODE
N/A(1)
1 = XREADY
(Async)
N/A = “Don’t care” for this example
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7.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
7.9.6.8.1 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
PARAMETER
td(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low
td(XCOHL-XZCSH)
Delay time, XCLKOUT high or low to zone chip-select inactive high
MIN
MAX
0
2
UNIT
ns
–0.2
0.9
ns
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
1.5
ns
td(XCOHL-XWEL)
Delay time, XCLKOUT high/low to XWE0, XWE1 low(3)
–0.3
0.7
ns
td(XCOHL-XWEH)
Delay time, XCLKOUT high/low to XWE0, XWE1 high(3)
–0.5
0.5
ns
td(XCOH-XRNWL)
Delay time, XCLKOUT high to XR/ W low
–0.2
1.5
ns
td(XCOHL-XRNWH)
Delay time, XCLKOUT high/low to XR/ W high
0.3
0.6
ns
ten(XD)XWEL
Enable time, data bus driven from XWE0, XWE1 low
–7.5
td(XWEL-XD)
Delay time, data valid after XWE0, XWE1 active low
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
0
high(3)
th(XD)XWE
Hold time, write data valid after XWE0, XWE1 inactive
tdis(XD)XRNW
Maximum time for processor to release the data bus after XR/ W
inactive high
(1)
(2)
(3)
ns
TW – 7.5
4
ns
(1)
ns
(2)
ns
0
ns
During inactive cycles, the XINTF address bus always holds the last address put out on the bus . This includes alignment cycles.
TW = trail period, write access (see Table 7-2)
XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
7.9.6.8.2 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State) Table 8-23
MIN
MAX
8
UNIT
tsu(XRDYsynchL)XCOHL
Setup time, XREADY (synchronous) low before XCLKOUT high/low
ns
th(XRDYsynchL)
Hold time, XREADY (synchronous) low
1tc(XTIM)
ns
tsu(XRDYsynchH)XCOHL
Setup time, XREADY (synchronous) high before XCLKOUT high/low
8
ns
th(XRDYsynchH)XZCSH
Hold time, XREADY (synchronous) held high after zone chip select high
0
ns
7.9.6.8.3 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State) (1)
MIN
UNIT
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
th(XRDYasynchL)
Hold time, XREADY (asynchronous) low
1tc(XTIM)
ns
tsu(XRDYasynchH)XCOHL
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
8
ns
th(XRDYasynchH)XZCSH
Hold time, XREADY (asynchronous) held high after zone chip select high
0
ns
(1)
8
MAX
tsu(XRDYasynchL)XCOHL
ns
The first XREADY (synchronous) sample occurs with respect to E in Figure 7-32:
E = (XWRLEAD + XWRACTIVE –2) tc(XTIM). When first sampled, if XREADY (asynchronous) is high, then the access will complete. If
XREADY (asynchronous) is low, it is sampled again each tc(XTIM) until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE –3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
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WS (Synch)
(A) (B)
(C)
Trail
Active
Lead 1
(D)
XCLKOUT = XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0, XZCS6, XZCS7
th(XRDYsynchH)XZCSH
td(XCOH-XA)
XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
XWE
td(XCOHL-XRNWH)
td(XCOH-XRNWL)
XR/W
tdis(XD)XRNW
td(XWEL-XD
th(XD)XWEH
)
ten(XD)XWEL
XD[0:15]
DOUT
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
tsu(XRDHsynchH)XCOHL
XREADY (Synch)
(E)
(F)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before
an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is used in 32-bit data bus mode only.
F. For each sample, setup time from the beginning of the access can be calculated as E = (XWRLEAD + XWRACTIVE + n –1) tc(XTIM) –
tsu(XRDYsynchL)XCOH where n is the sample number: n = 1, 2, 3, and so forth.
G. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE) tc(XTIM)
Figure 7-32. Write With Synchronous XREADY Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD
N/A(1)
(1)
82
XRDACTIVE
N/A(1)
XRDTRAIL
N/A(1)
USEREADY
1
X2TIMING
0
XWRLEAD
≥3
XWRACTIVE
1
XWRTRAIL
READYMODE
≥3
0 = XREADY
(Synch)
N/A = "Don't care" for this example.
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WS (Async)
(A) (B)
(C)
Trail
Active
Lead 1
(D)
XCLKOUT = XTIMCLK
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
th(XRDYasynchH)XZCSH
XZCS0, XZCS6, XZCS7
XA[0:19]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
(E)
XWE0, XWE1
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
XR/W
tdis(XD)XRNW
td(XWEL-XD
th(XD)XWEH
)
ten(XD)XWEL
XD[31:0], XD[15:0]
DOUT
tsu(XRDYasynchL)XCOHL
th(XRDYasynchL)
tsu(XRDYasynchH)XCOHL
XREADY(Asynch)
(F)
(G)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before
an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is used in 32-bit data bus mode only.
F. For each sample, set up time from the beginning of the access can be calculated as: E = (XWRLEAD + XWRACTIVE -3 + n) tc(XTIM) –
tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth.
G. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)
Figure 7-33. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD
N/A(1)
(1)
XRDACTIVE
N/A(1)
XRDTRAIL
N/A(1)
USEREADY
1
X2TIMING
0
XWRLEAD
≥3
XWRACTIVE
3
XWRTRAIL
READYMODE
≥3
1 = XREADY
(Async)
N/A = “Don’t care” for this example
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7.9.6.9 XHOLD and XHOLDA Timing
If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of highimpedance mode.
On a reset ( XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the bus
and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active low.
When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still execute
code from internal memory. If an access is made to the external interface, the CPU is stalled until the XHOLD
signal is removed.
An external DMA request, when granted, places the following signals in a high-impedance mode:
XA[19:0]
XZCS0
XD[31:0], XD[15:0]
XZCS6
XWE0, XWE1, XRD
XZCS7
XR/ W
All other signals not listed in this group remain in their default or functional operational modes during these
signal events.
84
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7.9.6.9.1 XHOLD/ XHOLDA Timing Requirements (1) (2) (3)
MIN
td(HL-HiZ)
MAX
Delay time, XHOLD low to Hi-Z on all address, data, and control
4tc(XTIM) + tc(XCO) + 20
UNIT
ns
td(HL-HAL)
Delay time, XHOLD low to XHOLDA low
4tc(XTIM) + 2tc(XCO) + 20
ns
td(HH-HAH)
Delay time, XHOLD high to XHOLDA high
4tc(XTIM) + 20
ns
td(HH-BV)
Delay time, XHOLD high to bus valid
6tc(XTIM) + 20
ns
(1)
(2)
(3)
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
The state of XHOLD is latched on the rising edge of XTIMCLK.
After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions occur with respect to the rising edge of
XCLKOUT. Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the
maximum value specified.
XCLKOUT
td(HL-Hiz)
XHOLD
td(HH-HAH)
XHOLDA
td(HL-HAL)
td(HH-BV)
XR/W
High-Impedance
XZCS0, XZCS6, XZCS7
XA[19:0]
Valid
XD[31:0], XD[15:0]
Valid
High-Impedance
Valid
(A)
(B)
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 7-34. External Interface Hold Waveform
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8 Detailed Description
8.1 Brief Descriptions
8.1.1 C28x CPU
The C2834x (C28x+FPU) family is a member of the TMS320C2000™ microcontroller unit (MCU) platform. The
C28x+FPU based controllers have the same 32-bit fixed-point architecture as TI's existing C28x MCUs, but also
include a single-precision (32-bit) IEEE 754 floating-point unit (FPU). It is a very efficient C/C++ engine,
enabling users to develop their system control software in a high-level language. It also enables math algorithms
to be developed using C/C++. The device is as efficient at DSP math tasks as it is at system control tasks . This
efficiency removes the need for a second processor in many systems. The 32 × 32-bit MAC 64-bit processing
capabilities enable the controller to handle higher numerical resolution problems efficiently. Add to this the fast
interrupt response with automatic context save of critical registers, resulting in a device that is capable of
servicing many asynchronous events with minimal latency. The device has an 8-level-deep protected pipeline
with pipelined memory accesses. This pipelining enables it to execute at high speeds without resorting to
expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional
discontinuities. Special store conditional operations further improve performance.
8.1.2 Memory Bus (Harvard Bus Architecture)
As with many MCU type devices, multiple buses are used to move data between the memories and peripherals
and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write
bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write buses
consist of 32 address lines and 32 data lines each. The 32-bit-wide data buses enable single cycle 32-bit
operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an
instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to
the memory bus will prioritize memory accesses. Generally, the priority of memory bus accesses can be
summarized as follows:
Highest:
Data Writes
(Simultaneous data and program writes cannot occur on the memory bus.)
Program Writes
(Simultaneous data and program writes cannot occur on the memory bus.)
Data Reads
Lowest:
Program Reads
(Simultaneous program reads and fetches cannot occur on the memory bus.)
Fetches
(Simultaneous program reads and fetches cannot occur on the memory bus.)
8.1.3 Peripheral Bus
To enable migration of peripherals between various TI MCU family of devices, the C2834x devices adopt a
peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various buses that
make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and
associated control signals. Three versions of the peripheral bus are supported. One version supports only 16-bit
accesses (called peripheral frame 2). Another version supports both 16- and 32-bit accesses (called peripheral
frame 1). The third version supports DMA access and both 16- and 32-bit accesses (called peripheral frame 3).
8.1.4 Real-Time JTAG and Analysis
The C2834x devices implement the standard IEEE 1149.1 JTAG interface. Additionally, the devices support realtime mode of operation whereby the contents of memory, peripheral and register locations can be modified while
the processor is running and executing code and servicing interrupts. The user can also single step through
nontime-critical code while enabling time-critical interrupts to be serviced without interference. The device
implements the real-time mode in hardware within the CPU. This is a feature unique to the C2834x device,
requiring no software monitor. Additionally, special analysis hardware is provided that allows setting of hardware
breakpoint or data/address watch-points and generate various user-selectable break events when a match
occurs.
8.1.5 External Interface (XINTF)
This asynchronous interface consists of 20 address lines, 32 data lines, and three chip-select lines. The chipselect lines are mapped to three external zones, Zones 0, 6, and 7. Each of the three zones can be programmed
86
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with a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for
extending wait states externally or not. The programmable wait state, chip-select and programmable strobe
timing enables glueless interface to external memories and peripherals.
8.1.6 M0, M1 SARAMs
All C2834x devices contain these two blocks of single access memory, each 1K × 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x
devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or
for data variables. The partitioning is performed within the linker. The C28x device presents a unified memory
map to the programmer. This makes for easier programming in high-level languages.
8.1.7 L0, L1, L2, L3, L4, L5, L6, L7, H0, H1, H2, H3, H4, H5 SARAMs
The 2834x has up to 256K × 16 single-access RAM (SARAM) divided up into the following categories:
L0, L1, L2, L3, L4, L5 SARAM Blocks
Up to 48K × 16 of SARAM at all frequencies. Each block is 8K × 16.
L6, L7 SARAM Blocks
These 8K × 16 SARAM blocks are single-wait state at all frequencies.
H0, H1, H2, H3, H4, H5 SARAM Blocks
H0–H5 are each 32K × 16 and 1-wait state at all frequencies. A program-access
prefetch buffer is used to improve performance of linear code.
All SARAM blocks are mapped to both program and data space. L0–L7 are accessible by both the CPU and the
DMA (1 wait state).
8.1.8 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the
bootloader software what boot mode to use on power up. The user can select to boot normally or to download
new software from an external connection or to select boot software that is programmed in the internal ROM.
The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math related algorithms.
Table 8-1. Boot Mode Selection
(1)
(2)
MODE(1)
MODE
GPIO87/XA15
GPIO86/XA14
GPIO85/XA13
GPIO84/XA12
F
1
1
1
1
Secure boot(2)
E
1
1
1
0
SCI-A boot
D
1
1
0
1
SPI-A boot
C
1
1
0
0
I2C-A boot Timing 1
B
1
0
1
1
eCAN-A boot Timing 1
A
1
0
1
0
McBSP-A boot
9
1
0
0
1
Jump to XINTF x16
8
1
0
0
0
Reserved
7
0
1
1
1
eCAN-A boot Timing 2
6
0
1
1
0
Parallel GPIO I/O boot
5
0
1
0
1
Parallel XINTF boot
4
0
1
0
0
Jump to SARAM
3
0
0
1
1
Branch to check boot mode
2
0
0
1
0
I2C-A boot Timing 2
1
0
0
0
1
Reserved
0
0
0
0
0
TI Test Only
All four GPIO pins have an internal pullup.
This mode is available on secure devices only. See Section 8.1.9, Security.
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8.1.9 Security
The 128-bit password locations on these devices will always read back 0xFFFF. To preserve compatibility with
other C28x designs with code security, the password locations at 0x33FFF8–0x33FFFF must be read after a
device reset; otherwise, certain memory locations will be inaccessible. The Boot ROM code performs this read
during start-up. If during debug the Boot ROM is bypassed, then it is the responsibility of the application software
to read the password locations after a reset.
Custom Encryption: Activating the Code Security Module (CSM) and Emulation Code Security Logic
(ECSL)
Custom secure versions of these devices enable the CSM and ECSL logic. In the custom version, the 128-bit
password locations are set to a customer-chosen value, activating the Code Security Module (CSM), which
protects the Hx RAM memories from unauthorized access. Additionally, a TI-generated AES decryption routine is
embedded into an on-chip secure ROM, providing a method to secure application code that is stored externally.
Requests for custom secure versions are not accepted by TI anymore.
Note
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (Hx RAM) AND IS
WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS
AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY
PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.
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8.1.10 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block
can support up to 96 peripheral interrupts. On the C2834x, 64 of the possible 96 interrupts are used by
peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines
(INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that
can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes
eight CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond
to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can
be enabled or disabled within the PIE block.
8.1.11 External Interrupts (XINT1–XINT7, XNMI)
The devices support eight masked external interrupts (XINT1–XINT7, XNMI). XNMI can be connected to the
INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or both negative
and positive edge triggering and can also be enabled or disabled (including the XNMI). XINT1, XINT2, and XNMI
also contain a 16-bit free-running up counter, which is reset to zero when a valid interrupt edge is detected. This
counter can be used to accurately time-stamp the interrupt. Unlike the 281x devices, there are no dedicated pins
for the external interrupts. XINT1 XINT2, and XNMI interrupts can accept inputs from GPIO0–GPIO31 pins.
XINT3–XINT7 interrupts can accept inputs from GPIO32–GPIO63 pins.
8.1.12 Oscillator and PLL
The device can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A
PLL is provided supporting up to 31 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in
software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer to
Section 7.9.4.4 for timing details. The PLL block can be set in bypass mode.
8.1.13 Watchdog
The devices contain a watchdog timer. The user software must regularly reset the watchdog counter within a
certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can be
disabled if necessary.
8.1.14 Peripheral Clocking
The clocks to each individual peripheral can be enabled or disabled so as to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN) blocks can be
scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled from increasing CPU
clock speeds.
8.1.15 Low-Power Modes
The devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that
need to function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog
timer will wake the processor from IDLE mode.
STANDBY:
Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt
event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the
interrupt event
HALT:
Turns off the internal oscillator. This mode basically shuts down the device and places it in the lowest possible
power consumption mode. A reset or external signal can wake the device from this mode.
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8.1.16 Peripheral Frames 0, 1, 2, 3 (PFn)
The device segregates peripherals into four sections. The mapping of peripherals is as follows:
PF0:
PF1:
PF2:
PF3:
PIE:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
XINTF:
External Interface Registers
DMA
DMA Registers
Timers:
CPU-Timers 0, 1, 2 Registers
eCAN:
eCAN Mailbox and Control Registers
GPIO:
GPIO MUX Configuration and Control Registers
ePWM:
Enhanced Pulse Width Modulator Module and Registers
eCAP:
Enhanced Capture Module and Registers
eQEP:
Enhanced Quadrature Encoder Pulse Module and Registers
SYS:
System Control Registers
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
SPI:
Serial Port Interface (SPI) Control and RX/TX Registers
ADC:
External ADC Interface
I2C:
Inter-Integrated Circuit Module and Registers
XINT
External Interrupt Registers
McBSP
Multichannel Buffered Serial Port Registers
8.1.17 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with GPIO signals. This enables the user to use a pin as GPIO if
the peripheral signal or function is not used. On reset, GPIO pins are configured as inputs. The user can
individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also
select the number of input qualification cycles. This is to filter unwanted noise glitches. The GPIO signals can
also be used to bring the device out of specific low-power modes.
8.1.18 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. The
counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches
zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for Real-Time OS (RTOS)/
BIOS applications. It is connected to INT14 of the CPU. If DSP/BIOS™ or SYS/BIOS is not being used, CPUTimer 2 is available for general use. CPU-Timer 1 is for general use and can be connected to INT13 of the CPU.
CPU-Timer 0 is also for general use and is connected to the PIE block.
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8.1.19 Control Peripherals
The C2834x devices support the following peripherals which are used for embedded control and communication:
ePWM:
The enhanced PWM peripheral supports independent and complementary PWM generation, adjustable deadband generation for leading and trailing edges, latched and cycle-by-cycle trip mechanism. Some of the PWM
pins support HRPWM features.
eCAP:
The enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in
continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
eQEP:
The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed measurement using capture
unit and high-speed measurement using a 32-bit unit timer.
This peripheral has a watchdog timer to detect motor stall and input error detection logic to identify simultaneous
edge transition in QEP signals.
8.1.20 Serial Port Peripherals
The devices support the following serial communication peripherals:
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time-stamping of messages, and is
compliant with ISO 11898-1 (CAN 2.0B).
McBSP:
The multichannel buffered serial port (McBSP) connects to E1/T1 lines, phone-quality codecs for modem
applications or high-quality stereo audio DAC devices. The McBSP receive and transmit registers are supported
by the DMA to significantly reduce the overhead for servicing this peripheral. Each McBSP module can be
configured as an SPI as required.
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (1 to
16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the MCU and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs.
Multidevice communications are supported by the master/slave operation of the SPI. The SPI contains a 16-level
receive and transmit FIFO for reducing interrupt servicing overhead.
SCI:
The serial communications interface is a 2-wire asynchronous serial port, commonly known as UART. The SCI
contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.
I2C:
The inter-integrated circuit (I2C) module provides an interface between an MCU and other devices compliant with
Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus.
External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the MCU
through the I2C module. The I2C contains a 16-level receive and transmit FIFO for reducing interrupt servicing
overhead.
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8.2 Peripherals
The integrated peripherals are described in the following subsections:
• 6-channel Direct Memory Access (DMA)
• Three 32-bit CPU-Timers
• Up to nine enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6, ePWM7,
ePWM8, ePWM9)
• Up to six enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4, eCAP5, eCAP6)
• Up to three enhanced QEP modules (eQEP1, eQEP2, eQEP3)
• External analog-to-digital converter (ADC) Interface
• Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B)
• Up to three serial communications interface modules (SCI-A, SCI-B, SCI-C)
• Up to two serial peripheral interface (SPI) modules (SPI-A, SPI-D)
• Inter-integrated circuit (I2C) module
• Up to two multichannel buffered serial port (McBSP-A, McBSP-B) modules
• Digital I/O and shared pin functions
• External Interface (XINTF)
8.2.1 DMA Overview
Features:
• 6 channels with independent PIE interrupts
• Trigger sources:
– McBSP-A and McBSP-B transmit and receive logic
– XINT1–7 and XINT13
– CPU timers
– Software
• Data sources and destinations:
– L0–L7 64K × 16 SARAM
– All XINTF zones
– McBSP-A and McBSP-B transmit and receive buffers
• Word Size: 16-bit or 32-bit (McBSPs limited to 16-bit)
• Throughput: 4 cycles/word (5 cycles/word for McBSP reads)
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L0
I/F
L0 RAM
L1
I/F
L1 RAM
L2
I/F
L2 RAM
L3
I/F
L3 RAM
L4
I/F
L4 RAM
L5
I/F
L5 RAM
L6
I/F
L6 RAM
L7
I/F
L7 RAM
INT7
External
interrupts
CPU
timers
PIE
DINT[CH1:CH6]
XINTF zones interface
XINTF memory zones
CPU bus
McBSP A
Event
triggers
PF3
I/F
CPU
DMA
6-ch
McBSP B
DMA bus
Figure 8-1. DMA Functional Block Diagram
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8.2.2 32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
There are three 32-bit CPU-timers on the devices (CPU-Timer 0, CPU-Timer 1, CPU-Timer 2).
CPU-Timer 2 is reserved for DSP/BIOS or SYS/BIOS. CPU-Timer 0 and CPU-Timer 1 can be used in user
applications. These timers are different from the timers that are present in the ePWM modules.
Note
If the application is not using DSP/BIOS or SYS/BIOS, then CPU-Timer 2 can be used in the
application.
Reset
Timer Reload
16-Bit Timer Divide-Down
TDDRH:TDDR
32-Bit Timer Period
PRDH:PRD
16-Bit Prescale Counter
PSCH:PSC
SYSCLKOUT
TCR.4
(Timer Start Status)
32-Bit Counter
TIMH:TIM
Borrow
Borrow
TINT
Figure 8-2. CPU-Timers
The timer interrupt signals ( TINT0, TINT1, TINT2) are connected as shown in Figure 8-3.
INT1
to
INT12
PIE
TINT0
CPU-TIMER 0
28x
CPU
TINT1
CPU-TIMER 1
INT13
XINT13
INT14
TINT2
CPU-TIMER 2
(Reserved for
DSP/BIOS or SYS/BIOS)
A. The timer registers are connected to the memory bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 8-3. CPU-Timer Interrupt Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the value
in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the C28x.
When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in
Table 8-2 are used to configure the timers. For more information, see the TMS320x2834x Delfino System
Control and Interrupts Reference Guide .
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Table 8-2. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
ADDRESS
SIZE (x16)
TIMER0TIM
0x0C00
1
CPU-Timer 0, Counter Register
DESCRIPTION
TIMER0TIMH
0x0C01
1
CPU-Timer 0, Counter Register High
TIMER0PRD
0x0C02
1
CPU-Timer 0, Period Register
TIMER0PRDH
0x0C03
1
CPU-Timer 0, Period Register High
TIMER0TCR
0x0C04
1
CPU-Timer 0, Control Register
Reserved
0x0C05
1
TIMER0TPR
0x0C06
1
CPU-Timer 0, Prescale Register
TIMER0TPRH
0x0C07
1
CPU-Timer 0, Prescale Register High
TIMER1TIM
0x0C08
1
CPU-Timer 1, Counter Register
TIMER1TIMH
0x0C09
1
CPU-Timer 1, Counter Register High
TIMER1PRD
0x0C0A
1
CPU-Timer 1, Period Register
TIMER1PRDH
0x0C0B
1
CPU-Timer 1, Period Register High
TIMER1TCR
0x0C0C
1
CPU-Timer 1, Control Register
Reserved
0x0C0D
1
TIMER1TPR
0x0C0E
1
CPU-Timer 1, Prescale Register
TIMER1TPRH
0x0C0F
1
CPU-Timer 1, Prescale Register High
TIMER2TIM
0x0C10
1
CPU-Timer 2, Counter Register
TIMER2TIMH
0x0C11
1
CPU-Timer 2, Counter Register High
TIMER2PRD
0x0C12
1
CPU-Timer 2, Period Register
TIMER2PRDH
0x0C13
1
CPU-Timer 2, Period Register High
TIMER2TCR
0x0C14
1
CPU-Timer 2, Control Register
Reserved
0x0C15
1
TIMER2TPR
0x0C16
1
CPU-Timer 2, Prescale Register
0x0C17
1
CPU-Timer 2, Prescale Register High
0x0C18 – 0x0C3F
40
TIMER2TPRH
Reserved
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8.2.3 Enhanced PWM Modules
The devices contain up to nine enhanced PWM (ePWM) modules (ePWM1 to ePWM9). Figure 8-4 shows a
block diagram of multiple ePWM modules. Figure 8-5 shows the signal interconnections with the ePWM.
Table 8-3 and Table 8-4 show the complete ePWM register set per module .
EXTSOC1A
POLSEL
0
EXTSOC1A
ePWM1SOCA
ePWM1
ePWM1SOCB
1
EXTSOC1B
POLSEL
ePWM2SOCA
ePWM3
ePWM2SOCB
0
ePWM3SOCA
1
ePWM3SOCB
EXTSOC2A
POLSEL
ePWM4SOCA
ePWM4
0
ePWM4SOCB
ePWM5SOCA
ePWM5
ePWM5SOCB
ePWM6SOCA
ePWM6
1
EXTSOC2B
POLSEL
0
ePWM6SOCB
1
ePWM7SOCA
ePWM7
ePWM7SOCB
ePWM8SOCA
ePWM8
ePWM8SOCB
EXTSOC3A
POLSEL
EXTSOC1B
Pulse Stretcher,
32 HSPCLK Cycles Wide and Then to Chip Pins
ePWM2
ePWM9SOCB
EXTSOC2B
0
EXTSOC3A
ePWM9SOCA
ePWM9
EXTSOC2A
1
EXTSOC3B
POLSEL
0
EXTSOC3B
1
Figure 8-4. Generation of SOC Pulses to the External ADC Module
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Table 8-3. ePWM1–ePWM4 Control and Status Registers
ePWM1
ePWM2
ePWM3
ePWM4
SIZE (x16) /
#SHADOW
TBCTL
0x6800
0x6840
0x6880
0x68C0
1/0
Time Base Control Register
TBSTS
0x6801
0x6841
0x6881
0x68C1
1/0
Time Base Status Register
TBPHSHR
0x6802
0x6842
0x6882
0x68C2
1/0
Time Base Phase HRPWM Register
TBPHS
0x6803
0x6843
0x6883
0x68C3
1/0
Time Base Phase Register
NAME
DESCRIPTION
TBCTR
0x6804
0x6844
0x6884
0x68C4
1/0
Time Base Counter Register
TBPRD
0x6805
0x6845
0x6885
0x68C5
1/1
Time Base Period Register Set
CMPCTL
0x6807
0x6847
0x6887
0x68C7
1/0
Counter Compare Control Register
CMPAHR
0x6808
0x6848
0x6888
0x68C8
1/1
Time Base Compare A HRPWM Register
CMPA
0x6809
0x6849
0x6889
0x68C9
1/1
Counter Compare A Register Set
CMPB
0x680A
0x684A
0x688A
0x68CA
1/1
Counter Compare B Register Set
AQCTLA
0x680B
0x684B
0x688B
0x68CB
1/0
Action Qualifier Control Register For Output A
AQCTLB
0x680C
0x684C
0x688C
0x68CC
1/0
Action Qualifier Control Register For Output B
AQSFRC
0x680D
0x684D
0x688D
0x68CD
1/0
Action Qualifier Software Force Register
AQCSFRC
0x680E
0x684E
0x688E
0x68CE
1/1
Action Qualifier Continuous S/W Force Register Set
DBCTL
0x680F
0x684F
0x688F
0x68CF
1/1
Dead-Band Generator Control Register
DBRED
0x6810
0x6850
0x6890
0x68D0
1/0
Dead-Band Generator Rising Edge Delay Count
Register
DBFED
0x6811
0x6851
0x6891
0x68D1
1/0
Dead-Band Generator Falling Edge Delay Count
Register
TZSEL
0x6812
0x6852
0x6892
0x68D2
1/0
Trip Zone Select Register(1)
TZCTL
0x6814
0x6854
0x6894
0x68D4
1/0
Trip Zone Control Register(1)
TZEINT
0x6815
0x6855
0x6895
0x68D5
1/0
Trip Zone Enable Interrupt Register(1)
TZFLG
0x6816
0x6856
0x6896
0x68D6
1/0
Trip Zone Flag Register
TZCLR
0x6817
0x6857
0x6897
0x68D7
1/0
Trip Zone Clear Register(1)
TZFRC
0x6818
0x6858
0x6898
0x68D8
1/0
Trip Zone Force Register(1)
ETSEL
0x6819
0x6859
0x6899
0x68D9
1/0
Event Trigger Selection Register
ETPS
0x681A
0x685A
0x689A
0x68DA
1/0
Event Trigger Prescale Register
ETFLG
0x681B
0x685B
0x689B
0x68DB
1/0
Event Trigger Flag Register
ETCLR
0x681C
0x685C
0x689C
0x68DC
1/0
Event Trigger Clear Register
ETFRC
0x681D
0x685D
0x689D
0x68DD
1/0
Event Trigger Force Register
PCCTL
0x681E
0x685E
0x689E
0x68DE
1/0
PWM Chopper Control Register
HRCNFG
0x6820
0x6860
0x68A0
0x68E0
1/0
HRPWM Configuration Register(1)
(1)
Registers that are EALLOW protected.
Table 8-4. ePWM5–ePWM9 Control and Status Registers
ePWM5
ePWM6
ePWM7
ePWM8
ePWM9
SIZE
(x16) /
#SHADO
W
TBCTL
0x6900
0x6940
0x6980
0x69C0
0x6600
1/0
Time Base Control Register
TBSTS
0x6901
0x6941
0x6981
0x69C1
0x6601
1/0
Time Base Status Register
TBPHSHR
0x6902
0x6942
0x6982
0x69C2
0x6602
1/0
Time Base Phase HRPWM Register
NAME
DESCRIPTION
TBPHS
0x6903
0x6943
0x6983
0x69C3
0x6603
1/0
Time Base Phase Register
TBCTR
0x6904
0x6944
0x6984
0x69C4
0x6604
1/0
Time Base Counter Register
TBPRD
0x6905
0x6945
0x6985
0x69C5
0x6605
1/1
Time Base Period Register Set
CMPCTL
0x6907
0x6947
0x6987
0x69C7
0x6607
1/0
Counter Compare Control Register
CMPAHR
0x6908
0x6948
0x6988
0x69C8
0x6608
1/1
Time Base Compare A HRPWM Register
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Table 8-4. ePWM5–ePWM9 Control and Status Registers (continued)
NAME
ePWM5
ePWM6
ePWM7
ePWM8
ePWM9
SIZE
(x16) /
#SHADO
W
DESCRIPTION
CMPA
0x6909
0x6949
0x6989
0x69C9
0x6609
1/1
Counter Compare A Register Set
CMPB
0x690A
0x694A
0x698A
0x69CA
0x660A
1/1
Counter Compare B Register Set
AQCTLA
0x690B
0x694B
0x698B
0x69CB
0x660B
1/0
Action Qualifier Control Register For Output A
AQCTLB
0x690C
0x694C
0x698C
0x69CC
0x660C
1/0
Action Qualifier Control Register For Output B
AQSFRC
0x690D
0x694D
0x698D
0x69CD
0x660D
1/0
Action Qualifier Software Force Register
AQCSFRC
0x690E
0x694E
0x698E
0x69CE
0x660E
1/1
Action Qualifier Continuous S/W Force
Register Set
DBCTL
0x690F
0x694F
0x698F
0x69CF
0x660F
1/1
Dead-Band Generator Control Register
DBRED
0x6910
0x6950
0x6990
0x69D0
0x6610
1/0
Dead-Band Generator Rising Edge Delay
Count Register
DBFED
0x6911
0x6951
0x6991
0x69D1
0x6611
1/0
Dead-Band Generator Falling Edge Delay
Count Register
TZSEL
0x6912
0x6952
0x6992
0x69D2
0x6612
1/0
Trip Zone Select Register(1)
TZCTL
0x6914
0x6954
0x6994
0x69D4
0x6614
1/0
Trip Zone Control Register(1)
TZEINT
0x6915
0x6955
0x6995
0x69D5
0x6615
1/0
Trip Zone Enable Interrupt Register(1)
TZFLG
0x6916
0x6956
0x6996
0x69D6
0x6616
1/0
Trip Zone Flag Register
TZCLR
0x6917
0x6957
0x6997
0x69D7
0x6617
1/0
Trip Zone Clear Register(1)
TZFRC
0x6918
0x6958
0x6998
0x69D8
0x6618
1/0
Trip Zone Force Register(1)
ETSEL
0x6919
0x6959
0x6999
0x69D9
0x6619
1/0
Event Trigger Selection Register
ETPS
0x691A
0x695A
0x699A
0x69DA
0x661A
1/0
Event Trigger Prescale Register
ETFLG
0x691B
0x695B
0x699B
0x69DB
0x661B
1/0
Event Trigger Flag Register
ETCLR
0x691C
0x695C
0x699C
0x69DC
0x661C
1/0
Event Trigger Clear Register
ETFRC
0x691D
0x695D
0x699D
0x69DD
0x661D
1/0
Event Trigger Force Register
PCCTL
0x691E
0x695E
0x699E
0x69DE
0x661E
1/0
PWM Chopper Control Register
HRCNFG
0x6920
0x6960
0x69A0
0x69E0
0x6620
1/0
HRPWM Configuration Register(1)
(1)
98
Registers that are EALLOW protected.
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Time−base (TB)
Sync
in/out
select
Mux
CTR=ZERO
CTR=CMPB
Disabled
TBPRD shadow (16)
TBPRD active (16)
CTR=PRD
EPWMxSYNCO
TBCTL[SYNCOSEL]
TBCTL[PHSEN]
EPWMxSYNCI
Counter
up/down
(16 bit)
CTR=ZERO
CTR_Dir
TBCTR
active (16)
TBPHSHR (8)
16
8
TBPHS active (24)
Phase
control
Counter compare (CC)
CTR=CMPA
CMPAHR (8)
16
TBCTL[SWFSYNC]
(software forced sync)
Action
qualifier
(AQ)
CTR = PRD
CTR = ZERO
CTR = CMPA
CTR = CMPB
CTR_Dir
8
Event
trigger
and
interrupt
(ET)
EPWMxINT
EPWMxSOCA
EPWMxSOCB
HRPWM
CMPA active (24)
EPWMxAO
EPWMA
CMPA shadow (24)
CTR=CMPB
Dead
band
(DB)
16
PWM
chopper
(PC)
EPWMxBO
EPWMB
CMPB active (16)
CMPB shadow (16)
Trip
zone
(TZ)
EPWMxTZINT
CTR = ZERO
TZ1 to TZ6
Figure 8-5. ePWM Submodules Showing Critical Internal Signal Interconnections
8.2.4 High-Resolution PWM (HRPWM)
The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• Typically used when effective PWM resolution falls below approximately 9 or 10 bits. This occurs at PWM
frequencies greater than approximately 500 kHz when using a CPU/System clock of 300 MHz or
approximately 375 kHz when using a CPU/system clock of 200 MHz.
• This capability can be used in both duty cycle and phase-shift control methods.
• Finer time granularity control or edge positioning is controlled through extensions to the Compare A and
Phase registers of the ePWM module.
• HRPWM capabilities are offered only on the A signal path of an ePWM module (that is, on the EPWMxA
output). EPWMxB output has conventional PWM capabilities.
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8.2.5 Enhanced CAP Modules
The device contains up to six enhanced capture (eCAP) modules (eCAP1 to eCAP6). Figure 8-6 shows a
functional block diagram of a module.
SYNC
CTRPHS
(Phase Register - 32-bit)
SYNCIn
SYNCOut
TSCTR
(Counter - 32-bit)
APWM Mode
CTR_OVF
OVF
RST
Delta Mode
CTR [0-31]
PRD [0-31]
PWM
Compare
Logic
CMP [0-31]
32
CTR=PRD
CTR [0-31]
CTR=CMP
32
CAP1
(APRD Active)
APRD
Shadow
32
32
32
LD1
Polarity
Select
CMP [0-31]
CAP2
(ACMP Active)
32
LD
MODE SELECT
32
PRD [0-31]
LD
32
CAP3
(APRD Shadow)
LD
32
CAP4
(ACMP Shadow)
LD
Polarity
Select
LD2
Event
Qualifier
ACMP
Shadow
eCAPx
Event
Prescale
LD3
Polarity
Select
LD4
Polarity
Select
4
Capture Events
4
CEVT[1:4]
to PIE
Interrupt
Trigger
and
Flag
Control
CTR_OVF
Continuous/
One-Shot
Capture Control
CTR=PRD
CTR=CMP
Figure 8-6. eCAP Functional Block Diagram
100
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The eCAP modules are clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, ECAP4ENCLK, ECAP5ENCLK,
ECAP6ENCLK) in the PCLKCR1 register are used to turn off the eCAP modules individually (for low power
operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, ECAP4ENCLK, ECAP5ENCLK, and
ECAP6ENCLK are set to low, indicating that the peripheral clock is off.
Table 8-5. eCAP Control and Status Registers
eCAP1
eCAP2
eCAP3
eCAP4
eCAP5
eCAP6
SIZE
(x16)
TSCTR
0x6A00
0x6A20
0x6A40
0x6A60
0x6A80
0x6AA0
2
Timestamp Counter
CTRPHS
0x6A02
0x6A22
0x6A42
0x6A62
0x6A82
0x6AA2
2
Counter Phase Offset Value Register
CAP1
0x6A04
0x6A24
0x6A44
0x6A64
0x6A84
0x6AA4
2
Capture 1 Register
CAP2
0x6A06
0x6A26
0x6A46
0x6A66
0x6A86
0x6AA6
2
Capture 2 Register
NAME
DESCRIPTION
CAP3
0x6A08
0x6A28
0x6A48
0x6A68
0x6A88
0x6AA8
2
Capture 3 Register
CAP4
0x6A0A
0x6A2A
0x6A4A
0x6A6A
0x6A8A
0x6AAA
2
Capture 4 Register
Reserved
0x6A0C0x6A12
0x6A2C-0x6
A32
0x6A4C0x6A52
0x6A6C0x6A72
0x6A8C-0
x6A92
0x6AAC0x6AB2
8
Reserved
ECCTL1
0x6A14
0x6A34
0x6A54
0x6A74
0x6A94
0x6AB4
1
Capture Control Register 1
ECCTL2
0x6A15
0x6A35
0x6A55
0x6A75
0x6A95
0x6AB5
1
Capture Control Register 2
ECEINT
0x6A16
0x6A36
0x6A56
0x6A76
0x6A96
0x6AB6
1
Capture Interrupt Enable Register
ECFLG
0x6A17
0x6A37
0x6A57
0x6A77
0x6A97
0x6AB7
1
Capture Interrupt Flag Register
ECCLR
0x6A18
0x6A38
0x6A58
0x6A78
0x6A98
0x6AB8
1
Capture Interrupt Clear Register
ECFRC
0x6A19
0x6A39
0x6A59
0x6A79
0x6A99
0x6AB9
1
Capture Interrupt Force Register
Reserved
0x6A1A0x6A1F
0x6A3A0x6A3F
0x6A5A0x6A5F
0x6A7A0x6A7F
0x6A9A-0x 0x6ABA6A9F
0x6ABF
6
Reserved
8.2.6 Enhanced QEP Modules
The device contains up to three enhanced quadrature encoder (eQEP) modules with 32-bit resolution (eQEP1,
eQEP2, eQEP3). Figure 8-7 shows the block diagram of the eQEP module.
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System Control
Registers
To CPU
EQEPxENCLK
Data Bus
SYSCLKOUT
QCPRD
QCAPCTL
QCTMR
16
16
16
Quadrature
Capture
Unit
(QCAP)
QCTMRLAT
QCPRDLAT
Registers
Used by
Multiple Units
QUTMR
QWDTMR
QUPRD
QWDPRD
32
16
QEPCTL
QEPSTS
UTIME
QFLG
UTOUT
QWDOG
QDECCTL
16
WDTOUT
PIE
QCLK
EQEPxINT
QDIR
16
QI
Position Counter/
Control Unit
(PCCU)
QPOSLAT
QS Quadrature
Decoder
PHE
(QDU)
PCSOUT
QPOSSLAT
QPOSILAT
EQEPxAIN
EQEPxA/XCLK
EQEPxBIN
EQEPxIIN
EQEPxB/XDIR
EQEPxIOUT
EQEPxIOE
GPIO
MUX
EQEPxSIN
EQEPxSOUT
EQEPxSOE
32
32
QPOSCNT
QPOSCMP
EQEPxI
EQEPxS
16
QEINT
QPOSINIT
QFRC
QPOSMAX
QCLR
QPOSCTL
Enhanced QEP (eQEP) Peripheral
Figure 8-7. eQEP Functional Block Diagram
102
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Table 8-6 provides a summary of the eQEP registers.
Table 8-6. eQEP Control and Status Registers
eQEP1
ADDRESS
eQEP2
ADDRESS
eQEP3
ADDRESS
eQEPx
SIZE(x16)/
#SHADOW
QPOSCNT
0x6B00
0x6B40
0x6B80
2/0
eQEP Position Counter
QPOSINIT
0x6B02
0x6B42
0x6B82
2/0
eQEP Initialization Position Count
QPOSMAX
0x6B04
0x6B44
0x6B84
2/0
eQEP Maximum Position Count
QPOSCMP
0x6B06
0x6B46
0x6B86
2/1
eQEP Position-compare
NAME
REGISTER DESCRIPTION
QPOSILAT
0x6B08
0x6B48
0x6B88
2/0
eQEP Index Position Latch
QPOSSLAT
0x6B0A
0x6B4A
0x6B8A
2/0
eQEP Strobe Position Latch
QPOSLAT
0x6B0C
0x6B4C
0x6B8C
2/0
eQEP Position Latch
QUTMR
0x6B0E
0x6B4E
0x6B8E
2/0
eQEP Unit Timer
QUPRD
0x6B10
0x6B50
0x6B90
2/0
eQEP Unit Period Register
QWDTMR
0x6B12
0x6B52
0x6B92
1/0
eQEP Watchdog Timer
QWDPRD
0x6B13
0x6B53
0x6B93
1/0
eQEP Watchdog Period Register
QDECCTL
0x6B14
0x6B54
0x6B94
1/0
eQEP Decoder Control Register
QEPCTL
0x6B15
0x6B55
0x6B95
1/0
eQEP Control Register
QCAPCTL
0x6B16
0x6B56
0x6B96
1/0
eQEP Capture Control Register
QPOSCTL
0x6B17
0x6B57
0x6B97
1/0
eQEP Position-compare Control Register
QEINT
0x6B18
0x6B58
0x6B98
1/0
eQEP Interrupt Enable Register
QFLG
0x6B19
0x6B59
0x6B99
1/0
eQEP Interrupt Flag Register
QCLR
0x6B1A
0x6B5A
0x6B9A
1/0
eQEP Interrupt Clear Register
QFRC
0x6B1B
0x6B5B
0x6B9B
1/0
eQEP Interrupt Force Register
QEPSTS
0x6B1C
0x6B5C
0x6B9C
1/0
eQEP Status Register
QCTMR
0x6B1D
0x6B5D
0x6B9D
1/0
eQEP Capture Timer
QCPRD
0x6B1E
0x6B5E
0x6B9E
1/0
eQEP Capture Period Register
QCTMRLAT
0x6B1F
0x6B5F
0x6B9F
1/0
eQEP Capture Timer Latch
QCPRDLAT
0x6B20
0x6B60
0x6BA0
1/0
eQEP Capture Period Latch
0x6B61 - 0x6B7F
0x6BBA1 0x6BBF
31/0
Reserved
0x6B21 - 0x6B3F
8.2.7 External ADC Interface
The external ADC interface operation is configured, controlled, and monitored by the External SoC Configuration
Register (EXTSOCCFG) at address 0x702E. Figure 8-8 shows how the Start-of-Conversion signals for external
ADCs are generated by the on-chip PWM modules.
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EXTSOC1A
POLSEL
0
EXTSOC1A
1
ePWM1SOCA
ePWM1
EXTSOC1B
POLSEL
ePWM1SOCB
ePWM2SOCA
ePWM3
ePWM2SOCB
0
ePWM3SOCA
1
EXTSOC2A
POLSEL
ePWM3SOCB
ePWM4SOCA
ePWM4
0
ePWM4SOCB
1
ePWM5SOCA
ePWM5
ePWM5SOCB
EXTSOC2B
POLSEL
0
ePWM6SOCA
ePWM6
ePWM6SOCB
1
ePWM7SOCA
ePWM7
ePWM7SOCB
EXTSOC3A
POLSEL
ePWM8SOCA
ePWM8
ePWM8SOCB
EXTSOC2A
EXTSOC2B
0
EXTSOC3A
ePWM9SOCA
ePWM9
EXTSOC1B
Pulse Stretcher,
32 HSPCLK Cycles Wide and Then to Chip Pins
ePWM2
1
ePWM9SOCB
EXTSOC3B
POLSEL
0
EXTSOC3B
1
Figure 8-8. External ADC Interface
Table 8-7. External ADC Interface Registers
NAME
EXTSOCCFG
DESCRIPTION
External SoC Configuration Register
ADDRESS
0x00 702E
8.2.8 Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
• Compatible to McBSP in TMS320C54x/TMS320C55x DSP devices
• Full-duplex communication
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Double-buffered data registers that allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits
8-bit data transfers with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
Highly programmable internal clock and frame generation
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected
A/D and D/A devices
Works with SPI-compatible devices
The following application interfaces can be supported on the McBSP:
– T1/E1 framers
– IOM-2 compliant devices
– AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
– IIS-compliant devices
– SPI
McBSP clock rate,
CLKG =
CLKSRG
(1 + CLKGDV )
where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O buffer
switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O
buffer speed limit.
Note
See Section 7 for maximum I/O pin toggling speed.
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Figure 8-9 shows the block diagram of the McBSP module.
TX
Interrupt
MXINT
To CPU
Peripheral Write Bus
CPU
TX Interrupt Logic
16
McBSP Transmit
Interrupt Select Logic
16
DXR2 Transmit Buffer
LSPCLK
DXR1 Transmit Buffer
MFSXx
16
16
MCLKXx
DMA Bus
Peripheral Bus
CPU
Bridge
Compand Logic
XSR2
XSR1
MDXx
RSR2
RSR1
MDRx
16
MCLKRx
16
Expand Logic
MFSRx
RBR2 Register
McBSP Receive
Interrupt Select Logic
MRINT
RX Interrupt Logic
16
16
DRR2 Receive Buffer
DRR1 Receive Buffer
16
RX
Interrupt
RBR1 Register
16
Peripheral Read Bus
CPU
To CPU
Figure 8-9. McBSP Module
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Table 8-8 provides a summary of the McBSP registers.
Table 8-8. McBSP Register Summary
NAME
McBSP-A
ADDRESS
McBSP-B
ADDRESS
TYPE
RESET VALUE
DESCRIPTION
Data Registers, Receive, Transmit
DRR2
0x5000
0x5040
R
0x0000
McBSP Data Receive Register 2
DRR1
0x5001
0x5041
R
0x0000
McBSP Data Receive Register 1
DXR2
0x5002
0x5042
W
0x0000
McBSP Data Transmit Register 2
DXR1
0x5003
0x5043
W
0x0000
McBSP Data Transmit Register 1
SPCR2
0x5004
0x5044
R/W
0x0000
McBSP Serial Port Control Register 2
SPCR1
0x5005
0x5045
R/W
0x0000
McBSP Serial Port Control Register 1
RCR2
0x5006
0x5046
R/W
0x0000
McBSP Receive Control Register 2
RCR1
0x5007
0x5047
R/W
0x0000
McBSP Receive Control Register 1
XCR2
0x5008
0x5048
R/W
0x0000
McBSP Transmit Control Register 2
McBSP Control Registers
XCR1
0x5009
0x5049
R/W
0x0000
McBSP Transmit Control Register 1
SRGR2
0x500A
0x504A
R/W
0x0000
McBSP Sample Rate Generator Register 2
SRGR1
0x500B
0x504B
R/W
0x0000
McBSP Sample Rate Generator Register 1
Multichannel Control Registers
MCR2
0x500C
0x504C
R/W
0x0000
McBSP Multichannel Register 2
MCR1
0x500D
0x504D
R/W
0x0000
McBSP Multichannel Register 1
RCERA
0x500E
0x504E
R/W
0x0000
McBSP Receive Channel Enable Register Partition A
RCERB
0x500F
0x504F
R/W
0x0000
McBSP Receive Channel Enable Register Partition B
XCERA
0x5010
0x5050
R/W
0x0000
McBSP Transmit Channel Enable Register Partition A
XCERB
0x5011
0x5051
R/W
0x0000
McBSP Transmit Channel Enable Register Partition B
PCR
0x5012
0x5052
R/W
0x0000
McBSP Pin Control Register
RCERC
0x5013
0x5053
R/W
0x0000
McBSP Receive Channel Enable Register Partition C
RCERD
0x5014
0x5054
R/W
0x0000
McBSP Receive Channel Enable Register Partition D
XCERC
0x5015
0x5055
R/W
0x0000
McBSP Transmit Channel Enable Register Partition C
XCERD
0x5016
0x5056
R/W
0x0000
McBSP Transmit Channel Enable Register Partition D
RCERE
0x5017
0x5057
R/W
0x0000
McBSP Receive Channel Enable Register Partition E
RCERF
0x5018
0x5058
R/W
0x0000
McBSP Receive Channel Enable Register Partition F
XCERE
0x5019
0x5059
R/W
0x0000
McBSP Transmit Channel Enable Register Partition E
XCERF
0x501A
0x505A
R/W
0x0000
McBSP Transmit Channel Enable Register Partition F
RCERG
0x501B
0x505B
R/W
0x0000
McBSP Receive Channel Enable Register Partition G
RCERH
0x501C
0x505C
R/W
0x0000
McBSP Receive Channel Enable Register Partition H
XCERG
0x501D
0x505D
R/W
0x0000
McBSP Transmit Channel Enable Register Partition G
XCERH
0x501E
0x505E
R/W
0x0000
McBSP Transmit Channel Enable Register Partition H
MFFINT
0x5023
0x5063
R/W
0x0000
McBSP Interrupt Enable Register
MFFST
0x5024
0x5064
R/W
0x0000
McBSP Pin Status Register
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
8.2.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
The CAN module has the following features:
• Fully compliant with ISO 11898-1 (CAN 2.0B)
• Supports data rates up to 1 Mbps
• Thirty-two mailboxes, each with the following properties:
– Configurable as receive or transmit
– Configurable with standard or extended identifier
– Has a programmable receive mask
– Supports data and remote frame
– Composed of 0 to 8 bytes of data
– Uses a 32-bit timestamp on receive and transmit message
– Protects against reception of new message
– Holds the dynamically programmable priority of transmit message
– Employs a programmable interrupt scheme with two interrupt levels
– Employs a programmable alarm on transmission or reception time-out
• Low-power mode
• Programmable wake-up on bus activity
• Automatic reply to a remote request message
• Automatic retransmission of a frame in case of loss of arbitration or error
• 32-bit local network time counter synchronized by a specific message (communication in conjunction with
mailbox 16)
• Self-test mode
– Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided, thereby
eliminating the need for another node to provide the acknowledge bit.
Note
For a SYSCLKOUT of 300 MHz, the smallest bit rate possible is 11.719 kbps.
For a SYSCLKOUT of 200 MHz, the smallest bit rate possible is 7.8125 kbps.
The CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and exceptions.
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eCAN0INT
eCAN1INT
Controls Address
Data
Enhanced CAN Controller
32
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
32-Message Mailbox
of 4 x 32-Bit Words
32
CPU Interface,
Receive Control Unit,
Timer Management Unit
eCAN Memory
(512 Bytes)
Registers and
Message Objects Control
32
32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 8-10. eCAN Block Diagram and Interface Circuit
Table 8-9. 3.3-V eCAN Transceivers
PART NUMBER
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
VREF
OTHER
TA
SN65HVD230Q
3.3 V
Standby
Adjustable
Yes
–
–40°C to 125°C
SN65HVD231Q
3.3 V
Sleep
Adjustable
Yes
–
–40°C to 125°C
SN65HVD232Q
3.3 V
None
None
None
–
–40°C to 125°C
SN65HVD233
3.3 V
Standby
Adjustable
None
Diagnostic Loopback
–40°C to 125°C
SN65HVD234
3.3 V
Standby and Sleep
Adjustable
None
–
–40°C to 125°C
SN65HVD235
3.3 V
Standby
Adjustable
None
Autobaud Loopback
–40°C to 125°C
ISO1050
3–5.5 V
None
None
None
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Built-in isolation
Low-prop delay
Thermal shutdown
Fail-safe operation
Dominant time-out
–55°C to 105°C
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eCAN-A Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
Abort Acknowledge - CANAA
eCAN-A Memory (512 Bytes)
6000h
Received Message Pending - CANRMP
Control and Status Registers
603Fh
6040h
607Fh
6080h
60BFh
60C0h
60FFh
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Local Acceptance Masks (LAM)
(32 x 32-Bit RAM)
Global Acceptance Mask - CANGAM
Message Object Timestamps (MOTS)
(32 x 32-Bit RAM)
Bit-Timing Configuration - CANBTC
Master Control - CANMC
Error and Status - CANES
Message Object Time-Out (MOTO)
(32 x 32-Bit RAM)
Transmit Error Counter - CANTEC
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
eCAN-A Memory RAM (512 Bytes)
6100h-6107h
Mailbox 0
6108h-610Fh
Mailbox 1
6110h-6117h
Mailbox 2
6118h-611Fh
Mailbox 3
6120h-6127h
Mailbox 4
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Timestamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
61E0h-61E7h
Mailbox 28
61E8h-61EFh
Mailbox 29
61F0h-61F7h
Mailbox 30
61F8h-61FFh
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
61E8h-61E9h
Message Identifier - MSGID
61EAh-61EBh
Message Control - MSGCTRL
61ECh-61EDh
Message Data Low - MDL
61EEh-61EFh
Message Data High - MDH
Figure 8-11. eCAN-A Memory Map
Note
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and
mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for
this.
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eCAN-B Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
Abort Acknowledge - CANAA
eCAN-B Memory (512 Bytes)
6200h
Received Message Pending - CANRMP
Control and Status Registers
623Fh
6240h
627Fh
6280h
62BFh
62C0h
62FFh
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Local Acceptance Masks (LAM)
(32 x 32-Bit RAM)
Global Acceptance Mask - CANGAM
Message Object Timestamps (MOTS)
(32 x 32-Bit RAM)
Bit-Timing Configuration - CANBTC
Master Control - CANMC
Error and Status - CANES
Message Object Time-Out (MOTO)
(32 x 32-Bit RAM)
Transmit Error Counter - CANTEC
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
eCAN-B Memory RAM (512 Bytes)
6300h-6307h
Mailbox 0
6308h-630Fh
Mailbox 1
6310h-6317h
Mailbox 2
6318h-631Fh
Mailbox 3
6320h-6327h
Mailbox 4
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Timestamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
63E0h-63E7h
Mailbox 28
63E8h-63EFh
Mailbox 29
63F0h-63F7h
Mailbox 30
63F8h-63FFh
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
63E8h-63E9h
Message Identifier - MSGID
63EAh-63EBh
Message Control - MSGCTRL
63ECh-63EDh
Message Data Low - MDL
63EEh-63EFh
Message Data High - MDH
Figure 8-12. eCAN-B Memory Map
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The CAN registers listed in Table 8-10 are used by the CPU to configure and control the CAN controller and the
message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be
accessed as 16 bits or 32 bits. Thirty-two-bit accesses are aligned to an even boundary.
Table 8-10. CAN Register Map (1)
eCAN-A
ADDRESS
eCAN-B
ADDRESS
SIZE
(x32)
CANME
0x6000
0x6200
1
Mailbox enable
CANMD
0x6002
0x6202
1
Mailbox direction
CANTRS
0x6004
0x6204
1
Transmit request set
CANTRR
0x6006
0x6206
1
Transmit request reset
CANTA
0x6008
0x6208
1
Transmission acknowledge
REGISTER NAME
DESCRIPTION
CANAA
0x600A
0x620A
1
Abort acknowledge
CANRMP
0x600C
0x620C
1
Receive message pending
CANRML
0x600E
0x620E
1
Receive message lost
CANRFP
0x6010
0x6210
1
Remote frame pending
CANGAM
0x6012
0x6212
1
Global acceptance mask
CANMC
0x6014
0x6214
1
Master control
CANBTC
0x6016
0x6216
1
Bit-timing configuration
CANES
0x6018
0x6218
1
Error and status
CANTEC
0x601A
0x621A
1
Transmit error counter
CANREC
0x601C
0x621C
1
Receive error counter
CANGIF0
0x601E
0x621E
1
Global interrupt flag 0
CANGIM
0x6020
0x6220
1
Global interrupt mask
CANGIF1
0x6022
0x6222
1
Global interrupt flag 1
CANMIM
0x6024
0x6224
1
Mailbox interrupt mask
CANMIL
0x6026
0x6226
1
Mailbox interrupt level
CANOPC
0x6028
0x6228
1
Overwrite protection control
CANTIOC
0x602A
0x622A
1
TX I/O control
CANRIOC
0x602C
0x622C
1
RX I/O control
CANTSC
0x602E
0x622E
1
Timestamp counter (Reserved in SCC mode)
CANTOC
0x6030
0x6230
1
Time-out control (Reserved in SCC mode)
CANTOS
0x6032
0x6232
1
Time-out status (Reserved in SCC mode)
(1)
112
These registers are mapped to Peripheral Frame 1.
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8.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
The devices include three serial communications interface (SCI) modules. The SCI modules support digital
communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero
(NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and
interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data
integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is
programmable to more than 65000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
Note
Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:
Baud rate =
LSPCLK
(BRR + 1) * 8
when BRR ¹ 0
Baud rate =
LSPCLK
16
when BRR = 0
Note
See Section 7 for maximum I/O pin toggling speed.
•
•
•
•
•
•
•
•
Data-word format
– One start bit
– Data-word length programmable from one to eight bits
– Optional even/odd/no parity bit
– One or two stop bits
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ (nonreturn-to-zero) format
Note
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7-0), and the upper byte (15-8) is read as
zeros. Writing to the upper byte has no effect.
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Enhanced features:
• Auto baud-detect hardware logic
• 16-level transmit/receive FIFO
The SCI port operation is configured and controlled by the registers listed in Table 8-11, Table 8-12, and Table
8-13.
Table 8-11. SCI-A Registers (1)
ADDRESS
SIZE (x16)
SCICCRA
NAME
0x7050
1
SCI-A Communications Control Register
DESCRIPTION
SCICTL1A
0x7051
1
SCI-A Control Register 1
SCIHBAUDA
0x7052
1
SCI-A Baud Register, High Bits
SCILBAUDA
0x7053
1
SCI-A Baud Register, Low Bits
SCICTL2A
0x7054
1
SCI-A Control Register 2
SCIRXSTA
0x7055
1
SCI-A Receive Status Register
SCIRXEMUA
0x7056
1
SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA
0x7057
1
SCI-A Receive Data Buffer Register
SCITXBUFA
0x7059
1
SCI-A Transmit Data Buffer Register
SCIFFTXA(2)
0x705A
1
SCI-A FIFO Transmit Register
SCIFFRXA(2)
0x705B
1
SCI-A FIFO Receive Register
SCIFFCTA(2)
0x705C
1
SCI-A FIFO Control Register
SCIPRIA
0x705F
1
SCI-A Priority Control Register
(1)
(2)
Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
These registers are new registers for the FIFO mode.
Table 8-12. SCI-B Registers (1) (2)
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
SCICCRB
0x7750
1
SCI-B Communications Control Register
SCICTL1B
0x7751
1
SCI-B Control Register 1
SCIHBAUDB
0x7752
1
SCI-B Baud Register, High Bits
SCILBAUDB
0x7753
1
SCI-B Baud Register, Low Bits
SCICTL2B
0x7754
1
SCI-B Control Register 2
SCIRXSTB
0x7755
1
SCI-B Receive Status Register
SCIRXEMUB
0x7756
1
SCI-B Receive Emulation Data Buffer Register
SCIRXBUFB
0x7757
1
SCI-B Receive Data Buffer Register
SCITXBUFB
0x7759
1
SCI-B Transmit Data Buffer Register
SCIFFTXB(2)
0x775A
1
SCI-B FIFO Transmit Register
SCIFFRXB(2)
0x775B
1
SCI-B FIFO Receive Register
SCIFFCTB(2)
0x775C
1
SCI-B FIFO Control Register
SCIPRIB
0x775F
1
SCI-B Priority Control Register
(1)
(2)
114
Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
These registers are new registers for the FIFO mode.
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Table 8-13. SCI-C Registers (1) (2)
NAME
ADDRESS
SIZE (x16)
0x7770
1
SCI-C Communications Control Register
SCICTL1C
0x7771
1
SCI-C Control Register 1
SCIHBAUDC
0x7772
1
SCI-C Baud Register, High Bits
SCILBAUDC
0x7773
1
SCI-C Baud Register, Low Bits
SCICTL2C
0x7774
1
SCI-C Control Register 2
SCIRXSTC
0x7775
1
SCI-C Receive Status Register
SCIRXEMUC
0x7776
1
SCI-C Receive Emulation Data Buffer Register
SCIRXBUFC
0x7777
1
SCI-C Receive Data Buffer Register
SCITXBUFC
0x7779
1
SCI-C Transmit Data Buffer Register
SCIFFTXC(2)
0x777A
1
SCI-C FIFO Transmit Register
SCIFFRXC(2)
0x777B
1
SCI-C FIFO Receive Register
SCIFFCTC(2)
0x777C
1
SCI-C FIFO Control Register
SCIPRC
0x777F
1
SCI-C Priority Control Register
SCICCRC
DESCRIPTION
Figure 8-13 shows the SCI module block diagram.
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SCICTL1.1
Frame Format and Mode
SCITXD
TXSHF
Register
Parity
Even/Odd
Enable
TX EMPTY
SCICTL2.6
8
SCICCR.6 SCICCR.5
TXRDY
SCICTL2.7
Transmitter-Data
Buffer Register
TXWAKE
SCICTL1.3
WUT
SCICTL2.0
TXINT
TX FIFO _0
TX Interrupt Logic
-----
TX FIFO _15
TX
FIFO
Interrupts
SCITXBUF.7-0
TX FIFO Registers
SCIFFENA
SCIHBAUD. 15 - 8
Baud Rate
MSbyte
Register
LSPCLK
TX INT ENA
8
TX FIFO _1
1
SCITXD
TXENA
To CPU
SCI TX Interrupt Select Logic
AutoBaud Detect Logic
SCIFFTX.14
SCIRXD
SCIRXD
RXSHF Register
RXWAKE
SCIRXST.1
SCILBAUD. 7 - 0
Baud Rate
LSbyte
Register
RXENA
8
SCICTL1.0
SCICTL2.1
RXRDY
Receive-Data
Buffer Register
SCIRXBUF.7-0
RX/BK INT ENA
SCIRXST.6
BRKDT
8
SCIRXST.5
RX FIFO _15
-----
RX FIFO _1
RX FIFO _0
RX
FIFO
Interrupts
RX Interrupt Logic
To CPU
SCIRXBUF.7-0
RX FIFO Registers
RXFFOVF
SCIRXST.7
SCIRXST.4 - 2
RX Error
FE OE PE
RXINT
SCIFFRX.15
RX Error
RX ERR INT ENA
SCI RX Interrupt Select Logic
SCICTL1.6
Figure 8-13. Serial Communications Interface (SCI) Module Block Diagram
116
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8.2.11 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D)
The device includes the four-pin serial peripheral interface (SPI) module. Two SPI modules (SPI-A and SPI-D)
are available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed
length (1 to 16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI
is used for communications between the MCU controller and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as shift registers, display drivers,
and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.
The SPI module features include:
• Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin
Note
All four pins can be used as GPIO if the SPI module is not used.
•
Two operational modes: master and slave
Baud rate: 125 different programmable rates.
Baud rate =
LSPCLK
(SPIBRR + 1)
when SPIBRR = 3 to 127
Baud rate =
LSPCLK
4
when SPIBRR = 0, 1, 2
Note
See Section 7 for maximum I/O pin toggling speed.
•
•
•
•
•
Data word length: 1 to 16 data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
Note
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read
as zeros. Writing to the upper byte has no effect.
Enhanced features:
• 16-level transmit/receive FIFO
• Delayed transmit control
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The SPI port operation is configured and controlled by the registers listed in Table 8-14 and Table 8-15 .
Table 8-14. SPI-A Registers
NAME
DESCRIPTION(1)
ADDRESS
SIZE (x16)
SPICCR
0x7040
1
SPI-A Configuration Control Register
SPICTL
0x7041
1
SPI-A Operation Control Register
SPISTS
0x7042
1
SPI-A Status Register
SPIBRR
0x7044
1
SPI-A Baud Rate Register
SPIRXEMU
0x7046
1
SPI-A Receive Emulation Buffer Register
SPIRXBUF
0x7047
1
SPI-A Serial Input Buffer Register
SPITXBUF
0x7048
1
SPI-A Serial Output Buffer Register
SPIDAT
0x7049
1
SPI-A Serial Data Register
SPIFFTX
0x704A
1
SPI-A FIFO Transmit Register
SPIFFRX
0x704B
1
SPI-A FIFO Receive Register
SPIFFCT
0x704C
1
SPI-A FIFO Control Register
SPIPRI
0x704F
1
SPI-A Priority Control Register
(1)
Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Table 8-15. SPI-D Registers
NAME
DESCRIPTION(1)
ADDRESS
SIZE (x16)
SPICCR
0x7780
1
SPI-D Configuration Control Register
SPICTL
0x7781
1
SPI-D Operation Control Register
SPISTS
0x7782
1
SPI-D Status Register
SPIBRR
0x7784
1
SPI-D Baud Rate Register
SPIRXEMU
0x7786
1
SPI-D Receive Emulation Buffer Register
SPIRXBUF
0x7787
1
SPI-D Serial Input Buffer Register
SPITXBUF
0x7788
1
SPI-D Serial Output Buffer Register
SPIDAT
0x7789
1
SPI-D Serial Data Register
SPIFFTX
0x778A
1
SPI-D FIFO Transmit Register
SPIFFRX
0x778B
1
SPI-D FIFO Receive Register
SPIFFCT
0x778C
1
SPI-D FIFO Control Register
SPIPRI
0x778F
1
SPI-D Priority Control Register
(1)
Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Figure 8-14 is a block diagram of the SPI in slave mode.
118
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SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO registers
SPISTS.7
SPICTL.4
SPIRXBUF
RX FIFO _0
RX FIFO _1
SPIINT/SPIRXINT
RX FIFO Interrupt
−−−−−
RX Interrupt
Logic
RX FIFO _15
16
SPIRXBUF
Buffer Register
SPIFFOVF FLAG
SPIFFRX.15
To CPU
TX FIFO registers
SPITXBUF
TX FIFO _15
TX Interrupt
Logic
TX FIFO Interrupt
−−−−−
TX FIFO _1
TX FIFO _0
SPITXINT
16
SPI INT FLAG
SPITXBUF
Buffer Register
16
SPI INT
ENA
SPISTS.6
SPICTL.0
16
M
M
SPIDAT
Data Register
S
SPIDAT.15 − 0
M
S
SW1
SPISIMO
M
S
S
SW2
SPISOMI
Talk
SPICTL.1
(A)
SPISTE
State Control
Master/Slave
SPI Char
SPICCR.3 − 0
3
2
1
SW3
M
SPI Bit Rate
LSPCLK
SPIBRR.6 − 0
6
5
4
3
SPICTL.2
S
0
2
1
0
S
Clock
Polarity
Clock
Phase
SPICCR.6
SPICTL.3
SPICLK
M
A. SPISTE is driven low by the master for a slave device.
Figure 8-14. SPI Module Block Diagram (Slave Mode)
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8.2.12 Inter-Integrated Circuit (I2C)
The device contains one I2C Serial Port. Figure 8-15 shows how the I2C peripheral module interfaces within the
device.
System Control Block
C28x CPU
I2CAENCLK
SYSRS
Control
Data[16]
SDAA
GPIO
MUX
Peripheral Bus
SYSCLKOUT
Data[16]
I2C-A
Addr[16]
SCLA
I2CINT1A
I2CINT2A
PIE
Block
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the
SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCR0 register turns off the clock to the I2C port for low power operation. Upon reset,
I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 8-15. I2C Peripheral Module Interfaces
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The I2C module has the following features:
• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate from 10 kbps up to 400 kbps (I2C Fast-mode rate)
• One 16-word receive FIFO and one 16-word transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following
conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module-enable and module-disable capability
• Free data format mode
The registers in Table 8-16 configure and control the I2C port operation.
Table 8-16. I2C-A Registers
NAME
ADDRESS
DESCRIPTION
I2COAR
0x7900
I2C own address register
I2CIER
0x7901
I2C interrupt enable register
I2CSTR
0x7902
I2C status register
I2CCLKL
0x7903
I2C clock low-time divider register
I2CCLKH
0x7904
I2C clock high-time divider register
I2CCNT
0x7905
I2C data count register
I2CDRR
0x7906
I2C data receive register
I2CSAR
0x7907
I2C slave address register
I2CDXR
0x7908
I2C data transmit register
I2CMDR
0x7909
I2C mode register
I2CISRC
0x790A
I2C interrupt source register
I2CPSC
0x790C
I2C prescaler register
I2CFFTX
0x7920
I2C FIFO transmit register
I2CFFRX
0x7921
I2CRSR
–
I2C receive shift register (not accessible to the CPU)
I2CXSR
–
I2C transmit shift register (not accessible to the CPU)
I2C FIFO receive register
8.2.13 GPIO MUX
On the 2834x devices, the GPIO MUX can multiplex up to three independent peripheral signals on a single
GPIO pin in addition to providing individual pin bit-banging I/O capability. The GPIO MUX block diagram per pin
is shown in Figure 8-16. Because of the open-drain capabilities of the I2C pins, the GPIO MUX block diagram for
these pins differ. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide for details.
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Note
There is a 2-SYSCLKOUT cycle delay from when the write to the GPxMUXn and GPxQSELn registers
occurs to when the action is valid.
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
GPIOLMPSEL
GPIOXINT7SEL
LPMCR0
GPIOXNMISEL
Low-Power
Modes Block
External Interrupt
MUX
PIE
GPxDAT (read)
Asynchronous
path
GPxQSEL1/2
GPxCTRL
GPxPUD
Input
Qualification
Internal
Pullup
00
N/C
01
Peripheral 1 Input
10
Peripheral 2 Input
11
Peripheral 3 Input
Asynchronous path
GPxTOGGLE
GPxCLEAR
GPxSET
GPIOx pin
00
GPxDAT (latch)
01
Peripheral 1 Output
10
Peripheral 2 Output
11
Peripheral 3 Output
High-Impedance
Output Control
00
0 = Input, 1 = Output
XRS
= Default at Reset
GPxDIR (latch)
01
Peripheral 1 Output Enable
10
Peripheral 2 Output Enable
11
Peripheral 3 Output Enable
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular
GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the TMS320x2834x Delfino System
Control and Interrupts Reference Guide for pin-specific variations.
Figure 8-16. GPIO MUX Block Diagram
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The device supports 88 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to
enable 32-bit operations on the registers (along with 16-bit operations). Table 8-17 shows the GPIO register
mapping.
Table 8-17. GPIO Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL
0x6F80
2
GPIO A Control Register (GPIO0 to 31)
GPAQSEL1
0x6F82
2
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL2
0x6F84
2
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX1
0x6F86
2
GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX2
0x6F88
2
GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR
0x6F8A
2
GPIO A Direction Register (GPIO0 to 31)
GPAPUD
0x6F8C
2
GPIO A Pullup Disable Register (GPIO0 to 31)
Reserved
0x6F8E – 0x6F8F
2
GPBCTRL
0x6F90
2
GPIO B Control Register (GPIO32 to 63)
GPBQSEL1
0x6F92
2
GPIO B Qualifier Select 1 Register (GPIO32 to 47)
GPBQSEL2
0x6F94
2
GPIOB Qualifier Select 2 Register (GPIO48 to 63)
GPBMUX1
0x6F96
2
GPIO B MUX 1 Register (GPIO32 to 47)
GPBMUX2
0x6F98
2
GPIO B MUX 2 Register (GPIO48 to 63)
GPBDIR
0x6F9A
2
GPIO B Direction Register (GPIO32 to 63)
GPBPUD
0x6F9C
2
GPIO B Pullup Disable Register (GPIO32 to 63)
Reserved
0x6F9E – 0x6FA5
8
0x6FA6
2
GPCMUX1
GPIO C MUX1 Register (GPIO64 to 79)
GPCMUX2
0x6FA8
2
GPIO C MUX2 Register (GPIO80 to 87)
GPCDIR
0x6FAA
2
GPIO C Direction Register (GPIO64 to 87)
GPIO C Pullup Disable Register (GPIO64 to 87)
GPCPUD
0x6FAC
2
Reserved
0x6FAE – 0x6FBF
18
GPADAT
0x6FC0
2
GPIO A Data Register (GPIO0 to 31)
GPASET
0x6FC2
2
GPIO A Data Set Register (GPIO0 to 31)
GPACLEAR
0x6FC4
2
GPIO A Data Clear Register (GPIO0 to 31)
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPATOGGLE
0x6FC6
2
GPIO A Data Toggle Register (GPIO0 to 31)
GPBDAT
0x6FC8
2
GPIO B Data Register (GPIO32 to 63)
GPBSET
0x6FCA
2
GPIO B Data Set Register (GPIO32 to 63)
GPBCLEAR
0x6FCC
2
GPIO B Data Clear Register (GPIO32 to 63)
GPBTOGGLE
0x6FCE
2
GPIOB Data Toggle Register (GPIO32 to 63)
GPCDAT
0x6FD0
2
GPIO C Data Register (GPIO64 to 87)
GPCSET
0x6FD2
2
GPIO C Data Set Register (GPIO64 to 87)
GPCCLEAR
0x6FD4
2
GPIO C Data Clear Register (GPIO64 to 87)
GPCTOGGLE
0x6FD6
2
GPIO C Data Toggle Register (GPIO64 to 87)
0x6FD8 – 0x6FDF
8
Reserved
GPIO INTERRUPT AND LOW-POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
0x6FE0
1
XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL
0x6FE1
1
XINT2 GPIO Input Select Register (GPIO0 to 31)
GPIOXNMISEL
0x6FE2
1
XNMI GPIO Input Select Register (GPIO0 to 31)
GPIOXINT3SEL
0x6FE3
1
XINT3 GPIO Input Select Register (GPIO32 to 63)
GPIOXINT4SEL
0x6FE4
1
XINT4 GPIO Input Select Register (GPIO32 to 63)
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Table 8-17. GPIO Registers (continued)
NAME
ADDRESS
SIZE (x16)
GPIOXINT5SEL
0x6FE5
1
XINT5 GPIO Input Select Register (GPIO32 to 63)
GPIOXINT6SEL
0x6FE6
1
XINT6 GPIO Input Select Register (GPIO32 to 63)
GPIOINT7SEL
0x6FE7
1
XINT7 GPIO Input Select Register (GPIO32 to 63)
0x6FE8
2
LPM GPIO Select Register (GPIO0 to 31)
0x6FEA – 0x6FFF
22
GPIOLPMSEL
Reserved
DESCRIPTION
Table 8-18. GPIO-A Mux Peripheral Selection Matrix
REGISTER BITS
GPADIR
GPADAT
GPASET
GPACLR
GPATOGGLE
QUALPRD0
QUALPRD1
QUALPRD2
QUALPRD3
124
PERIPHERAL SELECTION
GPAMUX1
GPAQSEL1
GPIOx
GPAMUX1 = 0,0
PER1
GPAMUX1 = 0, 1
PER2
GPAMUX1 = 1, 0
PER3
GPAMUX1 = 1, 1
0
1, 0
GPIO0 (I/O)
EPWM1A (O)
Reserved
Reserved
1
3, 2
GPIO1 (I/O)
EPWM1B (O)
ECAP6 (I/O)
MFSRB (I/O)
2
5, 4
GPIO2 (I/O)
EPWM2A (O)
Reserved
Reserved
3
7, 6
GPIO3 (I/O)
EPWM2B (O)
ECAP5 (I/O)
MCLKRB (I/O)
4
9, 8
GPIO4 (I/O)
EPWM3A (O)
Reserved
Reserved
5
11, 10
GPIO5 (I/O)
EPWM3B (O)
MFSRA (I/O)
ECAP1 (I/O)
6
13, 12
GPIO6 (I/O)
EPWM4A (O)
EPWMSYNCI (I)
EPWMSYNCO (O)
7
15, 14
GPIO7 (I/O)
EPWM4B (O)
MCLKRA (I/O)
ECAP2 (I/O)
8
17, 16
GPIO8 (I/O)
EPWM5A (O)
CANTXB (O)
ADCSOCAO (O)
9
19, 18
GPIO9 (I/O)
EPWM5B (O)
SCITXDB (O)
ECAP3 (I/O)
10
21, 20
GPIO10 (I/O)
EPWM6A (O)
CANRXB (I)
ADCSOCBO (O)
11
23, 22
GPIO11 (I/O)
EPWM6B (O)
SCIRXDB (I)
ECAP4 (I/O)
12
25, 24
GPIO12 (I/O)
TZ1 (I)
CANTXB (O)
MDXB (O)
13
27, 26
GPIO13 (I/O)
TZ2 (I)
CANRXB (I)
MDRB (I)
14
29, 28
GPIO14 (I/O)
TZ3 (I)/ XHOLD (I)
SCITXDB (O)
MCLKXB (I/O)
15
31, 30
GPIO15 (I/O)
TZ4 (I)/ XHOLDA (O)
SCIRXDB (I)
MFSXB (I/O)
GPAMUX2
GPAQSEL2
GPAMUX2 = 0, 0
GPAMUX2 = 0, 1
GPAMUX2 = 1, 0
GPAMUX2 = 1, 1
16
1, 0
GPIO16 (I/O)
SPISIMOA (I/O)
CANTXB (O)
TZ5 (I)
17
3, 2
GPIO17 (I/O)
SPISOMIA (I/O)
CANRXB (I)
TZ6 (I)
18
5, 4
GPIO18 (I/O)
SPICLKA (I/O)
SCITXDB (O)
CANRXA (I)
19
7, 6
GPIO19 (I/O)
SPISTEA (I/O)
SCIRXDB (I)
CANTXA (O)
20
9, 8
GPIO20 (I/O)
EQEP1A (I)
MDXA (O)
CANTXB (O)
21
11, 10
GPIO21 (I/O)
EQEP1B (I)
MDRA (I)
CANRXB (I)
22
13, 12
GPIO22 (I/O)
EQEP1S (I/O)
MCLKXA (I/O)
SCITXDB (O)
23
15, 14
GPIO23 (I/O)
EQEP1I (I/O)
MFSXA (I/O)
SCIRXDB (I)
24
17, 16
GPIO24 (I/O)
ECAP1 (I/O)
EQEP2A (I)
MDXB (O)
25
19, 18
GPIO25 (I/O)
ECAP2 (I/O)
EQEP2B (I)
MDRB (I)
26
21, 20
GPIO26 (I/O)
ECAP3 (I/O)
EQEP2I (I/O)
MCLKXB (I/O)
27
23, 22
GPIO27 (I/O)
ECAP4 (I/O)
EQEP2S (I/O)
28
25, 24
GPIO28 (I/O)
SCIRXDA (I)
XZCS6 (O)
29
27, 26
GPIO29 (I/O)
SCITXDA (O)
XA19 (O)
30
29, 28
GPIO30 (I/O)
CANRXA (I)
XA18 (O)
31
31, 30
GPIO31 (I/O)
CANTXA (O)
XA17 (O)
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Table 8-19. GPIO-B Mux Peripheral Selection Matrix
REGISTER BITS
GPBDIR
GPBDAT
GPBSET
GPBCLR
GPBTOGGLE
0
QUALPRD0
QUALPRD1
QUALPRD3
(1)
GPBMUX1
GPBQSEL1
GPIOx
GPBMUX1 = 0, 0
PER1
GPBMUX1 = 0, 1
PER2
GPBMUX1 = 1, 0
PER3
GPBMUX1 = 1, 1
1, 0
GPIO32 (I/O)
SDAA (I/OC)(1)
EPWMSYNCI (I)
ADCSOCAO (O)
(I/OC)(1)
EPWMSYNCO (O)
ADCSOCBO (O)
1
3, 2
GPIO33 (I/O)
2
5, 4
GPIO34 (I/O)
ECAP1 (I/O)
3
7, 6
GPIO35 (I/O)
SCITXDA (O)
XR/ W (O)
4
9, 8
GPIO36 (I/O)
SCIRXDA (I)
XZCS0 (O)
5
11, 10
GPIO37 (I/O)
ECAP2 (I/O)
XZCS7 (O)
6
13, 12
GPIO38 (I/O)
XWE0 (O)
7
15, 14
GPIO39 (I/O)
XA16 (O)
8
17, 16
GPIO40 (I/O)
XA0 (O)
SCLA
XREADY (I)
9
19, 18
GPIO41 (I/O)
XA1 (O)
10
21, 20
GPIO42 (I/O)
XA2 (O)
11
23, 22
GPIO43 (I/O)
12
25, 24
GPIO44 (I/O)
XA4 (O)
13
27, 26
GPIO45 (I/O)
XA5 (O)
14
29, 28
GPIO46 (I/O)
XA6 (O)
XA7 (O)
15
QUALPRD2
PERIPHERAL SELECTION
Reserved
XA3 (O)
31, 30
GPIO47 (I/O)
GPBMUX2
GPBQSEL2
GPBMUX2 = 0, 0
GPBMUX2 = 0, 1
GPBMUX2 = 1, 0
GPBMUX2 = 1, 1
16
1, 0
GPIO48 (I/O)
ECAP5 (I/O)
XD31 (I/O)
SPISIMOD (I/O)
17
3, 2
GPIO49 (I/O)
ECAP6 (I/O)
XD30 (I/O)
SPISOMID (I/O)
18
5, 4
GPIO50 (I/O)
EQEP1A (I)
XD29 (I/O)
SPICLKD (I/O)
19
7, 6
GPIO51 (I/O)
EQEP1B (I)
XD28 (I/O)
SPISTED (I/O)
20
9, 8
GPIO52 (I/O)
EQEP1S (I/O)
XD27 (I/O)
Reserved
21
11, 10
GPIO53 (I/O)
EQEP1I (I/O)
XD26 (I/O)
Reserved
22
13, 12
GPIO54 (I/O)
SPISIMOA (I/O)
XD25 (I/O)
EQEP3A (I)
23
15, 14
GPIO55 (I/O)
SPISOMIA (I/O)
XD24 (I/O)
EQEP3B (I)
24
17, 16
GPIO56 (I/O)
SPICLKA (I/O)
XD23 (I/O)
EQEP3S (I/O)
25
19, 18
GPIO57 (I/O)
SPISTEA (I/O)
XD22 (I/O)
EQEP3I (I/O)
26
21, 20
GPIO58 (I/O)
MCLKRA (I/O)
XD21 (I/O)
EPWM7A (O)
27
23, 22
GPIO59 (I/O)
MFSRA (I/O)
XD20 (I/O)
EPWM7B (O)
28
25, 24
GPIO60 (I/O)
MCLKRB (I/O)
XD19 (I/O)
EPWM8A (O)
29
27, 26
GPIO61 (I/O)
MFSRB (I/O)
XD18 (I/O)
EPWM8B (O)
30
29, 28
GPIO62 (I/O)
SCIRXDC (I)
XD17 (I/O)
EPWM9A (O)
31
31, 30
GPIO63 (I/O)
SCITXDC (O)
XD16 (I/O)
EPWM9B (O)
Open drain
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 8-20. GPIO-C Mux Peripheral Selection Matrix
REGISTER BITS
GPCDIR
GPCDAT
GPCSET
GPCCLR
GPCTOGGLE
no qual
no qual
GPCMUX1
GPIOx or PER1
GPCMUX1 = 0, 0 or 0, 1
PER2 or PER3
GPCMUX1 = 1, 0 or 1, 1
0
1, 0
GPIO64 (I/O)
XD15 (I/O)
1
3, 2
GPIO65 (I/O)
XD14 (I/O)
2
5, 4
GPIO66 (I/O)
XD13 (I/O)
3
7, 6
GPIO67 (I/O)
XD12 (I/O)
4
9, 8
GPIO68 (I/O)
XD11 (I/O)
5
11, 10
GPIO69 (I/O)
XD10 (I/O)
6
13, 12
GPIO70 (I/O)
XD9 (I/O)
7
15, 14
GPIO71 (I/O)
XD8 (I/O)
8
17, 16
GPIO72 (I/O)
XD7 (I/O)
9
19, 18
GPIO73 (I/O)
XD6 (I/O)
10
21, 20
GPIO74 (I/O)
XD5 (I/O)
11
23, 22
GPIO75 (I/O)
XD4 (I/O)
12
25, 24
GPIO76 (I/O)
XD3 (I/O)
13
27, 26
GPIO77 (I/O)
XD2 (I/O)
14
29, 28
GPIO78 (I/O)
XD1 (I/O)
15
no qual
126
PERIPHERAL SELECTION
31, 30
GPIO79 (I/O)
XD0 (I/O)
GPCMUX2
GPCMUX2 = 0, 0 or 0, 1
GPCMUX2 = 1, 0 or 1, 1
16
1, 0
GPIO80 (I/O)
XA8 (O)
17
3, 2
GPIO81 (I/O)
XA9 (O)
18
5, 4
GPIO82 (I/O)
XA10 (O)
19
7, 6
GPIO83 (I/O)
XA11 (O)
20
9, 8
GPIO84 (I/O)
XA12 (O)
21
11, 10
GPIO85 (I/O)
XA13 (O)
22
13, 12
GPIO86 (I/O)
XA14 (O)
23
15, 14
GPIO87 (I/O)
XA15 (O)
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The user can select the type of input qualification for each GPIO pin through the GPxQSEL1/2 registers from
four choices:
• Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at
reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
• Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the
input is allowed to change.
Time Between Samples
GPyCTRL Reg
GPIOx
SYNC
Qualification
Input Signal
Qualified by
3 or 6 Samples
GPxQSEL
SYSCLKOUT
Number of Samples
•
•
Figure 8-17. Qualification Using Sampling Window
The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling
window is either 3-samples or 6-samples wide and the output is only changed when all samples are the same
(all 0s or all 1s) as shown in Figure 8-17 (for 6-sample mode).
No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not
required (synchronization is performed within the peripheral).
Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral input
signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will
default to either a 0 or 1 state, depending on the peripheral.
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8.2.14 External Interface (XINTF)
This section gives a top-level view of the external interface (XINTF) that is implemented on the C2834x devices.
The XINTF is a nonmultiplexed asynchronous bus, similar to the 2812 XINTF. The XINTF is mapped into three
fixed zones shown in Figure 8-18.
Data Space
Prog Space
0x0000−0000
XD(31:0)
XA(19:0)
0x0000−4000
XINTF Zone 0
(8K x 16)
XZCS0
XINTF Zone 6
(1M x 16)
XZCS6
0x0000−5000
0x0010−0000
0x0020−0000
0x0030−0000
XZCS7
XINTF Zone 7
(1M x 16)
XWE1
XWE0
XRD
XR/W
XREADY
XHOLD
XHOLDA
XCLKOUT
Figure 8-18. External Interface Block Diagram
128
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Figure 8-19 and Figure 8-20 show typical 16-bit and 32-bit data bus XINTF connections, illustrating how the
functionality of the XA0 and XWE1 signals change, depending on the configuration. Table 8-21 defines XINTF
configuration and control registers.
XINTF
External
wait-state
generator
16-bits
XREADY
XCLKOUT
XZCS0, XZCS6, XZCS7
CS
A(19:0)
XA(19:0)
X
XWE1
OE
XRD
WE
XWE0
D(15:0)
XD(15:0)
Figure 8-19. Typical 16-Bit Data Bus XINTF Connections
XINTF
External
wait-state
generator
Low 16-bits
CS
A(18:0)
OE
WE
D(15:0)
XREADY
XCLKOUT
X
XA(0)
XA(19:1)
XRD
XWE0
XD(15:0)
High 16-bits
A(18:0)
XZCS0, XZCS6, XZCS7
CS
OE
WE
XWE1
D(31:16)
XD(31:16)
Figure 8-20. Typical 32-Bit Data Bus XINTF Connections
Table 8-21. XINTF Configuration and Control Register Mapping
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
XTIMING0
0x00−0B20
2
XINTF Timing Register, Zone 0
XTIMING6(1)
0x00−0B2C
2
XINTF Timing Register, Zone 6
XTIMING7
0x00−0B2E
2
XINTF Timing Register, Zone 7
XINTCNF2(2)
0x00−0B34
2
XINTF Configuration Register
XBANK
0x00−0B38
1
XINTF Bank Control Register
XREVISION
0x00−0B3A
1
XINTF Revision Register
XRESET
0x00−0B3D
1
XINTF Reset Register
(1)
(2)
XTIMING1 - XTIMING5 are reserved for future expansion and are not currently used.
XINTCNF1 is reserved and not currently used.
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8.3 Memory Maps
In Figure 8-21 to Figure 8-23, the following apply:
• Memory blocks are not to scale.
• Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are
restricted to data memory only. A user program cannot access these memory maps in program space.
• Protected means the order of "Write followed by Read" operations is preserved rather than the pipeline order.
See the TMS320x2834x Delfino System Control and Interrupts Reference Guide for more details.
• Certain memory ranges are EALLOW protected against spurious writes after configuration.
• If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox
RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this.
130
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Block
Start Address
On-Chip Memory
Prog Space
Data Space
0x00 0000
External Memory XINTF
Prog Space
Data Space
M0 Vector - RAM (32 x 32)
(Enable if VMAP = 0)
0x00 0040
M0 SARAM (1K x 16)
0x00 0400
M1 SARAM (1K x 16)
0x00 0800
Peripheral Frame 0
Reserved
0x00 0D00
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE =1)
0x00 0E00
Reserved
Peripheral Frame 0
0x00 2000
0x00 5000
0x00 4000
0x00 5000
XINTF Zone 0 (4K x 16, XZCS0)
(Protected) DMA Accessible
Reserved
Peripheral Frame 3
(Protected) DMA Accessible
0x00 6000
Peripheral Frame 1
(Protected)
Reserved
0x00 7000
Peripheral Frame 2
(Protected)
0x00 8000
0x00 A000
0x00 C000
0x00 E000
0x01 0000
0x01 2000
0x01 4000
0x01 6000
L0 SARAM (8K x 16, DMA Accessible)
L1 SARAM (8K x 16, DMA Accessible)
Reserved
L2 SARAM (8K x 16, DMA Accessible)
L3 SARAM (8K x 16, DMA Accessible)
L4 SARAM (8K x 16, DMA Accessible)
L5 SARAM (8K x 16, DMA Accessible)
L6 SARAM (8K x 16, DMA Accessible)
L7 SARAM (8K x 16, DMA Accessible)
0x01 8000
XINTF Zone 6 (1M x 16, XZCS6) (DMA Accessible)
Reserved
XINTF Zone 7 (1M x 16, XZCS7) (DMA Accessible)
0x30 0000
0x30 8000
0x31 0000
0x31 8000
0x32 0000
0x32 8000
0x33 0000
H0 SARAM
(32K x 16 Prefetch)
H1 SARAM
(32K x 16 Prefetch)
H2 SARAM
(32K x 16 Prefetch)
H3 SARAM
(32K x 16 Prefetch)
H4 SARAM
(32K x 16 Prefetch)
H5 SARAM
(32K x 16 Prefetch)
Reserved
0x33 FFF8
128-Bit Password
0x10 0000
0x20 0000
0x30 0000
Reserved
(A)
0x33 FFFF
Reserved
0x3F E000
Boot ROM (8K x 16)
0x3F FFC0
BROM Vector - ROM (32 x 32)
(Enable if VMAP = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps-M0 vector, PIE vector, BROM vector-should be enabled at a time.
A. These locations support compatibility with legacy C28x designs only. See Section 8.1.9.
Figure 8-21. C28346, C28345 Memory Map
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Block
Start Address
On-Chip Memory
Prog Space
Data Space
0x00 0000
External Memory XINTF
Prog Space
Data Space
M0 Vector - RAM (32 x 32)
(Enable if VMAP = 0)
0x00 0040
M0 SARAM (1K x 16)
0x00 0400
M1 SARAM (1K x 16)
0x00 0800
Peripheral Frame 0
Reserved
0x00 0D00
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE =1)
0x00 0E00
Reserved
Peripheral Frame 0
0x00 2000
XINTF Zone 0 (4K x 16, XZCS0)
(Protected) DMA Accessible
Reserved
0x00 5000
0x00 4000
0x00 5000
Peripheral Frame 3
(Protected) DMA Accessible
0x00 6000
Peripheral Frame 1
(Protected)
Reserved
0x00 7000
Peripheral Frame 2
(Protected)
0x00 8000
0x00 A000
0x00 C000
0x00 E000
0x01 0000
0x01 2000
0x01 4000
0x01 6000
L0 SARAM (8K x 16, DMA Accessible)
L1 SARAM (8K x 16, DMA Accessible)
Reserved
L2 SARAM (8K x 16, DMA Accessible)
L3 SARAM (8K x 16, DMA Accessible)
L4 SARAM (8K x 16, DMA Accessible)
L5 SARAM (8K x 16, DMA Accessible)
L6 SARAM (8K x 16, DMA Accessible)
L7 SARAM (8K x 16, DMA Accessible)
0x01 8000
XINTF Zone 6 (1M x 16, XZCS6) (DMA Accessible)
Reserved
0x20 0000
XINTF Zone 7 (1M x 16, XZCS7) (DMA Accessible)
0x30 0000
0x10 0000
0x30 0000
H0 SARAM
(32K x 16 Prefetch)
0x30 8000
H1 SARAM
(32K x 16 Prefetch)
0x31 0000
Reserved
Reserved
0x33 FFF8
128-Bit Password
(A)
0x33 FFFF
Reserved
0x3F E000
Boot ROM (8K x 16)
0x3F FFC0
BROM Vector - ROM (32 x 32)
(Enable if VMAP = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps-M0 vector, PIE vector, BROM vector-should be enabled at a time.
A. These locations support compatibility with legacy C28x designs only. See Section 8.1.9.
Figure 8-22. C28344, C28343 Memory Map
132
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Block
Start Address
On-Chip Memory
Prog Space
Data Space
0x00 0000
External Memory XINTF
Prog Space
Data Space
M0 Vector - RAM (32 x 32)
(Enable if VMAP = 0)
0x00 0040
M0 SARAM (1K x 16)
0x00 0400
M1 SARAM (1K x 16)
0x00 0800
Peripheral Frame 0
Reserved
0x00 0D00
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE =1)
0x00 0E00
Reserved
Peripheral Frame 0
0x00 2000
0x00 5000
0x00 4000
0x00 5000
XINTF Zone 0 (4K x 16, XZCS0)
(Protected) DMA Accessible
Reserved
Peripheral Frame 3
(Protected) DMA Accessible
0x00 6000
Peripheral Frame 1
(Protected)
Reserved
0x00 7000
Peripheral Frame 2
(Protected)
0x00 8000
0x00 A000
0x00 C000
0x00 E000
L0 SARAM (8K x 16, DMA Accessible)
L1 SARAM (8K x 16, DMA Accessible)
Reserved
L2 SARAM (8K x 16, DMA Accessible)
L3 SARAM (8K x 16, DMA Accessible)
0x01 0000
Reserved
0x10 0000
XINTF Zone 6 (1M x 16, XZCS6) (DMA Accessible)
0x20 0000
XINTF Zone 7 (1M x 16, XZCS7) (DMA Accessible)
0x30 0000
0x30 8000
0x31 0000
0x30 0000
H0 SARAM
(32K x 16 Prefetch)
H1 SARAM
(32K x 16 Prefetch)
Reserved
Reserved
0x33 FFF8
128-Bit Password
(A)
0x33 FFFF
Reserved
0x3F E000
Boot ROM (8K x 16)
0x3F FFC0
BROM Vector - ROM (32 x 32)
(Enable if VMAP = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps-M0 vector, PIE vector, BROM vector-should be enabled at a time.
A. These locations support compatibility with legacy C28x designs only. See Section 8.1.9.
Figure 8-23. C28342, C28341 Memory Map
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Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these blocks to
be write/read peripheral block protected. The protected mode ensures that all accesses to these blocks happen
as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory locations,
will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral
applications where the user expected the write to occur first (as written). The C28x CPU supports a block
protection mode where a region of memory can be protected so as to make sure that operations occur as written
(the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it will
protect the selected zones.
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The wait states for the various spaces in the memory map area are listed in Table 8-22.
Table 8-22. Wait States
AREA
WAIT STATES
(CPU)
WAIT STATES
(DMA)(1)
M0 and M1 SARAMs
0-wait
No access
Peripheral Frame 0
0-wait (writes)
No access (writes)
1-wait (reads)
0-wait (reads)
0-wait (writes)
0-wait (writes)
2-wait (reads)
1-wait (reads)
Peripheral Frame 3
Peripheral Frame 1
0-wait (writes)
2-wait (reads)
Peripheral Frame 2
0-wait (writes)
2-wait (reads)
L0 SARAM
L1 SARAM
COMMENTS
Fixed
Assumes no conflicts between CPU and DMA.
Cycles can be extended by peripheral generated ready.
No access
No access
0-wait data and
program
Consecutive writes to the CAN will experience a 1-cycle
pipeline hit.
Fixed. Cycles cannot be extended by the peripheral.
Assumes no CPU conflicts
L2 SARAM
L3 SARAM
1-wait
L4 SARAM
Assumes no conflicts between CPU and DMA
L5 SARAM
L6 SARAM
1-wait
L7 SARAM
XINTF
Programmable
Programmed through the XTIMING registers or extendable
through external XREADY signal.
1-wait minimum
1-wait is minimum wait states allowed on external waveforms
for both reads and writes on XINTF.
0-wait minimum writes
with write buffer
enabled
H0 SARAM
0-wait data (write)
0-wait data (read)
A program-access prefetch mechanism is enabled on these
memories to improve instruction fetch performance for linear
code execution.
1-wait
H1 SARAM
H2 SARAM
0-wait minimum for writes assumes write buffer enabled and
not full.
Assumes no conflicts between CPU and DMA. When DMA
and CPU try simultaneous conflict, 1-cycle delay is added for
arbitration.
No access
H3 SARAM
H4 SARAM
H5 SARAM
Boot-ROM
(1)
1-wait
No access
The DMA has a base of four cycles/word.
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8.4 Register Map
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0:
These are peripherals that are mapped directly to the CPU memory bus. See Table 8-23.
Peripheral Frame 1
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 8-24.
Peripheral Frame 2:
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 8-25.
Peripheral Frame 3:
These are peripherals that are mapped to the 32-bit DMA-accessible peripheral bus. See Table 8-26.
Table 8-23. Peripheral Frame 0 Registers (1)
NAME
ACCESS TYPE(2)
ADDRESS RANGE
SIZE (x16)
Device Emulation Registers
0x00 0880 – 0x00 09FF
384
EALLOW protected
Code Security Module Registers
0x00 0AE0 – 0x00 0AEF
16
EALLOW protected
XINTF Registers
0x00 0B20 – 0x00 0B3F
32
Not EALLOW protected
CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
Registers
0x00 0C00 – 0x00 0C3F
64
Not EALLOW protected
PIE Registers
0x00 0CE0 – 0x00 0CFF
32
Not EALLOW protected
PIE Vector Table
0x00 0D00 – 0x00 0DFF
256
EALLOW protected
DMA Registers
0x00 1000 – 0x00 11FF
512
EALLOW protected
(1)
(2)
Registers in Frame 0 support 16-bit and 32-bit accesses.
If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
Table 8-24. Peripheral Frame 1 Registers
NAME
ADDRESS RANGE
SIZE (x16)
eCAN-A Registers
0x00 6000 – 0x00 61FF
512
eCAN-B Registers
0x00 6200 – 0x00 63FF
512
ePWM1 + HRPWM1 Registers
0x00 6800 – 0x00 683F
64
ePWM2 + HRPWM2 Registers
0x00 6840 – 0x00 687F
64
ePWM3 + HRPWM3 Registers
0x00 6880 – 0x00 68BF
64
ePWM4 + HRPWM4 Registers
0x00 68C0 – 0x00 68FF
64
ePWM5 + HRPWM5 Registers
0x00 6900 – 0x00 693F
64
ePWM6 + HRPWM6 Registers
0x00 6940 – 0x00 697F
64
ePWM7 + HRPWM7 Registers
0x00 6980 – 0x00 69BF
64
ePWM8 + HRPWM8 Registers
0x00 69C0 – 0x00 69FF
64
ePWM9 + HRPWM9 Registers
0x00 6600 – 0x00 663F
64
eCAP1 Registers
0x00 6A00 – 0x00 6A1F
32
eCAP2 Registers
0x00 6A20 – 0x00 6A3F
32
eCAP3 Registers
0x00 6A40 – 0x00 6A5F
32
eCAP4 Registers
0x00 6A60 – 0x00 6A7F
32
eCAP5 Registers
0x00 6A80 – 0x00 6A9F
32
eCAP6 Registers
0x00 6AA0 – 0x00 6ABF
32
eQEP1 Registers
0x00 6B00 – 0x00 6B3F
64
eQEP2 Registers
0x00 6B40 – 0x00 6B7F
64
eQEP3 Registers
0x00 6B80 – 0x00 6BBF
64
GPIO Registers
0x00 6F80 – 0x00 6FFF
128
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Table 8-25. Peripheral Frame 2 Registers
NAME
ADDRESS RANGE
SIZE (x16)
System Control Registers
0x00 7010 – 0x00 702F
32
SPI-A Registers
0x00 7040 – 0x00 704F
16
SCI-A Registers
0x00 7050 – 0x00 705F
16
External Interrupt Registers
0x00 7070 – 0x00 707F
16
SCI-B Registers
0x00 7750 – 0x00 775F
16
SCI-C Registers
0x00 7770 – 0x00 777F
16
SPI-D Registers
0x00 7780 – 0x00 778F
16
I2C-A Registers
0x00 7900 – 0x00 793F
64
Table 8-26. Peripheral Frame 3 Registers
NAME
ADDRESS RANGE
SIZE (x16)
McBSP-A Registers
0x00 5000 – 0x00 503F
64
McBSP-B Registers
0x00 5040 – 0x00 507F
64
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8.4.1 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. The registers are defined in Table 8-27.
Table 8-27. Device Emulation Registers
ADDRESS
RANGE
SIZE (x16)
DEVICECNF
0x0880
0x0881
2
Device Configuration Register
PARTID
0x0882
1
Part ID Register
NAME
DESCRIPTION
TMS320C28346
0xFFD0
TMS320C28345
0xFFD1
TMS320C28344
0xFFD2
TMS320C28343
0xFFD3
TMS320C28342
0xFFD4
TMS320C28341
0xFFD5
REVID
0x0883
1
Revision ID
Register
PROTSTART
0x0884
1
Block Protection Start Address Register
PROTRANGE
0x0885
1
Block Protection Range Address Register
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8.5 Interrupts
Figure 8-24 shows how the various interrupt sources are multiplexed.
WAKEINT
DMA
C28
Core
PIE
INT1
to
INT12
96 Interrupts
XINT1
Clear
WDINT
Sync
LPMINT
Watchdog
Low Power Models
SYSCLKOUT
Interrupt Control
XINT1
Latch
MUX
DMA
Peripherals
(A),
(SPI, SCI, I2C, CAN, McBSP
EPWM, ECAP, EQEP)
XINT1CR(15:0)
XINT1CTR(15:0)
GPIOXINT1SEL(4:0)
XINT2
XINT2
Latch
Interrupt Control
MUX
DMA
XINT2CR(15:0)
XINT2CTR(15:0)
GPIOXINT2SEL(4:0)
DMA
TINT0
CPU Timer 0
DMA
TINT2
CPU Timer 2
NMI
CPU Timer 1
Interrupt Control
MUX
INT13
MUX
TINT1
XNMI_
XINT13
GPIO0.int
Latch
MUX
INT14
XNMICR(15:0)
1
GPIO
Mux
GPIO31.int
XNMICTR(15:0)
GPIOXNMISEL(4:0)
DMA
A. DMA-accessible
Figure 8-24. External and PIE Interrupt Sources
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XINT3
Interrupt Control
Latch
Mux
DMA
XINT3CR(15:0)
GPIOXINT3SEL(4:0)
XINT4
Interrupt Control
Latch
Mux
DMA
XINT4CR(15:0)
PIE
C28
Core
XINT5
Interrupt Control
Latch
Mux
INT1
to
INT12
96 Interrupts
GPIOXINT4SEL(4:0)
DMA
XINT5CR(15:0)
GPIOXINT5SEL(4:0)
XINT6
Interrupt Control
Latch
Mux
DMA
XINT6CR(15:0)
GPIOXINT6SEL(4:0)
DMA
Interrupt Control
Latch
Mux
GPIO32.int
XINT7
XINT7CR(15:0)
GPIO63.int
GPIO
Mux
GPIOXINT7SEL(4:0)
Figure 8-25. External Interrupts
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts
per group equals 96 possible interrupts. On the C2834x devices, 64 of these are used by peripherals as shown
in Table 8-28.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to
the vector specified. TRAP #0 tries to transfer program control to the address pointed to by the reset vector. The
PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the
PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 to TRAP #12 will transfer program control to the interrupt service routine
corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1,
TRAP #2 fetches the vector from INT2.1, and so forth.
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IFR(12:1)
INTM
IER(12:1)
INT1
INT2
1
CPU
MUX
0
INT11
INT12
(Flag)
Global
Enable
(Enable)
INTx.1
INTx.2
INTx
INTx.3
INTx.4
MUX
From
Peripherals
or
External
Interrupts
INTx.5
INTx.6
INTx.7
PIEACKx
INTx.8
(Enable)
(Flag)
PIEIERx(8:1)
PIEIFRx(8:1)
(Enable/Flag)
Figure 8-26. Multiplexing of Interrupts Using the PIE Block
Table 8-28. PIE Peripheral Interrupts (1)
CPU
INTERRUPTS
(1)
PIE INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INT1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
INTx.4
INTx.3
INTx.2
INTx.1
Reserved
XINT2
XINT1
Reserved
Reserved
Reserved
INT2
EPWM8_TZINT
(ePWM8)
EPWM7_TZINT
(ePWM7)
EPWM6_TZINT
(ePWM6)
EPWM5_TZINT
(ePWM5)
EPWM4_TZINT
(ePWM4)
EPWM3_TZINT
(ePWM3)
EPWM2_TZINT
(ePWM2)
EPWM1_TZINT
(ePWM1)
INT3
EPWM8_INT
(ePWM8)
EPWM7_INT
(ePWM7)
EPWM6_INT
(ePWM6)
EPWM5_INT
(ePWM5)
EPWM4_INT
(ePWM4)
EPWM3_INT
(ePWM3)
EPWM2_INT
(ePWM2)
EPWM1_INT
(ePWM1)
INT4
Reserved
Reserved
ECAP6_INT
(eCAP6)
ECAP5_INT
(eCAP5)
ECAP4_INT
(eCAP4)
ECAP3_INT
(eCAP3)
ECAP2_INT
(eCAP2)
ECAP1_INT
(eCAP1)
INT5
Reserved
Reserved
Reserved
Reserved
Reserved
EQEP3_INT
(eQEP3)
EQEP2_INT
(eQEP2)
EQEP1_INT
(eQEP1)
INT6
SPITXINTD
(SPI-D)
SPIRXINTD
(SPI-D)
MXINTA
(McBSP-A)
MRINTA
(McBSP-A)
MXINTB
(McBSP-B)
MRINTB
(McBSP-B)
SPITXINTA
(SPI-A)
SPIRXINTA
(SPI-A)
INT7
Reserved
Reserved
DINTCH6
(DMA)
DINTCH5
(DMA)
DINTCH4
(DMA)
DINTCH3
(DMA)
DINTCH2
(DMA)
DINTCH1
(DMA)
INT8
Reserved
Reserved
SCITXINTC
(SCI-C)
SCIRXINTC
(SCI-C)
Reserved
Reserved
I2CINT2A
(I2C-A)
I2CINT1A
(I2C-A)
INT9
ECAN1_INTB
(CAN-B)
ECAN0_INTB
(CAN-B)
ECAN1_INTA
(CAN-A)
ECAN0_INTA
(CAN-A)
SCITXINTB
(SCI-B)
SCIRXINTB
(SCI-B)
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
INT10
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EPWM9_TZINT
(ePWM9)
INT11
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EPWM9_INT
(ePWM9)
INT12
LUF
(FPU)
LVF
(FPU)
Reserved
XINT7
XINT6
XINT5
XINT4
XINT3
Out of the 96 possible interrupts, 64 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group
is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there is one safe case when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
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Table 8-29. PIE Configuration and Control Registers
NAME
PIECTRL
SIZE (x16)
0x0CE0
1
DESCRIPTION(1)
PIE, Control Register
PIEACK
0x0CE1
1
PIE, Acknowledge Register
PIEIER1
0x0CE2
1
PIE, INT1 Group Enable Register
PIEIFR1
0x0CE3
1
PIE, INT1 Group Flag Register
PIEIER2
0x0CE4
1
PIE, INT2 Group Enable Register
PIEIFR2
0x0CE5
1
PIE, INT2 Group Flag Register
PIEIER3
0x0CE6
1
PIE, INT3 Group Enable Register
PIEIFR3
0x0CE7
1
PIE, INT3 Group Flag Register
PIEIER4
0x0CE8
1
PIE, INT4 Group Enable Register
PIEIFR4
0x0CE9
1
PIE, INT4 Group Flag Register
PIEIER5
0x0CEA
1
PIE, INT5 Group Enable Register
PIEIFR5
0x0CEB
1
PIE, INT5 Group Flag Register
PIEIER6
0x0CEC
1
PIE, INT6 Group Enable Register
PIEIFR6
0x0CED
1
PIE, INT6 Group Flag Register
PIEIER7
0x0CEE
1
PIE, INT7 Group Enable Register
PIEIFR7
0x0CEF
1
PIE, INT7 Group Flag Register
PIEIER8
0x0CF0
1
PIE, INT8 Group Enable Register
PIEIFR8
0x0CF1
1
PIE, INT8 Group Flag Register
PIEIER9
0x0CF2
1
PIE, INT9 Group Enable Register
PIEIFR9
0x0CF3
1
PIE, INT9 Group Flag Register
PIEIER10
0x0CF4
1
PIE, INT10 Group Enable Register
PIEIFR10
0x0CF5
1
PIE, INT10 Group Flag Register
PIEIER11
0x0CF6
1
PIE, INT11 Group Enable Register
PIEIFR11
0x0CF7
1
PIE, INT11 Group Flag Register
PIEIER12
0x0CF8
1
PIE, INT12 Group Enable Register
PIEIFR12
0x0CF9
1
PIE, INT12 Group Flag Register
Reserved
0x0CFA – 0x0CFF
6
Reserved
(1)
142
ADDRESS
The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector
table is protected.
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8.5.1 External Interrupts
Table 8-30. External Interrupt Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
XINT1CR
0x00 7070
1
XINT1 configuration register
XINT2CR
0x00 7071
1
XINT2 configuration register
XINT3CR
0x00 7072
1
XINT3 configuration register
XINT4CR
0x00 7073
1
XINT4 configuration register
XINT5CR
0x00 7074
1
XINT5 configuration register
XINT6CR
0x00 7075
1
XINT6 configuration register
XINT7CR
0x00 7076
1
XINT7 configuration register
XNMICR
0x00 7077
1
XNMI configuration register
XINT1CTR
0x00 7078
1
XINT1 counter register
XINT2CTR
0x00 7079
1
XINT2 counter register
Reserved
0x707A – 0x707E
5
XNMICTR
0x00 707F
1
XNMI counter register
Each external interrupt can be enabled or disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the TMS320x2834x Delfino System Control and Interrupts Reference
Guide.
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8.6 System Control
This section describes the oscillator, PLL and clocking mechanisms, the watchdog function and the low-power
modes. Figure 8-27 shows the various clock and reset domains that will be discussed.
C28x Core
SYSCLKOUT
LSPCLK
LOSPCP
SPI-A/D, SCI-A/B/C
Peripheral
registers
Clock enables
/4
I/O
Peripheral
registers
eCAN-A/B
Peripheral bus
I/O
Bridge
Memory bus
Clock enables
System
control
register
Clock enables
GPIO
Mux
Bridge
I/O
ePWM1/../9, HRPWM1/../9,
eCAP1/../6, eQEP1/../3
Peripheral
registers
Clock enables
LOSPCP
LSPCLK
I/O
Peripheral
registers
McBSP-A/B
Bridge
Clock enable
CPU timer
registers
CPU timer 0/1/2
EXTADCCLK
Clock enable
HISPCP
EXTSOC
Bridge
Peripheral
registers
I2C-A
DMA
bus
ADC SOC
DMA
Clock Enables
Figure 8-27. Clock and Reset Domains
Note
There is a 2-SYSCLKOUT cycle delay from when the write to the PCLKCR0, PCLKCR1, and
PCLKCR2 registers (enables peripheral clocks) occurs to when the action is valid. This delay must be
considered before trying to access the peripheral configuration registers.
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The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 8-31.
Table 8-31. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
PLLSTS
0x00 7011
1
PLL Status Register
Reserved
0x00 7012 – 0x00 7018
7
Reserved
PCLKCR2
0x00 7019
1
Peripheral Clock Control Register 2
HISPCP
0x00 701A
1
High-Speed Peripheral Clock Prescaler Register
LOSPCP
0x00 701B
1
Low-Speed Peripheral Clock Prescaler Register
PCLKCR0
0x00 701C
1
Peripheral Clock Control Register 0
PCLKCR1
0x00 701D
1
Peripheral Clock Control Register 1
LPMCR0
0x00 701E
1
Low-Power Mode Control Register 0
Reserved
0x00 701F
1
Reserved
PCLKCR3
0x00 7020
1
Peripheral Clock Control Register 3
PLLCR
0x00 7021
1
PLL Control Register
SCSR
0x00 7022
1
System Control and Status Register
WDCNTR
0x00 7023
1
Watchdog Counter Register
Reserved
0x00 7024
1
Reserved
WDKEY
Reserved
WDCR
Reserved
0x00 7025
1
Watchdog Reset Key Register
0x00 7026 – 0x00 7028
3
Reserved
0x00 7029
1
Watchdog Control Register
0x00 702A – 0x00 702C
3
Reserved
EXTSOCCFG
0x00 702D
1
External ADC SOC Configuration Register
Reserved
0x00 702E
1
Reserved
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8.6.1 OSC and PLL Block
Figure 8-28 shows the OSC and PLL block.
XCLKIN
(3.3-V clock input
from external
oscillator)
OSCCLK
OSCCLK
0
PLLSTS[OSCOFF]
PLL
OSCCLK or
VCOCLK
VCOCLK
n
/1
/2
/4
/8
CLKIN
To
CPU
n≠ 0
PLLSTS[PLLOFF]
External
Crystal or
Resonator
PLLSTS[DIVSEL]
X1
On-chip
oscillator
5-bit multiplier PLLCR[DIV]
X2
Figure 8-28. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the C2834x devices using the X1 and
X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the following
configurations:
• A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied to VSSK . The logic-high level in this case should not exceed VDDIO.
• A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left unconnected
and the XCLKIN pin tied to VSS . The logic-high level in this case should not exceed VDD18 .
The three possible input-clock configurations are shown in Figure 8-29 to Figure 8-31.
XCLKIN
VSSK
X1
X2
NC
External Clock Signal
(Toggling 0 -VDDIO)
Figure 8-29. Using a 3.3-V External Oscillator
XCLKIN
X1
X2
External Clock Signal
(Toggling 0-VDD)
NC
Figure 8-30. Using a 1.8-V External Oscillator
XCLKIN
X1
X2
VSSK
VDD18
Crystal
1.8 V
C1
C2
Figure 8-31. Using the Internal Oscillator
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8.6.1.1 External Reference Oscillator Clock Option
The on-chip oscillator requires an external crystal to be connected across the X1 and X2 pins.
The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 8-31.
The load capacitors, C1 and C2, must be chosen such that the equation below is satisfied (typical values are on
the order of C1 = C2 = 10 pF). CL in the equation is the load specified for the crystal. All discrete components
used to implement the oscillator circuit must be placed as close as possible to the associated oscillator pins (X1,
X2, and VSSK).
Note
The external crystal load capacitors must be connected only to the oscillator ground pin (VSSK). Do not
connect to board ground (VSS).
CL +
C 1C 2
(C1 ) C2)
Where: CL equals the crystal load capacitance.
TI recommends that customers have the crystal vendor characterize the operation of their device with the MCU
chip. The crystal vendor has the equipment and expertise to tune the crystal circuit. The vendor can also advise
the customer regarding the proper component values that will produce proper start up and stability over the
entire operating range.
8.6.1.2 PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals
for the device, as well as control for low-power mode entry. The PLL has a 5-bit ratio control PLLCR[DIV] to
select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register.
It can be re-enabled (if need be) after the PLL module has stabilized. The input clock and PLLCR[DIV] bits
should be chosen in such a way that the output frequency of the PLL (VCOCLK) falls between 400 MHz and
600 MHz. The PLLSTS[DIVSEL] bit should be selected such that SYSCLKOUT(CLKIN) does not exceed the
maximum operating frequency allowed for the device (300 MHz or 200 MHz). For example, suppose it is desired
to operate a 300-MHz device at 100 MHz using a 20-MHz OSCCLK input (that is, for power savings). The PLL
should be configured for OSCCLK * 20, which produces VCOCLK = 400 MHz. PLLSTS[DIVSEL] should then be
configured for /4 mode, resulting in the desired 100-MHz CLKIN to the CPU. The PLL should not be configured
for OSCCLK * 10 with PLLSTS[DIVSEL] set for /2 mode. This combination would produce VCOCLK = 200 MHz,
which does not fall within the required 400 MHz to 600 MHz range.
Table 8-32. PLL Settings (1)
SYSCLKOUT (CLKIN)
PLLCR[DIV]
VALUE(3) (4)
PLLSTS[DIVSEL] = 0
00000 (PLL bypass)
OSCCLK/8 (Default)
00001
(OSCCLK * 2)/8
00010
(OSCCLK * 3)/8
(OSCCLK * 3)/4
(OSCCLK * 3)/2
–
00011
(OSCCLK * 4)/8
(OSCCLK * 4)/4
(OSCCLK * 4)/2
–
00100
(OSCCLK * 5)/8
(OSCCLK * 5)/4
(OSCCLK * 5)/2
–
00101
(OSCCLK * 6)/8
(OSCCLK * 6)/4
(OSCCLK * 6)/2
–
00110
(OSCCLK * 7)/8
(OSCCLK * 7)/4
(OSCCLK * 7)/2
–
PLLSTS[DIVSEL] = 1
PLLSTS[DIVSEL] = 2
PLLSTS[DIVSEL] = 3 (2)
OSCCLK/4
OSCCLK/2
OSCCLK
(OSCCLK * 2)/4
(OSCCLK * 2)/2
–
00111
(OSCCLK * 8)/8
(OSCCLK * 8)/4
(OSCCLK * 8)/2
–
01000
(OSCCLK * 9)/8
(OSCCLK * 9)/4
(OSCCLK * 9)/2
–
01001
(OSCCLK * 10)/8
(OSCCLK * 10)/4
(OSCCLK * 10)/2
–
01010
(OSCCLK * 11)/8
(OSCCLK * 11)/4
(OSCCLK * 11)/2
–
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Table 8-32. PLL Settings (1) (continued)
PLLCR[DIV]
VALUE(3) (4)
01011 – 11111
(1)
(2)
(3)
(4)
148
PLLSTS[DIVSEL] = 0
PLLSTS[DIVSEL] = 1
(OSCCLK * 12)/8 –
(OSCCLK * 32)/8
(OSCCLK * 12)/4 –
(OSCCLK * 32)/4
SYSCLKOUT (CLKIN)
PLLSTS[DIVSEL] = 2
PLLSTS[DIVSEL] = 3 (2)
(OSCCLK * 12)/2 –
(OSCCLK * 32)/2
–
PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and must be set only to 1 or 2 after PLLSTS[PLLLOCKS] = 1. At reset,
PLLSTS[DIVSEL] is configured for /8. The boot ROM changes this to /2 or /1, depending on the boot option.
PLLSTS[DIVSEL] = 3 should be used only when the PLL is bypassed or off.
The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic have no effect.
This register is EALLOW protected. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide for more
information.
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Table 8-33. CLKIN Divide Options
PLLSTS [DIVSEL]
CLKIN DIVIDE
0
/8
1
/4
2
/2
3
/1
The PLL-based clock module provides two modes of operation:
•
Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base to the
device.
External clock source operation - This mode allows the internal oscillator to be bypassed. The device clocks
are generated from an external clock source input on the X1 or the XCLKIN pin.
•
Table 8-34. Possible PLL Configuration Modes
REMARKS
PLLSTS[DIVSEL](1)
CLKIN AND
SYSCLKOUT
PLL Off
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
0
1
2
3
OSCCLK/8
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Bypass
PLL Bypass is the default PLL configuration upon power up or after an external
reset ( XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
0
1
2
3
OSCCLK/8
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Enable
Achieved by writing a nonzero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
0
1
2
3
OSCCLK*n/8
OSCCLK*n/4
OSCCLK*n/2
–(2)
PLL MODE
(1)
(2)
PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and must be set to 1 or 2 only after PLLSTS[PLLLOCKS] = 1. See the
TMS320x2834x Delfino System Control and Interrupts Reference Guide for more information.
PLLSTS[DIVSEL] should not be set to /1 mode while the PLL is enabled and not bypassed.
8.6.1.3 Loss of Input Clock
Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism
by which the MCU will be held in reset, should the input clocks ever fail. For example, an R-C circuit may be
used to trigger the XRS pin of the MCU, should the capacitor ever get fully charged. An I/O pin may be used to
discharge the capacitor on a periodic basis to prevent it from getting fully charged.
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8.6.2 Watchdog Block
The watchdog block on the C2834x device is similar to the one used on the 240x and 281x devices. The
watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the
software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the
watchdog counter. Figure 8-32 shows the various functional blocks within the watchdog module.
WDCR (WDPS[2:0])
WDCR (WDDIS)
WDCNTR[7:0]
OSCCLK
Watchdog
Prescaler
/512
WDCLK
8-Bit
Watchdog
Counter
CLR
Clear Counter
Internal
Pullup
WDKEY[7:0]
Watchdog
55 + AA
Key Detector
Generate
Output Pulse
(512 OSCCLKs)
Good Key
WDRST
WDINT
XRS
Core-reset
Bad
WDCHK
Key
SCSR (WDENINT)
WDCR (WDCHK[2:0])
(A)
WDRST
1
0
1
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 8-32. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is
the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the LPM block so that
it can wake the device from STANDBY (if enabled). See Section 8.7, Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, through the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the
WATCHDOG.
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8.7 Low-Power Modes Block
The low-power modes on the C2834x devices are similar to the 240x devices. Table 8-35 summarizes the
various modes.
Table 8-35. Low-Power Modes
EXIT(1)
MODE
LPMCR0(1:0)
OSCCLK
CLKIN
SYSCLKOUT
IDLE
00
On
On
On(2)
XRS, watchdog interrupt, any enabled
interrupt, XNMI
STANDBY
01
On
(watchdog still running)
Off
Off
XRS, watchdog interrupt, GPIO Port A
signal, debugger(3), XNMI
HALT
1X
Off
(oscillator and PLL turned off,
watchdog not functional)
Off
Off
XRS, GPIO port A signal, XNMI,
debugger(3)
(1)
(2)
(3)
The EXIT column lists which signals or under what conditions the low-power mode will be exited. A low signal, on any of the signals,
will exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise,
the low-power mode will not be exited and the device will go back into the indicated low-power mode.
The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is
still functional while on the 24x/240x the clock is turned off.
On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE mode:
This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor. The
LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY mode:
Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must
select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are
also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the
LPMCR0 register.
HALT mode:
Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT mode. The
user selects the signal in the GPIOLPMSEL register.
Note
The low-power modes do not affect the state of the output pins (PWM pins included). They will be in
whatever state the code left them in when the IDLE instruction was executed. See the TMS320x2834x
Delfino System Control and Interrupts Reference Guide for more details.
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9 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 TI Design or Reference Design
TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at TIDesigns.
C2000 Resolver to Digital Conversion Kit
This is a motherboard-style Resolver to Digital conversion kit used to experiment with various C2000™
microcontrollers for software-based resolver to digital conversion using on-chip ADCs. The Resolver Kit also
allows interface to resolvers and inverter control processor.
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10 Device and Documentation Support
10.1 Getting Started
This section gives a brief overview of the steps to take when first developing for a C28x device. For more detail
on each of these steps, see the following:
• C2000 Real-Time Control MCUs – Getting started
• C2000 Real-Time Control MCUs – Tools & software
• Motor drive and control
• Digital power
10.2 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ MCU devices and support tools. Each TMS320™ commercial family member has one of three
prefixes: TMX, TMP, or TMS (for example, TMS 320C28345). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages
of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/
tools (TMS/TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device's electrical specifications
TMP
Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability
verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification testing
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, ZFE) and temperature range (for example, T). Figure 10-1 provides a legend for reading the
complete device name for any family member.
For device part numbers and further ordering information, see the Package Option Addendum of this document,
the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320C2834x Delfino™
MCUs Silicon Errata .
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Figure 10-1. Example of C2834x Device Nomenclature
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10.3 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions are listed below. To view all available tools and software for
C2000™ real-time control MCUs, visit the C2000 MCU Tools and Software page.
Design Kits and Evaluation Modules
C2000 Delfino MCUs F28377S LaunchPad Development Kit
The C2000™ Delfino™ MCUs LaunchPad™ development kit is an inexpensive evaluation platform that provides
designers with a low-cost development kit for high-performance digital control applications. This tool provides a
great starting point for development of many high-end digital control applications such as industrial drives and
automation; power line communications; solar inverters; and more.
Delfino C28343 controlCARD
The C28343 controlCARD allows users to easily evaluate all the functionality of the 200-MHz C28343 floatingpoint controller and is compatible with existing controlCARD tool kits. The card provides all the chip support
necessary, needing only a 5-V supply to be fully functional. The controlCARD also has two onboard 12-bit ADCs
and a 64KB EEPROM for nonvolatile program storage. Based on the standard DIM100 controlCARD form factor,
it is pin-compatible with other C2000 controlCARDs.
Software
C2000 DesignDRIVE Software for Industrial Drives and Motor Control
The DesignDRIVE platform combines software solutions with DesignDRIVE Development Kits to make it easy to
develop and evaluate solutions for many industrial drive and servo topologies. DesignDRIVE offers support for a
wide variety of motor types, sensing technologies, position sensors and communications networks, including
specific examples for vector control of motors, incorporating current, speed and position loops, to help
developers jumpstart their evaluation and development. Based on the real-time control architecture of TI’s
C2000™ microcontrollers (MCUs), DesignDRIVE is ideal for the development of industrial inverter and servo
drives used in robotics, computer numerical control machinery (CNC), elevators, materials conveyance and
other industrial manufacturing applications.
powerSUITE Digital Power Supply Software Frequency Response Analyzer Tool for C2000™ MCUs
The Software Frequency Response Analyzer (SFRA) is one of several tools included in the powerSUITE Digital
Power Supply Design Software Tools for C2000™ Microcontrollers. The SFRA includes a software library that
enables developers to quickly measure the frequency response of their digital power converter. The SFRA library
contains software functions that inject a frequency into the control loop and measure the response of the system
using the C2000 MCUs’ on-chip analog to digital converter (ADC). This process provides the plant frequency
response characteristics and the open loop gain frequency response of the closed loop system. The user can
then view the plant and open loop gain frequency response on a PC-based GUI. All of the frequency response
data is exported into a CSV file, or optionally an Excel® spreadsheet, which can then be used to design the
compensation loop using the Compensation Designer.
C2000Ware for C2000 MCUs
C2000Ware for C2000™ microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device peripheral
examples, C2000Ware provides a solid foundation to begin development and evaluation of your product.
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Development Tools
C2000 Gang Programmer
The C2000 Gang Programmer is a C2000 device programmer that can program up to eight identical C2000
devices at the same time. The C2000 Gang Programmer connects to a host PC using a standard RS-232 or
USB connection and provides flexible programming options that allow the user to fully customize the process.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user
through each step of the application development flow. Familiar tools and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework
with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development
environment for embedded developers.
Models
Various models are available for download from the product Tools & Software pages. These include I/O Buffer
Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all
available models, visit the Models section of the Tools & Software page for each device.
10.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral is
listed below.
Errata
TMS320C2834x Delfino™ MCUs Silicon Errata describes the advisories and usage notes for different versions
of silicon.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also
describes emulation features available on these DSPs.
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, and
instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control MCU Peripherals Reference Guide describes the peripheral reference guides of the
28x digital signal processors (DSPs).
TMS320x2834x Delfino System Control and Interrupts Reference Guide This document describes the various
interrupts and system control features of the x2834x microcontroller (MCUs).
TMS320x2834x Delfino External Interface (XINTF) Reference Guide This document describes the XINTF, which
is a nonmultiplexed asynchronous bus, as it is used on the x2834x device.
TMS320x2834x Delfino Boot ROM Reference Guide This document describes the purpose and features of the
bootloader (factory-programmed boot-loading software) and provides examples of code. It also describes other
contents of the device on-chip boot ROM and identifies where all of the information is located within that
memory.
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TMS320x2834x Delfino Multichannel Buffered Serial Port (McBSP) Reference Guide This document describes
the McBSP available on the x2834x devices. The McBSPs allow direct interface between a microcontroller
(MCU) and other devices in a system.
TMS320x2834x Delfino Direct Memory Access (DMA) Module Reference Guide This document describes the
DMA on the x2834x microcontroller (MCUs).
TMS320x2834x Delfino Enhanced Pulse Width Modulator (ePWM) Module Reference Guide This document
describes the main areas of the enhanced pulse width modulator that include digital motor control, switch mode
power supply control, UPS (uninterruptible power supplies), and other forms of power conversion.
TMS320x2834x Delfino High Resolution Pulse Width Modulator (HRPWM) Reference Guide This document
describes the operation of the high-resolution extension to the pulse width modulator (HRPWM).
TMS320x2834x Delfino Enhanced Capture (eCAP) Module Reference Guide This document describes the
enhanced capture module. It includes the module description and registers.
TMS320x2834x Delfino Enhanced Quadrature Encoder Pulse (eQEP) Module Reference Guide This document
describes the eQEP module, which is used for interfacing with a linear or rotary incremental encoder to get
position, direction, and speed information from a rotating machine in high performance motion and position
control systems. It includes the module description and registers.
TMS320x2834x Delfino Enhanced Controller Area Network (eCAN) Reference Guide This document describes
the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy
environments.
TMS320x2834x Delfino Serial Communications Interface (SCI) Reference Guide This document describes the
SCI, which is a 2-wire asynchronous serial port, commonly known as a UART. The SCI modules support digital
communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero
(NRZ) format.
TMS320x2834x Delfino Serial Peripheral Interface (SPI) Reference Guide This document describes the SPI - a
high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of programmed length (1 to
16 bits) to be shifted into and out of the device at a programmed bit-transfer rate.
TMS320x2834x Delfino Inter-Integrated Circuit (I2C) Module Reference Guide This document describes the
features and operation of the inter-integrated circuit (I2C) module.
Tools Guides
TMS320C28x Assembly Language Tools v20.2.0.LTS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v20.2.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
TMS320C28x DSP/BIOS 5.x Application Programming Interface (API) Reference Guide describes development
using DSP/BIOS.
Application Reports
The SMT & packaging application notes website lists documentation on TI’s surface mount technology (SMT)
and application notes on a variety of packaging-related topics.
TMS320C28x FPU Primer provides an overview of the floating-point unit (FPU) in the C2000™ Delfino
microcontroller devices.
Running an Application from Internal Flash Memory on the TMS320F28xxx DSP covers the requirements
needed to properly configure application software for execution from on-chip flash memory. Requirements for
both DSP/BIOS and non-DSP/BIOS projects are presented. Example code projects are included.
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Programming TMS320x28xx and TMS320x28xxx Peripherals in C/C++ explores a hardware abstraction layer
implementation to make C/C++ coding easier on 28x DSPs. This method is compared to traditional #define
macros and topics of code efficiency and special case registers are also addressed.
Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x Digital Signal Controller presents a
method for using the on-chip pulse width modulated (PWM) signal generators on the TMS320F280x family of
digital signal controllers as a digital-to-analog converter (DAC).
TMS320F280x Digital Signal Controller USB Connectivity using the TUSB3410 USB-to-UART Bridge Chip
presents hardware connections as well as software preparation and operation of the development system using
a simple communication echo program.
Using the Enhanced Quadrature Encoder Pulse (eQEP) Module in TMS320x280x, 28xxx as a Dedicated
Capture provides a guide for the use of the eQEP module as a dedicated capture unit and is applicable to the
TMS320x280x, 28xxx family of processors.
Using the ePWM Module for 0% - 100% Duty Cycle Control provides a guide for the use of the ePWM module to
provide 0% to 100% duty cycle control and is applicable to the TMS320x280x family of processors.
TMS320x2833x/2823x to TMS320x2834x Delfino Migration Overview This application report describes
differences between the Texas Instruments TMS320x2833x/2823x and the TMS320x2834x devices to assist in
application migration.
Online Stack Overflow Detection on the TMS320C28x DSP presents the methodology for online stack overflow
detection on the TMS320C28x DSP. C-source code is provided that contains functions for implementing the
overflow detection on both DSP/BIOS and non-DSP/BIOS applications.
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
Semiconductor and IC Package Thermal Metrics describes traditional and new thermal metrics and puts their
application in perspective with respect to system-level junction temperature estimation.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures and future trends.
10.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.6 Trademarks
MicroStar BGA™, Delfino™, C2000™, Piccolo™, DSP/BIOS™, Code Composer Studio™, and TI E2E™ are
trademarks of Texas Instruments.
Excel® is a registered trademark of Microsoft Corporation in the United States and/or other countries.
All trademarks are the property of their respective owners.
10.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
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10.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
26-May-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
TMS320C28341ZAYT
ACTIVE
NFBGA
ZAY
179
160
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
TMS320
C28341ZAYT
TMS320C28342ZFET
ACTIVE
BGA
ZFE
256
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
TMS
320C28342ZFET
TMS320C28343ZAYT
ACTIVE
NFBGA
ZAY
179
160
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
TMS320
C28343ZAYT
TMS320C28343ZFEQ
ACTIVE
BGA
ZFE
256
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 125
TMS
320C28343ZFEQ
TMS320C28344ZFET
ACTIVE
BGA
ZFE
256
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
TMS
320C28344ZFET
TMS320C28345ZAYT
ACTIVE
NFBGA
ZAY
179
160
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
TMS320
C28345ZAYT
TMS320C28345ZFET
ACTIVE
BGA
ZFE
256
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
TMS
320C28345ZFET
TMS320C28346ZFEQ
ACTIVE
BGA
ZFE
256
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 125
TMS
320C28346ZFEQ
TMS320C28346ZFET
ACTIVE
BGA
ZFE
256
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
TMS
320C28346ZFET
TMS320C28346ZFETR
ACTIVE
BGA
ZFE
256
750
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
TMS320
C28346ZFET
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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