TMS320C44PDB60

TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 D Highest Performance Floating-Point Digital D D D D D D D D D Signal Processor (DSP) − TMS320C44-60: 33-ns Instruction Cycle Time, 330 MOPS, 60 MFLOPS, 30 MIPS, 336M Bytes/s − TMS320C44-50: 40-ns Instruction Cycle Time Four Communication Ports Six-Channel Direct Memory Address (DMA) Coprocessor Single-Cycle Conversion to and From IEEE-754 Floating-Point Format Single Cycle, 1/x, 1/√x Source-Code Compatible With C3x and C4x Single-Cycle 40-Bit Floating-Point, 32-Bit Integer Multipliers Twelve 40-Bit Registers, Eight Auxiliary Registers, 14 Control Registers, and Two Timers IEEE-1149.1† (JTAG) Boundary-Scan Compatible Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers − High Port-Data Rate of 120M Bytes/s (TMS320C44-60) (Each Bus) − 128M-Byte Program/Data/Peripheral Address Space − Memory-Access Request for Fast, Intelligent Bus Arbitration − Separate Address-Bus, Data-Bus, and Control-Enable Pins − Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware D Fabricated Using 0.72-µm Enhanced D D D D D D D D D Performance Implanted CMOS (EPIC) Technology by Texas Instruments (TI) Separate Internal Program-, Data-, and DMA-Coprocessor Buses for Support of Massive Concurrent I/O of Program and Data, Thereby Maximizing Sustained CPU Performance IDLE2 Clock-Stop Power-Down Mode Communication-Port-Direction Pin On-Chip Program Cache and Dual-Access/Single-Cycle RAM for Increased Memory-Access Performance − 512-Byte Instruction Cache − 8K Bytes of Single-Cycle Dual-Access Program or Data RAM − ROM-Based Boot Loader Supports Program Bootup Using 8-, 16-, or 32-Bit Memories or One of the Communication Ports Software-Communication-Port Reset NMI With Bus-Grant Feature 304-Pin Plastic Quad Flatpack (PDB Suffix) (Commercial Temperature) 388-Pin Plastic Ball Grid Array (GFW Suffix) (Commercial Temperature) 388-Pin Plastic Ball Grid Array (GFW Suffix) (Industrial Temperature) description The TMSC44 DSP is a 32-bit, floating-point processor manufactured in 0.72-µm double-level-metal CMOS technology. The TMSC44 is part of the TMS320C4x generation of DSPs from Texas Instruments. The on-chip parallel-processing capabilities of the C44 make the immense floating-point performance required by many applications achievable. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † IEEE Standard 1149.1−1990 Standard Test-Access Port and Boundary-Scan Architecture. EPIC and TI are trademarks of Texas Instruments. All trademarks are the property of their respective owners. Copyright  2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 1 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 operation The C44 has four on-chip communication ports for processor-to-processor communication with no external hardware and simple communication software. This allows connectivity with no external-glue logic. The communication ports remove input/output bottlenecks, and the independent smart 6-channel DMA coprocessor is able to handle the CPU input/output burden. To fit the C40 into a 304-pin PQFP package (thermally enhanced plastic quad flatpack), two communication ports are removed and the external local and global address buses are reduced to 24 address lines each. In this case, both the bond pads and driver circuits are removed, decreasing die size and power consumption. Otherwise, functionality remains the same as the rest of the C4x family. The communication-port token and data-strobe control lines are internally connected to avoid spurious data, boot-up, and power consumption problems. functions This section lists signal descriptions for the C44 device: each signal, number of pins, operating mode(s) (that is, input, output, or high-impedance state as indicated by I, O, or Z, respectively), and function. The signals are grouped according to function. Pin Functions SIGNAL NAME NO. OF PINS TYPE† DESCRIPTION GLOBAL-BUS EXTERNAL INTERFACE (73 pins) D31 −D0 32 I/O/Z DE 1 I 32-bit data port of the global-bus external interface A23 −A0 24 O/Z AE 1 I Address-bus-enable signal for the global-bus external interface STAT3 −STAT0 4 O Status signals for the global-bus external interface LOCK 1 O Lock signal for the global-bus external interface STRB0‡ 1 O/Z Access strobe 0 for the global-bus external interface R / W0‡ 1 O/Z Read / write signal for STRB0 accesses PAGE0‡ 1 O/Z Page signal for STRB0 accesses RDY0‡ 1 I Ready signal for STRB0 accesses CE0‡ 1 I Control enable for the STRB0, PAGE0, and R / W0 signals STRB1‡ 1 O/Z Access strobe 1 for the global-bus external interface R / W1‡ 1 O/Z Read / write signal for STRB1 accesses PAGE1‡ 1 O/Z Page signal for STRB1 accesses RDY1‡ 1 I Ready signal for STRB1 accesses CE1‡ 1 I Control enable for the STRB1, PAGE1, and R / W1 signals LD31 −LD0 32 I/O/Z Data-bus-enable signal for the global-bus external interface 24-bit address port of the global-bus external interface LOCAL-BUS EXTERNAL INTERFACE (73 pins) 32-bit data port of the local-bus external interface LDE 1 I LA23 −LA0 24 O/Z Data-bus-enable signal for the local-bus external interface LAE 1 I Address-bus-enable signal for the local-bus external interface LSTAT3 −LSTAT0 4 O Status signals for the local-bus external interface LLOCK 1 O Lock signal for the local-bus external interface 24-bit address port of the local-bus external interface † I = input, O = output, Z = high impedance ‡ The effective address range is defined by the local /global STRB ACTIVE bits in the memory interface-control registers. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 Pin Functions (Continued) SIGNAL NAME NO. OF PINS TYPE† DESCRIPTION LOCAL-BUS EXTERNAL INTERFACE (73 pins) (Continued) LSTRB0‡ 1 O/Z Access strobe 0 for the local-bus external interface LR / W0 1 O/Z Read / write signal for LSTRB0 accesses LPAGE0 1 O/Z Page signal for LSTRB0 accesses LRDY0 1 I Ready signal for LSTRB0 accesses LCE0 1 I Control enable for the LSTRB0, LPAGE0, and LR / W0 signals LSTRB1‡ 1 O/Z Access strobe 1 for the local-bus external interface LR / W1 1 O/Z Read / write signal for LSTRB1 accesses LPAGE1 1 O/Z Page signal for LSTRB1 accesses LRDY1 1 I Ready signal for LSTRB1 accesses LCE1 1 I Control enable for the LSTRB1, LPAGE1, and LR / W1 signals C1D7 −C1D0 8 I/O Communication port 1 data bus CREQ1 1 I/O Communication port 1 token-request signal CACK1 1 I/O Communication port 1 token-request-acknowledge signal CSTRB1 1 I/O Communication port 1 data-strobe signal CRDY1 1 I/O Communication port 1 data-ready signal CDIR1 1 O Communication port 1 direction signal COMMUNICATION PORT 1 INTERFACE (13 pins) COMMUNICATION PORT 2 INTERFACE (13 pins) C2D7 −C2D0 8 I/O Communication port 2 data bus CREQ2 1 I/O Communication port 2 token-request signal CACK2 1 I/O Communication port 2 token-request-acknowledge signal CSTRB2 1 I/O Communication port 2 data-strobe signal CRDY2 1 I/O Communication port 2 data-ready signal CDIR2 1 O Communication port 2 direction signal COMMUNICATION PORT 4 INTERFACE (13 pins) C4D7 −C4D0 8 I/O Communication port 4 data bus CREQ4 1 I/O Communication port 4 token-request signal CACK4 1 I/O Communication port 4 token-request-acknowledge signal CSTRB4 1 I/O Communication port 4 data-strobe signal CRDY4 1 I/O Communication port 4 data-ready signal CDIR4 1 O Communication port 4 direction signal C5D7 −C5D0 8 I/O Communication port 5 data bus CREQ5 1 I/O Communication port 5 token-request signal CACK5 1 I/O Communication port 5 token-request-acknowledge signal CSTRB5 1 I/O Communication port 5 data-strobe signal CRDY5 1 I/O Communication port 5 data-ready signal CDIR5 1 O Communication port 5 direction signal COMMUNICATION PORT 5 INTERFACE (13 pins) † I = input, O = output, Z = high impedance ‡ The effective address range is defined by the local /global STRB ACTIVE bits in the memory interface-control registers. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 3 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 Pin Functions (Continued) SIGNAL NAME NO. OF PINS TYPE† DESCRIPTION INTERRUPTS, I / O FLAGS, RESET, TIMER (12 pins) IIOF3 −IIOF0 4 I/O NMI 1 I Interrupt and I / O flags Nonmaskable interrupt. NMI is sensitive to a low-going edge. IACK 1 O Interrupt acknowledge RESET 1 I Reset signal RESETLOC1 RESETLOC0 2 I Reset-vector location ROMEN 1 I On-chip ROM enable (0 = disable, 1 = enable) TCLK0 1 I/O Timer 0 TCLK1 1 I/O Timer 1 X1 1 O Crystal X2 / CLKIN 1 I Crystal /oscillator H1 1 O H1 clock H3 1 O H3 clock CLOCK (4 pins) POWER (71 pins) CVSS 17 I Ground DVSS 17 I Ground IVSS 6 I Ground DVDD 22 I 5-VDC supply VSUBS 1 I Substrate (tie to ground) VDDL 4 I 5-VDC supply VSSL 4 I Ground EMULATION (7 pins) TCK 1 I IEEE 1149.1 test port clock TDI 1 I IEEE 1149.1 test port data in TDO 1 O/Z TMS 1 I IEEE 1149.1 test port mode select TRST 1 I IEEE 1149.1 test port reset EMU0 1 I/O Emulation pin 0 EMU1 1 I/O Emulation pin 1 † ‡ 4 IEEE 1149.1 test port data out I = input, O = output, Z = high impedance The effective address range is defined by the local /global STRB ACTIVE bits in the memory interface-control registers. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 304-PIN PDB PLASTIC QUAD FLATPACK (TOP VIEW) 304 229 1 228 76 153 77 152 PDB Package Pin Assignments — Alphabetical Listing PIN PIN PIN PIN NAME NO. NAME NO. NAME NO. NAME NO. A0 149 C2D7 34 CVSS 134 D24 137 A1 150 C4D0 87 CVSS 117 D25 138 A2 151 C4D1 88 CVSS 102 D26 140 A3 152 C4D2 90 CVSS 78 D27 141 A4 154 C4D3 92 CVSS 62 D28 142 A5 155 C4D4 94 CVSS 44 D29 143 A6 156 C4D5 97 CVSS 25 D30 144 A7 157 C4D6 99 CVSS 7 D31 145 A8 158 C4D7 100 CVSS 282 DE 89 A9 159 C5D0 37 CVSS 262 DVDD 139 A10 160 C5D1 39 CVSS 247 DVDD 124 A11 162 C5D2 41 CVSS 230 DVDD 109 A12 165 C5D3 42 CVSS 218 DVDD 96 A13 166 C5D4 45 CVSS 202 DVDD 83 A14 167 C5D5 46 CVSS 182 DVDD 67 A15 168 C5D6 47 CVSS 164 DVDD 51 A16 169 C5D7 48 D0 104 DVDD 40 A17 170 CACK1 13 D1 105 DVDD 28 A18 171 CACK2 21 D2 106 DVDD 17 A19 174 CACK4 73 D3 107 DVDD 302 A20 175 CACK5 50 D4 108 DVDD 288 A21 176 CDIR1 19 D5 110 DVDD 272 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 5 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 PDB Package Pin Assignments — Alphabetical Listing (Continued) PIN 6 PIN PIN PIN NAME NO. NAME NO. NAME NO. NAME NO. A22 177 CDIR2 18 D6 111 DVDD 256 A23 178 CDIR4 16 D7 112 DVDD 244 AE 57 CDIR5 15 D8 113 DVDD 236 C1D0 269 CE0 93 D9 114 DVDD 223 C1D1 271 CE1 101 D10 115 DVDD 207 C1D2 274 CRDY1 8 D11 118 DVDD 188 C1D3 276 CRDY2 23 D12 120 DVDD 172 C1D4 278 CRDY4 85 D13 122 DVDD 161 C1D5 280 CRDY5 53 D14 123 DVDD 153 C1D6 283 CREQ1 11 D15 125 DVSS 147 C1D7 286 CREQ2 20 D16 127 DVSS 133 C2D0 26 CREQ4 71 D17 128 DVSS 116 C2D1 27 CREQ5 49 D18 129 DVSS 103 C2D2 29 CSTRB1 14 D19 130 DVSS 79 C2D3 30 CSTRB2 22 D20 131 DVSS 63 C2D4 31 CSTRB4 84 D21 132 DVSS 43 C2D5 32 CSTRB5 52 D22 135 DVSS 24 C2D6 33 CVSS 148 D23 136 DVSS 6 DVSS 281 LA17 253 LD30 228 STAT0 68 DVSS 261 LA18 254 LD31 229 STAT1 66 DVSS 246 LA19 255 LDE 291 STAT2 64 DVSS 231 LA20 257 LLOCK 284 STAT3 61 DVSS 217 LA21 258 LOCK 95 STRB0 58 DVSS 201 LA22 259 LPAGE0 299 STRB1 69 DVSS 179 LA23 260 LPAGE1 294 TCK 86 DVSS 163 LAE 287 LRDY0 298 TCLK0 290 EMU0 75 LCE0 297 LRDY1 293 TCLK1 289 EMU1 74 LCE1 292 LR / W0 300 TDI 76 H1 266 LD0 183 LR / W1 295 TDO 80 H3 268 LD1 184 LSTAT0 279 TMS 82 IACK 270 LD2 185 LSTAT1 277 TRST 81 IIOF0 10 LD3 186 LSTAT2 275 VDDL 38 IIOF1 9 LD4 187 LSTAT3 273 VDDL 121 IIOF2 5 LD5 192 LSTRB0 301 VDDL 191 IIOF3 4 LD6 194 LSTRB1 296 VDDL 267 IVSS 126 LD7 195 NC 1 VSSL 36 IVSS 65 LD8 196 NC 77 VSSL 119 IVSS 35 LD9 197 NC 173 VSSL 193 IVSS 2 LD10 200 NC 180 VSSL 265 IVSS 285 LD11 203 NC 181 VSUBS 146 IVSS 209 LD12 204 NC 189 X1 264 LA0 232 LD13 205 NC 190 X2 / CLKIN 263 LA1 233 LD14 206 NC 198 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 PDB Package Pin Assignments — Alphabetical Listing (Continued) PIN PIN PIN PIN NAME NO. NAME NO. NAME NO. LA2 234 LD15 208 NC 199 LA3 235 LD16 210 NC 214 LA4 237 LD17 211 NC 303 LA5 238 LD18 212 NC 304 LA6 239 LD19 213 NMI 3 LA7 240 LD20 215 PAGE0 60 LA8 241 LD21 216 PAGE1 72 LA9 242 LD22 219 RDY0 91 LA10 243 LD23 220 RDY1 98 LA11 245 LD24 221 RESET 54 LA12 248 LD25 222 RESETLOC0 55 LA13 249 LD26 224 RESETLOC1 56 LA14 250 LD27 225 ROMEN 12 LA15 251 LD28 226 R / W0 59 LA16 252 LD29 227 R / W1 70 NAME NO. PDB Package Pin Assignments — Numerical Listing PIN NO. PIN PIN PIN NAME NO. NAME NO. NAME NO. NAME 1 NC 41 C5D2 81 TRST 121 VDDL 2 IVSS 42 C5D3 82 TMS 122 D13 3 NMI 43 DVSS 83 DVDD 123 D14 4 IIOF3 44 CVSS 84 CSTRB4 124 DVDD 5 IIOF2 45 C5D4 85 CRDY4 125 D15 6 DVSS 46 C5D5 86 TCK 126 IVSS 7 CVSS 47 C5D6 87 C4D0 127 D16 8 CRDY1 48 C5D7 88 C4D1 128 D17 9 IIOF1 49 CREQ5 89 DE 129 D18 10 IIOF0 50 CACK5 90 C4D2 130 D19 D20 11 CREQ1 51 DVDD 91 RDY0 131 12 ROMEN 52 CSTRB5 92 C4D3 132 D21 13 CACK1 53 CRDY5 93 CE0 133 DVSS 14 CSTRB1 54 RESET 94 C4D4 134 CVSS 15 CDIR5 55 RESETLOC0 95 LOCK 135 D22 16 CDIR4 56 RESETLOC1 96 DVDD 136 D23 17 DVDD 57 AE 97 C4D5 137 D24 18 CDIR2 58 STRB0 98 RDY1 138 D25 19 CDIR1 59 R / W0 99 C4D6 139 DVDD 20 CREQ2 60 PAGE0 100 C4D7 140 D26 21 CACK2 61 STAT3 101 CE1 141 D27 22 CSTRB2 62 CVSS 102 CVSS 142 D28 23 CRDY2 63 DVSS 103 DVSS 143 D29 24 DVSS 64 STAT2 104 D0 144 D30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 7 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 PDB Package Pin Assignments — Numerical Listing (Continued) PIN 8 PIN PIN PIN NO. NAME NO. NAME NO. NAME NO. NAME 25 CVSS 65 IVSS 105 D1 145 D31 26 C2D0 66 STAT1 106 D2 146 VSUBS 27 C2D1 67 DVDD 107 D3 147 DVSS 28 DVDD 68 STAT0 108 D4 148 CVSS 29 C2D2 69 STRB1 109 DVDD 149 A0 30 C2D3 70 R / W1 110 D5 150 A1 31 C2D4 71 CREQ4 111 D6 151 A2 32 C2D5 72 PAGE1 112 D7 152 A3 33 C2D6 73 CACK4 113 D8 153 DVDD 34 C2D7 74 EMU1 114 D9 154 A4 35 IVSS 75 EMU0 115 D10 155 A5 36 VSSL 76 TDI 116 DVSS 156 A6 37 C5D0 77 NC 117 CVSS 157 A7 38 VDDL 78 CVSS 118 D11 158 A8 39 C5D1 79 DVSS 119 VSSL 159 A9 40 DVDD 80 TDO 120 D12 160 A10 161 DVDD 201 DVSS 241 LA8 281 DVSS 162 A11 202 CVSS 242 LA9 282 CVSS 163 DVSS 203 LD11 243 LA10 283 C1D6 164 CVSS 204 LD12 244 DVDD 284 LLOCK 165 A12 205 LD13 245 LA11 285 IVSS 166 A13 206 LD14 246 DVSS 286 C1D7 167 A14 207 DVDD 247 CVSS 287 LAE 168 A15 208 LD15 248 LA12 288 DVDD 169 A16 209 IVSS 249 LA13 289 TCLK1 170 A17 210 LD16 250 LA14 290 TCLK0 171 A18 211 LD17 251 LA15 291 LDE 172 DVDD 212 LD18 252 LA16 292 LCE1 173 NC 213 LD19 253 LA17 293 LRDY1 174 A19 214 NC 254 LA18 294 LPAGE1 175 A20 215 LD20 255 LA19 295 LR / W1 176 A21 216 LD21 256 DVDD 296 LSTRB1 177 A22 217 DVSS 257 LA20 297 LCE0 178 A23 218 CVSS 258 LA21 298 LRDY0 179 DVSS 219 LD22 259 LA22 299 LPAGE0 180 NC 220 LD23 260 LA23 300 LR / W0 181 NC 221 LD24 261 DVSS 301 LSTRB0 182 CVSS 222 LD25 262 CVSS 302 DVDD 183 LD0 223 DVDD 263 X2 / CLKIN 303 NC 184 LD1 224 LD26 264 X1 304 NC 185 LD2 225 LD27 265 VSSL 186 LD3 226 LD28 266 H1 187 LD4 227 LD29 267 VDDL POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 PDB Package Pin Assignments — Numerical Listing (Continued) PIN PIN PIN PIN NO. NAME NO. NAME NO. NAME 188 DVDD 228 LD30 268 H3 189 NC 229 LD31 269 C1D0 190 NC 230 CVSS 270 IACK 191 VDDL 231 DVSS 271 C1D1 192 LD5 232 LA0 272 DVDD 193 VSSL 233 LA1 273 LSTAT3 194 LD6 234 LA2 274 C1D2 195 LD7 235 LA3 275 LSTAT2 196 LD8 236 DVDD 276 C1D3 197 LD9 237 LA4 277 LSTAT1 198 NC 238 LA5 278 C1D4 199 NC 239 LA6 279 LSTAT0 200 LD10 240 LA7 280 C1D5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 NO. NAME 9 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 388-PIN GFW BALL GRID ARRAY (BOTTOM VIEW) AF AE AD AC AB AA Y W V U T R P N M L K J H G T R P N M L 11 16 F E D C B A 1 26 NOTES: A. N/C = No connection to this frame pin B. Numbers around the detail in this figure are ball pin numbers. C. VSS ground potential ring is connected to the BGA ball pins as listed: A1, A2, A26, B2, B25, B26, C3, C24, D4, D9, D14, D19, D23, H4, J23, L11 −L16, M11 −M16, N4, P23, V4, W23, AC4, AC8, AC13, AC18, AC23, AD3, AD24, AE1, AE2, AE25, AF1, AF25, AF26. (The following VSS pins are also thermal connections) L11 − L16, T11 − T16, M11 − M16, N11 − N16, P11 − P16, R11 − R16. D. VDD power potential ring is connected to the BGA ball pins as listed: D6, D11, D16, D21, F4, F23, L4, L23, T4, T23, AA4, AA23, AC6, AC11, AC16, AC21. GFW Package Pin Assignments Numerical Listing by Ball Pin Number PIN † 10 PIN PIN NO. NAME NO. NAME NO. A1 VSS B17 LD13 A2 VSS B18 N/C A3 N/C B19 LD16 A4 A7 B20 LD19 A5 N/C B21 N/C A6 N/C B22 A7 A14 B23 A8 A18 A9 A10 PIN NAME NO. NAME D7 N/C G25 N/C D8 A15 G26 N/C D9 VSS H1 N/C D10 A21 H2 D22 D11 VDD H3 D21 LD25 D12 N/C H4 VSS LD27 D13 N/C H23 LA11 B24 LD29 D14 VSS H24 LA10 N/C B25 VSS D15 LD6 H25 LA13 A22 B26 VSS D16 VDD H26 LA12 A11 N/C C1 A1 D17 N/C J1 D19 A12 LD1 C2 A2 D18 N/C J2 D20 A13 N/C C3 VSS D19 VSS J3 D17 A14 N/C C4 A4 D20 N/C J4 N/C A15 LD9 C5 A6 D21 VDD J23 VSS Thermal connection POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 GFW Package Pin Assignments Numerical Listing by Ball Pin Number (Continued) PIN PIN PIN NAME NO. NAME NO. NAME NO. NAME A16 N/C C6 A10 D22 LD24 J24 N/C A17 LD11 C7 N/C D23 VSS J25 LA16 A18 LD14 C8 A13 D24 N/C J26 LA14 A19 LD15 C9 A17 D25 LA3 K1 D16 A20 LD18 C10 A19 D26 LA1 K2 D18 A21 LD20 C11 A23 E1 D29 K3 N/C A22 LD22 C12 N/C E2 V(SUB) K4 N/C A23 N/C C13 LD2 E3 D30 K23 LA17 A24 LD28 C14 LD4 E4 D31 K24 LA15 A25 LD30 C15 LD5 E23 LA2 K25 N/C A26 VSS C16 LD8 E24 LA0 K26 LA18 B1 A3 C17 N/C E25 LA5 L1 D14 B2 VSS C18 LD12 E26 LA4 L2 D15 B3 A5 C19 N/C F1 N/C L3 D12 B4 A9 C20 LD17 F2 D28 L4 VDD B5 A11 C21 LD21 F3 D26 L11 VSS† B6 A12 C22 LD23 F4 VDD L12 VSS† B7 A16 C23 LD26 F23 VDD L13 VSS† B8 N/C C24 VSS F24 N/C L14 VSS† B9 A20 C25 N/C F25 LA9 L15 VSS† B10 N/C C26 LD31 F26 LA7 L16 VSS† B11 LD0 D1 N/C G1 D24 L23 VDD B12 LD3 D2 A0 G2 D25 L24 LA19 B13 N/C D3 N/C G3 D23 L25 LA23 B14 LD7 D4 VSS G4 D27 L26 LA21 B15 LD10 D5 A8 G23 LA8 M1 N/C B16 N/C D6 VDD G24 LA6 M2 D13 M3 N/C R3 D3 W1 N/C AC11 VDD M4 D11 R4 D1 W2 C4D5 AC12 C5D3 M11 VSS† R11 VSS† W3 RDY0 AC13 VSS M12 VSS† R12 VSS† W4 CE0 AC14 N/C M13 R13 VSS AC15 C2D2 W24 LLOCK AC16 VDD R15 VSS† VSS† VSS† W23 M16 VSS† VSS† VSS† W25 LAE AC17 N/C M15 VSS† R16 VSS† W26 N/C AC18 VSS M23 LA20 R23 IACK Y1 C4D3 AC19 N/C M24 LA22 R24 H3 Y2 C4D4 AC20 CACK1 M25 X2CLKIN R25 C1D2 Y3 C4D0 AC21 VDD M26 N/C R26 LSTAT3 Y4 DE AC22 N/C N1 N/C T1 D2 Y23 LRDY1 AC23 VSS N2 N/C T2 D4 Y24 N/C AC24 LRW0 N3 D7 T3 N/C Y25 TCLK0 AC25 LSTRB0 M14 † PIN NO. R14 Thermal connection POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 11 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 GFW Package Pin Assignments Numerical Listing by Ball Pin Number (Continued) PIN PIN NO. NAME NO. NAME NO. NAME N4 VSS T4 VDD Y26 TCLK1 AC26 LPAGE0 N11 VSS† T11 VSS† AA1 C4D1 AD1 N/C N12 VSS† T12 VSS† AA2 C4D2 AD2 N/C N13 T13 CSTRB4 AD3 VSS AA4 VDD AD4 PAGE1 AA23 VDD AD5 STAT0 T16 VSS† VSS† VSS† VSS† AA3 N16 VSS† VSS† VSS† VSS† AA24 LCE1 AD6 STAT2 N23 H1 T23 VDD AA25 LPAGE1 AD7 PAGE0 N24 N/C T24 N/C AA26 LDE AD8 RESETLOC1 N25 N/C T25 LSTAT1 AB1 CRDY4 AD9 CSTRB5 N26 N/C T26 LSTAT2 AB2 TCK AD10 C5D7 P1 D8 U1 N/C AB3 TDO AD11 N/C P2 D10 U2 D0 AB4 TMS AD12 N/C P3 D5 U3 C4D6 AB23 LCE0 AD13 N/C P4 D9 U4 CE1 AB24 LSTRB1 AD14 C2D7 P11 VSS† U23 C1D4 AB25 LRDY0 AD15 C2D4 P12 U24 C1D3 AB26 LRW1 AD16 C2D1 U25 N/C AC1 TRST AD17 CRDY2 U26 LSTAT0 AC2 N/C AD18 CDIR1 P15 VSS† VSS† VSS† VSS† V1 RDY1 AC3 N/C AD19 CDIR5 P16 VSS† V2 C4D7 AC4 VSS AD20 CREQ1 P23 VSS V3 LOCK AC5 STRB1 AD21 CRDY1 P24 X1 V4 VSS AC6 VDD AD22 IIOF3 P25 C1D1 V23 C1D7 AC7 N/C AD23 N/C P26 C1D0 V24 C1D5 AC8 VSS AD24 VSS R1 N/C V25 C1D6 AC9 STRB0 AD25 N/C N15 P13 P14 12 PIN NAME N14 † PIN NO. T14 T15 R2 D6 V26 N/C AC10 CACK5 AD26 N/C AE1 VSS AE14 C5D1 AF1 VSS AF14 C5D0 AE2 VSS AE15 N/C AF2 TD1 AF15 C2D6 AE3 EMU0 AE16 C2D5 AF3 EMU1 AF16 C2D3 AE4 CACK4 AE17 N/C AF4 CREQ4 AF17 C2D0 AE5 RW1 AE18 N/C AF5 N/C AF18 CSTRB2 AE6 STAT1 AE19 CACK2 AF6 N/C AF19 CREQ2 AE7 N/C AE20 CDIR2 AF7 STAT3 AF20 CDIR4 AE8 RW0 AE21 CSTRB1 AF8 AE AF21 ROMEN AE9 RESETLOC0 AE22 IIOF0 AF9 RESET AF22 IIOF1 AE10 CRDY5 AE23 N/C AF10 N/C AF23 IIOF2 AE11 CREQ5 AE24 NMI AF11 C5D6 AF24 N/C AE12 C5D5 AE25 VSS AF12 C5D4 AF25 VSS AE13 N/C AE26 N/C AF13 C5D2 AF26 VSS Thermal connection POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 GFW Package Pin Assignments Alphabetical Listing by Ball Pin Function PIN † PIN PIN NO. FUNCTION NO. FUNCTION D2 A0 AA1 C1 A1 AA2 C2 A2 PIN NO. FUNCTION NO. FUNCTION C4D1 P3 C4D2 R2 D5 E25 LA5 D6 G24 Y1 C4D3 LA6 N3 D7 F26 LA7 B1 A3 Y2 C4D4 P1 D8 G23 LA8 C4 A4 W2 C4D5 P4 D9 F25 LA9 LA10 B3 A5 U3 C4D6 P2 D10 H24 C5 A6 V2 C4D7 M4 D11 H23 LA11 A4 A7 AF14 C5D0 L3 D12 H26 LA12 D5 A8 AE14 C5D1 M2 D13 H25 LA13 B4 A9 AF13 C5D2 L1 D14 J26 LA14 C6 A10 AC12 C5D3 L2 D15 K24 LA15 B5 A11 AF12 C5D4 K1 D16 J25 LA16 B6 A12 AE12 C5D5 J3 D17 K23 LA17 C8 A13 AF11 C5D6 K2 D18 K26 LA18 A7 A14 AD10 C5D7 J1 D19 L24 LA19 D8 A15 AC20 CACK1 J2 D20 M23 LA20 B7 A16 AE19 CACK2 H3 D21 L26 LA21 C9 A17 AE4 CACK4 H2 D22 M24 LA22 LA23 A8 A18 AC10 CACK5 G3 D23 L25 C10 A19 AD18 CDIR1 G1 D24 W25 LAE B9 A20 AE20 CDIR2 G2 D25 AB23 LCE0 D10 A21 AF20 CDIR4 F3 D26 AA24 LCE1 A10 A22 AD19 CDIR5 G4 D27 B11 LD0 C11 A23 W4 CE0 F2 D28 A12 LD1 AF8 AE U4 CE1 E1 D29 C13 LD2 P26 C1D0 AD21 CRDY1 E3 D30 B12 LD3 P25 C1D1 AD17 CRDY2 E4 D31 C14 LD4 R25 C1D2 AB1 CRDY4 Y4 DE C15 LD5 U24 C1D3 AE10 CRDY5 AE3 EMU0 D15 LD6 U23 C1D4 AD20 CREQ1 AF3 EMU1 B14 LD7 V24 C1D5 AF19 CREQ2 N23 H1 C16 LD8 V25 C1D6 AF4 CREQ4 R24 H3 A15 LD9 V23 C1D7 AE11 CREQ5 R23 IACK B15 LD10 AF17 C2D0 AE21 CSTRB1 AE22 IIOF0 A17 LD11 AD16 C2D1 AF18 CSTRB2 AF22 IIOF1 C18 LD12 AC15 C2D2 AA3 CSTRB4 AF23 IIOF2 B17 LD13 AF16 C2D3 AD9 CSTRB5 AD22 IIOF3 A18 LD14 AD15 C2D4 U2 D0 E24 LA0 A19 LD15 AE16 C2D5 R4 D1 D26 LA1 B19 LD16 AF15 C2D6 T1 D2 E23 LA2 C20 LD17 AD14 C2D7 R3 D3 D25 LA3 A20 LD18 Y3 C4D0 T2 D4 E26 LA4 B20 LD19 Thermal connection POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 13 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 GFW Package Pin Assignments Alphabetical Listing by Ball Pin Function (Continued) PIN † 14 PIN PIN PIN NO. FUNCTION NO. FUNCTION NO. FUNCTION NO. FUNCTION A21 LD20 AC7 N/C G25 N/C AB2 TCK C21 LD21 AD1 N/C G26 N/C Y25 TCLK0 A22 LD22 AD11 N/C H1 N/C Y26 TCLK1 C22 LD23 AD12 N/C J24 N/C AF2 TD1 D22 LD24 AD13 N/C J4 N/C AB3 TDO B22 LD25 AD2 N/C K25 N/C AB4 TMS C23 LD26 AD23 N/C K3 N/C AC1 TRST B23 LD27 AD25 N/C K4 N/C AA23 VDD A24 LD28 AD26 N/C M1 N/C AA4 VDD B24 LD29 AE13 N/C M26 N/C AC11 VDD A25 LD30 AE15 N/C M3 N/C AC16 VDD C26 LD31 AE17 N/C N1 N/C AC21 VDD AA26 LDE AE18 N/C N2 N/C AC6 VDD W24 LLOCK AE23 N/C N24 N/C D11 VDD V3 LOCK AE26 N/C N25 N/C D16 VDD AC26 LPAGE0 AE7 N/C N26 N/C D21 VDD AA25 LPAGE1 AF10 N/C R1 N/C D6 VDD AB25 LRDY0 AF24 N/C T24 N/C F23 VDD Y23 LRDY1 AF5 N/C T3 N/C F4 VDD AC24 LRW0 AF6 N/C U1 N/C L23 VDD AB26 LRW1 B10 N/C U25 N/C L4 VDD U26 LSTAT0 B13 N/C V26 N/C T23 VDD T25 LSTAT1 B16 N/C W1 N/C T4 VDD T26 LSTAT2 B18 N/C W26 N/C A1 VSS R26 LSTAT3 B21 N/C Y24 N/C A2 VSS AC25 LSTRB0 B8 N/C AE24 NMI A26 VSS AB24 LSTRB1 C12 N/C AD7 PAGE0 B2 VSS A11 N/C C17 N/C AD4 PAGE1 B25 VSS A13 N/C C19 N/C W3 RDY0 B26 VSS A14 N/C C25 N/C V1 RDY1 C24 VSS A16 N/C C7 N/C AF9 RESET C3 VSS A23 N/C D1 N/C AE9 RESETLOC0 D14 VSS A3 N/C D12 N/C AD8 RESETLOC1 D19 VSS A5 N/C D13 N/C AF21 ROMEN D23 VSS A6 N/C D17 N/C AE8 RW0 D4 VSS A9 N/C D18 N/C AE5 RW1 D9 VSS AC14 N/C D20 N/C AD5 STAT0 H4 VSS AC17 N/C D24 N/C AE6 STAT1 J23 VSS AC19 N/C D3 N/C AD6 STAT2 L11 VSS† AC2 N/C D7 N/C AF7 STAT3 L12 VSS† AC22 N/C F1 N/C AC9 STRB0 L13 VSS† AC3 N/C F24 N/C AC5 STRB1 L14 VSS† L15 VSS† N4 VSS T11 VSS† AD24 VSS Thermal connection POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 GFW Package Pin Assignments Alphabetical Listing by Ball Pin Function (Continued) PIN PIN PIN FUNCTION NO. FUNCTION NO. FUNCTION NO. FUNCTION L16 VSS† P11 VSS† T12 VSS† AE1 VSS M11 VSS† VSS† VSS† VSS† VSS† VSS† VSS† VSS† VSS† VSS† VSS† VSS† P12 T13 P15 VSS† VSS† VSS† VSS† T16 VSS† VSS† VSS† VSS† P16 VSS† V4 VSS P23 VSS W23 R11 VSS† AC4 R12 VSS† VSS† VSS† VSS† VSS† M12 M13 M14 M15 M16 N11 N12 N13 N14 N15 N16 † PIN NO. P13 P14 R13 R14 R15 R16 T14 T15 AE2 VSS AE25 VSS AF1 VSS AF25 VSS AF26 VSS VSS E2 V(SUB) VSS P24 X1 M25 X2CLKIN AC8 VSS AC13 VSS AC18 VSS AC23 VSS AD3 VSS Thermal connection POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 15 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 block diagram Cache (512 bytes) 32 RAM Block 0 (4K bytes) 32 32 RAM Block 1 (4K bytes) 32 32 ROM Block (reserved) 32 32 32 Continued on next page PDATA Bus PADDR Bus DDATA Bus MUX D31 −D0 A23 −A0 DE AE STAT3 −STAT0 LOCK STRB0, STRB1 R / W0, R / W1 PAGE0, PAGE1 RDY0, RDY1 CE0, CE1 DADDR 1 Bus DADDR 2 Bus DMADATA Bus DMAADDR Bus 32 32 32 32 32 IR PC MUX X1 X2 / CLKIN CPU1 ROMEN CPU2 RESET REG 1 REG1 IACK H1 Controller REG2 REG2 IIOF(3 −0) R E G 1 REG1 NMI CPU1 RESETLOC0, RESETLOC1 40 40 Multiplier H3 CVSS 32 IVSS 40 Extended Precision Registers ( R0 −R11) 40 DVDD DVDD 40 40 DISP, IR0, IR1 VDDL VSSL ARAU0 VSUBS BK ARAU1 32 32 32 32 32 Auxiliary Registers (AR0 −AR7) 32 32 16 40 ALU 40 40 DVDD DVSS 40 32-Bit Barrel Shifter POST OFFICE BOX 1443 Other Registers (14) • HOUSTON, TEXAS 77251−1443 32 32 32 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 PDATA Bus PADDR Bus MUX DDATA Bus DADDR 1 Bus DADDR 2 Bus DMADATA Bus LD31 − LD0 LA23 −LA0 LDE LAE LSTAT3 −LSTAT0 LLOCK LSTRB0, LSTRB1 LR / W0, LR / W1 LPAGE0, LPAGE1 LRDY0, LRDY1 LCE0, LCE1 DMAADDR Bus 32 MUX 32 COM Port 1 Input FIFO PAU Output FIFO Port-Control Registers DMA Coprocessor DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 DMA Channel 4 DMA Channel 5 CREQ1 CACK1 CSTRB1 CRDY1 C1D7 −C1D0 CDIR1 COM Port 2 Four Communication Ports† Peripheral Data Bus COM Port 4 Six DMA Channels Peripheral Address Bus Continued from previous page block diagram (continued) COM Port 5 Input FIFO PAU Output FIFO Port-Control Registers CREQ5 CACK5 CSTRB5 CRDY5 C5D7 −C5D0 CDIR5 Timer 0 Global-Control Register Time-Period Register Timer-Counter Register TCLK0 Timer 1 Global-Control Register Time-Period Register Timer-Counter Register TCLK1 Port Control Global Local † Communication ports 0 and 3 are not connected. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 17 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 memory map Structure Depends Upon Romen Bit Figure 1 shows the memory map for the C44. Refer to the TMS320C4x User’s Guide (literature number SPRU063) for a detailed description of this memory mapping. 00000 0000h 1M Accessible Local Bus (External) Peripherals (Internal) 1M 00000 0FFFh 00000 1000h Boot-Loader ROM (Internal) Reserved 0000F FFFFh 00010 0000h Peripherals (Internal) 00010 00FFh 00010 0100h Reserved Reserved 0001F FFFFh 00020 0000h Reserved Reserved 1M 1K RAM BLK 0 (Internal) Structure Identical 1K RAM BLK 1 (Internal) 13 M 0002F F7FFh 0002F F800h 0002F FBFFh 0002F FC00h 0002F FFFFh 00030 0000h 1K RAM BLK 0 (Internal) 1K RAM BLK 1 (Internal) Local Bus (External) Local Bus (External) 000FF FFFFh 0100 0000h 2 G −16 M Local Bus (alias region, see Figure 2) Local Bus (alias region, see Figure 2) 7FFF FFFFh 8000 0000h 16 M Global Bus (External) Global Bus (External) 80FF FFFh 8100 0000 2 G −16 M Global Bus (alias region, see Figure 2) Global Bus (alias region, see Figure 2) FFFF FFFFh (a) INTERNAL ROM DISABLED (ROMEN = 0) (b) INTERNAL ROM ENABLED (ROMEN = 1) Microprocessor Mode Microcomputer Mode Figure 1. Memory Map for TMS320C44 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 memory aliasing The C44 offers global and local addresses of A0−A23 and LA0−LA23, giving an external address reach of (2 buses) × (2 24) = 225 words. Since the internal address span of the C44 is 232 words, reading or writing to memory outside of the base-address region causes memory aliasing. Figure 2 shows how the memory pages overlap each other. Local Bus 0x0000 0000 Global Bus 0x8000 0000 Base-Address Region 0x00FF FFFF 0x0100 0000 Base-Address Region 0x80FF FFFF 0x8100 0000 External Alias 1 External Alias 1 0x01FF FFFF 0x0200 0000 0x81FF FFFF 0x8200 0000 External Alias 2 External Alias 2 0x02FF FFFF 0x82FF FFFF 0x7F00 0000 0xFF00 0000 External Alias n External Alias n 0x7FFFFFFF 0xFFFFFFFF Figure 2. Memory Alias central processing unit The C44 CPU is configured for high-speed internal parallelism for the highest sustained performance. The key features of the CPU are: D Eight operations/cycle: − − − − D D D D 40-/32-bit floating-point/integer multiply 40-/32-bit floating-point/integer ALU operation Two data accesses Two address-register updates Floating-point conversion Divide and square-root support C3x and C4x assembly-language compatibility Byte and halfword accessibility POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 19 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 DMA coprocessor The DMA coprocessor allows concurrent I/O and CPU processing for the highest sustained CPU performance. The key features of the DMA coprocessor are: D D D D Link pointers to allow DMA channels to autoinitialize without CPU intervention Parallel CPU operation and DMA transfers Six DMA channels to support memory-to-memory data transfers Split-mode operation which doubles the available channels to twelve when data transfers to and from a communication port are required communication ports The C44 contains four identical high-speed communication ports, each of which provides a bidirectional-communication interface to other C4x devices and external peripherals. The key features of the communication ports are: D D D D D Direct interprocessor communication and processor I/O 20M-byte/s bidirectional interface on each communication port for high-speed multiprocessor interface Port direction pin (CDIR) to ease interfacing Separate input and output 8-word-deep FIFO buffers for processor-to-processor communication and I/O Automatic arbitration and handshaking for direct processor-to-processor connection communication-port direction pin A port-direction pin (CDIR1, CDIR2, CDIR4, CDIR5) is available for each C44 communication port. When the communication port is in the output mode, CDIRx is driven low. When the communication port is in the input mode, CDIRx is driven high. The truth table for two C44 devices is shown in Table 1. Communication port 1 of CPUA is connected to communication port 4 of CPUB. Table 1. Truth Table for Two C44 Devices CDIR1 CDIR4 0 0 Token error DESCRIPTION 0 1 CPUA is configured to transmit to CPUB. 1 0 CPUB is configured to transmit to CPUA . 1 1 Token exchange overlap, if > 1H then token error communication-port-software reset The input and output FIFO levels for a communication port can be flushed by writing at least two back-to-back values to its communication-port software-reset address as specified in Table 2. This software reset flushes any word or byte already present in the FIFOs, but it does not affect the status of the communication-port pins. Table 2. Communication-Port Software-Reset Address 20 COMMUNICATION PORT SOFTWARE-RESET ADDRESS 1 0x0100053 2 0x0100063 4 0x0100083 5 0x0100093 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 communication-port-software reset (continued) When used in conjunction with the communication-port direction pins and NMI bus-grant, an effective method of error detection and correction can be achieved. A subroutine showing how to reset communication port 1 is given in Figure 3. ; −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−-−−−; ; RESET1:Flushes FIFOs data for communication port 1; ; −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−-−−−; RESET1 push AR0 ; Save registers push R0 ; push RC ; ldhi 010h,AR0 ; Set AR0 to base address of COM 1 or 050h,AR0 ; FLUSH: rpts 1 ; Flush FIFO data with back-to-back write sti R0,*+AR0(3) ; rpts 10 ; Wait nop ; ldi *+AR0(0),R0 ; Check for new data from other port and 01FE0h,R0 ; bnz FLUSH ; pop RC ; Restore registers pop R0 ; pop AR0 ; rets ; Return Figure 3. Example of Communication-Port-Software Reset NMI with bus-grant feature The C44 devices have a software-configurable feature that allows forcing the internal-peripheral bus ready when the NMI signal is asserted. The NMI bus-grant feature is enabled when bits 19 and 18 of the status register (ST) are set to 10b. When enabled, a peripheral bus-grant signal is generated on the falling edge of NMI. If NMI is asserted and this feature is not enabled, the CPU stalls on access to the peripheral bus if it is not ready. A stall condition occurs when writing to a full output FIFO or reading an empty input FIFO. This feature is useful in correcting communication-port errors when used in conjunction with the communication-port software-reset feature. IDLE2 clock-stop power-down mode The C44 has a clock-stop mode, or power-down mode (IDLE2) to achieve extremely low power consumption. When an IDLE2 instruction is executed, the clocks are halted with H1 held high. (Exiting IDLE2 requires asserting one of the IIOF3−IIOF0 pins configured as an external interrupt.) A macro showing how to generate the IDLE2 opcode is given in Figure 4. During this power-down mode: D No instructions are executed. D The CPU, peripherals, and internal memory retain their previous state. D The external-bus outputs are idle. The address lines remain in their previous state; the data lines are in the high-impedance state; and the output-control signals are inactive. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 21 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 IDLE2 clock-stop power-down mode (continued) ; −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−-−-−; ; IDLE2: Macro to generate idle2 opcode ; ; −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−-−−; IDLE2 .macro .word 06000001h .endm Figure 4. Example Software Subroutine Using IDLE2 IDLE2 is exited when one of the five external interrupts (NMI and IIOF3−IIOF0) is asserted low for at least four input clocks (two H1 cycles). The clocks then start after a delay of two input clocks (one H1 cycle). The clocks can start in the opposite phase; that is, H1 can be high when H3 was high before the clocks were stopped. However, the H1 and H3 clocks remain 180 degrees out of phase with each other. During IDLE2 operation, an external interrupt can be recognized and serviced by the CPU if it is enabled before entering IDLE2 and asserted for at least two H1 cycles. For the processor to recognize only one interrupt, the interrupt pin must be configured for edge-trigger mode or asserted less than three cycles in level-trigger mode. Any external interrupt pin can wake up the device from IDLE2, but for the CPU to recognize that interrupt, it must also be enabled. If an interrupt is recognized and executed by the CPU, the instruction following the IDLE2 instruction is not executed until after a return opcode is executed. When the device is in emulation mode, the CPU executes an IDLE2 instruction as if it were an IDLE instruction. The clocks continue to run for correct operation of the emulator. boot-loader mode selection Table 3. Boot-Loader Mode Selection Using Pins IIOF3−IIOF0 EXTERNAL PIN IIOF2 IIOF1 IIOF0 1 1 0 1 Load source program from address 0030 0000h 1 0 1 1 Load source program from address 4000 0000h (see Note 1) 1 0 0 1 Load source program from address 80 0000h 0 1 1 1 Load source program from address 8000 0000h (see Note 2) 0 1 0 1 Load source program from address 8040 0000h (see Note 3) 0 0 1 1 Load source program from address 8080 0000h (see Note 4) 0 0 0 1 Reserved (boot-loader program terminates) 1 1 1 Load source program from communication port 1 NOTES: 1. 2. 3. 4. 22 SOURCE PROGRAM LOCATION IIOF3 This selection cause the C44 to drive 0 in the 24 external local address pins and activates the LSTRB0 signal. This selection cause the C44 to drive 0 in the 24 external global address pins ando activates the STRB0 signal. This selection cause the C44 to drive 0x40 0000 in the 24 external global address pins and activates the STRB0 signal. This selection cause the C44 to drive 0x80 0000 in the 24 external global address pins and to activate the STRB0 signal. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 development tools A key aspect to a parallel-processing implementation is the development tools available. The C44 is supported by a host of parallel-processing tools for developing and simulating code easily and for debugging parallel-processing systems. The code-generation tools include: D An optimizing ANSI C compiler with a runtime-support library that supports use of communication ports and DMA D Third party support for C, C++, and Ada compilers D Several operating systems available for parallel-processing support as well as DMA and communication-port drivers D Assembler and linker with support for mapping program and data to parallel processors The simulation tools include a TI software-simulator with a high-level-language debugger interface for simulating a single processor. The hardware development and verification tools consist of the XDS510 (parallel-processor in-circuit emulator and high-level-language debugger). silicon revision identification DSP TMS320C44PDB EAXXX YYYYY 1991 TI TAIWAN Device Type Revision Number and Package Data Code E XXXXX : Silicon rev 1.X EA XXXXX : Silicon rev 2.X Lot Number (May or may not exist) XDS510 is a trademark of Texas Instruments. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 23 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 silicon revision identification (continued) Table 4. Device Descriptions DEVICE PART NUMBER VOLTAGE OPERATING FREQUENCY COMM PORTS PACKAGE TMS320C40GFL 5V 50 MHz/40 ns 6 325-pin ceramic PGA TMS320C40GFL60 5V 60 MHz/33 ns 6 325-pin ceramic PGA TMS320C44PDB50 5V 50 MHz/40 ns 4 304-pin PQFP TMS320C44PDB60 5V 60 MHz/33 ns 4 304-pin PQFP TMS320C44GFW 5V 50 MHz/40 ns 4 388-pad ball grid array TMS320C44GFW60 5V 60 MHz/33 ns 4 388-pad ball grid array TMS320C44GFWA 5V 50 MHz/40 ns 4 388-pad ball grid array (industrial temp.) SMJ320C40GFM40 5V 40 MHz/50 ns 6 325-pin ceramic PGA SMJ320C40GFM50 5V 50 MHz/40 ns 6 325-pin ceramic PGA SMJ320C40HFHM40 5V 40 MHz/50 ns 6 352-lead ceramic PGA SMJ320C40HFHM50 5V 50 MHz/40 ns 6 352-lead ceramic PGA SMJ320C40TAM40 5V 40 MHz/50 ns 6 324 pad TAB tape (encapsulated) SMJ320C40TBM40 5V 40 MHz/50 ns 6 324 pad TAB tape (bare die) TMS320C40TAL50 5V 50 MHz/40 ns 6 324 pad TAB tape (encapsulated) SMJ320C40TAM50 5V 50 MHz/40 ns 6 324 pad TAB tape (encapsulated) SMJ320C40TBM50 5V 50 MHz/40 ns 6 324 pad TAB tape (bare die) TMS320C40TAL60 5V 60 MHz/33 ns 6 324 pad TAB tape (encapsulated) SMJ320C40KGDM40 5V 40 MHz/50 ns 6 Known good die SMJ320C40KGDM50 5V 50 MHz/40 ns 6 Known good die TMS320C40KGDL50 5V 50 MHz/40 ns 6 Known good die TMS320C40KGDL60 5V 60 MHz/33 ns 6 Known good die 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 absolute maximum ratings over specified temperature range (unless otherwise noted)† Supply voltage range, VDD (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 7 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 7 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 7 V Operating case temperature range, TC: (PDB and GFW commercial temperature parts) . . . . . 0°C to 85°C (GFWA industrial temperature parts)‡ . . . . . . . . . . − 40°C to 115°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ Assuming C44 nominal power consumption (350 mA) and given the C44 thermal characteristics, the maximum T corresponds to 85°C C NOTE 5: All voltage values are with respect to VSS. recommended operating conditions VDD VIH Supply voltage (DDVDD, etc.) High-level High level input voltage NOM§ MAX UNIT 4.75 5 5.25 V X2 / CLKIN 2.6 VDD + 0.3 CSTRB and CRDY pins 2.4 VDD + 0.3 2 VDD + 0.3 All other pins § MIN − 0.3 V VIL Low-level input voltage 0.8 V IOH High-level output current − 300 µA IOL Low-level output current 2 mA TC Operating case temperature PDB and GFW (commercial) GFWA (industrial) 0 85 − 40 115 °C All typical values are at VDD = 5 V, TA (air temperature)= 25°C. electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) TEST CONDITIONS¶ PARAMETER VOH High-level output voltage VDD = MIN, IOH = MAX VOL Low-level output voltage VDD = MIN, IOL = MAX IZ High-impedance current VDD = MAX II Input current VI = VSS to VDD All others ICC Supply current TA = 25 °C, VDD = MAX, fx = MAX (see Note 7) TYP# 2.4 3 0.3 X2 / CLKIN only Inputs with internal pullups (see Note 6) MIN MAX UNIT V 0.6 V −20 20 µA −30 30 −400 20 −10 10 C44-40 C44-50 350 850 C44-60 350 950 µA mA CI Input capacitance 15 pF Co Output capacitance 15 pF ¶ For conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. # All typical values are at V DD = 3.3 V, TA (air temperature) = 25°C. NOTES: 6. Pins with internal pullup devices: TDI, TCK, TMS. Pin with internal pulldown device: TRST. 7. fx is the input clock frequency. The maximum value (max) for the C44-40, C44-50, and C44-60 is 40, 50 and 60 MHz, respectively. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 25 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics VLoad CT Output Under Test IOH Where: IOL IOH VLOAD CT = = = = 2 mA (all outputs) 300 µA (all outputs) 2.15 V 80 pF typical load-circuit capacitance Figure 5. Test Load Circuit signal transition levels TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V. Output transition times are specified as follows: D For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at which the output is said to be high is 2 V. D For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be no longer high is 2 V and the level at which the output is said to be low is 1 V. 2.4 V 2V 1V 0.6 V Figure 6. TTL-Level Outputs Transition times for TTL-compatible inputs are specified as follows: D For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 0.92 V (10%) and the level at which the input is said to be high is 1.88 V (90%). D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 1.88 V (90%) and the level at which the input is said to be low is 0.92 V (10%). 2V 1.88 V (90%) 0.92 V (10%) 0.8 V Figure 7. TTL-Level Inputs 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 PARAMETER MEASUREMENT INFORMATION timing parameter symbology Timing parameter symbols used herein were created in accordance with JEDEC Standard 100. In order to shorten the symbols, pin names that have both global and local applications are generally represented with (L) immediately preceding the basic signal name (for example, (L)RDY represents both the global term RDY and local term LRDY). Other pin names and related terminology have been abbreviated as follows, unless otherwise noted: A (L)A23 −(L)A0 or (L)Ax IACK IACK AE (L)AE IF IIOF(3 −0) or IIOFx ASYNCH Asynchronous reset signals in the high-impedance state IIOF IIOF(3 −0) or IIOFx BYTE Byte transfer LOCK (L)LOCK CA CACK(1,2,4,5) or CACKx P tc(H) CD C(1,2,4,5)D7 −C(1,2,4,5)D0 or CxDx PAGE (L)PAGE0 and (L)PAGE1 or (L)PAGEx CDIR CDIR(1,2,4,5) or CDIRx RDY (L)RDY0, (L)RDY1, or (L)RDYx CE (L)CE0, (L)CE1, or (L)CEx RESET RESET CI CLKIN RW (L)R / W0, (L)R / W1, or (L)R / Wx COMM Asynchronous reset signals S (L)STRB0, (L)STRB1, or (L)STRBx CONTROL Control signals ST (L)STAT3 −(L)STAT0 or (L)STATx CRQ CREQ(1,2,4,5) or CREQx TCK TCK CRDY CRDY(1,2,4,5) or CRDYx TCLK TCLK0, TCLK1, or TCLKx CS CSTRB(1,2,4,5) or CSTRBx TDO TDO D (L)D31 −(L)D0 or (L)Dx TMS TMS / TDI DE (L)DE WORD 32-bit word transfer H H1, H3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 27 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 timing for X2/CLKIN, H1, H3 (see Figure 8 and Figure 9) TMS320C44- 50 NO NO. 1 tf(CI) Fall time, CLKIN 2 tw(CIL) Pulse duration, CLKIN low, tc(CI) = MIN 7 3 tw(CIH) Pulse duration, CLKIN high, tc(CI) = MIN 7 4 tr(CI) Rise time, CLKIN 5 tc(CI) Cycle time, CLKIN 6 tf(H) Fall time, H1 and H3 7 tw(HL) Pulse duration, H1 and H3 low tc(CI) −6 8 tw(HH) Pulse duration, H1 and H3 high tc(CI) −6 9 tr(H) Rise time, H1 and H3 td(HL - HH) Delay time from H1 low to H3 high or from H3 low to H1 high 9.1 10 † MIN tc(H) Cycle time, H1 and MAX MIN 5 5 ns 242.5 ns 3 ns tc(CI) + 6 tc(CI) −6 tc(CI) + 6 ns tc(CI) + 6 tc(CI) −6 tc(CI) + 6 ns −1 4 ns 40 485 33.3 485 ns 1 X2 / CLKIN 3 2 Figure 8. X2/CLKIN Timing 10 6 8 7 9.1 H3 8 9 7 10 Figure 9. H1 and H3 Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ns 4 5 9.1 4 −1 4 H1 ns 16.67 242.5 4 9 ns 5 3 H3† UNIT ns 5 5 20 MAX 5 Maximum cycle time is not limited during IDLE2 operation. 28 TMS320C44- 60 6 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 memory-read-cycle and memory-write-cycle timing [(L)STRBx = 0] (see Note 8, Figure 10, and Figure 11) TMS320C44- 50 NO NO. TMS320C44- 60 MIN MAX MIN MAX UNIT 1 td(H1L - SL) Delay time, H1 low to (L)STRBx low 0 9 0 8 ns 2 td(H1L - SH) Delay time, H1 low to (L)STRBx high 0 9 0 8 ns 3 td(H1H - RWL) Delay time, H1 high to (L)R / Wx low 0 9 0 8 ns 4 td(H1L - A) Delay time, H1 low to (L)Ax valid 0 9 0 8 ns 5 tsu(D-H1L)R Setup time, (L)Dx valid before H1 low (read) 6 th(H1L-D)R Hold time, (L)Dx after H1 low (read) 7 tsu(RDY-H1L) Setup time, (L)RDYx valid before H1 low 8 th(H1L-RDY) Hold time, (L)RDYx after H1 low 8.1 td(H1L - ST) Delay time, H1 low to (L)STAT3 −(L)STAT0 valid 9 td(H1H-RWH)W Delay time, H1 high to (L)R / Wx high (write) 10 tv(H1L-D)W Valid time, (L)Dx after H1 low (write) 11 th(H1H-D)W Hold time, (L)Dx after H1 high (write) 12 td(H1H - A) Delay time, H1 high to address valid on back-to-back write cycles 10 9 ns 0 0 ns 20† 18 ns 0 0 ns 8 0 9 0 16 0 8 ns 8 ns 13 ns 0 9 ns 8 ns † If this setup time is not met, the read/write operation is not assured. NOTE 8: For consecutive reads, (L)R / Wx stays high and (L)STRBx stays low. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 29 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 memory-read-cycle and memory-write-cycle timing [(L)STRBx = 0] (continued) H3 H1 1 2 (L)STRBx (L)R / Wx 5 4 3 (L)Ax 6 (L)Dx 8 7 (L)RDYx 8.1 (L)STATx Figure 10. Memory-Read-Cycle Timing [(L)STRBx = 0] 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 memory-read-cycle and memory-write-cycle timing [(L)STRBx = 0] (continued) H3 H1 1 2 (L)STRBx 3 9 (L)R / Wx 12 4 (L)Ax 10 11 (L)Dx 8 (L)RDYx 7 (L)STATx Figure 11. Memory-Write-Cycle Timing [(L)STRBx = 0] POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 31 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 (L)DE-, (L)AE-, and (L)CEx-enable timing (see Figure 12) TMS320C44- 50 NO NO. TMS320C44- 60 MIN MAX MIN MAX UNIT 1 td(DEH - DZ) Delay time, (L)DE high to (L)D0 −(L)D31 in the high-impedance state 0 15 0 15 ns 2 td(DEL - DV) Delay time, (L)DE low to (L)D0 −(L)D31 valid 0 21 0 16 ns 3 td(AEH - AZ) Delay time, (L)AE high to (L)A0 −(L)A23 in the high-impedance state 0 15 0 15 ns 4 td(AEL - AV) Delay time, (L)AE low to (L)A0 −(L)A23 valid 0 18 0 16 ns 5 td(CEH - RWZ) Delay time, (L)CEx high to (L)R / W0, (L)R / W1 in the high-impedance state 0 15 0 15 ns 6 td(CEL - RWV) Delay time, (L)CEx low to (L)R / W0, (L)R / W1 valid 0 21 0 16 ns 7 td(CEH - SZ) Delay time, (L)CEx high to (L)STRB0, (L)STRB1 in the high-impedance state 0 15 0 15 ns 8 td(CEL - SV) Delay time, (L)CEx low to (L)STRB0, (L)STRB1 valid 0 21 0 16 ns 9 td(CEH - PAGEZ) Delay time, (L)CEx high to (L)PAGE0, (L)PAGE1 in the high-impedance state 0 15 0 15 ns 10 td(CEL - PAGEV) Delay time, (L)CEx low to (L)PAGE0, (L)PAGE1 valid 0 21 0 16 ns (L)DE 2 1 Hi-Z (L)Dx (L)AE 4 3 Hi-Z (L)Ax (L)CEx 6 5 Hi-Z (L)R / Wx 7 8 Hi-Z (L)STRBx 9 10 Hi-Z (L)PAGEx Figure 12. (L)DE-, (L)AE-, and (L)CEx-Enable Timing 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 timing for (L)LOCK when executing LDFI or LDII (see Figure 13) TMS320C44- 50 NO NO. 1 MIN td(H1L - LOCKL) Delay time, H1 low to (L)LOCK low MAX 8 TMS320C44- 60 MIN MAX 8 UNIT ns LDFI or LDII External Access H3 H1 (L)STRBx (L)R / Wx (L)Ax (L)Dx (L)RDYx 1 (L)LOCK Figure 13. Timing for (L)LOCK When Executing LDFI or LDII POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 33 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 timing for (L)LOCK when executing STFI or STII (see Figure 14) TMS320C44- 50 NO NO. 1 MIN td(H1L - LOCKH) Delay time, H1 low to (L)LOCK high MAX 8 STFI or STII External Access H3 H1 (L)STRBx (L)R / Wx (L)Ax (L)Dx (L)RDYx 1 (L)LOCK Figure 14. Timing for (L)LOCK When Executing STFI or STII 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44- 60 MIN MAX 8 UNIT ns TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 timing for (L)LOCK when executing SIGI (see Figure 15) TMS320C44- 50 NO NO. MIN MAX TMS320C44- 60 MIN MAX UNIT 1 td(H1L - LOCKL) Delay time, H1 low to (L)LOCK low 8 8 ns 2 td(H1L - LOCKH) Delay time, H1 low to (L)LOCK high 8 8 ns H3 H1 1 2 (L)LOCK (L)R / Wx (L)Ax (L)Dx (L)RDYx (L)STATx Figure 15. Timing for (L)LOCK When Executing SIGI POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 35 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 timing for (L)PAGE0, (L)PAGE1 during memory access to a different page (see Figure 16) TMS320C44- 50 NO NO. TMS320C44- 60 MIN MAX MIN MAX UNIT 1 td(H1L - PAGEH) Delay time, H1 low to (L)PAGEx high for access to different page 0 9 0 8 ns 2 td(H1L - PAGEL) Delay time, H1 low to (L)PAGEx low for access to different page 0 9 0 8 ns H1 (L)R / Wx (L)STRBx (L)RDYx 1 2 1 2 (L)PAGEx (L)Dx (L)Ax (L)STATx (L)STRB1 write to a different page (L)STRB1 read from a different page Figure 16. (L)PAGE0, (L)PAGE1 Timing Cycle, Memory Access to a Different Page 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 timing for the IIOFx when configured as an output (see Figure 17) TMS320C44- 50 NO NO. 1 MIN tv(H1L - IIOF) H1 low to IIOFx valid Fetch Load Instruction MAX TMS320C44- 60 MIN MAX 14 Decode Read 14 UNIT ns Execute H3 H1 1 or 0 FLAGx (IIF Register) 1 IIOFx Pins Figure 17. Timing for the IIOFx When Configured as an Output POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 37 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 timing of IIOFx changing from output to input mode (see Figure 18) TMS320C44- 50 NO NO. MIN 1 th(H1L - IIOF) Hold time, IIOFx after H1 low 2 tsu(IIOF-H1L) Setup time, IIOFx before H1 low 3 th(H1L-IIOF) Hold time, IIOFx after H1 low TMS320C44- 60 MIN 14 Buffers Go From Output to Input Execute Load of IIF Register MAX 14 ns 0 0 ns Value on IIOF Seen in IIF H1 2 3 1 Output FLAGx (IIF Register) Data Sampled Figure 18. Change of IIOFx From Output to Input Mode 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ns 11 H3 IIOFx UNIT 11 Synchronizer Delay TYPEx (IIF Register) MAX Data Seen TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 timing of IIOFx changing from input to output mode (see Figure 19) TMS320C44- 50 NO NO. 1 MIN td(H1L - IFIO) MAX Delay time, H1 low to IIOFx switching from input to output H3 TMS320C44- 60 MIN MAX 14 14 TMS320C44- 50 TMS320C44- 60 UNIT ns Execution of Load of IIF Register H1 TYPEx (IIF Register) 1 IIOFx Figure 19. Change of IIOFx From Input to Output Mode RESET timing (see Figure 20) NO NO. 1 UNIT MIN MAX MIN MAX 11 tc(CI) 11 tc(CI) ns tsu(RESET-C1L) Setup time for RESET before CLKIN low 2.1 td(CIH - H1H) Delay time, CLKIN high to H1 high 2 10 2 10 ns 2.2 td(CIH - H1L) Delay time, CLKIN high to H1 low 2 10 2 10 ns tsu(RESETH - H1L) Setup time for RESET high before H1 low and after ten H1 clock cycles 4.1 td(CIH - H3L) Delay time, CLKIN high to H3 low 2 10 2 10 ns 4.2 td(CIH - H3H) Delay time, CLKIN high to H3 high 2 10 2 10 ns 5 td(H1H - DZ) Delay time, H1 high to (L)Dx in the high-impedance state 13 13 ns 6 td(H3H - AZ) Delay time, H3 high to (L)Ax in the high-impedance state 9 9 ns 7 td(H3H - CONTROLH) Delay time, H3 high to control signals high [low for (L)PAGE] 9 9 ns 8 td(H1H - IACKH) Delay time, H1 high to IACK high 9 9 ns 9 td(RESETL - ASYNCH) Delay time, RESET low to asynchronous reset signals in the high-impedance state 21 21 ns 10 td(RESETH - COMMH) Delay time, RESET high to asynchronous reset signals high 15 15 ns 11 td(H1H-CDIRL) Delay time, 9 9 ns 12 td(H1H-CDIRH) Delay time, 9 9 ns 3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 13 13 ns 39 1 2.2 2.1 3 H1 5 4.1 H3 Ten H1 Clock Cycles POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Control Signals (L)Dx (see Note C) 4.2 (L)Ax (see Note C) 6 7 Control Signals (see Note D) 7 (L)PAGEx (see Note D) 8 IACK Asynchronous Reset Signals (see Note E) Asynchronous Reset Signals (see Note A) CDIRx (see Note F) CDIRy (see Note F) 9 10 9 11 12 NOTES: A. Asynchronous reset signals that go to a high logic level after RESET returns to a high state include CREQy, CACKx, CSTRBx, and CRDYy (where x = 1 or 2 and y = 4 or 5). B. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown occurs; otherwise, an additional delay of one clock cycle can occur. C. For this diagram, (L)Dx includes D31 − D0, LD31 −LD0, and CxD7 −CxD0; (L)Ax includes LA(23 −0) and A(23 −0). D. Control signals LSTRB0, LSTRB1, STRB0, STRB1, (L)STAT3 −(L)STAT0, (L)LOCK, (L)R/W0, and (L)R/W1 go high while (L)PAGE0 and (L)PAGE1 go low. E. Asynchronous reset signals that go into the high-impedance state after RESET goes low include TCLK0, TCLK1, IIOF3 −IIOF0, and the communication-port control signals CREQx, CACKy, CSTRBy, and CRDYx (where x = 1 or 2, and y = 4 or 5). At reset, ports 1 and 2 become outputs, and ports 4 and 5 become inputs. F. x = 1 or 2 and y = 4 or 5 Figure 20. RESET Timing Template Release Date: 7−11−94 RESET (see Notes A and B) TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED − MARCH 2004 40 CLKIN TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 timing for IIOFx interrupt response [P = tc(H)] (see Notes 9 and 10 and Figure 21) TMS320C44- 50 NO NO. 1 2 MIN TYP MAX 11† tsu(IIOF-H1L ) Setup time, IIOFx before H1 low tw(INT ) Pulse duration, to assure one interrupt seen (see Note 11) P TMS320C44 - 60 MIN TYP MAX 11† 1.5 P 2P P UNIT ns 1.5 P 2P ns † If this timing is not met, the interrupt is recognized in the next cycle. NOTES: 9. IIOFx is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown occurs; otherwise, an additional delay of one clock cycle can occur. 10. Edge-triggered interrupts require a setup of time (1) and a minimum duration of P. No maximum duration limit exists. 11. Level-triggered interrupts require interrupt-pulse duration of at least 1 P wide (P = one H1 period) to ensure it will be seen. It must be ≤ to 2 P wide to ensure it will be responded to only once. Recommended pulse duration is 1.5 P. Reset or Interrupt Vector Read Fetch First Instruction of Service Routine H3 H1 IIOFx 1 (see Note A) First Instruction Address 2 FLAGx (IIF Register) Address Vector Address Data NOTE A: The C44 can accept an interrupt from the same source every two H1 clock cycles. Figure 21. IIOFx Interrupt-Response Timing [P = tc(H)] POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 41 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 timing for IACK (see Note 12 and Figure 22) TMS320C44 - 50 NO NO. 1 2 MIN MAX TMS320C44 - 60 MIN MAX UNIT td(H1L - IACKL) Delay time, H1 low to IACK low 9 7 ns td(H1L - IACKH) Delay time, H1 low to IACK high during first cycle of IACK instruction data read 9 7 ns NOTE 12: The IACK output is active for the entire duration of the bus cycle and is, therefore, extended if the bus cycle utilizes wait states. Fetch IACK Instruction Decode IACK Instruction IACK Data Read Execute IACK Instruction H3 H1 1 IACK Address Data Figure 22. IACK Timing 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 2 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 communication-port word-transfer-cycle timing† [P = tc(H)] (see Note 13 and Figure 23) TMS320C44 - 50 NO NO. 1 2 MIN TMS320C44 - 60 MAX MIN MAX UNIT tc(WORD)‡ Cycle time, word transfer (4 bytes = 1 word) 1.5 P + 7 2.5 P + 170 1.5 P + 7 2.5 P + 170 ns td(CRDYL-CSL)W Delay time, CRDYx low to CSTRBx low between back-to-back write cycles 1.5 P + 7 1.5 P + 7 2.5P + 28 ns 2.5 P + 28 † For these timing values, it is assumed that the C4x receiving data is ready to receive data. Line propagation delay is not considered. tc(WORD) max = 2.5 P + 28 ns + the maximum summed values of 4 × td(CSL-CRDYL)R, 3 × td(CRDYL-CSH), 3 × td(CSH-CRDYH)R, and 3 × td(CRDYH-CSL)W as seen in Figure 24. This timing assumes two C4xs are connected. NOTE 13: These timings apply only to two communicating C4xs. When a non-C4x device communicates with a C44, timings can be longer. No restriction exists in this case on how slow the transfer could be except when using early silicon (C40 PG 1.x or 2.x). Refer to the CSTRB width restriction section of the TMS320C4x User’s Guide (literature number SPRU063). ‡ CREQx CACKx 1 CSTRBx CxDx B0 B1 B2 B3 Undef. B0† 2 CRDYx = When signal is an input (clear = when signal is an output). † Begins byte 0 of the next word. NOTE A: For correct operation during token exchange, the two communicating C4xs must have CLKIN frequencies within a factor of 2 of each other (in other words, at most, one of the C4xs can be twice as fast as the other). Figure 23. Communication-Port Word-Transfer-Cycle Timing [P = tc(H)] POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 43 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 communication-port byte-cycle timing (write and read) (see Note 14 and Figure 24) TMS320C44 - 50 NO NO. MIN TMS320C44 - 60 MAX MIN MAX 2 UNIT 1 tsu(CD-CSL)W Setup time, CxDx valid before CSTRBx low (write) 2 2 td(CRDYL - CSH)W Delay time, CRDYx low to CSTRBx high (write) 0 3 th(CRDYL - CD)W Hold time, CxDx after CRDYx low (write) 2 4 td(CRDYH - CSL)W Delay time, CRDYx high to CSTRBx low for subsequent bytes (write) 0 5 tc(BYTE)† Cycle time, byte transfer 6 td(CSL - CRDYL)R Delay time, CSTRBx low to CRDYx low (read) 0 7 tsu(CSL - CD)R Setup time, CxDx valid after CSTRBx low (read) 0 0 ns 8 th(CRDYL - CD)R Hold time, CxDx valid after CRDYx low (read) 2 2 ns 9 td(CSH - CRDYH)R Delay time, CSTRBx high to CRDYx high (read) 0 12 0 ns 12 2 12 0 44 10 0 10 0 † ns ns 12 ns 44 ns 10 ns 10 ns tc(BYTE) max = summed maximum values of td(CRDY-CSH), td(CSL-CRDYL)R, td(CSH-CRDYH)R, and td(CRDYH-CSL)W. This assumes two C4xs are connected. NOTE 14: Communication port timing does not include line length delay. CREQx CACKx 5 7 5 CSTRBx 1 2 9 CxDx Valid Data 3 8 6 CRDYx 4 (a) WRITE TIMING (b) READ TIMING = When signal is an input (clear = when signal is an output). Figure 24. Communication-Port Byte-Cycle Timing (Write and Read) 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 timing for communication-token transfer sequence, input to an output port [P = tc(H)] (see Figure 25) NO. † MIN MAX UNIT 1 td(CAL - CS)T† Delay time, CACKx low to CSTRBx change from input to a high-level output 0.5 P+ 6 1.5 P + 22 ns 2 td(CAL - CRQH)T† Delay time, CACKx low to start of CREQx going high for token-request acknowledge P+5 2 P + 22 ns 3 td(CRQH - CRQ)T Delay time, start of CREQx going high to CREQx change from output to an input 0.5 P − 5 0.5 P + 13 ns 4 td(CRQH - CA)T Delay time, start of CREQx going high to CACKx change from an input- to an output-level high 0.5 P − 5 0.5 P + 13 ns 4.1 td(CRQH - CD)T Delay time, start of CREQx going high to CxDx change from input-driven to output-driven 0.5 P − 5 0.5 P + 13 ns 4.2 td(CRQH - CRDY)T Delay time, start of CREQx going high to CRDYx change from an output to an input 0.5 P − 5 0.5 P + 13 ns 5 td(CRQH - CSL)T Delay time, start of CREQx going high to CSTRBx low for start of word-transfer out 1.5 P − 8 1.5 P + 9 ns 6 td(CRDYL - CSL)T Delay time, CRDYx low at end of word-input to CSTRBx low for word-output 3.5 P + 12 5.5 P + 48 ns 7 td(CRQH - CDIRL) Delay time, CREQx high to CDIRx low, change from input to output 0.5 P − 5 0.5 P + 13 ns These timing parameters result from synchronizer delays and are referenced from the falling edge of H1. The inputs (that cause the output-signal pins to change values) are sampled on H1 falling. The minimum delay occurs when the input condition occurs just before H1 falling, and the maximum delay occurs when the input condition occurs just after H1 falling. CDIRx 7 3 CREQx 2 4 CACKx 5 1 CSTRBx 4.1 Valid Data Out CxDx 6 CRDYx 4.2 = When signal is an input (clear = when signal is an output). NOTE A: Before the token exchange, CREQx and CRDYx are output signals asserted by the C44 receiving data. CACKx, CSTRBx, and CxD7 −CxD0 are input signals asserted by the device sending data to the C44; these are asynchronous with respect to the H1 clock of the receiving C44. After token exchange, CACKx, CSTRBx, and CxD7 −CxD0 become output signals, and CREQx and CRDYx become inputs. Figure 25. Communication-Token Transfer Sequence, Input to an Output Port [P = tc(H)] POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 45 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 timing for communication-token transfer sequence, output to an input port [P = tc(H)] (see Figure 26) NO. † MIN MAX UNIT P+5 2 P + 22 ns 1 td(CRQL - CAL)T† Delay time, CREQx low to start of CACKx going low for token-request-acknowledge 2 td(CRDYL - CAL)T† Delay time, CRDYx low at end of word-transfer out to start of CACKx going low P+6 2 P + 27 ns 3 td(CAL - CD)I Delay time, start of CACKx going low to CxDx change from outputs to inputs 0.5 P −8 0.5 P + 8 ns 4 td(CAL - CRDY)T Delay time, start of CACKx going low to CRDYx change from an input to output, high level 0.5 P −8 0.5 P + 8 ns 5 td(CRQH - CRQ)T† Delay time, CREQx high to CREQx change from an input to output, high level 4 22 ns 6 td(CRQH - CA)T† Delay time, CREQx high to CACKx change from output to an input 4 22 ns 7 td(CRQH - CS)T† Delay time, CREQx high to CSTRBx change from output to an input 4 22 ns 8 td(CRQH - CRQL)T† Delay time, CREQx high to CREQx low for the next token-request P −4 2 P+8 ns 9 td(CAL - CDIRH) Delay time, CACKx low to CDIRx high, change from output to input 0.5 P −8 0.5 P + 10 ns These timing parameters result from synchronizer delays and are referenced from the falling edge of H1. The inputs (that cause the output-signal pins to change values) are sampled on H1 falling. The minimum delay occurs when the input condition occurs just before H1 falling, and the maximum delay occurs when the input condition occurs just after H1 falling. CDIRx 9 8 CREQx 1 5 CACKx 6 CSTRBx 3 7 CxDx Valid Data Valid Data 4 CRDYx 2 = When signal is an input (clear = when signal is an output). NOTE A: Before the token exchange, CACKx, CSTRBx, and CxD7 −CxD0 are asserted by the C44 sending data. CREQx and CRDYx are input signals asserted by the C44 receiving data and are asynchronous with respect to the H1 clock of the sending C44. After token exchange, CREQx and CRDYx become outputs, and CSTRBx, CACKx, and CxD7 −CxD0 become inputs. Figure 26. Communication-Token Transfer Sequence, Output to an Input Port [P = tc(H)] 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 timer-pin timing (see Note 15 and Figure 27) NO. MIN 1 tsu(TCLK-H1L) Setup time, TCLKx before H1 low 2 th(H1L-TCLK) Hold time, TCLKx after H1 low 3 td(H1H-TCLK) Delay time, TCLKx valid after H1 high MAX 10 UNIT ns 0 ns 13 ns NOTE 15: Period and polarity are specified by contents of internal control registers. H3 H1 2 3 1 3 TCLKx Figure 27. Timer-Pin Timing Cycle timing for IEEE-1149.1 test access port (see Figure 28) TMS320C44 - 50 NO NO. MIN MAX TMS320C44 - 60 MIN MAX UNIT 1 tsu(TMS - TCKH) Setup time, TMS / TDI to TCK high 10 10 ns 2 th(TCKH-TMS) Hold time, TMS / TDI from TCK high 5 5 ns 3 td(TCKL - TDOV) Delay time, TCK low to TDO valid 0 15 0 12 ns TCK 1 TMS/TDI 3 2 TDO Figure 28. IEEE-1149.1 Test Access Port Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 47 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 MECHANICAL DATA PDB (S-PQFP-G304) PLASTIC QUAD FLATPACK (DIE DOWN) 228 153 229 152 Heat Slug 0,27 0,17 0,08 M 0,50 0,13 NOM 304 77 1 76 37,50 TYP 40,20 SQ 39,80 42,80 SQ 42,40 4,00 3,60 Gage Plane 0,25 0,25 MIN 0,75 0,50 0°−
7° Seating Plane 0,08 4,50 MAX 4040148 -2/ C 10/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Thermally enhanced molded plastic package with a heat slug (HSL) Falls within JEDEC MO-143 Parameter RΘJC RΘJA RΘJA RΘJA RΘJA 48 Thermal Resistance Characteristics °C / W 0.8 16 14.2 12.1 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Air Flow LFPM N /A 0 150 250 500 TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 MECHANICAL DATA GFW (S-PBGA-N388) PLASTIC BALL GRID ARRAY 35,20 SQ 34,80 30,70 SQ 30,00 31,75 TYP 1,27 0,635 A1 Corner 0,635 1,27 AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 Bottom View 2,50 2,10 0,58 0,48 Seating Plane 0,90 0,60 ∅ 0,10 M 0,70 0,50 0,15 4073201/C 02/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-151 Parameter RΘJC RΘJA RΘJA RΘJA RΘJA Thermal Resistance Characteristics °C / W 3.7 18.5 16.1 15 13.4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Air Flow LFPM N /A 0 150 250 500 49 PACKAGE OPTION ADDENDUM www.ti.com 30-Nov-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TMS320C44GFW50 NRND BGA GFW 388 TBD Call TI Call TI TMS320C44GFW @1990 TI 50 TMS320C44GFW60 NRND BGA GFW 388 TBD Call TI Call TI TMS320C44GFW @1990 TI 60 TMS320C44GFWA NRND BGA GFW 388 TBD Call TI Level-4-220C-72 HR TMS320C44GFW @1990 TI A TMS320C44PDB50 NRND HQFP PDB 304 TBD Call TI Call TI TMS320C44PDB50 @1990 TI 50 TMS320C44PDB60 NRND HQFP PDB 304 TBD Call TI Call TI TMS320C44PDB60 @1990 TI 60 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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