TMS320C5533AZHHA10

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 TMS320C5535, 'C5534, 'C5533, 'C5532 Fixed-Point Digital Signal Processors 1 Device Overview 1.1 Features 1 • CORE: – High-Performance, Low-Power, TMS320C55x Fixed-Point Digital Signal Processor • 20-, 10-ns Instruction Cycle Time • 50-, 100-MHz Clock Rate • One or Two Instructions Executed per Cycle • Dual Multiply-and-Accumulate Units (Up to 200 Million Multiply-Accumulates per Second [MMACS]) • Two Arithmetic and Logic Units (ALUs) • Three Internal Data and Operand Read Buses and Two Internal Data and Operand Write Buses • Software-Compatible with C55x Devices • Industrial Temperature Devices Available – 320KB of Zero-Wait State On-Chip RAM, Composed of: • 64KB of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit • 256KB of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit – 128KB of Zero Wait-State On-Chip ROM (4 Blocks of 16K x 16-Bit) – Tightly Coupled FFT Hardware Accelerator • PERIPHERAL: – Direct Memory Access (DMA) Controller • Four DMA with 4 Channels Each (16 Channels Total) – Three 32-Bit General-Purpose (GP) Timers • One Selectable as a Watchdog or GP – Two Embedded Multimedia Card (eMMC) or Secure Digital (SD) Interfaces – Universal Asynchronous Receiver/Transmitter (UART) – Serial Port Interface (SPI) with Four Chip Selects – Master and Slave Inter-Integrated Circuit (I2C Bus) • • • • – Four Inter-IC Sound (I2S Bus) for Data Transport – Device USB Port with Integrated 2.0 HighSpeed PHY that Supports: • USB 2.0 Full- and High-Speed Device – LCD Bridge with Asynchronous Interface – 10-Bit 4-Input Successive Approximation (SAR) ADC – IEEE-1149.1 (JTAG) Boundary-Scan-Compatible – 32 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions) • Configure Up to 20 GPIO Pins at the Same Time POWER: – Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB – Three I/O Isolated Power Supply Domains: RTC I/O, USB PHY, and DVDDIO – Three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power the isolated domains: DSP Core, Analog, and USB Core, respectively – 1.05-V Core (50 MHz), 1.8-, 2.5-, 2.75-, or 3.3-V I/Os – 1.3-V Core (100 MHz), 1.8-, 2.5-, 2.75-, or 3.3-V I/Os CLOCK: – Real-Time Clock (RTC) with Crystal Input, Separate Clock Domain, and Separate Power Supply – Low-Power Software Programmable PhaseLocked Loop (PLL) Clock Generator BOOTLOADER: – On-Chip ROM Bootloader (RBL) to Boot From SPI EEPROM, SPI Serial Flash or I2C EEPROM eMMC, SD, SDHC, UART, and USB PACKAGE: – 144-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZHH Suffix) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 1.2 • • • Applications Wireless Audio Devices (for example, Headsets, Microphones, Speakerphones) Echo Cancellation Headphones Portable Medical Devices 1.3 www.ti.com • • • • Voice Applications Industrial Controls Fingerprint Biometrics Software-defined Radio Description These devices are members of TI's C5000™ fixed-point Digital Signal Processor (DSP) product family and are designed for low-power applications. The fixed-point DSP is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The PU decodes the instructions, directs tasks to the AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The general-purpose input and output functions, along with the 10-bit SAR ADC on the TMS320C5535, provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two secure digital (SD) peripherals, four Inter-IC Sound (I2S Bus) modules, one serial port interface (SPI) with up to four chip selects, one I2C multimaster and slave interface, and a universal asynchronous receiver/transmitter (UART) interface. Additional peripherals include: a high-speed Universal Serial Bus (USB 2.0) device mode only (not available on TMS320C5532), a real-time clock (RTC), three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator. In addition, the TMS320C5535 includes a tightly coupled FFT Hardware Accelerator. The tightly coupled FFT Hardware Accelerator supports 8- to 1024-point (in power of 2) real and complex-valued FFTs. Furthermore, the device includes the following three integrated LDOs to power different sections of the device. ANA_LDO (all devices) provides 1.3 V to the DSP PLL (VDDA_PLL), SAR, and power-management circuits (VDDA_ANA). 2 Device Overview Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 DSP_LDO (TMS320C5535 and 'C5534) provides 1.3 V or 1.05 V to the DSP core (CVDD), selectable onthe-fly by software as long as operating frequency ranges are observed. For lowest power operation, the programmer can shut down the internal DSP_LDO, cutting power to the DSP core (CVDD) while an external supply provides power to the RTC (CVDDRTC and DVDDRTC). The RTC alarm interrupt or the WAKEUP pin can re-enable the internal DSP_LDO and re-apply power to the DSP core. When DSP_LDO comes out of reset, it is enabled to 1.3 V for the bootloader to operate. For the 50-MHz devices, DSP_LDO must be programmed to 1.05 V to match the core voltage, CVDD, for proper operation after reset. USB_LDO (TMS320C5535, 'C5534, and 'C5533) provides 1.3 V to the USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3). These devices are supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The devices are also supported by the C55x DSP library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries. Table 1-1. Device Information PACKAGE BODY SIZE TMS320C5535AZHH10 PART NUMBER BGA MICROSTAR (144) 12.0 mm x 12.0 mm TMS320C5535AZHHA10 BGA MICROSTAR (144) 12.0 mm x 12.0 mm TMS320C5534AZHH10 BGA MICROSTAR (144) 12.0 mm x 12.0 mm TMS320C5534AZHHA10 BGA MICROSTAR (144) 12.0 mm x 12.0 mm Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Device Overview 3 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 1.4 www.ti.com Functional Block Diagram Figure 1-1 shows the functional block diagram of the devices. DSP System JTAG Interface C55x DSP CPU PLL/Clock Generator Power Management Input Clocks 64KB DARAM Pin Multiplexing 128KB ROM TMS320C5532 No SARAM TMS320C5533 64KB SARAM TMS320C5534 192KB SARAM 256KB SARAM TMS320C5535 FFT Hardware Accelerator Switched Central Resource (SCR) Peripherals TMS320C5534 TMS320C5535 TMS320C5533 Interconnect Program/Data Storage DMA (x4) eMMC/SD SDHC (x2) Connectivity I2C SPI UART Display 10-Bit SAR ADC LCD Bridge USB 2.0 PHY (HS) [DEVICE] Not Applicable TMS320C5532 System Serial Interfaces I2S (x4) Application Specific RTC GP Timer (x2) GP Timer or WD ANA_LDO TMS320C5532 USB_LDO TMS320C5533 DSP_LDO TMS320C5535/C5534 Figure 1-1. Functional Block Diagram 4 Device Overview Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 Table of Contents Device Overview ......................................... 1 5.5 Thermal Characteristics ............................. 54 1.1 Features .............................................. 1 5.6 Power-On Hours 1.2 Applications ........................................... 2 5.7 Timing and Switching Characteristics ............... 55 1.3 Description ............................................ 2 1.4 Functional Block Diagram ............................ 4 6.1 CPU ................................................ 118 2 3 Revision History ......................................... 6 Device Comparison ..................................... 7 6.2 Memory 6.3 Identification........................................ 144 6.4 Boot Modes ........................................ 145 4 Terminal Configuration and Functions ............ 13 1 3.1 5 6 Device Characteristics ................................ 7 7 54 Detailed Description.................................. 118 ............................................ 118 Device and Documentation Support .............. 149 4.1 Pin Diagram ......................................... 13 7.1 4.2 Signal Descriptions .................................. 17 7.2 4.3 Pin Multiplexing...................................... 46 7.3 Specifications ........................................... 49 7.4 5.1 Absolute Maximum Ratings ......................... 49 7.5 5.2 Recommended Operating Conditions ............... 50 7.6 5.3 Electrical Characteristics ............................ 51 7.7 5.4 Handling Ratings .................................... 54 8 .................................... .................................... Documentation Support ............................ Related Links ...................................... Community Resources............................. Trademarks ........................................ Electrostatic Discharge Caution ................... Glossary............................................ Device Support 149 150 151 151 151 151 151 Mechanical Packaging and Orderable Information ............................................. 152 Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Table of Contents 5 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (February, 2012) to Revision C • • • • • • • • • • • • • • • • • 6 Page Added power-on information for USB_VBUS, USB_VDDA3P3, USB_VDDA1P3, and USB_VDD1P3 (LitBug SDOCM00101620) .................................................................................................................. 28 Changed description for RSV6 to tie directly to Vss (LitBug SDOCM00101619) ........................................... 41 Changed values for ESD Stress Voltage. HBM changed to > 1000 V ....................................................... 54 Added note that CVDDRTC must always be powered by an external power source and cannot be powered by onchip LDOs (Bugzilla 2151) ......................................................................................................... 56 Changed WU_DOUT reset value to 1 (LitBug SDOCM00096670) ........................................................... 58 Added steps to Power-Supply Sequencing when USB subsystem is used (LitBug SDOCM00101620) ................ 64 Deleted unsupported EMIF pins (LitBug SDOCM00095615).................................................................. 68 Changed PLLOUT minimum to 60, maximum to 120 (LitBug SDOCM00097379) ......................................... 76 Changed SYSCLK maximum to 50 (Bugzilla 2145) ............................................................................ 76 Changed PLL_LOCKTIME to 4 ms maximum from 4 ms minimum (LitBug SDOCM00097381) ......................... 76 Changed minimum value for timing requirement for Wake-Up From IDLE (LitBug SDOCM00096476) ................. 82 Changed description of switching characteristic parameter for Wake-Up From IDLE (LitBug SDOCM00096480) .... 82 Changed timing diagram for Wake-Up From IDLE (LitBug SDOCM00096480) ............................................ 83 Added hardware requirement for RTC-Only Mode to verify the USB oscillator is disabled (LitBug SDOCM00097368) ................................................................................................................ 104 Changed addresses for SD0 and SD1 in Peripheral I/O-Space Control Registers (LitBug SDOCM00101622) ...... 121 Added step to copy boot image sections to system memory (TIS Doc Feedback ID 5979) ............................. 146 Changed Bootloader Software Architecture (TIS Doc Feedback ID 5979) ................................................ 147 Revision History Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 3 Device Comparison Table 3-1 lists the important differences between the devices. Table 3-1. Differences Between Devices Device Digital Core Supply Voltage (CVDD) 1.05 V On-chip DARAM On-chip SARAM USB LCD Interface TightlyCoupled FFT SAR ADC 64KB 256KB √ (1) √ √ √ ANA, DSP, and USB 64KB 192KB √ - (2) - - ANA, DSP, and USB 64KB 64KB √ - - - ANA and USB 64KB 0KB - - - - ANA only 1.3 V LDO Maximum CPU Speed TMS320C5535A05 50 MHz - TMS320C5535A10 50 MHz 100 MHz TMS320C5534A05 50 MHz - TMS320C5534A10 50 MHz 100 MHz TMS320C5533A05 50 MHz - TMS320C5533A10 50 MHz 100 MHz TMS320C5532A05 50 MHz - TMS320C5532A10 50 MHz 100 MHz (1) (2) 3.1 √ — Supported - — Not supported Device Characteristics The following tables provide an overview of all the devices. The tables show significant features of each device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. For more detailed information on the actual device part number and maximum device operating frequency, see Section 7.1.2, Device Nomenclature. Table 3-2. Characteristics of the C5535 Processor HARDWARE FEATURES TMS320C5535A05, C5535A10 Peripherals Not all peripheral pins are available at the same time DMA (for more detail, see Section 5). Four DMA controllers each with four channels, for a total of 16 channels Timers 2 32-Bit General-Purpose (GP) Timers 1 Additional Timer Configurable as a 32-Bit GP Timer or a Watchdog UART 1 (with RTS and CTS flow control) SPI 1 with 4 chip selects 2 I C 1 (Master or Slave) I2S 4 (Two Channel, Full Duplex Communication) USB 2.0 (Device only) SD LCD Bridge ADC (Successive Approximation [SAR]) Real-Time Clock (RTC) FFT Hardware Accelerator General-Purpose Input/Output Port (GPIO) High- and Full-Speed Device 2 SD, 256-byte read and write buffer, max 50-MHz clock and signaling for DMA transfers 1 (8-bit or 16-bit asynchronous parallel bus) 1 (10-bit, 4 -input, 16-μs conversion time) 1 (Crystal Input, Separate Clock Domain and Power Supply) 1 (Supports 8 to 1024-point 16-bit real and complex FFT) 32 pins (with 1 Additional General-Purpose Output (XF) and 4 Special-Purpose Outputs for Use With SAR Configure up to 20 pins simultaneously Device Comparison Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 7 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com Table 3-2. Characteristics of the C5535 Processor (continued) HARDWARE FEATURES TMS320C5535A05, C5535A10 Size (Bytes) On-Chip Memory 320 KB RAM, 128KB ROM • • • Organization JTAG BSDL_ID JTAGID Register (Value is: 0x1B8F E02F) CPU Frequency MHz Cycle Time ns Voltage Core (V) 64KB On-Chip Dual-Access RAM (DARAM) 256KB On-Chip Single-Access RAM (SARAM) 128 KB On-Chip Single-Access ROM (SAROM) see Figure 6-5 1.05-V Core 50 MHz 1.3-V Core 100 MHz (TMS320C5535A10 only) 1.05-V Core 20 ns 1.3-V Core 10 ns (TMS320C5535A10 only) 1.05 V – 50 MHz 1.3 V – 100 MHz (TMS320C5535A10 only) I/O (V) LDOs Power Characterization 1.3 V or 1.05 V, 250 mA max current for DSP CPU (CVDD) ANA_LDO 1.3 V, 4 mA max current to supply power to PLL (VDDA_PLL), SAR, and power management circuits (VDDA_ANA) USB_LDO 1.3 V, 25 mA max current to supply power to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3) Active @ Room Temp 25°C, 75% DMAC + 25% ADD 0.15 mW/MHz @ 1.05 V, 50 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz Active @ Room Temp 25°C, 75% DMAC + 25% NOP 0.14 mW/MHz @ 1.05 V, 50 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM and SARAM in Active Mode) 0.26 mW @ 1.05 V 0.44 mW @ 1.3 V Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Retention and SARAM in Active Mode) 0.23 mW @ 1.05 V 0.40 mW @ 1.3 V Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Active Mode and SARAM in Retention) 0.15 mW @ 1.05 V 0.28 mW @ 1.3 V PLL Options Software Programmable Multiplier BGA Package 12 x 12 mm Product Status (1) Product Preview (PP), Advance Information (AI), or Production Data (PD) (1) 8 1.8 V, 2.5 V, 2.75 V, 3.3 V DSP_LDO x4 to x4099 multiplier 144-Pin BGA (ZHH) PD PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Device Comparison Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 Table 3-3. Characteristics of the C5534 Processor HARDWARE FEATURES TMS320C5534A05, C5534A10 Peripherals Not all peripheral pins are available at the same time DMA (for more detail, see Section 5). Four DMA controllers each with four channels, for a total of 16 channels Timers 2 32-Bit General-Purpose (GP) Timers 1 Additional Timer Configurable as a 32-Bit GP Timer or a Watchdog UART 1 (with RTS and CTS flow control) SPI 1 with 4 chip selects I2C 1 (Master or Slave) I2S 4 (Two Channel, Full Duplex Communication) USB 2.0 (Device only) High- and Full-Speed Device SD 2 SD, 256-byte read and write buffer, max 50-MHz clock and signaling for DMA transfers Real-Time Clock (RTC) 1 (Crystal Input, Separate Clock Domain and Power Supply) General-Purpose Input/Output Port (GPIO) Up to 20 pins (with 1 Additional General-Purpose Output (XF)) Size (Bytes) On-Chip Memory • • • Organization JTAG BSDL_ID JTAGID Register (Value is: 0x1B8F E02F) CPU Frequency MHz Cycle Time ns Voltage 256KB RAM, 128KB ROM see Figure 6-5 1.05-V Core 50 MHz 1.3-V Core 100 MHz (TMS320C5534A10 only) 1.05-V Core 20 ns 1.3-V Core 10 ns (TMS320C5534A10 only) Core (V) I/O (V) LDOs Power Characterization 64KB On-Chip Dual-Access RAM (DARAM) 192KB On-Chip Single-Access RAM (SARAM) 128KB On-Chip Single-Access ROM (SAROM) 1.05 V – 50 MHz 1.3 V – 100 MHz (TMS320C5534A10 only) 1.8 V, 2.5 V, 2.75 V, 3.3 V DSP_LDO 1.3 V or 1.05 V, 250 mA max current for DSP CPU (CVDD) ANA_LDO 1.3 V, 4 mA max current to supply power to PLL (VDDA_PLL) and power management circuits (VDDA_ANA) USB_LDO 1.3 V, 25 mA max current to supply power to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3) Active @ Room Temp 25°C, 75% DMAC + 25% ADD 0.15 mW/MHz @ 1.05 V, 50 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz Active @ Room Temp 25°C, 75% DMAC + 25% NOP 0.14 mW/MHz @ 1.05 V, 50 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM and SARAM in Active Mode) 0.26 mW @ 1.05 V 0.44 mW @ 1.3 V Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Retention and SARAM in Active Mode) 0.23 mW @ 1.05 V 0.40 mW @ 1.3 V Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Active Mode and SARAM in Retention) 0.15 mW @ 1.05 V 0.28 mW @ 1.3 V PLL Options Software Programmable Multiplier BGA Package 12 x 12 mm x4 to x4099 multiplier 144-Pin BGA (ZHH) Device Comparison Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 9 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com Table 3-3. Characteristics of the C5534 Processor (continued) HARDWARE FEATURES Product Preview (PP), Advance Information (AI), or Production Data (PD) Product Status (1) (1) 10 TMS320C5534A05, C5534A10 PD PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Device Comparison Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 Table 3-4. Characteristics of the C5533 Processor HARDWARE FEATURES TMS320C5533A05, C5533A10 Peripherals Not all peripheral pins are available at the same time DMA (for more detail, see Section 5). Four DMA controllers each with four channels, for a total of 16 channels Timers 2 32-Bit General-Purpose (GP) Timers 1 Additional Timer Configurable as a 32-Bit GP Timer or a Watchdog UART 1 (with RTS and CTS flow control) SPI 1 with 4 chip selects I2C 1 (Master or Slave) I2S 4 (Two Channel, Full Duplex Communication) USB 2.0 (Device only) High- and Full-Speed Device SD 2 SD, 256-byte read and write buffer, max 50-MHz clock and signaling for DMA transfers Real-Time Clock (RTC) 1 (Crystal Input, Separate Clock Domain and Power Supply) General-Purpose Input/Output Port (GPIO) Up to 20 pins (with 1 Additional General-Purpose Output (XF)) Size (Bytes) On-Chip Memory • • • Organization JTAG BSDL_ID JTAGID Register (Value is: 0x1B8F E02F) CPU Frequency MHz Cycle Time ns Voltage 128 KB RAM, 128KB ROM see Figure 6-5 1.05-V Core 50 MHz 1.3-V Core 100 MHz (TMS320C5533A10 only) 1.05-V Core 20 ns 1.3-V Core 10 ns (TMS320C5533A10 only) Core (V) I/O (V) LDOs Power Characterization 1.05 V – 50 MHz 1.3 V – 100 MHz (TMS320C5533A10 only) 1.8 V, 2.5 V, 2.75 V, 3.3 V ANA_LDO 1.3 V, 4 mA max current to supply power to PLL (VDDA_PLL) and power management circuits (VDDA_ANA) USB_LDO 1.3 V, 25 mA max current to supply power to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3) Active @ Room Temp 25°C, 75% DMAC + 25% ADD 0.15 mW/MHz @ 1.05 V, 50 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz Active @ Room Temp 25°C, 75% DMAC + 25% NOP 0.14 mW/MHz @ 1.05 V, 50 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM and SARAM in Active Mode) 0.26 mW @ 1.05 V 0.44 mW @ 1.3 V Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Retention and SARAM in Active Mode) 0.23 mW @ 1.05 V 0.40 mW @ 1.3 V Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Active Mode and SARAM in Retention) 0.15 mW @ 1.05 V 0.28 mW @ 1.3 V PLL Options Software Programmable Multiplier BGA Package 12 x 12 mm Product Status (1) Product Preview (PP), Advance Information (AI), or Production Data (PD) (1) 64 KB On-Chip Dual-Access RAM (DARAM) 64 KB On-Chip Single-Access RAM (SARAM) 128 KB On-Chip Single-Access ROM (SAROM) x4 to x4099 multiplier 144-Pin BGA (ZHH) PD PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Device Comparison Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 11 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com Table 3-5. Characteristics of the C5532 Processor HARDWARE FEATURES TMS320C5532A05, C5532A10 Peripherals Not all peripheral pins are available at the same time DMA (for more detail, see Section 5). Four DMA controllers each with four channels, for a total of 16 channels Timers 2 32-Bit General-Purpose (GP) Timers 1 Additional Timer Configurable as a 32-Bit GP Timer or a Watchdog UART 1 (with RTS and CTS flow control) SPI 1 with 4 chip selects I2C 1 (Master or Slave) I2S 4 (Two Channel, Full Duplex Communication) SD 2 SD, 256-byte read and write buffer, max 50-MHz clock and signaling for DMA transfers Real-Time Clock (RTC) 1 (Crystal Input, Separate Clock Domain and Power Supply) General-Purpose Input/Output Port (GPIO) Up to 20 pins (with 1 Additional General-Purpose Output (XF)) Size (Bytes) On-Chip Memory 64KB RAM, 128KB ROM • • Organization JTAG BSDL_ID JTAGID Register (Value is: 0x1B8F E02F) CPU Frequency MHz Cycle Time ns see Figure 6-5 1.05-V Core 50 MHz 1.3-V Core 100 MHz (TMS320C5532A10 only) 1.05-V Core 20 ns 1.3-V Core 10 ns (TMS320C5532A10 only) Core (V) Voltage 64KB On-Chip Dual-Access RAM (DARAM) 128KB On-Chip Single-Access ROM (SAROM) I/O (V) 1.05 V – 50 MHz 1.3 V – 100 MHz (TMS320C5532A10 only) 1.8 V, 2.5 V, 2.75 V, 3.3 V 1.3 V, 4 mA max current for PLL (VDDA_PLL) power management circuits (VDDA_ANA) LDO ANA_LDO Power Characterization Active @ Room Temp 25°C, 75% DMAC + 25% ADD 0.15 mW/MHz @ 1.05 V, 50 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz Active @ Room Temp 25°C, 75% DMAC + 25% NOP 0.14 mW/MHz @ 1.05 V, 50 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM and SARAM in Active Mode) 0.26 mW @ 1.05 V 0.44 mW @ 1.3 V Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Retention and SARAM in Active Mode) 0.23 mW @ 1.05 V 0.40 mW @ 1.3 V Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Active Mode and SARAM in Retention) 0.15 mW @ 1.05 V 0.28 mW @ 1.3 V PLL Options Software Programmable Multiplier BGA Package 12 x 12 mm Product Status (1) Product Preview (PP), Advance Information (AI), or Production Data (PD) (1) 12 x4 to x4099 multiplier 144-Pin BGA (ZHH) PD PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Device Comparison Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 4 Terminal Configuration and Functions 4.1 Pin Diagram The following figures show the bottom view of the package pin assignments. SD0_D1/ I2S0_RX/ GP[3] SD0_D3/ GP[5] SD1_D1/ I2S1_RX/ GP[9] SD0_D2/ GP[4] SD0_CLK/ I2S0_CLK/ GP[0] SD0_CMD/ I2S0_FS/ GP[1] SD1_D3/ GP[11] SD1_CMD/ I2S1_FS/ GP[7] SD1_D0/ I2S1_DX/ GP[8] SD1_CLK/ I2S1_CLK/ GP[6] SD1_D2/ GP[10] SD0_D0/ I2S0_DX/ GP[2] USB_MXI USB_MXO INT0 DSP_LDO_ EN DVDDRTC INT1 LDOI LDOI DSP_LDOO Figure 4-1. C5535 Pin Diagram Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 13 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com P VSS GP[14] GP[16] TRST I2S2_CLK/ GP[18]/ SPI_CLK SD0_D1/ I2S0_RX/ GP[3] SD0_D3/ GP[5] GP[17] I2S2_RX/ GP[20]/ SPI_RX SD1_D1/ I2S1_RX/ GP[9] I2S2_DX/ GP[27]/ SPI_TX UART_CTS/ GP[29]/ I2S3_FS UART_RXD/ GP[30]/ I2S3_RX N TDO SPI_CS2 TCK SPI_RX GP[13] TMS GP[15] DVDDIO CVDD I2S2_FS/ GP[19]/ SPI_CS0 DVDDIO UART_RTS/ GP[28]/ I2S3_CLK SD0_D2/ GP[4] DVDDIO M EMU1 SPI_CS1 DVDDIO DVDDIO SPI_CS3 CVDD VSS SD0_CLK/ I2S0_CLK/ GP[0] CVDD SD0_CMD/ I2S0_FS/ GP[1] UART_TXD/ GP[31]/ I2S3_DX SD1_D3/ GP[11] SD1_D0/ I2S1_DX/ GP[8] SD1_CLK/ I2S1_CLK/ GP[6] L SPI_CS0 EMU0 SPI_CLK DVDDIO VSS VSS SD1_CMD/ I2S1_FS/ GP[7] SD1_D2/ GP[10] RSV2 USB_VBUS K SPI_TX TDI VSS VSS CVDD RSV1 USB_VDD1P3 J SD0_D0/ I2S0_DX/ GP[2] GP[12] XF USB_VSSA1P3 VSS USB_DM H RSV10 CVDD VSS USB_ VDDA1P3 USB_VSSA3P3 USB_DP G RSV9 RSV12 CVDD USB_VDDA3P3 USB_VDDPLL USB_R1 F RSV8 CVDD VSS E RSV7 RSV11 VSS VSS D CLK_SEL RESET CVDD VSS VSS C CLKIN INT0 DVDDRTC SCL VSSRTC DVDDIO VDDA_PLL VSS B INT1 VSS VSS CVDDRTC CVDDRTC VSSA_ANA VDDA_ANA A VSSA_PLL CLKOUT RTC_CLKOUT SDA WAKEUP RTC_XO 1 2 3 4 5 6 VSS USB_VSS1P3 USB_VSSREF USB_VSSPLL USB_VDD1P3 VSS USB_VDD1P3 USB_VDDOSC USB_MXI USB_VSSOSC USB_LDOO USB_MXO VSS CVDD VSSA_ANA BG_CAP CVDD VSS DSP_LDO_ EN LDOI NC ANA_LDOO LDOI RSV5 RSV3 RSV6 LDOI RTC_XI NC NC NC RSV4 RSV0 DSP_LDOO VSS 7 8 9 10 11 12 13 14 Figure 4-2. C5534 Pin Diagram 14 Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 P VSS GP[14] GP[16] TRST I2S2_CLK/ GP[18]/ SPI_CLK SD0_D1/ I2S0_RX/ GP[3] SD0_D3/ GP[5] GP[17] I2S2_RX/ GP[20]/ SPI_RX SD1_D1/ I2S1_RX/ GP[9] I2S2_DX/ GP[27]/ SPI_TX UART_CTS/ GP[29]/ I2S3_FS UART_RXD/ GP[30]/ I2S3_RX N TDO SPI_CS2 TCK SPI_RX GP[13] TMS GP[15] DVDDIO CVDD I2S2_FS/ GP[19]/ SPI_CS0 DVDDIO UART_RTS/ GP[28]/ I2S3_CLK SD0_D2/ GP[4] DVDDIO M EMU1 SPI_CS1 DVDDIO DVDDIO SPI_CS3 CVDD VSS SD0_CLK/ I2S0_CLK/ GP[0] CVDD SD0_CMD/ I2S0_FS/ GP[1] UART_TXD/ GP[31]/ I2S3_DX SD1_D3/ GP[11] SD1_D0/ I2S1_DX/ GP[8] SD1_CLK/ I2S1_CLK/ GP[6] L SPI_CS0 EMU0 SPI_CLK DVDDIO VSS VSS SD1_CMD/ I2S1_FS/ GP[7] SD1_D2/ GP[10] RSV2 USB_VBUS K SPI_TX TDI VSS VSS CVDD RSV1 USB_VDD1P3 J SD0_D0/ I2S0_DX/ GP[2] GP[12] XF USB_VSSA1P3 VSS USB_DM H RSV10 CVDD VSS USB_ VDDA1P3 USB_VSSA3P3 USB_DP G RSV9 RSV12 CVDD USB_VDDA3P3 USB_VDDPLL USB_R1 F RSV8 CVDD VSS E RSV7 RSV11 VSS VSS D CLK_SEL RESET CVDD VSS VSS C CLKIN INT0 DVDDRTC SCL VSSRTC VSS DVDDIO VDDA_PLL VSS VSSA_ANA VSS CVDD BG_CAP CVDD USB_VDD1P3 USB_VDDOSC USB_MXI USB_VSSOSC USB_LDOO USB_MXO VSS DSP_LDO_ LDOI B INT1 VSS VSS CVDDRTC CVDDRTC VSSA_ANA VDDA_ANA NC ANA_LDOO LDOI RSV5 RSV3 A VSSA_PLL CLKOUT RTC_CLKOUT SDA WAKEUP RTC_XO RTC_XI NC NC NC RSV4 RSV0 1 2 3 4 5 6 7 8 9 10 11 12 (2) USB_VSS1P3 USB_VSSREF USB_VSSPLL USB_VDD1P3 EN (1) VSS (1) LDOI RSV6 DSP_LDOO (2) 13 VSS 14 DSP_LDOO is not supported on the TMS320C5533. An external power supply is used to provide power to CVDD, DSP_LDO_EN must be tied to LDOI, and DSP_LDOO must be left unconnected. The RESET pin must be asserted appropriately for device initialization after power up. DSP_LDOO is not supported on the TMS320C5533. For proper device operation, this pin must be left connected. DSP_LDOO can be enabled to provide a regulated 1.3- or 1.05-V output only to the internal POR to support the RTC-only mode. For more information, see Section 5.7.11.1, RTC Only Mode. Figure 4-3. C5533 Pin Diagram Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 15 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com P VSS GP[14] GP[16] TRST I2S2_CLK/ GP[18]/ SPI_CLK SD0_D1/ I2S0_RX/ GP[3] SD0_D3/ GP[5] GP[17] I2S2_RX/ GP[20]/ SPI_RX SD1_D1/ I2S1_RX/ GP[9] I2S2_DX/ GP[27]/ SPI_TX UART_CTS/ GP[29]/ I2S3_FS UART_RXD/ GP[30]/ I2S3_RX N TDO SPI_CS2 TCK SPI_RX GP[13] TMS GP[15] DVDDIO CVDD I2S2_FS/ GP[19]/ SPI_CS0 DVDDIO UART_RTS/ GP[28]/ I2S3_CLK SD0_D2/ GP[4] DVDDIO M EMU1 SPI_CS1 DVDDIO DVDDIO SPI_CS3 CVDD VSS SD0_CLK/ I2S0_CLK/ GP[0] CVDD SD0_CMD/ I2S0_FS/ GP[1] UART_TXD/ GP[31]/ I2S3_DX SD1_D3/ GP[11] SD1_D0/ I2S1_DX/ GP[8] SD1_CLK/ I2S1_CLK/ GP[6] L SPI_CS0 EMU0 SPI_CLK DVDDIO VSS VSS SD1_CMD/ I2S1_FS/ GP[7] SD1_D2/ GP[10] RSV2 USB_VBUS K SPI_TX TDI VSS VSS CVDD RSV1 USB_VDD1P3 J SD0_D0/ I2S0_DX/ GP[2] GP[12] XF USB_VSSA1P3 VSS USB_DM H RSV10 CVDD VSS USB_ VDDA1P3 USB_VSSA3P3 USB_DP G RSV9 RSV12 CVDD USB_VDDA3P3 USB_VDDPLL USB_R1 F RSV8 CVDD VSS E RSV7 RSV11 VSS VSS D CLK_SEL RESET CVDD VSS VSS USB_VSS1P3 USB_VSSREF USB_VSSPLL USB_VDD1P3 VSS VSS VSS CVDD USB_VDD1P3 USB_VDDOSC USB_MXI USB_VSSOSC USB_MXO USB_ (1) LDOO CLKIN C INT0 DVDDRTC SCL VSSRTC DVDDIO VDDA_PLL VSS VSSA_ANA BG_CAP CVDD VSS DSP_LDO_ EN B INT1 VSS VSS CVDDRTC CVDDRTC VSSA_ANA VDDA_ANA NC ANA_LDOO LDOI RSV5 RSV3 A VSSA_PLL CLKOUT RTC_CLKOUT SDA WAKEUP RTC_XO RTC_XI NC NC NC RSV4 RSV0 (2) RSV6 1 (3) 2 3 4 5 6 7 8 9 10 11 12 LDOI DSP_ (3) LDOO (1) (2) LDOI 13 VSS 14 USB_LDOO is not supported on the TMS320C5532. For proper device operation, this pin must be left unconnected. DSP_LDOO is not supported on the TMS320C5532. An external power supply is used to provide power to CVDD, DSP_LDO_EN must be tied to LDOI, and DSP_LDOO must be left unconnected. The RESET pin must be asserted appropriately for device initialization after power up. DSP_LDOO is not supported on the TMS320C5532. For proper device operation, this pin must be left connected. DSP_LDOO can be enabled to provide a regulated 1.3- or 1.05-V output only to the internal POR to support the RTC-only mode. For more information, see Section 5.7.11.1, RTC Only Mode. Shaded pins are not supported on this device. To ensure proper device operation, these pins must be hooked up properly. See Table 4-9, Unsupported USB 2.0 Signal Descriptions. Figure 4-4. C5532 Pin Diagram 16 Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com 4.2 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 Signal Descriptions The signal descriptions tables (Table 4-1 through Table 4-18) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors or bus-holders, and a functional pin description. For more information on pin multiplexing, see Section 4.3, Pin Multiplexing. For proper device operation, external pullup and pulldown resistors may be required on some pins. Section 5.7.17.1.1, Pullup and Pulldown Resistors discusses situations where external pullup and pulldown resistors are required. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 17 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 4.2.1 www.ti.com Oscillator and PLL Table 4-1. Oscillator and PLL Signal Descriptions SIGNAL NAME TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION DSP clock output signal. For debug purposes only, the CLKOUT pin can be used to tap different clocks within the system clock generator. The SRC bits in the CLKOUT Control Source Register (CCSSR) can be used to specify the CLKOUT pin source. Additionally, the slew rate of the CLKOUT pin can be controlled by the Output Slew Rate Control Register (OSRCR) [1C16h]. CLKOUT A2 O/Z – DVDDIO BH The CLKOUT pin is enabled and disabled through the CLKOFF bit in the CPU ST3_55 register. When disabled, the CLKOUT pin is placed in high-impedance (Hi-Z). At reset the CLKOUT pin is enabled until the beginning of the boot sequence, when the on-chip bootloader sets CLKOFF = 1 and the CLKOUT pin is disabled (Hi-Z). For more information on the ST3_55 register, see the TMS320C55x 3.0 CPU Reference Guide (literature number: SWPU073). Note: This pin may consume static power if configured as Hi-Z and not externally pulled low or high. Prevent current drain by externally terminating the pin. Input clock. This signal is used to input an external clock when the 32-kHz on-chip oscillator is not used as the DSP clock (pin CLK_SEL = 1). For boot purposes, the CLKIN frequency is assumed to be either 11.2896, 12, or 12.288 MHz. The CLK_SEL pin (D1) selects between the 32-kHz crystal clock or CLKIN. CLKIN C1 I – DVDDIO BH When the CLK_SEL pin is low, this pin must be tied to ground (VSS). When CLK_SEL is high, this pin must be driven by an external clock source. If CLK_SEL is high, this pin is used as the reference clock for the clock generator. During bootup, the bootloader bypasses the PLL and assumes the CLKIN frequency is one of the following frequencies: 11.2896-, 12-, or 12.288-MHz. In addition, the bootloader sets the SPI clock rate at 500 kHz and the I2C clock rate at 400 kHz . Clock input select. This pin selects between the 32-kHz crystal clock or CLKIN. CLK_SEL D1 I – DVDDIO BH 0 = 32-kHz on-chip oscillator drives the RTC timer and the system clock generator while CLKIN is ignored. 1 = CLKIN drives the system clock generator and the 32-kHz on-chip oscillator drives only the RTC timer. This pin is not allowed to change during device operation; it must be tied high or low at the board. (1) (2) (3) (4) 18 VDDA_PLL C7 PWR 1.3-V Analog PLL power supply for the system clock generator (PLLOUT ≤ 120 see Section 5.2, MHz). ROC This signal can be powered from the ANA_LDOO pin. VSSA_PLL A1 GND see Section 5.2, Analog PLL ground for the system clock generator. ROC I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com 4.2.2 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 Real-Time Clock (RTC) Table 4-2. RTC Signal Descriptions SIGNAL NAME TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION Real-time clock oscillator output. This pin operates at the RTC core voltage, CVDDRTC, and supports a 32.768-kHz crystal. RTC_XO A6 I/O/Z – CVDDRTC DVDDRTC If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to CVDDRTC and RTC_XO to ground (VSS). A voltage must still be applied to CVDDRTC by an external power source (see Section 5.2, Recommended Operating Conditions). None of the on-chip LDOs can be used to power CVDDRTC. Note: When RTC oscillator is disabled, the RTC registers (I/O address range 1900h – 197Fh) are not accessible. Real-time clock oscillator input. – RTC_XI A7 I CVDDRTC DVDDRTC If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to CVDDRTC and RTC_XO to ground (VSS). A voltage must still be applied to CVDDRTC by an external power source (see Section 5.2, Recommended Operating Conditions). None of the on-chip LDOs can be used to power CVDDRTC. Note: When RTC oscillator is disabled, the RTC registers (I/O address range 1900h – 197Fh) are not accessible. RTC_CLKOUT A3 O/Z WAKEUP A5 I/O/Z (1) (2) (3) (4) – DVDDRTC – DVDDRTC Real-time clock output pin. This pin operates at DVDDRTC voltage. The RTC_CLKOUT pin is enabled and disabled through the RTCCLKOUTEN bit in the RTC Power Management Register (RTCPMGT). At reset, the RTC_CLKOUT pin is disabled (high-impedance [Hi-Z]). The pin is used to WAKEUP the core from idle condition. This pin defaults to an input at CVDDRTC powerup, but can also be configured as an active-low open-drain output signal to wakeup an external device from an RTC alarm. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 19 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 4.2.3 www.ti.com RESET, Interrupts, and JTAG Table 4-3. RESET, Interrupts, and JTAG Signal Descriptions SIGNAL NAME TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION RESET External Flag Output. XF is used for signaling other processors in multiprocessor configurations or XF can be used as a fast general-purpose output pin. XF J3 O/Z – DVDDIO BH XF is set high by the BSET XF instruction and XF is set low by the BCLR XF instruction or by writing to bit 13 of the ST1_55 register. For more information on the ST1_55 register, see the TMS320C55x 3.0 CPU Reference Guide (literature number: SWPU073). For XF pin behavior at reset, see Section 5.7.3.2, Pin Behavior at Reset. Note: This pin may consume static power if configured as Hi-Z and not externally pulled low or high. Prevent current drain by externally terminating the pin. XF pin is ONLY in the Hi-Z state when doing boundary scan. Therefore, external termination is probably not required for most applications. RESET D2 I IPU DVDDIO BH Device reset. RESET causes the DSP to terminate execution and loads the program counter with the contents of the reset vector. When RESET is brought to a high level, the reset vector in ROM at FFFF00h forces the program execution to branch to the location of the on-chip ROM bootloader. RESET affects the various registers and status bits. The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register but will be forced ON when RESET is asserted. JTAG [For more detailed information on emulation header design guidelines, see the XDS560 Emulator Technical Reference (literature number: SPRU589).] IEEE standard 1149.1 test mode select. This serial control input is clocked into the TAP controller on the rising edge of TCK. TMS N6 I IPU DVDDIO BH If the emulation header is located greater than 6 inches from the device, TMS must be buffered. In this case, the input buffer for TMS needs a pullup resistor connected to DVDDIO to hold the signal at a known value when the emulator is not connected. A resistor value of 4.7 kΩ or greater is suggested. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589). The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register. IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance (Hi-Z) state except when the scanning of data is in progress. TDO N1 O/Z – DVDDIO BH For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589). If the emulation header is located greater than 6 inches from the device, TDO must be buffered. Note: This pin may consume static power if configured as Hi-Z and not externally pulled low or high. Prevent current drain by externally terminating the pin. TDO pin will be in Hi-Z whenever not doing emulation and boundary scan, so an external pullup is highly recommended. (1) (2) (3) (4) 20 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 Table 4-3. RESET, Interrupts, and JTAG Signal Descriptions (continued) SIGNAL NAME TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION IEEE standard 1149.1 test data input. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. TDI K2 I IPU DVDDIO BH If the emulation header is located greater than 6 inches from the device, TDI must be buffered. In this case, the input buffer for TDI needs a pullup resistor connected to DVDDIO to hold this signal at a known value when the emulator is not connected. A resistor value of 4.7 kΩ or greater is suggested. The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register. IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. TCK N3 I IPU DVDDIO BH If the emulation header is located greater than 6 inches from the device, TCK must be buffered. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589). The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register. TRST P4 I IPD DVDDIO BH IEEE standard 1149.1 reset signal for test and emulation logic. TRST, when high, allows the IEEE standard 1149.1 scan and emulation logic to take control of the operations of the device. If TRST is not connected or is driven low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are ignored. The device will not operate properly if this reset pin is never asserted low. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589). It is recommended that an external pulldown resistor be used in addition to the IPD - especially if there is a long trace to an emulation header. Emulator 1 pin. EMU1 is used as an interrupt to or from the emulator system and is defined as input/output by way of the emulation logic. EMU1 M1 I/O/Z IPU DVDDIO BH For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589). An external pullup to DVDDIO is required to provide a signal rise time of less than 10 μsec. A 4.7-kΩ resistor is suggested for most applications. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589). The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register. EMU0 L2 I/O/Z IPU DVDDIO BH Emulator 0 pin. When TRST is driven low and then high, the state of the EMU0 pin is latched and used to connect the JTAG pins (TCK, TMS, TDI, TDO) to either the IEEE1149.1 Boundary-Scan TAP (when the latched value of EMU0 = 0) or to the DSP Emulation TAP (when the latched value of EMU0 = 1). Once TRST is high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the emulation logic. An external pullup to DVDDIO is required to provide a signal rise time of less than 10 μsec. A 4.7-kΩ resistor is suggested for most applications. For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589). The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register. EXTERNAL INTERRUPTS INT1 B1 I IPU DVDDIO BH External interrupt inputs (INT1 and INT0). These pins are maskable via their specific Interrupt Mask Register (IMR1, IMR0) and the interrupt mode bit. The pins can be polled and reset by their specific Interrupt Flag Register (IFR1, IFR0). INT0 C2 I IPU DVDDIO BH The IPU resistor on these pins can be enabled or disabled via the PDINHIBR2 register. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 21 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 4.2.4 www.ti.com Inter-Integrated Circuit (I2C) Table 4-4. I2C Signal Descriptions SIGNAL NAME NO. TYPE (1) (2) OTHER (3) This pin is the I2C clock output. Per the I2C standard, an external pullup is required on this pin. This pin is the I2C bidirectional data signal. Per the I2C standard, an external pullup is required on this pin. (4) DESCRIPTION I2C (1) (2) (3) (4) 22 SCL C4 I/O/Z DVDDIO BH SDA A4 I/O/Z DVDDIO BH I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com 4.2.5 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 Inter-IC Sound (I2S) Table 4-5. I2S0 – I2S3 Signal Descriptions SIGNAL NAME (5) TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION (5) Interface 0 (I2S0) This pin is multiplexed between SD0, I2S0, and GPIO. SD0_D0/ I2S0_DX/ GP[2] J1 I/O/Z IPD DVDDIO BH For I2S, it is I2S0 transmit data output I2S0_DX. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD0, I2S0, and GPIO. SD0_CLK/ I2S0_CLK/ GP[0] M8 I/O/Z IPD DVDDIO BH For I2S, it is I2S0 clock input/output I2S0_CLK. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD0, I2S0, and GPIO. SD0_D1/ I2S0_RX/ GP[3] P6 I/O/Z IPD DVDDIO BH For I2S, it is I2S0 receive data input I2S0_RX. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD0, I2S0, and GPIO. SD0_CMD/ I2S0_FS/ GP[1] M10 I/O/Z IPD DVDDIO BH For I2S, it is I2S0 frame synchronization input/output I2S0_FS. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. Interface 1 (I2S1) This pin is multiplexed between SD1, I2S1, and GPIO. SD1_D0/ I2S1_DX/ GP[8] M13 I/O/Z IPD DVDDIO BH For I2S, it is I2S1 transmit data output I2S1_DX. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD1, I2S1, and GPIO. SD1_CLK/ I2S1_CLK/ GP[6] M14 I/O/Z IPD DVDDIO BH For I2S, it is I2S1 clock input/output I2S1_CLK. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD1, I2S1, and GPIO. SD1_D1/ I2S1_RX/ GP[9] P10 I/O/Z IPD DVDDIO BH For I2S, it is I2S1 receive data input I2S1_RX. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD1, I2S2, and GPIO. SD1_CMD/ I2S1_FS/ GP[7] (1) (2) (3) (4) (5) L11 I/O/Z IPD DVDDIO BH For I2S, it is I2S1 frame synchronization input/output I2S1_FS. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal LCD Bridge applies only to TMS320C5535. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 23 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com Table 4-5. I2S0 – I2S3 Signal Descriptions (continued) SIGNAL NAME (5) TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION (5) Interface 2 (I2S2) LCD_D[11]/ I2S2_DX/ GP[27]/ SPI_TX LCD_D[8]/ I2S2_CLK/ GP[18]/ SPI_CLK LCD_D[10]/ I2S2_RX/ GP[20]/ SPI_RX LCD_D[9]/ I2S2_FS/ GP[19]/ SPI_CS0 This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI. P11 I/O/Z IPD DVDDIO BH For I2S, it is I2S2 transmit data output I2S2_DX. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI. P5 I/O/Z IPD DVDDIO BH For I2S, it is I2S2 clock input/output I2S2_CLK. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI. P9 I/O/Z IPD DVDDIO BH For I2S, it is I2S2 receive data input I2S2_RX. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, I2S2 and GPIO. N10 I/O/Z IPD DVDDIO BH For I2S, it is I2S2 frame synchronization input/output I2S2_FS. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. Interface 3 (I2S3) LCD_D[15]/ UART_TXD/ GP[31]/ I2S3_DX LCD_D[12]/ UART_RTS/ GP[28]/ I2S3_CLK LCD_D[14]/ UART_RXD/ GP[30]/ I2S3_RX LCD_D[13]/ UART_CTS/ GP[29]/ I2S3_FS 24 This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3. M11 I/O/Z IPD DVDDIO BH For I2S, it is I2S3 transmit data output I2S3_DX. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3. N12 I/O/Z IPD DVDDIO BH For I2S, it is I2S3 clock input/output I2S3_CLK. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3. P13 I/O/Z IPD DVDDIO BH For I2S, it is I2S3 receive data input I2S3_RX. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3. P12 I/O/Z IPD DVDDIO BH Terminal Configuration and Functions For I2S, it is I2S3 frame synchronization input/output I2S3_FS. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com 4.2.6 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 Serial Peripheral Interface (SPI) Table 4-6. SPI Signal Descriptions SIGNAL NAME (5) TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION (5) Serial Port Interface (SPI) This pin is multiplexed between LCD Bridge and SPI. LCD_CS0_E0/ SPI_CS0 L1 I/O/Z DVDDIO BH Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI chip select SPI_CS0. This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI. LCD_D[9]/ I2S2_FS/ GP[19]/ SPI_CS0 N10 I/O/Z IPD DVDDIO BH Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI chip select SPI_CS0. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge and SPI. LCD_CS1_E1/ SPI_CS1 M2 I/O/Z DVDDIO BH Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI chip select SPI_CS1. This pin is multiplexed between LCD Bridge and SPI. LCD_RW_WRB/ SPI_CS2 N2 I/O/Z DVDDIO BH LCD_RS/ SPI_CS3 M5 I/O/Z DVDDIO BH Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI chip select SPI_CS2. This pin is multiplexed between LCD Bridge and SPI. Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI chip select SPI_CS3. This pin is multiplexed between LCD Bridge and SPI. LCD_EN_RDB/ SPI_CLK L3 O/Z DVDDIO BH Mux control via the PPMODE bits in the EBSR. For SPI, this pin is clock output SPI_CLK. Note: This pin may consume static power if configured as Hi-Z and not externally pulled low or high. Prevent current drain by externally terminating the pin. This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI. LCD_D[8]/ I2S2_CLK/ GP[18]/ SPI_CLK P5 I/O/Z IPD DVDDIO BH Mux control via the PPMODE bits in the EBSR. For SPI, this pin is clock output SPI_CLK. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge and SPI. LCD_D[1]/ SPI_TX K1 I/O/Z DVDDIO BH I/O/Z IPD DVDDIO BH Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI transmit data output. This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI. LCD_D[11]/ I2S2_DX/ GP[27]/ SPI_TX P11 Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI transmit data output. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge and SPI. LCD_D[0]/ SPI_RX (1) (2) (3) (4) (5) N4 I/O/Z DVDDIO BH Mux control via the PPMODE bits in the EBSR. For SPI this pin is SPI receive data input. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal LCD Bridge applies to only TMS320C5535. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 25 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com Table 4-6. SPI Signal Descriptions (continued) SIGNAL NAME (5) NO. TYPE (1) (2) OTHER (3) I/O/Z IPD DVDDIO BH (4) DESCRIPTION (5) This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI. LCD_D[10]/ I2S2_RX/ GP[20]/ SPI_RX P9 Mux control via the PPMODE bits in the EBSR. For SPI this pin is SPI receive data input. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. 26 Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com 4.2.7 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 Universal Asynchronous Receiver/Transmitter (UART) Table 4-7. UART Signal Descriptions SIGNAL NAME (5) TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION (5) UART LCD_D[14]/ UART_RXD/ GP[30]/ I2S3_RX LCD_D[15]/ UART_TXD/ GP[31]/ I2S3_DX LCD_D[13]/ UART_CTS/ GP[29]/ I2S3_FS LCD_D[12]/ UART_RTS/ GP[28]/ I2S3_CLK (1) (2) (3) (4) (5) This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3. P13 I/O/Z IPD DVDDIO BH When used by UART, it is the receive data input UART_RXD. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3. M11 I/O/Z IPD DVDDIO BH In UART mode, it is the transmit data output UART_TXD. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3. P12 I/O/Z IPD DVDDIO BH In UART mode, it is the clear to send input UART_CTS. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3. N12 I/O/Z IPD DVDDIO BH In UART mode, it is the ready to send output UART_RTS. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal LCD Bridge applies only to TMS320C5535. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 27 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 4.2.8 www.ti.com Universal Serial Bus (USB) 2.0 Table 4-8. USB 2.0 Signal Descriptions — Not Used On C5532 SIGNAL NAME TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION USB 2.0 12-MHz crystal oscillator input. When the USB peripheral is not used, USB_MXI must be connected to ground (VSS). USB_MXI E14 I USB_VDDOSC When using an external 12-MHz oscillator, the external oscillator clock signal must be connected to the USB_MXI pin and the amplitude of the oscillator clock signal must meet the VIH requirement (see Section 5.2, Recommended Operating Conditions). The USB_MXO remains unconnected and the USB_VSSOSC signal is connected to board ground (VSS). 12-MHz crystal oscillator output. When the USB peripheral is not used, USB_MXO must be left unconnected. USB_MXO D14 O/Z USB_VDDOSC USB_VDDOSC E13 S see Section 5.2, ROC When using an external 12-MHz oscillator, the external oscillator clock signal must be connected to the USB_MXI pin and the amplitude of the oscillator clock signal must meet the VIH requirement (see Section 5.2, Recommended Operating Conditions). The USB_MXO remains unconnected and the USB_VSSOSC signal is connected to board ground (VSS). 3.3-V power supply for USB oscillator. When the USB peripheral is not used, USB_VDDOSC must be connected to ground (VSS). Ground for USB oscillator. USB_VSSOSC D12 S see Section 5.2, ROC When the USB peripheral is not used, USB_VSSOSC must be connected to ground (VSS). When using an external 12-MHz oscillator, the external oscillator clock signal must be connected to the USB_MXI pin and the amplitude of the oscillator clock signal must meet the VIH requirement (see Section 5.2, Recommended Operating Conditions). The USB_MXO remains unconnected and the USB_VSSOSC signal is connected to board ground (VSS). USB power detect. 5-V input that signifies that VBUS is connected. USB_VBUS L14 A I/O see Section 5.2, ROC USB_DP H14 A I/O USB_VDDA3P3 USB_DM J14 A I/O USB_VDDA3P3 USB_R1 G14 A I/O USB_VDDA3P3 This signal must be powered on in the order listed in Section 5.7.2.4, Power-Supply Sequencing. When the USB peripheral is not used, the USB_VBUS signal must be connected to ground (VSS). USB bi-directional Data Differential signal pair [positive and negative]. When the USB peripheral is not used, the USB_DP and USB_DM signals should both be tied to ground (VSS). External resistor connect. Reference current output. This must be connected via a 10-kΩ ±1% resistor to USB_VSSREF and be placed as close to the device as possible. When the USB peripheral is not used, the USB_R1 signal must be connected via a 10-kΩ resistor to ground (VSS). USB_VSSREF (1) (2) (3) (4) 28 F12 GND see Section 5.2, ROC Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to USB_R1. When the USB peripheral is not used, the USB_VSSREF signal must be connected directly to ground (Vss). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 Table 4-8. USB 2.0 Signal Descriptions — Not Used On C5532 (continued) SIGNAL NAME TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION Analog 3.3 V power supply for USB PHY. USB_VDDA3P3 USB_VSSA3P3 G12 H13 S GND see Section 5.2, ROC see Section 5.2, ROC This signal must be powered on in the order listed in Section 5.7.2.4, Power-Supply Sequencing. When the USB peripheral is not used, the USB_VDDA3P3 signal must be connected to ground (VSS). Analog ground for USB PHY. Analog 1.3 V power supply for USB PHY. [For high-speed sensitive analog circuits] USB_VDDA1P3 USB_VSSA1P3 H12 J12 S GND see Section 5.2, ROC see Section 5.2, ROC This signal must be powered on in the order listed in Section 5.7.2.4, Power-Supply Sequencing. When the USB peripheral is not used, the USB_VDDA1P3 signal must be connected to ground (VSS). Analog ground for USB PHY [For high speed sensitive analog circuits]. 1.3-V digital core power supply for USB PHY. K13, E12, F14 S USB_VSS1P3 K14 GND see Section 5.2, ROC USB_VDDPLL G13 S see Section 5.2, ROC USB_VSSPLL F13 GND see Section 5.2, ROC USB_VDD1P3 see Section 5.2, ROC This signal must be powered on in the order listed in Section 5.7.2.4, Power-Supply Sequencing. When the USB peripheral is not used, the USB_VDD1P3 signal must be connected to ground (VSS). Digital core ground for USB PHY. Analog ground for USB PHY [For high-speed sensitive analog circuits]. 3.3 V USB Analog PLL power supply. When the USB peripheral is not used, the USB_VDDPLL signal must be connected to ground (VSS). USB Analog PLL ground. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 29 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com Table 4-9. Unsupported USB 2.0 Signal Descriptions — TMS320C5532 Only SIGNAL NAME TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION USB 2.0 (1) (2) (3) (4) 30 USB_MXI E14 I - When the USB peripheral is not used, USB_MXI must be connected to ground (VSS). USB_MXO D14 O/Z - When the USB peripheral is not used, USB_MXO must be left unconnected. USB_VDDOSC E13 S - When the USB peripheral is not used, USB_VDDOSC must be connected to ground (VSS). USB_VSSOSC D12 S - The USB_MXO remains unconnected and the USB_VSSOSC signal is connected to board ground (VSS). USB_VBUS L14 A I/O - When the USB peripheral is not used, the USB_VBUS signal must be connected to ground (VSS). USB_DP H14 A I/O - USB_DM J14 A I/O - When the USB peripheral is not used, the USB_DP and USB_DM signals should both be tied to ground (VSS). USB_R1 G14 A I/O - When the USB peripheral is not used, the USB_R1 signal must be connected via a 10-kΩ resistor to ground (Vss). USB_VSSREF F12 GND - When the USB peripheral is not used, the USB_VSSREF signal must be connected directly to ground (Vss). USB_VDDA3P3 G12 S - When the USB peripheral is not used, the USB_VDDA3P3 signal must be connected to ground (VSS). USB_VSSA3P3 H13 GND - When the USB peripheral is not used, USB_VSSA3P3 must be conntected to ground (VSS). USB_VDDA1P3 H12 S - When the USB peripheral is not used, the USB_VDDA1P3 signal must be connected to ground (VSS). USB_VSSA1P3 J12 GND - When the USB peripheral is not used, USBVSSA1P3 must be connected to ground (VSS). USB_VDD1P3 K13, E12, F14 S - When the USB peripheral is not used, the USB_VDD1P3 signal must be connected to ground (VSS). USB_VSS1P3 K14 GND - When the USB peripheral is not used, USB_VSS1P3 must be connected to ground (VSS). USB_VDDPLL G13 S - When the USB peripheral is not used, the USB_VDDPLL signal must be connected to ground (VSS). USB_VSSPLL F13 GND - When the USB peripheral is not used, USB_VSSPLL must be connected to ground (VSS). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com 4.2.9 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 LCD Bridge Table 4-10. LCD Bridge Signal Descriptions — C5535 Only SIGNAL NAME TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION This pin is multiplexed between LCD Bridge and SPI. LCD_EN_RDB/ SPI_CLK L3 O/Z DVDDIO BH For LCD Bridge, this pin is either LCD Bridge read and write enable (MPU68 mode) or read strobe (MPU80 mode). Mux control via the PPMODE bits in the EBSR. Note: This pin may consume static power if configured as Hi-Z and not externally pulled low or high. Prevent current drain by externally terminating the pin. This pin is multiplexed between LCD Bridge and SPI. LCD_CS0_E0/ SPI_CS0 L1 I/O/Z DVDDIO BH For LCD Bridge, this pin is either LCD Bridge chip select 0 (MPU68 and MPU80 modes) or enable 0 (HD44780 mode). Mux control via the PPMODE bits in the EBSR. This pin is multiplexed between LCD Bridge and SPI. LCD_CS1_E1/ SPI_CS1 M2 I/O/Z DVDDIO BH For LCD Bridge, this pin is either LCD Bridge chip select 1 (MPU68 and MPU80 modes) or enable 1 (HD44780 mode). Mux control via the PPMODE bits in the EBSR. This pin is multiplexed between LCD Bridge and SPI. LCD_RW_WRB/ SPI_CS2 N2 I/O/Z DVDDIO BH For LCD, this pin is either LCD Bridge read and write select (HD44780 and MPU68 modes) or write strobe (MPU80 mode). Mux control via the PPMODE bits in the EBSR. This pin is multiplexed between LCD Bridge and SPI. LCD_RS/ SPI_CS3 M5 I/O/Z DVDDIO BH For LCD, this pin is the LCD Bridge address set-up. Mux control via the PPMODE bits in the EBSR. LCD_D[15]/ UART_TXD/ GP[31]/ I2S3_DX LCD_D[14]/ UART_RXD/ GP[30]/ I2S3_RX LCD_D[13]/ UART_CTS/ GP[29]/ I2S3_FS LCD_D[12]/ UART_RTS/ GP[28]/ I2S3_CLK (1) (2) (3) (4) This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3. M11 I/O/Z IPD DVDDIO BH For LCD Bridge, it is LCD data pin 15. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3. P13 I/O/Z IPD DVDDIO BH For LCD Bridge, it is LCD data pin 14. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3. P12 I/O/Z IPD DVDDIO BH For LCD Bridge, it is LCD data pin 13. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, I2S2, and GPIO. N12 I/O/Z IPD DVDDIO BH For LCD Bridge, it is LCD data pin 12. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 31 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com Table 4-10. LCD Bridge Signal Descriptions — C5535 Only (continued) SIGNAL NAME LCD_D[11]/ I2S2_DX/ GP[27]/ SPI_TX LCD_D[10]/ I2S2_RX/ GP[20]/ SPI_RX LCD_D[9]/ I2S2_FS/ GP[19]/ SPI_CS0 LCD_D[8]/ I2S2_CLK GP[18]/ SPI_CLK NO. TYPE (1) (2) OTHER (3) I/O/Z IPD DVDDIO BH (4) DESCRIPTION This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI. P11 For LCD Bridge, it is LCD data pin 11. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI. P9 I/O/Z IPD DVDDIO BH For LCD Bridge, it is LCD data pin 10. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI. N10 I/O/Z IPD DVDDIO BH For LCD Bridge, it is LCD data pin 9. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI. P5 I/O/Z IPD DVDDIO BH For LCD Bridge, it is LCD data pin 8. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge and GPIO. LCD_D[7]/ GP[17] P8 I/O/Z IPD DVDDIO BH For LCD Bridge, it is LCD data pin 7. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge and GPIO. LCD_D[6]/ GP[16] P3 I/O/Z IPD DVDDIO BH For LCD Bridge, it is LCD data pin 6. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge and GPIO. LCD_D[5]/ GP[15] N7 I/O/Z IPD DVDDIO BH For LCD Bridge, it is LCD data pin 5. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge and GPIO. LCD_D[4]/ GP[14] P2 I/O/Z IPD DVDDIO BH For LCD Bridge, it is LCD data pin 4. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge and GPIO. LCD_D[3]/ GP[13] N5 I/O/Z IPD DVDDIO BH For LCD Bridge, it is LCD data pin 3. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge and GPIO. LCD_D[2]/ GP[12] J2 I/O/Z IPD DVDDIO BH For LCD Bridge, it is LCD data pin 2. Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge and SPI. LCD_D[1]/ SPI_TX K1 I/O/Z DVDDIO BH For LCD Bridge, it is LCD data pin 1. Mux control via the PPMODE bits in the EBSR. This pin is multiplexed between LCD Bridge and SPI. LCD_D[0]/ SPI_RX N4 I/O/Z DVDDIO BH For LCD Bridge, it is LCD data pin 0. Mux control via the PPMODE bits in the EBSR. 32 Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 4.2.10 Secure Digital (SD) 4.2.10.1 SD1 Signal Descriptions Table 4-11. SD1 Signal Descriptions SIGNAL NAME TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION SD This pin is multiplexed between SD1, I2S1, and GPIO. SD1_CLK/ I2S1_CLK/ GP[6] M14 I/O/Z IPD DVDDIO BH For SD, this is the SD1 data clock output SD1_CLK. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD1, I2S1, and GPIO. SD1_CMD/ I2S1_FS/ GP[7] L11 SD1_D3/ GP[11] M12 SD1_D2/ GP[10] (1) (2) (3) (4) L12 SD1_D1/ I2S1_RX/ GP[9] P10 SD1_D0/ I2S1_DX/ GP[8] M13 I/O/Z IPD DVDDIO BH I/O/Z IPD DVDDIO BH I/O/Z IPD DVDDIO BH I/O/Z IPD DVDDIO BH I/O/Z IPD DVDDIO BH For SD, this is the SD1 command I/O output SD1_CMD. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. The SD1_D3 and SD1_D2 pins are multiplexed between SD1 and GPIO. The SD1_D1 and SD1_D0 pins are multiplexed between SD1, I2S1, and GPIO. In SD mode, all these pins are the SD1 nibble wide bi-directional data bus. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on these pins can be enabled or disabled via the PDINHIBR1 register. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 33 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com 4.2.10.2 SD0 Signal Descriptions Table 4-12. SD0 Signal Descriptions SIGNAL NAME TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION SD This pin is multiplexed between SD0, I2S0, and GPIO. SD0_CLK/ I2S0_CLK/ GP[0] M8 I/O/Z IPD DVDDIO BH For SD, this is the SD0 data clock output SD0_CLK. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD0, I2S0, and GPIO. SD0_CMD/ I2S0_FS/ GP[1] M10 SD0_D3/ GP[5] P7 SD0_D2/ GP[4] SD0_D1/ I2S0_RX/ GP[3] SD0_D0/ I2S0_DX/ GP[2] (1) (2) (3) (4) 34 N13 P6 J1 I/O/Z IPD DVDDIO BH I/O/Z IPD DVDDIO BH I/O/Z IPD DVDDIO BH I/O/Z IPD DVDDIO BH I/O/Z IPD DVDDIO BH For SD, this is the SD0 command I/O output SD0_CMD. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. The SD0_D3 and SD0_D2 pins are multiplexed between SD0 and GPIO. The SD0_D1 and SD0_D0 pins are multiplexed between SD0, I2S0, and GPIO. In SD mode, these pins are the SD0 nibble wide bi-directional data bus. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on these pins can be enabled or disabled via the PDINHIBR1 register. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 4.2.11 Successive Approximation (SAR) Analog-to-Digital Converter (ADC) Table 4-13. 10-Bit SAR ADC Signal Descriptions — C5535 Only SIGNAL NAME TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION SAR ADC GPAIN0 A8 I/O VDDA_ANA GPAIN0: General -Purpose Output and Analog Input pin 0. This pin is demuxed internally into ADC Channels 0, 1, and 2. GPAIN0 can also be used as a generalpurpose open-drain output. This pin is unique among the GPAIN pins in that it is the only pin that is 3.6 V-tolerant to support measuring a battery voltage. GPAIN0 can accommodate input voltages from 0 V to 3.6 V; although, the ADC is unable to accept signals greater than VDDA_ANA without clamping. ADC Channel 1 is capable of switching in an internal resistor divider that has a divide ratio of approximately 1/8. GPAIN1: General -Purpose Output and Analog Input pin 1. This pin is connected to ADC Channel 3. GPAIN1 can be used as a general-purpose output if certain requirements are met (see the following note). GPAIN1 can accommodate input voltages from 0 V to VDDA_ANA. GPAIN1 GPAIN2 GPAIN3 (1) (2) (3) (4) B8 A9 A10 I/O I/O I/O VDDA_ANA VDDA_ANA VDDA_ANA Note: If the ANA_LDO is used to supply power to VDDA_ANA, this pin must not be used as a general-purpose output (driving high) since the max current capability (see the ISD parameter in Section 5.3, Electrical Characteristics) of the ANA_LDO can be exceeded. Doing so may result in the on-chip power-on reset (POR) resetting the chip. GPAIN2: General -Purpose Output and Analog Input pin 2. This pin is connected to ADC Channel 4. GPAIN2 can be used as a general-purpose output if certain requirements are met (see the following note). GPAIN2 can accommodate input voltages from 0 V to VDDA_ANA. Note: If the ANA_LDO is used to supply power to VDDA_ANA, this pin must not be used as a general-purpose output (driving high) since the max current capability (see the ISD parameter in Section 5.3, Electrical Characteristics) of the ANA_LDO can be exceeded. Doing so may result in the on-chip POR resetting the chip. GPAIN3: General -Purpose Output and Analog Input pin 3. This pin is connected to ADC Channel 5. GPAIN3 can be used as a general-purpose output if certain requirements are met (see the following note). GPAIN3 can accommodate input voltages from 0 V to VDDA_ANA. Note: If the ANA_LDO is used to supply power to VDDA_ANA, this pin must not be used as a general-purpose output (driving high) since the max current capability (see the ISD parameter in Section 5.3, Electrical Characteristics) of the ANA_LDO can be exceeded. Doing so may result in the on-chip POR resetting the chip. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 35 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com 4.2.12 General-Purpose Input/Output (GPIO) Table 4-14. GPIO Signal Descriptions SIGNAL NAME (5) TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION (5) General-Purpose Input/Output External Flag Output. XF is used for signaling other processors in multiprocessor configurations or XF can be used as a fast general-purpose output pin. XF J3 O/Z – DVDDIO BH XF is set high by the BSET XF instruction and XF is set low by the BCLR XF instruction or by writing to bit 13 of the ST1_55 register. For more information on the ST1_55 register, see the TMS320C55x 3.0 CPU Reference Guide (literature number: SWPU073). For XF pin behavior at reset, see Section 5.7.3.2, Pin Behavior at Reset. Note: This pin may consume static power if configured as Hi-Z and not externally pulled low or high. Prevent current drain by externally terminating the pin. XF pin is ONLY in the Hi-Z state when doing boundary scan. Therefore, external termination is probably not required for most applications. This pin is multiplexed between SD0, I2S0, and GPIO. SD0_CLK/ I2S0_CLK/ GP[0] M8 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 0 (GP[0]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD0, I2S0, and GPIO. SD0_CMD/ I2S0_FS/ GP[1] M10 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 1 (GP[1]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD0, I2S0, and GPIO. SD0_D0/ I2S0_DX/ GP[2] J1 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 2 (GP[2]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD0, I2S0, and GPIO. SD0_D1/ I2S0_RX/ GP[3] P6 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 3 (GP[3]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD0 and GPIO. SD0_D2/ GP[4] N13 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 4 (GP[4]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD0 and GPIO. (1) (2) (3) (4) (5) 36 SD0_D3/ GP[5] P7 SD1_CLK/ I2S1_CLK/ GP[6] M14 I/O/Z I/O/Z IPD DVDDIO BH IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 5 (GP[5]). Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD1, I2S1, and GPIO. For GPIO, it is general-purpose input/output pin 6 (GP[6]). Mux control via the SP1MODE bits in the EBSR. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal LCD Bridge applies to only TMS320C5535. Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 Table 4-14. GPIO Signal Descriptions (continued) SIGNAL NAME (5) NO. TYPE (1) (2) OTHER (3) I/O/Z IPD DVDDIO BH (4) DESCRIPTION (5) This pin is multiplexed between SD1, I2S1, and GPIO. SD1_CMD/ I2S1_FS/ GP[7] L11 For GPIO, it is general-purpose input/output pin 7 (GP[7]). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD1, I2S1, and GPIO. SD1_D0/ I2S1_DX/ GP[8] M13 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 8 (GP[8]). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD1, I2S1, and GPIO. SD1_D1/ I2S1_RX/ GP[9] P10 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 9 (GP[9]). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD1 and GPIO. SD1_D2/ GP[10] L12 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 10 (GP[10]). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between SD1 and GPIO. SD1_D3/ GP[11] M12 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 11 (GP[11]). Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between LCD Bridge and GPIO. LCD_D[2]/ GP[12] J2 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 12 (GP[12]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge and GPIO. LCD_D[3]/ GP[13] N5 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 13 (GP[13]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge and GPIO. LCD_D[4]/ GP[14] P2 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 14 (GP[14]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge and GPIO. LCD_D[5]/ GP[15] N7 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 15 (GP[15]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge and GPIO. LCD_D[6]/ GP[16] P3 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 16 (GP[16]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge and GPIO. LCD_D[7]/ GP[17] P8 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 17 (GP[17]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 37 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com Table 4-14. GPIO Signal Descriptions (continued) SIGNAL NAME (5) LCD_D[8]/ I2S2_CLK/ GP[18]/ SPI_CLK LCD_D[9]/ I2S2_FS/ GP[19]/ SPI_CS0 LCD_D[10]/ I2S2_RX/ GP[20]/ SPI_RX LCD_D[11]/ I2S2_DX/ GP[27]/ SPI_TX LCD_D[12]/ UART_RTS/ GP[28]/ I2S3_CLK LCD_D[13]/ UART_CTS/ GP[29]/ I2S3_FS LCD_D[14]/ UART_RXD/ GP[30]/ I2S3_RX LCD_D[15]/ UART_TXD/ GP[31]/ I2S3_DX 38 NO. TYPE (1) (2) OTHER (3) I/O/Z IPD DVDDIO BH (4) DESCRIPTION (5) This pin is multiplexed between LCD Bridge and GPIO. P5 For GPIO, it is general-purpose input/output pin 18 (GP[18]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, I2S2, and GPIO. N10 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 19 (GP[19]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, I2S2, GPIO and SPI. P9 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 20 (GP[20]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI. P11 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 27 (GP[27]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3. N12 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 28 (GP[28]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3. P12 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 29 (GP[29]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3. P13 I/O/Z IPD DVDDIO BH For GPIO, it is general-purpose input/output pin 30 (GP[30]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3. M11 I/O/Z IPD DVDDIO BH Terminal Configuration and Functions For GPIO, it is general-purpose input/output pin 31 (GP[31]). Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register. Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 4.2.13 Regulators and Power Management Table 4-15. Regulators and Power Management Signal Descriptions SIGNAL NAME TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION Regulators DSP_LDO output. When enabled, this output provides a regulated 1.3- or 1.05-V output and up to 250 mA of current (see the ISD parameter in Section 5.3, Electrical Characteristics). The DSP_LDO is intended to supply current to the digital core circuits only (CVDD) and not external devices. For proper device operation, the external decoupling capacitor of this pin must be 5µF ~ 10µF. For more detailed information, see Section 5.7.2.7, Power-Supply Decoupling. DSP_LDOO (5) When disabled, this pin is in the high-impedance (Hi-Z) state. A13 S When DSP_LDO comes out of reset, it is enabled to 1.3 V for the bootloader to operate. For the 50 -MHz devices, DSP_LDO must be programmed to 1.05 V to match the core voltage, CVDD, for proper operation after reset. Note: DSP_LDO is not supported on TMS320C5533 and C5532, so the DSP_LDOO pin must be left unconnected. DSP_LDO can be enabled to provide a regulated 1.3 V or 1.05 V output to only the internal POR to support the RTC only mode (see Section 5.7.11.1, RTC Only Mode). DSP_LDOO must never be used to provide power to the CPU Core (CVDD) on these devices. B14, C14, B10 LDOI LDO inputs. For proper device operation, LDOI must always be powered. The LDOI pins must be connected to the same power supply source with a voltage range of 1.8 V to 3.6 V. These pins supply power to the internal LDOs, the bandgap reference generator circuits, and serve as the I/O supply for some input pins. S DSP_LDO enable input. This signal is not intended to be dynamically switched. 0 = DSP_LDO is enabled. The internal DSP LDO is enabled to regulate power on the DSP_LDOO pin at either 1.3 V or 1.05 V, according to the DSP_LDO_V bit in the LDOCNTL register (see Figure 5-4). At power-on-reset, the internal POR monitors the DSP_LDOO pin voltage and generates the internal POWERGOOD signal when the DSP_LDO voltage is above a minimum threshold voltage. The internal device reset is generated by the AND of POWERGOOD and the RESET pin. Note: For the 50 -MHz devices, DSP_LDO must be programmed to 1.05 V to match the core voltage, CVDD, for proper operation after reset. DSP_LDO_EN (5) C13 I – LDOI 1 = DSP_LDO is disabled and the DSP_LDOO pin is in a high-impedance (Hi-Z) state. The internal voltage monitoring on the DSP_LDOO is bypassed and the internal POWERGOOD signal is immediately set high. The RESET pin (D2) will act as the sole reset source for the device. If an external power supply is used to provide power to CVDD, then DSP_LDO_EN must be tied to LDOI, DSP_LDOO must be left unconnected, and the RESET pin must be asserted appropriately for device initialization after power up. Note: To pull-up this pin, connect it to the same supply as the LDOI pins. Note: DSP_LDO is not supported on the TMS320C5533 and C5532. An external power supply is used to provide power to CVDD, DSP_LDO_EN must be tied to LDOI, and DSP_LDOO must be left unconnected. The RESET pin must be asserted appropriately for device initialization after power up. (1) (2) (3) (4) (5) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Applies to only TMS320C5535 and TMS320C5534. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 39 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com Table 4-15. Regulators and Power Management Signal Descriptions (continued) SIGNAL NAME USB_LDOO TYPE NO. D13 (1) (2) OTHER (3) S (4) DESCRIPTION USB_LDO output. This output provides a regulated 1.3 V output and up to 25 mA of current (see the ISD parameter in Section 5.3, Electrical Characteristics). For proper device operation, this pin must be connected to a 1 μF ~ 2 μF decoupling capacitor to VSS. For more detailed information, see Section 5.7.2.7, Power-Supply Decoupling. This LDO is intended to supply power to the USB_ VDD1P3, USB_VDDA1P3 pins and not external devices. Note: USB_LDO is not supported on TMS320C5532 . For proper device operation, this pin must be left unconnected on these devices. ANA_LDO output. This output provides a regulated 1.3 V output and up to 4 mA of current (see the ISD parameter in Section 5.3, Electrical Characteristics). ANA_LDOO B9 S For proper device operation, this pin must be connected to an ~ 1.0 μF decoupling capacitor to VSS. For more detailed information, see Section 5.7.2.7, Power-Supply Decoupling. This LDO is intended to supply power to the VDDA_ANA and VDDA_PLL pins and not external devices. Bandgap reference filter signal. For proper device operation, this pin needs to be bypassed with a 0.1 μF capacitor to analog ground (VSSA_ANA). BG_CAP C10 A I/O BG_CAP provides a settling time of 200 ms that must elapse before executing bootloader code. The settling time is used by Timer0. The BG_CAP external capacitor provides filtering for stable reference voltages and currents generated by the bandgap circuit. The bandgap produces the references for use by the System PLL, SAR, and POR circuits. 40 Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 4.2.14 Reserved and No Connects Table 4-16. Reserved and No Connects Signal Descriptions SIGNAL TYPE (1) (2) OTHER (3) (4) DESCRIPTION NAME NO. RSV0 A12 I RSV1 K12 PWR RSV2 L13 PWR RSV3 B12 I - Reserved. For proper device operation, this pin must be tied directly to VSS. RSV4 A11 I - Reserved. For proper device operation, this pin must be tied directly to VSS. RSV5 B11 I - Reserved. For proper device operation, this pin must be tied directly to VSS. RSV6 B13 I - Reserved. For proper device operation, this pin must be directly tied to VSS. RSV7 E1 I Reserved. (Leave unconnected, do not connect to power or ground). RSV8 F1 I Reserved. (Leave unconnected, do not connect to power or ground). Reserved (1) (2) (3) (4) - Reserved. For proper device operation, this pin must be tied directly to VSS. Reserved. For proper device operation, this pin must be tied directly to CVDD. Reserved. For proper device operation, this pin must be tied directly to CVDD. RSV9 G1 I Reserved. (Leave unconnected, do not connect to power or ground). RSV10 H1 I Reserved. (Leave unconnected, do not connect to power or ground). RSV11 E2 I Reserved. (Leave unconnected, do not connect to power or ground). RSV12 G2 I Reserved. (Leave unconnected, do not connect to power or ground). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 41 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com 4.2.15 Supply Voltage Table 4-17. Supply Voltage Signal Descriptions SIGNAL NAME (5) TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION (5) SUPPLY VOLTAGES F2 H2 CVDD D3 G3 1.05-V Digital Core supply voltage (50 MHz) PWR 1.3-V Digital Core supply voltage (100 MHz) M6 M9 N9 C11 D11 K11 M3 DVDDIO L4 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/O power supply for non-RTC I/Os The DVDDIO must always be powered for proper operation. PWR M4 C6 N8 N11 N14 1.05-V thru 1.3-V RTC digital core and RTC oscillator power supply. CVDDRTC B5 Note: The CVDDRTC must always be powered even though RTC is not used. PWR Note: The CVDDRTC cannot be powered by any of the on-chip LDOs and must be externally powered. B4 DVDDRTC C3 PWR VDDA_PLL C7 PWR 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/O power supply for RTC_CLOCKOUT and WAKEUP pins . Note: The DVDDRTC can be tied to ground (VSS) when the RTC_CLKOUT and WAKEUP pins are not permanently used. In this case, the WAKEUP pin must be configured as an output by software (see Table 5-1). see Section 5.2, ROC 1.3-V Analog PLL power supply for the system clock generator (PLLOUT ≤ 120 MHz). This signal can be powered from the ANA_LDOO pin. G13 S see Section 5.2, ROC 3.3 V USB Analog PLL power supply. USB_VDDPLL E12 S see Section 5.2, ROC 1.3-V digital core power supply for USB PHY. USB_VDD1P3 H12 S see Section 5.2, ROC Analog 1.3 V power supply for USB PHY. [For high-speed sensitive analog circuits] USB_VDDA1P3 (1) (2) (3) (4) (5) 42 When the USB peripheral is not used, the USB_VDDPLL signal must be connected to ground (VSS). When the USB peripheral is not used, the USB_VDD1P3 signal must be connected to ground (VSS). When the USB peripheral is not used, the USB_VDDA1P3 signal must be connected to ground (VSS). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal USB signal does not apply to TMS320C5532. Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 Table 4-17. Supply Voltage Signal Descriptions (continued) SIGNAL TYPE (1) (2) OTHER (3) (4) DESCRIPTION (5) NAME (5) NO. G12 S see Section 5.2, ROC Analog 3.3 V power supply for USB PHY. USB_VDDA3P3 E13 S see Section 5.2, ROC 3.3-V power supply for USB oscillator. USB_VDDOSC VDDA_ANA B7 PWR When the USB peripheral is not used, the USB_VDDA3P3 signal must be connected to ground (VSS). When the USB peripheral is not used , USB_VDDOSC must be connected to ground (VSS). 1.3-V supply for power management and 10-bit SAR ADC This signal can be powered from the ANA_LDOO pin. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 43 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com 4.2.16 Ground Table 4-18. Ground Signal Descriptions SIGNAL NAME (5) TYPE NO. (1) (2) OTHER (3) (4) DESCRIPTION (5) P1 B2 B3 E3 F3 H3 K3 VSS D4 E4 GND Ground pins K4 D5 L5 M7 C8 D10 L10 E11 C12 J13 A14 P14 (1) (2) (3) (4) (5) 44 VSSRTC C5 GND see Section 5.2, ROC Ground for RTC oscillator. When using a 32.768-kHz crystal, this pin is a local ground for the crystal and must not be connected to the board ground (See Figure 5-11 and Figure 5-12). When not using RTC and the crystal is not populated on the board, this pin is connected to the board ground. VSSA_PLL A1 GND see Section 5.2, ROC Analog PLL ground for the system clock generator. USB_VSSPLL F13 GND see Section 5.2, ROC USB Analog PLL ground. USB_VSS1P3 K14 GND see Section 5.2, ROC Digital core ground for USB PHY. Analog ground for USB PHY [For high speed sensitive analog circuits]. USB_VSSA1P3 J12 GND see Section 5.2, ROC Analog ground for USB PHY [For high speed sensitive analog circuits]. USB_VSSA3P3 H13 GND see Section 5.2, ROC Analog ground for USB PHY. USB_VSSOSC D12 S see Section 5.2, ROC Ground for USB oscillator. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors. Specifies the operating I/O supply voltage for each signal USB signal does not apply to TMS320C5532. Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 Table 4-18. Ground Signal Descriptions (continued) SIGNAL NAME (5) USB_VSSREF VSSA_ANA NO. F12 B6 C9 TYPE OTHER (3) GND see Section 5.2, ROC (1) (2) 0 (4) DESCRIPTION (5) Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to USB_R1. When the USB peripheral is not used, the USB_VSSREF signal must be connected directly to ground (Vss). Ground pins for power management (POR and Bandgap circuits) and 10-bit SAR ADC Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Copyright © 2011–2014, Texas Instruments Incorporated 45 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 4.3 www.ti.com Pin Multiplexing Extensive pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. The external bus selection register (EBSR) controls all the pin multiplexing functions on the device. This section discusses how to program the external bus selection register (EBSR) to select the desired peripheral functions and pin muxing. See the individual pin mux sections for pin muxing details for a specific muxed pin. After changing any of the pin mux control registers, it will be necessary to reset the peripherals that are affected. 4.3.1 LCD Controller, SPI, UART, I2S2, I2S3, and GP[31:27, 20:12] Pin Multiplexing [EBSR.PPMODE Bits] — C5535 Only The LCD Controller, SPI, UART, I2S2, I2S3, and GPIO signal muxing is determined by the value of the PPMODE bit fields in the External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see Table 4-19 . 46 Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 Table 4-19. LCD Controller (1), SPI, UART, I2S2, I2S3, and GP[31:27, 20:12] Pin Multiplexing PDINHIBR3 REGISTER BIT FIELDS (2) EBSR PPMODE BITS PIN NAME LCD_EN_RDB/SPI_CLK MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 000 (Reset default) 001 010 011 100 101 110 LCD_EN_RDB SPI_CLK LCD_EN_RDB LCD_EN_RDB LCD_EN_RDB LCD_EN_RDB SPI_CLK LCD_D[0]/SPI_RX LCD_D[0] SPI_RX LCD_D[0] LCD_D[0] LCD_D[0] LCD_D[0] SPI_RX LCD_D[1]/SPI_TX LCD_D[1] SPI_TX LCD_D[1] LCD_D[1] LCD_D[1] LCD_D[1] SPI_TX P2PD LCD_D[2]/GP[12] LCD_D[2] GP[12] LCD_D[2] LCD_D[2] LCD_D[2] LCD_D[2] GP[12] P3PD LCD_D[3]/GP[13] LCD_D[3] GP[13] LCD_D[3] LCD_D[3] LCD_D[3] LCD_D[3] GP[13] P4PD LCD_D[4]/GP[14] LCD_D[4] GP[14] LCD_D[4] LCD_D[4] LCD_D[4] LCD_D[4] GP[14] P5PD LCD_D[5]/GP[15] LCD_D[5] GP[15] LCD_D[5] LCD_D[5] LCD_D[5] LCD_D[5] GP[15] P6PD LCD_D[6]/GP[16] LCD_D[6] GP[16] LCD_D[6] LCD_D[6] LCD_D[6] LCD_D[6] GP[16] P7PD LCD_D[7]/GP[17] LCD_D[7] GP[17] LCD_D[7] LCD_D[7] LCD_D[7] LCD_D[7] GP[17] P8PD LCD_D[8]/I2S2_CLK/GP[18]/SPI_CLK LCD_D[8] I2S2_CLK GP[18] SPI_CLK I2S2_CLK SPI_CLK I2S2_CLK P9PD LCD_D[9]/I2S2_FS/GP[19]/SPI_CS0 LCD_D[9] I2S2_FS GP[19] SPI_CS0 I2S2_FS SPI_CS0 I2S2_FS P10PD LCD_D[10]/I2S2_RX/GP[20]/SPI_RX LCD_D[10] I2S2_RX GP[20] SPI_RX I2S2_RX SPI_RX I2S2_RX P11PD LCD_D[11]/I2S2_DX/GP[27]/SPI_TX LCD_D[11] I2S2_DX GP[27] SPI_TX I2S2_DX SPI_TX I2S2_DX P12PD LCD_D[12]/UART_RTS/GP[28]/I2S3_CLK LCD_D[12] UART_RTS GP[28] I2S3_CLK UART_RTS UART_RTS I2S3_CLK P13PD LCD_D[13]/UART_CTS/GP[29]/I2S3_FS LCD_D[13] UART_CTS GP[29] I2S3_FS UART_CTS UART_CTS I2S3_FS P14PD LCD_D[14]/UART_RXD/GP[30]/I2S3_RX LCD_D[14] UART_RXD GP[30] I2S3_RX UART_RXD UART_RXD I2S3_RX P15PD LCD_D[15]/UART_TXD/GP[31]/I2S3_DX LCD_D[15] UART_TXD GP[31] I2S3_DX UART_TXD UART_TXD I2S3_DX LCD_CS0_E0/SPI_CS0 LCD_CS0_E0 SPI_CS0 LCD_CS0_E0 LCD_CS0_E0 LCD_CS0_E0 LCD_CS0_E0 SPI_CS0 LCD_CS1_E1/SPI_CS1 LCD_CS1_E1 SPI_CS1 LCD_CS1_E1 LCD_CS1_E1 LCD_CS1_E1 LCD_CS1_E1 SPI_CS1 LCD_RW_WRB SPI_CS2 LCD_RW_WRB LCD_RW_WRB LCD_RW_WRB LCD_RW_WRB SPI_CS2 LCD_RS SPI_CS3 LCD_RS LCD_RS LCD_RS LCD_RS SPI_CS3 LCD_RW_WRB/SPI_CS2 LCD_RS/SPI_CS3 (1) LCD Controller is supported on only TMS320C5535. For TMS320C5534, C5533, and C5532, the LCD Controller clock gate control bit in PCGCR2 must be disabled for a lower operating power. For a description of disabling the bit, see TMS320C5535/34/33/32 Ultra-Low Power DSP Technical Reference Manual (literature number SPRUH87). (2) The pin names with PDINHIBR3 register bit field references can have the pulldown resistor enabled or disabled via this register. Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 47 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 4.3.2 www.ti.com SD1, I2S1, and GP[11:6] Pin Multiplexing [EBSR.SP1MODE Bits] The SD1, I2S1, and GPIO signal muxing is determined by the value of the SP1MODE bit fields in the External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see Table 4-20. Table 4-20. SD1, I2S1, and GP[11:6] Pin Multiplexing EBSR SP1MODE BITS PDINHIBR1 REGISTER BIT FIELDS (1) (1) PIN NAME MODE 0 MODE 1 MODE 2 00 (Reset default) 01 10 S10PD SD1_CLK/I2S1_CLK/GP[6] SD1_CLK I2S1_CLK GP[6] S11PD SD1_CMD/I2S1_FS/GP[7] SD1_CMD I2S1_FS GP[7] S12PD SD1_D0/I2S1_DX/GP[8] SD1_D0 I2S1_DX GP[8] S13PD SD1_D1/I2S1_RX/GP[9] SD1_D1 I2S1_RX GP[9] S14PD SD1_D2/GP[10] SD1_D2 GP[10] GP[10] S15PD SD1_D3/GP[11] SD1_D3 GP[11] GP[11] The pin names with PDINHIBR1 register bit field references can have the pulldown register enabled or disabled via this register. 4.3.3 SD0, I2S0, and GP[5:0] Pin Multiplexing [EBSR.SP0MODE Bits] The SD0, I2S0, and GPIO signal muxing is determined by the value of the SP0MODE bit fields in the External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see Table 4-21. Table 4-21. SD0, I2S0, and GP[5:0] Pin Multiplexing EBSR SP0MODE BITS PDINHIBR1 REGISTER BIT FIELDS (1) (1) 48 PIN NAME MODE 0 MODE 1 MODE 2 00 (Reset default) 01 10 I2S0_CLK GP[0] S00PD SD0_CLK/I2S0_CLK/GP[0] SD0_CLK S01PD SD0_CMD/I2S0_FS/GP[1] SD0_CMD I2S0_FS GP[1] S02PD SD0_D0/I2S0_DX/GP[2] SD0_D0 I2S0_DX GP[2] S03PD SD0_D1/I2S0_RX/GP[3] SD0_D1 I2S0_RX GP[3] S04PD SD0_D2/GP[4] SD0_D2 GP[4] GP[4] S05PD SD0_D3/GP[5] SD0_D3 GP[5] GP[5] The pin names with PDINHIBR1 register bit field references can have the pulldown register enabled or disabled via this register. Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 5 Specifications For the device maximum operating frequency, see Section 7.1.2, Device Nomenclature. 5.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) (1) Supply voltage ranges: Input and Output voltage ranges: Digital Core (CVDD, CVDDRTC , USB_VDD1P3 ) (2) –0.5 V to 1.7 V I/O, 1.8 V, 2.5 V, 2.75 V, 3.3 V (DVDDIO, DVDDRTC) 3.3 V USB supplies USB PHY (USB_VDDOSC, USB_VDDPLL, USB_VDDA3P3) (2) –0.5 V to 4.2 V LDOI –0.5 V to 4.2 V Analog, 1.3 V (VDDA_PLL, USB_VDDA1P3, VDDA_ANA) (2) –0.5 V to 1.7 V VI I/O, All pins with DVDDIO or USB_VDDOSC or USB_VDDPLL or USB_VDDA3P3 as supply source –0.5 V to 4.2 V VO I/O, All pins with DVDDIO or USB_VDDOSC or USB_VDDPLLor USB_VDDA3P3 as supply source –0.5 V to 4.2 V RTC_XI and RTC_XO –0.5 V to 1.7 V VI and VO, GPAIN[0] –0.5 V to 4.2 V VI and VO, GPAIN[3:1] –0.5 V to 1.7 V VO, BG_CAP –0.5 V to 1.7 V USB_VBUS Input ANA_LDOO, DSP_LDOO, and USB_LDOO Operating case temperature ranges, Tc: (1) (2) (3) -0.5 V to 5.5 V (3) Commercial Temperature (default) –0.5 V to 1.7 V -10°C to 70°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS. DSP_LDOO on TMS320C5533 and C5532 and USB_LDOO on TMS320C5532 are not supported and must be left unconnected. Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Specifications 49 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 5.2 www.ti.com Recommended Operating Conditions CVDD Core Supplies I/O Supplies GND Supply voltage, Digital Core MIN NOM MAX UNIT 50 MHz 0.998 1.05 1.15 V 100 MHz 1.24 1.3 1.43 V 1.43 V CVDDRTC Supply voltage, RTC and RTC OSC USB_VDD1P3 Supply voltage, Digital USB 1.24 1.3 1.43 V USB_VDDA1P3 Supply voltage, 1.3 V Analog USB 1.24 1.3 1.43 V VDDA_ANA Supply voltage, 1.3 V SAR and Pwr Mgmt 1.24 1.3 1.43 V VDDA_PLL Supply voltage, System PLL 1.24 1.3 1.43 V USB_VDDPLL Supply voltage, 3.3 V USB PLL 2.97 3.3 3.63 V Supply voltage, I/O, 3.3 V 2.97 3.3 3.63 V Supply voltage, I/O, 2.75 V 2.48 2.75 3.02 V Supply voltage, I/O, 2.5 V 2.25 2.5 2.75 V DVDDIO DVDDRTC 32.768 kHz 0.998 Supply voltage, I/O, 1.8 V 1.65 1.8 1.98 V USB_VDDOSC Supply voltage, I/O, 3.3 V USB OSC 2.97 3.3 3.63 V USB_VDDA3P3 Supply voltage, I/O, 3.3 V Analog USB PHY 2.97 3.3 3.63 V LDOI Supply voltage, Analog Pwr Mgmt and LDO Inputs 3.6 V VSS Supply ground, Digital I/O VSSRTC Supply ground, RTC USB_VSSOSC Supply ground, USB OSC USB_VSSPLL Supply ground, USB PLL USB_VSSA3P3 Supply ground, 3.3 V Analog USB PHY 0 V USB_VSSA1P3 Supply ground, USB 1.3 V Analog USB PHY USB_VSSREF Supply ground, USB Reference Current VSSA_PLL Supply ground, System PLL USB_VSS1P3 Supply ground, 1.3 V Digital USB PHY VSSA_ANA Supply ground, SAR and Pwr Mgmt 1.8 0 0 VIH (1) High-level input voltage, 3.3, 2.75, 2.5, 1.8 V I/O (except GPAIN[3:0 ] pins) (2) 0.7 * DVDD DVDD + 0.3 V VIL (1) Low-level input voltage, 3.3, 2.75, 2.5, 1.8 V I/O (except GPAIN[3:0 ] pins) (2) -0.3 0.3 * DVDD V Input voltage, GPAIN0 pin (3) -0.3 3.6 V Input voltage, GPAIN[3:1] pins -0.3 VDDA_ANA + 0.3 V -10 70 °C VIN Tc Operating case temperature Default (Commercial) FSYSCLK DSP Operating Frequency (SYSCLK) 1.05 V 0 50 MHz 1.3 V 0 100 MHz (1) (2) (3) 50 DVDD refers to the pin I/O supply voltage. To determine the I/O supply voltage for each pin, see Section 4.2, Signal Descriptions. The I2C pin SDA and SCL do not feature fail-safe I/O buffers. These pin could potentially draw current when the DVDDIO is powered down. Due to the fact that different voltage devices can be connected to I2C bus and the I2C inputs are LVCMOS, the level of logic 0 (low) and logic 1 (high) are not fixed and depend on DVDDIO. The GNDON bit in the SARPINCTRL register must be set to "1" before SAR channels 0, 1, or 2 are enabled via the CHSEL bit in the SARCTRL register, when VIN greater than VDDA_ANA. Specifications Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com 5.3 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted) PARAMETER VOH VOL VLDO IIHPD (6) (7) (6) (7) IIH/ IIL (7) IOH (7) (8) MAX High speed: USB_DN and USB_DP (2) 360 440 UNIT V mV High-level output voltage, 3.3, 2.75, 2.5, 1.8 V I/O (except GPAIN[3:0 ] pins) IO = IOH 0.8 * DVDD V High-level output voltage, GPAIN[3:1] pins IO = IOH 0.8 * VDDA_ANA V Full speed: USB_DN and USB_DP (2) 0.0 0.3 V High speed: USB_DN and USB_DP (2) –10 10 mV Low-level output voltage, 3.3, 2.75, 2.5, 1.8V I/O (except I2C and GPAIN[3:0 ] pins) IO = IOL Low-level output voltage, I2C pins (3) VDD > 2 V, IO L = 3 mA Low-level output voltage, GPAIN[3:0 ] pins IO = IOL 0 0.2 * DVDD V 0.4 V 0.2 * VDDA_ANA V DVDD = 3.3 V 162 mV DVDD = 2.5 V 141 mV DVDD = 1.8 V 122 mV USB_LDOO voltage 1.24 1.3 1.43 V ANA_LDOO voltage 1.24 1.3 1.43 V DSP_LDO_V bit in the LDOCNTL register = 1 1.24 1.3 1.43 V DSP_LDO_V bit in the LDOCNTL register = 0 0.998 1.05 1.15 DSP_LDO shutdown current (5) LDOI = VMIN ANA_LDO shutdown current (5) USB_LDO shutdown current (5) Input current [DC] (except WAKEUP, I2C and GPAIN[3:0 ] pins) Input current [DC] (except WAKEUP, I2C and GPAIN[3:0 ] pins) V 250 mA LDOI = VMIN 4 mA LDOI = VMIN 25 Input only pin, internal pulldown or pullup disabled -5 mA +5 μA DVDD = 3.3 V with internal pullup enabled (8) -59 to -161 μA DVDD = 2.5 V with internal pullup enabled (8) -31 to -93 μA DVDD = 1.8 V with internal pullup enabled (8) -14 to -44 Input only pin, internal pulldown or pullup disabled -5 μA +5 μA DVDD = 3.3 V with internal pulldown enabled (8) 52 to 158 μA DVDD = 2.5 V with internal pulldown enabled (8) 27 to 83 μA DVDD = 1.8 V with internal pulldown enabled (8) 11 to 35 μA VI = VSS to DVDD with internal pullups and pulldowns disabled. -5 All Pins (except USB, CLKOUT, and GPAIN[3:0 ] pins) -4 mA DVDD = 3.3 V -6 mA DVDD = 1.8 V -4 mA High-level output current [DC] CLKOUT pin (1) (2) (3) (4) (5) (6) TYP USB_VDDA3P3 Input current [DC], ALL pins (7) MIN 2.8 DSP_LDOO voltage ISD (1) Full speed: USB_DN and USB_DP (2) Input hysteresis (4) VHYS IILPU TEST CONDITIONS +5 μA For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table. The USB I/Os adhere to the Universal Bus Specification Revision 2.0 (USB2.0 spec). VDD is the voltage to which the I2C bus pullup resistors are connected. Applies to all input pins except WAKEUP, I2C pins, GPAIN[3:0 ], RTC_XI, and USB_MXI. ISD is the amount of current the LDO is ensured to deliver before shutting down to protect itself. II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II indicates the input leakage current and off-state (Hi-Z) output leakage current. When CVDD power is "ON", the pin bus-holders are disabled. For more detailed information, see Section 5.7.2.5, Digital I/O Behavior When Core Power (CVDD) is Down. Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Specifications 51 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com Electrical Characteristics (continued) Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted) PARAMETER TEST CONDITIONS (1) MIN TYP mA (GPAIN0 is open-drain DV = V DDA_ANA = 1.3 and cannot drive high) V, DD Internal Regulator (9) -100 μA All Pins (except USB, CLKOUT, and GPAIN[3:0 ]) (7) Low-level output current [DC] CLKOUT pin GPAIN[3:0 ] IOZ (10) I/O Off-state output current +4 mA DVDD = 3.3 V +6 mA DVDD = 1.8 V +4 mA DVDD = VDDA_ANA = 1.3 V, external regulator +4 mA DVDD = VDDA_ANA = 1.3 V, internal regulator (9) +4 mA μA All Pins (except USB and GPAIN[3:0 ]) -10 +10 GPAIN[3:0 ] pins -10 +10 μA 2.2 mA 1.6 mA 1.4 mA 0.72 mA Supply voltage, I/O, 3.3 V IOLBH (11) Bus Holder pull low current when Supply voltage, I/O, 2.75 V CVDD is powered "OFF" Supply voltage, I/O, 2.5 V Supply voltage, I/O, 1.8 V IOHBH (11) Bus Holder pull high current when CVDD is powered "OFF" UNIT -4 GPAIN[3:1] pins IOL MAX DVDD = VDDA_ANA = 1.3 V, External Regulator (9) Supply voltage, I/O, 3.3 V -1.3 mA Supply voltage, I/O, 2.75 V -0.97 mA Supply voltage, I/O, 2.5 V -0.83 mA Supply voltage, I/O, 1.8 V -0.46 mA (9) When the ANA_LDO supplies VDDA_ANA, it is not recommended to use the GPAIN[3:1] signals for general-purpose outputs (driving high). The ISD parameter of the ANA_LDO is too low to drive any realistic load on the GPAIN[3:1] pins while also supplying the PLL through VDDA_PLL and the SAR through VDDA_ANA . (10) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current. (11) This parameter specifies the maximum strength of the Bus Holder and is needed to calculate the minimum strength of external pull-ups and pull-downs. 52 Specifications Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 www.ti.com SPRS737C – AUGUST 2011 – REVISED APRIL 2014 Electrical Characteristics (continued) Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT Active, CVDD = 1.3 V, DSP clock = 100 MHz, Clock source = RTC on-chip Oscillator 0.22 mW/MHz 0.15 mW/MHz 0.22 mW/MHz 0.14 mW/MHz 0.44 mW 0.26 mW 0.40 mW 0.23 mW 0.28 mW 0.15 mW 0.7 mA Room Temp (25 °C), 75% DMAC + 25% ADD (typical sine wave data switching) Active, CVDD = 1.05 V, DSP clock = 50 MHz, Clock source = RTC on-chip Oscillator Room Temp (25 °C), 75% DMAC + 25% ADD (typical data switching) Active, CVDD = 1.3 V, DSP clock = 100 MHz, Clock source = RTC on-chip Oscillator Room Temp (25 °C), 75% DMAC + 25% NOP (typical sine wave data switching) Active, CVDD = 1.05 V, DSP clock = 50 MHz, Clock source = RTC on-chip Oscillator Room Temp (25 °C), 75% DMAC + 25% NOP (typical data switching) Standby, CVDD = 1.3 V, Master clock disabled, Clock source = RTC on-chip Oscillator P Core (CVDD) supply power Room Temp (25 °C), DARAM and SARAM in active mode Standby, CVDD = 1.05 V, Master clock disabled, Clock source = RTC on-chip Oscillator Room Temp (25 °C), DARAM and SARAM in active mode Standby, CVDD = 1.3 V, Master clock disabled, Clock source = RTC on-chip Oscillator Room Temp (25 °C), DARAM in retention and SARAM in active mode Standby, CVDD = 1.05 V, Master clock disabled, Clock source = RTC on-chip Oscillator Room Temp (25 °C), DARAM in retention and SARAM in active mode Standby, CVDD = 1.3 V, Master clock disabled, Clock source = RTC on-chip Oscillator Room Temp (25 °C), DARAM in active mode and SARAM in retention Standby, CVDD = 1.05 V, Master clock disabled, Clock source = RTC on-chip Oscillator Room Temp (25 °C), DARAM in active mode and SARAM in retention I Analog PLL (VDDA_PLL) supply current SAR Analog (VDDA_ANA) supply current VDDA_PLL = 1.3 V Room Temp (25 °C), Phase detector = 170 kHz, VCO = 100 MHz VDDA_ANA = 1.3 V, SAR clock = 2 MHz, Temp 1 mA (70 °C) CI Input capacitance 4 pF Co Output capacitance 4 pF Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 Specifications 53 TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 5.4 Handling Ratings MIN MAX UNIT –65 150 ºC Human Body Model (HBM) (2) 0 > 1000 V Charged Device Model (CDM) (3) 0 > 250 V Storage temperature range, Tstg (default) ESD Stress Voltage (1) (1) (2) (3) www.ti.com Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by electrostatic discharges into the device. Level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if necessary precautions are taken. Pins listed as 1000 V may actually have higher performance. Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance. Section 5.5 shows the thermal resistance characteristics for the PBGA–ZHH mechanical package. 5.5 Thermal Characteristics °C/W (1) AIR FLOW (m/s) (2) N/A RTJC Junction-to-case 1S0P 12.53 RTJB Junction-to-board 2S2P 38 N/A RTJA Junction-to-free air 2S2P 50 0.00 PsiJT Junction-to-package top 2S2P 0.49 0.00 PsiJB Junction-to-board 2S2P 37.4 0.00 (1) (2) 5.6 These measurements were conducted in a JEDEC-defined 1S0P/2S2P system and will change based on environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. m/s = meters per second Power-On Hours Over Operating Case Temperature Range (Unless Otherwise Noted) Device Operating Life Power-On Hours (POH) (1) 54 (1) DSP Operating Frequency (SYSCLK ) ≤100 MHz