TMS320C6204GHKA200

TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 D High-Performance Fixed-Point Digital D D D D D Signal Processor (DSP) -- TMS320C6204 -- 5-ns Instruction Cycle Time -- 200-MHz Clock Rate -- Eight 32-Bit Instructions/Cycle -- 1600 MIPS C6204 GLW Ball Grid Array (BGA) Package is Pin-Compatible With the C6202/02B/03 GLS BGA Package† VelociTI™ Advanced Very-Long-InstructionWord (VLIW) TMS320C62x™ DSP Core -- Eight Highly Independent Functional Units: -- Six ALUs (32-/40-Bit) -- Two 16-Bit Multipliers (32-Bit Result) -- Load-Store Architecture With 32 32-Bit General-Purpose Registers -- Instruction Packing Reduces Code Size -- All Instructions Conditional Instruction Set Features -- Byte-Addressable (8-, 16-, 32-Bit Data) -- 8-Bit Overflow Protection -- Saturation -- Bit-Field Extract, Set, Clear -- Bit-Counting -- Normalization 1M-Bit On-Chip SRAM -- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) -- 512K-Bit Dual-Access Internal Data (64K Bytes) -- Organized as Two 32K-Byte Blocks for Improved Concurrency 32-Bit External Memory Interface (EMIF) -- Glueless Interface to Synchronous Memories: SDRAM or SBSRAM -- Glueless Interface to Asynchronous Memories: SRAM and EPROM -- 52M-Byte Addressable External Memory Space D Four-Channel Bootloading D D D D D D D D D Direct-Memory-Access (DMA) Controller With an Auxiliary Channel 32-Bit Expansion Bus (XB) -- Glueless/Low-Glue Interface to Popular PCI Bridge Chips -- Glueless/Low-Glue Interface to Popular Synchronous or Asynchronous Microprocessor Buses -- Master/Slave Functionality -- Glueless Interface to Synchronous FIFOs and Asynchronous Peripherals Two Multichannel Buffered Serial Ports (McBSPs) -- Direct Interface to T1/E1, MVIP, SCSA Framers -- ST-Bus-Switching Compatible -- Up to 256 Channels Each -- AC97-Compatible -- Serial-Peripheral Interface (SPI) Compatible (Motorola™) Two 32-Bit General-Purpose Timers Flexible Phase-Locked-Loop (PLL) Clock Generator IEEE-1149.1 (JTAG‡) Boundary-Scan-Compatible 288-Pin MicroStar BGA™ Package (GHK) 340-Pin BGA Package (GLW) 0.15-μm/5-Level Metal Process -- CMOS Technology 3.3-V I/Os, 1.5-V Internal Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI, TMS320C62x, and MicroStar BGA are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. † For more details, see the GLW BGA package bottom view. ‡ IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright © 2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 1 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 Table of Contents GHK and GLW BGA packages (bottom view) . . . . . . . . . . 3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 C62x device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 functional and CPU (DSP core) block diagram . . . . . . . . . 7 CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . 8 memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . 11 DMA channel synchronization events . . . . . . . . . . . . . . . 16 interrupt sources and interrupt selector . . . . . . . . . . . . . . 17 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . 18 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-down mode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature ranges . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions . . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 21 31 34 35 36 38 39 39 parameter measurement information . . . . . . . . . . . . . . . 41 input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 45 synchronous-burst memory timing . . . . . . . . . . . . . . . . . 48 synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . 50 HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 57 expansion bus synchronous FIFO timing . . . . . . . . . . . 58 expansion bus asynchronous peripheral timing . . . . . . 60 expansion bus synchronous host-port timing . . . . . . . . 63 expansion bus asynchronous host-port timing . . . . . . . 69 XHOLD/XHOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . 71 multichannel buffered serial port timing . . . . . . . . . . . . . 73 DMAC, timer, power-down timing . . . . . . . . . . . . . . . . . . 85 JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 thermal/mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . 89 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 GHK and GLW BGA packages (bottom view) GHK 288-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW) W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 17 18 19 GLW 340-PIN BGA PACKAGE (BOTTOM VIEW) AB Y V T P M K H F D B AA W U R N L J G E C A 3 1 2 5 4 9 7 6 8 10 11 13 15 17 19 21 12 14 16 18 20 22 The C6204 GLW BGA package is pin-compatible with the C6202/02B/03 GLS package except that the inner row of balls (which are additional power and ground pins) are removed for the C6204 GLW package. These balls are NOT applicable for the C6204 devices 340-pin GLW BGA package. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 3 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 description The TMS320C62x™ DSPs (including the TMS320C6204 device) compose the fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6204 (C6204) device is based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making the C6204 an excellent choice for multichannel and multifunction applications. With performance of up to 1600 million instructions per second (MIPS) at a clock rate of 200 MHz, the C6204 offers cost-effective solutions to high-performance DSP-programming challenges. The C6204 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6204 can produce two multiply-accumulates (MACs) per cycle for a total of 400 million MACs per second (MMACS). The C6204 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The C6204 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped as program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a 32-bit expansion bus (XB) that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The C6204 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution. device characteristics Table 1 provides an overview of the TMS320C6204, TMS320C6202/02B, and the TMS320C6203 pin-compatible C62x™ DSPs. The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc. This data sheet primarily focuses on the functionality of the TMS320C6204 device although it also identifies to the user the pin-compatibility of the 6204 GLW and the C6202/02B and C6203 GLS BGA packages. For the functionality information on the TMS320C6202/02B devices, see the TMS320C6202, TMS320C6202B Fixed-Point Digital Signal Processors Data Sheet (literature number SPRS104). For the functionality information on the TMS320C6203 device, see the TMS320C6203 Fixed-Point Digital Signal Processor Data Sheet (literature number SPRS086). And for more details on the C6000™ DSP device part numbers and part numbering, see Table 14 and Figure 4. TMS320C6000, C62x, and C6000 are trademarks of Texas Instruments. Windows is a registered trademark of Microsoft Corporation. 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 device characteristics (continued) Table 1. Characteristics of the Pin-Compatible TMS320C6204 and C6202/02B/03B/03C DSPs HARDWARE FEATURES C6204 C6202 C6202B C6203B/C EMIF √ √ √ √ DMA 4-Channel With Throughput Enhancements 4-Channel 4-Channel With Throughput Enhancements 4-Channel With Throughput Enhancements Expansion Bus √ √ √ √ McBSPs 2 3 3 3 32-Bit Timers 2 2 2 2 Size (Bytes) 64K 256K 256K 384K Organization 1 Block: 64K-Byte Cache/Mapped Program Block 0: 128K-Byte Mapped Program Block 1: 128K-Byte Cache/Mapped Program Block 0: 128K-Byte Mapped Program Block 1: 128K-Byte Cache/Mapped Program Block 0: 256K-Byte Mapped Program Block 1: 128K-Byte Cache/Mapped Program Size (Bytes) 64K 128K 128K 512K Internal Data Memory Organization 2 Blocks: Four 16-Bit Banks per Block 50/50 Split 2 Blocks: Four 16-Bit Banks per Block 50/50 Split 2 Blocks: Four 16-Bit Banks per Block 50/50 Split 2 Blocks: Four 16-Bit Banks per Block 50/50 Split CPU ID + Rev ID Control Status Register (CSR.[31:16]) 0x0003 0x0002 0x0003 0x0003 Frequency MHz 200 200, 250 250 250, 300 (03B) 300 (03C) Cycle Time ns 5 ns (C6204-200) 4 ns (C6202-250) 5 ns (C6202-200) 4 ns (C6202B-250) 3.33 ns (C6203C-300) 3.33 ns (C6203B-300) 4 ns (C6203B-250) Core (V) 1.5 1.8 1.5 1.2 (C6203C) 1.5 (C6203B) 1.7 (C6203BGLS Only) I/O (V) 3.3 3.3 3.3 3.3 x1, x4, x8, x10 (GJL Pkg) x1, x4, x8, x10 (GJL Pkg) All PLL Options (GLS Pkg) All PLL Options (GLS Pkg) Peripherals Internal Program Memory Voltage PLL Options BGA Packages CLKIN frequency multiplier [Bypass (x1), x4, x6, x7, x8, x9, x10, and x11] x1, x4 (Both Pkgs) x1, x4 (Both Pkgs) 27 x 27 mm -- 352-pin GJL 352-pin GJL 352-pin GNZ 18 x 18 mm 340-pin GLW 384-pin GLS 384-pin GLS 384-pin GLS 384-pin GNY 16 x 16 mm 288-pin GHK -- -- -- 0.15 μm 0.18 μm 0.15 μm 0.15 μm PD PD PP PD Process Technology μm Product Status Product Preview (PP) Advance Information (AI) Production Data (PD) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 5 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 C62x™ device compatibility The TMS320C6202, C6202B, C6203, and C6204 devices are pin-compatible; thus, making new system designs easier and providing faster time to market. The following list summarizes the C62x™ DSP device characteristic differences: D Core Supply Voltage (1.8 V versus 1.7 V, 1.5 V, 1.2 V) The C6202 device core supply voltage is 1.8 V while the C6202B, C6203B, C6204 devices have core supply voltages of 1.5 V. The C6203B device (GLS package only) has a 1.7-V core supply voltage, and the C6203C device has a core supply voltage of 1.2 V. D PLL Options Availability Table 1 identifies the available PLL multiply factors [e.g., CLKIN x1 (PLL bypassed), x4, etc.] for each of the C62x™ DSP devices. For additional details on the PLL clock module and specific options for the C6204 device, see the Clock PLL section of this data sheet. For additional details on the PLL clock module and specific options for the C6202/02B/03 devices, see the Clock PLL sections of the TMS320C6202, TMS320C6202B Fixed-Point Digital Signal Processors Data Sheet (literature number SPRS104) and the TMS320C6203 Fixed-Point Digital Signal Processor Data Sheet (literature number SPRS086). D On-Chip Memory Size The C6202/02B, C6203, and C6204 devices have different on-chip program memory and data memory sizes (see Table 1). D McBSPs The C6204 device has two McBSPs on-chip while the C6202, C6202B, C6203 devices have three McBSPs on-chip. For a more detailed discussion on migration concerns, and similarities/differences between the C6202, C6202B, C6203, and C6204 devices, see the How to Begin Development and Migrate Across the TMS320C6202/6202B/6203/6204 DSPs Application Report (literature number SPRA603). 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 functional and CPU (DSP core) block diagram C6204 Digital Signal Processor SDRAM or SBSRAM SRAM Program Access/Cache Controller 32 External Memory Interface (EMIF) ROM/FLASH Internal Program Memory 64K I/O Devices C62x CPU (DSP Core) Timer 0 Instruction Fetch Timer 1 I/O Devices HOST CONNECTION Master /Slave TI PCI2040 Power PC 683xx 960 32 Expansion Bus (XB) 32-Bit Control Logic Instruction Decode Data Path B Data Path A A Register File Multichannel Buffered Serial Port 1 .L1 DMA Bus Interrupt Selector Synchronous FIFOs Instruction Dispatch Multichannel Buffered Serial Port 0 Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs Control Registers .S1 .M1 .D1 Test B Register File .D2 .M2 .S2 In-Circuit Emulation .L2 Interrupt Control Peripheral Control Bus DMA 4-Ch With Throughput PLL (x1, x4) POST OFFICE BOX 1443 Data Access Controller PowerDown Logic • HOUSTON, TEXAS 77251--1443 Internal Data Memory 64K Boot Configuration 7 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 CPU (DSP core) description The CPU fetches VelociTI™ advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI™ VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C62x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional and CPU (DSP core) block diagram and Figure 1]. The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the 256-bit-wide fetch-packet boundary, the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 CPU (DSP core) description (continued) src1 src2 .L1 dst long dst long src ST1 long src long dst dst .S1 src1 Data Path A 8 8 32 8 Register File A (A0--A15) src2 .M1 dst src1 src2 LD1 DA1 .D1 dst src1 src2 2X 1X DA2 .D2 src2 src1 dst LD2 src2 .M2 src1 dst src2 Data Path B src1 dst long dst long src Register File B (B0--B15) .S2 ST2 long src long dst dst .L2 src2 8 32 8 8 src1 Control Register File Figure 1. TMS320C62x CPU (DSP Core) Data Paths POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 9 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 memory map summary Table 2 shows the memory map address ranges of the C6204 device. The C6204 device has the capability of a MAP 0 or MAP 1 memory block configuration. The maps differ in that MAP 0 has external memory mapped at address 0x0000 0000 and MAP 1 has internal memory mapped at address 0x0000 0000. These memory block configurations are set up at reset by the boot configuration pins (generically called BOOTMODE[4:0]). For the C6204 device, the BOOTMODE configuration is handled, at reset, by the expansion bus module (specifically XD[4:0] pins). For more detailed information on the C6204 device settings, which include the device boot mode configuration at reset and other device-specific configurations, see TMS320C6201/C670x DSP Boot Modes and Configuration (literature number SPRU642). Table 2. TMS320C6204 Memory Map Summary MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE MAP 0 MAP 1 External Memory Interface (EMIF) CE0 Internal Program RAM 64K 0000 0000 – 0000 FFFF EMIF CE0 Reserved 4M – 64K 0001 0000 – 003F FFFF EMIF CE0 EMIF CE0 12M 0040 0000 – 00FF FFFF EMIF CE1 EMIF CE0 4M 0100 0000 – 013F FFFF Internal Program RAM EMIF CE1 64K 0140 0000 – 0140 FFFF EMIF CE1 Reserved 10 4M – 64K 0141 0000 – 017F FFFF EMIF Registers 256K 0180 0000 – 0183 FFFF DMA Controller Registers 256K 0184 0000 – 0187 FFFF Expansion Bus (XBus) Registers 256K 0188 0000 – 018B FFFF McBSP 0 Registers 256K 018C 0000 – 018F FFFF McBSP 1 Registers 256K 0190 0000 – 0193 FFFF Timer 0 Registers 256K 0194 0000 – 0197 FFFF Timer 1 Registers 256K 0198 0000 – 019B FFFF Interrupt Selector Registers 256K 019C 0000 – 019F FFFF Reserved 6M 01A0 0000 – 01FF FFFF EMIF CE2 16M 0200 0000 – 02FF FFFF EMIF CE3 16M 0300 0000 – 03FF FFFF Reserved 1G – 64M 0400 0000 – 3FFF FFFF XBus XCE0 256M 4000 0000 – 4FFF FFFF XBus XCE1 256M 5000 0000 – 5FFF FFFF XBus XCE2 256M 6000 0000 – 6FFF FFFF XBus XCE3 256M 7000 0000 – 7FFF FFFF Internal Data RAM 64K 8000 0000 – 8000 FFFF Reserved 2G – 64K 8001 0000 – FFFF FFFF POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 peripheral register descriptions Table 3 through Table 11 identify the peripheral registers for the C6204 device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names, and their descriptions, see the peripheral reference guide referenced in TMS320C6000 Peripherals Reference Guide (literature number SPRU190). Table 3. EMIF Registers HEX ADDRESS RANGE ACRONYM 0180 0000 GBLCTL EMIF global control REGISTER NAME COMMENTS 0180 0004 CECTL1 EMIF CE1 space control External or internal; dependant on MAP0 or MAP1 configuration (selected byt the MAP bit in the EMIF GBLCTL register 0180 0008 CECTL0 EMIF CE0 space control External or internal; dependant on MAP0 or MAP1 configuration (selected byt the MAP bit in the EMIF GBLCTL register 0180 000C -- 0180 0010 CECTL2 EMIF CE2 space control Corresponds to EMIF CE2 memory space: [0200 0000 -- 02FF FFFF] 0180 0014 CECTL3 EMIF CE3 space control Corresponds to EMIF CE3 memory space: [0300 0000 -- 03FF FFFF] 0180 0018 SDCTL EMIF SDRAM control EMIF SDRAM refresh control Reserved 0180 001C SDTIM 0180 0020 -- 0180 0054 -- Reserved 0180 0058 -- 0183 FFFF – Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 11 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 peripheral register descriptions (continued) Table 4. DMA Registers 12 HEX ADDRESS RANGE ACRONYM 0184 0000 PRICTL0 DMA channel 0 primary control REGISTER NAME 0184 0004 PRICTL2 DMA channel 2 primary control 0184 0008 SECCTL0 DMA channel 0 secondary control 0184 000C SECCTL2 DMA channel 2 secondary control 0184 0010 SRC0 DMA channel 0 source address 0184 0014 SRC2 DMA channel 2 source address 0184 0018 DST0 DMA channel 0 destination address 0184 001C DST2 DMA channel 2 destination address 0184 0020 XFRCNT0 DMA channel 0 transfer counter 0184 0024 XFRCNT2 DMA channel 2 transfer counter 0184 0028 GBLCNTA DMA global count reload register A 0184 002C GBLCNTB DMA global count reload register B 0184 0030 GBLIDXA DMA global index register A 0184 0034 GBLIDXB DMA global index register B 0184 0038 GBLADDRA DMA global address register A 0184 003C GBLADDRB DMA global address register B 0184 0040 PRICTL1 DMA channel 1 primary control 0184 0044 PRICTL3 DMA channel 3 primary control 0184 0048 SECCTL1 DMA channel 1 secondary control 0184 004C SECCTL3 DMA channel 3 secondary control 0184 0050 SRC1 DMA channel 1 source address 0184 0054 SRC3 DMA channel 3 source address 0184 0058 DST1 DMA channel 1 destination address 0184 005C DST3 DMA channel 3 destination address 0184 0060 XFRCNT1 DMA channel 1 transfer counter 0184 0064 XFRCNT3 DMA channel 3 transfer counter 0184 0068 GBLADDRC DMA global address register C 0184 006C GBLADDRD DMA global address register D 0184 0070 AUXCTL DMA auxiliary control register 0184 0074 -- 0187 FFFF – Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 peripheral register descriptions (continued) Table 5. Expansion Bus (XBUS) Registers HEX ADDRESS RANGE ACRONYM 0188 0000 XBGC REGISTER NAME COMMENTS 0188 0004 XCECTL1 XCE1 space control register Corresponds to XBus XCE0 memory space: [4000 0000 -- 4FFF FFFF] 0188 0008 XCECTL0 XCE0 space control register Corresponds to XBus XCE1 memory space: [5000 0000 -- 5FFF FFFF] 0188 000C XBHC Expansion bus host port interface control register DSP read/write access only 0188 0010 XCECTL2 XCE2 space control register Corresponds to XBus XCE2 memory space: [6000 0000 -- 6FFF FFFF] 0188 0014 XCECTL3 XCE3 space control register Corresponds to XBus XCE3 memory space: [7000 0000 -- 7FFF FFFF] Expansion bus global control register 0188 0018 -- Reserved 0188 001C -- Reserved 0188 0020 XBIMA Expansion bus internal master address register DSP read/write access only 0188 0024 XBEA Expansion bus external address register DSP read/write access only 0188 0028 -- 018B FFFF -- -- XBISA -- XBD Reserved Expansion bus internal slave address Expansion bus data Table 6. Interrupt Selector Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 019C 0000 MUXH Interrupt multiplexer high Selects which interrupts drive CPU interrupts 10--15 (INT10--INT15) 019C 0004 MUXL Interrupt multiplexer low Selects which interrupts drive CPU interrupts 4--9 (INT04--INT09) 019C 0008 EXTPOL External interrupt polarity Sets the polarity of the external interrupts (EXT_INT4--EXT_INT7) 019C 000C -- 019C 01FF -- 019C 0200 PDCTL 019C 0204 -- 019F FFFF -- Reserved Peripheral power-down control register Reserved Table 7. Peripheral Power-Down Control Register HEX ADDRESS RANGE ACRONYM 019C 0200 PDCTL REGISTER NAME Peripheral power-down control register POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 13 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 peripheral register descriptions (continued) Table 8. McBSP 0 Registers HEX ADDRESS RANGE 018C 0000 ACRONYM REGISTER NAME DRR0 McBSP0 data receive register 018C 0004 DXR0 McBSP0 data transmit register 018C 0008 SPCR0 018C 000C RCR0 McBSP0 receive control register 018C 0010 XCR0 McBSP0 transmit control register 018C 0014 SRGR0 018C 0018 MCR0 McBSP0 multichannel control register 018C 001C RCER0 McBSP0 receive channel enable register 018C 0020 XCER0 McBSP0 transmit channel enable register 018C 0024 PCR0 018C 0028 -- 018F FFFF – COMMENTS The CPU and DMA/EDMA controller can only read this register; they cannot write to it. McBSP0 serial port control register McBSP0 sample rate generator register McBSP0 pin control register Reserved Table 9. McBSP 1 Registers 14 HEX ADDRESS RANGE ACRONYM REGISTER NAME 0190 0000 DRR1 Data receive register 0190 0004 DXR1 McBSP1 data transmit register 0190 0008 SPCR1 0190 000C RCR1 McBSP1 receive control register 0190 0010 XCR1 McBSP1 transmit control register 0190 0014 SRGR1 McBSP1 serial port control register McBSP1 sample rate generator register 0190 0018 MCR1 McBSP1 multichannel control register 0190 001C RCER1 McBSP1 receive channel enable register 0190 0020 XCER1 McBSP1 transmit channel enable register 0190 0024 PCR1 0190 0028 -- 0193 FFFF – McBSP1 pin control register Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 COMMENTS The CPU and DMA/EDMA controller can only read this register; they cannot write to it. TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 peripheral register descriptions (continued) Table 10. Timer 0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0194 0000 CTL0 Timer 0 control register Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. 0194 0004 PRD0 Timer 0 period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 0194 0008 CNT0 Timer 0 counter register Contains the current value of the incrementing counter. 0194 000C -- 0197 FFFF -- Reserved Table 11. Timer 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0198 0000 CTL1 Timer 1 control register Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. 0198 0004 PRD1 Timer 1 period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 0198 0008 CNT1 Timer 1 counter register Contains the current value of the incrementing counter. 0198 000C -- 019B FFFF -- Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 15 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 DMA channel synchronization events The C6204 DMA supports up to four independent programmable DMA channels. The four main DMA channels can be read/write synchronized based on the events shown in Table 12. Selection of these events is done via the RSYNC and WSYNC fields in the Primary Control registers (PRICTLx) of the specific DMA channel. The default setting is “no synchronization” for all four DMA channels. For more detailed information on the DMA module, associated channels, and event-synchronization, see TMS320C620x/C670x DSP Program and Data Memory Controller / Direct Memory Access (DMA) Controller Reference Guide (literature number SPRU190). Table 12. TMS320C6204 DMA Synchronization Events† † DMA EVENT NUMBER (BINARY) EVENT NAME 00000 None No Synchronization (default) 00001 TINT0 Timer 0 interrupt 00010 TINT1 Timer 1 interrupt EVENT DESCRIPTION 00011 SD_INT 00100 EXT_INT4 EMIF SDRAM timer interrupt External interrupt pin 4 00101 EXT_INT5 External interrupt pin 5 00110 EXT_INT6 External interrupt pin 6 00111 EXT_INT7 External interrupt pin 7 01000 DMA_INT0 DMA channel 0 interrupt 01001 DMA_INT1 DMA channel 1 interrupt 01010 DMA_INT2 DMA channel 2 interrupt 01011 DMA_INT3 DMA channel 3 interrupt 01100 XEVT0 McBSP0 transmit event 01101 REVT0 McBSP0 receive event 01110 XEVT1 McBSP1 transmit event 01111 REVT1 McBSP1 receive event 10000 DSP_INT Host processor-to-DSP interrupt 10001 -- 11111 Reserved Reserved. Not used. For synchronization event selection, the PRICTLx register for the specific DMA channel needs to be programmed with a binary event number identified in this table. The default setting is “no synchronization” for all four DMA channels. 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 interrupt sources and interrupt selector The C62x DSP core supports 16 prioritized interrupts, which are listed in Table 13. The highest-priority interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts (INT_00--INT_03) are non-maskable and fixed. The remaining interrupts (INT_04--INT_15) are maskable and default to the interrupt source specified in Table 13. The interrupt source for interrupts 4--15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004). Table 13. C6204 DSP Interrupts CPU INTERRUPT NUMBER INTERRUPT SELECTOR CONTROL REGISTER SELECTOR VALUE (BINARY) INTERRUPT EVENT INT_00† -- -- RESET INT_01† -- -- NMI INT_02† -- -- Reserved Reserved. Do not use. INT_03† -- -- Reserved Reserved. Do not use. INT_04‡ MUXL[4:0] 00100 EXT_INT4 External interrupt pin 4 INT_05‡ MUXL[9:5] 00101 EXT_INT5 External interrupt pin 5 INT_06‡ MUXL[14:10] 00110 EXT_INT6 External interrupt pin 6 INT_07‡ MUXL[20:16] 00111 EXT_INT7 External interrupt pin 7 INT_08‡ MUXL[25:21] 01000 DMA_INT0 DMA channel 0 interrupt INT_09‡ MUXL[30:26] 01001 DMA_INT1 DMA channel 1 interrupt INT_10‡ MUXH[4:0] 00011 SD_INT INT_11‡ MUXH[9:5] 01010 DMA_INT2 DMA channel 2 interrupt INT_12‡ MUXH[14:10] 01011 DMA_INT3 DMA channel 3 interrupt INT_13‡ MUXH[20:16] 00000 DSP_INT INT_14‡ MUXH[25:21] 00001 TINT0 Timer 0 interrupt INT_15‡ MUXH[30:26] 00010 TINT1 Timer 1 interrupt -- -- 01100 XINT0 McBSP0 transmit interrupt -- -- 01101 RINT0 McBSP0 receive interrupt -- -- 01110 XINT1 McBSP1 transmit interrupt -- -- 01111 RINT1 McBSP1 receive interrupt -- -- 10000 -- 11111 Reserved INTERRUPT SOURCE EMIF SDRAM timer interrupt Host-port interface (HPI)-to-DSP interrupt Reserved. Do not use. † Interrupts INT_00 through INT_03 are non-maskable and fixed. ‡ Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields. Table 13 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and selection, see TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 17 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 signal groups description CLKIN CLKOUT2 CLKOUT1 CLKMODE0 CLKMODE1 CLKMODE2 PLLV PLLG PLLF TMS TDO TDI TCK TRST EMU1 EMU0 Clock/PLL Reset and Interrupts IEEE Standard 1149.1 (JTAG) Emulation RESET NMI EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 IACK INUM3 INUM2 INUM1 INUM0 DMA Status DMAC3 DMAC2 DMAC1 DMAC0 Power-Down Status PD RSV11 RSV10 RSV9 RSV8 RSV7 RSV6 RSV5 Reserved RSV4 RSV3 RSV2 RSV1 RSV0 Control/Status Figure 2. CPU (DSP Core) Signals 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 signal groups description (continued) ED[31:0] 32 CE3 CE2 CE1 CE0 EA[21:2] BE3 BE2 BE1 BE0 TOUT1 TINP1 Asynchronous Memory Control Data Memory Map Space Select 20 Synchronous Memory Control Word Address HOLD/ HOLDA Byte Enables ARE AOE AWE ARDY SDA10 SDRAS/SSOE SDCAS/SSADS SDWE/SSWE HOLD HOLDA EMIF (External Memory Interface) Timer 1 Timer 0 TOUT0 TINP0 Timers McBSP1 McBSP0 CLKX1 FSX1 DX1 Transmit Transmit CLKX0 FSX0 DX0 CLKR1 FSR1 DR1 Receive Receive CLKR0 FSR0 DR0 CLKS1 Clock Clock CLKS0 McBSPs (Multichannel Buffered Serial Ports) Figure 3. Peripheral Signals POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 19 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 signal groups description (continued) XD[31:0] XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2 XRDY 32 Data Byte-Enable Control/ Address Control Clocks I/O Port Control XHOLD XHOLDA XFCLK XOE XRE XWE/XWAIT XCE3 XCE2 XCE1 XCE0 Arbitration Expansion Bus Host Interface Control Figure 3. Peripheral Signals (Continued) 20 XCLKIN POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 XCS XAS XCNTL XW/R XBLAST XBOFF TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 Signal Descriptions SIGNAL NAME PIN NO. GHK GLW† TYPE‡ DESCRIPTION CLOCK/PLL CLKIN J3 B10 I Clock Input CLKOUT1 T18 Y18 O Clock output at full device speed CLKOUT2 T19 AB19 O CLKMODE0 L3 B12 I Clock output at half of device speed - Used for synchronous memory interface Clock mode selects Selects what multiply factors of the input clock frequency the CPU frequency equals. For more details on CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this data sheet. sheet Note: For the C6204 GLW package, the CLKMODE2 (A14) and CLKMODE1 (A9) pins are internally unconnected. CLKMODE1 -- A9 I CLKMODE2 -- A14 I PLLV§ K5 C11 A¶ PLL analog VCC connection for the low-pass filter PLLG§ L2 C12 A¶ PLL analog GND connection for the low-pass filter A11 A¶ PLL low-pass filter connection to external components and a bypass capacitor PLLF§ L1 JTAG EMULATION TMS E17 Y5 I TDO D19 AA4 O/Z JTAG test-port mode select (features an internal pullup) TDI D18 Y4 I JTAG test-port data in (features an internal pullup) TCK D17 AB2 I JTAG test-port clock TRST C19 AA3 I JTAG test-port reset (features an internal pulldown) EMU1 E18 AA5 I/O/Z Emulation pin 1, pullup with a dedicated 20-kΩ resistor# EMU0 F15 AB4 I/O/Z Emulation pin 0, pullup with a dedicated 20-kΩ resistor# JTAG test-port data out RESET AND INTERRUPTS † ‡ § ¶ # RESET E8 J3 I NMI A8 K2 I EXT_INT7 B15 U2 EXT_INT6 C15 U3 EXT_INT5 A16 W1 EXT_INT4 B16 V2 IACK A15 V1 INUM3 F12 R3 INUM2 A14 T1 INUM1 B14 T2 INUM0 C14 T3 Device reset Nonmaskable interrupt - Edge-driven (rising edge) External interrupts I O - Edge-driven - Polarity independently selected via the external interrupt polarity register bits (EXTPOL.[3:0]) Interrupt acknowledge for all active interrupts serviced by the CPU A ti interrupt Active i t t id identification tifi ti number b O - Valid during IACK for all active interrupts (not just external) Encoding order follows the interrupt-service interrupt service fetch-packet fetch packet ordering The C6204 GLW BGA package is a subset of the GLS package (C6202/02B/03), with the inner row of core supply voltage (CVDD) and ground (VSS) pins removed (see the GLW BGA package bottom view). I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground PLLV, PLLG, and PLLF are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins. A = Analog Signal (PLL Filter) For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-kΩ resistor. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 21 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GHK GLW† TYPE‡ DESCRIPTION POWER-DOWN STATUS PD B18 Y2 O Power-down modes 2 or 3 (active if high) XCLKIN H5 C8 I Expansion bus synchronous host interface clock input O Expansion bus FIFO interface clock output EXPANSION BUS XFCLK G2 A8 XD31 M1 C13 XD30 M2 A13 XD29 M3 C14 XD28 N1 B14 XD27 N2 B15 XD26 N3 C15 XD25 P1 A15 XD24 P2 B16 XD23 N5 C16 XD22 R1 A17 XD21 R2 B17 Expansion p bus data XD20 P5 C17 - Used for transfer of data, address, and control XD19 T1 B18 - XD18 T2 A19 XD17 U1 C18 Also controls initialization of DSP modes and expansion bus at reset via pullup/ pulldown resistors p (Note: Reserved boot configuration fields should be pulled down.) XD16 T3 B19 XD15 U2 C19 XD14 V1 B20 XD13 V2 A21 XD12 W2 C21 XD11 U4 D20 XD10 W3 B22 XD9 V4 D21 XD8 W4 E20 XD7 U5 E21 XD6 V5 D22 XD5 W5 F20 XD4 U6 F21 XD3 V6 E22 XD2 V3 G20 XD1 W6 G21 XD0 U7 G22 I/O/Z XD[30:16] XD13 XD12 XD11 XD10 XD9 XD8 XD[4:0] Others ---------- XCE[3:0] memory type XBLAST polarity p y XW/R polarity l i Asynchronous or synchronous host operation Arbitration mode (internal or external) FIFO mode Littl Little endian/big di /bi endian di Boot mode Reserved † The C6204 GLW BGA package is a subset of the GLS package (C6202/02B/03), with the inner row of core supply voltage (CVDD) and ground (VSS) pins removed (see the GLW BGA package bottom view). ‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE‡ DESCRIPTION GHK GLW† XCE3 B4 D2 XCE2 A3 B1 XCE1 C4 D3 XCE0 B3 C2 XBE3/XA5 E3 C5 XBE2/XA4 E2 A4 XBE1/XA3 E1 B5 XBE0/XA2 F3 C6 XOE F5 A6 O/Z Expansion bus I/O port output-enable XRE F1 C7 O/Z Expansion bus I/O port read-enable XWE/XWAIT G3 B7 O/Z Expansion bus I/O port write-enable and host-port wait signals XCS H1 C9 I XAS F2 B6 I/O/Z XCNTL H2 B9 I XW/R H3 B8 I/O/Z Expansion bus host-port write/read enable. XW/R polarity is selected at reset. XRDY D2 C4 I/O/Z Expansion bus host-port ready (active low) and I/O port ready (active high) XBLAST D1 B4 I/O/Z Expansion bus host-port burst last-polarity selected at reset XBOFF J1 A10 I XHOLD C2 A2 I/O/Z Expansion bus hold request XHOLDA C1 B3 I/O/Z Expansion bus hold acknowledge EXPANSION BUS (CONTINUED) E Expansion i bus b I/O portt memory space enables bl O/Z - Enabled by bits 28, 29, and 30 of the word address Only one asserted during any I/O port data access E Expansion i bus b multiplexed lti l d byte-enable b t bl control/address t l/ dd signals i l I/O/Z - Act as byte-enable for host port operation Act as address for I/O port operation Expansion bus host-port chip-select input Expansion bus host-port address strobe Expansion bus host control. XCNTL selects between expansion bus address or data register. Expansion bus back off EMIF -- CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY CE3 V18 Y21 CE2 U17 W20 CE1 W18 AA22 CE0 V17 W21 BE3 U16 V20 BE2 W17 V21 BE1 V16 W22 BE0 W16 U20 M Memory space enables bl O/Z - Enabled by bits 24 and 25 of the word address Only one asserted during any external data access Byte-enable control O/Z - Decoded from the two lowest bits of the internal address Byte-write Byte write enables for most types of memory Can be directly connected to SDRAM read and write mask signal (SDQM) † The C6204 GLW BGA package is a subset of the GLS package (C6202/02B/03), with the inner row of core supply voltage (CVDD) and ground (VSS) pins removed (see the GLW BGA package bottom view). ‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 23 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GHK GLW† EA21 V7 H20 EA20 W7 H21 EA19 U8 H22 EA18 V8 J20 EA17 W8 J21 EA16 W9 K21 EA15 V9 K20 EA14 U9 K22 EA13 W10 L21 EA12 V10 L20 EA11 U10 L22 EA10 W11 M20 EA9 V11 M21 EA8 U11 N22 EA7 R11 N20 EA6 W12 N21 EA5 U12 P21 TYPE‡ DESCRIPTION EMIF -- ADDRESS EA4 R12 P20 EA3 W13 R22 EA2 V13 R21 ED31 F14 Y6 ED30 E19 AA6 ED29 F17 AB6 ED28 G15 Y7 ED27 F18 AA7 ED26 F19 AB8 ED25 G17 Y8 ED24 G18 AA8 ED23 G19 AA9 ED22 H17 Y9 ED21 H18 AB10 ED20 H19 Y10 ED19 J18 AA10 ED18 J19 AA11 ED17 K15 Y11 ED16 K17 AB12 ED15 K18 Y12 ED14 K19 AA12 O/Z External address (word address) EMIF -- DATA I/O/Z External data † The C6204 GLW BGA package is a subset of the GLS package (C6202/02B/03), with the inner row of core supply voltage (CVDD) and ground (VSS) pins removed (see the GLW BGA package bottom view). ‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE‡ DESCRIPTION GHK GLW† ED13 L17 AA13 ED12 L18 Y13 ED11 L19 AB13 ED10 M19 Y14 ED9 M18 AA14 ED8 M17 AA15 ED7 N19 Y15 ED6 P19 AB15 ED5 N15 AA16 ED4 P18 Y16 ED3 P17 AB17 ED2 R19 AA17 ED1 R18 Y17 ED0 R17 AA18 ARE U14 T21 O/Z Asynchronous memory read-enable AOE W14 R20 O/Z Asynchronous memory output-enable AWE V14 T22 O/Z Asynchronous memory write-enable ARDY W15 T20 I Asynchronous memory ready input EMIF -- DATA (CONTINUED) I/O/Z External data EMIF -- ASYNCHRONOUS MEMORY CONTROL EMIF -- SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL SDA10 U19 AA19 O/Z SDRAM address 10 (separate for deactivate command) SDCAS/SSADS V19 AB21 O/Z SDRAM column-address strobe/SBSRAM address strobe SDRAS/SSOE U18 Y19 O/Z SDRAM row-address strobe/SBSRAM output-enable SDWE/SSWE T17 AA20 O/Z SDRAM write-enable/SBSRAM write-enable EMIF -- BUS ARBITRATION HOLD P14 V22 I Hold request from the host HOLDA V15 U21 O Hold-request-acknowledge to the host TOUT0 E5 D1 O Timer 0 or general-purpose output TINP0 C5 E2 I Timer 0 or general-purpose input TOUT1 A5 F2 O Timer 1 or general-purpose output TINP1 B5 F3 I Timer 1 or general-purpose input DMAC3 A17 V3 TIMER 0 TIMER 1 DMA ACTION COMPLETE STATUS DMAC2 B17 W2 DMAC1 C16 AA1 DMAC0 A18 W3 O DMA action complete † The C6204 GLW BGA package is a subset of the GLS package (C6202/02B/03), with the inner row of core supply voltage (CVDD) and ground (VSS) pins removed (see the GLW BGA package bottom view). ‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 25 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GHK GLW† TYPE‡ DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 A12 K3 I CLKR0 B9 L2 I/O/Z External clock source (as opposed to internal) Receive clock CLKX0 C9 K1 I/O/Z Transmit clock DR0 A10 M2 I Receive data DX0 B10 M3 O/Z Transmit data FSR0 E10 M1 I/O/Z Receive frame sync FSX0 A9 L3 I/O/Z Transmit frame sync MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1 C6 E1 I CLKR1 B6 G2 I/O/Z External clock source (as opposed to internal) Receive clock CLKX1 E6 G3 I/O/Z Transmit clock DR1 A7 H1 I Receive data DX1 B7 H2 O/Z Transmit data FSR1 C7 H3 I/O/Z Receive frame sync FSX1 A6 G1 I/O/Z Transmit frame sync RESERVED FOR TEST RSV0 C8 J2 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV1 A4 E3 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV2 K3 B11 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV3 L5 B13 O Reserved (leave unconnected, do not connect to power or ground) RSV4 B19 C10 O Reserved (leave unconnected, do not connect to power or ground) RSV5 C17 N1 I Reserved (leave unconnected) RSV6 D3 N2 I/O Reserved (leave unconnected) RSV7 K2 N3 I/O Reserved (leave unconnected) RSV8 J17 R2 I Reserved (leave unconnected) RSV9 N18 R1 O Reserved (leave unconnected) RSV10 C11 P3 I/O Reserved (leave unconnected) RSV11 -- P2 I/O Reserved (leave unconnected) [For C6204 GLW packages only] † The C6204 GLW BGA package is a subset of the GLS package (C6202/02B/03), with the inner row of core supply voltage (CVDD) and ground (VSS) pins removed (see the GLW BGA package bottom view). ‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GHK GLW† A2 A3 TYPE‡ DESCRIPTION SUPPLY VOLTAGE PINS DVDD B1 A7 B2 A16 C3 A20 E7 D4 E9 D6 E11 D7 E13 D9 F6 D10 G1 D13 H14 D14 J6 D16 K14 D17 L6 D19 L15 F1 M14 F4 P3 F19 P15 F22 R3 G4 R6 G19 R7 J4 R8 J19 R9 K4 R10 K19 R13 L1 R14 M22 U3 N4 U15 N19 -- P4 -- P19 -- T4 -- T19 -- U1 -- U4 -- U19 -- U22 -- W4 -- W6 -- W7 S 3.3-V 3.3 V supply voltage (I/O) † The C6204 GLW BGA package is a subset of the GLS package (C6202/02B/03), with the inner row of core supply voltage (CVDD) and ground (VSS) pins removed (see the GLW BGA package bottom view). ‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 27 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GHK GLW† -- W9 -- W10 -- W13 -- W14 -- W16 -- W17 -- W19 -- AB5 -- AB9 -- AB14 -- AB18 B12 E7 TYPE‡ DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) DVDD CVDD E14 E8 F9 E10 F10 E11 G5 E12 H15 E13 J2 E15 J5 E16 J15 G5 M5 G18 M15 H5 N17 H18 P6 K5 P9 K18 P12 L5 U13 L18 -- M5 -- M18 -- N5 -- N18 -- R5 -- R18 -- T5 -- T18 -- V7 -- V8 -- V10 -- V11 S 3.3-V 3.3 V supply voltage (I/O) S 1 5 V supply voltage (core) 1.5-V † The C6204 GLW BGA package is a subset of the GLS package (C6202/02B/03), with the inner row of core supply voltage (CVDD) and ground (VSS) pins removed (see the GLW BGA package bottom view). ‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GHK GLW† -- V12 -- V13 -- V15 -- V16 A11 A1 TYPE‡ DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) CVDD S 1 5 V supply voltage (core) 1.5-V GROUND PINS VSS A13 A5 B8 A12 B11 A18 B13 A22 C10 B2 C12 B21 C13 C1 C18 C3 E12 C20 G7 C22 G8 D5 G9 D8 G10 D11 G11 D12 G12 D15 G13 D18 H7 E4 H8 E5 H9 E6 H10 E9 H11 E14 H12 E17 H13 E18 J7 E19 J8 F5 J9 F18 J10 H4 J11 H19 J12 J1 J13 J5 K1 J18 K7 J22 GND Ground pins † The C6204 GLW BGA package is a subset of the GLS package (C6202/02B/03), with the inner row of core supply voltage (CVDD) and ground (VSS) pins removed (see the GLW BGA package bottom view). ‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 29 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GHK GLW† K8 L4 TYPE‡ DESCRIPTION GROUND PINS (CONTINUED) VSS K9 L19 K10 M4 K11 M19 K12 P1 K13 P5 L7 P18 L8 P22 L9 R4 L10 R19 L11 U5 L12 U18 L13 V4 M7 V5 M8 V6 M9 V9 M10 V14 M11 V17 M12 V18 M13 V19 N7 W5 N8 W8 N9 W11 N10 W12 N11 W15 N12 W18 N13 Y1 V12 Y3 -- Y20 -- Y22 -- AA2 -- AA21 -- AB1 -- AB3 -- AB7 -- AB11 -- AB16 -- AB20 -- AB22 GND Ground pins † The C6204 GLW BGA package is a subset of the GLS package (C6202/02B/03), with the inner row of core supply voltage (CVDD) and ground (VSS) pins removed (see the GLW BGA package bottom view). ‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 development support TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000™ DSP-based applications: Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE) including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug) EVM (Evaluation Module) The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320™ DSP family member devices, including documentation. See this document for further information on TMS320™ DSP documentation or any TMS320™ DSP support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320™ DSP-related products from other companies in the industry. To receive TMS320™ DSP literature, contact the Literature Response Center at 800/477-8924. For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and select “Find Development Tools”. For device-specific tools, under “Semiconductor Products” select “Digital Signal Processors”, choose a product family, and select the particular DSP device. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 31 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320™ DSP devices and support tools. Each TMS320™ DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device’s electrical specifications TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GLW), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -200 is 200 MHz). Table 14 lists the device orderable part numbers (P/Ns) and Figure 4 provides a legend for reading the complete device name for any TMS320C6000™ DSP family member. For more information on the C6204 device orderable P/Ns, visit the Texas Instruments web site on the Worldwide web at http://www.ti.com URL, or contact the nearest TI field sales office or authorized distributor. 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 device and development-support tool nomenclature (continued) Table 14. TMS320C6204 Device Part Numbers (P/Ns) and Ordering Information DEVICE ORDERABLE P/N DEVICE SPEED CVDD (CORE VOLTAGE) DVDD (I/O VOLTAGE) OPERATING CASE TEMPERATURE RANGE TMS320C6204GHK 200 MHz/1600 MIPS 1.5 V 3.3 V 0_C to 90_C TMS320C6204GLW 200 MHz/1600 MIPS 1.5 V 3.3 V 0_C to 90_C TMS 320 C 6204 PREFIX TMX = Experimental device TMP = Prototype device TMS = Qualified device SMX= Experimental device, MIL SMJ = MIL-PRF-38535, QML SM = High Rel (non-38535) GLW ( ) 200 DEVICE SPEED RANGE 100 MHz 120 MHz 150 MHz 167 MHz PACKAGE TYPE† GFN = 256-pin plastic BGA GGP = 352-pin plastic BGA GJC = 352-pin plastic BGA GJL = 352-pin plastic BGA GLS = 384-pin plastic BGA GLW = 340-pin plastic BGA GNY = 384-pin plastic BGA GNZ = 352-pin plastic BGA GLZ = 532-pin plastic BGA GHK = 288-pin plastic MicroStar BGAt TECHNOLOGY C = CMOS DEVICE C6000 DSP: 6201 6202 6202B 6203B 6203C BGA = QFP = 400 MHz 500 MHz 600 MHz TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C) Blank = 0°C to 90°C, commercial temperature A = --40°C to 105°C, extended temperature DEVICE FAMILY 320 = TMS320t DSP family † 200 MHz 233 MHz 250 MHz 300 MHz 6204 6205 6211 6211B 6414 6415 6416 6701 6711 6711B 6712 6713 Ball Grid Array Quad Flatpack Figure 4. TMS320C6000™ DSP Platform Device Nomenclature (Including the TMS320C6204) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 33 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 documentation support Extensive documentation supports all TMS320™ DSP family devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000™ DSP devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000™ DSP core (CPU) architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) briefly describes the functionality of the peripherals available on the C6000™ DSP platform of devices, such as the 64-/32-/16-bit external memory interfaces (EMIFs), 32-/16-bit host-port interfaces (HPIs), multichannel buffered serial ports (McBSPs), direct memory access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XB), peripheral component interconnect (PCI), clocking and phase-locked loop (PLL); and power-down modes. The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x™/C67x™ devices, associated development tools, and third-party support. The tools support documentation is electronically available within the Code Composer Studio™ IDE. For a complete listing of the latest C6000™ DSP documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). The How to Begin Development and Migrate Across the TMS320C6202/6202B/6203/6204 DSPs application report (literature number SPRA603) describes the migration concerns and identifies the similarities and differences between the C6202, C6202B, C6203, and C6204 C6000™ DSP devices. C67x is a trademark of Texas Instruments. 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 clock PLL Most of the internal C6204 clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock. To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5, Table 15, and Table 16 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Figure 6 shows the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode. To minimize the clock jitter, a single clean power supply should power both the C6204 device and the external clock oscillator circuit. Noise coupling into PLLF directly impacts PLL clock jitter. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and output clocks electricals section. 3.3V EMI Filter PLLV C3 10 mF C4 Internal to C6204 PLL CLKMODE0 CLKMODE1† CLKMODE2† PLLMULT PLLCLK 0.1 mF CLKIN CLKIN LOOP FILTER 1 PLLF (For the PLL Options and CLKMODE pins setup, see Table 15 and Table 16) C2 C1 CPU CLOCK PLLG 0 R1 † CLKMODE1 and CLKMODE2 pins are not applicable to the GHK package. NOTES: A. Keep the lead length and the number of vias between pin PLLF, pin PLLG, R1, C1, and C2 to a minimum. In addition, place all PLL components (R1, C1, C2, C3, C4, and EMI Filter) as close to the C6000™ DSP device as possible. Best performance is achieved with the PLL components on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4, and the EMI Filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U. Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode 3.3V PLLV CLKMODE0 CLKMODE1† CLKMODE2† Internal to C6204 PLLMULT PLL PLLCLK CLKIN CLKIN LOOP FILTER 1 CPU CLOCK PLLG PLLF 0 † CLKMODE1 and CLKMODE2 pins are not applicable to the GHK package. NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF to PLLG. B. The 3.3-V supply for PLLV must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. Figure 6. External PLL Circuitry for x1 (Bypass) PLL Mode Only POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 35 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 clock PLL (continued) Table 15. GHK/GLW Packages PLL Multiply and Bypass (x1) Options† GHK PACKAGE -- 16 X 16 MM MICROSTAR BGA™ GLW PACKAGE -- 18 X 18 MM BGA BIT (PIN NO.) Value CLKMODE2 (A14) [GLW ONLY] CLKMODE1 (A9) [GLW ONLY] CLKMODE0 (L3) [GHK] CLKMODE0 (B12) [GLW] PLL MULTIPLY FACTOR‡ X (Don’t Cares) X 0 Bypass (x1) X X 1 x4 † For the GLW package only, the CLKMODE2 (A14) and CLKMODE1 (A9) pins are internally unconnected. These pins are not applicable to the GHK package. ‡ f(CPU Clock) = f(CLKIN) x (PLL mode) Table 16. PLL Component Selection Table§ § CLKMODE CLKIN RANGE (MHz) CPU CLOCK FREQUENCY (CLKOUT1) RANGE (MHz) CLKOUT2 RANGE (MHz) R1 [±1%] (Ω) C1 [±10%] (nF) C2 [±10%] (pF) TYPICAL LOCK TIME (μs) x4 32.5--50 130--200 65--100 60.4 27 560 75 Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 μs, the maximum value may be as long as 250 μs. power-down mode logic Figure 7 shows the power-down mode logic on the C6204. CLKOUT1 TMS320C6204 Internal Clock Tree PD1 PD2 PD PowerDown Logic Clock PLL (pin) IFR IER PWRD Internal Peripheral CSR CPU PD3 CLKIN RESET Figure 7. Power-Down Mode Logic† 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 Internal Peripheral TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 triggering, wake-up, and effects The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15--10) of the control status register (CSR). The PWRD field of the CSR is shown in Figure 8 and described in Table 17. When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when “writing” to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). 31 16 15 14 13 12 11 10 Reserved Enable or Non-Enabled Interrupt Wake Enabled Interrupt Wake PD3 PD2 PD1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 9 8 0 Legend: R/W--x = Read/write reset value NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). Figure 8. PWRD Field of the CSR Register Power-down mode PD1 takes effect eight to nine clock cycles after the instruction that sets the PWRD bits in the CSR. If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first, then the program execution returns to the instruction where PD1 took effect. The GIE bit in CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order for the interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect upon PD1 mode termination by an enabled interrupt. PD2 and PD3 modes can only be aborted by device reset. Table 17 summarizes all the power-down modes. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 37 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 triggering, wake-up, and effects (continued) Table 17. Characteristics of the Power-Down Modes PRWD FIELD (BITS 15--10) POWER-DOWN MODE WAKE-UP METHOD 000000 No power-down — † — 001001 PD1 Wake by an enabled interrupt 010001 PD1 Wake by an enabled or non-enabled interrupt 011010 PD2† 011100 PD3† All others Reserved EFFECT ON CHIP’S OPERATION CPU halted (except for the interrupt logic) Power-down Power down mode blocks the internal clock inputs at the boundary of the CPU, preventing most of the CPU’s logic from switching. During PD1, DMA transactions can proceed between peripherals and internal memory. Wake by a device reset Output clock from PLL is halted, stopping the internal clock structure from switching and resulting in the entire chip being halted. All register and internal RAM contents are preserved. All functional I/O “freeze” in the last state when the PLL clock is turned off. Wake by a device reset Input clock to the PLL stops generating clocks. All register and internal RAM contents are preserved. All functional I/O “freeze” in the last state when the PLL clock is turned off. Following reset, the PLL needs time to re-lock, just as it does following power-up. Wake-up from PD3 takes longer than wake-up from PD2 because the PLL needs to be re-locked. — — When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions, peripherals will not operate according to specifications. power-supply sequencing TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. system-level design considerations System-level design considerations, such as bus contention, may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board. power-supply design considerations For systems using the C6000™ DSP platform of devices, the core supply may be required to provide in excess of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the PLL disabled, as many as five external clock cycle pulses may be required to stop this extra current draw. A normal current state returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing the amount of time between the core supply power up and the I/O supply power up can minimize the effects of this current draw. 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 power-supply design considerations (continued) A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the Using the TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also be used to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the logic within the DSP. Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C6000™ platform of DSPs, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors. absolute maximum ratings over operating case temperature ranges (unless otherwise noted)† Supply voltage range, CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -- 0.3 V to 2.3 V Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4 V Operating case temperature ranges, TC:(default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C (A version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --40_C to105_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --65_C to 150_C Temperature cycle range, (1000-cycle performance): (GHK package) . . . . . . . . . . . . . . . . . . . --55_C to 125_C (GLW package) . . . . . . . . . . . . . . . . . . . . --40_C to125_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX UNIT CVDD Supply voltage, Core 1.43 1.5 1.57 V DVDD Supply voltage, I/O 3.14 3.3 3.46 V VSS Supply ground 0 0 0 V VIH High-level input voltage 2 VIL Low-level input voltage 0.8 V IOH High-level output current --8 mA IOL Low-level output current 8 mA TC Operating case temperature 0 90 _C --40 105 _C (default) (A version) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 V 39 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER ‡ § TEST CONDITIONS MIN TYP MAX High-level output voltage DVDD = MIN, IOH = MAX VOL Low-level output voltage DVDD = MIN, IOL = MAX 0.6 V II Input current‡ VI = VSS to DVDD ±10 uA IOZ Off-state output current VO = DVDD or 0 V ±10 uA IDD2V Supply current, CPU + CPU memory IDD2V Supply current, peripherals§ pins§ access§ 2.4 UNIT VOH V CVDD = NOM, CPU clock = 200 MHz 290 mA CVDD = NOM, CPU clock = 200 MHz 240 mA DVDD = NOM, CPU clock = 200 MHz 100 IDD3V Supply current, I/O Ci Input capacitance 10 mA pF Co Output capacitance 10 pF TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown. Measured with average activity (50% high / 50% low power). For more details on CPU, peripheral, and I/O activity, see the TMS320C6000 Power Consumption Summary application report (literature number SPRA486). 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics 50 Ω Vcomm Output Under Test CT IOH Where: IOL IOH Vcomm CT = = = = 2 mA 2 mA 1.5 V 15--30-pF typical load-circuit capacitance Figure 9. Test Load Circuit for AC Timing Measurements signal transition levels All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels. Vref = 1.5 V Figure 10. Input and Output Voltage Reference Levels for ac Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, and VOL MAX and VOH MIN for output clocks. Vref = VIH MIN (or VOH MIN) Vref = VIL MAX (or VOL MAX) Figure 11. Rise and Fall Transition Time Voltage Reference Levels POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 41 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN†‡§ (see Figure 12) -200 PLL Mode x4 NO. MIN MAX PLL Mode x1 (BYPASS) MIN UNIT MAX 1 tc(CLKIN) Cycle time, CLKIN 5*M 5 ns 2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.45C ns 3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 4 tt(CLKIN) Transition time, CLKIN 0.45C ns 5 0.6 ns † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. M = the PLL multiplier factor (x4). For more details, see the Clock PLL section of this data sheet. § C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. ‡ 1 4 2 CLKIN 3 4 Figure 12. CLKIN Timings timing requirements for XCLKIN¶ (see Figure 13) -200 NO NO. ¶ MIN UNIT 1 tc(XCLKIN) Cycle time, XCLKIN 4P ns 2 tw(XCLKINH) Pulse duration, XCLKIN high 1.8P ns 3 tw(XCLKINL) Pulse duration, XCLKIN low 1.8P ns P = 1/CPU clock frequency in nanoseconds (ns). 1 2 XCLKIN 3 Figure 13. XCLKIN Timings 42 MAX POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for CLKOUT1†‡§ (see Figure 14) -200 NO. CLKMODE = X4 PARAMETER CLKMODE = X1 UNIT MIN MAX MIN MAX P -- 0.7 P + 0.7 P -- 0.7 P + 0.7 ns 1 tc(CKO1) Cycle time, CLKOUT1 2 tw(CKO1H) Pulse duration, CLKOUT1 high (P/2) -- 0.7 (P/2 ) + 0.7 PH -- 0.7 PH + 0.7 ns 3 tw(CKO1L) Pulse duration, CLKOUT1 low (P/2) -- 0.7 (P/2 ) + 0.7 PL -- 0.7 PL + 0.7 ns 4 tt(CKO1) Transition time, CLKOUT1 0.6 ns 0.6 † The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. § P = 1/CPU clock frequency in ns. ‡ 1 4 2 CLKOUT1 3 4 Figure 14. CLKOUT1 Timings switching characteristics over recommended operating conditions for CLKOUT2†§ (see Figure 15) NO NO. -200 PARAMETER MIN MAX UNIT 2 tw(CKO2H) Pulse duration, CLKOUT2 high P -- 0.7 P + 0.7 ns 3 tw(CKO2L) Pulse duration, CLKOUT2 low P -- 0.7 P + 0.7 ns 4 tt(CKO2) Transition time, CLKOUT2 0.6 ns † The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. § P = 1/CPU clock frequency in ns. 1 4 2 CLKOUT2 3 4 Figure 15. CLKOUT2 Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 43 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for XFCLK†‡ (see Figure 16) NO NO. -200 PARAMETER MAX D * P -- 0.7 D * P + 0.7 ns 1 tc(XFCK) Cycle time, XFCLK 2 tw(XFCKH) Pulse duration, XFCLK high (D/2) * P -- 0.7 (D/2) * P + 0.7 ns 3 tw(XFCKL) Pulse duration, XFCLK low (D/2) * P -- 0.7 (D/2) * P + 0.7 ns 4 tt(CKO2) Transition time, XFCLK 0.6 ns † P = 1/CPU clock frequency in ns. ‡ D = 8, 6, 4, or 2; FIFO clock divide ratio, user-programmable 1 4 2 XFCLK 3 4 Figure 16. XFCLK Timings 44 UNIT MIN POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles†‡§¶ (see Figure 17 -- Figure 20) -200 NO NO. MIN MAX UNIT 3 tsu(EDV-AREH) Setup time, EDx valid before ARE high 1.5 ns 4 th(AREH-EDV) Hold time, EDx valid after ARE high 3.5 ns 6 tsu(ARDYH-AREL) Setup time, ARDY high before ARE low --[(RST -- 3) * P -- 6] ns 7 th(AREL-ARDYH) Hold time, ARDY high after ARE low (RST -- 3) * P + 3 ns --[(RST -- 3) * P -- 6] ns (RST -- 3) * P + 3 ns 2P ns --[(WST -- 3) * P -- 6] ns (WST -- 3) * P + 3 ns --[(WST -- 3) * P -- 6] ns (WST -- 3) * P + 3 ns 9 tsu(ARDYL-AREL) Setup time, ARDY low before ARE low 10 th(AREL-ARDYL) Hold time, ARDY low after ARE low 11 tw(ARDYH) Pulse width, ARDY high 15 tsu(ARDYH-AWEL) Setup time, ARDY high before AWE low 16 th(AWEL-ARDYH) Hold time, ARDY high after AWE low 18 tsu(ARDYL-AWEL) Setup time, ARDY low before AWE low 19 th(AWEL-ARDYL) Hold time, ARDY low after AWE low † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input. ‡ RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the EMIF CE space control registers. § P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width. switching characteristics over recommended operating conditions for asynchronous memory cycles‡§¶# (see Figure 17 -- Figure 20) NO NO. -200 PARAMETER MIN TYP MAX UNIT 1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS * P -- 2 ns 2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid RH * P -- 2 ns 5 tw(AREL) Pulse width, ARE low 8 td(ARDYH-AREH) Delay time, ARDY high to ARE high 12 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS * P -- 2 13 toh(AWEH-SELIV) Output hold time, AWE high to select signals invalid WH * P -- 2 14 tw(AWEL) Pulse width, AWE low 17 td(ARDYH-AWEH) Delay time, ARDY high to AWE high RST * P 3P ns 4P + 5 ns ns WST * P 3P ns ns 4P + 5 ns ‡ RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the EMIF CE space control registers. § P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width. # Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional 7P ns following the end of the cycle. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 45 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Hold = 2 CLKOUT1 1 2 1 2 1 2 CEx BE[3:0] EA[21:2] 3 4 ED[31:0] 1 2 AOE 6 7 ARE 5 AWE ARDY Figure 17. Asynchronous Memory Read Timing (ARDY Not Used) Setup = 2 Strobe = 3 Not Ready Hold = 2 CLKOUT1 CEx BE[3:0] EA[21:2] 1 2 1 2 1 2 3 4 ED[31:0] 1 2 AOE 8 10 9 ARE AWE 11 ARDY Figure 18. Asynchronous Memory Read Timing (ARDY Used) 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Hold = 2 CLKOUT1 CEx 12 13 12 13 12 13 12 13 BE[3:0] EA[21:2] ED[31:0] AOE 15 ARE 16 14 AWE ARDY Figure 19. Asynchronous Memory Write Timing (ARDY Not Used) Setup = 2 Strobe = 3 Not Ready Hold = 2 CLKOUT1 12 13 12 13 12 13 12 13 CEx BE[3:0] EA[21:2] ED[31:0] AOE ARE 17 18 19 AWE 11 ARDY Figure 20. Asynchronous Memory Write Timing (ARDY Used) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 47 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (see Figure 21) -200 NO NO. MIN MAX UNIT 7 tsu(EDV-CKO2H) Setup time, read EDx valid before CLKOUT2 high 2.5 ns 8 th(CKO2H-EDV) Hold time, read EDx valid after CLKOUT2 high 1.5 ns switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles†‡ (see Figure 21 and Figure 22) NO NO. PARAMETER 1 tosu(CEV-CKO2H) Output setup time, CEx valid before CLKOUT2 high 2 toh(CKO2H-CEV) Output hold time, CEx valid after CLKOUT2 high 3 tosu(BEV-CKO2H) Output setup time, BEx valid before CLKOUT2 high 4 toh(CKO2H-BEIV) Output hold time, BEx invalid after CLKOUT2 high 5 tosu(EAV-CKO2H) Output setup time, EAx valid before CLKOUT2 high 6 toh(CKO2H-EAIV) Output hold time, EAx invalid after CLKOUT2 high 9 tosu(ADSV-CKO2H) Output setup time, SDCAS/SSADS valid before CLKOUT2 high 10 toh(CKO2H-ADSV) Output hold time, SDCAS/SSADS valid after CLKOUT2 high -200 MIN MAX UNIT P -- 0.8 ns P -- 4 ns P -- 0.8 ns P -- 4 ns P -- 0.8 ns P -- 4 ns P -- 0.8 ns P -- 4 ns 11 tosu(OEV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2 high P -- 0.8 ns 12 toh(CKO2H-OEV) Output hold time, SDRAS/SSOE valid after CLKOUT2 high P -- 4 ns 13 tosu(EDV-CKO2H) Output setup time, EDx valid before CLKOUT2 high§ P -- 1 ns 14 toh(CKO2H-EDIV) Output hold time, EDx invalid after CLKOUT2 high 15 tosu(WEV-CKO2H) Output setup time, SDWE/SSWE valid before CLKOUT2 high 16 toh(CKO2H-WEV) Output hold time, SDWE/SSWE valid after CLKOUT2 high † P -- 4 ns P -- 0.8 ns P -- 4 ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. § For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time. 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) CLKOUT2 1 2 CEx BE[3:0] 3 BE1 BE2 BE3 BE4 4 EA[21:2] 5 A1 A2 A3 A4 6 7 Q1 ED[31:0] 8 Q2 Q3 9 Q4 10 SDCAS/SSADS† 11 12 SDRAS/SSOE† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. Figure 21. SBSRAM Read Timing CLKOUT2 1 2 CEx BE[3:0] 3 BE1 BE2 BE3 BE4 4 EA[21:2] 5 A1 A2 A3 A4 Q1 Q2 Q3 Q4 6 13 ED[31:0] 14 9 10 15 16 SDCAS/SSADS† SDRAS/SSOE† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. Figure 22. SBSRAM Write Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 49 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 23) -200 NO NO. MIN 7 tsu(EDV-CKO2H) Setup time, read EDx valid before CLKOUT2 high 8 th(CKO2H-EDV) Hold time, read EDx valid after CLKOUT2 high MAX UNIT 1.25 ns 3 ns switching characteristics over recommended operating conditions for synchronous DRAM cycles†‡ (see Figure 23--Figure 28) NO NO. -200 PARAMETER MIN 1 tosu(CEV-CKO2H) Output setup time, CEx valid before CLKOUT2 high 2 toh(CKO2H-CEV) Output hold time, CEx valid after CLKOUT2 high 3 tosu(BEV-CKO2H) Output setup time, BEx valid before CLKOUT2 high 4 toh(CKO2H-BEIV) Output hold time, BEx invalid after CLKOUT2 high 5 tosu(EAV-CKO2H) Output setup time, EAx valid before CLKOUT2 high 6 toh(CKO2H-EAIV) Output hold time, EAx invalid after CLKOUT2 high 9 tosu(CASV-CKO2H) Output setup time, SDCAS/SSADS valid before CLKOUT2 high 10 toh(CKO2H-CASV) Output hold time, SDCAS/SSADS valid after CLKOUT2 high high§ 11 tosu(EDV-CKO2H) Output setup time, EDx valid before CLKOUT2 12 toh(CKO2H-EDIV) Output hold time, EDx invalid after CLKOUT2 high 13 tosu(WEV-CKO2H) Output setup time, SDWE/SSWE valid before CLKOUT2 high 14 toh(CKO2H-WEV) Output hold time, SDWE/SSWE valid after CLKOUT2 high 15 tosu(SDA10V-CKO2H) Output setup time, SDA10 valid before CLKOUT2 high 16 toh(CKO2H-SDA10IV) Output hold time, SDA10 invalid after CLKOUT2 high 17 tosu(RASV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2 high 18 toh(CKO2H-RASV) Output hold time, SDRAS/SSOE valid after CLKOUT2 high † MAX UNIT P -- 1 ns P -- 3.5 ns P -- 1 ns P -- 3.5 ns P -- 1 ns P -- 3.5 ns P -- 1 ns P -- 3.5 ns P -- 3 ns P -- 3.5 ns P -- 1 ns P -- 3.5 ns P -- 1 ns P -- 3.5 ns P -- 1 ns P -- 3.5 ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. § For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time. ‡ 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 SYNCHRONOUS DRAM TIMING (CONTINUED) READ READ READ CLKOUT2 1 2 CEx 3 BE[3:0] 5 EA[15:2] 4 BE1 BE2 CA2 CA3 BE3 6 CA1 7 8 D1 ED[31:0] 15 16 9 10 D2 D3 SDA10 SDRAS/SSOE† SDCAS/SSADS† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 23. Three SDRAM READ Commands WRITE WRITE WRITE CLKOUT2 1 2 CEx 3 BE[3:0] 4 BE1 5 EA[15:2] BE3 CA2 CA3 D2 D3 6 CA1 11 D1 ED[31:0] BE2 12 15 16 9 10 13 14 SDA10 SDRAS/SSOE† SDCAS/SSADS† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 24. Three SDRAM WRT Commands POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 51 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 SYNCHRONOUS DRAM TIMING (CONTINUED) ACTV CLKOUT2 1 2 CEx BE[3:0] 5 Bank Activate/Row Address EA[15:2] ED[31:0] 15 Row Address SDA10 17 18 SDRAS/SSOE† SDCAS/SSADS† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 25. SDRAM ACTV Command DCAB CLKOUT2 1 2 15 16 17 18 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS/SSOE† SDCAS/SSADS† 13 14 SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 26. SDRAM DCAB Command 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 SYNCHRONOUS DRAM TIMING (CONTINUED) REFR CLKOUT2 1 2 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 17 18 SDRAS/SSOE† 9 10 SDCAS/SSADS† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 27. SDRAM REFR Command MRS CLKOUT2 1 2 5 6 CEx BE[3:0] EA[15:2] MRS Value ED[31:0] SDA10 17 18 9 10 13 14 SDRAS/SSOE† SDCAS/SSADS† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 28. SDRAM MRS Command POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 53 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles† (see Figure 29) -200 NO NO. 3 † MIN toh(HOLDAL-HOLDL) Output hold time, HOLD low after HOLDA low MAX P UNIT ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles†‡ (see Figure 29) NO NO. -200 PARAMETER 1 td(HOLDL-EMHZ) Delay time, HOLD low to EMIF Bus high impedance 2 td(EMHZ-HOLDAL) Delay time, EMIF Bus high impedance to HOLDA low 4 td(HOLDH-EMLZ) Delay time, HOLD high to EMIF Bus low impedance 5 td(EMLZ-HOLDAH) Delay time, EMIF Bus low impedance to HOLDA high UNIT MIN MAX 4P § ns 0 2P ns 3P 7P ns 0 2P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10. § All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. ‡ External Requestor Owns Bus DSP Owns Bus DSP Owns Bus 3 HOLD 2 5 HOLDA EMIF Bus† † 1 4 C6204 C6204 EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10. Figure 29. HOLD/HOLDA Timing 54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 RESET TIMING timing requirements for reset† (see Figure 30) -200 NO NO. MIN 1 tw(RST) 10 tsu(XD) 11 th(XD) MAX UNIT Width of the RESET pulse (PLL stable)‡ 10P ns Width of the RESET pulse (PLL needs to sync up)§ 250 μs Setup time, XD configuration bits valid before RESET high¶ 5P ns Hold time, XD configuration bits valid after RESET high¶ 5P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4 when CLKIN and PLL are stable. § This parameter applies to CLKMODE x4 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the Clock PLL circuit. The PLL requires a minimum of 250 μs to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. ¶ XD[31:0] are the boot configuration pins during device reset. ‡ switching characteristics over recommended operating conditions during reset†# (see Figure 30) NO NO. PARAMETER 2 td(RSTL-CKO2IV) Delay time, RESET low to CLKOUT2 invalid 3 td(RSTH-CKO2V) Delay time, RESET high to CLKOUT2 valid 4 td(RSTL-HIGHIV) Delay time, RESET low to high group invalid 5 td(RSTH-HIGHV) Delay time, RESET high to high group valid 6 td(RSTL-LOWIV) Delay time, RESET low to low group invalid 7 td(RSTH-LOWV) Delay time, RESET high to low group valid 8 td(RSTL-ZHZ) Delay time, RESET low to Z group high impedance 9 td(RSTH-ZV) Delay time, RESET high to Z group valid -200 MIN MAX P UNIT ns 4P P ns ns 4P P ns ns 4P P ns ns 4P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. # High group consists of: XFCLK, HOLDA Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, SDA10, CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD, and XHOLDA. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 55 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 RESET TIMING (CONTINUED) CLKOUT1 1 10 RESET 11 2 3 4 5 6 7 8 9 CLKOUT2 HIGH GROUP† LOW GROUP† Z GROUP† Boot Configuration XD[31:0]‡ † High group consists of: Low group consists of: Z group consists of: XFCLK, HOLDA IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, SDA10, CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD, and XHOLDA. ‡ XD[31:0] are the boot configuration pins during device reset. Figure 30. Reset Timing 56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 EXTERNAL INTERRUPT TIMING timing requirements for interrupt response cycles† (see Figure 31) -200 NO NO. † MIN MAX UNIT 2 tw(ILOW) Width of the interrupt pulse low 2P ns 3 tw(IHIGH) Width of the interrupt pulse high 2P ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. switching characteristics over recommended operating conditions during interrupt response cycles† (see Figure 31) NO NO. † -200 PARAMETER MIN MAX 9P UNIT 1 tR(EINTH -- IACKH) Response time, EXT_INTx high to IACK high 4 td(CKO2L-IACKV) Delay time, CLKOUT2 low to IACK valid 0 10 ns ns 5 td(CKO2L-INUMV) Delay time, CLKOUT2 low to INUMx valid 0 10 ns 6 td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid 0 10 ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. 1 CLKOUT2 2 3 EXT_INTx, NMI Intr Flag 4 4 IACK 6 5 INUMx Interrupt Number Figure 31. Interrupt Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 57 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 EXPANSION BUS SYNCHRONOUS FIFO TIMING timing requirements for synchronous FIFO interface (see Figure 32, Figure 33, and Figure 34) -200 NO NO. MIN 5 tsu(XDV-XFCKH) Setup time, read XDx valid before XFCLK high 6 th(XFCKH-XDV) Hold time, read XDx valid after XFCLK high MAX UNIT 3.5 ns 2 ns switching characteristics over recommended operating conditions for synchronous FIFO interface (see Figure 32, Figure 33, and Figure 34) NO NO. 1 -200 PARAMETER td(XFCKH-XCEV) Delay time, XFCLK high to XCEx valid valid† MAX 1 7 ns 2 td(XFCKH-XAV) Delay time, XFCLK high to XBE[3:0]/XA[5:2] 1 7 ns 3 td(XFCKH-XOEV) Delay time, XFCLK high to XOE valid 1 7 ns 4 td(XFCKH-XREV) Delay time, XFCLK high to XRE valid 1 7 ns 7 td(XFCKH-XWEV) Delay time, XFCLK high to XWE/XWAIT‡ valid 1 7 ns 8 td(XFCKH-XDV) Delay time, XFCLK high to XDx valid 9 ns 9 td(XFCKH-XDIV) Delay time, XFCLK high to XDx invalid 1 ns † XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses. ‡ XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses. XFCLK 1 1 XCE3† 2 XBE[3:0]/XA[5:2]‡ 2 XA1 XA2 XA3 XA4 3 3 XOE 4 4 XRE XWE/XWAIT§ 6 5 XD[31:0] D1 D2 D3 † FIFO read (glueless) mode only available in XCE3. XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses. § XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses. ‡ Figure 32. FIFO Read Timing (Glueless Read Mode) 58 UNIT MIN POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 D4 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED) XFCLK 1 1 XCEx 2 XBE[3:0]/XA[5:2]† 2 XA1 XA2 XA3 XA4 3 3 XOE 4 4 XRE XWE/XWAIT‡ 6 5 XD[31:0] † ‡ D1 D2 D3 D4 XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses. XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses. Figure 33. FIFO Read Timing XFCLK 1 1 XCEx 2 XBE[3:0]/XA[5:2]† 2 XA1 XA2 XA3 XA4 XOE XRE 7 7 XWE/XWAIT‡ 9 8 XD[31:0] † ‡ D1 D2 D3 D4 XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses. XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses. Figure 34. FIFO Write Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 59 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING timing requirements for asynchronous peripheral cycles†‡§¶ (see Figure 35--Figure 38) -200 NO NO. MIN 3 tsu(XDV-XREH) Setup time, XDx valid before XRE high 4 th(XREH-XDV) Hold time, XDx valid after XRE high 6 tsu(XRDYH-XREL) Setup time, XRDY high before XRE low 7 th(XREL-XRDYH) Hold time, XRDY high after XRE low 9 tsu(XRDYL-XREL) Setup time, XRDY low before XRE low 10 th(XREL-XRDYL) Hold time, XRDY low after XRE low 11 tw(XRDYH) Pulse width, XRDY high 15 tsu(XRDYH-XWEL) Setup time, XRDY high before XWE low 16 th(XWEL-XRDYH) Hold time, XRDY high after XWE low 18 tsu(XRDYL-XWEL) Setup time, XRDY low before XWE low 19 th(XWEL-XRDYL) Hold time, XRDY low after XWE low MAX UNIT 8.5 ns 1 ns --[(RST -- 3) * P -- 10] ns (RST -- 3) * P + 2 ns --[(RST -- 3) * P -- 6] ns (RST -- 3) * P + 2 ns 2P ns --[(WST -- 3) * P -- 10] ns (WST -- 3) * P + 2 ns --[(WST -- 3) * P -- 6] ns (WST -- 3) * P + 2 ns † To ensure data setup time, simply program the strobe width wide enough. XRDY is internally synchronized. If XRDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, XRDY can be an asynchronous input. ‡ RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the XBUS XCE space control registers. § P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width. switching characteristics over recommended operating conditions for asynchronous peripheral cycles‡§¶# (see Figure 35--Figure 38) NO NO. -200 PARAMETER MIN TYP MAX UNIT 1 tosu(SELV-XREL) Output setup time, select signals valid to XRE low RS * P -- 2 ns 2 toh(XREH-SELIV) Output hold time, XRE low to select signals invalid RH * P -- 2 ns 5 tw(XREL) Pulse width, XRE low 8 td(XRDYH-XREH) Delay time, XRDY high to XRE high 12 tosu(SELV-XWEL) Output setup time, select signals valid to XWE low WS * P -- 2 13 toh(XWEH-SELIV) Output hold time, XWE low to select signals invalid WH * P -- 2 14 tw(XWEL) Pulse width, XWE low 17 td(XRDYH-XWEH) Delay time, XRDY high to XWE high RST * P 3P ns 4P + 5 ns ns WST * P ‡ 3P ns ns 4P + 5 ns RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the XBUS XCE space control registers. § P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width. # Select signals include: XCEx, XBE[3:0]/XA[5:2], XOE; and for writes, include XD[31:0], with the exception that XCEx can stay active for an additional 7P ns following the end of the cycle. 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED) Setup = 2 Strobe = 3 Hold = 2 CLKOUT1 1 2 1 2 XCEx XBE[3:0]/ XA[5:2]† 3 4 XD[31:0] 1 2 XOE 6 7 XRE 5 XWE/XWAIT‡ XRDY§ † XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses. XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses. § XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses. ‡ Figure 35. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Not Used) Setup = 2 Strobe = 3 Not Ready Hold = 2 CLKOUT1 1 2 1 2 XCEx XBE[3:0]/ XA[5:2]† 3 4 XD[31:0] 1 2 XOE 8 10 9 XRE XWE/XWAIT‡ 11 XRDY§ † XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses. XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses. § XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses. ‡ Figure 36. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Used) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 61 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED) Setup = 2 Strobe = 3 Hold = 2 CLKOUT1 12 13 12 13 12 13 XCEx XBE[3:0]/ XA[5:2]† XD[31:0] XOE XRE 15 16 14 XWE/XWAIT‡ XRDY§ † XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses. XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses. § XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses. ‡ Figure 37. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Not Used) Setup = 2 Strobe = 3 Not Ready Hold = 2 CLKOUT1 12 13 12 13 12 13 XCEx XBE[3:0]/ XA[5:2]† XD[31:0] XOE XRE 17 18 19 XWE/XWAIT‡ 11 XRDY§ † XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses. XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses. § XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses. ‡ Figure 38. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Used) 62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING timing requirements with external device as bus master (see Figure 39 and Figure 40) -200 NO NO. MIN MAX UNIT 1 tsu(XCSV-XCKIH) Setup time, XCS valid before XCLKIN high 3.5 ns 2 th(XCKIH-XCS) Hold time, XCS valid after XCLKIN high 2.8 ns 3 tsu(XAS-XCKIH) Setup time, XAS valid before XCLKIN high 3.5 ns 4 th(XCKIH-XAS) Hold time, XAS valid after XCLKIN high 2.8 ns 5 tsu(XCTL-XCKIH) Setup time, XCNTL valid before XCLKIN high 3.5 ns 6 th(XCKIH-XCTL) Hold time, XCNTL valid after XCLKIN high 2.8 ns 7 tsu(XWR-XCKIH) Setup time, XW/R valid before XCLKIN high† 3.5 ns 2.8 ns 3.5 ns 2.8 ns 3.5 ns 2.8 ns high† 8 th(XCKIH-XWR) Hold time, XW/R valid after XCLKIN 9 tsu(XBLTV-XCKIH) Setup time, XBLAST valid before XCLKIN high‡ high‡ 10 th(XCKIH-XBLTV) Hold time, XBLAST valid after XCLKIN 16 tsu(XBEV-XCKIH) Setup time, XBE[3:0]/XA[5:2] valid before XCLKIN high§ high§ 17 th(XCKIH-XBEV) Hold time, XBE[3:0]/XA[5:2] valid after XCLKIN 18 tsu(XD-XCKIH) Setup time, XDx valid before XCLKIN high 3.5 ns 19 th(XCKIH-XD) Hold time, XDx valid after XCLKIN high 2.8 ns † XW/R input/output polarity selected at boot. ‡ XBLAST input polarity selected at boot. § XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. switching characteristics over recommended operating conditions with external device as bus master¶ (see Figure 39 and Figure 40) NO NO. -200 PARAMETER MIN 11 td(XCKIH-XDLZ) Delay time, XCLKIN high to XDx low impedance 12 td(XCKIH-XDV) Delay time, XCLKIN high to XDx valid 13 td(XCKIH-XDIV) Delay time, XCLKIN high to XDx invalid 14 td(XCKIH-XDHZ) Delay time, XCLKIN high to XDx high impedance invalid# td(XCKIH-XRY) Delay time, XCLKIN high to XRDY td(XCKIH-XRYLZ) Delay time, XCLKIN high to XRDY low impedance Delay time, XCLKIN high to XRDY high impedance# UNIT ns 16.5 20 td(XCKIH-XRYHZ) 0 5 15 21 MAX ns ns 4P ns 5 16.5 ns 5 16.5 ns 2P + 5 3P + 16.5 ns ¶ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. # XRDY operates as active-low ready input/output during host-port accesses. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 63 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED) XCLKIN 2 1 XCS 4 3 XAS 6 5 XCNTL 8 7 XW/R† 8 7 XW/R† XBE[3:0]/XA[5:2]‡ 10 9 XBLAST§ 10 9 XBLAST§ 11 D1 XD[31:0] 20 13 14 12 D2 15 XRDY¶ † XW/R input/output polarity selected at boot XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. § XBLAST input polarity selected at boot ¶ XRDY operates as active-low ready input/output during host-port accesses. ‡ Figure 39. External Host as Bus Master—Read 64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 D3 D4 15 21 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED) XCLKIN 2 1 XCS 4 3 XAS 6 5 XCNTL 8 7 XW/R† 8 7 XW/R† 17 16 XBE[3:0]/XA[5:2]‡ XBE1 XBE2 XBE3 XBE4 10 9 XBLAST§ 10 9 XBLAST§ 19 18 D1 XD[31:0] 20 D2 D3 D4 15 15 21 XRDY¶ † XW/R input/output polarity selected at boot XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. § XBLAST input polarity selected at boot ¶ XRDY operates as active-low ready input/output during host-port accesses. ‡ Figure 40. External Host as Bus Master—Write POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 65 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED) timing requirements with C62x™ as bus master (see Figure 41, Figure 42, and Figure 43) -200 NO NO. † MIN MAX UNIT 9 tsu(XDV-XCKIH) Setup time, XDx valid before XCLKIN high 3.5 ns 10 th(XCKIH-XDV) Hold time, XDx valid after XCLKIN high 2.8 ns 11 tsu(XRY-XCKIH) Setup time, XRDY valid before XCLKIN high† 3.5 ns high† 12 th(XCKIH-XRY) Hold time, XRDY valid after XCLKIN 2.8 ns 14 tsu(XBFF-XCKIH) Setup time, XBOFF valid before XCLKIN high 3.5 ns 15 th(XCKIH-XBFF) Hold time, XBOFF valid after XCLKIN high 2.8 ns XRDY operates as active-low ready input/output during host-port accesses. switching characteristics over recommended operating conditions with C62x™ as bus master (see Figure 41, Figure 42, and Figure 43) NO NO. -200 PARAMETER MAX UNIT 1 td(XCKIH-XASV) Delay time, XCLKIN high to XAS valid 5 16.5 ns 2 td(XCKIH-XWRV) Delay time, XCLKIN high to XW/R valid‡ 5 16.5 ns valid§ 3 td(XCKIH-XBLTV) Delay time, XCLKIN high to XBLAST 5 16.5 ns 4 td(XCKIH-XBEV) Delay time, XCLKIN high to XBE[3:0]/XA[5:2] valid¶ 5 16.5 ns 5 td(XCKIH-XDLZ) Delay time, XCLKIN high to XDx low impedance 0 6 td(XCKIH-XDV) Delay time, XCLKIN high to XDx valid 7 td(XCKIH-XDIV) Delay time, XCLKIN high to XDx invalid 8 td(XCKIH-XDHZ) Delay time, XCLKIN high to XDx high impedance 13 td(XCKIH-XWTV) Delay time, XCLKIN high to XWE/XWAIT valid# ‡ XW/R input/output polarity selected at boot. XBLAST output polarity is always active low. ¶ XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. # XWE/XWAIT operates as XWAIT output signal during host-port accesses. § 66 MIN POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 ns 16.5 5 5 ns ns 4P ns 16.5 ns TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED) XCLKIN 1 1 XAS 2 2 XW/R† XW/R† 3 3 XBLAST‡ 4 4 XBE[3:0]/XA[5:2]§ 5 6 AD XD[31:0] 7 BE 9 8 D1 10 D2 D3 D4 11 12 XRDY 13 13 XWE/XWAIT¶ † XW/R input/output polarity selected at boot XBLAST output polarity is always active low. § XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. ¶ XWE/XWAIT operates as XWAIT output signal during host-port accesses. ‡ Figure 41. C62x™ as Bus Master—Read XCLKIN 1 1 XAS XW/R† 2 2 XW/R† 3 3 XBLAST‡ 4 4 6 7 XBE[3:0]/XA[5:2]§ 5 XD[31:0] Addr D1 D2 D3 11 XRDY 8 D4 12 13 13 XWE/XWAIT¶ † XW/R input/output polarity selected at boot XBLAST output polarity is always active low. § XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. ¶ XWE/XWAIT operates as XWAIT output signal during host-port accesses. ‡ Figure 42. C62x™ as Bus Master—Write POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 67 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED) XCLKIN 1 1 XAS XW/R† 2 2 4 4 XW/R† XBLAST‡ XBE[3:0]/XA[5:2]§ 6 5 XD[31:0] 8 Addr D1 11 D2 12 XRDY 15 14 XBOFF XHOLD¶ XHOLDA¶ XHOLD# XHOLDA# † ‡ § ¶ # || XW/R input/output polarity selected at boot XBLAST output polarity is always active low. XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. Internal arbiter enabled External arbiter enabled This diagram illustrates XBOFF timing. Bus arbitration timing is shown in Figure 46 and Figure 47. Figure 43. C62x™ as Bus Master—BOFF Operation|| 68 7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING timing requirements with external device as asynchronous bus master† (see Figure 44 and Figure 45) -200 NO NO. MIN MAX UNIT 1 tw(XCSL) Pulse duration, XCS low 4P ns 2 tw(XCSH) Pulse duration, XCS high 4P ns 3 tsu(XSEL-XCSL) Setup time, expansion bus select signals‡ valid before XCS low 1 ns 4 th(XCSL-XSEL) Hold time, expansion bus select signals‡ valid after XCS low 3 ns 10 th(XRYL-XCSL) Hold time, XCS low after XRDY low P + 1.5 ns 11 tsu(XBEV-XCSH) Setup time, XBE[3:0]/XA[5:2] valid before XCS high§ 1 ns 12 th(XCSH-XBEV) Hold time, XBE[3:0]/XA[5:2] valid after XCS high§ 3 ns 13 tsu(XDV-XCSH) Setup time, XDx valid before XCS high 1 ns 14 th(XCSH-XDV) Hold time, XDx valid after XCS high 3 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. Expansion bus select signals include XCNTL and XR/W. § XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. ‡ switching characteristics over recommended operating conditions with external device as asynchronous bus master† (see Figure 44 and Figure 45) NO NO. † PARAMETER -200 MIN 5 td(XCSL-XDLZ) Delay time, XCS low to XDx low impedance 0 6 td(XCSH-XDIV) Delay time, XCS high to XDx invalid 0 7 td(XCSH-XDHZ) Delay time, XCS high to XDx high impedance 8 td(XRYL-XDV) Delay time, XRDY low to XDx valid 9 td(XCSH-XRYH) Delay time, XCS high to XRDY high 0 MAX UNIT ns 12 ns 4P ns 1 ns 12 ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 69 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING (CONTINUED) 1 10 XCS 3 1 2 3 4 10 4 XCNTL XBE[3:0]/XA[5:2]† 3 3 4 4 XR/W‡ 3 3 4 4 XR/W‡ 5 7 6 8 5 7 6 8 Word XD[31:0] 9 9 XRDY † ‡ XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. XW/R input/output polarity selected at boot Figure 44. External Device as Asynchronous Master—Read 10 1 XCS 3 XBE[3:0]/XA[5:2]† XR/W‡ XR/W‡ XD[31:0] 3 4 XCNTL 11 3 3 1 2 11 3 3 4 13 4 12 4 10 4 4 14 13 9 ‡ XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. XW/R input/output polarity selected at boot Figure 45. External Device as Asynchronous Master—Write 70 14 word Word XRDY † 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 9 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 XHOLD/XHOLDA TIMING timing requirements for expansion bus arbitration (internal arbiter enabled)† (see Figure 46) -200 NO NO. 3 † MIN toh(XHDAH-XHDH) Output hold time, XHOLD high after XHOLDA high MAX P UNIT ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. switching characteristics over recommended operating conditions for expansion bus arbitration (internal arbiter enabled)†‡ (see Figure 46) NO NO. -200 PARAMETER 1 td(XHDH-XBHZ) Delay time, XHOLD high to XBus high impedance 2 td(XBHZ-XHDAH) Delay time, XBus high impedance to XHOLDA high 4 td(XHDL-XHDAL) Delay time, XHOLD low to XHOLDA low 5 td(XHDAL-XBLZ) Delay time, XHOLDA low to XBus low impedance UNIT MIN MAX 3P § ns 0 2P ns 3P 0 ns 2P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST. § All pending XBus transactions are allowed to complete before XHOLDA is asserted. External Requestor Owns Bus DSP Owns Bus DSP Owns Bus 3 XHOLD (input) 2 4 XHOLDA (output) 1 XBus† † 5 C6204 C6204 XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST. Figure 46. Expansion Bus Arbitration—Internal Arbiter Enabled POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 71 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 XHOLD/XHOLDA TIMING (CONTINUED) switching characteristics over recommended operating conditions for expansion bus arbitration (internal arbiter disabled)† (see Figure 47) NO NO. † ‡ -200 PARAMETER MIN 1 td(XHDAH-XBLZ) Delay time, XHOLDA high to XBus low impedance‡ 2 td(XBHZ-XHDL) Delay time, XBus high impedance to XHOLD low‡ 2P 2P + 10 0 P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST. 2 XHOLD (output) XHOLDA (input) 1 XBus† † C6204 XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST. Figure 47. Expansion Bus Arbitration—Internal Arbiter Disabled 72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 MAX 2P UNIT ns ns TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡ (see Figure 48) -200 NO NO. MIN MAX UNIT 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P--1¶ ns 5 tsu(FRH-CKRL) Setup time, time external FSR high before CLKR low 6 th(CKRL-FRH) Hold time, time external FSR high after CLKR low 7 tsu(DRV-CKRL) Setup time time, DR valid before CLKR low 8 th(CKRL-DRV) Hold time time, DR valid after CLKR low 10 tsu(FXH-CKXL) Setup time, time external FSX high before CLKX low 11 th(CKXL-FXH) Hold time, time external FSX high after CLKX low CLKR int 9 CLKR ext 2 CLKR int 6 CLKR ext 3 CLKR int 8 CLKR ext 0.5 CLKR int 4 CLKR ext 3 CLKX int 9 CLKX ext 2 CLKX int 6 CLKX ext 3 ns ns ns ns ns ns † CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. § The maximum bit rate for the C6204 devices is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz (P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. ¶ The minimum CLKR/X pulse duration is either (P--1) or 4 ns, whichever is larger. For example, when running parts at 200 MHz (P = 5 ns), use 4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P--1) = 9 ns as the minimum CLKR/X pulse duration. ‡ POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 73 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 48) NO NO. -200 PARAMETER 1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 2 tc(CKRX) Cycle time, CLKR/X MIN MAX 3 12 CLKR/X int 2P--2§¶ 2# tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int --3 3 CLKX int --3 3 CLKX ext 3 9 CLKX int --1 5 CLKX ext 2 9 td(CKXH-FXV) Dela time, Delay time CLKX high to internal FSX valid alid 12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 13 td(CKXH-DXV) Dela time, Delay time CLKX high to DX valid alid 14 td(FXH-DXV) Delay time, FSX high to DX valid ONLY applies when in data delay 0 (XDATDLY = 00b) mode. † ns ns 3 9 C -- UNIT C+ 2# CLKX int --1 4 CLKX ext 2 11 FSX int --1 5 FSX ext 2 12 ns ns ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. § P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ¶ The maximum bit rate for the C6204 devices is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz (P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. # C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit. ‡ 74 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKS 1 2 3 3 CLKR 4 FSR (int) 4 5 6 FSR (ext) 7 DR 2 3 8 Bit(n-1) (n-2) (n-3) 3 CLKX 9 FSX (int) 10 11 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) (n-3) Figure 48. McBSP Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 75 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 49) -200 NO NO. MIN UNIT 1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 4 ns 2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 ns CLKS 1 FSR external 2 CLKR/X (no need to resync) CLKR/X (needs resync) Figure 49. FSR Timing When GSYNC = 1 76 MAX POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 50) -200 MASTER NO. MIN 4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 5 th(CKXL-DRV) Hold time, DR valid after CLKX low SLAVE MAX MIN UNIT MAX 12 2 -- 3P ns 4 6 + 6P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 50) -200 NO. † ‡ § ¶ # MASTER§ PARAMETER MIN MAX SLAVE MIN UNIT MAX 1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶ T -- 3 T+5 ns 2 td(FXL-CKXH) Delay time, FSX low to CLKX high# L -- 4 L+5 ns 3 td(CKXH-DXV) Delay time, CLKX high to DX valid --4 5 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low L -- 2 L+3 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high P+3 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns 3P + 3 5P + 17 ns ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit. FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 77 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 50. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 78 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 51) -200 MASTER NO. MIN 4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 5 th(CKXH-DRV) Hold time, DR valid after CLKX high SLAVE MAX MIN UNIT MAX 12 2 -- 3P ns 4 5 + 6P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 51) -200 NO. MASTER§ PARAMETER MIN MAX SLAVE MIN UNIT MAX 1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶ L -- 2 L+3 ns 2 td(FXL-CKXH) Delay time, FSX low to CLKX high# T -- 2 T+3 ns 3 td(CKXL-DXV) Delay time, CLKX low to DX valid --2 4 3P + 4 5P + 17 ns 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low --2 4 3P + 3 5P + 17 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid H -- 2 H+4 2P + 2 4P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit. ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). ‡ POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 79 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 6 Bit 0 7 FSX DX 3 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 51. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 80 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 52) -200 MASTER NO. MIN 4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 5 th(CKXH-DRV) Hold time, DR valid after CLKX high SLAVE MAX MIN UNIT MAX 12 2 -- 3P ns 4 5 + 6P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 52) -200 NO. MASTER§ PARAMETER MIN MAX SLAVE MIN UNIT MAX 1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶ T -- 2 T+3 ns 2 td(FXL-CKXL) Delay time, FSX low to CLKX low# H -- 2 H+3 ns 3 td(CKXL-DXV) Delay time, CLKX low to DX valid --2 4 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high H -- 2 H+3 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high P+3 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns 3P + 4 5P + 17 ns ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit. ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). ‡ POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 81 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 52. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 82 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 53) -200 MASTER NO. MIN 4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 5 th(CKXL-DRV) Hold time, DR valid after CLKX low SLAVE MAX MIN UNIT MAX 12 2 -- 3P ns 4 5 + 6P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 53) -200 NO. MASTER§ PARAMETER MIN MAX SLAVE MIN UNIT MAX 1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶ H -- 2 H+3 ns 2 td(FXL-CKXL) Delay time, FSX low to CLKX low# T -- 2 T+1 ns 3 td(CKXH-DXV) Delay time, CLKX high to DX valid --2 4 3P + 4 5P + 17 ns 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high --2 4 3P + 3 5P + 17 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid L -- 2 L+4 2P + 2 4P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit. ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). ‡ POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 83 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 53. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 84 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 DMAC, TIMER, POWER-DOWN TIMING switching characteristics over recommended operating conditions for DMAC outputs† (see Figure 54) NO NO. 1 † -200 PARAMETER tw(DMACH) MIN Pulse duration, DMAC high MAX 2P--3 UNIT ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. 1 DMAC[3:0] Figure 54. DMAC Timing timing requirements for timer inputs† (see Figure 55) -200 NO NO. † MIN MAX UNIT 1 tw(TINPH) Pulse duration, TINP high 2P ns 2 tw(TINPL) Pulse duration, TINP low 2P ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. switching characteristics over recommended operating conditions for timer outputs† (see Figure 55) NO NO. † -200 PARAMETER MIN MAX UNIT 3 tw(TOUTH) Pulse duration, TOUT high 2P--3 ns 4 tw(TOUTL) Pulse duration, TOUT low 2P--3 ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. 2 1 TINPx 4 3 TOUTx Figure 55. Timer Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 85 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 DMAC, TIMER, POWER-DOWN TIMING (CONTINUED) switching characteristics over recommended operating conditions for power-down outputs† (see Figure 56) NO NO. 1 † -200 PARAMETER tw(PDH) MIN Pulse duration, PD high 2P P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. 1 PD Figure 56. Power-Down Timing 86 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 MAX UNIT ns TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 57) -200 NO NO. MIN MAX UNIT 1 tc(TCK) Cycle time, TCK 35 ns 3 tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high 11 ns 4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns switching characteristics over recommended operating conditions for JTAG test port (see Figure 57) NO NO. 2 -200 PARAMETER td(TCKL-TDOV) Delay time, TCK low to TDO valid MIN MAX --4.5 12 UNIT ns 1 TCK 2 2 TDO 3 4 TDI/TMS/TRST Figure 57. JTAG Test-Port Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 87 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 REVISION HISTORY This data sheet revision history highlights the technical changes made to the SPR152B device-specific data sheet to make it an SPRS152C revision. Scope: Applicable updates to the C62x device family, specifically relating to the C6204 device, have been incorporated. PAGE(S) NO. 88 ADDITIONS/CHANGES/DELETIONS All Updated the title for literature number SPRU190 to: TMS320C6000 DSP Peripherals Overview Reference Guide 10 memory map summary: Changed the document reference in the last sentence of the paragraph. 11 peripheral register descriptions: Updated the information regarding the document reference. 16 DMA synchronization events: Updated the information regarding the document reference. 17 Table 13, C6202/02B DSP Interrupts: Changed the document reference in the second footnote to: TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646) 36 Added the power-down mode logic section and accompanying information. 43 switching characteristics over recommended operating conditions for CLKOUT2 table: Removed NO. 1 (parameter tc(CKO2) ) from the table. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004 THERMAL/MECHANICAL DATA The mechanical package diagrams that follow the tables reflect the most current released mechanical data available for the designated devices. thermal resistance characteristics (GHK-288 S-PBGA package) NO † °C/W Air Flow (m/s†) 1 RΘJC Junction-to-case 9.5 N/A 2 RΘJA Junction-to-free air 26.5 0.00 3 RΘJA Junction-to-free air 23.9 0.50 4 RΘJA Junction-to-free air 22.6 1.00 5 RΘJA Junction-to-free air 21.3 2.00 °C/W Air Flow (m/s†) m/s = meters per second thermal resistance characteristics (GLW-340 S-PBGA package) NO † 1 RΘJC Junction-to-case 11.7 N/A 2 RΘJA Junction-to-free air 14.2 0.00 3 RΘJA Junction-to-free air 12.3 0.50 4 RΘJA Junction-to-free air 10.9 1.00 5 RΘJA Junction-to-free air 9.3 2.00 m/s = meters per second POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 89 PACKAGE OPTION ADDENDUM www.ti.com 5-Nov-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) TMS320C6204GWTA200 ACTIVE NFBGA GWT 288 90 Non-RoHS & Green SNPB Level-3-220C-168 HR -40 to 105 TMS320 C6204GWT200 A TMS320C6204ZWT200 ACTIVE NFBGA ZWT 288 90 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 90 TMS 320C6204ZWT 200 TMS320C6204ZWTA200 ACTIVE NFBGA ZWT 288 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 105 TMS320 C6204ZWT200 A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of