TMS320C6414TZLZ7



 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009
Highest-Performance Fixed-Point DSPs




− 1.67-/1.39-/1.17-/1-ns Instruction Cycle − 600-/720-/850-MHz, 1-GHz Clock Rate − Eight 32-Bit Instructions/Cycle − Twenty-Eight Operations/Cycle − 4800, 5760, 6800, 8000 MIPS − Fully Software-Compatible With C62x − C6414/15/16 Devices Pin-Compatible − Extended Temperature Devices Available VelociTI.2 Extensions to VelociTI Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x DSP Core − Eight Highly Independent Functional Units With VelociTI.2 Extensions: − Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle − Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle − Non-Aligned Load-Store Architecture − 64 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional Instruction Set Features − Byte-Addressable (8-/16-/32-/64-Bit Data) − 8-Bit Overflow Protection − Bit-Field Extract, Set, Clear − Normalization, Saturation, Bit-Counting − VelociTI.2 Increased Orthogonality VCP [C6416T Only] − Supports Over 833 7.95-Kbps AMR − Programmable Code Parameters TCP [C6416T Only] − Supports up to 10 2-Mbps or 60 384-Kbps 3GPP (6 Iterations) − Programmable Turbo Code and Decoding Parameters L1/L2 Memory Architecture − 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped) − 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative) − 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)
Two External Memory Interfaces (EMIFs)












− One 64-Bit (EMIFA), One 16-Bit (EMIFB) − Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO) − 1280M-Byte Total Addressable External Memory Space Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) Host-Port Interface (HPI) − User-Configurable Bus Width (32-/16-Bit) 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415T/C6416T] − Three PCI Bus Address Registers: Prefetchable Memory Non-Prefetchable Memory I/O − Four-Wire Serial EEPROM Interface − PCI Interrupt Request Under DSP Program Control − DSP Interrupt Via PCI I/O Cycle Three Multichannel Buffered Serial Ports − Direct Interface to T1/E1, MVIP, SCSA Framers − Up to 256 Channels Each − ST-Bus-Switching-, AC97-Compatible − Serial Peripheral Interface (SPI) Compatible (Motorola) Three 32-Bit General-Purpose Timers UTOPIA [C6415T/C6416T] − UTOPIA Level 2 Slave ATM Controller − 8-Bit Transmit and Receive Operations up to 50 MHz per Direction − User-Defined Cell Format up to 64 Bytes Sixteen General-Purpose I/O (GPIO) Pins Flexible PLL Clock Generator IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible 532-Pin Ball Grid Array (BGA) Package (GLZ/ZLZ/CLZ Suffixes), 0.8-mm Ball Pitch 0.09-µm/7-Level Cu Metal Process (CMOS) 3.3-V I/Os, 1.1-V Internal (600 MHz) 3.3-V I/Os, 1.2-V Internal (720/850 MHZ, 1 GHz) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright  2009, Texas Instruments Incorporated 
 
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   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Table of Contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 GLZ, ZLZ and CLZ BGA packages (bottom view) . . . . . . . . 4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 functional block and CPU (DSP core) diagram . . . . . . . . . . . 8 CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . . 9 memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . . 15 EDMA channel synchronization events . . . . . . . . . . . . . . . . 28 interrupt sources and interrupt selector . . . . . . . . . . . . . . . . 30 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 multiplexed pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 debugging considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 device support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 general-purpose input/output (GPIO) . . . . . . . . . . . . . . . . . . 69 power-down mode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 JTAG compatibility statement . . . . . . . . . . . . . EMIF device speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 POST OFFICE BOX 1443 70 72 73 74 74 75 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature . 75 76 76 77 recommended clock and control signal transition behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 parameter measurement information . . . . . . . . . . . . . . . 78 input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 85 programmable synchronous interface timing . . . . . . . . 89 synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 94 HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . 108 host-port interface (HPI) timing . . . . . . . . . . . . . . . . . . . 109 peripheral component interconnect (PCI) timing [C6415T and C6416T only] . . . . . . . . . . . . . . . . . . 114 multichannel buffered serial port (McBSP) timing . . . . 117 UTOPIA slave timing [C6415T and C6416T only] . . . 128 timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 general-purpose input/output (GPIO) port timing . . . . 132 JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 REVISION HISTORY This data sheet revision history highlights the technical changes made to the SPRS226L device-specific data sheet to make it an SPRS226M. Scope: Applicable updates to the C64x device family, specifically relating to the C6414T/C6415T/C6416T devices, have been incorporated. PAGE NO. 55 ADDITIONS/CHANGES/DELETIONS Updated RSV pin W25 Description in the Terminal Functions table POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 3 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 GLZ, ZLZ and CLZ BGA packages (bottom view) GLZ, ZLZ and CLZ 532-PIN BALL GRID ARRAY (BGA) PACKAGES ( BOTTOM VIEW ) AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 2 4 5 4 7 6 9 8 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 description The TMS320C64x DSPs (including the TMS320C6414T, TMS320C6415T, and TMS320C6416T devices†) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The TMS320C64x (C64x) device is based on the second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelociTI.2) developed by Texas Instruments (TI), making these DSPs an excellent choice for wireless infrastructure applications. The C64x is a code-compatible member of the C6000 DSP platform. With performance of up to 8000 million instructions per second (MIPS) at a clock rate of 1 GHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI architecture. The C64x can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 4000 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 8000 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The C6416T device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 833 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to sixty 384-Kbps or ten 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller. The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port [C6415T/C6416T only]; three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415T/C6416T only]; a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB‡), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals. The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation. Other trademarks are the property of their respective owners. † Throughout the remainder of this document, the TMS320C6414T, TMS320C6415T, and TMS320C6416T shall be referred to as TMS320C64x or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414T, C6415T, or C6416T. ‡ These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 5 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 device characteristics Table 1 provides an overview of the C6414T, C6415T, C6416T DSPs. The table shows significant features of the C64x devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 1. Characteristics of the C6414T, C6415T, C6416T Processors HARDWARE FEATURES Peripherals Not all peripherals pins are available at the same time. (For more details, see the Device Configuration section.) Peripheral performance is dependent on chip-level configuration. C6414T, C6415T, and C6416T EMIFA (64-bit bus width) (default clock source = AECLKIN) 1 EMIFB (16-bit bus width) (default clock source = BECLKIN) 1 EDMA (64 independent channels) 1 HPI (32- or 16-bit user selectable) 1 (HPI16 or HPI32) PCI (32-bit) [DeviceID Register Value 0xA16] 1 [C6415T/C6416T only] McBSPs (default internal clock source = CPU/4 clock frequency) 3 UTOPIA (8-bit mode) 1 [C6415T/C6416T only] 32-Bit Timers (default internal clock source = CPU/8 clock frequency) 3 General-Purpose Input/Output 0 (GP0) Decoder Coprocessors 16 VCP 1 [C6416T only] TCP 1 [C6416T only] Size (Bytes) On-Chip Memory 1056K 16K-Byte (16KB) L1 Program (L1P) Cache 16KB L1 Data (L1D) Cache 1024KB Unified Mapped RAM/Cache (L2) Organization CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) Device_ID Silicon Revision Identification Register (DEVICE_REV [20:16]) Address: 0x01B0 0200 Frequency MHz Cycle Time Voltage 0x0C01 DEVICE_REV[20:16] 10000 or 10001 10010 Silicon Revision 1.0 (14T/15T/16T) 2.0 (14T/15T/16T) 600, 720, 850, 1000 (1-GHz) 1.67 ns (C6414T/15T/16T - 6 [A-600, 600 MHz])† 1.39 ns (C6414T/15T/16T - 7 [A-720, 720 MHz])† 1.17 ns (C6414T/15T/16T - 8 [A-850, 850 MHz]† 1 ns (C6414T/15T/16T - 1 [1 GHz]) ns 1.1 V (600) 1.2 V (-720, -850, -1 G) Core (V) I/O (V) 3.3 V PLL Options CLKIN frequency multiplier BGA Package 23 x 23 mm Bypass (x1), x6, x12, x20 532-Pin BGA (GLZ, ZLZ and CLZ) Process Technology µm 0.09 µm † Note: The extended temperature devices’ (A−600, A−720, and A−850) Electrical Characteristics and AC Timings are the same as those for commercial temperature devices (e.g., −600, −720, and −850). 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 device compatibility The C64x generation of devices has a diverse and powerful set of peripherals. The common peripheral set and pin-compatibility that the C6414T, C6415T, and C6416T devices offer lead to easier system designs and faster time to market. Table 2 identifies the peripherals and coprocessors that are available on the C6414T, C6415T, and C6416T devices. The C6414T, C6415T, and C6416T devices are pin-for-pin compatible, provided the following conditions are met:
All devices are using the same peripherals. The C6414T is pin-for-pin compatible with the C6415T/C6416T when the PCI and UTOPIA peripherals on the C6415T/C6416T are disabled. The C6415T is pin-for-pin compatible with the C6416T when they are in the same peripheral selection mode. [For more information on peripheral selection, see the Device Configurations section of this data sheet.]
The BEA[9:7] pins are properly pulled up/down. [For more details on the device-specific BEA[9:7] pin configurations, see the Terminal Functions table of this data sheet.] Table 2. Peripherals and Coprocessors Available on the C6414T, C6415T, and C6416T Devices†‡ C6414T C6415T C6416T EMIFA (64-bit bus width) PERIPHERALS/COPROCESSORS √ √ √ EMIFB (16-bit bus width) √ √ √ EDMA (64 independent channels) √ √ √ HPI (32- or 16-bit user selectable) √ √ √ PCI (32-bit) [Specification v2.2] — √ √ McBSPs (McBSP0, McBSP1, McBSP2) √ √ √ UTOPIA (8-bit mode) [Specification v1.0] — √ √ Timers (32-bit) [TIMER0, TIMER1, TIMER2] √ √ √ √ √ √ GPIOs (GP[15:0]) √ † — denotes peripheral/coprocessor is not available on this device. ‡ Not all peripherals pins are available at the same time. (For more details, see the Device Configuration section.) VCP/TCP Coprocessors — POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 — 7 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 functional block and CPU (DSP core) diagram C64x Digital Signal Processor VCP† L1P Cache Direct-Mapped 16K Bytes Total TCP† SDRAM 64 SBSRAM 16 EMIF A EMIF B C64x DSP Core ZBT SRAM Instruction Fetch Timer 2 FIFO SRAM Control Registers Instruction Dispatch Advanced Instruction Packet Timer 1 ROM/FLASH Control Logic Instruction Decode Timer 0 I/O Devices Data Path A A Register File A31−A16 A15−A0 McBSP2 .L1 UTOPIA‡ UTOPIA: Up to 400 Mbps Master ATMC or McBSPs: Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs Enhanced DMA Controller (64-channel) .S1 .M1 .D1 Data Path B Test B Register File B31−B16 B15−B0 .D2 .M2 .S2 Advanced In-Circuit Emulation .L2 L2 Memory 1024K Bytes Interrupt Control McBSP1‡ L1D Cache 2-Way Set-Associative 16K Bytes Total McBSP0 16 GPIO[8:0] GPIO[15:9]‡ 32 HPI‡ or PCI‡ Boot Configuration PLL (x1, x6, x12, and x20) Power-Down Logic Interrupt Selector † VCP and TCP decoder coprocessors are applicable to the C6416T device only. ‡ For the C6415T and C6416T devices, the UTOPIA peripheral is muxed with McBSP1, and the PCI peripheral is muxed with the HPI peripheral and the GPIO[15:9] port. For more details on the multiplexed pins of these peripherals, see the Device Configurations section of this data sheet. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 CPU (DSP core) description The CPU fetches VelociTI advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other VLIW architectures. The C64x VelociTI.2 extensions add enhancements to the TMS320C62x DSP VelociTI architecture. These enhancements include:





Register file enhancements Data path extensions Quad 8-bit and dual 16-bit extensions with data flow enhancements Additional functional unit hardware Increased orthogonality of the instruction set Additional instructions that reduce code size and increase register flexibility The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the packed 16-bit and 32-/40-bit fixed-point data types found in the C62x VelociTI VLIW architecture, the C64x register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP core) diagram, and Figure 1]. The four functional units on each side of the CPU can freely share the 32 registers belonging to that side. Additionally, each side features a “data cross path”—a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in the same execute packet. All functional units in the C64x CPU can access operands via the data cross path. Register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that register was updated in the previous clock cycle. In addition to the C62x DSP fixed-point instructions, the C64x DSP includes a comprehensive collection of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2 extensions allow the C64x CPU to operate directly on packed data to streamline data flow and increase instruction set efficiency. Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits) with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 64 registers. Some registers, however, are singled out to support specific addressing modes or to hold the condition for conditional instructions (if the condition is not automatically “true”). TMS320C62x is a trademark of Texas Instruments. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 9 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 CPU (DSP core) description (continued) The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two 16 × 16-bit multiplies or four 8 × 8-bit multiplies per clock cycle. The .M unit can also perform 16 × 32-bit multiply operations, dual 16 × 16-bit multiplies with add/subtract operations, and quad 8 × 8-bit multiplies with add operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies, and bidirectional variable shift hardware. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual 16-bit, and quad 8-bit operations. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. A C64x DSP device enhancement now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x/TMS320C67x DSP devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the C64x DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes, half-words, words, or doublewords. All load and store instructions are byte-, half-word-, word-, or doubleword-addressable. For more details on the C64x CPU functional units enhancements, see the following documents: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) TMS320C64x Technical Overview (literature number SPRU395) For more detailed information on the device compatibility, similarities/differences, and migration from the TMS320C6414/15/16 devices to the TMS320C6414T/15T/16T devices, see the following document: Migrating From TMS320C6416/15/14 to TMS320C6416T/15T/14T application report (literature number SPRA981). TMS320C67x is a trademark of Texas Instruments. 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 CPU (DSP core) description (continued) src1 .L1 src2 dst long dst long src ST1b (Store Data) ST1a (Store Data) 8 8 32 MSBs 32 LSBs long src long dst dst .S1 src1 Data Path A 8 8 Register File A (A0−A31) src2 See Note A See Note A long dst dst .M1 src1 src2 LD1b (Load Data) LD1a (Load Data) 32 MSBs 32 LSBs DA1 (Address) .D1 dst src1 src2 2X 1X src2 .D2 DA2 (Address) LD2a (Load Data) LD2b (Load Data) src1 dst 32 LSBs 32 MSBs src2 .M2 src1 dst See Note A See Note A long dst Register File B (B0− B31) src2 Data Path B .S2 src1 dst long dst long src ST2a (Store Data) ST2b (Store Data) 8 8 32 MSBs 32 LSBs long src long dst dst 8 8 .L2 src2 src1 Control Register File NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs. Figure 1. TMS320C64x CPU (DSP Core) Data Paths POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 11 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 memory map summary Table 3 shows the memory map address ranges of the TMS320C64x device. Internal memory is always located at address 0 and can be used as both program and data memory. The external memory address ranges in the C64x device begin at the hex address locations 0x6000 0000 for EMIFB and 0x8000 0000 for EMIFA. 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Table 3. TMS320C6414T, C6415T, C6416T Memory Map Summary MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) Internal RAM (L2) 1M Reserved 23M External Memory Interface A (EMIFA) Registers 256K L2 Registers 256K HPI Registers 256K McBSP 0 Registers 256K McBSP 1 Registers 256K Timer 0 Registers 256K Timer 1 Registers 256K Interrupt Selector Registers 256K EDMA RAM and EDMA Registers 256K McBSP 2 Registers 256K EMIFB Registers 256K Timer 2 Registers 256K GPIO Registers 256K UTOPIA Registers (C6415T and C6416T only)† TCP/VCP Registers (C6416T only)‡ 256K Reserved 256K PCI Registers (C6415T and C6416T only)† 256K Reserved 256K 4M – 256K QDMA Registers 52 Reserved 736M – 52 McBSP 0 Data 64M McBSP 1 Data 64M McBSP 2 Data 64M UTOPIA Queues (C6415T and C6416T only)† 64M Reserved 256M TCP/VCP (C6416T only)‡ 256M EMIFB CE0 64M EMIFB CE1 64M EMIFB CE2 64M EMIFB CE3 64M Reserved 256M EMIFA CE0 256M EMIFA CE1 256M EMIFA CE2 256M EMIFA CE3 256M Reserved 1G HEX ADDRESS RANGE 0000 0010 0180 0184 0188 018C 0190 0194 0198 019C 01A0 01A4 01A8 01AC 01B0 01B4 01B8 01BC 01C0 01C4 0200 0200 3000 3400 3800 3C00 4000 5000 6000 6400 6800 6C00 7000 8000 9000 A000 B000 C000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0034 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 000F 017F 0183 0187 018B 018F 0193 0197 019B 019F 01A3 01A7 01AB 01AF 01B3 01B7 01BB 01BF 01C3 01FF 0200 2FFF 33FF 37FF 3BFF 3FFF 4FFF 5FFF 63FF 67FF 6BFF 6FFF 7FFF 8FFF 9FFF AFFF BFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 0033 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF † For the C6414T device, these memory address locations are reserved. The C6414T device does not support the UTOPIA and PCI peripherals. ‡ Only the C6416T device supports the VCP/TCP Coprocessors. For the C6414T and C6415T devices, these memory address locations are reserved. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 13 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 L2 architecture expanded Figure 2 shows the detail of the L2 architecture on the TMS320C6414T, TMS320C6415T, and TMS320C6416T devices. For more information on the L2MODE bits, see the cache configuration (CCFG) register bit field descriptions in the TMS320C64x Two-Level Internal Memory Reference Guide (literature number SPRU610). L2MODE 000 001 010 L2 Memory 011 Block Base Address 111 768K SRAM 896K SRAM 960K SRAM 992K SRAM 1024K SRAM (All) 0x0000 0000 768K-Byte SRAM ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ 0x000C 0000 256K Cache (4 Way) 128K Cache (4 Way) 64K Cache (4 Way) 32K Cache (4 Way) 128K-Byte RAM 0x000E 0000 64K-Byte RAM 0x000F 0000 32K-Byte RAM 0x000F 8000 32K-Byte RAM 0x000F FFFF Figure 2. TMS320C6414T/C6415T/C6416T L2 Architecture Memory Configuration 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 peripheral register descriptions Table 4 through Table 23 identify the peripheral registers for the C6414T, C6415T, and C6416T devices by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190). Table 4. EMIFA Registers HEX ADDRESS RANGE ACRONYM 0180 0000 GBLCTL EMIFA global control REGISTER NAME 0180 0004 CECTL1 EMIFA CE1 space control 0180 0008 CECTL0 EMIFA CE0 space control 0180 000C − 0180 0010 CECTL2 EMIFA CE2 space control 0180 0014 CECTL3 EMIFA CE3 space control 0180 0018 SDCTL EMIFA SDRAM control 0180 001C SDTIM EMIFA SDRAM refresh control 0180 0020 SDEXT EMIFA SDRAM extension 0180 0024 − 0180 003C − 0180 0040 PDTCTL Peripheral device transfer (PDT) control 0180 0044 CESEC1 EMIFA CE1 space secondary control 0180 0048 CESEC0 EMIFA CE0 space secondary control Reserved Reserved 0180 004C − 0180 0050 CESEC2 Reserved EMIFA CE2 space secondary control 0180 0054 CESEC3 EMIFA CE3 space secondary control 0180 0058 − 0183 FFFF – Reserved Table 5. EMIFB Registers HEX ADDRESS RANGE ACRONYM 01A8 0000 GBLCTL EMIFB global control REGISTER NAME 01A8 0004 CECTL1 EMIFB CE1 space control 01A8 0008 CECTL0 EMIFB CE0 space control 01A8 000C − 01A8 0010 CECTL2 EMIFB CE2 space control 01A8 0014 CECTL3 EMIFB CE3 space control 01A8 0018 SDCTL EMIFB SDRAM control 01A8 001C SDTIM EMIFB SDRAM refresh control 01A8 0020 SDEXT EMIFB SDRAM extension 01A8 0024 − 01A8 003C − 01A8 0040 PDTCTL Peripheral device transfer (PDT) control 01A8 0044 CESEC1 EMIFB CE1 space secondary control 01A8 0048 CESEC0 EMIFB CE0 space secondary control 01A8 004C − 01A8 0050 CESEC2 EMIFB CE2 space secondary control 01A8 0054 CESEC3 EMIFB CE3 space secondary control 01A8 0058 − 01AB FFFF – Reserved Reserved Reserved Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 15 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 peripheral register descriptions (continued) Table 6. L2 Cache Registers 16 HEX ADDRESS RANGE ACRONYM 0184 0000 CCFG 0184 0004 − 0184 0FFC − 0184 1000 EDMAWEIGHT REGISTER NAME Cache configuration register Reserved L2 EDMA access control register 0184 1004 − 0184 1FFC − 0184 2000 L2ALLOC0 Reserved L2 allocation register 0 0184 2004 L2ALLOC1 L2 allocation register 1 0184 2008 L2ALLOC2 L2 allocation register 2 0184 200C L2ALLOC3 L2 allocation register 3 0184 2010 − 0184 3FFC − 0184 4000 L2WBAR Reserved L2 writeback base address register 0184 4004 L2WWC L2 writeback word count register 0184 4010 L2WIBAR L2 writeback invalidate base address register 0184 4014 L2WIWC L2 writeback invalidate word count register 0184 4018 L2IBAR L2 invalidate base address register 0184 401C L2IWC L2 invalidate word count register 0184 4020 L1PIBAR L1P invalidate base address register 0184 4024 L1PIWC L1P invalidate word count register 0184 4030 L1DWIBAR L1D writeback invalidate base address register L1D writeback invalidate word count register 0184 4034 L1DWIWC 0184 4038 − 0184 4044 − 0184 4048 L1DIBAR L1D invalidate base address register 0184 404C L1DIWC L1D invalidate word count register 0184 4050 − 0184 4FFC − Reserved Reserved 0184 5000 L2WB 0184 5004 L2WBINV L2 writeback all register 0184 5008 − 0184 7FFC − Reserved 0184 8000 − 0184 817C MAR0 to MAR95 Reserved 0184 8180 MAR96 Controls EMIFB CE0 range 6000 0000 − 60FF FFFF 0184 8184 MAR97 Controls EMIFB CE0 range 6100 0000 − 61FF FFFF 0184 8188 MAR98 Controls EMIFB CE0 range 6200 0000 − 62FF FFFF 0184 818C MAR99 Controls EMIFB CE0 range 6300 0000 − 63FF FFFF 0184 8190 MAR100 Controls EMIFB CE1 range 6400 0000 − 64FF FFFF 0184 8194 MAR101 Controls EMIFB CE1 range 6500 0000 − 65FF FFFF L2 writeback invalidate all register 0184 8198 MAR102 Controls EMIFB CE1 range 6600 0000 − 66FF FFFF 0184 819C MAR103 Controls EMIFB CE1 range 6700 0000 − 67FF FFFF 0184 81A0 MAR104 Controls EMIFB CE2 range 6800 0000 − 68FF FFFF 0184 81A4 MAR105 Controls EMIFB CE2 range 6900 0000 − 69FF FFFF 0184 81A8 MAR106 Controls EMIFB CE2 range 6A00 0000 − 6AFF FFFF 0184 81AC MAR107 Controls EMIFB CE2 range 6B00 0000 − 6BFF FFFF POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 COMMENTS 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 peripheral register descriptions (continued) Table 6. L2 Cache Registers (Continued) HEX ADDRESS RANGE ACRONYM 0184 81B0 MAR108 Controls EMIFB CE3 range 6C00 0000 − 6CFF FFFF REGISTER NAME 0184 81B4 MAR109 Controls EMIFB CE3 range 6D00 0000 − 6DFF FFFF 0184 81B8 MAR110 Controls EMIFB CE3 range 6E00 0000 − 6EFF FFFF 0184 81BC MAR111 Controls EMIFB CE3 range 6F00 0000 − 6FFF FFFF 0184 81C0 − 0184 81FC MAR112 to MAR127 0184 8200 MAR128 Controls EMIFA CE0 range 8000 0000 − 80FF FFFF 0184 8204 MAR129 Controls EMIFA CE0 range 8100 0000 − 81FF FFFF COMMENTS Reserved 0184 8208 MAR130 Controls EMIFA CE0 range 8200 0000 − 82FF FFFF 0184 820C MAR131 Controls EMIFA CE0 range 8300 0000 − 83FF FFFF 0184 8210 MAR132 Controls EMIFA CE0 range 8400 0000 − 84FF FFFF 0184 8214 MAR133 Controls EMIFA CE0 range 8500 0000 − 85FF FFFF 0184 8218 MAR134 Controls EMIFA CE0 range 8600 0000 − 86FF FFFF 0184 821C MAR135 Controls EMIFA CE0 range 8700 0000 − 87FF FFFF 0184 8220 MAR136 Controls EMIFA CE0 range 8800 0000 − 88FF FFFF 0184 8224 MAR137 Controls EMIFA CE0 range 8900 0000 − 89FF FFFF 0184 8228 MAR138 Controls EMIFA CE0 range 8A00 0000 − 8AFF FFFF 0184 822C MAR139 Controls EMIFA CE0 range 8B00 0000 − 8BFF FFFF 0184 8230 MAR140 Controls EMIFA CE0 range 8C00 0000 − 8CFF FFFF 0184 8234 MAR141 Controls EMIFA CE0 range 8D00 0000 − 8DFF FFFF 0184 8238 MAR142 Controls EMIFA CE0 range 8E00 0000 − 8EFF FFFF 0184 823C MAR143 Controls EMIFA CE0 range 8F00 0000 − 8FFF FFFF 0184 8240 MAR144 Controls EMIFA CE1 range 9000 0000 − 90FF FFFF 0184 8244 MAR145 Controls EMIFA CE1 range 9100 0000 − 91FF FFFF 0184 8248 MAR146 Controls EMIFA CE1 range 9200 0000 − 92FF FFFF 0184 824C MAR147 Controls EMIFA CE1 range 9300 0000 − 93FF FFFF 0184 8250 MAR148 Controls EMIFA CE1 range 9400 0000 − 94FF FFFF 0184 8254 MAR149 Controls EMIFA CE1 range 9500 0000 − 95FF FFFF 0184 8258 MAR150 Controls EMIFA CE1 range 9600 0000 − 96FF FFFF 0184 825C MAR151 Controls EMIFA CE1 range 9700 0000 − 97FF FFFF 0184 8260 MAR152 Controls EMIFA CE1 range 9800 0000 − 98FF FFFF 0184 8264 MAR153 Controls EMIFA CE1 range 9900 0000 − 99FF FFFF 0184 8268 MAR154 Controls EMIFA CE1 range 9A00 0000 − 9AFF FFFF 0184 826C MAR155 Controls EMIFA CE1 range 9B00 0000 − 9BFF FFFF 0184 8270 MAR156 Controls EMIFA CE1 range 9C00 0000 − 9CFF FFFF 0184 8274 MAR157 Controls EMIFA CE1 range 9D00 0000 − 9DFF FFFF 0184 8278 MAR158 Controls EMIFA CE1 range 9E00 0000 − 9EFF FFFF 0184 827C MAR159 Controls EMIFA CE1 range 9F00 0000 − 9FFF FFFF 0184 8280 MAR160 Controls EMIFA CE2 range A000 0000 − A0FF FFFF 0184 8284 MAR161 Controls EMIFA CE2 range A100 0000 − A1FF FFFF 0184 8288 MAR162 Controls EMIFA CE2 range A200 0000 − A2FF FFFF 0184 828C MAR163 Controls EMIFA CE2 range A300 0000 − A3FF FFFF POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 17 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 peripheral register descriptions (continued) Table 6. L2 Cache Registers (Continued) 18 HEX ADDRESS RANGE ACRONYM 0184 8290 MAR164 Controls EMIFA CE2 range A400 0000 − A4FF FFFF REGISTER NAME 0184 8294 MAR165 Controls EMIFA CE2 range A500 0000 − A5FF FFFF 0184 8298 MAR166 Controls EMIFA CE2 range A600 0000 − A6FF FFFF 0184 829C MAR167 Controls EMIFA CE2 range A700 0000 − A7FF FFFF 0184 82A0 MAR168 Controls EMIFA CE2 range A800 0000 − A8FF FFFF 0184 82A4 MAR169 Controls EMIFA CE2 range A900 0000 − A9FF FFFF 0184 82A8 MAR170 Controls EMIFA CE2 range AA00 0000 − AAFF FFFF 0184 82AC MAR171 Controls EMIFA CE2 range AB00 0000 − ABFF FFFF 0184 82B0 MAR172 Controls EMIFA CE2 range AC00 0000 − ACFF FFFF 0184 82B4 MAR173 Controls EMIFA CE2 range AD00 0000 − ADFF FFFF 0184 82B8 MAR174 Controls EMIFA CE2 range AE00 0000 − AEFF FFFF 0184 82BC MAR175 Controls EMIFA CE2 range AF00 0000 − AFFF FFFF 0184 82C0 MAR176 Controls EMIFA CE3 range B000 0000 − B0FF FFFF 0184 82C4 MAR177 Controls EMIFA CE3 range B100 0000 − B1FF FFFF 0184 82C8 MAR178 Controls EMIFA CE3 range B200 0000 − B2FF FFFF 0184 82CC MAR179 Controls EMIFA CE3 range B300 0000 − B3FF FFFF 0184 82D0 MAR180 Controls EMIFA CE3 range B400 0000 − B4FF FFFF 0184 82D4 MAR181 Controls EMIFA CE3 range B500 0000 − B5FF FFFF 0184 82D8 MAR182 Controls EMIFA CE3 range B600 0000 − B6FF FFFF 0184 82DC MAR183 Controls EMIFA CE3 range B700 0000 − B7FF FFFF 0184 82E0 MAR184 Controls EMIFA CE3 range B800 0000 − B8FF FFFF 0184 82E4 MAR185 Controls EMIFA CE3 range B900 0000 − B9FF FFFF 0184 82E8 MAR186 Controls EMIFA CE3 range BA00 0000 − BAFF FFFF 0184 82EC MAR187 Controls EMIFA CE3 range BB00 0000 − BBFF FFFF 0184 82F0 MAR188 Controls EMIFA CE3 range BC00 0000 − BCFF FFFF 0184 82F4 MAR189 Controls EMIFA CE3 range BD00 0000 − BDFF FFFF 0184 82F8 MAR190 Controls EMIFA CE3 range BE00 0000 − BEFF FFFF 0184 82FC MAR191 Controls EMIFA CE3 range BF00 0000 − BFFF FFFF 0184 8300 − 0184 83FC MAR192 to MAR255 Reserved 0184 8400 − 0187 FFFF − Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 COMMENTS 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 peripheral register descriptions (continued) Table 7. EDMA Registers HEX ADDRESS RANGE ACRONYM 01A0 FF9C EPRH Event polarity high register REGISTER NAME 01A0 FFA4 CIPRH Channel interrupt pending high register 01A0 FFA8 CIERH Channel interrupt enable high register 01A0 FFAC CCERH Channel chain enable high register 01A0 FFB0 ERH 01A0 FFB4 EERH Event enable high register Event high register 01A0 FFB8 ECRH Event clear high register 01A0 FFBC ESRH Event set high register 01A0 FFC0 PQAR0 Priority queue allocation register 0 01A0 FFC4 PQAR1 Priority queue allocation register 1 01A0 FFC8 PQAR2 Priority queue allocation register 2 01A0 FFCC PQAR3 Priority queue allocation register 3 01A0 FFDC EPRL Event polarity low register 01A0 FFE0 PQSR Priority queue status register 01A0 FFE4 CIPRL Channel interrupt pending low register 01A0 FFE8 CIERL Channel interrupt enable low register 01A0 FFEC CCERL Channel chain enable low register 01A0 FFF0 ERL 01A0 FFF4 EERL Event enable low register Event low register 01A0 FFF8 ECRL Event clear low register 01A0 FFFC ESRL Event set low register 01A1 0000 − 01A3 FFFF – Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 19 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 peripheral register descriptions (continued) Table 8. EDMA Parameter RAM† HEX ADDRESS RANGE ACRONYM REGISTER NAME 01A0 0000 − 01A0 0017 − Parameters for Event 0 (6 words) 01A0 0018 − 01A0 002F − Parameters for Event 1 (6 words) 01A0 0030 − 01A0 0047 − Parameters for Event 2 (6 words) 01A0 0048 − 01A0 005F − Parameters for Event 3 (6 words) 01A0 0060 − 01A0 0077 − Parameters for Event 4 (6 words) 01A0 0078 − 01A0 008F − Parameters for Event 5 (6 words) 01A0 0090 − 01A0 00A7 − Parameters for Event 6 (6 words) 01A0 00A8 − 01A0 00BF − Parameters for Event 7 (6 words) 01A0 00C0 − 01A0 00D7 − Parameters for Event 8 (6 words) 01A0 00D8 − 01A0 00EF − Parameters for Event 9 (6 words) 01A0 00F0 − 01A0 00107 − Parameters for Event 10 (6 words) 01A0 0108 − 01A0 011F − Parameters for Event 11 (6 words) 01A0 0120 − 01A0 0137 − Parameters for Event 12 (6 words) 01A0 0138 − 01A0 014F − Parameters for Event 13 (6 words) 01A0 0150 − 01A0 0167 − Parameters for Event 14 (6 words) 01A0 0168 − 01A0 017F − Parameters for Event 15 (6 words) 01A0 0150 − 01A0 0167 − Parameters for Event 16 (6 words) 01A0 0168 − 01A0 017F − Parameters for Event 17 (6 words) ... COMMENTS ... ... ... 01A0 05D0 − 01A0 05E7 − Parameters for Event 62 (6 words) 01A0 05E8 − 01A0 05FF − Parameters for Event 63 (6 words) 01A0 0600 − 01A0 0617 − Reload/link parameters for Event M (6 words) 01A0 0618 − 01A0 062F − Reload/link parameters for Event N (6 words) ... ... 01A0 07E0 − 01A0 07F7 − 01A0 07F8 − 01A0 07FF − Reload/link parameters for Event Z (6 words) Scratch pad area (2 words) † The C6414T/C6415T/C6416T device has twenty-one parameter sets [six (6) words each] that can be used to reload/link EDMA transfers. Table 9. Quick DMA (QDMA) and Pseudo Registers HEX ADDRESS RANGE ACRONYM 0200 0000 QOPT QDMA options parameter register 0200 0004 QSRC QDMA source address register 0200 0008 QCNT QDMA frame count register 0200 000C QDST QDMA destination address register 0200 0010 QIDX QDMA index register 0200 0014 − 0200 001C 20 REGISTER NAME Reserved 0200 0020 QSOPT QDMA pseudo options register 0200 0024 QSSRC QDMA pseudo source address register 0200 0028 QSCNT QDMA pseudo frame count register 0200 002C QSDST QDMA pseudo destination address register 0200 0030 QSIDX QDMA pseudo index register POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 peripheral register descriptions (continued) Table 10. Interrupt Selector Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 019C 0000 MUXH Interrupt multiplexer high Selects which interrupts drive CPU interrupts 10−15 (INT10−INT15) 019C 0004 MUXL Interrupt multiplexer low Selects which interrupts drive CPU interrupts 4−9 (INT04−INT09) 019C 0008 EXTPOL External interrupt polarity Sets the polarity of the external interrupts (EXT_INT4−EXT_INT7) 019C 000C − 019C 01FF − Reserved Table 11. McBSP 0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 018C 0000 DRR0 McBSP0 data receive register via Configuration Bus 0x3000 0000 − 0x33FF FFFF DRR0 McBSP0 data receive register via Peripheral Bus 018C 0004 DXR0 McBSP0 data transmit register via Configuration Bus 0x3000 0000 − 0x33FF FFFF DXR0 McBSP0 data transmit register via Peripheral Bus 018C 0008 SPCR0 018C 000C RCR0 McBSP0 receive control register 018C 0010 XCR0 McBSP0 transmit control register 018C 0014 SRGR0 COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it. McBSP0 serial port control register McBSP0 sample rate generator register 018C 0018 MCR0 018C 001C RCERE00 McBSP0 multichannel control register McBSP0 enhanced receive channel enable register 0 018C 0020 XCERE00 McBSP0 enhanced transmit channel enable register 0 018C 0024 PCR0 018C 0028 RCERE10 McBSP0 enhanced receive channel enable register 1 018C 002C XCERE10 McBSP0 enhanced transmit channel enable register 1 018C 0030 RCERE20 McBSP0 enhanced receive channel enable register 2 018C 0034 XCERE20 McBSP0 enhanced transmit channel enable register 2 McBSP0 pin control register 018C 0038 RCERE30 McBSP0 enhanced receive channel enable register 3 018C 003C XCERE30 McBSP0 enhanced transmit channel enable register 3 018C 0040 − 018F FFFF – Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 21 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 peripheral register descriptions (continued) Table 12. McBSP 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0190 0000 DRR1 McBSP1 data receive register via Configuration Bus 0x3400 0000 − 0x37FF FFFF DRR1 McBSP1 data receive register via Peripheral Bus 0190 0004 DXR1 McBSP1 data transmit register via Configuration Bus 0x3400 0000 − 0x37FF FFFF DXR1 McBSP1 data transmit register via Peripheral Bus 0190 0008 SPCR1 0190 000C RCR1 McBSP1 receive control register 0190 0010 XCR1 McBSP1 transmit control register 0190 0014 SRGR1 COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it. McBSP1 serial port control register McBSP1 sample rate generator register 0190 0018 MCR1 0190 001C RCERE01 McBSP1 multichannel control register McBSP1 enhanced receive channel enable register 0 0190 0020 XCERE01 McBSP1 enhanced transmit channel enable register 0 0190 0024 PCR1 0190 0028 RCERE11 McBSP1 enhanced receive channel enable register 1 0190 002C XCERE11 McBSP1 enhanced transmit channel enable register 1 0190 0030 RCERE21 McBSP1 enhanced receive channel enable register 2 0190 0034 XCERE21 McBSP1 enhanced transmit channel enable register 2 McBSP1 pin control register 0190 0038 RCERE31 McBSP1 enhanced receive channel enable register 3 0190 003C XCERE31 McBSP1 enhanced transmit channel enable register 3 0190 0040 − 0193 FFFF – Reserved Table 13. McBSP 2 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01A4 0000 DRR2 McBSP2 data receive register via Configuration Bus 0x3800 0000 − 0x3BFF FFFF DRR2 McBSP2 data receive register via Peripheral Bus 01A4 0004 DXR2 McBSP2 data transmit register via Configuration Bus 0x3800 0000 − 0x3BFF FFFF DXR2 McBSP2 data transmit register via Peripheral Bus 01A4 0008 SPCR2 01A4 000C RCR2 McBSP2 receive control register 01A4 0010 XCR2 McBSP2 transmit control register 01A4 0014 SRGR2 22 McBSP2 serial port control register McBSP2 sample rate generator register 01A4 0018 MCR2 01A4 001C RCERE02 McBSP2 multichannel control register McBSP2 enhanced receive channel enable register 0 01A4 0020 XCERE02 McBSP2 enhanced transmit channel enable register 0 01A4 0024 PCR2 01A4 0028 RCERE12 McBSP2 enhanced receive channel enable register 1 01A4 002C XCERE12 McBSP2 enhanced transmit channel enable register 1 01A4 0030 RCERE22 McBSP2 enhanced receive channel enable register 2 01A4 0034 XCERE22 McBSP2 enhanced transmit channel enable register 2 McBSP2 pin control register 01A4 0038 RCERE32 McBSP2 enhanced receive channel enable register 3 01A4 003C XCERE32 McBSP2 enhanced transmit channel enable register 3 01A4 0040 − 01A7 FFFF – Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it. 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 peripheral register descriptions (continued) Table 14. Timer 0 Registers HEX ADDRESS RANGE ACRONYM 0194 0000 CTL0 REGISTER NAME COMMENTS Timer 0 control register Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. 0194 0004 PRD0 Timer 0 period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 0194 0008 CNT0 Timer 0 counter register Contains the current value of the incrementing counter. 0194 000C − 0197 FFFF − Reserved Table 15. Timer 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0198 0000 CTL1 Timer 1 control register Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. 0198 0004 PRD1 Timer 1 period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 0198 0008 CNT1 Timer 1 counter register Contains the current value of the incrementing counter. 0198 000C − 019B FFFF − Reserved Table 16. Timer 2 Registers HEX ADDRESS RANGE 01AC 0000 ACRONYM CTL2 REGISTER NAME COMMENTS Timer 2 control register Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. 01AC 0004 PRD2 Timer 2 period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 01AC 0008 CNT2 Timer 2 counter register Contains the current value of the incrementing counter. 01AC 000C − 01AF FFFF − Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 23 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 peripheral register descriptions (continued) Table 17. HPI Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS − HPID HPI data register Host read/write access only 0188 0000 HPIC HPI control register HPIC has both Host/CPU read/write access 0188 0004 HPIA (HPIAW)† HPI address register (Write) 0188 0008 HPIA (HPIAR)† HPI address register (Read) 0188 000C − 0189 FFFF − 018A 0000 TRCTL 018A 0004 − 018B FFFF − HPIA has both Host/CPU read/write access Reserved HPI transfer request control register Reserved † Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently. Table 18. GPIO Registers 24 HEX ADDRESS RANGE ACRONYM 01B0 0000 GPEN GPIO enable register REGISTER NAME 01B0 0004 GPDIR GPIO direction register 01B0 0008 GPVAL GPIO value register 01B0 000C − 01B0 0010 GPDH GPIO delta high register 01B0 0014 GPHM GPIO high mask register 01B0 0018 GPDL GPIO delta low register 01B0 001C GPLM GPIO low mask register 01B0 0020 GPGC GPIO global control register 01B0 0024 GPPOL GPIO interrupt polarity register 01B0 0028 − 01B0 01FF − 01B0 0200 DEVICE_REV 01B0 0204 − 01B3 FFFF − Reserved Reserved Silicon Revision Identification Register (For more details, see the device characteristics listed in Table 1.) Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 peripheral register descriptions (continued) Table 19. PCI Peripheral Registers (C6415T and C6416T Only)† HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C0 0000 RSTSRC 01C0 0004 − 01C0 0008 PCIIS PCI interrupt source register 01C0 000C PCIIEN PCI interrupt enable register 01C0 0010 DSPMA DSP master address register 01C0 0014 PCIMA PCI master address register 01C0 0018 PCIMC PCI master control register 01C0 001C CDSPA Current DSP address register 01C0 0020 CPCIA Current PCI address register 01C0 0024 CCNT Current byte count register 01C0 0028 − Reserved 01C0 002C − 01C1 FFEF – Reserved 0x01C1 FFF0 HSR 0x01C1 FFF4 HDCR Host-to-DSP control register DSP page register DSP Reset source/status register Reserved Host status register 0x01C1 FFF8 DSPP 0x01C1 FFFC − 01C2 0000 EEADD EEPROM address register 01C2 0004 EEDAT EEPROM data register 01C2 0008 EECTL EEPROM control register 01C2 000C − 01C2 FFFF – 01C3 0000 TRCTL 01C3 0004 − 01C3 FFFF – Reserved Reserved PCI transfer request control register Reserved † These PCI registers are not supported on the C6414T device. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 25 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 peripheral register descriptions (continued) Table 20. UTOPIA (C6415T and C6416T Only)† HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B4 0000 UCR 01B4 0004 − Reserved 01B4 0008 − Reserved 01B4 000C UIER UTOPIA interrupt enable register 01B4 0010 UIPR UTOPIA interrupt pending register 01B4 0014 CDR Clock detect register 01B4 0018 EIER Error interrupt enable register 01B4 001C EIPR Error interrupt pending register 01B4 0020 − 01B7 FFFF − UTOPIA control register Reserved † These UTOPIA registers are not supported on the C6414T device. Table 21. UTOPIA QUEUES (C6415T and C6416T Only)† HEX ADDRESS RANGE ACRONYM 3C00 0000 URQ UTOPIA receive queue REGISTER NAME 3D00 0000 UXQ UTOPIA transmit queue 3D00 0004 − 3FFF FFFF − Reserved † These UTOPIA registers are not supported on the C6414T device. 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 peripheral register descriptions (continued) Table 22. VCP Registers (C6416T Only)† EDMA BUS HEX ADDRESS RANGE PERIPHERAL BUS HEX ADDRESS RANGE ACRONYM 5000 0000 01B8 0000 VCPIC0 VCP input configuration register 0 5000 0004 01B8 0004 VCPIC1 VCP input configuration register 1 5000 0008 01B8 0008 VCPIC2 VCP input configuration register 2 5000 000C 01B8 000C VCPIC3 VCP input configuration register 3 5000 0010 01B8 0010 VCPIC4 VCP input configuration register 4 5000 0014 01B8 0014 VCPIC5 VCP input configuration register 5 5000 0040 01B8 0024 VCPOUT0 VCP output register 0 5000 0044 01B8 0028 VCPOUT1 VCP output register 1 5000 0080 − VCPWBM VCP branch metrics write register 5000 0088 − VCPRDECS − 01B8 0018 VCPEXE VCP execution register − 01B8 0020 VCPEND VCP endian register − 01B8 0040 VCPSTAT0 VCP status register 0 − 01B8 0044 VCPSTAT1 VCP status register 1 − 01B8 0050 VCPERR REGISTER NAME VCP decisions read register VCP error register † These VCP registers are supported on the C6416T device only. Table 23. TCP Registers (C6416T Only)‡ EDMA BUS HEX ADDRESS RANGE PERIPHERAL BUS HEX ADDRESS RANGE ACRONYM 5800 0000 01BA 0000 TCPIC0 TCP input configuration register 0 5800 0004 01BA 0004 TCPIC1 TCP input configuration register 1 5800 0008 01BA 0008 TCPIC2 TCP input configuration register 2 5800 000C 01BA 000C TCPIC3 TCP input configuration register 3 5800 0010 01BA 0010 TCPIC4 TCP input configuration register 4 5800 0014 01BA 0014 TCPIC5 TCP input configuration register 5 5800 0018 01BA 0018 TCPIC6 TCP input configuration register 6 5800 001C 01BA 001C TCPIC7 TCP input configuration register 7 5800 0020 01BA 0020 TCPIC8 TCP input configuration register 8 5800 0024 01BA 0024 TCPIC9 TCP input configuration register 9 5800 0028 01BA 0028 TCPIC10 TCP input configuration register 10 5800 002C 01BA 002C TCPIC11 TCP input configuration register 11 5800 0030 01BA 0030 TCPOUT TCP output parameters register 5802 0000 − TCPSP 5804 0000 − TCPEXT 5806 0000 − TCPAP 5808 0000 − TCPINTER REGISTER NAME TCP systematics and parities memory TCP extrinsics memory TCP apriori memory TCP interleaver memory 580A 0000 − TCPHD TCP hard decisions memory − 01BA 0038 TCPEXE TCP execution register − 01BA 0040 TCPEND TCP endian register − 01BA 0050 TCPERR TCP error register − 01BA 0058 TCPSTAT TCP status register ‡ These TCP registers are supported on the C6416T device only. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 27 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 EDMA channel synchronization events The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory. Table 24 lists the source of C64x EDMA synchronization events associated with each of the programmable EDMA channels. For the C64x device, the association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL, EERH). The priority of each event can be specified independently in the transfer parameters stored in the EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234). 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 EDMA channel synchronization events (continued) Table 24. TMS320C64x EDMA Channel Synchronization Events† EDMA CHANNEL EVENT NAME 0 DSP_INT 1 TINT0 Timer 0 interrupt 2 TINT1 Timer 1 interrupt 3 SD_INTA 4 GPINT4/EXT_INT4 GPIO event 4/External interrupt pin 4 5 GPINT5/EXT_INT5 GPIO event 5/External interrupt pin 5 6 GPINT6/EXT_INT6 GPIO event 6/External interrupt pin 6 7 GPINT7/EXT_INT7 GPIO event 7/External interrupt pin 7 8 GPINT0 GPIO event 0 9 GPINT1 GPIO event 1 10 GPINT2 GPIO event 2 11 GPINT3 GPIO event 3 12 XEVT0 McBSP0 transmit event 13 REVT0 McBSP0 receive event 14 XEVT1 McBSP1 transmit event 15 REVT1 McBSP1 receive event 16 – 17 XEVT2 McBSP2 transmit event 18 REVT2 McBSP2 receive event 19 TINT2 Timer 2 interrupt 20 SD_INTB EMIFB SDRAM timer interrupt 21 – Reserved, for future expansion 22−27 – None 28 VCPREVT 29 VCPXEVT 30 TCPREVT 31 TCPXEVT 32 UREVT EVENT DESCRIPTION HPI/PCI-to-DSP interrupt (PCI peripheral supported on C6415T and C6416T only)‡ EMIFA SDRAM timer interrupt None VCP receive event (C6416T only)§ VCP transmit event (C6416T only)§ TCP receive event (C6416T only)§ TCP transmit event (C6416T only)§ UTOPIA receive event (C6415T and C6416T only)‡ 33−39 – 40 UXEVT None 41−47 – 48 GPINT8 GPIO event 8 49 GPINT9 GPIO event 9 50 GPINT10 GPIO event 10 51 GPINT11 GPIO event 11 52 GPINT12 GPIO event 12 53 GPINT13 GPIO event 13 54 GPINT14 GPIO event 14 55 GPINT15 GPIO event 15 56−63 – UTOPIA transmit event (C6415T and C6416T only)‡ None None † In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234). ‡ The PCI and UTOPIA peripherals are not supported on the C6414T device; therefore, these EDMA synchronization events are reserved. § The VCP/TCP EDMA synchronization events are supported on the C6416T only. For the C6414T and C6415T devices, these events are reserved. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 29 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 interrupt sources and interrupt selector The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 25. The highest-priority interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts (INT_00−INT_03) are non-maskable and fixed. The remaining interrupts (INT_04−INT_15) are maskable and default to the interrupt source specified in Table 25. The interrupt source for interrupts 4−15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004). 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 interrupt sources and interrupt selector (continued) Table 25. C64x DSP Interrupts INTERRUPT SELECTOR CONTROL REGISTER SELECTOR VALUE (BINARY) INTERRUPT EVENT INT_00† INT_01† − − RESET − − NMI INT_02† INT_03† − − Reserved Reserved. Do not use. − − Reserved Reserved. Do not use. INT_04‡ INT_05‡ MUXL[4:0] 00100 GPINT4/EXT_INT4 GPIO interrupt 4/External interrupt pin 4 MUXL[9:5] 00101 GPINT5/EXT_INT5 GPIO interrupt 5/External interrupt pin 5 INT_06‡ INT_07‡ MUXL[14:10] 00110 GPINT6/EXT_INT6 GPIO interrupt 6/External interrupt pin 6 MUXL[20:16] 00111 GPINT7/EXT_INT7 GPIO interrupt 7/External interrupt pin 7 INT_08‡ INT_09‡ MUXL[25:21] 01000 EDMA_INT EDMA channel (0 through 63) interrupt MUXL[30:26] 01001 EMU_DTDMA INT_10‡ MUXH[4:0] 00011 SD_INTA INT_11‡ MUXH[9:5] 01010 EMU_RTDXRX EMU real-time data exchange (RTDX) receive INT_12‡ MUXH[14:10] 01011 EMU_RTDXTX EMU RTDX transmit INT_13‡ MUXH[20:16] 00000 DSP_INT INT_14‡ INT_15‡ MUXH[25:21] 00001 TINT0 Timer 0 interrupt MUXH[30:26] 00010 TINT1 Timer 1 interrupt − − 01100 XINT0 McBSP0 transmit interrupt − − 01101 RINT0 McBSP0 receive interrupt − − 01110 XINT1 McBSP1 transmit interrupt − − 01111 RINT1 McBSP1 receive interrupt − − 10000 GPINT0 − − 10001 XINT2 McBSP2 transmit interrupt − − 10010 RINT2 McBSP2 receive interrupt − − 10011 TINT2 Timer 2 interrupt − − 10100 SD_INTB EMIFB SDRAM timer interrupt − − 10101 Reserved Reserved. Do not use. − − 10110 Reserved Reserved. Do not use. − − 10111 UINT − − 11000 − 11101 Reserved − − 11110 VCPINT VCP interrupt (C6416T only) − − 11111 TCPINT TCP interrupt (C6416T only) CPU INTERRUPT NUMBER INTERRUPT SOURCE EMU DTDMA EMIFA SDRAM timer interrupt HPI/PCI-to-DSP interrupt (PCI supported on C6415T and C6416T) GPIO interrupt 0 UTOPIA interrupt (C6415T/C6416T only) Reserved. Do not use. † Interrupts INT_00 through INT_03 are non-maskable and fixed. ‡ Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields. Table 25 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and selection, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 31 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 signal groups description CLKIN CLKOUT4/GP1† CLKOUT6/GP2† CLKMODE1 CLKMODE0 PLLV TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 EMU6 EMU7 EMU8 EMU9 EMU10 EMU11 Reset and Interrupts Clock/PLL Reserved IEEE Standard 1149.1 (JTAG) Emulation RESET NMI GP7/EXT_INT7‡ GP6/EXT_INT6‡ GP5/EXT_INT5‡ GP4/EXT_INT4‡ RSV RSV RSV RSV RSV RSV • • • RSV RSV RSV Peripheral Control/Status PCI_EN MCBSP2_EN Control/Status GP15/PRST§ GP14/PCLK§ GP13/PINTA§ GP12/PGNT§ GP11/PREQ§ GP10/PCBE3§ GP9/PIDSEL§ CLKS2/GP8† GPIO GP7/EXT_INT7‡ GP6/EXT_INT6‡ GP5/EXT_INT5‡ GP4/EXT_INT4‡ GP3 CLKOUT6/GP2† CLKOUT4/GP1† GP0 General-Purpose Input/Output (GPIO) Port † These pins are muxed with the GPIO port pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6) or McBSP2 clock source (CLKS2). To use these muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly enabled and configured. For more details, see the Device Configurations section of this data sheet. ‡ These pins are GPIO pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or GPIO as input-only. § For the C6415T and C6416T devices, these GPIO pins are muxed with the PCI peripheral pins. By default, these signals are set up to no function with both the GPIO and PCI pin functions disabled. For more details on these muxed pins, see the Device Configurations section of this data sheet. For the C6414T device, the GPIO peripheral pins are not muxed; the C6414T device does not support the PCI peripheral. Figure 3. CPU and Peripheral Signals 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 signal groups description (continued) 64 Data AED[63:0] AECLKIN ACE3 ACE2 Memory Map Space Select ACE1 ACE0 20 AEA[22:3] External Memory I/F Control Address ABE7 ABE6 ABE5 ABE4 Byte Enables ABE3 ABE2 ABE1 ABE0 Bus Arbitration AECLKOUT1 AECLKOUT2 ASDCKE AARE/ASDCAS/ASADS/ASRE AAOE/ASDRAS/ASOE AAWE/ASDWE/ASWE AARDY ASOE3 APDT AHOLD AHOLDA ABUSREQ EMIFA (64-bit)† 16 Data BED[15:0] BECLKIN BECLKOUT1 BECLKOUT2 BCE3 BCE2 BCE1 BCE0 Memory Map Space Select External Memory I/F Control 20 BEA[20:1] BBE1 BBE0 BARE/BSDCAS/BSADS/BSRE BAOE/BSDRAS/BSOE BAWE/BSDWE/BSWE BARDY BSOE3 BPDT Address Byte Enables Bus Arbitration BHOLD BHOLDA BBUSREQ EMIFB (16-bit)† † These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name. Figure 4. Peripheral Signals POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 33 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 signal groups description (continued) 32 HPI† (Host-Port Interface) Data HD[31:0]/AD[31:0] HCNTL0/PSTOP HCNTL1/PDEVSEL Register Select Control Half-Word Select HHWIL/PTRDY (HPI16 ONLY) HAS/PPAR HR/W/PCBE2 HCS/PPERR HDS1/PSERR HDS2/PCBE1 HRDY/PIRDY HINT/PFRAME 32 HD[31:0]/AD[31:0] GP10/PCBE3 HR/W/PCBE2 HDS2/PCBE1 PCBE0§ GP12/PGNT Data/Address Clock Command Byte Enable Control Arbitration Error GP11/PREQ Serial EEPROM GP14/PCLK GP9/PIDSEL HCNTL1/PDEVSEL HINT/PFRAME GP13/PINTA HAS/PPAR GP15/PRST HRDY/PIRDY HCNTL0/PSTOP HHWIL/PTRDY HDS1/PSERR HCS/PPERR DX2/XSP_DO XSP_CS§ CLKX2/XSP_CLK DR2/XSP_DI PCI Interface‡ (C6415T and C6416T Only † For the C6415T and C6416T devices, these HPI pins are muxed with the PCI peripheral. By default, these signals function as HPI. For more details on these muxed pins, see the Device Configurations section of this data sheet. For the C6414 device, these HPI pins are not muxed; the C6414T device does not support the PCI peripheral. ‡ For the C6415T and C6416T devices, these PCI pins (excluding PCBE0 and XSP_CS) are muxed with the HPI, McBSP2, or GPIO peripherals. By default, these signals function as HPI, McBSP2, and no function, respectively. For more details on these muxed pins, see the Device Configurations section of this data sheet. For the C6414T device, the HPI, McBSP2, and GPIO peripheral pins are not muxed; the C6414T device does not support the PCI peripheral. § For the C6414T device, these pins are “Reserved (leave unconnected, do not connect to power or ground).” Figure 4. Peripheral Signals (Continued) 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 signal groups description (continued) McBSP1 McBSP0 CLKX1/URADDR4† FSX1/UXADDR3† DX1/UXADDR4† Transmit Transmit CLKR1/URADDR2† FSR1/UXADDR2† DR1/UXADDR1† Receive Receive CLKS1/URADDR3† Clock CLKX0 FSX0 DX0 CLKR0 FSR0 DR0 Clock CLKS0 McBSP2 CLKX2/XSP_CLK† FSX2 DX2/XSP_DO† Transmit CLKR2 FSR2 DR2/XSP_DI† Receive CLKS2/GP8‡ Clock McBSPs (Multichannel Buffered Serial Ports) † For the C6415T and C6416T devices, these McBSP2 and McBSP1 pins are muxed with the PCI and UTOPIA peripherals, respectively. By default, these signals function as McBSP2 and McBSP1, respectively. For more details on these muxed pins, see the Device Configurations section of this data sheet. For the C6414T device, these McBSP2 and McBSP1 peripheral pins are not muxed; the C6414T device does not support PCI and UTOPIA peripherals. ‡ The McBSP2 clock source pin (CLKS2, default) is muxed with the GP8 pin. To use this muxed pin as the GP8 signal, the appropriate GPIO register bits (GP8EN and GP8DIR) must be properly enabled and configured. For more details, see the Device Configurations section of this data sheet. Figure 4. Peripheral Signals (Continued) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 35 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 signal groups description (continued) UTOPIA (SLAVE) [C6415T and C6416T Only] URDATA7 URDATA6 URDATA5 URDATA4 URDATA3 URDATA2 Receive Transmit URDATA1 URDATA0 URENB CLKX1/URADDR4† CLKS1/URADDR3† CLKR1/URADDR2† URADDR1 URADDR0 URCLAV URSOC UXDATA7 UXDATA6 UXDATA5 UXDATA4 UXDATA3 UXDATA2 UXDATA1 UXDATA0 Control/Status Control/Status UXENB DX1/UXADDR4† FSX1/UXADDR3† FSR1/UXADDR2† DR1/UXADDR1† UXADDR0 UXCLAV UXSOC URCLK Clock TOUT1 TINP1 Timer 1 TOUT2 TINP2 Timer 2 Clock Timer 0 UXCLK TOUT0 TINP0 Timers † For the C6415T and C6416T devices, these UTOPIA pins are muxed with the McBSP1 peripheral. By default, these signals function as McBSP1. For more details on these muxed pins, see the Device Configurations section of this data sheet. For the C6414T device, these McBSP1 peripheral pins are not muxed; the C6414T does not support the UTOPIA peripheral. Figure 4. Peripheral Signals (Continued) 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 DEVICE CONFIGURATIONS The C6414T, C6415T, and C6416T device configurations are determined by external pullup/pulldown resistors on the following pins (all of which are latched during device reset):
peripherals selection (C6415T and C6416T devices) − BEA11 (UTOPIA_EN) − PCI_EN (for C6415T or C6416T, see Table 27 footnotes) − MCBSP2_EN (for C6415T or C6416T, see Table 27 footnotes) The C6414T device does not support the PCI and UTOPIA peripherals; for proper operation of the C6414T device, do not oppose the internal pulldowns (IPDs) on the BEA11, PCI_EN, and MCBSP2_EN pins. (For IPUs/IPDs on pins, see the Terminal Functions table of this data sheet.)
other device configurations (C64x) − BEA[20:13, 7] − HD5 peripherals selection Some C6415T/C6416T peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI, general-purpose input/output pins GP[15:9], PCI and its internal EEPROM, McBSP1, McBSP2, and UTOPIA). The VCP/TCP coprocessors (C6416T only) and other C64x peripherals (i.e., the Timers, McBSP0, and the GP[8:0] pins), are always available.
UTOPIA and McBSP1 peripherals The UTOPIA_EN pin (BEA11) is latched at reset. For C6415T and C6416T devices, this pin selects whether the UTOPIA peripheral or McBSP1 peripheral is functionally enabled (see Table 26). The C6414T device does not support the UTOPIA peripheral; for proper device operation, do not oppose the internal pulldown (IPD) on the BEA11 pin. Table 26. UTOPIA_EN Peripheral Selection (McBSP1 and UTOPIA) (C6415T/C6416T Only) PERIPHERAL SELECTION UTOPIA_EN (BEA11) Pin [D16] PERIPHERALS SELECTED UTOPIA √ 0 1 √ DESCRIPTION McBSP1 McBSP1 is enabled and UTOPIA is disabled [default]. This means all multiplexed McBSP1/UTOPIA pins function as McBSP1 and all other standalone UTOPIA pins are tied-off (Hi-Z). UTOPIA is enabled and McBSP1 is disabled. This means all multiplexed McBSP1/UTOPIA pins now function as UTOPIA and all other standalone McBSP1 pins are tied-off (Hi-Z).
HPI, GP[15:9], PCI, EEPROM (internal to PCI), and McBSP2 peripherals The PCI_EN and MCBSP2_EN pins are latched at reset. They determine specific peripheral selection for the C6415T and C6416T devices, summarized in Table 27. The C6414T device does not support the PCI peripheral; for proper device operation, do not oppose the internal pulldowns (IPDs) on the PCI_EN and MCBSP2_EN pins. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 37 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 DEVICE CONFIGURATIONS (CONTINUED) Table 27. PCI_EN and MCBSP2_EN Peripheral Selection (HPI, GP[15:9], PCI, and McBSP2) PERIPHERAL SELECTION† PERIPHERALS SELECTED PCI_EN Pin [AA4] MCBSP2_EN Pin [AF3] HPI GP[15:9] 0 0 √ √ √ 0 1 √ √ 1 0 √ ‡ PCI √ EEPROM (Internal to PCI) √ McBSP2 √ † The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation. The MCBSP2_EN pin must be driven valid at all times and the user can switch values throughout device operation. ‡ The only time McBSP2 is disabled is when both PCI_EN = 1 and MCBSP2_EN = 0. This configuration enables, at reset, the auto-initialization of the PCI peripheral through the PCI internal EEPROM [provided the PCI EEPROM Auto-Initialization pin (BEA13) is pulled up (EEAI = 1)]. The user can then enable the McBSP2 peripheral (disabling EEPROM) by dynamically changing MCBSP2_EN to a “1” after the device is initialized (out of reset). 1 √ 1 − If the PCI is disabled (PCI_EN = 0), the HPI peripheral is enabled and GP[15:9] pins can be programmed as GPIO, provided the GPxEN and GPxDIR bits are properly configured. [Note: The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation.] This means all multiplexed HPI/PCI pins function as HPI and all standalone PCI pins (PCBE0 and XSP_CS) are tied-off (Hi-Z). Also, the multiplexed GPIO/PCI pins can be used as GPIO with the proper software configuration of the GPIO enable and direction registers (for more details, see Table 29). − If the PCI is enabled (PCI_EN = 1), the HPI peripheral is disabled. [Note: The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation.] This means all multiplexed HPI/PCI pins function as PCI. Also, the multiplexed GPIO/PCI pins function as PCI pins (for more details, see Table 29). − The MCBSP2_EN pin, in combination with the PCI_EN pin, controls the selection of the McBSP2 peripheral and the PCI internal EEPROM (for more details, see Table 27 and its footnotes). [Note: The MCBSP2_EN pin must be driven valid at all times and the user can switch values throughout device operation.] other device configurations Table 28 describes the C6414T, C6415T, and C6416T devices configuration pins, which are set up via external pullup/pulldown resistors through the specified EMIFB address bus pins (BEA[20:13, 11, 9:7]) and the HD5 pin. For more details on these device configuration pins, see the Terminal Functions table and the Debugging Considerations section. 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 DEVICE CONFIGURATIONS (CONTINUED) Table 28. Device Configuration Pins (BEA[20:13, 9:7], HD5, and BEA11) CONFIGURATION PIN NO. BEA20 E16 BEA[19:18] BEA[17:16] BEA[15:14] BEA13 FUNCTIONAL DESCRIPTION Device Endian mode (LEND) 0 – System operates in Big Endian mode 1 − System operates in Little Endian mode (default) [D18, C18] Bootmode [1:0] 00 – No boot 01 − HPI boot 10 − EMIFB 8-bit ROM boot with default timings (default mode) 11 − Reserved [B18, A18] EMIFA input clock select Clock mode select for EMIFA (AECLKIN_SEL[1:0]) 00 – AECLKIN (default mode) 01 − CPU/4 Clock Rate 10 − CPU/6 Clock Rate 11 − Reserved [D17, C17] EMIFB input clock select Clock mode select for EMIFB (BECLKIN_SEL[1:0]) 00 – BECLKIN (default mode) 01 − CPU/4 Clock Rate 10 − CPU/6 Clock Rate 11 − Reserved B17 PCI EEPROM Auto-Initialization (EEAI) [C6415T and C6416T devices only] [The C6414T device does not support the PCI peripheral; for proper device operation, do not oppose the internal pulldown (IPD) on the BEA13 pin.] PCI auto-initialization via external EEPROM 0 − PCI auto-initialization through EEPROM is disabled; the PCI peripheral uses the specified PCI default values (default). 1 − PCI auto-initialization through EEPROM is enabled; the PCI peripheral is configured through EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1) and the McBSP2 peripheral pin is disabled (MCBSP2_EN = 0). Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up. For more information on the PCI EEPROM default values, see the TMS320C6000 DSP Peripheral Component Interconnect (PCI) Reference Guide (literature number SPRU581). UTOPIA Enable (UTOPIA_EN) [C6415T and C6416T devices only] [The C6414T device does not support the UTOPIA peripheral; for proper device operation, do not oppose the internal pulldown (IPD) on the BEA11 pin.] UTOPIA peripheral enable (functional) BEA11 D16 0 − UTOPIA peripheral disabled (McBSP1 functions are enabled). [default] This means all multiplexed McBSP1/UTOPIA pins function as McBSP1 and all other standalone UTOPIA pins are tied-off (Hi-Z). 1 − UTOPIA peripheral enabled (McBSP1 functions are disabled). This means all multiplexed McBSP1/UTOPIA pins now function as UTOPIA and all other standalone McBSP1 pins are tied-off (Hi-Z). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 39 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 DEVICE CONFIGURATIONS (CONTINUED) Table 28. Device Configuration Pins (BEA[20:13, 9:7], HD5, and BEA11) (Continued) CONFIGURATION PIN NO. FUNCTIONAL DESCRIPTION C6414T Devices BEA7 BEA8 BEA9 D15 A16 B16 C6415T Devices Do not oppose internal pulldown (IPD) Pullup† Do not oppose IPD Do not oppose IPD Do not oppose IPD Do not oppose IPD C6416T Devices Do not oppose IPD Pullup† Pullup† †For proper device operation, this pin must be externally pulled up with a 1-kΩ resistor. HD5 Y1 HPI peripheral bus width (HPI_WIDTH) 0 − HPI operates as an HPI16. (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the Hi-Z state.) 1 − HPI operates as an HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) multiplexed pins Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Some of these pins are configured by software, and the others are configured by external pullup/pulldown resistors only at reset. Those muxed pins that are configured by software can be programmed to switch functionalities at any time. Those muxed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. Table 29 identifies the multiplexed pins on the C6414T, C6415T, and C6416T devices; shows the default (primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to configure specific multiplexed functions. debugging considerations It is recommended that external connections be provided to device configuration pins, including CLKMODE[1:0], BEA[20:13, 11, 9:7], HD5/AD5, PCI_EN, and MCBSP2_EN. Although internal pullup/pulldown resistors exist on these pins (except for HD5/AD5), providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. Internal pullup/pulldown resistors also exist on the non-configuration pins on the BEA bus (BEA[12, 10, 6:1]). Do not oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown resistors. If an external controller provides signals to these non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven at all. For the internal pullup/pulldown resistors on the C6414T, C6415T, and C6416T device pins, see the terminal functions table. 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 DEVICE CONFIGURATIONS (CONTINUED) Table 29. C6414T, C6415T, and C6416T Device Multiplexed Pins† MULTIPLEXED PINS NAME NO. DEFAULT FUNCTION DEFAULT SETTING CLKOUT4/GP1‡ AE6 CLKOUT4 GP1EN = 0 (disabled) CLKOUT6/GP2‡ AD6 CLKOUT6 GP2EN = 0 (disabled) CLKS2/GP8‡ AE4 CLKS2 GP8EN = 0 (disabled) GP9/PIDSEL M3 GP10/PCBE3 L2 GP11/PREQ F1 GP12/PGNT J3 GP13/PINTA G4 GP14/PCLK F2 GP15/PRST None AB11 DX1 FSX1/UXADDR3 AB13 FSX1 FSR1/UXADDR2 AC9 FSR1 DR1/UXADDR1 AF11 DR1 CLKX1/URADDR4 AB12 CLKX1 CLKS1/URADDR3 AC8 CLKS1 CLKR1/URADDR2 AC10 CLKR1 CLKX2/XSP_CLK AC2 CLKX2 DR2/XSP_DI AB3 DR2 DX2/XSP_DO AA2 ‡ DX2 HAS/PPAR T3 HAS HCNTL1/PDEVSEL R1 HCNTL1 HCNTL0/PSTOP T4 HCNTL0 HDS1/PSERR T1 HDS1 HDS2/PCBE1 T2 HDS2 HR/W/PCBE2 P1 HR/W HHWIL/PTRDY R3 HHWIL (HPI16 only) HINT/PFRAME R4 HINT HCS/PPERR R2 HCS HD[31:0]/AD[31:0] These pins are software-configurable. To use these pins as GPIO pins, the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input GPxDIR = 1: GPx pin is an output GPxEN = 0 (disabled) PCI_EN = 0 (disabled)† To use GP[15:9] as GPIO pins, the PCI needs to be disabled (PCI_EN = 0), the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input GPxDIR = 1: GPx pin is an output UTOPIA_EN (BEA11) = 0 (disabled)† By default, McBSP1 is enabled upon reset (UTOPIA is disabled). To enable the UTOPIA peripheral, an external pullup resistor (1 kΩ) must be provided on the BEA11 pin (setting UTOPIA_EN = 1 at reset). PCI_EN = 0 (disabled)† By default, HPI is enabled upon reset (PCI is disabled). To enable the PCI peripheral an external pullup resistor (1 kkΩ)) must be provided on the PCI_EN pin (setting PCI_EN = 1 at reset). G3 DX1/UXADDR4 DESCRIPTION HD[31:0] HRDY/PIRDY P4 HRDY † For the C6415T and C6416T devices, all other standalone UTOPIA and PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled [UTOPIA_EN (BEA11) = 0 or PCI_EN = 0]. ‡ The C6414T device does not support the PCI and UTOPIA peripherals. These are the only multiplexed pins on the C6414T device, all other pins are standalone peripheral functions and are not muxed. § For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 41 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions SIGNAL NAME TYPE† IPD/ IPU‡ H4 I IPD Clock Input. This clock is the input to the on-chip PLL. CLKOUT4/GP1§ AE6 I/O/Z IPD Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 1 pin (I/O/Z). CLKOUT6/GP2§ AD6 I/O/Z IPD Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 2 pin (I/O/Z). CLKMODE1 G1 I IPD CLKMODE0 H2 I IPD PLLV¶ J6 A# NO. DESCRIPTION CLOCK/PLL CONFIGURATION CLKIN Clock mode select • Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x6, or x12, or x20. For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this data sheet. PLL voltage supply JTAG EMULATION TMS AB16 I IPU JTAG test-port mode select TDO AE19 O/Z IPU JTAG test-port data out TDI AF18 I IPU JTAG test-port data in TCK AF16 I IPU JTAG test-port clock TRST AB15 I IPD JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG Compatibility Statement section of this data sheet. EMU11 AC18 I/O/Z IPU Emulation pin 11. Reserved for future use, leave unconnected. EMU10 AD18 I/O/Z IPU Emulation pin 10. Reserved for future use, leave unconnected. EMU9 AE18 I/O/Z IPU Emulation pin 9. Reserved for future use, leave unconnected. EMU8 AC17 I/O/Z IPU Emulation pin 8. Reserved for future use, leave unconnected. EMU7 AF17 I/O/Z IPU Emulation pin 7. Reserved for future use, leave unconnected. EMU6 AD17 I/O/Z IPU Emulation pin 6. Reserved for future use, leave unconnected. EMU5 AE17 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected. EMU4 AC16 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected. EMU3 AD16 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected. EMU2 AE16 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected. EMU1 EMU0 AC15 AF15 I/O/Z IPU Emulation [1:0] pins • Select the device functional mode of operation Operation EMU[1:0] 00 Boundary Scan/Normal Mode (see Note) 01 Reserved 10 Reserved 11 Emulation/Normal Mode [default] (see the IEEE 1149.1 JTAG Compatibility Statement section of this data sheet) Normal mode refers to the DSPs normal operational mode, when the DSP is free running. The DSP can be placed in normal operational mode when the EMU[1:0] pins are configured for either Boundary Scan or Emulation. Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the internal pulldown (IPD) on the TRST signal must not be opposed in order to operate in Normal mode. For the Boundary Scan mode pulldown EMU[1:0] pins with a dedicated 1-kΩ resistor. † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. ¶ PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin. # A = Analog signal (PLL Filter) 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS RESET AC7 I Device reset Nonmaskable interrupt, edge-driven (rising edge) NMI B4 I IPD Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is not used, it is recommended that the NMI pin be grounded versus relying on the IPD. GP7/EXT_INT7 AF4 GP6/EXT_INT6 AD5 GP5/EXT_INT5 AE5 GP4/EXT_INT4 GP15/PRST§ AF5 General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The default after reset setting is GPIO enabled as input-only. • When these pins function as External Interrupts [by selecting the corresponding interrupt enable register bit (IER.[7:4])], they are edge-driven and the polarity can be independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]). G3 General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default. GP14/PCLK§ GP13/PINTA§ GP12/PGNT§ GP11/PREQ§ I/O/Z IPU F2 GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default. G4 GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default. J3 GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default. F1 GP10/PCBE3§ GP9/PIDSEL§ M3 GP3 AC6 L2 GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default. GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default. I/O/Z GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default. IPD GPIO 3 pin (I/O/Z). The default after reset setting is GPIO 3 enabled as input-only. IPD GPIO 0 pin. The general-purpose I/O 0 pin (GPIO 0) (I/O/Z) can be programmed as GPIO 0 (input only) [default] or as GPIO 0 (output only) pin or output as a general-purpose interrupt (GP0INT) signal (output only). GP0 AF6 CLKS2/GP8§¶ AE4 I/O/Z IPD McBSP2 external clock source (CLKS2) [input only] [default] or this pin can be programmed as a GPIO 8 pin (I/O/Z). CLKOUT6/GP2§¶ AD6 I/O/Z IPD Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 2 pin (I/O/Z). CLKOUT4/GP1§¶ AE6 I/O/Z IPD Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 1 pin (I/O/Z). HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415T or C6416T devices only] PCI_EN IPD PCI enable pin. This pin controls the selection (enable/disable) of the HPI and GP[15:9], or PCI peripherals. This pin works in conjunction with the MCBSP2_EN pin to enable/disable other peripherals (for more details, see the Device Configurations section of this data sheet). AA4 I HINT/PFRAME§ R4 I/O/Z Host interrupt from DSP to host (O) [default] or PCI frame (I/O/Z) HCNTL1/ PDEVSEL§ R1 I/O/Z Host control − selects between control, address, or data registers (I) [default] or PCI device select (I/O/Z). HCNTL0/ PSTOP§ T4 I/O/Z Host control − selects between control, address, or data registers (I) [default] or PCI stop (I/O/Z) HHWIL/PTRDY§ R3 I/O/Z Host half-word select − first or second half-word (not necessarily high or low order) [For HPI16 bus width selection only] (I) [default] or PCI target ready (I/O/Z) HR/W/PCBE2§ P1 I/O/Z Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z) † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § For the C6415T and C6416T devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414T device does not support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions for this device. ¶ For the C6414T device, only these pins are multiplexed pins. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 43 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415T or C6416T devices only] (CONTINUED) HAS/PPAR§ T3 I/O/Z Host address strobe (I) [default] or PCI parity (I/O/Z) HCS/PPERR§ HDS1/PSERR§ R2 I/O/Z Host chip select (I) [default] or PCI parity error (I/O/Z) T1 I/O/Z Host data strobe 1 (I) [default] or PCI system error (I/O/Z) HDS2/PCBE1§ HRDY/PIRDY§ T2 I/O/Z Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z) P4 I/O/Z Host ready from DSP to host (O) [default] or PCI initiator ready (I/O/Z). HD31/AD31§ HD30/AD30§ K3 HD29/AD29§ HD28/AD28§ K4 J2 J1 HD27/AD27§ HD26/AD26§ K2 HD25/AD25§ HD24/AD24§ K1 HD23/AD23§ HD22/AD22§ L3 L4 L1 Host-port data (I/O/Z) [default] (C64x) or PCI data-address bus (I/O/Z) [C6415T and C6416T] M4 HD21/AD21§ HD20/AD20§ M2 HD19/AD19§ HD18/AD18§ M1 HD17/AD17§ HD16/AD16§ N1 HD15/AD15§ HD14/AD14§ U4 HD13/AD13§ HD12/AD12§ U3 HD11/AD11§ HD10/AD10§ V4 HD9/AD9§ HD8/AD8§ V3 HD7/AD7§ HD6/AD6§ W2 HD5/AD5§ HD4/AD4§ Y1 HD3/AD3§ HD2/AD2§ Y2 HD1/AD1§ HD0/AD0§ AA1 As HPI data bus (PCI_EN pin = 0) • Used for transfer of data, address, and control • Host-Port bus width user-configurable at device reset via a 10-kΩ resistor pullup/pulldown resistor on the HD5 pin: N4 N5 P5 U1 U2 V1 I/O/Z HD5 pin = 0: HPI operates as an HPI16. (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the high-impedance state.) HD5 pin = 1: HPI operates as an HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) As PCI data-address bus (PCI_EN pin = 1) [C6415T and C6416T devices only] • Used for transfer of data and address The C6414T device does not support the PCI peripheral; therefore, the HPI peripheral pins are standalone peripheral functions, not muxed. V2 W4 Y3 Y4 AA3 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § For the C6415T and C6416T devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414T device does not support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions for this device. 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415T or C6416T devices only] (CONTINUED) PCI command/byte enable 0 (I/O/Z). When PCI is disabled (PCI_EN = 0), this pin is tied-off. For the C6414T device this pin is “Reserved (leave unconnected, do not connect to power or ground).” PCBE0 W3 I/O/Z XSP_CS AD1 O IPD PCI serial interface chip select (O). When PCI is disabled (PCI_EN = 0), this pin is tied-off. For the C6414T device this pin is “Reserved (leave unconnected, do not connect to power or ground).” CLKX2/ XSP_CLK§ AC2 I/O/Z IPD McBSP2 transmit clock (I/O/Z) [default] or PCI serial interface clock (O). DR2/XSP_DI§ AB3 I IPU McBSP2 receive data (I) [default] or PCI serial interface data in (I). In PCI mode, this pin is connected to the output data pin of the serial PROM. DX2/XSP_DO§ AA2 O/Z IPU McBSP2 transmit data (O/Z) [default] or PCI serial interface data out (O). In PCI mode, this pin is connected to the input data pin of the serial PROM. GP15/PRST§ GP14/PCLK§ G3 General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default. F2 GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default. GP13/PINTA§ GP12/PGNT§ G4 GP11/PREQ§ GP10/PCBE3§ F1 GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default. L2 GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default. GP9/PIDSEL§ M3 J3 GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default. GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default. I/O/Z GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default. EMIFA (64-bit) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY|| ACE3 L26 O/Z IPU ACE2 K23 O/Z IPU ACE1 K24 O/Z IPU ACE0 K25 O/Z IPU ABE7 T23 O/Z IPU ABE6 T24 O/Z IPU ABE5 R25 O/Z IPU ABE4 R26 O/Z IPU ABE3 M25 O/Z IPU ABE2 M26 O/Z IPU ABE1 L23 O/Z IPU ABE0 L24 O/Z IPU EMIFA memory space enables • Enabled by bits 28 through 31 of the word address • Only one pin is asserted during any external data access EMIFA byte-enable control • Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory. • Byte-write enables for most types of memory • Can be directly connected to SDRAM read and write mask signal (SDQM) APDT M22 O/Z IPU EMIFA peripheral data transfer, allows direct transfer between external peripherals † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § For the C6415T and C6416T devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414T device does not support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions for this device. || These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name.  To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 45 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION EMIFA (64-BIT) − BUS ARBITRATION|| AHOLDA N22 O IPU EMIFA hold-request-acknowledge to the host AHOLD V23 I IPU EMIFA hold request from the host ABUSREQ P22 O IPU EMIFA bus request output EMIFA (64-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL|| AECLKIN H25 I IPD EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the BEA[17:16] pins. AECLKIN is the default for the EMIFA input clock. AECLKOUT2 J23 O/Z IPD EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) frequency divided-by-1, -2, or -4. AECLKOUT1 J26 O/Z IPD EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) frequency]. AARE/ ASDCAS/ ASADS/ASRE J25 O/Z IPU EMIFA asynchronous memory read-enable/SDRAM column-address strobe/programmable synchronous interface-address strobe or read-enable • For programmable synchronous interface, the RENEN field in the CE Space Secondary Control Register (CExSEC) selects between ASADS and ASRE: If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal. If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal. AAOE/ ASDRAS/ ASOE J24 O/Z IPU EMIFA asynchronous memory output-enable/SDRAM row-address strobe/programmable synchronous interface output-enable AAWE/ ASDWE/ ASWE K26 O/Z IPU EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable synchronous interface write-enable ASDCKE L25 O/Z IPU EMIFA SDRAM clock-enable (used for self-refresh mode). [EMIFA module only.] • If SDRAM is not in system, ASDCKE can be used as a general-purpose output. ASOE3 R22 O/Z IPU EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO interface) AARDY L22 I IPU Asynchronous memory ready input EMIFA (64-BIT) − ADDRESS|| O/Z IPD EMIFA external address (doubleword address) AEA22 T22 AEA21 V24 AEA20 V25 AEA19 V26 AEA18 U23 AEA17 U24 AEA16 U25 AEA15 U26 AEA14 T25 AEA13 T26 AEA12 R23 AEA11 R24 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) || These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name.  To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION EMIFA (64-BIT) − ADDRESS|| (CONTINUED) AEA10 P23 AEA9 P24 AEA8 P26 AEA7 N23 AEA6 N24 AEA5 N26 AEA4 M23 AEA3 M24 O/Z IPD EMIFA external address (doubleword address) EMIFA (64-bit) − DATA|| AED63 AF24 AED62 AF23 AED61 AE23 AED60 AE22 AED59 AD22 AED58 AF22 AED57 AD21 AED56 AE21 AED55 AC21 AED54 AF21 AED53 AD20 AED52 AE20 AED51 AC20 AED50 AF20 AED49 AC19 AED48 AD19 AED47 W24 AED46 W23 AED45 Y26 AED44 Y23 AED43 Y25 AED42 Y24 AED41 AA26 AED40 AA23 AED39 AA25 AED38 AA24 I/O/Z IPU EMIFA external data AED37 AB26 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) || These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name.  To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 47 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION EMIFA (64-bit) − DATA|| (CONTINUED) AED36 AB24 AED35 AB25 AED34 AC25 AED33 AC26 AED32 AD26 AED31 C26 AED30 D26 AED29 D25 AED28 E25 AED27 E24 AED26 E26 AED25 F24 AED24 F25 AED23 F23 AED22 F26 AED21 G24 AED20 G25 AED19 G23 AED18 G26 AED17 H23 AED16 H24 AED15 C19 AED14 D19 AED13 A20 AED12 D20 AED11 B20 AED10 C20 AED9 A21 AED8 D21 AED7 B21 AED6 C21 AED5 A22 AED4 C22 AED3 B22 AED2 B23 AED1 A23 I/O/Z IPU EMIFA external data AED0 A24 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) || These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name.  To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION EMIFB (16-bit) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY|| BCE3 A13 O/Z IPU BCE2 C12 O/Z IPU BCE1 B12 O/Z IPU BCE0 A12 O/Z IPU BBE1 D13 O/Z IPU BBE0 C13 O/Z IPU BPDT E12 O/Z IPU EMIFB peripheral data transfer, allows direct transfer between external peripherals EMIFB (16-BIT) − BUS ARBITRATION|| BHOLDA E13 O IPU EMIFB hold-request-acknowledge to the host BHOLD B19 I IPU EMIFB hold request from the host BBUSREQ E14 O IPU EMIFB bus request output EMIFB memory space enables • Enabled by bits 26 through 31 of the word address • Only one pin is asserted during any external data access EMIFB byte-enable control • Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory. • Byte-write enables for most types of memory • Can be directly connected to SDRAM read and write mask signal (SDQM) EMIFB (16-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL|| BECLKIN A11 I IPD EMIFB external input clock. The EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the BEA[15:14] pins. BECLKIN is the default for the EMIFB input clock. BECLKOUT2 D11 O/Z IPD EMIFB output clock 2. Programmable to be EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock) frequency divided by 1, 2, or 4. BECLKOUT1 D12 O/Z IPD EMIFB output clock 1 [at EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock) frequency]. BARE/ BSDCAS/ BSADS/BSRE A10 O/Z IPU EMIFB asynchronous memory read-enable/SDRAM column-address strobe/programmable synchronous interface-address strobe or read-enable • For programmable synchronous interface, the RENEN field in the CE Space Secondary Control Register (CExSEC) selects between BSADS and BSRE: If RENEN = 0, then the BSADS/BSRE signal functions as the BSADS signal. If RENEN = 1, then the BSADS/BSRE signal functions as the BSRE signal. BAOE/ BSDRAS/ BSOE B11 O/Z IPU EMIFB asynchronous memory output-enable/SDRAM row-address strobe/programmable synchronous interface output-enable BAWE/BSDWE/ BSWE C11 O/Z IPU EMIFB asynchronous memory write-enable/SDRAM write-enable/programmable synchronous interface write-enable BSOE3 E15 O/Z IPU EMIFB synchronous memory output enable for BCE3 (for glueless FIFO interface) BARDY E11 I IPU EMIFB asynchronous memory ready input † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) || These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name.  To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 49 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION EMIFB (16-BIT) − ADDRESS|| BEA20 E16 IPU BEA19 D18 IPU BEA18 C18 BEA17 B18 BEA16 A18 BEA15 D17 BEA14 C17 BEA13 B17 BEA12 A17 BEA11 D16 BEA10 C16 BEA9 B16 BEA8 A16 BEA7 D15 BEA6 C15 BEA5 B15 BEA4 A15 BEA3 D14 BEA2 C14 BEA1 A14 EMIFB external address (half-word address) (O/Z) • Also controls initialization of DSP modes at reset (I) via pullup/pulldown resistors − Device Endian mode BEA20: 0 – Big Endian 1 − Little Endian (default mode) − Boot mode BEA[19:18]: 00 – No boot 01 − HPI boot 10 − EMIFB 8-bit ROM boot with default timings (default mode) 11 − Reserved − EMIF clock select BEA[17:16]: Clock mode select for EMIFA (AECLKIN_SEL[1:0]) 00 – AECLKIN (default mode) 01 − CPU/4 Clock Rate 10 − CPU/6 Clock Rate 11 − Reserved BEA[15:14]: Clock mode select for EMIFB (BECLKIN_SEL[1:0]) 00 – BECLKIN (default mode) 01 − CPU/4 Clock Rate 10 − CPU/6 Clock Rate 11 − Reserved I/O/Z IPD − PCI EEPROM Auto-Initialization (EEAI) [C6415T and C6416T devices only] BEA13: PCI auto-initialization via external EEPROM If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up. 0 − PCI auto-initialization through EEPROM is disabled (default). 1 − PCI auto-initialization through EEPROM is enabled. − UTOPIA Enable (UTOPIA_EN) [C6415T and C6416T devices only] BEA11: UTOPIA peripheral enable (functional) 0 − UTOPIA disabled (McBSP1 enabled) [default] 1 − UTOPIA enabled (McBSP1 disabled) The C6414T device does not support the PCI and UTOPIA peripherals; for proper device operation, do not oppose the internal pulldowns (IPDs) on the BEA13 and BEA11 pins. Also for proper C6414T device operation, do not oppose the IPDs on the BEA7, BEA8, and BEA9 pins. For proper C6415T device operation, the BEA7 pin must be externally pulled up with a 1-k 1-kΩ resistor. For proper C6416T device operation, the BEA8 and BEA9 pins must be externally pulled up with a 1-kΩ resistor. For more details, see the Device Configurations section of this data sheet. † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) || These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name.  To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION EMIFB (16-bit) − DATA|| BED15 D7 BED14 B6 BED13 C7 BED12 A6 BED11 D8 BED10 B7 BED9 C8 BED8 A7 BED7 C9 BED6 B8 BED5 D9 BED4 B9 BED3 C10 BED2 A9 BED1 D10 BED0 B10 I/O/Z IPU EMIFB external data MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2) MCBSP2_EN AF3 I IPD McBSP2 enable pin. This pin works in conjunction with the PCI_EN pin to enable/disable other peripherals (for more details, see the Device Configurations section of this data sheet). CLKS2/GP8§ AE4 I/O/Z IPD McBSP2 external clock source (CLKS2) [input only] [default] or this pin can also be programmed as a GPIO 8 pin (I/O/Z). CLKR2 AB1 I/O/Z IPD McBSP2 receive clock. When McBSP2 is disabled (PCI_EN pin = 1 and MCBSP2_EN pin = 0), this pin is tied-off. CLKX2/ XSP_CLK§ AC2 I/O/Z IPD McBSP2 transmit clock (I/O/Z) [default] or PCI serial interface clock (O). DR2/XSP_DI§ AB3 I IPU McBSP2 receive data (I) [default] or PCI serial interface data in (I). In PCI mode, this pin is connected to the output data pin of the serial PROM. DX2/XSP_DO§ AA2 O/Z IPU McBSP2 transmit data (O/Z) [default] or PCI serial interface data out (O). In PCI mode, this pin is connected to the input data pin of the serial PROM. FSR2 AC1 I/O/Z IPD McBSP2 receive frame sync. When McBSP2 is disabled (PCI_EN pin = 1 and MCBSP2_EN pin = 0), this pin is tied-off. FSX2 AB2 I/O/Z IPD McBSP2 transmit frame sync. When McBSP2 is disabled (PCI_EN pin = 1 and MCBSP2_EN pin = 0), this pin is tied-off. † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § For the C6415T and C6416T devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414T device does not support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins except CLKS2/GP8 are standalone peripheral functions for this device. || These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name.  To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 51 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1/ URADDR3§ AC8 I McBSP1 external clock source (as opposed to internal) (I) [default] or UTOPIA receive address 3 pin (I) CLKR1/ URADDR2§ AC10 I/O/Z McBSP1 receive clock (I/O/Z) [default] or UTOPIA receive address 2 pin (I) CLKX1/ URADDR4§ AB12 I/O/Z McBSP1 transmit clock (I/O/Z) [default] or UTOPIA receive address 4 pin (I) DR1/ UXADDR1§ AF11 I DX1/ UXADDR4§ AB11 I/O/Z McBSP1 transmit data (O/Z) [default] or UTOPIA transmit address 4 pin (I) FSR1/ UXADDR2§ AC9 I/O/Z McBSP1 receive frame sync (I/O/Z) [default] or UTOPIA transmit address 2 pin (I) FSX1/ UXADDR3§ AB13 I/O/Z McBSP1 transmit frame sync (I/O/Z) [default] or UTOPIA transmit address 3 pin (I) CLKS0 F4 I IPD McBSP0 external clock source (as opposed to internal) CLKR0 D1 I/O/Z IPD McBSP0 receive clock CLKX0 E1 I/O/Z IPD McBSP0 transmit clock DR0 D2 I IPU McBSP0 receive data McBSP1 receive data (I) [default] or UTOPIA transmit address 1 pin (I) MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) DX0 E2 O/Z IPU McBSP0 transmit data FSR0 C1 I/O/Z IPD McBSP0 receive frame sync FSX0 E3 I/O/Z IPD McBSP0 transmit frame sync TOUT2 A4 O/Z IPD Timer 2 or general-purpose output TINP2 C5 I IPD Timer 2 or general-purpose input TOUT1 B5 O/Z IPD Timer 1 or general-purpose output TINP1 A5 I IPD Timer 1 or general-purpose input TIMER 2 TIMER 1 TIMER 0 TOUT0 D6 O/Z IPD Timer 0 or general-purpose output TINP0 C6 I IPD Timer 0 or general-purpose input † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § For the C6415T and C6416T devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414T device does not support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions for this device. 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION UNIVERSAL TEST AND OPERATIONS PHY INTERFACE FOR ASYNCHRONOUS TRANSFER MODE (ATM) [UTOPIA SLAVE] [C6415T and C6416T devices only] UTOPIA SLAVE (ATM CONTROLLER) − TRANSMIT INTERFACE UXCLKY UXCLAVY AD11 AC14 I  Source clock for UTOPIA transmit driven by Master ATM Controller. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. Transmit cell available status output signal from UTOPIA Slave. 0 indicates a complete cell is NOT available for transmit 1 indicates a complete cell is available for transmit O/Z When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. UXENBY UXSOCY AE15 AC13 I ◊ UTOPIA transmit interface enable input signal. Asserted by the Master ATM Controller to indicate that the UTOPIA Slave should put out on the Transmit Data Bus the first byte of valid data and the UXSOC signal in the next clock cycle. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. Transmit Start-of-Cell signal. This signal is output by the UTOPIA Slave on the rising edge of the UXCLK, indicating that the first valid byte of the cell is available on the 8-bit Transmit Data Bus (UXDATA[7:0]). When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. O/Z McBSP1 [default] or UTOPIA transmit address pins DX1/ UXADDR4§ As UTOPIA transmit address pins UXADDR[4:0] (I), UTOPIA_EN (BEA11 pin) = 1: • 5-bit Slave transmit address input pins driven by the Master ATM Controller to identify and select one of the Slave devices (up to 31 possible) in the ATM System. AB11 I/O/Z ◊ • UXADDR0 pin is tied off when the UTOPIA peripheral is disabled [UTOPIA_EN (BEA11 pin) = 0] For the McBSP1 pin functions (UTOPIA_EN (BEA11 pin) = 0 [default]), see the MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) section of this table. FSX1/ UXADDR3§ AB13 FSR1/ UXADDR2§ AC9 I/O/Z ◊ DR1/ UXADDR1§ AF11 I ◊ I/O/Z ◊ McBSP1 [default] or UTOPIA transmit address pins As UTOPIA transmit address pins UXADDR[4:0] (I), UTOPIA_EN (BEA11 pin) = 1: • 5-bit Slave transmit address input pins driven by the Master ATM Controller to identify and select one of the Slave devices (up to 31 possible) in the ATM System. • UXADDR0 pin is tied off when the UTOPIA peripheral is disabled [UTOPIA_EN (BEA11 pin) = 0] For the McBSP1 pin functions (UTOPIA_EN (BEA11 pin) = 0 [default]), see the MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) section of this table. † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § For the C6415T and C6416T devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. The C6414T device does not support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions for this device.  For the C6415T and C6416T devices, external pulldowns required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-kΩ resistor must be used to externally pull down each of these pins. If these pins are “no connects”, then only UXCLK and URCLK need to be pulled down and other pulldowns are not necessary. ◊ For the C6415T and C6416T devices, external pullups required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-kΩ resistor must be used to externally pull up each of these pins. If these pins are “no connects”, then the pullups are not necessary. Ψ The C6414T device does not support the UTOPIA peripheral; therefore, these standalone UTOPIA pins are Reserved (leave unconnected, do not connect to power or ground) with the exception of UXCLK and URCLK which should be connected to a 10-kΩ pulldown resistor (see the square [] footnote). UXADDR0Y AE9 I ◊ POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 53 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION UTOPIA SLAVE (ATM CONTROLLER) − TRANSMIT INTERFACE (CONTINUED) UXDATA7Y UXDATA6Y AD10 UXDATA5Y UXDATA4Y AD8 UXDATA3Y UXDATA2Y AF9 UXDATA1Y UXDATA0Y AD9 8-bit Transmit Data Bus Using the Transmit Data Bus, the UTOPIA Slave (on the rising edge of the UXCLK) transmits the 8-bit ATM cells to the Master ATM Controller. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), these pins are tiedoff. AE8 O/Z AF7 AE7 AD7 UTOPIA SLAVE (ATM CONTROLLER) − RECEIVE INTERFACE URCLKY URCLAVY AD12 AF14 I  Source clock for UTOPIA receive driven by Master ATM Controller. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. Receive cell available status output signal from UTOPIA Slave. 0 indicates NO space is available to receive a cell from Master ATM Controller 1 indicates space is available to receive a cell from Master ATM Controller O/Z When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. URENBY AD15 I ◊ UTOPIA receive interface enable input signal. Asserted by the Master ATM Controller to indicate to the UTOPIA Slave to sample the Receive Data Bus (URDATA[7:0]) and URSOC signal in the next clock cycle or thereafter. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. Receive Start-of-Cell signal. This signal is output by the Master ATM Controller to indicate to the UTOPIA Slave that the first valid byte of the cell is available to sample on the 8-bit Receive Data Bus (URDATA[7:0]). When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off. URSOCY AB14 I  CLKX1/ URADDR4§ AB12 I/O/Z ◊ CLKS1/ URADDR3§ AC8 I ◊ As UTOPIA receive address pins URADDR[4:0] (I), UTOPIA_EN (BEA11 pin) = 1: • 5-bit Slave receive address input pins driven by the Master ATM Controller to identify and select one of the Slave devices (up to 31 possible) in the ATM System. CLKR1/ URADDR2§ AC10 I/O/Z ◊ • URADDR1Y AF10 I ◊ McBSP1 [default] or UTOPIA receive address pins URADDR1 and URADDR0 pins are tied off when the UTOPIA peripheral is disabled [UTOPIA_EN (BEA11 pin) = 0] For the McBSP1 pin functions (UTOPIA_EN (BEA11 pin) = 0 [default]), see the MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) section of this table. † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.  External pulldowns required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-kΩ resistor must be used to externally pull down each of these pins. If these pins are “no connects”, then only UXCLK and URCLK need to be pulled down and other pulldowns are not necessary. ◊ External pullups required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-kΩ resistor must be used to externally pull up each of these pins. If these pins are “no connects”, then the pullups are not necessary. Ψ The C6414T device does not support the UTOPIA peripheral; therefore, these standalone UTOPIA pins are Reserved (leave unconnected, do not connect to power or ground) with the exception of UXCLK and URCLK which should be connected to a 10-kΩ pulldown resistor (see the square [] footnote). URADDR0Y 54 AE10 I ◊ POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION UTOPIA SLAVE (ATM CONTROLLER) − RECEIVE INTERFACE (CONTINUED) URDATA7Ψ AF12 URDATA6Ψ AE11 URDATA5Ψ AF13 URDATA4Ψ AC11 URDATA3Ψ AC12 URDATA2Ψ AE12 URDATA1Ψ AD14 URDATA0Ψ AD13 I  8-bit Receive Data Bus. Using the Receive Data Bus, the UTOPIA Slave (on the rising edge of the URCLK) can receive the 8-bit ATM cell data from the Master ATM Controller. When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), these pins are tiedoff. RESERVED FOR TEST G14 H7 RSV N20 Reserved. These pins must be connected directly to CVDD for proper device operation. P7 Y13 RSV R6 Reserved. This pin must be connected directly to DVDD for proper device operation. A3 G2 H3 RSV J4 K6 Reserved (leave unconnected, do not connect to power or ground. If the signal must be routed out from the device, the internal pull−up/down resistance should not be relied upon and an external pull−up/down should be used). N3 P3 RSV W25 IPD Reserved. This pin must be connected directly to VSS for proper device operation. † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.)  External pulldowns required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-kΩ resistor must be used to externally pull down each of these pins. If these pins are “no connects”, then only UXCLK and URCLK need to be pulled down and other pulldowns are not necessary. Ψ The C6414T device does not support the UTOPIA peripheral; therefore, these standalone UTOPIA pins are Reserved (leave unconnected, do not connect to power or ground) with the exception of UXCLK and URCLK which should be connected to a 10-kΩ pulldown resistor (see the square [] footnote). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 55 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION SUPPLY VOLTAGE PINS A2 A25 B1 B14 B26 E7 E8 E10 E17 E19 E20 F3 F9 F12 F15 F18 G5 G22 H5 H22 DVDD J21 S 3.3-V supply voltage (see the Power-Supply Decoupling section of this data sheet) K5 K22 L5 M5 M6 M21 N2 P25 R5 R21 T5 U5 U22 V6 V21 W5 W22 Y5 Y22 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground 56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) AA9 AA12 AA15 AA18 AB7 AB8 AB10 DVDD 3.3-V supply voltage (see the Power-Supply Decoupling section of this data sheet) AB17 AB19 AB20 AE1 AE13 AE26 AF2 AF25 A1 A26 B2 B25 C3 S C24 D4 D23 E5 E22 F6 F7 CVDD F20 1.1-V supply voltage (-600 device) 1.2 V supply voltage (-720, -850, -1G devices) (see the Power-Supply Decoupling section of this data sheet) F21 G6 G7 G8 G10 G11 G13 G16 G17 G19 G20 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 57 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) G21 H20 K7 K20 L7 L20 N7 P20 T7 T20 U7 U20 W7 W20 Y6 Y7 Y8 Y10 Y11 CVDD Y14 Y16 S 1.1-V supply voltage (-600 device) 1.2 V supply voltage (-720, -850, -1G devices) (see the Power-Supply Decoupling section of this data sheet) Y17 Y19 Y20 Y21 AA6 AA7 AA20 AA21 AB5 AB22 AC4 AC23 AD3 AD24 AE2 AE25 AF1 AF26 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground 58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION GROUND PINS A8 A19 B3 B13 B24 C2 C4 C23 C25 D3 D5 D22 D24 E4 E6 E9 E18 E21 E23 VSS F5 GND Ground pins F8 F10 F11 F13 F14 F16 F17 F19 F22 G9 G12 G15 G18 H1 H6 H21 H26 J5 J7 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 59 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION GROUND PINS (CONTINUED) J20 J22 K21 L6 L21 M7 M20 N6 N21 N25 P2 P6 P21 R7 R20 T6 T21 U6 U21 VSS V5 GND Ground pins V7 V20 V22 W1 W6 W21 W26 Y9 Y12 Y15 Y18 AA5 AA8 AA10 AA11 AA13 AA14 AA16 AA17 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Terminal Functions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION GROUND PINS (CONTINUED) AA19 AA22 AB4 AB6 AB9 AB18 AB21 AB23 AC3 AC5 VSS AC22 GND Ground pins AC24 AD2 AD4 AD23 AD25 AE3 AE14 AE24 AF8 AF19 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 61 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 development support TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module) For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Code Composer Studio, DSP/BIOS, and XDS are trademarks of Texas Instruments. 62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 device support device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. (e.g., TMS320C6415TGLZ7) Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device’s electrical specifications TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GLZ), the temperature range (for example, “blank” is the default commercial temperature range), and the device speed range in megahertz (for example, 7 is 720-MHz). Figure 5 provides a legend for reading the complete device name for any TMS320C64x DSP generation member. The ZLZ package, like the GLZ package, is a 532-ball plastic BGA only with Pb-free balls. The CLZ is the Pb−Free die bump and solder ball version of GLZ and ZLZ. For device part numbers and further ordering information for TMS320C6414T/TMS320C6415T/TMS320C6416T in the GLZ, ZLZ and CLZ package types, see the TI website (http://www.ti.com) or contact your TI sales representative. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 63 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 device and development-support tool nomenclature (continued) TMS 320 PREFIX TMX = TMP = TMS = SMX= SMJ = SM = C 6415T GLZ ( ) 7 DEVICE SPEED RANGE 6 (600-MHz CPU, 133-MHz EMIFA) 7 (720-MHz CPU, 133-MHz EMIFA) 8 (850-MHz CPU, 133 MHz EMIFA) 1 (1-GHz CPU, 133-MHz EMIFA) Experimental device Prototype device Qualified device Experimental device, MIL MIL-PRF-38535, QML High Rel (non-38535) DEVICE FAMILY 3 or 32 or 320 = TMS320 DSP family TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)†‡ Blank = 0°C to 90°C, commercial temperature M = 0°C to 90°C, commercial temperature A = −40°C to 105°C, extended temperature D = −40°C to 90°C, partial extended temperature PACKAGE TYPE§#|| GLZ = 532-pin plastic BGA ZLZ = 532-pin plastic BGA, with Pb−free soldered balls CLZ = Pb−Free die bump and solder ball version of GLZ and ZLZ DEVICE¶ C64x DSP: 6414T 6415T 6416T TECHNOLOGY C = CMOS † The extended temperature “A version” devices may have different operating conditions than the commercial temperature devices. ‡ See the Recommended Operating Conditions section of this data sheet for more details. § BGA = Ball Grid Array ¶ For the actual device part numbers (P/Ns) and ordering information, see the TI website (www.ti.com). # The ZLZ mechanical package designator represents the version of the GLZ with Pb−Free soldered balls. || The CLZ mechanical package designator represents the version of the GLZ and ZLZ with Pb−Free die bump and solder balls. Figure 5. TMS320C64x DSP Device Nomenclature (Including the C6414T, C6415T, and C6416T Devices) For additional information, see the TMS320C6414T, TMS320C6415T, and TMS320C6416T Digital Signal Processors Silicon Errata (literature number SPRZ216) 64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 documentation support Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000 DSP devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 DSP CPU (core) architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) provides an overview and briefly describes the functionality of the peripherals available on the C6000 DSP platform of devices. This document also includes a table listing the peripherals available on the C6000 devices along with literature numbers and hyperlinks to the associated peripheral documents. The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the TMS320C62x/TMS320C67x devices, associated development tools, and third-party support. The TMS320C64x Technical Overview (literature number SPRU395) gives an introduction to the C64x digital signal processor, and discusses the application areas that are enhanced by the C64x DSP VelociTI.2 VLIW architecture. The TMS320C6414T, TMS320C6415T, and TMS320C6416T Digital Signal Processors Silicon Errata (literature number SPRZ216) describes the known exceptions to the functional specifications for the TMS320C6414T, TMS320C6415T, and TMS320C6416T devices. The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to properly use IBIS models to attain accurate timing analysis for a given system. The Migrating From TMS320C6416/15/14 to TMS320C6416T/15T/14T application report (literature number SPRA981) provides more detailed information on the device compatibility, similarities/differences, and migration from a TMS320C6416 device to the TMS320C6414T/C6415T/C6416T devices. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). TMS320C67x is a trademark of Texas Instruments. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 65 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 clock PLL Most of the internal C64x DSP clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock. To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 6 shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes. To ensure proper operation of the PLL, a specified power-on reset sequence must be followed. For more detail on the specified power-on reset sequence, see the power-supply sequencing section of this data sheet. To minimize the clock jitter, a single clean power supply should power both the C64x DSP device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and output clocks electricals section. Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended ranges of supply voltage and operating case temperature table and the input and output clocks electricals section). Table 30 lists some examples of compatible CLKIN external clock sources: Table 30. Compatible CLKIN External Clock Sources COMPATIBLE PARTS FOR EXTERNAL CLOCK SOURCES (CLKIN) PART NUMBER JITO-2 Fox Electronix STA series, ST4100 series SaRonix Corporation SG-636 Epson America 342 Corning Frequency Control ICS525-02 Integrated Circuit Systems Oscillators PLL 66 MANUFACTURER POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 clock PLL (continued) 3.3 V CPU Clock EMI filter C1 C2 10 µF 0.1 µF /2 Peripheral Bus /8 Timer Internal Clock /4 CLKOUT4, McBSP Internal Clock /6 CLKOUT6 PLLV CLKMODE0 CLKMODE1 PLLMULT PLL x6, x12, x20 CLKIN PLLCLK 1 ECLKIN_SEL (DEVCFG.[17,16] and DEVCFG.[15,14]) 00 01 10 /4 0 /2 ECLKIN Internal to C64x (For the PLL Options, CLKMODE Pins Setup, and PLL Clock Frequency Ranges, see Table 31.) EMIF 00 01 10 ECLKOUT1 ECLKOUT2 EK2RATE (GBLCTL.[19,18]) NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000 DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI Filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U. Figure 6. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 67 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 clock PLL (continued) Table 31. TMS320C64x PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time†‡ GLZ, ZLZ and CLZ PACKAGES − 23 x 23 mm BGA CLKMODE1 CLKMODE0 CLKMODE (PLL MULTIPLY FACTORS) CLKIN RANGE (MHz) CPU CLOCK FREQUENCY RANGE (MHz) CLKOUT4 RANGE (MHz) CLKOUT6 RANGE (MHz) TYPICAL LOCK TIME (µs)§ N/A 0 0 Bypass (x1) 0−100 0−100 0−25 0−16.6 0 1 x6 42−75 252−450 63−112.5 42−75 1 0 x12 42−75 504−900 126−225 84−150 1 1 x20 25−50 500−1000 125−250 83.3−166.6 75 † These clock frequency range values are applicable to a C64x−600, −720, −850, and −1000-MHz speed devices. For more detailed information, see the CLKIN timing requirements table for the specific device speed. ‡ Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the C64x device to one of the valid PLL multiply clock modes (x6, x12, or x20). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock mode is x1 (bypass). § Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs. 68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 general-purpose input/output (GPIO) To use the GP[15:0] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register and the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured. GPxEN = 1 GP[x] pin is enabled GPxDIR = 0 GP[x] pin is an input GPxDIR = 1 GP[x] pin is an output where “x” represents one of the 15 through 0 GPIO pins Figure 7 shows the GPIO enable bits in the GPEN register for the C6414T/C6415T/C6416T device. To use any of the GPx pins as general-purpose input/output functions, the corresponding GPxEN bit must be set to “1” (enabled). Default values are device-specific, so refer to Figure 7 for the C6414T/15T/16T default configuration. 31 24 23 16 Reserved R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP15 EN GP14 EN GP13 EN GP12 EN GP11 EN GP10 EN GP9 EN GP8 EN GP7 EN GP6 EN GP5 EN GP4 EN GP3 EN GP2 EN GP1 EN GP0 EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset Figure 7. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000] Figure 8 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO pin is an input or an output providing the corresponding GPxEN bit is enabled (set to “1”) in the GPEN register. By default, all the GPIO pins are configured as input pins. 31 24 23 16 Reserved R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP15 DIR GP14 DIR GP13 DIR GP12 DIR GP11 DIR GP10 DIR GP9 DIR GP8 DIR GP7 DIR GP6 DIR GP5 DIR GP4 DIR GP3 DIR GP2 DIR GP1 DIR GP0 DIR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset Figure 8. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004] For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 69 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 power-down mode logic Figure 9 shows the power-down mode logic on the C6414T/C6415T/C6416T. CLKOUT4 CLKOUT6 Internal Clock Tree Clock Distribution and Dividers PD1 PD2 PowerDown Logic Clock PLL IFR IER Internal Peripherals PWRD CSR CPU PD3 TMS320C6414T/15T/16T CLKIN RESET † External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic. Figure 9. Power-Down Mode Logic† triggering, wake-up, and effects The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10) of the control status register (CSR). The PWRD field of the CSR is shown in Figure 10 and described in Table 32. When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). 70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 31 16 15 14 13 12 11 10 Reserved Enable or Non-Enabled Interrupt Wake Enabled Interrupt Wake PD3 PD2 PD1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 9 7 8 0 Legend: R/W−x = Read/write reset value NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). Figure 10. PWRD Field of the CSR Register A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR before the PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in the CSR to account for this delay. If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first, then the program execution returns to the instruction where PD1 took effect. In the case with an enabled interrupt, the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order for the interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect upon PD1 mode termination by an enabled interrupt. PD2 and PD3 modes can only be aborted by device reset. Table 32 summarizes all the power-down modes. Table 32. Characteristics of the Power-Down Modes PRWD FIELD (BITS 15−10) POWER-DOWN MODE WAKE-UP METHOD EFFECT ON CHIP’S OPERATION 000000 No power-down — — 001001 PD1 Wake by an enabled interrupt 010001 PD1 Wake by an enabled or non-enabled interrupt 011010 PD2† Wake by a device reset CPU halted (except for the interrupt logic) Power-down mode blocks the internal clock inputs at the boundary of the CPU, preventing most of the CPU’s logic from switching. During PD1, EDMA transactions can proceed between peripherals and internal memory. Output clock from PLL is halted, stopping the internal clock structure from switching and resulting in the entire chip being halted. All register and internal RAM contents are preserved. All functional I/O “freeze” in the last state when the PLL clock is turned off. † When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions, peripherals will not operate according to specifications. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 71 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 Table 32. Characteristics of the Power-Down Modes PRWD FIELD (BITS 15−10) 011100 POWER-DOWN MODE PD3† WAKE-UP METHOD Wake by a device reset EFFECT ON CHIP’S OPERATION Input clock to the PLL stops generating clocks. All register and internal RAM contents are preserved. All functional I/O “freeze” in the last state when the PLL clock is turned off. Following reset, the PLL needs time to re-lock, just as it does following power-up. Wake-up from PD3 takes longer than wake-up from PD2 because the PLL needs to be re-locked, just as it does following power-up. All others Reserved — — † When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions, peripherals will not operate according to specifications. C64x power-down mode with an emulator If user power-down modes are programmed, and an emulator is attached, the modes will be masked to allow the emulator access to the system. This condition prevails until the emulator is reset or the cable is removed from the header. If power measurements are to be performed when in a power-down mode, the emulator cable should be removed. When the DSP is in power-down mode PD2 or PD3, emulation logic will force any emulation execution command (such as Step or Run) to spin in IDLE. For this reason, PC writes (such as loading code) will fail. A DSP reset will be required to get the DSP out of PD2/PD3. power-supply sequencing TI DSPs typically do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that the Core is powered up prior to the I/O supply and that the I/O supply is powered up within ≤ 200 ms of the core. This power sequence becomes even more important in multiprocessor designs. In addition, for proper device initialization, device reset (RESET) must be held active (low) during device power ramp and should not be released until the PLL becomes stable. power-supply design considerations A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 11). 72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 I/O Supply DVDD Schottky Diode C6000 DSP Core Supply CVDD VSS GND Figure 11. Schottky Diode Diagram Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors. power-supply decoupling In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the core supply and 30 for the I/O supply. These caps need to be close to the DSP power pins, no more than 1.25 cm maximum distance to be effective. Physically smaller caps, such as 0402, are better because of their lower parasitic inductance. Proper capacitance values are also important. Small bypass caps (near 560 pF) should be closest to the power pins. Medium bypass caps (220 nF or as large as can be obtained in a small package) should be next closest. TI recommends no less than 8 small and 8 medium caps per supply (32 total) be placed immediately next to the BGA vias, using the “interior” BGA space and at least the corners of the “exterior”. Eight larger caps (4 for each supply) can be placed further away for bulk decoupling. Large bulk caps (on the order of 100 µF) should be furthest away (but still as close as possible). No less than 4 large caps per supply (8 total) should be placed outside of the BGA. Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of any component, verification of capacitor availability over the product’s production lifetime should be considered. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 73 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 IEEE 1149.1 JTAG compatibility statement The TMS320C6414T/15T/16T DSP requires that both TRST and RESET be asserted upon power up to be properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both resets are required for proper operation. Note: TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected after TRST is asserted. While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG controller to debug the DSP or exercise the DSP’s boundary scan functionality. RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan instructions work correctly independant of current state of RESET. For maximum reliability, the TMS320C6414T/15T/16T DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP’s internal emulation logic will always be properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations. Following the release of RESET, the low-to-high transition of TRST must be “seen” to latch the state of EMU1 and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see the terminal functions section of this data sheet. Note: The DESIGN_WARNING section of the C6414T, C6415T, C6416T GLZ BSDL file contains information and constraints regarding proper device operation while in Boundary Scan Mode. For more detailed information on the C6414T/15T/16T JTAG emulation, see the TMS320C6000 DSP Designing for JTAG Emulation Reference Guide (literature number SPRU641). EMIF device speed The rated EMIF speed, referring to both EMIFA and EMIFB, of these devices only applies to the SDRAM interface when in a system that meets the following requirements: − 1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF − up to 1 CE space of buffers connected to EMIF − EMIF trace lengths between 1 and 3 inches − 166-MHz SDRAM for 133-MHz operation (applies only to EMIFA) − 143-MHz SDRAM for 100-MHz operation Timing analysis must be done to verify all AC timings are met for all configurations. Verification of AC timings is mandatory when using configurations other than those specified above. TI recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see the Terminal Functions table for the EMIF output signals). 74 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 bootmode The C6414T/15T/16T device resets using the active-low signal RESET. While RESET is low, the device is held in reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and states of device pins during reset. The release of RESET starts the processor running with the prescribed device configuration and boot mode. The C6414T/C6415T/C6416T has three types of boot modes:
Host boot If host boot is selected, upon release of RESET, the CPU is internally “stalled” while the remainder of the device is released. During this period, an external host can initialize the CPU’s memory space as necessary through the host interface, including internal configuration registers, such as those that control the EMIF or other peripherals. For the C6414T device, the HPI peripheral is used for host boot. For the C6415T/C6416T device, the HPI peripheral is used for host boot if PCI_EN = 0, and the PCI peripheral is used for host boot if PCI_EN = 1. Once the host is finished with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration logic to bring the CPU out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT brings the CPU out of the “stalled” state only if the host boot process is selected. All memory may be written to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is out of the “stalled” state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
EMIF boot (using default ROM timings) Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0 by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be stored in the endian format that the system is using. In this case, the EMIF automatically assembles consecutive 8-bit bytes to form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is released from the “stalled” state and starts running from address 0.
No boot With no boot, the CPU begins direct execution from the memory located at address 0. Note: operation is undefined if invalid code is located at address 0. reset A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The RESET signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages have reached their proper operating conditions. As a best practice, reset should be held low during power-up. Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should be at their proper operating conditions and CLKIN should also be running at the correct frequency. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 75 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 absolute maximum ratings over operating case temperature range (unless otherwise noted)† Supply voltage ranges: CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 1.5 V DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.4 V Input voltage ranges: (except PCI), VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.4 V (PCI), VIP [C6415T and C6416T only] . . . . . . . . . . . . . . . . . . −0.5 V to DVDD + 0.5 V Output voltage ranges: (except PCI), VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.4 V (PCI), VOP [C6415T and C6416T only] . . . . . . . . . . . . . . . . . −0.5 V to DVDD + 0.5 V Operating case temperature ranges, TC: (default and M version) . . . . . . . . . . . . . . . . . . . . . . 0C to 90C (A version) [A-600, A-720, A−850 only] . . . . . . . −40C to 105C (D version) [D−1000 only] . . . . . . . . . . . . . . . . . . −40C to 90C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to 150C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX UNIT CVDD Supply voltage, Core (-600 devices)‡ 1.05 1.1 1.16 V CVDD Supply voltage, Core (-720, -850, 1G devices)‡ 1.16 1.2 1.24 V DVDD Supply voltage, I/O 3.14 3.3 3.46 V VSS VIH Supply ground 0 0 0 V High-level input voltage (except PCI) 2 VIL VIP Low-level input voltage (except PCI) VIHP VILP High-level input voltage (PCI) [C6415T and C6416T only] VOS Maximum voltage during overshoot/undershoot (except PCI) V −0.5 DVDD + 0.5 V 0.5DVDD −0.5 −1.0§ DVDD + 0.5 V 0.3DVDD 4.3§ V 0 90 C Extended temperature devices [A−600, A−720, A−850 only] -40 105 C Partial extended temperature devices [D−1000 only] -40 90 C Input voltage (PCI) [C6415T and C6416T only] Low-level input voltage (PCI) [C6415T and C6416T only] Commercial temperature devices [Blank, M−600, M−720, M−850, M−1000] TC Operating case temperature V 0.8 V ‡ Future variants of the C641xT DSPs may operate at voltages ranging from 1.0 V to 1.2 V to provide a range of system power/performance options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (with ± 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Examples of such supplies include the PT5406, PT5815, PT6476, PT6505, and PT6719 series from Power Trends, a subsidiary of Texas Instruments. Not incorporating a flexible supply may limit the system’s ability to easily adapt to future versions of C641xT devices. § The absolute maximum ratings should not be exceeded for more than 30% of the cycle period. This specification does not apply to PCI signals. 76 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) TEST CONDITIONS† PARAMETER VOH High-level output voltage (except PCI) DVDD = MIN, IOH = MAX VOHP High-level output voltage (PCI) [C6415T/C6416T only] IOHP = −0.5 mA, DVDD = 3.3 V VOL Low-level output voltage (except PCI) DVDD = MIN, IOL = MAX VOLP Low-level output voltage (PCI) [C6415T/C6416T only] IOLP = 1.5 mA, DVDD = 3.3 V MIN TYP IIP IOH Input current (except PCI) [DC] 0.9DVDD¶ V 0.4 0.1DVDD¶ V V ±1 uA VI = VSS to DVDD opposing internal pullup resistor‡ −200 −100 −50 uA VI = VSS to DVDD opposing internal pulldown resistor‡ 50 100 200 uA ±10 uA Input leakage current (PCI) [DC]§ [C6415T/C6416T only] 0 < VIP < DVDD = 3.3 V EMIF, CLKOUT4, CLKOUT6, EMUx −8 mA High-level output current [DC] Timer, UTOPIA, TDO, GPIO (Excluding GP[15:9, 2, 1]), McBSP −4 mA −0.5¶ mA EMIF, CLKOUT4, CLKOUT6, EMUx 8 mA Timer, UTOPIA, TDO, GPIO (Excluding GP[15:9, 2, 1]), McBSP 4 mA PCI/HPI 1.5¶ mA ±20 uA PCI/HPI IOL UNIT V VI = VSS to DVDD no opposing internal resistor II MAX 2.4 Low-level output current [DC] IOZ ICDD Off-state output current [DC] Core supply current# VO = DVDD or 0 V CVDD = 1.2 V, CPU clock = 720 MHz 713 mA ICDD Core supply current# CVDD = 1.2 V, CPU clock = 850 MHz 824 mA CVDD = 1.2 V, CPU clock = 1 GHz 952 mA CVDD = 1.1 V, CPU clock = 600 MHz 558 mA DVDD = 3.3 V, CPU clock = 720 MHz 151 mA ICDD Core supply current# IDDD Ci I/O supply current# Input capacitance 2 pF Co Output capacitance 3 pF † For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. ‡ Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. § PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs. ¶ These rated numbers are from the PCI specification version 2.3. The DC specification and AC specification are defined in Tables 4-3 and 4-4, respectively. # Measured with average activity (50% high/50% low power). The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6414T/15T/16T Power Consumption Application Report (literature number SPRAA45). recommended clock and control signal transition behavior All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 77 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 PARAMETER MEASUREMENT INFORMATION Tester Pin Electronics 42 W Data Sheet Timing Reference Point Output Under Test 3.5 nH Transmission Line Z0 = 50 W (see note) 4.0 pF Device Pin (see note) 1.85 pF NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 12. Test Load Circuit for AC Timing Measurements The tester load circuit is for characterization and measurement of AC timing signals. This load does not indicate the maximum load the device is capable of driving. signal transition levels All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels. Vref = 1.5 V Figure 13. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH MIN for output clocks, VILP MAX and VIHP MIN for PCI input clocks, and VOLP MAX and VOHP MIN for PCI output clocks. Vref = VIH MIN (or VOH MIN or VIHP MIN or VOHP MIN) Vref = VIL MAX (or VOL MAX or VILP MAX or VOLP MAX) Figure 14. Rise and Fall Transition Time Voltage Reference Levels signal transition rates All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns). 78 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameters and board routing analysis The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences. For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 33 and Figure 15). Figure 15 represents a general transfer between the DSP and an external device. The figure also represents board route delays and how they are perceived by the DSP and the external device. Table 33. Board-Level Parameters Example (see Figure 15) NO. DESCRIPTION 1 Clock route delay 2 Minimum DSP hold time 3 Minimum DSP setup time 4 External device hold time requirement 5 External device setup time requirement 6 Control signal route delay 7 External device hold time 8 External device access time 9 DSP hold time requirement 10 DSP setup time requirement 11 Data route delay ECLKOUTx (Output from DSP) 1 ECLKOUTx (Input to External Device) Control Signals† (Output from DSP) 2 3 4 5 Control Signals (Input to External Device) 6 7 Data Signals‡ (Output from External Device) 8 10 9 11 Data Signals‡ (Input to DSP) † Control signals include data for Writes. ‡ Data signals are generated during Reads from an external device. Figure 15. Board-Level Input/Output Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 79 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN for -600 devices†‡§ (see Figure 16) −600 PLL MODE x20 NO. 1 2 3 4 MIN MAX 40 tc(CLKIN) tw(CLKINH) Cycle time, CLKIN 33.3 Pulse duration, CLKIN high 0.4C tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 0.4C Transition time, CLKIN PLL MODE x12 MIN MAX 20 23.8 0.4C x1 (BYPASS) MIN MAX 13.3 23.8 0.4C 0.4C 5 PLL MODE x6 UNIT MIN MAX 0 10 0.45C 0.4C ns 0.45C 5 ns ns 5 1 ns 5 tJ(CLKIN) Period jitter, CLKIN 0.02C 0.02C 0.02C † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ For more details on the PLL multiplier factors (x6, x12, x20), see the Clock PLL section of this data sheet. § C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. 0.02C ns timing requirements for CLKIN for -720 devices†‡§ (see Figure 16) −720 PLL MODE x20 NO. 1 2 3 4 PLL MODE x12 PLL MODE x6 x1 (BYPASS) UNIT MIN MAX MIN MAX MIN MAX MIN MAX 40 16.6 23.8 13.3 23.8 0 10 tc(CLKIN) tw(CLKINH) Cycle time, CLKIN 27.7 Pulse duration, CLKIN high 0.4C 0.4C 0.4C 0.45C ns tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 0.4C 0.4C 0.4C 0.45C ns Transition time, CLKIN 5 5 ns 5 1 ns tJ(CLKIN) Period jitter, CLKIN 0.02C 0.02C 0.02C † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ For more details on the PLL multiplier factors (x6, x12, x20), see the Clock PLL section of this data sheet. § C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. 0.02C ns 5 80 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 timing requirements for CLKIN for -850 devices†‡§ (see Figure 16) −850 PLL MODE x20 NO. 1 2 3 4 PLL MODE x12 PLL MODE x6 x1 (BYPASS) UNIT MIN MAX MIN MAX MIN MAX MIN MAX 40 14 23.8 13.3 23.8 0 10 tc(CLKIN) tw(CLKINH) Cycle time, CLKIN 23.5 Pulse duration, CLKIN high 0.4C 0.4C 0.4C 0.45C tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 0.4C 0.4C 0.4C 0.45C Transition time, CLKIN 5 5 ns ns ns 5 1 ns 5 tJ(CLKIN) Period jitter, CLKIN 0.02C 0.02C 0.02C † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ For more details on the PLL multiplier factors (x6, x12, x20), see the Clock PLL section of this data sheet. § C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. 0.02C ns timing requirements for CLKIN for -1G devices†‡§ (see Figure 16) −1G PLL MODE x20 NO. 1 2 3 4 PLL MODE x12 MIN MAX 20 40 tc(CLKIN) tw(CLKINH) Cycle time, CLKIN Pulse duration, CLKIN high 0.4C tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 0.4C Transition time, CLKIN MIN MAX 13.3 23.8 0.4C PLL MODE x6 x1 (BYPASS) MIN MAX 13.3 23.8 0.4C 0.4C 5 MAX 0 10 0.45C 0.4C 5 UNIT MIN ns ns 0.45C ns 5 1 ns 5 tJ(CLKIN) Period jitter, CLKIN 0.02C 0.02C 0.02C † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ For more details on the PLL multiplier factors (x6, x12, x20), see the Clock PLL section of this data sheet. § C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. 0.02C ns 1 5 4 2 CLKIN 3 4 Figure 16. CLKIN Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 81 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for CLKOUT4†‡§ (see Figure 17) −600, −720 −850, −1G NO. CLKMODE = x1, x6, x12, x20 PARAMETER MIN 1 2 3 4 UNIT MAX tJ(CKO4) tw(CKO4H) Period jitter, CLKOUT4 0 ±175 ps Pulse duration, CLKOUT4 high 2P − 0.7 2P + 0.7 ns tw(CKO4L) tt(CKO4) Pulse duration, CLKOUT4 low 2P − 0.7 2P + 0.7 ns 1 ns Transition time, CLKOUT4 † The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. ‡ PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. § P = 1/CPU clock frequency in nanoseconds (ns) 1 4 2 CLKOUT4 3 4 Figure 17. CLKOUT4 Timing switching characteristics over recommended operating conditions for CLKOUT6†‡§ (see Figure 18) −600, −720 −850, −1G NO. CLKMODE = x1, x6, x12, x20 PARAMETER MIN 1 2 3 4 MAX 0 ±175 ps Pulse duration, CLKOUT6 high 3P − 0.7 3P + 0.7 ns Pulse duration, CLKOUT6 low 3P − 0.7 3P + 0.7 ns 1 ns tJ(CKO6) tw(CKO6H) Period jitter, CLKOUT6 tw(CKO6L) tt(CKO6) Transition time, CLKOUT6 † The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. ‡ PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. § P = 1/CPU clock frequency in nanoseconds (ns) 1 4 2 CLKOUT6 3 4 Figure 18. CLKOUT6 Timing 82 UNIT POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 INPUT AND OUTPUT CLOCKS (CONTINUED) timing requirements for ECLKIN for EMIFA and EMIFB†‡§¶ (see Figure 19) −600 −720 −850 −1G NO. UNIT MAX CVDD = 1.2 V MIN 6# 16P ns CVDD = 1.1 V 7.5# 16P ns 1 tc(EKI) Cycle time, ECLKIN 2 Pulse duration, ECLKIN high 2.7 3 tw(EKIH) tw(EKIL) Pulse duration, ECLKIN low 2.7 4 tt(EKI) Transition time, ECLKIN ns ns 2 ns 5 tJ(EKI) Period jitter, ECLKIN 0.02E ns † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. ‡ The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. § These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted. ¶ E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. # Minimum ECLKIN cycle times must be met, even when ECLKIN is generated by an internal clock source. Minimum ECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. On the devices, 133-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. 1 5 4 2 ECLKIN 3 4 Figure 19. ECLKIN Timing for EMIFA and EMIFB switching characteristics over recommended operating conditions for ECLKOUT1 for EMIFA and EMIFB modules§¶|| (see Figure 20) NO. −600 −720 −850 −1G PARAMETER MIN 1 2 3 4 5 UNIT tJ(EKO1) tw(EKO1H) Period jitter, ECLKOUT1 0 MAX ±175 Pulse duration, ECLKOUT1 high EH − 0.7 EH + 0.7 ns tw(EKO1L) tt(EKO1) Pulse duration, ECLKOUT1 low EL − 0.7 EL + 0.7 ns 1 ns td(EKIH-EKO1H) td(EKIL-EKO1L) Delay time, ECLKIN high to ECLKOUT1 high 8 ns Transition time, ECLKOUT1 0.8 ps 6 Delay time, ECLKIN low to ECLKOUT1 low 0.8 8 ns § These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted. ¶ E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. || The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.  EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA or EMIFB.  This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 83 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 INPUT AND OUTPUT CLOCKS (CONTINUED) ECLKIN 1 6 5 3 4 4 2 ECLKOUT1 Figure 20. ECLKOUT1 Timing for EMIFA and EMIFB Modules switching characteristics over recommended operating conditions for ECLKOUT2 for the EMIFA and EMIFB modules†‡§ (see Figure 21) NO. −600 −720 −850 −1G PARAMETER UNIT MIN 1 2 3 4 5 6 MAX 0 ±175¶ ps Pulse duration, ECLKOUT2 high 0.5NE − 0.7 0.5NE + 0.7 ns Pulse duration, ECLKOUT2 low 0.5NE − 0.7 0.5NE + 0.7 ns tJ(EKO2) tw(EKO2H) Period jitter, ECLKOUT2 tw(EKO2L) tt(EKO2) 1 ns td(EKIH-EKO2H) td(EKIH-EKO2L) Delay time, ECLKIN high to ECLKOUT2 high 3 8 ns Delay time, ECLKIN high to ECLKOUT2 low 3 8 Transition time, ECLKOUT2 ns † The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. ‡ These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted. § E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. N = the EMIF input clock divider; N = 1, 2, or 4. ¶ This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock. 5 6 ECLKIN 1 3 2 ECLKOUT2 Figure 21. ECLKOUT2 Timing for the EMIFA and EMIFB Modules 84 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 4 4 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles for EMIFA module†‡§ (see Figure 22 and Figure 23) −600 −720 −850 −1G NO. MIN 3 4 6 7 tsu(EDV-AREH) th(AREH-EDV) Setup time, EDx valid before ARE high tsu(ARDY-EKO1H) th(EKO1H-ARDY) UNIT MAX 6.5 ns Hold time, EDx valid after ARE high 1 ns Setup time, ARDY valid before ECLKOUTx high 3 ns Hold time, ARDY valid after ECLKOUTx high 1 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is only recognized two cycles before the end of the programmed strobe time and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is recognized low, the end of the strobe time is two cycles after ARDY is recognized high. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. switching characteristics over recommended operating conditions for asynchronous memory cycles for EMIFA module‡§¶# (see Figure 22 and Figure 23) NO. −600 −720 −850 −1G PARAMETER MIN 1 2 5 8 9 10 tosu(SELV-AREL) toh(AREH-SELIV) Output setup time, select signals valid to ARE low RS * E − 1.5 Output hold time, ARE high to select signals invalid RH * E − 1.9 td(EKO1H-AREV) tosu(SELV-AWEL) Delay time, ECLKOUTx high to ARE valid Output setup time, select signals valid to AWE low WS * E − 1.7 toh(AWEH-SELIV) td(EKO1H-AWEV) Output hold time, AWE high to select signals invalid WH * E − 1.8 Delay time, ECLKOUTx high to AWE valid 1 MAX ns ns 7 ns ns ns ns ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. ¶ E = ECLKOUT1 period in ns for EMIFA or EMIFB # Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0]. Select signals EMIFB include: BCEx, BBE[1:0], BEA[20:1], BAOE; and for EMIFB writes, include BED[15:0]. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 1.3 UNIT 7.1 85 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 ASYNCHRONOUS MEMORY TIMING (CONTINUED) timing requirements for asynchronous memory cycles for EMIFB module†‡§ (see Figure 22 and Figure 23) −600 −720 −850 −1G NO. MIN 3 4 6 7 tsu(EDV-AREH) th(AREH-EDV) Setup time, EDx valid before ARE high tsu(ARDY-EKO1H) th(EKO1H-ARDY) Setup time, ARDY valid before ECLKOUTx high Hold time, EDx valid after ARE high Hold time, ARDY valid after ECLKOUTx high UNIT MAX 6.2 ns 1 ns 3 ns 1.2 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is only recognized two cycles before the end of the programmed strobe time and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is recognized low, the end of the strobe time is two cycles after ARDY is recognized high. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. switching characteristics over recommended operating conditions for asynchronous memory cycles for EMIFB module‡§¶# (see Figure 22 and Figure 23) NO. −600 −720 −850 −1G PARAMETER MIN 1 2 5 8 9 10 UNIT MAX tosu(SELV-AREL) toh(AREH-SELIV) Output setup time, select signals valid to ARE low RS * E − 1.6 ns Output hold time, ARE high to select signals invalid RH * E − 1.7 ns td(EKO1H-AREV) tosu(SELV-AWEL) Delay time, ECLKOUTx high to ARE valid Output setup time, select signals valid to AWE low WS * E − 1.9 toh(AWEH-SELIV) td(EKO1H-AWEV) Output hold time, AWE high to select signals invalid WH * E − 1.7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 0.9 6.6 ns ns ns ns ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. ¶ E = ECLKOUT1 period in ns for EMIFA or EMIFB # Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0]. Select signals EMIFB include: BCEx, BBE[1:0], BEA[20:1], BAOE; and for EMIFB writes, include BED[15:0]. 86 Delay time, ECLKOUTx high to AWE vaild 0.8 6.7 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Not Ready Hold = 2 ECLKOUTx 1 2 1 2 CEx BE ABE[7:0] or BBE[1:0] 2 1 Address AEA[22:3] or BEA[20:1] 3 4 AED[63:0] or BED[15:0] 1 2 Read Data AOE/SDRAS/SOE‡ 5 5 ARE/SDCAS/SADS/SRE‡ AWE/SDWE/SWE‡ 7 7 6 6 ARDY † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. ‡ AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. Figure 22. Asynchronous Memory Read Timing for EMIFA and EMIFB† POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 87 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Hold = 2 Not Ready ECLKOUTx 9 8 CEx 9 8 ABE[7:0] or BBE[1:0] BE 9 8 AEA[22:3] or BEA[20:1] Address 9 8 AED[63:0] or BED[15:0] Write Data AOE/SDRAS/SOE‡ ARE/SDCAS/SADS/SRE‡ 10 10 AWE/SDWE/SWE‡ 7 6 7 6 ARDY † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and BAWE (for EMIFB)]. ‡ AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. Figure 23. Asynchronous Memory Write Timing for EMIFA and EMIFB† 88 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING timing requirements for programmable synchronous interface cycles for EMIFA module† (see Figure 24) −600 −720 −850 −1G NO. MIN 6 tsu(EDV-EKOxH) th(EKOxH-EDV) Setup time, read EDx valid before ECLKOUTx high UNIT MAX 2 ns 7 Hold time, read EDx valid after ECLKOUTx high 1.5 ns † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. switching characteristics over recommended operating conditions for synchronous interface cycles for EMIFA module†‡ (see Figure 24−Figure 26) NO. 1 2 3 4 5 8 9 10 11 12 PARAMETER programmable −600 −720 −850 −1G UNIT MIN MAX 1.3 4.9 ns 4.9 ns td(EKOxH-CEV) td(EKOxH-BEV) Delay time, ECLKOUTx high to CEx valid td(EKOxH-BEIV) td(EKOxH-EAV) Delay time, ECLKOUTx high to BEx invalid td(EKOxH-EAIV) td(EKOxH-ADSV) Delay time, ECLKOUTx high to EAx invalid 1.3 Delay time, ECLKOUTx high to SADS/SRE valid 1.3 4.9 ns td(EKOxH-OEV) td(EKOxH-EDV) Delay time, ECLKOUTx high to, SOE valid 1.3 4.9 ns 4.9 ns td(EKOxH-EDIV) td(EKOxH-WEV) Delay time, ECLKOUTx high to EDx invalid 1.3 Delay time, ECLKOUTx high to SWE valid 1.3 Delay time, ECLKOUTx high to BEx valid 1.3 Delay time, ECLKOUTx high to EAx valid ns 4.9 Delay time, ECLKOUTx high to EDx valid ns ns ns ns † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. ‡ The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): − Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency − Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency − CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). − Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). − Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 4.9 89 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED) timing requirements for programmable synchronous interface cycles for EMIFB module† (see Figure 24) −600 −720 −850 −1G NO. MIN 6 tsu(EDV-EKOxH) th(EKOxH-EDV) Setup time, read EDx valid before ECLKOUTx high UNIT MAX 3.1 ns 7 Hold time, read EDx valid after ECLKOUTx high 1.5 ns † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. switching characteristics over recommended operating conditions for synchronous interface cycles for EMIFB module†‡ (see Figure 24−Figure 26) NO. 1 2 3 4 5 8 9 10 11 12 PARAMETER programmable −600 −720 −850 −1G UNIT MIN MAX 1.3 6.4 ns 6.4 ns td(EKOxH-CEV) td(EKOxH-BEV) Delay time, ECLKOUTx high to CEx valid td(EKOxH-BEIV) td(EKOxH-EAV) Delay time, ECLKOUTx high to BEx invalid td(EKOxH-EAIV) td(EKOxH-ADSV) Delay time, ECLKOUTx high to EAx invalid 1.3 Delay time, ECLKOUTx high to SADS/SRE valid 1.3 6.4 ns td(EKOxH-OEV) td(EKOxH-EDV) Delay time, ECLKOUTx high to, SOE valid 1.3 6.4 ns 6.4 ns td(EKOxH-EDIV) td(EKOxH-WEV) Delay time, ECLKOUTx high to EDx invalid 1.3 Delay time, ECLKOUTx high to SWE valid 1.3 Delay time, ECLKOUTx high to BEx valid 1.3 Delay time, ECLKOUTx high to EAx valid ns 6.4 Delay time, ECLKOUTx high to EDx valid ns ns ns ns † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. ‡ The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): − Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency − Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency − CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). − Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). − Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 90 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 6.4 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED) READ latency = 2 ECLKOUTx 1 1 CEx ABE[7:0] or BBE[1:0] 2 BE1 3 BE2 BE3 BE4 4 AEA[22:3] or BEA[20:1] EA1 5 EA3 EA2 6 AED[63:0] or BED[15:0] EA4 7 Q1 Q2 Q3 Q4 8 8 ARE/SDCAS/SADS/SRE§ 9 9 AOE/SDRAS/SOE§ AWE/SDWE/SWE§ † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. ‡ The read latency and the length of CEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIFx CE Space Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and CEEXT = 0. § The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): − Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency − Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency − CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). − Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). − Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 ¶ ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during programmable synchronous interface accesses. Figure 24. Programmable Synchronous Interface Read Timing for EMIFA and EMIFB (With Read Latency = 2)†‡§ POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 91 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED) ECLKOUTx 1 1 CEx ABE[7:0] or BBE[1:0] 2 BE1 AEA[22:3] or BEA[20:1] 4 EA1 EA2 EA3 EA4 10 Q1 Q2 Q3 Q4 10 AED[63:0] or BED[15:0] 3 BE2 BE3 BE4 5 11 8 8 ARE/SDCAS/SADS/SRE¶ AOE/SDRAS/SOE¶ 12 12 AWE/SDWE/SWE¶ † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. ‡ The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFx CE Space Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and CEEXT = 0. § The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): − Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency − Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency − CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). − Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). − Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 ¶ ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during programmable synchronous interface accesses. Figure 25. Programmable Synchronous Interface Write Timing for EMIFA and EMIFB (With Write Latency = 0)†‡§ 92 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED) Write Latency = 1‡ ECLKOUTx 1 1 CEx ABE[7:0] or BBE[1:0] 2 BE1 AEA[22:3] or BEA[20:1] 4 EA1 10 AED[63:0] or BED[15:0] 3 BE2 BE3 BE4 5 EA2 10 EA3 EA4 Q1 Q2 Q3 11 Q4 8 8 ARE/SDCAS/SADS/SRE¶ AOE/SDRAS/SOE¶ 12 12 AWE/SDWE/SWE¶ † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)]. ‡ The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFx CE Space Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0. § The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): − Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency − Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency − CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). − Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). − Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 ¶ ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during programmable synchronous interface accesses. Figure 26. Programmable Synchronous Interface Write Timing for EMIFA and EMIFB (With Write Latency = 1)†‡§ POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 93 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles for EMIFA module† (see Figure 27) −600 −720 −850 −1G NO. MIN 6 7 tsu(EDV-EKO1H) th(EKO1H-EDV) Setup time, read EDx valid before ECLKOUTx high Hold time, read EDx valid after ECLKOUTx high CVDD = 1.2 V UNIT MAX 0.6 ns 1.8 ns CVDD = 1.1 V 2.0 ns † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. switching characteristics over recommended operating conditions for synchronous DRAM cycles for EMIFA module† (see Figure 27−Figure 34) NO. 1 PARAMETER −600 −720 −850 −1G UNIT MIN MAX 1.3 4.9 ns 4.9 ns td(EKO1H-CEV) td(EKO1H-BEV) Delay time, ECLKOUTx high to CEx valid td(EKO1H-BEIV) td(EKO1H-EAV) Delay time, ECLKOUTx high to BEx invalid td(EKO1H-EAIV) td(EKO1H-CASV) Delay time, ECLKOUTx high to EAx invalid 1.3 Delay time, ECLKOUTx high to SDCAS valid 1.3 td(EKO1H-EDV) td(EKO1H-EDIV) Delay time, ECLKOUTx high to EDx valid Delay time, ECLKOUTx high to EDx invalid 1.3 Delay time, ECLKOUTx high to SDWE valid 1.3 4.9 ns 12 td(EKO1H-WEV) td(EKO1H-RAS) Delay time, ECLKOUTx high to SDRAS valid 1.3 4.9 ns 13 td(EKO1H-ACKEV) Delay time, ECLKOUTx high to ASDCKE valid (EMIFA only) 1.3 4.9 ns 2 3 4 5 8 9 10 11 Delay time, ECLKOUTx high to BEx valid 1.3 Delay time, ECLKOUTx high to EAx valid ns 4.9 ns ns 4.9 ns 4.9 ns ns 14 td(EKO1H-PDTV) Delay time, ECLKOUTx high to PDT valid 1.3 4.9 ns † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. 94 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 SYNCHRONOUS DRAM TIMING (CONTINUED) timing requirements for synchronous DRAM cycles for EMIFB module† (see Figure 27) −600 −720 −850 −1G NO. MIN 6 7 tsu(EDV-EKO1H) th(EKO1H-EDV) Setup time, read EDx valid before ECLKOUTx high 2.1 Hold time, read EDx valid after ECLKOUTx high 2.5 UNIT MAX ns ns † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. switching characteristics over recommended operating conditions for synchronous DRAM cycles for EMIFB module† (see Figure 27−Figure 34) NO. 1 PARAMETER −600 −720 −850 −1G UNIT MIN MAX 1.3 6.4 ns 6.4 ns td(EKO1H-CEV) td(EKO1H-BEV) Delay time, ECLKOUTx high to CEx valid td(EKO1H-BEIV) td(EKO1H-EAV) Delay time, ECLKOUTx high to BEx invalid td(EKO1H-EAIV) td(EKO1H-CASV) Delay time, ECLKOUTx high to EAx invalid 1.3 Delay time, ECLKOUTx high to SDCAS valid 1.3 td(EKO1H-EDV) td(EKO1H-EDIV) Delay time, ECLKOUTx high to EDx valid Delay time, ECLKOUTx high to EDx invalid 1.3 td(EKO1H-WEV) td(EKO1H-RAS) Delay time, ECLKOUTx high to SDWE valid 1.3 6.4 ns 12 Delay time, ECLKOUTx high to SDRAS valid 1.3 6.4 ns 13 td(EKO1H-ACKEV) Delay time, ECLKOUTx high to ASDCKE valid (EMIFA only) 1.3 6.4 ns 2 3 4 5 8 9 10 11 Delay time, ECLKOUTx high to BEx valid 1.3 Delay time, ECLKOUTx high to EAx valid ns 6.4 ns ns 6.4 ns 6.4 ns ns 14 td(EKO1H-PDTV) Delay time, ECLKOUTx high to PDT valid 1.3 6.4 ns † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 95 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 SYNCHRONOUS DRAM TIMING (CONTINUED) READ ECLKOUTx 1 1 CEx 2 BE1 ABE[7:0] or BBE[1:0] AEA[22:14] or BEA[20:12] AEA[12:3] or BEA[10:1] 4 Bank 5 4 Column 5 4 3 BE2 BE3 BE4 5 AEA13 or BEA11 6 D1 AED[63:0] or BED[15:0] 7 D2 D3 D4 AOE/SDRAS/SOE‡ 8 8 ARE/SDCAS/SADS/SRE‡ AWE/SDWE/SWE‡ 14 14 PDT§ † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ‡ ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. § PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data phase of a read transaction. The latency of the PDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11, respectively. PDTRL equals 00 (zero latency) in Figure 27. Figure 27. SDRAM Read Command (CAS Latency 3) for EMIFA and EMIFB† 96 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 SYNCHRONOUS DRAM TIMING (CONTINUED) WRITE ECLKOUTx 1 2 CEx 2 3 4 ABE[7:0] or BBE[1:0] BE1 4 BE2 BE3 BE4 D2 D3 D4 5 Bank AEA[22:14] or BEA[20:12] 4 5 Column AEA[12:3] or BEA[10:1] 4 5 AEA13 or BEA11 9 AED[63:0] or BED[15:0] 10 9 D1 AOE/SDRAS/SOE‡ 8 8 11 11 ARE/SDCAS/SADS/SRE‡ AWE/SDWE/SWE‡ 14 14 PDT§ † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ‡ ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. § PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data phase of a write transaction. The latency of the PDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00, 01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 28. Figure 28. SDRAM Write Command for EMIFA and EMIFB† POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 97 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 SYNCHRONOUS DRAM TIMING (CONTINUED) ACTV ECLKOUTx 1 1 CEx ABE[7:0] or BBE[1:0] 4 Bank Activate 5 AEA[22:14] or BEA[20:12] 4 Row Address 5 AEA[12:3] or BEA[10:1] 4 Row Address 5 AEA13 or BEA11 AED[63:0] or BED[15:0] 12 12 AOE/SDRAS/SOE‡ ARE/SDCAS/SADS/SRE‡ AWE/SDWE/SWE‡ † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ‡ ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 29. SDRAM ACTV Command for EMIFA and EMFB† 98 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 SYNCHRONOUS DRAM TIMING (CONTINUED) DCAB ECLKOUTx 1 1 4 5 12 12 11 11 CEx ABE[7:0] or BBE[1:0] AEA[22:14, 12:3] or BEA[20:12, 10:1] AEA13 or BEA11 AED[63:0] or BED[15:0] AOE/SDRAS/SOE‡ ARE/SDCAS/SADS/SRE‡ AWE/SDWE/SWE‡ † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ‡ ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 30. SDRAM DCAB Command for EMIFA and EMIFB† POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 99 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 SYNCHRONOUS DRAM TIMING (CONTINUED) DEAC ECLKOUTx 1 1 CEx ABE[7:0] or BBE[1:0] 4 5 Bank AEA[22:14] or BEA[20:12] AEA[12:3] or BEA[10:1] 4 5 12 12 11 11 AEA13 or BEA11 AED[63:0] or BED[15:0] AOE/SDRAS/SOE‡ ARE/SDCAS/SADS/SRE‡ AWE/SDWE/SWE‡ † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ‡ ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 31. SDRAM DEAC Command for EMIFA and EMIFB† 100 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 SYNCHRONOUS DRAM TIMING (CONTINUED) REFR ECLKOUTx 1 1 12 12 8 8 CEx ABE[7:0] or BBE[1:0] AEA[22:14, 12:3] or BEA[20:12, 10:1] AEA13 or BEA11 AED[63:0] or BED[15:0] AOE/SDRAS/SOE‡ ARE/SDCAS/SADS/SRE‡ AWE/SDWE/SWE‡ † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ‡ ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 32. SDRAM REFR Command for EMIFA and EMIFB† POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 101 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 SYNCHRONOUS DRAM TIMING (CONTINUED) MRS ECLKOUTx 1 1 4 MRS value 5 12 12 8 8 11 11 CEx ABE[7:0] or BBE[1:0] AEA[22:3] or BEA[20:1] AED[63:0] or BED[15:0] AOE/SDRAS/SOE‡ ARE/SDCAS/SADS/SRE‡ AWE/SDWE/SWE‡ † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ‡ ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 33. SDRAM MRS Command for EMIFA and EMIFB† 102 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 SYNCHRONOUS DRAM TIMING (CONTINUED) ≥ TRAS cycles End Self-Refresh Self Refresh AECLKOUTx ACEx ABE[7:0] AEA[22:14, 12:3] AEA13 AED[63:0] AAOE/ASDRAS/ASOE‡ AARE/ASDCAS/ASADS/ ASRE‡ AAWE/ASDWE/ASWE‡ 13 13 ASDCKE † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ‡ AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. Figure 34. SDRAM Self-Refresh Timing for EMIFA Only† POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 103 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles for EMIFA and EMIFB modules† (see Figure 35) −600, −720 −850, −1G NO. MIN 3 th(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low † E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. UNIT MAX E ns switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles for EMIFA and EMIFB modules†‡§ (see Figure 35) NO. −600, −720 −850, −1G PARAMETER MIN 1 2 4 5 6 7 UNIT 2E MAX ¶ ns 0 2E ns td(HOLDL-EMHZ) td(EMHZ-HOLDAL) Delay time, HOLD low to EMIF Bus high impedance td(HOLDH-EMLZ) td(EMLZ-HOLDAH) Delay time, HOLD high to EMIF Bus low impedance 2E 7E ns Delay time, EMIF Bus low impedance to HOLDA high 0 ns td(HOLDL-EKOHZ) td(HOLDH-EKOLZ) Delay time, HOLD low to ECLKOUTx high impedance 2E 2E ¶ Delay time, HOLD high to ECLKOUTx low impedance 2E 7E Delay time, EMIF Bus high impedance to HOLDA low ns ns † E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. ‡ For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT. For EMIFB, EMIF Bus consists of: BCE[3:0], BBE[1:0], BED[15:0], BEA[20:1], BARE/BSDCAS/BSADS/BSRE, BAOE/BSDRAS/BSOE, and BAWE/BSDWE/BSWE, BSOE3, and BPDT. § The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0, ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35. ¶ All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. External Requestor Owns Bus DSP Owns Bus DSP Owns Bus 3 HOLD 2 5 HOLDA EMIF Bus† 1 4 C64x C64x ECLKOUTx‡ (EKxHZ = 0) ECLKOUTx‡ (EKxHZ = 1) 6 7 † For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT. For EMIFB, EMIF Bus consists of: BCE[3:0], BBE[1:0], BED[15:0], BEA[20:1], BARE/BSDCAS/BSADS/BSRE, BAOE/BSDRAS/BSOE, and BAWE/BSDWE/BSWE, BSOE3, and BPDT. ‡ The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0, ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35. Figure 35. HOLD/HOLDA Timing for EMIFA and EMIFB 104 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 BUSREQ TIMING switching characteristics over recommended operating conditions for the BUSREQ cycles for EMIFA and EMIFB modules (see Figure 36) NO. 1 2 −600 −720 −850 −1G PARAMETER td(AEKO1H-ABUSRV) td(BEKO1H-BBUSRV) UNIT MIN MAX Delay time, AECLKOUTx high to ABUSREQ valid 1 5.5 ns Delay time, BECLKOUTx high to BBUSREQ valid 0.9 5.5 ns ECLKOUTx 1 1 2 2 ABUSREQ BBUSREQ Figure 36. BUSREQ Timing for EMIFA and EMIFB POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 105 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 RESET TIMING timing requirements for reset† (see Figure 37) −600, −720, −850, −1G NO. MIN Width of the RESET pulse (PLL stable)‡ 1 16 17 tw(RST) Width of the RESET pulse (PLL needs to sync up)§ tsu(boot) th(boot) Setup time, boot configuration bits valid before RESET high¶ Hold time, boot configuration bits valid after RESET high¶ UNIT MAX 250 µs 250 4E or 4C# µs 4P ns ns Setup time, PCLK active before RESET high|| 18 tsu(PCLK-RSTH) 32N ns † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. ‡ This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x6, x12, x20 when CLKIN and PLL are stable. § This parameter applies to CLKMODE x6, x12, x20 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. ¶ EMIFB address pins BEA[20:13, 11, 9:7] are the boot configuration pins during device reset. # E = 1/AECLKIN clock frequency in ns. C = 1/CLKIN clock frequency in ns. Select whichever value is larger for the MIN parameter. || N = the PCI input clock (PCLK) period in ns. When PCI is enabled (PCI_EN = 1), this parameter must be met. switching characteristics over recommended operating conditions during reset†kh (see Figure 37) NO. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 −600, −720, −850, −1G PARAMETER UNIT MIN MAX td(RSTL-ECKI) td(RSTH-ECKI) Delay time, RESET low to ECLKIN synchronized internally 2E 3P + 20E ns Delay time, RESET high to ECLKIN synchronized internally 2E 16 070P ns td(RSTL-ECKO1HZ) td(RSTH-ECKO1V) Delay time, RESET low to ECLKOUT1 high impedance 2E td(RSTL-EMIFZHZ) td(RSTH-EMIFZV) Delay time, RESET low to EMIF Z high impedance td(RSTL-EMIFHIV) td(RSTH-EMIFHV) Delay time, RESET low to EMIF high group invalid td(RSTL-EMIFLIV) td(RSTH-EMIFLV) Delay time, RESET low to EMIF low group invalid td(RSTL-LOWIV) td(RSTH-LOWV) Delay time, RESET low to low group invalid td(RSTL-ZHZ) td(RSTH-ZV) Delay time, RESET low to Z group high impedance Delay time, RESET high to ECLKOUT1 valid Delay time, RESET high to EMIF Z valid ns 2E 3P + 4E ns 16E 16 070P ns 2E Delay time, RESET high to EMIF high group valid ns 16 070P 2E Delay time, RESET high to EMIF low group valid 16 070P ns ns 16 070P 0 2P ns ns 0 Delay time, RESET high to low group valid Delay time, RESET high to Z group valid ns 16 070P ns ns 16 070P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.  E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.  EMIF Z group consists of: AEA[22:3], BEA[20:1], AED[63:0], BED[15:0], CE[3:0], ABE[7:0], BBE[1:0], ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE, SOE3, ASDCKE, and PDT. EMIF high group consists of: AHOLDA and BHOLDA (when the corresponding HOLD input is high) EMIF low group consists of: ABUSREQ and BBUSREQ; AHOLDA and BHOLDA (when the corresponding HOLD input is low) Low group consists of: XSP_CS, CLKX2/XSP_CLK, and DX2/XSP_DO; all of which apply only when PCI EEPROM (BEA13) is enabled (with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the CLKX2/XSP_CLK and DX2/XSP_DO pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations section of this data sheet. Z group consists of: HD[31:0]/AD[31:0], CLKX0, CLKX1/URADDR4, CLKX2/XSP_CLK, FSX0, FSX1/UXADDR3, FSX2, DX0, DX1/UXADDR4, DX2/XSP_DO, CLKR0, CLKR1/URADDR2, CLKR2, FSR0, FSR1/UXADDR2, FSR2, TOUT0, TOUT1, TOUT2, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP13/PINTA, GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP, HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, UXDATA[7:0], UXSOC, UXCLAV, and URCLAV. 106 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 RESET TIMING (CONTINUED) CLKOUT4 CLKOUT6 1 RESET 18 PCLK 2 3 4 5 6 7 ECLKIN ECLKOUT1 ECLKOUT2 EMIF Z Group‡§ 8 9 10 11 EMIF High Group‡ EMIF Low Group‡ 12 13 14 15 Low Group‡ Z Group‡§ Boot and Device Configuration Inputs§¶ 16 17 † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., ECLKIN, ECLKOUT1, and ECLKOUT2]. ‡ EMIF Z group consists of: AEA[22:3], BEA[20:1], AED[63:0], BED[15:0], CE[3:0], ABE[7:0], BBE[1:0], ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE, SOE3, ASDCKE, and PDT. EMIF high group consists of: AHOLDA and BHOLDA (when the corresponding HOLD input is high) EMIF low group consists of: ABUSREQ and BBUSREQ; AHOLDA and BHOLDA (when the corresponding HOLD input is low) Low group consists of: XSP_CS, CLKX2/XSP_CLK, and DX2/XSP_DO; all of which apply only when PCI EEPROM (BEA13) is enabled (with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the CLKX2/XSP_CLK and DX2/XSP_DO pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations section of this data sheet. Z group consists of: HD[31:0]/AD[31:0], CLKX0, CLKX1/URADDR4, CLKX2/XSP_CLK, FSX0, FSX1/UXADDR3, FSX2, DX0, DX1/UXADDR4, DX2/XSP_DO, CLKR0, CLKR1/URADDR2, CLKR2, FSR0, FSR1/UXADDR2, FSR2, TOUT0, TOUT1, TOUT2, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP13/PINTA, GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP, HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, UXDATA[7:0], UXSOC, UXCLAV, and URCLAV. § If BEA[20:13, 11, 7] and HD5/AD5 pins are actively driven, care must be taken to ensure no timing contention between parameters 6, 7, 14, 15, 16, and 17. ¶ Boot and Device Configurations Inputs (during reset) include: EMIFB address pins BEA[20:13, 11, 9:7] and HD5/AD5. The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation. The MCBSP2_EN pin must be driven valid at all times and the user can switch values throughout device operation. Figure 37. Reset Timing† POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 107 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 EXTERNAL INTERRUPT TIMING timing requirements for external interrupts† (see Figure 38) −600 −720 −850 −1G NO. MIN 1 2 tw(ILOW) MAX Width of the NMI interrupt pulse low 4P ns Width of the EXT_INT interrupt pulse low 8P ns Width of the NMI interrupt pulse high 4P ns 8P ns tw(IHIGH) Width of the EXT_INT interrupt pulse high † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. 1 2 EXT_INTx, NMI Figure 38. External/NMI Interrupt Timing 108 UNIT POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 HOST-PORT INTERFACE (HPI) TIMING timing requirements for host-port interface cycles†‡ (see Figure 39 through Figure 46) −600 −850 −720 −1G NO. MIN 1 2 3 4 10 11 12 tsu(SELV-HSTBL) th(HSTBL-SELV) Setup time, select signals§ valid before HSTROBE low Hold time, select signals§ valid after HSTROBE low tw(HSTBL) tw(HSTBH) Pulse duration, HSTROBE low tsu(SELV-HASL) th(HASL-SELV) 13 tsu(HDV-HSTBH) th(HSTBH-HDV) 14 th(HRDYL-HSTBL) 18 tsu(HASL-HSTBL) th(HSTBL-HASL) UNIT MAX 5 ns 2.4 4P¶ ns 4P ns 5 ns Hold time, select signals§ valid after HAS low 2 ns Setup time, host data valid before HSTROBE high 5 ns 2.8 ns Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 2 ns Setup time, HAS low before HSTROBE low 2 ns 2.1 ns Pulse duration, HSTROBE high between consecutive accesses Setup time, select signals§ valid before HAS low Hold time, host data valid after HSTROBE high 19 Hold time, HAS low after HSTROBE low † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. § Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL. ¶ Select the parameter value of 4P or 12.5 ns, whichever is greater. ns switching characteristics over recommended operating conditions during host-port interface cycles†‡ (see Figure 39 through Figure 46) NO. −600 −850 −720 −1G PARAMETER 6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high# 7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 8 9 td(HDV-HRDYL) toh(HSTBH-HDV) 15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance UNIT MIN MAX 1.3 4P + 8 ns 2 ns Delay time, HD valid to HRDY low −3 ns Output hold time, HD valid after HSTROBE high 1.5 ns 12 ns 16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word only) 4P + 8 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. # This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16) on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is full. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 109 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 HOST-PORT INTERFACE (HPI) TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 4 3 HSTROBE† 3 HCS 15 9 7 15 9 16 HD[15:0] (output) 1st half-word 6 2nd half-word 8 HRDY † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 39. HPI16 Read Timing (HAS Not Used, Tied High) HAS† 19 11 19 10 11 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 4 3 HSTROBE‡ 18 18 HCS 15 7 9 15 16 9 HD[15:0] (output) 6 1st half-word 8 2nd half-word HRDY † For correct operation, strobe the HAS signal only once per HSTROBE active cycle. ‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 40. HPI16 Read Timing (HAS Used) 110 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 HOST-PORT INTERFACE (HPI) TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 3 3 4 HSTROBE† HCS 12 12 13 13 HD[15:0] (input) 1st half-word 2nd half-word 6 14 HRDY † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 41. HPI16 Write Timing (HAS Not Used, Tied High) 19 HAS† 19 11 11 10 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 3 4 HSTROBE‡ 18 18 HCS 12 13 12 13 HD[15:0] (input) 1st half-word 6 2nd half-word 14 HRDY † For correct operation, strobe the HAS signal only once per HSTROBE active cycle. ‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 42. HPI16 Write Timing (HAS Used) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 111 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 HOST-PORT INTERFACE (HPI) TIMING (CONTINUED) HAS 1 2 1 2 HCNTL[1:0] HR/W 3 HSTROBE† HCS 7 9 15 HD[31:0] (output) 6 8 HRDY † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 43. HPI32 Read Timing (HAS Not Used, Tied High) 19 HAS† 11 10 HCNTL[1:0] 11 10 HR/W 18 3 HSTROBE‡ HCS 7 9 15 HD[31:0] (output) 6 8 HRDY † For correct operation, strobe the HAS signal only once per HSTROBE active cycle. ‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 44. HPI32 Read Timing (HAS Used) 112 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 HOST-PORT INTERFACE (HPI) TIMING (CONTINUED) HAS 1 2 1 2 HCNTL[1:0] HR/W 3 HSTROBE† HCS 12 13 HD[31:0] (input) 6 14 HRDY † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 45. HPI32 Write Timing (HAS Not Used, Tied High) 19 HAS† 11 10 HCNTL[1:0] 11 10 HR/W 3 18 HSTROBE‡ HCS 12 13 HD[31:0] (input) 6 14 HRDY † For correct operation, strobe the HAS signal only once per HSTROBE active cycle. ‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 46. HPI32 Write Timing (HAS Used) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 113 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415T AND C6416T ONLY] timing requirements for PCLK†‡ (see Figure 47) −600 −720 −850 −1G NO. MIN 1 2 3 UNIT MAX 30 (or 8P§) tc(PCLK) tw(PCLKH) Cycle time, PCLK Pulse duration, PCLK high 11 ns tw(PCLKL) tsr(PCLK) Pulse duration, PCLK low 11 ns 4 ∆v/∆t slew rate, PCLK † For 3.3-V operation, the reference points for the rise and fall transitions are measured at VILP MAX and VIHP MIN. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. § Select the parameter value of 30 ns or 8P, whichever is greater. 1 1 4 V/ns 0.4 DVDD V MIN Peak to Peak for 3.3V signaling 4 2 ns PCLK 3 4 Figure 47. PCLK Timing timing requirements for PCI reset (see Figure 48) −600 −720 −850 −1G NO. MIN 1 2 tw(PRST) tsu(PCLKA-PRSTH) Pulse duration, PRST Setup time, PCLK active before PRST high PCLK 1 PRST 2 Figure 48. PCI Reset (PRST) Timing 114 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 UNIT MAX 1 ms 100 µs 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415T AND C6416T ONLY] (CONTINUED) timing requirements for PCI inputs (see Figure 49) −600 −720 −850 −1G NO. MIN 5 6 tsu(IV-PCLKH) th(IV-PCLKH) UNIT MAX Setup time, input valid before PCLK high 7 ns Hold time, input valid after PCLK high 0 ns switching characteristics over recommended operating conditions for PCI outputs (see Figure 49) NO. −600 −720 −850 −1G PARAMETER MIN 1 2 3 4 td(PCLKH-OV) td(PCLKH-OIV) Delay time, PCLK high to output valid Delay time, PCLK high to output invalid 2 td(PCLKH-OLZ) td(PCLKH-OHZ) Delay time, PCLK high to output low impedance 2 UNIT MAX 11 Delay time, PCLK high to output high impedance ns ns ns 28 ns PCLK 1 2 Valid PCI Output 3 4 Valid PCI Input 5 6 Figure 49. PCI Input/Output Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 115 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415T AND C6416T ONLY] (CONTINUED) timing requirements for serial EEPROM interface (see Figure 50) −600 −720 −850 −1G NO. MIN 8 tsu(DIV-CLKH) th(CLKH-DIV) 9 Setup time, XSP_DI valid before XSP_CLK high UNIT MAX 50 ns 0 ns Hold time, XSP_DI valid after XSP_CLK high switching characteristics over recommended operating conditions for serial EEPROM interface† (see Figure 50) NO. −600 −720 −850 −1G PARAMETER MIN 1 2 3 4 5 6 tw(CSL) td(CLKL-CSL) Pulse duration, XSP_CS low td(CSH-CLKH) tw(CLKH) tw(CLKL) tosu(DOV-CLKH) UNIT TYP 4092P ns 0 ns Delay time, XSP_CS high to XSP_CLK high 2046P ns Pulse duration, XSP_CLK high 2046P ns Pulse duration, XSP_CLK low 2046P ns Output setup time, XSP_DO valid before XSP_CLK high 2046P ns 2046P ns Delay time, XSP_CLK low to XSP_CS low 7 toh(CLKH-DOV) Output hold time, XSP_DO valid after XSP_CLK high † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. 2 1 XSP_CS 3 4 5 XSP_CLK 7 6 XSP_DO 8 9 XSP_DI Figure 50. PCI Serial EEPROM Interface Timing 116 MAX POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING timing requirements for McBSP† (see Figure 51) −600 −720 −850 −1G NO. MIN 2 Cycle time, CLKR/X CLKR/X ext 3 tc(CKRX) tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low 8 th(CKRL-DRV) Hold time, DR valid after CLKR low 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low 11 th(CKXL-FXH) Hold time, external FSX high after CLKX low 4P or 6.67‡§¶ 0.5tc(CKRX) − 1# CLKR int 9 CLKR ext 1.3 CLKR int 6 CLKR ext 3 CLKR int 8 CLKR ext 0.9 CLKR int 3 CLKR ext 3.1 CLKX int 9 CLKX ext 1.3 CLKX int 6 CLKX ext 3 UNIT MAX ns ns ns ns ns ns ns ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. § P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ¶ Use whichever value is greater. # This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 117 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 51) NO. −600 −720 −850 −1G PARAMETER Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input UNIT MIN MAX 1.4 10 4P or 6.67§¶# C − 1|| C + 1|| ns ns 1 td(CKSH-CKRXH) 2 Cycle time, CLKR/X 3 tc(CKRX) tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int −2.1 3 CLKX int −1.7 3 CLKX ext 1.7 9 CLKX int −3.9 4 CLKX ext 2 9 CLKX int −3.9 + D1 4 + D2 CLKX ext 2.0 + D1 9 + D2 CLKR/X int 9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid 12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 13 td(CKXH-DXV) Delay time, CLKX high to DX valid 14 td(FXH-DXV) ns ns Delay time, FSX high to DX valid FSX int −2.3 + D1 5.6 + D2 ONLY applies when in data delay 0 (XDATDLY = 00b) mode FSX ext 1.9 + D1 9 + D2 ns ns ns ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum delay times also represent minimum output hold times. § Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. ¶ P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. # Use whichever value is greater. || C = H or L S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).  Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 4P, D2 = 8P  Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 4P, D2 = 8P 118 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 DR 8 Bit(n-1) (n-2) (n-3) 2 3 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13† Bit(n-1) 13† (n-2) (n-3) † Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0 Figure 51. McBSP Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 119 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 52) −600 −720 −850 −1G NO. MIN 1 2 tsu(FRH-CKSH) th(CKSH-FRH) MAX Setup time, FSR high before CLKS high 4 ns Hold time, FSR high after CLKS high 4 ns CLKS 1 2 FSR external CLKR/X (no need to resync) CLKR/X (needs resync) Figure 52. FSR Timing When GSYNC = 1 120 UNIT POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 53) −600 −720 −850 −1G NO. MASTER MIN 4 5 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low UNIT SLAVE MAX MIN MAX 12 2 − 12P ns 4 5 + 24P ns Hold time, DR valid after CLKX low † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics over recommended operating conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 53) NO. −600 −720 −850 −1G PARAMETER MASTER§ 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 UNIT SLAVE MIN MAX MIN T−2 T+3 ns L−2 L+3 ns −2 4 L−2 L+3 12P + 2.8 MAX 20P + 17 ns ns 4P + 3 12P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 8P + 1.8 16P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 121 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 53. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 122 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 54) −600, −720 −850, −1G NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX high 4 † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN MAX 2 − 12P ns 5 + 24P ns switching characteristics over recommended operating conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 54) −600, −720 −850, −1G NO. PARAMETER MASTER§ 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 1 6 UNIT SLAVE MIN MAX L−2 L+3 MIN MAX T−2 T+3 −2 4 12P + 2.8 20P + 17 ns −2 4 12P + 3 20P + 17 ns ns ns 7 td(FXL-DXV) Delay time, FSX low to DX valid H−2 H+4 8P + 2 16P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). CLKX 1 2 6 Bit 0 7 FSX DX 3 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 54. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 123 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 55) −600 −720 −850 −1G NO. UNIT MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high SLAVE MAX MIN MAX 12 2 − 12P ns 4 5 + 24P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics over recommended operating conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 55) NO. −600 −720 −850 −1G PARAMETER MASTER§ MIN 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 UNIT SLAVE MAX MIN MAX T−2 T+3 ns H−2 H+3 ns −2 4 H−2 H+3 12P + 2.8 20P + 17 ns ns 4P + 3 12P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 8P + 2 16P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). 124 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 55. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 125 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 56) −600 −720 −850 −1G NO. UNIT MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high SLAVE MAX MIN MAX 12 2 − 12P ns 4 5 + 24P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics over recommended operating conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 56) NO. −600 −720 −850 −1G PARAMETER MASTER§ UNIT SLAVE MIN MAX MIN MAX H−2 H+3 ns T−2 T+1 ns 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid −2 4 12P + 2.8 20P + 17 ns tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high −2 4 12P + 3 20P + 17 ns 1 6 7 td(FXL-DXV) Delay time, FSX low to DX valid L−2 L+4 8P + 2 16P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). 126 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 56. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 127 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 UTOPIA SLAVE TIMING [C6415T AND C6416T ONLY] timing requirements for UXCLK† (see Figure 57) −600 −720 −850 −1G NO. MIN 1 2 3 tc(UXCK) tw(UXCKH) Cycle time, UXCLK tw(UXCKL) tt(UXCK) Pulse duration, UXCLK low UNIT MAX 20 Pulse duration, UXCLK high ns 0.4tc(UXCK) 0.4tc(UXCK) 4 Transition time, UXCLK † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. 1 0.6tc(UXCK) 0.6tc(UXCK) ns 2 ns ns 4 2 UXCLK 3 4 Figure 57. UXCLK Timing timing requirements for URCLK† (see Figure 58) −600 −720 −850 −1G NO. MIN 1 2 3 4 tc(URCK) tw(URCKH) Cycle time, URCLK tw(URCKL) tt(URCK) Pulse duration, URCLK low MAX 20 Pulse duration, URCLK high ns 0.4tc(URCK) 0.4tc(URCK) Transition time, URCLK 0.6tc(URCK) 0.6tc(URCK) 2 † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. 1 4 2 URCLK 3 4 Figure 58. URCLK Timing 128 UNIT POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ns ns ns 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 UTOPIA SLAVE TIMING [C6415T AND C6416T ONLY] (CONTINUED) timing requirements for UTOPIA Slave transmit (see Figure 59) −600, −720 −850, −1G NO. MIN 2 3 8 9 UNIT MAX tsu(UXAV-UXCH) th(UXCH-UXAV) Setup time, UXADDR valid before UXCLK high 4 ns Hold time, UXADDR valid after UXCLK high 1 ns tsu(UXENBL-UXCH) th(UXCH-UXENBL) Setup time, UXENB low before UXCLK high 4 ns Hold time, UXENB low after UXCLK high 1 ns switching characteristics over recommended operating conditions for UTOPIA Slave transmit (see Figure 59) NO. 1 4 5 6 7 10 −600, −720 −850, −1G PARAMETER UNIT MIN MAX td(UXCH-UXDV) td(UXCH-UXCLAV) Delay time, UXCLK high to UXDATA valid 3 12 ns Delay time, UXCLK high to UXCLAV driven active value 3 12 ns td(UXCH-UXCLAVL) td(UXCH-UXCLAVHZ) Delay time, UXCLK high to UXCLAV driven inactive low 3 12 ns Delay time, UXCLK high to UXCLAV going Hi-Z 9 18.5 ns tw(UXCLAVL-UXCLAVHZ) td(UXCH-UXSV) Pulse duration (low), UXCLAV low to UXCLAV Hi-Z 3 Delay time, UXCLK high to UXSOC valid 3 ns 12 ns UXCLK 1 UXDATA[7:0] P45 P46 P47 P48 H1 3 2 UXADDR[4:0] 0 x1F N 0x1F N 0x1F N+1 0x1F 6 7 4 UXCLAV 5 N N 9 8 UXENB 10 UXSOC † The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLAV and UXSOC signals). Figure 59. UTOPIA Slave Transmit Timing† POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 129 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 UTOPIA SLAVE TIMING [C6415T AND C6416T ONLY] (CONTINUED) timing requirements for UTOPIA Slave receive (see Figure 60) −600, −720 −850, −1G NO. MIN 1 2 3 4 9 10 11 12 UNIT MAX tsu(URDV-URCH) th(URCH-URDV) Setup time, URDATA valid before URCLK high 4 ns Hold time, URDATA valid after URCLK high 1 ns tsu(URAV-URCH) th(URCH-URAV) Setup time, URADDR valid before URCLK high 4 ns Hold time, URADDR valid after URCLK high 1 ns tsu(URENBL-URCH) th(URCH-URENBL) Setup time, URENB low before URCLK high 4 ns Hold time, URENB low after URCLK high 1 ns tsu(URSH-URCH) th(URCH-URSH) Setup time, URSOC high before URCLK high 4 ns Hold time, URSOC high after URCLK high 1 ns switching characteristics over recommended operating conditions for UTOPIA Slave receive (see Figure 60) NO. −600, −720 −850, −1G PARAMETER UNIT MIN MAX 5 td(URCH-URCLAV) Delay time, URCLK high to URCLAV driven active value 3 12 ns 6 td(URCH-URCLAVL) Delay time, URCLK high to URCLAV driven inactive low 3 12 ns 7 td(URCH-URCLAVHZ) Delay time, URCLK high to URCLAV going Hi-Z 9 18.5 ns 8 tw(URCLAVL-URCLAVHZ) Pulse duration (low), URCLAV low to URCLAV Hi-Z 3 ns URCLK 2 1 URDATA[7:0] P48 H1 H2 H3 0x1F N+2 0x1F 4 3 URADDR[4:0] N 0x1F N+1 7 6 5 URCLAV N N+1 10 8 N+2 9 URENB 11 12 URSOC † The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and URSOC signals). Figure 60. UTOPIA Slave Receive Timing† 130 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 TIMER TIMING timing requirements for timer inputs† (see Figure 61) −600 −720 −850 −1G NO. MIN 1 2 tw(TINPH) tw(TINPL) UNIT MAX Pulse duration, TINP high 8P ns Pulse duration, TINP low 8P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. switching characteristics over recommended operating conditions for timer outputs† (see Figure 61) NO. −600 −720 −850 −1G PARAMETER MIN 3 4 tw(TOUTH) tw(TOUTL) UNIT MAX Pulse duration, TOUT high 8P −3 ns Pulse duration, TOUT low 8P −3 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. 2 1 TINPx 4 3 TOUTx Figure 61. Timer Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 131 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING timing requirements for GPIO inputs†‡ (see Figure 62) −600 −720 −850 −1G NO. MIN 1 2 tw(GPIH) tw(GPIL) Pulse duration, GPIx high 8P Pulse duration, GPIx low 8P UNIT MAX ns ns † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. ‡ The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to at least 12P to allow the DSP enough time to access the GPIO register through the CFGBUS. switching characteristics over recommended operating conditions for GPIO outputs† (see Figure 62) NO. −600 −720 −850 −1G PARAMETER MIN 3 4 tw(GPOH) tw(GPOL) 24P − 8§ 24P − 8§ Pulse duration, GPOx high Pulse duration, GPOx low UNIT MAX ns ns † P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns. § This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO is dependent upon internal bus activity. 2 1 GPIx 4 3 GPOx Figure 62. GPIO Port Timing 132 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 63) −600 −720 −850 −1G NO. MIN 1 UNIT MAX tc(TCK) tsu(TDIV-TCKH) Cycle time, TCK 35 ns 3 Setup time, TDI/TMS/TRST valid before TCK high 10 ns 4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns switching characteristics over recommended operating conditions for JTAG test port (see Figure 63) NO. 2 −600 −720 −850 −1G PARAMETER td(TCKL-TDOV) Delay time, TCK low to TDO valid UNIT MIN MAX 0 18 ns 1 TCK 2 2 TDO 4 3 TDI/TMS/TRST Figure 63. JTAG Test-Port Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 133 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 MECHANICAL DATA FOR C6414T, C6415T, AND C6416T The following table(s) show the thermal resistance characteristics for the PBGA — GLZ, ZLZ and CLZ mechanical packages. thermal resistance characteristics (S-PBGA package) [GLZ] Air Flow (m/s†) NO. 1 °C/W‡ °C/W (with Heat Sink§) RΘJC RΘJB Junction-to-case N/A 3.11 3.11 Junction-to-board N/A 9.95 9.95 RΘJA RΘJA Junction-to-free air 0.00 19.6 14.4 Junction-to-free air 0.5 17.3 11.5 Junction-to-free air 1.0 15.6 9.3 6 RΘJA RΘJA Junction-to-free air 2.00 14.7 8.0 7 PsiJT Junction-to-package top N/A 0.83 0.83 8 PsiJB Junction-to-board N/A 7.88 Air Flow (m/s†) °C/W‡ °C/W (with Heat Sink§) N/A 3.11 3.11 2 3 4 5 7.88 † m/s = meters per second ‡ Numbers are based on simulations. § These thermal resistance numbers were modeled using a heat sink, part number 374024B00035, manufactured by AAVID Thermalloy. AAVID Thermalloy also manufactures a similar epoxy-mounted heat sink, part number 374024B00000. When operating at 1 GHz, a heat sink is required to reduce the thermal resistance characteristics of the package. TI recommends a passive, laminar heat sink, similar to the part numbers mentioned above. thermal resistance characteristics (S-PBGA package) [ZLZ] NO. 1 RΘJC RΘJB Junction-to-case Junction-to-board N/A 9.95 9.95 RΘJA RΘJA Junction-to-free air 0.00 19.6 14.4 Junction-to-free air 0.5 17.3 11.5 Junction-to-free air 1.0 15.6 9.3 6 RΘJA RΘJA Junction-to-free air 2.00 14.7 8.0 7 PsiJT Junction-to-package top N/A 0.83 0.83 2 3 4 5 8 PsiJB Junction-to-board N/A 7.88 7.88 † m/s = meters per second ‡ Numbers are based on simulations. § These thermal resistance numbers were modeled using a heat sink, part number 374024B00035, manufactured by AAVID Thermalloy. AAVID Thermalloy also manufactures a similar epoxy-mounted heat sink, part number 374024B00000. When operating at 1 GHz, a heat sink is required to reduce the thermal resistance characteristics of the package. TI recommends a passive, laminar heat sink, similar to the part numbers mentioned above. 134 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 


 

 


   SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 thermal resistance characteristics (S-PBGA package) [CLZ] NO. 1 Air Flow (m/s†) °C/W‡ °C/W (with Heat Sink§) N/A 3.11 3.11 RΘJC RΘJB Junction-to-case Junction-to-board N/A 9.95 9.95 RΘJA RΘJA Junction-to-free air 0.00 19.6 14.4 Junction-to-free air 0.5 17.3 11.5 RΘJA RΘJA Junction-to-free air 1.0 15.6 9.3 6 Junction-to-free air 2.00 14.7 8.0 7 PsiJT Junction-to-package top N/A 0.83 0.83 2 3 4 5 8 PsiJB Junction-to-board N/A 7.88 7.88 † m/s = meters per second ‡ Numbers are based on simulations. § These thermal resistance numbers were modeled using a heat sink, part number 374024B00035, manufactured by AAVID Thermalloy. AAVID Thermalloy also manufactures a similar epoxy-mounted heat sink, part number 374024B00000. When operating at 1 GHz, a heat sink is required to reduce the thermal resistance characteristics of the package. TI recommends a passive, laminar heat sink, similar to the part numbers mentioned above. packaging information The following addendum table (device orderables) and packaging information reflect the most current released data available for the TMS320C6414/TMS320C6415T/TMS320C6416T device(s) — GLZ, ZLZ and CLZ. This data is subject to change without notice and without revision of this document. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 135 PACKAGE OPTION ADDENDUM www.ti.com 13-May-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) TMS320C6414TBCLZ1 ACTIVE FCBGA CLZ 532 60 RoHS & Green SNAGCU Level-4-260C-72 HR 0 to 90 TMS320C6414TCLZ @2003 TI 1GHZ 3 TMS320C6414TBCLZ6 ACTIVE FCBGA CLZ 532 60 RoHS & Green SNAGCU Level-4-260C-72 HR 0 to 90 TMS320C6414TCLZ @2003 TI 6 4 TMS320C6414TBCLZ7 ACTIVE FCBGA CLZ 532 60 RoHS & Green SNAGCU Level-4-260C-72 HR 0 to 90 TMS320C6414TCLZ @2003 TI 5 TMS320C6414TBCLZ8 ACTIVE FCBGA CLZ 532 60 RoHS & Green SNAGCU Level-4-260C-72 HR 0 to 90 TMS320C6414TCLZ @2003 TI 8 4 TMS320C6414TBCLZA6 ACTIVE FCBGA CLZ 532 60 RoHS & Green SNAGCU Level-4-260C-72 HR -40 to 105 TMS320C6414TCLZ @2003 TI A6 4 TMS320C6414TBGLZ1 ACTIVE FCBGA GLZ 532 60 Non-RoHS & Green Call TI Level-4-220C-72 HR 0 to 90 TMS320C6414TGLZ @2003 TI 1GHZ 3 TMS320C6414TBGLZ6 ACTIVE FCBGA GLZ 532 60 Non-RoHS & Green Call TI Level-4-220C-72 HR 0 to 90 TMS320C6414TGLZ @2003 TI 6 4 TMS320C6414TBGLZ7 ACTIVE FCBGA GLZ 532 60 Non-RoHS & Green SNPB Level-4-220C-72 HR 0 to 90 TMS320C6414TGLZ @2003 TI 5 TMS320C6414TBGLZA6 ACTIVE FCBGA GLZ 532 60 Non-RoHS & Green SNPB Level-4-220C-72 HR -40 to 105 TMS320C6414TGLZ @2003 TI A6 4 TMS320C6414TBGLZA7 ACTIVE FCBGA GLZ 532 60 Non-RoHS & Green SNPB Level-4-220C-72 HR -40 to 105 TMS320C6414TGLZ @2003 TI Addendum-Page 1 Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 13-May-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) A7 5 TMS320C6414TBGLZA8 ACTIVE FCBGA GLZ 532 60 Non-RoHS & Green SNPB Level-4-220C-72 HR -40 to 105 TMS320C6414TGLZ @2003 TI GLZ A8 4 TMS320C6415TBCLZ1 ACTIVE FCBGA CLZ 532 60 RoHS & Green Call TI Level-4-260C-72 HR 0 to 90 TMS320C6415TCLZ @2003 TI 1GHZ 3 TMS320C6415TBCLZ6 ACTIVE FCBGA CLZ 532 60 RoHS & Green SNAGCU Level-4-260C-72 HR 0 to 90 TMS320C6415TCLZ @2003 TI 6 4 TMS320C6415TBCLZ7 ACTIVE FCBGA CLZ 532 60 RoHS & Green SNAGCU Level-4-260C-72 HR 0 to 90 TMS320C6415TCLZ @2003 TI 5 TMS320C6415TBGLZ1 ACTIVE FCBGA GLZ 532 60 Non-RoHS & Green Call TI Level-4-220C-72 HR 0 to 90 TMS320C6415TGLZ @2003 TI 1GHZ 3 TMS320C6415TBGLZ6 ACTIVE FCBGA GLZ 532 60 Non-RoHS & Green Call TI Level-4-220C-72 HR 0 to 90 TMS320C6415TGLZ @2003 TI 6 4 TMS320C6415TBGLZ7 NRND FCBGA GLZ 532 60 Non-RoHS & Green Call TI Level-4-220C-72 HR 0 to 90 TMS320C6415TGLZ @2003 TI 5 TMS320C6415TBGLZA8 ACTIVE FCBGA GLZ 532 60 Non-RoHS & Green SNPB Level-4-220C-72 HR -40 to 105 TMS320C6415TGLZ @2003 TI A8 4 TMS320C6416TBCLZ1 ACTIVE FCBGA CLZ 532 60 RoHS & Green SNAGCU Level-4-260C-72 HR 0 to 90 TMS320C6416TCLZ @2003 TI 1GHZ 3 Addendum-Page 2 Samples Samples Samples Samples Samples Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 13-May-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) TMS320C6416TBCLZ7 ACTIVE FCBGA CLZ 532 60 RoHS & Green SNAGCU Level-4-260C-72 HR 0 to 90 TMS320C6416TCLZ @2003 TI 5 TMS320C6416TBCLZA6 ACTIVE FCBGA CLZ 532 60 RoHS & Green SNAGCU Level-4-260C-72 HR -40 to 105 TMS320C6416TCLZ @2003 TI A6 4 TMS320C6416TBCLZA7 ACTIVE FCBGA CLZ 532 60 RoHS & Green SNAGCU Level-4-260C-72 HR -40 to 105 TMS320C6416TCLZ @2003 TI A7 5 TMS320C6416TBCLZD1 ACTIVE FCBGA CLZ 532 60 RoHS & Green SNAGCU Level-4-260C-72 HR -40 to 90 TMS320C6416TCLZ @2003 TI D1GHZ 3 TMS320C6416TBGLZ1 ACTIVE FCBGA GLZ 532 60 Non-RoHS & Green Call TI Level-4-220C-72 HR 0 to 90 TMS320C6416TGLZ @2003 TI 1GHZ 3 TMS320C6416TBGLZ6 NRND FCBGA GLZ 532 60 Non-RoHS & Green Call TI Level-4-220C-72 HR 0 to 90 TMS320C6416TGLZ @2003 TI 6 4 TMS320C6416TBGLZ7 ACTIVE FCBGA GLZ 532 60 Non-RoHS & Green Call TI Level-4-220C-72 HR 0 to 90 TMS320C6416TGLZ @2003 TI 5 TMS320C6416TBGLZA6 ACTIVE FCBGA GLZ 532 60 Non-RoHS & Green SNPB Level-4-220C-72 HR -40 to 105 TMS320C6416TGLZ @2003 TI A6 4 TMS320C6416TBGLZA8 ACTIVE FCBGA GLZ 532 60 Non-RoHS & Green Call TI Level-4-220C-72 HR -40 to 105 TMS320C6416TGLZ @2003 TI A8 4 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 3 Samples Samples Samples Samples Samples Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com 13-May-2022 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of