TMS320DM365ZCED30

TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com TMS320DM365 Digital Media System-on-Chip (DMSoC) Check for Samples: TMS320DM365 1 TMS320DM365 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 • Highlights – High-Performance Digital Media System-on-Chip (DMSoC) – Up to 300-MHz ARM926EJ-S Clock Rate – Two Video Image Co-processors (HDVICP, MJCP) Engines – Supports a Range of Encode, Decode, and Video Quality Operations – Video Processing Subsystem • HW Face Detect Engine • Resize Engine from 1/16x to 8x • 16-Bit Parallel AFE (Analog Front-End) Interface Up to 120 MHz • 4:2:2 (8-/16-bit) Interface • 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output • 3 DACs for HD Analog Video Output • Hardware On-Screen Display (OSD) – Capable of 720p 30fps H.264 video processing Note: 216-MHz is only capable of D1 processing – Peripherals include EMAC, USB 2.0 OTG, DDR2/NAND, 5 SPIs, 2 UARTs, 2 MMC/SD/SDIO, Key Scan – 8 Different Boot Modes and Configurable Power-Saving Modes – Pin-to-pin and software compatible with DM368 – Extended temperature (-40ºC – 85ºC) available for 300-MHz device – 3.3-V and 1.8-V I/O, 1.2-V/1.35-V Core – 338-Pin Ball Grid Array at 65nm Process Technology • High-Performance Digital Media System-on-Chip (DMSoC) – 216-, 270-, 300-MHz ARM926EJ-S Clock Rate – Fully Software-Compatible With ARM9™ – Extended temperature available for 300-MHz device • ARM926EJ-S™ Core – Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets – DSP Instruction Extensions and Single Cycle MAC – ARM® Jazelle® Technology – Embedded ICE-RT Logic for Real-Time Debug • ARM9 Memory Architecture – 16K-Byte Instruction Cache – 8K-Byte Data Cache – 32K-Byte RAM – 16K-Byte ROM – Little Endian • Two Video Image Co-processors (HDVICP, MJCP) Engines – Support a Range of Encode and Decode Operations, up to D1 on 216-MHz device and up to 720p on the 270- and 300-MHz parts – H.264, MPEG4, MPEG2, MJPEG, JPEG, WMV9/VC1 • Video Processing Subsystem – Front End Provides: • HW Face Detect Engine • Hardware IPIPE for Real-Time Image Processing – Resize Engine – Resize Images From 1/16x to 8x – Separate Horizontal/Vertical Control – Two Simultaneous Output Paths • IPIPE Interface (IPIPEIF) • Image Sensor Interface (ISIF) and CMOS Imager Interface • 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz • Glueless Interface to Common Video Decoders • BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8-/16-Bit) Interface • Histogram Module • Lens distortion correction module (LDC) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2011, Texas Instruments Incorporated TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 • • • • • • • • • • • 2 Hardware 3A statistics collection module (H3A) – Back End Provides: • Hardware On-Screen Display (OSD) • Composite NTSC/PAL video encoder output • 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output • 3 DACs for HD Analog Video Output • LCD Controller • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface Analog-to-Digital Convertor (ADC) Power Management and Real Time Clock Subsystem (PRTCSS) – Real Time Clock 16-Bit Host-Port Interface (HPI) 10/100 Mb/s Ethernet Media Access Controller (EMAC) - Digital Media – IEEE 802.3 Compliant – Supports Media Independent Interface (MII) – Management Data I/O (MDIO) Module Key Scan Voice Codec External Memory Interfaces (EMIFs) – DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O) – Asynchronous16-/8-bit Wide EMIF (AEMIF) • Flash Memory Interfaces – NAND (8-/16-bit Wide Data) – 16 MB NOR Flash, SRAM – OneNAND(16-bit Wide Data) Flash Card Interfaces – Two Multimedia Card (MMC) / Secure Digital (SD/SDIO) – SmartMedia/xD Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) USB Port with Integrated 2.0 High-Speed PHY that Supports – USB 2.0 High-Speed Device – USB 2.0 High-Speed Host (mini-host, supporting one external device) – USB On The Go (HS-USB OTG) www.ti.com • Four 64-Bit General-Purpose Timers (each configurable as two 32-bit timers) • One 64-Bit Watch Dog Timer • Two UARTs (One fast UART with RTS and CTS Flow Control) • Five Serial Port Interfaces (SPI) each with two Chip-Selects • One Master/Slave Inter-Integrated Circuit (I2C) Bus™ • One Multi-Channel Buffered Serial Port (McBSP) – I2S – AC97 Audio Codec Interface – S/PDIF via Software – Standard Voice Codec Interface (AIC12) – SPI Protocol (Master Mode Only) – Direct Interface to T1/E1 Framers – Time Division Multiplexed Mode (TDM) – 128 Channel Mode • Four Pulse Width Modulator (PWM) Outputs • Four RTO (Real Time Out) Outputs • Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions) • Boot Modes – On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI – AEMIF (NOR and OneNAND) • Configurable Power-Saving Modes • Crystal or External Clock Input (typically 19.2 MHz, 24 MHz, 27 MHz or 36 MHz) • Flexible PLL Clock Generators • Debug Interface Support – IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible – ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory – Device Revision ID Readable by ARM • 338-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch • 65nm Process Technology • 3.3-V and 1.8-V I/O, 1.2-V/ 1.35-V Internal • Community Resources – TI E2E Community – TI Embedded Processors Wiki TMS320DM365 Digital Media System-on-Chip (DMSoC) Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 www.ti.com 1.2 SPRS457E – MARCH 2009 – REVISED JUNE 2011 Description Developers can now deliver pixel-perfect images at up to 720p H.264 at 30fps in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM365 digital media processor based on DaVinci technology from Texas Instruments Incorporated (TI). With multi-format HD video, the DM365 also features a suite of peripherals saving developers on system costs. This ARM9-based DM365 device offers speeds up to 300 MHz and supports production-qualified H.264, MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providing customers with the flexibility to select the right video codec for their application. These codecs are driven from video accelerators offloading compression needs from the ARM core so that developers can utilize the most performance from the ARM for their application. Video surveillance designers achieve greater compression efficiency providing more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players and more can ensure interoperability as well as product scalability by taking advantage of the full suite of codecs supported on the DM365. Along with multi-format HD video, the DM365 enables seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.656, BT1120. The DM365 also offers a high level of integration with HD display support including, 3 built-in 10-bit HD Analog Video Digital to Analog Converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, Host Port Interface (HPI), Analog to Digital Converter, and many more features saving developers on overall system costs as well as real estate on their circuit boards allowing for a slimmer, sleeker design. Copyright © 2009–2011, Texas Instruments Incorporated TMS320DM365 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback Product Folder Link(s): TMS320DM365 3 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 1.3 www.ti.com Functional Block Diagram Figure 1-1 shows the functional block diagram of the TMS320DM365 device. 16 Bit ISIF IPIPE Resizer 3A Face Det Lens Dist Video FE SDTV/HDTV Analog Video 3Ch DAC EDMA Buffer Camera AFE NAND/SM Memory I/F Video OSD Encoder Digital RGB/YUV DDR2 Controller 16 Bit HPI Video BE VPSS 8/16 Bit 16-Bit DDR2/ mDDR NAND/ OneNAND/ NOR Flash, SmartMedia/ xD Host CPU DMA/Data and Configuration Bus ARM INTC HDVICP MJCP ARM926EJ-S I-Cache RAM 16 KB 32 KB D-Cache ROM 8 KB 16 KB JTAG I/F CLOCK Ctrl PLL PRTCSS 19.2 MHz, 24 MHz 32.768 27 MHz or 36 MHz kHz USB2.0 HS w/OTG MMC/SD (x2) SPI (x5) UART (x2) I2C Timer (x4-64b) WDT (x1-64b) GIO PWM (x4) RTO McBSP EMAC ADC Key Scan Voice Codec System I/O Interface PMIC/ SW Figure 1-1. Functional Block Diagram 4 TMS320DM365 Digital Media System-on-Chip (DMSoC) Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 1 TMS320DM365 Digital Media System-on-Chip (DMSoC) ................................................... 1 1.1 6 6.1 Features .............................................. 1 ........................................... 3 1.3 Functional Block Diagram ............................ 4 Revision History (Revision E) ............................. 6 2 Device Overview ........................................ 7 2.1 Device Characteristics ............................... 7 2.2 Device Compatibility ................................. 8 2.3 ARM Subsystem Overview .......................... 8 2.4 System Control Module ............................. 12 2.5 Power Management ................................ 13 2.6 Memory Map Summary ............................. 14 2.7 Pin Assignments .................................... 16 2.8 Terminal Functions ................................. 21 2.9 Device Support ..................................... 46 3 Device Configurations ................................ 50 3.1 System Module Registers .......................... 50 3.2 Boot Modes ......................................... 51 3.3 Device Clocking .................................... 54 3.4 Power and Sleep Controller (PSC) ................. 62 3.5 Pin Multiplexing ..................................... 63 3.6 Device Reset ....................................... 64 3.7 Default Device Configurations ...................... 64 3.8 Debugging Considerations ......................... 69 4 System Interconnect .................................. 70 5 Device Operating Conditions ....................... 71 1.2 Description Recommended Operating Conditions .............. 72 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) ................................... 74 ...................................................... 76 Recommended Clock and Control Signal Transition Behavior ............................................ 77 6.3 Power Supplies 77 6.4 Power-Supply Sequencing 78 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) ................................. 71 7 Parameter Information Device-Specific Information 6.2 6.5 5.1 5.2 5.3 Peripheral Information and Electrical Specifications .......................................... 76 ..................................... ......................... Reset ............................................... Oscillators and Clocks .............................. 80 81 Power Management and Real Time Clock Subsystem (PRTCSS) .............................. 85 ............. 87 .................................... 89 External Memory Interface (EMIF) ................. 99 MMC/SD ........................................... 120 General-Purpose Input/Output (GPIO) EDMA Controller Video Processing Subsystem (VPSS) Overview ..................................................... 123 USB 2.0 ........................................... 149 Universal Asynchronous Receiver/Transmitter (UART) ............................................ 157 ......................... ...................... 6.17 Multi-Channel Buffered Serial Port (McBSP) ..... 6.18 Timer .............................................. 6.19 Pulse Width Modulator (PWM) .................... 6.20 Real Time Out (RTO) ............................. 6.21 Ethernet Media Access Controller (EMAC) ....... 6.22 Management Data Input/Output (MDIO) .......... 6.23 Host-Port Interface (HPI) Peripheral .............. 6.24 Key Scan .......................................... 6.25 Analog-to-Digital Converter (ADC) ................ 6.26 Voice Codec ....................................... 6.27 IEEE 1149.1 JTAG ................................ Mechanical Data ...................................... 7.1 Thermal Data for ZCE ............................. 7.2 Packaging Information ............................ 6.15 Serial Port Interface (SPI) 159 6.16 Inter-Integrated Circuit (I2C) 169 Contents Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 172 181 183 185 187 193 195 199 201 201 203 206 206 206 5 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. highlights the technical changes made to the SPRS457D device-specific data sheet to make it an SPRS457E revision. Revision E Updates See Global Removed sentence stating "micro-vias are not required." Figure 2-2 Corrected J5 pin name. Table 2-5 Changed TYPE of VREF pin from A I/O to A I. Table 2-5 Changed TYPE of VCOM pin from AI to AO. Section 3.2.1 6 Additions/Changes/Deletions Added 24 MHz reference clock to ARM ROM Boot - UART mode. Table 6-21 Updated first table note. Table 6-22 Updated second table note. Table 6-26 Updated table and added table note. Contents Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 2 Device Overview 2.1 Device Characteristics Table 2-1 provides an overview of the DMSoC. The table shows significant features of the device, including the peripherals, capacity of on-chip RAM, ARM operating frequency, the package type with pin count, etc. Table 2-1. Characteristics of the Processor HARDWARE FEATURES DDR2 / mDDR Memory Controller Asynchronous EMIF (AEMIF) Flash Card Interfaces Peripherals DEVICE DDR2 / mDDR (16-bit bus width) Asynchronous (8/16-bit bus width) RAM, Flash (NOR, NAND, OneNAND) Two MMC/SD One SmartMedia/xD EDMA 64 independent DMA channels Eight QDMA channels Timers Four 64-Bit General Purpose (each configurable as two separate 32-bit timers) One 64-Bit Watch Dog UART Two (one with RTS and CTS flow control) SPI Five (each supports two slave devices) I2C One (Master/Slave) Not all peripherals pins are 10/100 Ethernet MAC with Management Data I/O available at the same time (For Multi-Channel Buffered Serial Port [McBSP] more detail, see the Device Configuration section). Power Management and Real Time Clock Subsystem (PRTCSS) Key Scan One One McBSP RTC (32.768kHz), GPIO 4 x 4 Matrix, 5 x 3 Matrix Voice Codec One Analog-to-Digital Converter (ADC) General-Purpose Input/Output Port Pulse width modulator (PWM) Configurable Video Ports 6-channel, 10-bit Interface Up to 104 Four outputs One Input (VPFE) One Output (VPBE) High Speed Device High Speed Host On The Go (HS-USB-OTG) USB 2.0 Wireless Interfaces Through SDIO RTO Four Channels ARM 16-KB I-cache, 8-KB D-cache, 32-KB RAM, 16-KB ROM On-Chip CPU Memory Organization JTAG BSDL_ID JTAGID register (address location: 0x01C4 0028) See Section 6.27.1, JTAG Register Description(s) CPU Frequency (Maximum) MHz ARM: 216-MHz, 270-MHz, 300-MHz Voltage Core (V) 1.2 V or 1.35 V I/O (V) 3.3 V, 1.8 V PLL Options Reference frequency options Configurable PLL controller BGA Package 13 x 13 mm 19.2 MHz, 24 MHz, 27 MHz, 36 MHz PLL bypass, programmable PLL 338-Pin BGA (ZCE) Process Technology 65 nm Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 7 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-1. Characteristics of the Processor (continued) Product Status (1) (1) HARDWARE FEATURES DEVICE Product Preview (PP), Advance Information (AI), or Production Data (PD) PD PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 2.2 Device Compatibility The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc. 2.3 ARM Subsystem Overview The ARM Subsystem contains components required to provide the ARM926EJ-S (ARM) master control of the overall device system, including the components of the ARM Subsystem, the peripherals, and the external memories. The ARM is responsible for handling system functions such as system-level initialization, configuration, user interface, user command execution, connectivity functions, interface and control of the subsystem, etc. The ARM is master and performs these functions because it has a large program memory space and fast context switching capability, and is thus suitable for complex, multi-tasking, and general-purpose control tasks. 2.3.1 Components of the ARM Subsystem The ARM Subsystem consists of the following components: • ARM926EJ-S RISC processor, including: – coprocessor 15 (CP15) – MMU – 16KB Instruction cache – 8KB Data cache – Write Buffer – Java accelerator • ARM Internal Memories – 32KB Internal RAM (32-bit wide access) – 16KB Internal ROM (ARM bootloader for non-AEMIF boot modes) • Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) • System Control Peripherals – ARM Interrupt Controller – PLL Controller – Power and Sleep Controller – System Control Module The ARM also manages/controls all the device peripherals. Figure 2-1 shows the functional block diagram of the ARM Subsystem. 8 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Master IF ARM Interrupt Controller (AINTC) Master IF Arbiter Arbiter I-AHB D-AHB System Control I-TCM D-TCM Slave Arbiter 16K I$ CP15 8K D$ MMU 16K ROM 16K RAM1 PLLC2 IF 16K RAM0 CFG Bus DMA Bus ARM926EJ-S PLLC1 Power Sleep Controller (PSC) Peripherals ... Figure 2-1. ARM Subsystem Block Diagram 2.3.2 ARM926EJ-S RISC CPU The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including: • ARM926EJ -S integer core • CP15 system control coprocessor • Memory Management Unit (MMU) • Separate instruction and data Caches • Write buffer • Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces • Separate instruction and data AHB bus interfaces • Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available at http://www.arm.com Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 9 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 2.3.3 www.ti.com CP15 The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as supervisor or system mode. 2.3.4 MMU The ARM926EJ-S MMU provides virtual memory features required by operating systems such as Linux, WindowCE, ultron, ThreadX, etc. A single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The MMU features are: • Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme. • Mapping sizes are: – 1MB (sections) – 64KB (large pages) – 4KB (small pages) – 1KB (tiny pages) • Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions) • Hardware page table walks • Invalidate entire TLB, using CP15 register 8 • Invalidate TLB entry, selected by MVA, using CP15 register 8 • Lockdown of TLB entries, using CP15 register 10 2.3.5 Caches and Write Buffer The size of the Instruction Cache is 16KB, Data cache is 8KB. Additionally, the Caches have the following features: • Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA) • Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with two dirty bits in the Dcache • Dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the C and B bits in the MMU translation tables. • Critical-word first cache refilling • Cache lockdown registers enable control over which cache ways are used for allocation on a line fill, providing a mechanism for both lockdown, and controlling cache corruption • Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the possibility of TLB misses related to the write-back address. • Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of the Dcache or Icache, and regions of virtual memory. The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a four-address buffer. The Dcache write-back has eight data word entries and a single address entry. 2.3.6 Tightly Coupled Memory (TCM) ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt 10 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Vector table. ARM internal ROM boot modes include NAND, MMC/SD, UART, USB, SPI, EMAC, and HPI. The RAM and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface that provides for separate instruction and data bus connections. Since the ARM TCM does not allow instructions on the D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and instructions can be stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM from extra-ARM sources (e.g., EDMA or other masters). The ARM926EJ-S has built-in DMA support for direct accesses to the ARM internal memory from a non-ARM master. Because of the time-critical nature of the TCM link to the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers. Instruction and Data accesses are differentiated via accessing different memory map regions, with the instruction region from 0x0000 through 0x7FFF and data from 0x10000 through 0x17FFF. Placing the instruction region at 0x0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000, as required by the ARM architecture. The internal 32-KB RAM is split into two physical banks of 16KB each, which allows simultaneous instruction and data accesses to be accomplished if the code and data are in separate banks. 2.3.7 Advanced High-performance Bus (AHB) The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the configuration bus and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the configuration bus and the external memories bus. 2.3.8 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB) To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem also includes the Embedded Trace Buffer (ETB). The ETM consists of two parts: • Trace Port provides real-time trace capability for the ARM9. • Triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers. The device trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data. 2.3.9 ARM Memory Mapping The ARM memory map is shown in Table 2-3 and Table 2-4. This section describes the memories and interfaces within the ARM's memory map. 2.3.9.1 ARM Internal Memories The ARM has access to the following ARM internal memories: • 32KB ARM Internal RAM on TCM interface, logically separated into two 16KB pages to allow simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data (D-TCM) to the different memory regions. • 16KB ARM Internal ROM 2.3.9.2 External Memories The ARM has access to the following External memories: • DDR2 / mDDR Synchronous DRAM • Asynchronous EMIF / OneNAND / NOR • NAND Flash Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 11 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 • www.ti.com Flash card devices: – MMC/SD – xD – SmartMedia 2.3.10 Peripherals The ARM has access to all of the peripherals on the device. 2.3.11 ARM Interrupt Controller (AINTC) The device ARM Interrupt Controller (AINTC) has the following features: • Supports up to 64 interrupt channels (16 external channels) • Interrupt mask for each channel • Each interrupt channel can be mapped to a Fast Interrupt Request (FIQ) or to an Interrupt Request (IRQ) type of interrupt. • Hardware prioritization of simultaneous interrupts • Configurable interrupt priority (2 levels of FIQ and 6 levels of IRQ) • Configurable interrupt entry table (FIQ and IRQ priority table entry) to reduce interrupt processing time The ARM core supports two interrupt types: FIQ and IRQ. See the ARM926EJ-S Technical Reference Manual for detailed information about the ARM’s FIQ and IRQ interrupts. Each interrupt channel is mappable to an FIQ or to an IRQ type of interrupt, and each channel can be enabled or disabled. The INTC supports user-configurable interrupt-priority and interrupt entry addresses. Entry addresses minimize the time spent jumping to interrupt service routines (ISRs). When an interrupt occurs, the corresponding highest priority ISR’s address is stored in the INTC’s ENTRY register. The IRQ or FIQ interrupt routine can read the ENTRY register and jump to the corresponding ISR directly. Thus, the ARM does not require a software dispatcher to determine the asserted interrupt. 2.4 System Control Module The system control module is a system-level module containing status and top-level control logic required by the device. The system control module consists of a miscellaneous set of status and control registers, accessible by the ARM and supporting all of the following system features and operations: • Device identification • Device configuration – Pin multiplexing control – Device boot configuration status • ARM interrupt and EDMA event multiplexing control • Special peripheral status and control – Timer64 – USB PHY control – VPSS clock and video DAC control and status – DDR VTP control – Clockout circuitry – GIO de-bounce control • Power management – Deep sleep • Bandwidth Management – Bus master DMA priority control For more information on the System Control Module refer to Section 3, Device Configurations and the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5). 12 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 2.5 Power Management The device is designed for minimal power consumption. There are two components to power consumption: active power and leakage power. Active power is the power consumed to perform work and scales with clock frequency and the amount of computations being performed. Active power can be reduced by controlling the clocks in such a way as to either operate at a clock setting just high enough to complete the required operation in the required time-line or to run at a clock setting until the work is complete and then drastically cut the clocks (e.g. to PLL Bypass mode) until additional work must be performed. Leakage power is due to static current leakage and occurs regardless of the clock rate. Leakage, or standby power, is unavoidable while power is applied and scales roughly with the operating junction temperatures. Leakage power can only be avoided by removing power completely from a device or subsystem. The device includes several power management modes which are briefly described in Table 2-2. See the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5) for more information on power management. Table 2-2. Power Management Conditions POWER MGMT. APPLICATION SCENARIO PRTCSS Deep Sleep Mode (1) Standby Low-power (PLL Bypass Mode) System Running (PLL Mode) (1) PRTCSS CORE POWER OSC. POWER PLL CNTRLR. ARM926 CLOCK GIO, UART, I2C CLOCKS SPI, PWM, TIMER CLOCKS OTHER PERIPH. CLOCKS DDR CLOCK/ MODE DESCRIPTION Active Off Off Off Off Off Off Off Off This condition consumes the lowest possible power, except for the PRTCSS. Off Bypass Mode (not Active) Active Active Active Active On On On On On On On Bypass Mode Bypass Mode PLL Mode Off Off On On Off Off On On / Off On / Off Off On / Off On / Off Off This mode consumes the second lowest Suspend / possible power, except "Selffor PRTCSS and core Refresh" power, where only the deep sleep circuit is on in this mode. Off This condition keeps the minimum possible modules powered-on Suspend / in order to wake up the "Selfdevice. Clocks are Refresh" suspended except for GIO (interrupts), UART, and I2C (in slave mode). On / Off Most clocks are suspended, except for ARM, GIO, UART, SPI, I2C, PWM, and Suspend / timers. Since ARM will "Selfnot have access to Refresh" DDR, its internal Cache will be either frozen or not accessed. On / Off Nominal Clock / Operation The device, including system PLLs, are on. This condition conserves the least amount of power. For more details, see TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5) Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 13 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 2.6 www.ti.com Memory Map Summary Table 2-3 shows the memory map address ranges of the device. Table 2-4 depicts the expanded map of the Configuration Space (0x01C0 0000 through 0x01FF FFFF). The device has multiple on-chip memories associated with its processor and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters. The bus masters are the ARM, EDMA, EMAC, USB, HPI, MJCP, HDVICP and VPSS. The Master Peripherals are EMAC, USB, and HPI. Please refer to Section 4 for more details. Table 2-3. Memory Map 14 Start Address End Address Size (Bytes) ARM Mem Map EDMA Mem Map Master Periph Mem Map 0x0000 0000 0x0000 3FFF 16K ARM RAM0 (Instruction) 0x0000 4000 0x0000 7FFF 16K ARM RAM1 (Instruction) Reserved Reserved 0x0000 8000 0x0000 BFFF 16K ARM ROM (Instruction) 0x0000 C000 0x0000 FFFF 16K Reserved 0x0001 0000 0x0001 3FFF 16K ARM RAM0 (Data) ARM RAM0 ARM RAM0 0x0001 4000 0x0001 7FFF 0x0001 8000 0x0001 BFFF 16K ARM RAM1 (Data) ARM RAM1 ARM RAM1 16K ARM ROM ARM ROM 0x0001 C000 ARM ROM 0x000F FFFF 912K Reserved 0x0010 0000 0x01BB FFFF 26M 0x01BC 0000 0x01BC 0FFF 4K 0x01BC 1000 0x01BC 17FF 2K ARM ETB Reg 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher 0x01BC 1900 0x01BC FFFF 59136 Reserved 0x01BD 0000 0x01BF FFFF 192K 0x01C0 0000 0x01FF FFFF 4M VPSS Mem Map ARM ETB Mem CFG Bus Peripherals Reserved Reserved CFG Bus Peripherals 0x0200 0000 0x09FF FFFF 128M 0x0A00 0000 0x11EF FFFF 127M - 16K Reserved Reserved 0x11F0 0000 0x11F1 FFFF 128K MJCP DMA Port MJCP DMA Port 0x11F2 0000 0x11FF FFFF 896K Reserved Reserved 0x1200 0000 0x1207 FFFF 512K HDVICP DMA Port1 HDVICP DMA Port1 0x1208 0000 0x120F FFFF 512K Reserved HDVICP DMA Port2 0x1210 0000 0x1217 FFFF 512K 0x1218 0000 0x1FFF FFFF 222.5M 0x2000 0000 0x2000 7FFF 32K 0x2000 8000 0x41FF FFFF 544M-32K 0x4200 0000 0x49FF FFFF 128M 0x4A00 0000 0x7FFF FFFF 864M 0x8000 0000 0x8FFF FFFF 0x9000 0000 0xFFFF FFFF CFG Bus Peripherals ASYNC EMIF (Data) ASYNC EMIF (Data) HDVICP DMA Port1 Reserved HDVICP DMA Port3 Reserved DDR EMIF Control Regs DDR EMIF Control Regs Reserved Reserved 256M DDR EMIF DDR EMIF DDR EMIF DDR EMIF 1792M Reserved Reserved Reserved Reserved Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-4. ARM Configuration Bus Access to Peripherals Address Region Start End Size EDMA CC 0x01C0 0000 0x01C0 FFFF 64K EDMA TC0 0x01C1 0000 0x01C1 03FF 1K EDMA TC1 0x01C1 0400 0x01C1 07FF 1K EDMA TC2 0x01C1 0800 0x01C1 0BFF 1K EDMA TC3 0x01C1 0C00 0x01C1 0FFF 1K Reserved 0x01C1 1000 0x01C1 FFFF 60 K UART0 0x01C2 0000 0x01C2 03FF 1K Reserved 0x01C2 0400 0x01 20 7FFF 1K Timer 3 0x01C2 0800 0x01C2 0BFF 1K Real-time out 0x01C2 0C00 0x01C2 0FFF 1K I2C 0x01C2 1000 0x01C2 13FF 1K Timer 0 0x01C2 1400 0x01C2 17FF 1K Timer 1 0x01C2 1800 0x01C2 1BFF 1K Timer 2 0x01C2 1C00 0x01C2 1FFF 1K PWM0 0x01C2 2000 0x01C2 23FF 1K PWM1 0x01C2 2400 0x01C2 27FF 1K PWM2 0x01C2 2800 0x01C2 2BFF 1K PWM3 0x01C2 2C00 0x01C2 2FFF 1K SPI4 0x01C2 3000 0x01C2 37FF 2K Timer 4 0x01C2 3800 0x01C2 3BFF 1K ADCIF 0x01C2 3C00 0x01C2 3FFF 1K Reserved 0x01C2 4000 0x01C3 4FFF 112K System Module 0x01C4 0000 0x01C4 07FF 2K PLL Controller 1 0x01C4 0800 0x01C4 0BFF 1K PLL Controller 2 0x01C4 0C00 0x01C4 0FFF 1K Power/Sleep Controller 0x01C4 1000 0x01C4 1FFF 4K Reserved 0x01C4 2000 0x01C4 7FFF 24K ARM Interrupt Controller 0x01C4 8000 0x01C4 83FF 1K Reserved 0x01 C4 8400 0x01C63FFF 111K USB OTG 2.0 Regs / RAM 0x01C6 4000 0x01C6 5FFF 8K SPI0 0x01C6 6000 0x01C6 67FF 2K SPI1 0x01C6 6800 0x01C6 6FFF 2K GPIO 0x01C6 7000 0x01C6 77FF 2K SPI2 0x01C6 7800 0x01C6 FFFF 2K SPI3 0x01C6 8000 0x01C6 87FF 2K Reserved 0x01C6 8800 0x01C6 87FF 2K PRTCSS Interface Registers 0x01C6 9000 0x01C6 93FF 1K KEYSCAN 0x01C6 9400 0x01C6 97FF 1K HPI 0x01C6 9800 0x01C6 9FFF 2K Reserved 0x01C6 A000 0x01C6 FFFF 24K ISP System Configuration Registers 0x01C7 0000 0x01C7 00FF 256 VPBE Clock Control Register 0x01C7 0200 0x01C7 02FF 256 Resizer Registers 0x01C7 0400 0x01C7 07FF 1K IPIPE Registers 0x01C7 0800 0x01C7 0FFF 2K ISIF Registers 0x01C7 1000 0x01C7 11FF 512 VPSS Subsystem Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 15 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-4. ARM Configuration Bus Access to Peripherals (continued) Address IPIPEIF Registers 0x01C7 1200 0x01C7 12FF 768 H3A Registers 0x01C7 1400 0x01C7 14FF 256 Reserved 0x01C7 1600 0x01C7 17FF 512 FDIF Registers 0x01C7 1800 0x01C7 1BFF 1K OSD Registers 0x01C7 1C00 0x01C7 1CFF 256 Reserved 0x01C7 1D00 0x01C7 1DFF 256 VENC Registers 0x01C7 1E00 0x01C7 1FFF 512 Reserved 0x01C7 2000 0x01CF FFFF 568K Multimedia / SD 1 0x01D0 0000 0x01D0 1FFF 8K McBSP 0x01D0 2000 0x01D0 3FFF 8K Reserved 0x01D0 4000 0x01D0 5FFF 8K 1K UART1 0x01D0 6000 0x01D0 63FF Reserved 0x01D0 6400 0x01D0 7FFF 3K EMAC Control Registers 0x01D0 7000 0x01D0 9FFF 0x01D0 4K 7FFF EMAC Control Module RAM 0x01D0 8000 EMAC Control Module Registers 0x01D0 A000 0x01D0 AFFF 4K EMAC MDIO Control Registers 0x01D0 B000 0x01D0 B7FF 2K Voice Codec 0x01D0 C000 0x01D0 C3FF 1K Reserved 0x01D0 C400 0x01D0 FFFF 17K ASYNC EMIF Control 0x01D1 0000 0x01D1 0FFF 4K Multimedia / SD 0 0x01D1 1000 0x01D1 FFFF 60K Reserved 0x01D2 0000 0x01D3 FFFF 128K Reserved 0x01D4 0000 0x01DF FFFF 768K Reserved 0x01E0 0000 0x01FF FFFF 2M ASYNC EMIF Data (CE0) 0x0200 0000 0x03FF FFFF 32M ASYNC EMIF Data (CE1) 0x0400 0000 0x05FF FFFF 32M Reserved 0x0600 0000 0x09FF FFFF 64M Reserved 0x0A00 0000 0x0FFF FFFF 96M 2.7 8K Pin Assignments Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. 2.7.1 Pin Map (Bottom View) Figure 2-2 through Figure 2-5 show the pin assignments in four quadrants (A, B, C, and D). 16 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com B C A D (1) VDD12_ VDDS18 CVDD VSS VDDS33 CVDD CVDD VSS EMU0 CVDD N.B. CVDD VDDA18_ADC TCK TDI VDDS33 VDDS33 VSSA_ADC VSSA18_VC GIO19 GIO17 VDD18_SLDO GPIO46 GIO44 ADC_CH0 VDDA18_VC GIO15 GIO13 VDDRAM GIO49 GIO1 ADC_CH4 ADC_CH3 VSSA33_VC GIO12 GIO9 N.B. GIO2 GIO3 GIO47 N.B. MICIN LINEO B GIO11 GIO10 GIO6 GIO5 GIO0 GPIO45 ADC_CH1 MICIP SPP A RSV0 GIO8 GIO7 GIO4 GIO48 ADC_CH5 ADC_CH2 VCOM SPN 1 2 3 4 5 6 7 8 9 J PWCTRIO2 PWCTRIO1 PECTRIO0 PWCTRIO4 PWCTRIO3 H RTCXO VSS_32K RESET EMU1 TRST G RTCXI TMS N.B. TDO F GIO20 RTCK GIO21 E GIO16 GIO18 D GIO14 C PRTCSS N.B stands for No-Ball. Figure 2-2. ZCE Pin Map [Quadrant A] Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 17 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 1 2 3 4 5 6 7 8 9 W VSS GIO32 GIO35 GIO36 GIO41 DDR_ DQM1 DDR_ DQ12 DDR_ DQ8 DDR_ DQ6 V GIO28 GIO23 GIO33 GIO34 GIO38 DDR_ DQ15 DDR_ DQ14 DDR_ DQ11 DDR_ DQ5 U GIO26 GIO29 N.B. GIO31 GIO40 DDR_ DQSN1 N.B. DDR_DQ9 DDR_ DQSN0 T GIO25 GIO27 GIO24 GIO30 GIO37 GIO43 DDR_DQS1 DDR_ DQGATE0 DDR_ DQGATE1 R RSV1 GIO22 VPP RSV2 GIO39 GIO42 DDR_DQ13 DDR_DQ10 DDR_DQ7 P USB_DM VSSA18_USB VSSA33_USB VDDA33_USB VDDS33 VDDS33 VDDS18 VSS VDD18_DDR N USB_DP USB_VBUS N.B. VDDA18_PLL VDD18_USB VDDS33 N.B. VSS VDD18_DDR M USB_ID PWRCNTON PWRST VSSA VDDA12LDO_ USB CVDD VSS VSS VSS L MXI1 VSS_MX1 PWCTRO3 PWCTRO2 PWCTRO1 VDDMXI VSS VSS VSS K MXO1 PWCTRO0 N.B. PWCTRIO6 PWCTRIO5 CVDD VSS VDD18_PRTCSS VDD12_PRTCSS B C A D (1) N.B stands for No-Ball. Figure 2-3. ZCE Pin Map [Quadrant B] 18 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 10 11 12 13 14 15 16 17 18 19 DDR_DQ4 DDR_CLK DDR_CLK DDR_WE DDR_BA0 DDR_A2 DDR_A6 DDR_A8 DDR_A11 VSS W DDR_DQ3 DDR_DQ1 DDR_CAS DDR_BA2 DDR_A1 DDR_A5 DDR_A10 DDR_A12 EM_A13 EM_A11 V N.B. DDR_DQ0 DDR_RAS N.B. DDR_A0 DDR_A4 DDR_A9 N.B. EM_A12 EM_A10 U DDR_DQS0 DDR_DQM0 DDR_CS DDR_BA1 DDR_A3 DDR_A7 DDR_A13 EM_A7 EM_A9 EM_A8 T DDR_DQ2 DDR_ PADREFP VDD18_DDR DDR_CKE VDD_ EM_A3 EM_A5 EM_BA1 EM_A6 EM_A4 R VDD18_DDR DDR_VREF VDD18_DDR VSS EM_D12 EM_D14 EM_BA0 EM_D15 EM_D13 P N.B. VDD18_DDR VSS N.B. VSS EM_D8 EM_D11 N.B. EM_D10 EM_D9 N CVDD VSS CVDD CVDD VDDS18 EM_CLK EM_ADV EM_CE[0] EM_A2 EM_A1 M VSS VSS VDDS33 CVDD EM_D4 EM_D7 EM_A0 EM_D6 EM_D5 L VSS VSS CVDD N.B. EM_D3 EM_D1 N.B. EM_D0 EM_D2 K AEMIF1_18_33 VDD_ AEMIF1_18_33 VDD_ AEMIF2_18_33 VDD_ AEMIF2_18_33 B C A D (1) N.B stands for No-Ball. Figure 2-4. ZCE Pin Map [Quadrant C] Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 19 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com B C A D (1) VSS VSS CVDD VSS CVDD EM_WE MMCSD0_CLK EM_CE[1] EM_WAIT EM_OE J VSS VDDS18 CVDD VDDS33 VDDS18 MMCSD0_ CMD MMCSD0_ DATA3 MMCSD0_ DATA2 MMCSD0_ DATA0 MMCSD0_ DATA1 H N.B. VSS VSS N.B. VDDS18 HSYNC YOUT7 N.B. VSYNC YOUT6 G VDDS33 VSSA12_DAC VDD_ISIF18_33 VDD_ISIF18_33 VSS YOUT5 YOUT3 YOUT1 YOUT4 YOUT2 F VDDA33_VC VSSA18_ DAC VDDA12_DAC C_WE_ FIELD VSS COUT5 YOUT0 COUT4 COUT7 COUT6 E VDDA18_DAC VREF YIN4 PCLK YIN1 YIN0 COUT3 COUT0 COUT1 COUT2 D N.B. COMPPR YIN7 N.B. HD CIN6 CIN2 N.B. FIELD LCD_OE C VFB IDACOUT COMPY YIN5 VD YIN2 CIN5 CIN0 VCLK EXTCLK B TVOUT IREF COMPPB YIN6 YIN3 CIN7 CIN4 CIN3 CIN1 VSS A 10 11 12 13 14 15 16 17 18 19 N.B stands for No-Ball. Figure 2-5. ZCE Pin Map [Quadrant D] 20 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 2.8 Terminal Functions Table 2-5 provides a complete pin description list which shows external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see Section 3. Table 2-5. Pin Descriptions Name CIN7 (5) BGA ID Type A15 I/O (1) Group ISIF Power Supply (2) IPU IPD (3) Reset State VDD_ISIF18_33 IPD Input Description (4) Standard ISIF Analog Front End (AFE): raw[7] YCC 16-bit: time multiplexed between chroma: CB/CR[07] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[07] CIN6 (5) C15 I/O ISIF VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[6] YCC 16-bit: time multiplexed between chroma: CB/CR[06] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[06] CIN5 (5) B16 I/O ISIF VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[5] YCC 16-bit: time multiplexed between chroma: CB/CR[05] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[05] CIN4 (5) A16 I/O ISIF VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[4] YCC 16-bit: time multiplexed between chroma: CB/CR[04] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[04] CIN3 (5) A17 I/O ISIF VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[3] YCC 16-bit: time multiplexed between chroma: CB/CR[03] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[03] CIN2 (5) C16 I/O ISIF VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[2] YCC 16-bit: time multiplexed between chroma: CB/CR[02] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[02] (1) (2) (3) (4) (5) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. Specifies the operating I/O supply voltage for each signal. See Section 6.3 , Power Supplies for more detail. PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the following outputs placed near the device: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK. The trace lengths should be minimized. The Y input (YIN[7:0]) and C input (CIN[7:0]) buses can be swapped by programming the field bit YCINSWP in the VPFE CCD Configuration (CCDCFG) register (0x01C7 0136h). IF YCINSWP bit is 0 (default) YIN[7:0] = Y signal / CIN[7:0] = C signal . IF YCINSWP bit is 1 YIN[7:0] = C signal / CIN[7:0] = Y signal For more information, see the TMS320DM36x Video Processing Front End (VPFE) Reference Guide (literature number SPRUFG8). Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 21 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name CIN1 (5) BGA ID Type A18 I/O (1) Group ISIF Power Supply (2) IPU IPD (3) Reset State VDD_ISIF18_33 IPD Input Description (4) Standard ISIF Analog Front End (AFE): raw[1] YCC 16-bit: time multiplexed between chroma: CB/CR[01] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[01] CIN0 (5) B17 I/O ISIF VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[0] YCC 16-bit: time multiplexed between chroma: CB/CR[00] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[00] YIN7 (5) / GIO103 /SPI3_SCLK C12 I/O ISIF/ GIO / SPI3 VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[15] YCC 16-bit: time multiplexed between luma: Y[07] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[07] GIO: GIO[103] SPI3: Clock (5) YIN6 / GIO102 /SPI3_SIMO A13 I/O ISIF / GIO / SPI3 VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[14] YCC 16-bit: time multiplexed between luma: Y[06] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[06] GIO: GIO[102] SPI3: Slave Input Master Output Data Signal YIN5 (6) / GIO101 /SPI3_SCS[0] B13 I/O ISIF / GIO / SPI3 VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[13] YCC 16-bit: time multiplexed between luma: Y[05] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[05] GIO: GIO[101] SPI3: Chip Select 0 (6) YIN4 / GIO100 / SPI3_SOMI / SPI3_SCS[1] D12 I/O ISIF / GIO / SPI3 VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[12] YCC 16-bit: time multiplexed between luma: Y[04] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[04] GIO: GIO[100] SPI3: Slave Output Master Input Data Signal SPI3: Chip Select 1 (6) 22 The Y input (YIN[7:0]) and C input (CIN[7:0]) buses can be swapped by programming the field bit YCINSWP in the VPFE CCD Configuration (CCDCFG) register (0x01C7 0136h). IF YCINSWP bit is 0 (default) YIN[7:0] = Y signal / CIN[7:0] = C signal . IF YCINSWP bit is 1 YIN[7:0] = C signal / CIN[7:0] = Y signal For more information, see the TMS320DM36x Video Processing Front End (VPFE) Reference Guide (literature number SPRUFG8). Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name YIN3 (6) / GIO99 BGA ID Type A14 I/O (1) Group ISIF / GIO Power Supply (2) IPU IPD (3) Reset State VDD_ISIF18_33 IPD Input Description (4) Standard ISIF Analog Front End (AFE): raw[11] YCC 16-bit: time multiplexed between luma: Y[03] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[03] GIO: GIO[99] YIN2 (6) / GIO98 B15 I/O ISIF / GIO VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[10] YCC 16-bit: time multiplexed between luma: Y[02] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[02] GIO: GIO[98] YIN1 (6) / GIO97 D14 I/O ISIF / GIO VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[09] YCC 16-bit: time multiplexed between luma: Y[01] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[01] GIO: GIO[97] YIN0 (7) / GIO96 D15 I/O ISIF / GIO VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[08] YCC 16-bit: time multiplexed between luma: Y[00] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[00] GIO: GIO[96] HD / GIO95 C14 I/O ISIF / GIO VDD_ISIF18_33 IPD Input Horizontal synchronization signal that can be either an input (slave mode) or an output (master mode). Tells the ISIF when a new line starts. GIO: GIO[95] VD / GIO94 B14 I/O ISIF / GIO VDD_ISIF18_33 IPD Input Vertical synchronization signal that can be either an input (slave mode) or an output (master mode). Tells the ISIF when a new frame starts. GIO: GIO[94] C_WE_FIELD / GIO93 / CLKOUT0 / USBDRVVBUS E13 I/O ISIF / GIO / CLKOU T / USB VDD_ISIF18_33 IPD Input Write enable input signal is used by external device (AFE/TG) to gate the DDR output of the ISIF module. Alternately, the field identification input signal is used by external device (AFE/TG) to indicate the which of two frames is input to the ISIF module for sensors with interlaced output. ISIF handles 1- or 2-field sensors in hardware. GIO: GIO[93] CLKOUT0: Clock Output USB: Digital output to control external 5 V supply PCLK (7) D13 I/O/Z ISIF VDD_ISIF18_33 IPD Input Pixel clock input (strobe for lines CI7 through YI0) The Y input (YIN[7:0]) and C input (CIN[7:0]) buses can be swapped by programming the field bit YCINSWP in the VPFE CCD Configuration (CCDCFG) register (0x01C7 0136h). IF YCINSWP bit is 0 (default) YIN[7:0] = Y signal / CIN[7:0] = C signal . IF YCINSWP bit is 1 YIN[7:0] = C signal / CIN[7:0] = Y signal For more information, see the TMS320DM36x Video Processing Front End (VPFE) Reference Guide (literature number SPRUFG8). Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 23 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name Type YOUT7(R7) (8) G16 I/O VENC VDDS33 Input Digital Video Out: VENC settings determine function (9). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). YOUT6(R6) (8) G19 I/O VENC VDDS33 Input Digital Video Out: VENC settings determine function (9). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). YOUT5(R5) (8) F15 I/O VENC VDDS33 Input Digital Video Out: VENC settings determine function (9). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). YOUT4(R4) (8) F18 I/O VENC VDDS33 Input Digital Video Out: VENC settings determine function (9). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). YOUT3(R3) (8) F16 I/O VENC VDDS33 Input Digital Video Out: VENC settings determine function (9). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). YOUT2(G7) (8) F19 I/O VENC VDDS33 Input Digital Video Out: VENC settings determine function (9). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). YOUT1(G6) (10) F17 I/O VENC VDDS33 Input Digital Video Out: VENC settings determine function (11). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). YOUT0(G5) (10) E16 I/O VENC VDDS33 Input Digital Video Out: VENC settings determine function (11). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). HSYNC / GIO84 G15 I/O VENC / GIO VDDS33 Input Video Encoder: Horizontal Sync (11) VSYNC / GIO83 G18 I/O VENC / GIO VDDS33 Input LCD_OE / GIO82 C19 I/O VENC / GIO VDDS33 Output (1) Group Power Supply (2) IPU IPD (3) Description (4) BGA ID Reset State GIO: GIO[84] Video Encoder: Vertical Sync (11) GIO: GIO[83] Video Encoder: Data valid duration (11) GIO: GIO[82] (8) The Y output (YOUT[7:0]) and C output (COUT[7:0]) buses can be swapped by programming the field bit YCOUTSWP in the VPFE CCD Configuration (CCDCFG) register (0x01C7 0136h). If the YCOUTSWP bit is 0 (default), YOUT[7:0] = Y signal / COUT[7:0] = C signal . If the YCOUTSWP bit is 1, YOUT[7:0] = C signal / COUT[7:0] = Y signal. For more information, see the TMS320DM36x Video Processing Front End (VPFE) Reference Guide (literature number SPRUFG8). (9) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the following outputs placed near the device: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK. The trace lengths should be minimized. (10) The Y output (YOUT[7:0]) and C output (COUT[7:0]) buses can be swapped by programming the field bit YCOUTSWP in the VPFE CCD Configuration (CCDCFG) register (0x01C7 0136h). If the YCOUTSWP bit is 0 (default), YOUT[7:0] = Y signal / COUT[7:0] = C signal . If the YCOUTSWP bit is 1, YOUT[7:0] = C signal / COUT[7:0] = Y signal. For more information, see the TMS320DM36x Video Processing Front End (VPFE) Reference Guide (literature number SPRUFG8). (11) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the following outputs placed near the device: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK. The trace lengths should be minimized. 24 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name BGA ID Type Group Power Supply (2) IPU IPD (3) Reset State GIO80 / EXTCLK / B2 / PWM3 B19 I/O GIO / VENC / PWM3 VDDS33 IPD Input (1) Description (4) GIO: GIO[80] Video Encoder: External clock Input, used if clock rates > 27 MHz are needed, e.g. 74.25 MHz for HDTV digital output. Digital Video Out: B2 (11). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). PWM3: PWM3 Output VCLK / GIO79 B18 I/O VENC / GIO VDDS33 Input GIO92 / COUT7(G4) (10) / PWM0 E18 I/O GIO / VENC / PWM0 VDDS33 Input Video Encoder: Video Output Clock (11) GIO: GIO[79] GIO: GIO[92] Digital Video Out: VENC settings determine function (11). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). PWM0: PWM0 Output GIO91 / COUT6(G3) (10) / PWM1 E19 I/O GIO / VENC / PWM1 VDDS33 Input GIO: GIO[91] Digital Video Out: VENC settings determine function (11). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). PWM1: PWM1 Output GIO90 / COUT5(G2) (10) / PWM2 / RTO0 E15 I/O GIO / VENC /PWM2 / RTO0 VDDS33 Input GIO: GIO[90] Digital Video Out: VENC settings determine function (11). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). PWM2: PWM2 Output RTO0: RTO0 Output GIO89 / COUT4(B7) (12)/ PWM2 / RTO1 E17 I/O GIO / VENC / PWM2 / RTO1 VDDS33 Input GIO: GIO[89] Digital Video Out: VENC settings determine function (13). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). PWM2: PWM2 Output RTO1: RTO1 Output (12) The Y output (YOUT[7:0]) and C output (COUT[7:0]) buses can be swapped by programming the field bit YCOUTSWP in the VPFE CCD Configuration (CCDCFG) register (0x01C7 0136h). If the YCOUTSWP bit is 0 (default), YOUT[7:0] = Y signal / COUT[7:0] = C signal . If the YCOUTSWP bit is 1, YOUT[7:0] = C signal / COUT[7:0] = Y signal. For more information, see the TMS320DM36x Video Processing Front End (VPFE) Reference Guide (literature number SPRUFG8). (13) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the following outputs placed near the device: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK. The trace lengths should be minimized. Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 25 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name GIO88 / COUT3(B6) (12)/ PWM2 / RTO2 BGA ID Type Group Power Supply (2) D16 I/O GIO / VENC / PWM2 / RTO2 VDDS33 (1) IPU IPD (3) Description (4) Reset State Input GIO: GIO[88] Digital Video Out: VENC settings determine function (13). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). PWM2: PWM2 Output RTO2: RTO2 Output GIO87 / COUT2(B5) (12) / PWM2 / RTO3 D19 I/O GIO / VENC /PWM2 / RTO3 VDDS33 Input GIO: GIO[87] Digital Video Out: VENC settings determine function (13). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). PWM2: PWM2 Output RTO3: RTO3 Output GIO86 / COUT1(B4) (12) / PWM3 / STTRIG D18 I/O GIO / VENC / PWM3 VDDS33 Input GIO: GIO[86] Digital Video Out: VENC settings determine function (13). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). PWM3: PWM3 Output STTRIG: Camera FLASH control trigger signal GIO85 / COUT0(B3) PWM3 (14) D17 I/O / GIO / VENC / PWM3 VDDS33 Input GIO: GIO[85] Digital Video Out: VENC settings determine function (15). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). PWM3: PWM3 Output GIO81(OSCCFG) / LCD_FIELD / R2 / PWM3 C18 I/O GIO / VENC / PWM3 VDDS33 Input GIO: GIO[81] Note: This pin will be used as oscillator configuration (OSCCFG). The GIO81(OSCCFG) state is latched during reset, and it specifies the oscillation frequency range mode of the pin. See Section 3.7.6 for more details. Video Encoder: Field identifier for interlaced display formats (15). For more details, see the DM36x DMSoC Video Processor Back End User's Guide (SPRUFG9). Digital Video Out: R2 (15) PWM3: PWM3 Output (14) The Y output (YOUT[7:0]) and C output (COUT[7:0]) buses can be swapped by programming the field bit YCOUTSWP in the VPFE CCD Configuration (CCDCFG) register (0x01C7 0136h). If the YCOUTSWP bit is 0 (default), YOUT[7:0] = Y signal / COUT[7:0] = C signal . If the YCOUTSWP bit is 1, YOUT[7:0] = C signal / COUT[7:0] = Y signal. For more information, see the TMS320DM36x Video Processing Front End (VPFE) Reference Guide (literature number SPRUFG8). (15) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the following outputs placed near the device: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK. The trace lengths should be minimized. 26 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name VREF BGA ID Type D11 AI (1) Group Video DAC Power Supply (2) VDDA18_DAC IPU IPD (3) Description (4) Reset State Video DAC: Reference voltage for DAC. For more details, see Section 6.12.2.4, DAC and Video Buffer Electrical Data/Timing. Note: If the DAC peripheral is not used, this pin must be tied directly to VSS for proper device operation. IREF A11 A I/O Video DAC VDDA18_DAC Video DAC: Sets reference current for DAC. An external resistor with nominal value, 2400 ohms, is connected between IREF and VSS. For more details, see Section 6.12.2.4, DAC and Video Buffer Electrical Data/Timing. Note: If the DAC peripheral is not used, this pin must be tied directly to VSS for proper device operation. IDACOUT B11 A I/O Video DAC VDDA18_DAC Video DAC: Current source input from DAC. An external resistor with nominal value, 2100 ohms, is connected between IDACOUT and VFB. For more details, see Section 6.12.2.4, DAC and Video Buffer Electrical Data/Timing. Note: If the DAC peripheral is not used at all in the application, this pin can either be connected to VSS or be left open. VFB B10 A I/O Video DAC VDDA18_DAC Video DAC: Amplifier feedback node. An external resistor with nominal value, 2150 ohms, is connected between VFB and TVOUT. For more details, see Section 6.12.2.4, DAC and Video Buffer Electrical Data/Timing. Note: If the DAC peripheral is not used at all in the application, this pin can either be connected to VSS or be left open. TVOUT A10 A I/O Video DAC VDDA18_DAC Video DAC: DAC1video output. An external resistor with nominal value, 2150 ohms, is connected between TVOUT and VFB. This is the output node that drives the load (75 ohms). For more details, see Section 6.12.2.4, DAC and Video Buffer Electrical Data/Timing. Note: If the DAC peripheral is not used at all in the application, this pin can either be connected to VSS or be left open. COMPY COMPPB B12 A12 AO AO Video DAC VDDA18_DAC Video DAC VDDA18_DAC Video DAC: Analog video signal component output Y Note: If the DAC peripheral is not used at all in the application, this pin can either be connected to VSS or be left open. Video DAC: Analog video signal component output Pb Note: If the DAC peripheral is not used at all in the application, this pin can either be connected to VSS or be left open. COMPPR C11 AO Video DAC VDDA18_DAC Video DAC: Analog video signal component output Pr Note: If the DAC peripheral is not used at all in the application, this pin can either be connected to VSS or be left open. VDDA18_DAC VDDA12_DAC D10 E12 PWR PWR Video DAC VDDA18_DAC Video Dac VDDA12_DAC Video DAC: Analog 1.8-V power Note: If the DAC peripheral is not used, this pin must be tied directly to VSS for proper device operation. Video DAC: Analog 1.2-V power Note: If the DAC peripheral is not used, this pin must be tied directly to VSS for proper device operation. Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 27 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name VSSA18_DAC VSSA12_DAC BGA ID Type E11 GND F11 (1) GND Group Power Supply (2) IPU IPD (3) Description (4) Reset State Video DAC Video DAC: Analog 1.8-V ground Video DAC Video DAC: Analog 1.2-V ground Note: If the DAC peripheral is not used, this pin must be tied directly to VSS for proper device operation. Note: If the DAC peripheral is not used, this pin must be tied directly to VSS for proper device operation. DDR_CLK W11 O DDR VDD18_DDR DDR Data Clock DDR_CLK W12 O DDR VDD18_DDR DDR Complementary Data Clock DDR_RAS U12 O DDR VDD18_DDR DDR Row Address Strobe DDR_CAS V12 O DDR VDD18_DDR DDR Column Address Strobe DDR_WE W13 O DDR VDD18_DDR DDR Write Enable DDR_CS T12 O DDR VDD18_DDR DDR Chip Select DDR_CKE R13 O DDR VDD18_DDR DDR Clock Enable DDR_DQM[1] W6 O DDR VDD18_DDR Data mask input for DDR_DQ[15:8] DDR_DQM[0] T11 O DDR VDD18_DDR Data mask input for DDR_DQ[7:0] DDR_DQS[1] T7 I/O DDR VDD18_DDR Data strobe input/outputs for each byte of the 16-bit data bus used to synchronize the data transfers. Output to DDR2 when writing and inputs when reading. They are used to synchronize the data transfers. DDR_DQS1: For DDR_DQ[15:8] DDR_DQS[0] T10 I/O DDR VDD18_DDR DDR_DQSN[1] U6 I/O DDR VDD18_DDR Data strobe input/outputs for each byte of the 16-bit data bus used to synchronize the data transfers. Output to DDR2 when writing and inputs when reading. They are used to synchronize the data transfers. DDR_DQS0: For DDR_DQ[7:0] DDR: Complimentary data strobe input/outputs for each byte of the 16-bit data bus. They are outputs to the DDR2 when writing and inputs when reading. They are used to synchronize the data transfers. Note: This signal is used in double ended differential memory interfaces supported by the device. DDR_DQSN[0] U9 I/O DDR VDD18_DDR DDR: Complimentary data strobe input/outputs for each byte of the 16-bit data bus. They are outputs to the DDR2 when writing and inputs when reading. They are used to synchronize the data transfers. Note: This signal is used in double ended differential memory interfaces supported by the device. DDR_BA[2] V13 O DDR VDD18_DDR Bank select outputs. Two are required for 1Gb DDR2 memories. DDR_BA[1] T13 O DDR VDD18_DDR Bank select outputs. Two are required for 1Gb DDR2 memories. DDR_BA[0] W14 O DDR VDD18_DDR Bank select outputs. Two are required for 1Gb DDR2 memories. DDR_A13 T16 O DDR VDD18_DDR DDR Address Bus bit 13 DDR_A12 V17 O DDR VDD18_DDR DDR Address Bus bit 12 DDR_A11 W18 O DDR VDD18_DDR DDR Address Bus bit 11 DDR_A10 V16 O DDR VDD18_DDR DDR Address Bus bit 10 DDR_A9 U16 O DDR VDD18_DDR DDR Address Bus bit 09 DDR_A8 W17 O DDR VDD18_DDR DDR Address Bus bit 08 DDR_A7 T15 O DDR VDD18_DDR DDR Address Bus bit 07 DDR_A6 W16 O DDR VDD18_DDR DDR Address Bus bit 06 28 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name Type DDR_A5 V15 O DDR VDD18_DDR DDR Address Bus bit 05 DDR_A4 U15 O DDR VDD18_DDR DDR Address Bus bit 04 DDR_A3 T14 O DDR VDD18_DDR DDR Address Bus bit 03 DDR_A2 W15 O DDR VDD18_DDR DDR Address Bus bit 02 DDR_A1 V14 O DDR VDD18_DDR DDR Address Bus bit 01 DDR_A0 U14 O DDR VDD18_DDR DDR Address Bus bit 00 DDR_DQ15 V6 I/O DDR VDD18_DDR DDR Data Bus bit 15 DDR_DQ14 V7 I/O DDR VDD18_DDR DDR Data Bus bit 14 DDR_DQ13 R7 I/O DDR VDD18_DDR DDR Data Bus bit 13 DDR_DQ12 W7 I/O DDR VDD18_DDR DDR Data Bus bit 12 DDR_DQ11 V8 I/O DDR VDD18_DDR DDR Data Bus bit 11 DDR_DQ10 R8 I/O DDR VDD18_DDR DDR Data Bus bit 10 DDR_DQ9 U8 I/O DDR VDD18_DDR DDR Data Bus bit 09 DDR_DQ8 W8 I/O DDR VDD18_DDR DDR Data Bus bit 08 DDR_DQ7 R9 I/O DDR VDD18_DDR DDR Data Bus bit 07 DDR_DQ6 W9 I/O DDR VDD18_DDR DDR Data Bus bit 06 DDR_DQ5 V9 I/O DDR VDD18_DDR DDR Data Bus bit 05 DDR_DQ4 W10 I/O DDR VDD18_DDR DDR Data Bus bit 04 DDR_DQ3 V10 I/O DDR VDD18_DDR DDR Data Bus bit 03 DDR_DQ2 R10 I/O DDR VDD18_DDR DDR Data Bus bit 02 DDR_DQ1 V11 I/O DDR VDD18_DDR DDR Data Bus bit 01 DDR_DQ0 U11 I/O DDR VDD18_DDR DDR Data Bus bit 00 DDR_ DQGATE0 T8 O DDR VDD18_DDR DDR: Loopback signal for external DQS gating. Route to DDR and back to DDR_DQGATE1 with same constraints as used for DDR clock and data. DDR_ DQGATE1 T9 I DDR VDD18_DDR DDR: Loopback signal for external DQS gating. Route to DDR and back to DDR_DQGATE0 with same constraints as used for DDR clock and data. DDR_VREF P11 PWR DDR VDD18_DDR DDR: DDR_VREF is .5* VDD18_DDR = 0.9V for SSTL2 specific reference voltage. DDR_PADREFP R11 O DDR VDD18_DDR DDR: External resistor ( 50 ohm to ground) EM_A13 / GIO78 / BTSEL[2] V18 I/O/Z (1) Group Power Supply (2) IPU IPD (3) Description (4) BGA ID AEMIF / VDD_AEMIF1_18_ IPU/IPD GIO / disable 33 BTSEL[ d by 2] default Reset State Input Async EMIF: Address Bus bit[13] GIO: GIO[78] BTSEL[2]: See Section 3.2, Device Boot Modes for system usage of these pins. EM_A12 / GIO77 / BTSEL[1] U18 I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD GIO / disable 33 BTSEL[ d by 1] default Input Async EMIF: Address Bus bit[12] GIO: GIO[77] BTSEL[1]: See Section 3.2, Device Boot Modes for system usage of these pins. EM_A11 / GIO76 / BTSEL[0] V19 I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD GIO / disable 33 BTSEL[ d by 0] default Input Async EMIF: Address Bus bit[11] GIO: GIO[76] BTSEL[0]: See Section 3.2, Device Boot Modes for system usage of these pins. Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 29 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name BGA ID Type EM_A10 / GIO75 / AECFG[2] U19 I/O/Z (1) Group Power Supply (2) IPU IPD (3) AEMIF / VDD_AEMIF1_18_ IPU/IPD GIO / disable 33 AECFG d by [2] default Description (4) Reset State Input Async EMIF: Address Bus bit[10] GIO: GIO[75] AECFG[2]: See Section 3.2, Device Boot Modes and Table 3-14, AECFG (Async EMIF Configuration) for system usage of these pins. EM_A9 / GIO74 / AECFG[1] T18 I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD GIO / disable 33 AECFG d by [1] default Input Async EMIF: Address Bus bit[09] GIO: GIO[74] AECFG[1]: See Section 3.2, Device Boot Modes and Table 3-14, AECFG (Async EMIF Configuration) for system usage of these pins. EM_A8 / GIO73 / AECFG[0] T19 I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD GIO / disable 33 AECFG d by [0] default Input Async EMIF: Address Bus bit[08] GIO: GIO[73] AECFG[0]: See Section 3.2, Device Boot Modes and Table 3-14, AECFG (Async EMIF Configuration) for system usage of these pins. EM_A7 / GIO72 / KEYA3 T17 I/O/Z AEMIF / VDD_AEMIF1_18_ GIO / 33 KEYSC AN Input Async EMIF: Address Bus bit[07] GIO: GIO[72] Keyscan: A3 EM_A6 / GIO71 / KEYA2 R18 I/O/Z AEMIF / VDD_AEMIF1_18_ GIO / 33 KEYSC AN Input Async EMIF: Address Bus bit[06] GIO: GIO[71] Keyscan: A2 EM_A5 / GIO70 / KEYA1 R16 I/O/Z AEMIF / VDD_AEMIF1_18_ GIO / 33 KEYSC AN Input Async EMIF: Address Bus bit[05] GIO: GIO[70] Keyscan: A1 EM_A4 / GIO69 / KEYA0 R19 I/O/Z AEMIF / VDD_AEMIF1_18_ GIO/KE 33 YSCAN Input Async EMIF: Address Bus bit[04] GIO: GIO[69] Keyscan: A0 EM_A3 / GIO68 / KEYB3 R15 I/O/Z AEMIF / VDD_AEMIF1_18_ GIO/ 33 KEYSC AN Input Async EMIF: Address Bus bit[03] GIO: GIO[68] Keyscan: B3 30 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name BGA ID Type Group Power Supply (2) EM_A2 / HCNTLA M18 I/O/Z AEMIF/ HPI VDD_AEMIF2_18_ (1) IPU IPD (3) Description (4) Reset State Output Async EMIF: Address Bus bit[02] 33 HPI: The state of HCNTLA and HCNTLB determines if address, data, or control information is being transmitted between an external host and the device. Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_A1 / HHWIL M19 I/O/Z AEMIF/ HPI VDD_AEMIF2_18_ Output Async EMIF: Address Bus bit[01] 33 HPI: This pin is half-word identification input HHWIL. Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_A0 / GIO67 / KEYB2 / HCNTLB L17 I/O/Z AEMIF / VDD_AEMIF2_18_ GIO / 33 KEYSC AN / HPI Input Async EMIF: Address Bus bit[00] Note that the EM_A0 is always a 32-bit address GIO: GIO[56] Keyscan: B2 HPI: The state of HCNTLA and HCNTLB determines if address, data, or control information is being transmitted between an external host and the device. Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_BA1 / GIO66 / KEYB1 / HINTN R17 I/O/Z AEMIF / VDD_AEMIF1_18_ GIO / 33 KEYSC AN / HPI Input Async EMIF: Bank Address 1 signal = 16-bit address. In 16-bit mode, lowest address bit. In 8-bit mode, second lowest address bit GIO: GIO[66] Keyscan: B1 HPI: This pin is host interrupt output HINT Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_BA0 / EM_A14 / GIO65 / KEYB0 P17 I/O/Z AEMIF / VDD_AEMIF1_18_ GIO / 33 KEYSC AN Input Async EMIF: Bank Address 0 signal = 8-bit address. In 8-bit mode, lowest address bit. Async EMIF: Address line (bit[14] when using 16-bit memories. GIO: GIO[65] Keyscan: B0 EM_D15 / GIO64 / HD15 P18 I/O/Z AEMIF / VDD_AEMIF1_18_ GIO / 33 HPI Input Async EMIF: Data Bus bit[15] GIO: GIO[64] HPI: Data bus bit [15] Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 31 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name BGA ID Type EM_D14 / GIO63 / HD14 P16 I/O/Z (1) Group Power Supply (2) AEMIF / VDD_AEMIF1_18_ GIO / 33 HPI IPU IPD (3) Description (4) Reset State Input Async EMIF: Data Bus bit[14] GIO: GIO[63] HPI: Data bus bit [14] Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_D13 / GIO62 / HD13 P19 I/O/Z AEMIF / VDD_AEMIF1_18_ GIO / 33 HPI Input Async EMIF: Data Bus bit[13] GIO: GIO[62] HPI: Data bus bit [13] Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_D12 / GIO61 / HD12 P15 I/O/Z AEMIF / VDD_AEMIF1_18_ GIO / 33 HPI Input Async EMIF: Data Bus bit[12] GIO: GIO[61] HPI: Data bus bit [12] Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_D11 / GIO60 / HD11 N16 I/O/Z AEMIF / VDD_AEMIF1_18_ GIO / 33 HPI Input Async EMIF: Data Bus bit[11] GIO: GIO[60] HPI: Data bus bit [11] Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_D10 / GIO59 / HD10 N18 I/O/Z AEMIF / VDD_AEMIF1_18_ GIO / 33 HPI Input Async EMIF: Data Bus bit[10] GIO: GIO[59] HPI: Data bus bit [10] Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_D9 / GIO58 / HD9 N19 I/O/Z AEMIF / VDD_AEMIF1_18_ GIO / 33 HPI Input Async EMIF: Data Bus bit[09] GIO: GIO[58] HPI: Data bus bit [9] Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_D8 / GIO57 / HD8 N15 I/O/Z AEMIF / VDD_AEMIF1_18_ GIO / 33 HPI Input Async EMIF: Data Bus bit[08] GIO: GIO[57] 32 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name BGA ID Type (1) Group Power Supply (2) IPU IPD (3) Description (4) Reset State HPI: Data bus bit [8] Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_D7 / HD7 L16 I/O/Z AEMIF / VDD_AEMIF2_18_ HPI 33 Input Async EMIF: Data Bus bit[07] HPI: Data bus bit [7] Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_D6 / HD6 L18 I/O/Z AEMIF / VDD_AEMIF2_18_ HPI 33 Input Async EMIF: Data Bus bit[06] HPI: Data bus bit [6] Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_D5 / HD5 L19 I/O/Z AEMIF / VDD_AEMIF2_18_ HPI 33 Input Async EMIF: Data Bus bit[05] HPI: Data bus bit [5] Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_D4 / HD4 L15 I/O/Z AEMIF / VDD_AEMIF2_18_ HPI 33 Input Async EMIF: Data Bus bit[04] HPI: Data bus bit [4] Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_D3 / HD3 K15 I/O/Z AEMIF / VDD_AEMIF2_18_ HPI 33 Input Async EMIF: Data Bus bit[03] HPI: Data bus bit [3] Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_D2 / HD2 K19 I/O/Z AEMIF / VDD_AEMIF2_18_ HPI 33 Input Async EMIF: Data Bus bit[02] HPI: Data bus bit [2] Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_D1 / HD1 K16 I/O/Z AEMIF / VDD_AEMIF2_18_ HPI 33 Input Async EMIF: Data Bus bit[01] HPI: Data bus bit [1] Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_D0 / HD0 K18 I/O/Z AEMIF / VDD_AEMIF2_18_ HPI 33 Input Async EMIF: Data Bus bit[00] HPI: Data bus bit [0] Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 33 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name BGA ID Type EM_CE[0] / GIO56 / HCS M17 I/O/Z (1) Group Power Supply (2) IPU IPD (3) AEMIF / VDD_AEMIF1_18_ GIO / 33 HPI Reset State Description (4) Output Async EMIF: Lowest numbered Chip Select. Can be programmed to be used for standard asynchronous memories (example:flash), OneNand or NAND memory. Used for the default boot and ROM boot modes. GIO: GIO[56] HPI: this pin is HPI chip select input. Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_CE[1] / GIO55 / HAS J17 I/O/Z AEMIF / VDD_AEMIF2_18_ GIO / 33 HPI Output Async EMIF: Second Chip Select., Can be programmed to be used for standard asynchronous memories (example: flash), OneNand or NAND memory. GIO: GIO[55] HPI: This pin is host address strobe. Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_WE / GIO54 / HDS2 J15 I/O/Z AEMIF / VDD_AEMIF2_18_ GIO / 33 HPI Output Async EMIF: Write Enable GIO: GIO[54] HPI: This pin is host data strobe input 2. Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. EM_OE / GIO53 / HDS1 J19 I/O/Z AEMIF / VDD_AEMIF2_18_ GIO / 33 HPI Output Async EMIF: Output Enable GIO: GIO[53] HPI: This pin is host data strobe input 1. EM_WAIT / GIO52 / HRDY J18 I/O/Z AEMIF / VDD_AEMIF2_18_ GIO / 33 HPI IPU Input Async EMIF: Async WAIT GIO: GIO[52] HPI: This pin is host ready output from DSP to host. EM_ADV / GIO51 / HR/W M16 I/O/Z AEMIF / VDD_AEMIF1_18_ GIO / 33 HPI Output Async EMIF: Address Valid Detect for OneNAND interface GIO: GIO[51] HPI: This pin is host read or write select input. EM_CLK / GIO50 M15 I/O/Z AEMIF / VDD_AEMIF1_18_ GIO 33 Output Async EMIF: Clock signal for OneNAND flash interface GIO: GIO[50] GIO49 / McBSP_DX D5 I/O/Z GIO / McBSP VDDS33 IPD Input GIO: GIO[49] McBSP: Transmit Data GIO48 / McBSP_CLKX A5 I/O/Z GIO / McBSP VDDS33 IPD Input GIO: GIO[48] McBSP: Transmit Clock 34 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name GIO47 / McBSP_FSX BGA ID Type Group Power Supply (2) IPU IPD (3) Reset State C6 I/O/Z GIO / McBSP VDDS33 IPD Input (1) Description (4) GIO: GIO[47] McBSP: Transmit Frame Sync GIO46 / McBSP_DR E6 I/O/Z GIO / McBSP VDDS33 IPD Input GIO45 / McBSP_CLKR B6 I/O/Z GIO / McBSP VDDS33 IPD Input GIO44 / McBSP_FSR E7 I/O/Z GIO / McBSP VDDS33 IPD Input GIO43 / MMCSD1_CLK / EM_A20 T6 I/O/Z GIO / MMCS D1 / AEMIF VDDS33 IPD Input GIO: GIO[46] McBSP: Receive Data GIO: GIO[45] McBSP: Receive Clock GIO: GIO[44] McBSP: Receive Frame Sync GIO: GIO[43] MMCSD1: Clock Async EMIF: Address bit[20] GIO42 / MMCSD1_CMD / EM_A19 R6 I/O/Z GIO / MMCS D1 / AEMIF VDDS33 IPD Input GIO: GIO[42] MMCSD1: Command Async EMIF: Address bit[19] GIO41 / MMCSD1_DATA3 / EM_A18 W5 I/O/Z GIO / MMCS D/ AEMIF VDDS33 IPD Input GIO: GIO[41] MMCSD1: DATA3 Async EMIF: Address bit[18] GIO40 / MMCSD1_DATA2 / EM_A17 U5 I/O/Z GIO / MMCS D1 / AEMIF VDDS33 IPD Input GIO: GIO[40] MMCSD1: DATA2 Async EMIF: Address bit[17] GIO39 / MMCSD1_DATA1 / EM_A16 R5 I/O/Z GIO / MMCS D1 / AEMIF VDDS33 IPD Input GIO: GIO[39] MMCSD1: DATA1 Async EMIF: Address bit[16] GIO38 / MMCSD1_DATA0 / EM_A15 V5 I/O/Z GIO / MMCS D1 / AEMIF VDDS33 IPD Input GIO: GIO[38] MMCSD1: DATA0 Async EMIF: Address bit[15] GIO37 / SPI4_SCS[0]/ McBSP_CLKS / CLKOUT0 T5 I/O/Z GIO / SPI4 / McBSP / CLKOU T VDDS33 IPD Input GIO: GIO[37] SPI4: SPI4 Chip Select 0 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 35 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name BGA ID Type (1) Group Power Supply (2) IPU IPD (3) Description (4) Reset State McBSP: CLKS pin to source an external clock CLKOUT: Output Clock 0 GIO36 / SPI4_SCLK / EM_A21 / EM_A14 W4 I/O/Z GIO / SPI4 / AEMIF VDDS33 IPD Input GIO: GIO[36] SPI4: Clock Async EMIF: Address bit[21] Async EMIF: Address bit[14] GIO35 / SPI4_SOMI / SPI4_SCS[1] / CLKOUT1 W3 I/O/Z GIO / SPI4 /CLKO UT VDDS33 IPD Input GIO: GIO[35] SPI4: Slave Out Master In data SPI4: SPI4 Chip Select 1 CLKOUT: Output Clock 1 GIO34 / SPI4_SIMO / SPI4_SOMI / UART1_RXD V4 I/O/Z GIO / SPI4 / UART1 VDDS33 IPD Input GIO: GIO[34] SPI4: Slave In Master Out data SPI4: Slave Out Master In data. UART1: RXD GIO33 / SPI2_SCS[0] / USBDRVVBUS / R1 V3 I/O/Z GIO / SPI2 / USB /VENC VDDS33 IPD Input GIO: GIO[33] SPI3: SPI3 Chip Select 0 USB: USB: Digital output to control external 5 V supply VENC: Red output data bit 1 GIO32 / SPI2_SCLK / R0 W2 I/O/Z GIO / SPI2 / VENC VDDS33 IPD Input GIO: GIO[32] SPI2: Clock VENC: Red output data bit 0 GIO31 / SPI2_SOMI / SPI2_SCS[1] / CLKOUT2 U4 I/O/Z GIO / SPI2 / CLKOU T VDDS33 IPD Input GIO: GIO[31] SPI2: Slave Out Master In data SPI2: SPI2 Chip Select 1 CLKOUT: Output Clock 2 GIO30 / SPI2_SIMO / G1 T4 I/O/Z GIO / SPI2 / VENC VDDS33 IPD Input GIO: GIO[30] SPI2: Slave In Master Out data VENC: Green output data bit 1 GIO29 / SPI1_SCS[0] / G0 U2 I/O/Z GIO / SPI1 / VENC VDDS33 IPD Input GIO: GIO[29] SPI1: SPI1 Chip Select 0 VENC: Green output data bit 0 36 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name GIO28 / SPI1_SCLK / B1 BGA ID Type V1 I/O/Z (1) Group GIO / SPI1 / VENC Power Supply (2) IPU IPD (3) Reset State VDDS33 IPD Input Description (4) GIO: GIO[28] SPI1: Clock VENC: Blue output data bit 1 GIO27 / SPI1_SOMI / SPI1_SCS[1] / B0 T2 I/O/Z GIO / SPI1 / VENC VDDS33 IPD Input GIO: GIO[27] SPI1: Slave Out Master In data SPI1: SPI1 Chip Select 1 VENC: Blue output data bit 1 GIO26 / SPI1_SIMO U1 I/O/Z GIO / SPI1 VDDS33 IPD Input GIO: GIO[26] SPI1: Slave In Master Out data GIO25 / SPI0_SCS[0] / PWM1 / UART1_TXD T1 I/O/Z GIO / SPI0 / PWM1 / UART1 VDDS33 IPD Input GIO: GIO[25] SPI0: SPI0 Chip Select 0 PWM1: Output UART1: Transmit data GIO24 / SPI0_SCLK T3 I/O/Z GIO / SPI0 VDDS33 IPD Input GIO23 / SPI0_SOMI / SPI0_SCS[1] / PWM0 V2 I/O/Z GIO / SPI0 / PWM0 VDDS33 IPD Input GIO: GIO[24] SPI0: Clock GIO: GIO[23] SPI0: Slave Out Master In data SPI0: SPI0 Chip Select 1 PWM0: Output GIO22 / SPI0_SIMO R2 I/O/Z GIO / SPI0 VDDS33 IPD Input GIO21 / UART1_RTS / I2C_SDA F3 I/O/Z GIO / UART1 / I2C VDDS33 IPD Input GIO: GIO[22] SPI0: Slave In Master Out data GIO: GIO[21] UART1: RTS I2C: Serial Data GIO20 / UART1_CTS / I2C_SCL F1 I/O/Z GIO / UART1 / I2C VDDS33 IPD Input GIO: GIO[20] UART1: CTS I2C: Serial Clock GIO19 / UART0_RXD E3 I/O/Z GIO / UART0 VDDS33 IPD Input GIO18 / UART0_TXD E2 I/O/Z GIO / UART0 VDDS33 IPD Input GIO: GIO[19] UART0: Receive data GIO: GIO[18] UART0: Transmit data GIO17 / EMAC_TX_EN / UART1_RXD E4 I/O/Z GIO / EMAC / UART1 VDDS33 IPD Input GIO: GIO[17] Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 37 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name BGA ID Type (1) Group Power Supply (2) IPU IPD (3) Description (4) Reset State EMAC: Transmit enable output UART1: Receive Data GIO16 / EMAC_TX_CLK / UART1_TXD E1 I/O/Z GIO / EMAC / UART1 VDDS33 IPD Input GIO: GIO[16] EMAC: Transmit clock UART1: Transmit Data GIO15 / EMAC_COL D2 I/O/Z GIO / EMAC VDDS33 IPD Input GIO: GIO[15] EMAC: Collision Detect input GIO14 / EMAC_TXD3 D1 I/O/Z GIO / EMAC VDDS33 IPD Input GIO13 / EMAC_TXD2 D3 I/O/Z GIO / EMAC VDDS33 IPD Input GIO12 / EMAC_TXD1 C1 I/O/Z GIO / EMAC VDDS33 IPD Input GIO11 / EMAC_TXD0 B1 I/O/Z GIO / EMAC VDDS33 IPD Input GIO10 / EMAC_RXD3 B2 I/O/Z GIO / EMAC VDDS33 IPD Input GIO9 / EMAC_RXD2 C2 I/O/Z GIO / EMAC VDDS33 IPD Input GIO: GIO[14] EMAC: Transmit Data 3 output GIO: GIO[13] EMAC: Transmit Data 2 output GIO: GIO[12] EMAC: Transmit Data 1 output GIO: GIO[11] EMAC: Transmit Data 0 output GIO: GIO[10] EMAC: Receive Data 3 output GIO: GIO[09] EMAC: Receive Data 2 output GIO8 / EMAC_RXD1 A2 I/O/Z GIO / EMAC VDDS33 IPD Input GIO: GIO[08] EMAC: Receive Data 1 output GIO7 / EMAC_RXD0 A3 I/O/Z GIO / EMAC VDDS33 IPD Input GIO6 / EMAC_RX_CLK B3 I/O/Z GIO / EMAC VDDS33 IPD Input GIO5 / EMAC_RX_DV B4 I/O/Z GIO / EMAC VDDS33 IPD Input GIO4 / EMAC_RX_ER A4 I/O/Z GIO / EMAC VDDS33 IPD Input GIO3 / EMAC_CRS C5 I/O/Z GIO / EMAC VDDS33 IPD Input GIO: GIO[07] EMAC: Receive Data 0 output GIO: GIO[06] EMAC: Receive clock GIO: GIO[05] EMAC: Receive data valid input GIO: GIO[04] EMAC: Receive error input GIO: GIO[03] EMAC: Carrier sense input GIO2 / MDIO C4 I/O/Z GIO / EMAC VDDS33 IPD Input GIO: GIO[02] EMAC: Management Data I/O GIO1 / MDCLK D6 I/O/Z GIO / EMAC VDDS33 IPD Input GIO: GIO[01] EMAC: Management Data clock output 38 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name BGA ID Type (1) Group Power Supply (2) IPU IPD (3) Reset State VDDS33 IPD Input Description (4) GIO0 B5 I/O/Z GIO USB_DP N1 A I/O USBPH Y VDDA33_USB GIO: GIO[00] USB D+ (differential signal pair) Note: If the USB peripheral is not used at all in the application, this pin should be connected to 3.3V . USB_DM P1 A I/O USBPH Y VDDA33_USB USB D- (differential signal pair) Note: If the USB peripheral is not used at all in the application, this pin should be connected to VSS. VDDA33_USB P4 PWR 3.3-V USB analog power supply Note: If the USB peripheral is not used at all in the application, this pin should be connected to 3.3V. VSSA33_USB P3 GND 3.3-V USB ground Note: If the USB peripheral is not used at all in the application, this pin should be connected to VSS. VDDA12LDO_USB M5 PWR VDDA18_USB N5 PWR Output For proper device operation, even if the USB peripheral is not used, a 0.22µF capacitor must be connected as close as possible to the package, and the capacitor mst be connected to VSSA. 1.8-V USB analog power supply Note: If the USB peripheral is not used at all in the application, this pin should be connected to 1.8V. VSSA18_USB P2 GND 1.8-V USB ground Note: If the USB peripheral is not used at all in the application, this pin should be connected to VSS. USB_ID M1 AI USBPH Y VDDA33_USB USB operating mode identification pin. For device mode operation only, pull up this pin to VDD with a 1.5K ohm resistor. For host mode operation only, pull down this pin to ground (VSS) with a 1.5K ohm resistor. If using an OTG or mini-USB connector, this pin will be set properly via the cable/connector configuration. Note: If the USB peripheral is not used at all in the application, this pin should be connected to 3.3V. USB_VBUS N2 A I/O USBPH Y USB_VBUS This pin is used by the USB Controller to detect a presence of 5V power (4.4V is the threshold) on the USB_VBUS line for normal operation. This power is sourced by the USB Component that is assuming the role of a Host. In other words, the power on the USB_VBUS line is not sourced by the Device. From DM365 perspective, when operating as a Host, it ensures that the external power supply that the DM365 has sourced is within the required voltage level (>= 4.4V) and when DM365 is operating as a Device, the presence of a 5V power on the VBUS Line is used to signify the presence of an external Host. Note 1: When the DM365 is operating as a Device, it uses the power on the USB_VBUS line to power up its internal pull-up resistor on the D+ line. Note2: If the USB peripheral is not used at all in the application, this pin should be connected to VSS. MMCSD0_CLK J16 O MMCS D0 VDDS33 out MMCSD0: Clock MMCSD0_CMD H15 I/O/Z MMCS D0 VDDS33 Input MMCSD0: Command MMCSD0_DATA3 H16 I/O/Z MMCS D0 VDDS33 Input MMCSD0: DATA3 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 39 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) BGA ID Type Group Power Supply (2) MMCSD0_DATA2 H17 I/O/Z MMCS D0 VDDS33 Input MMCSD0: DATA2 MMCSD0_DATA1 H19 I/O/Z MMCS D0 VDDS33 Input MMCSD0: DATA1 MMCSD0_DATA0 H18 I/O/Z MMCS D0 VDDS33 Input MMCSD0: DATA0 B8 AI VCODE C VDDA33_VC or VDDA18_VC MIC positive input VCODE C VDDA33_VC or VDDA18_VC MIC negative input VCODE C VDDA33_VC or VDDA18_VC Line driver output VCODE C VDDA33_VC or VDDA18_VC Speaker amplifier positive output VCODE C VDDA33_VC or VDDA18_VC Speaker amplifier negative output VCODE C VDDA33_VC or VDDA18_VC Analog block common voltage. It is recommended that a 10µF capacitor be connected between this pin and ground to provide clean voltage. MICIP MICIN C8 LINEO C9 SPP B9 SPN A9 VCOM A8 (1) AI AO AO AO AO IPU IPD (3) Description (4) Name Reset State Note: If the Voice Codec peripheral is not used, this pin must be tied directly to VSS for proper device operation. Note: If the Voice Codec peripheral is not used, this pin must be tied directly to VSS for proper device operation. Note: If the Voice Codec peripheral is not used, this pin can be left open or can be connected directly to Vss for proper device operation. Note: If the Voice Codec peripheral is not used, this pin can be left open or can be connected directly to Vss for proper device operation. Note: If the Voice Codec peripheral is not used, this pin can be left open or can be connected directly to Vss for proper device operation. Note: If the Voice Codec peripheral is not used, this pin must be tied directly to VSS for proper device operation. VDDA18_VC E9 PWR 1.8-V Voice Codec module analog power supply Note: If the Voice Codec peripheral is not used, this pin must be tied directly to VSS for proper device operation. VSSA18_VC F9 GND 1.8-V Voice Codec module ground Note: If the Voice Codec peripheral is not used, this pin must be tied directly to VSS for proper device operation. VDDA33_VC E10 PWR 3.3-V Voice Codec module power supply Note: If the Voice Codec peripheral is not used, this pin must be tied directly to VSS for proper device operation. VSSA33_VC D9 GND 3.3-V Voice Codec module ground Note: If the Voice Codec peripheral is not used, this pin must be tied directly to VSS for proper device operation. 40 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name ADC_CH0 BGA ID Type E8 AI (1) Group ADC Power Supply (2) IPU IPD (3) Description (4) Reset State VDDA18_ADC Analog-to-Digital converter channel 0 Note: If the ADC is not used, it is recommended to either leave this pin open, as no connect, or tie this pin along with the other ADC_CHs together to a single resistor to ground. ADC_CH1 B7 AI ADC VDDA18_ADC Analog-to-Digital converter channel 1 Note: If the ADC is not used, it is recommended to either leave this pin open, as no connect, or tie this pin along with the other ADC_CHs together to a single resistor to ground. ADC_CH2 A7 AI ADC VDDA18_ADC Analog-to-Digital converter channel Note: If the ADC is not used, it is recommended to either leave this pin open, as no connect, or tie this pin along with the other ADC_CHs together to a single resistor to ground. ADC_CH3 D8 AI ADC VDDA18_ADC Analog-to-Digital converter channel 3 Note: If the ADC is not used, it is recommended to either leave this pin open, as no connect, or tie this pin along with the other ADC_CHs together to a single resistor to ground. ADC_CH4 D7 AI ADC VDDA18_ADC Analog-to-Digital converter channel 4 Note: If the ADC is not used, it is recommended to either leave this pin open, as no connect, or tie this pin along with the other ADC_CHs together to a single resistor to ground. ADC_CH5 A6 AI ADC VDDA18_ADC Analog-to-Digital converter channel 5 Note: If the ADC is not used, it is recommended to either leave this pin open, as no connect, or tie this pin along with the other ADC_CHs together to a single resistor to ground. VDDA18_ADC G9 PWR 1.8- V Analog-to-Digital converter analog power supply Note: If the ADC is not used at all in an application, this pin can be directly connected to the 1.8-V supply without any filtering or to ground. VSSA_ADC F8 GND 1.8- V Analog-to-Digital converter ground PWCTRIO0 J3 I/O/Z PRTCS S VDD18_PRTCSS Input PRTCSS: General Input / Output Signal 0 For more pin termination details, see Section 6.7, Power Management and Real Time Clock Subsystem (PRTCSS). PWCTRIO1 J2 I/O/Z PRTCS S VDD18_PRTCSS Input PRTCSS: General Input / Output Signal 1 For more pin termination details, see Section 6.7, Power Management and Real Time Clock Subsystem (PRTCSS). PWCTRIO2 J1 I/O/Z PRTCS S VDD18_PRTCSS Input PRTCSS: General Input / Output Signal 2 For more pin termination details, see Section 6.7, Power Management and Real Time Clock Subsystem (PRTCSS). PWCTRIO3 J5 I/O/Z PRTCS S VDD18_PRTCSS Input PRTCSS: General Input / Output Signal 3 For more pin termination details, see Section 6.7, Power Management and Real Time Clock Subsystem (PRTCSS). PWCTRIO4 J4 I/O/Z PRTCS S VDD18_PRTCSS Input PRTCSS: General Input / Output Signal 4 For more pin termination details, see Section 6.7, Power Management and Real Time Clock Subsystem (PRTCSS). Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 41 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name Type Group Power Supply (2) PWCTRIO5 K5 I/O/Z PRTCS S VDD18_PRTCSS Input PRTCSS: General Input / Output Signal 5 For more pin termination details, see Section 6.7, Power Management and Real Time Clock Subsystem (PRTCSS). PWCTRIO6 K4 I/O/Z PRTCS S VDD18_PRTCSS Input PRTCSS: General Input / Output Signal 6 For more pin termination details, see Section 6.7, Power Management and Real Time Clock Subsystem (PRTCSS). PWCTRO0 K2 O PRTCS S VDD18_PRTCSS Output PRTCSS: General Output Signal 0 For more pin termination details, see Section 6.7, Power Management and Real Time Clock Subsystem (PRTCSS). PWCTRO1 L5 O PRTCS S VDD18_PRTCSS Output PRTCSS: General Output Signal 1 For more pin termination details, see Section 6.7, Power Management and Real Time Clock Subsystem (PRTCSS). PWCTRO2 L4 I/O/Z PRTCS S VDD18_PRTCSS Output PRTCSS: General Output Signal 2 For more pin termination details, see Section 6.7, Power Management and Real Time Clock Subsystem (PRTCSS). PWCTRO3 L3 O PRTCS S VDD18_PRTCSS Output PRTCSS: General Output Signal 3 For more pin termination details, see Section 6.7, Power Management and Real Time Clock Subsystem (PRTCSS). RTCXI G1 I PRTCS S VDD12_PRTCSS Input PRTCSS: Crystal Input for PRTCSS oscillator Note: If the RTC calendar is not used, this pin should be pulled down. For more pin termination details, see Section 6.7, Power Management and Real Time Clock Subsystem (PRTCSS). RTCXO H1 O PRTCS S VDD12_PRTCSS Output PRTCSS: Crystal Output for PRTCSS oscillator Note: If the RTC calendar is not used, this pin should be left unconnected. For more pin termination details, see Section 6.7, Power Management and Real Time Clock Subsystem (PRTCSS). PWRST M3 I PRTCS S VDD12_PRTCSS Input PRTCSS: Reset signal for PRTCSS For more pin termination details, see Section 6.7, Power Management and Real Time Clock Subsystem (PRTCSS). PWRCNTON M2 I PRTCS S VDD12_PRTCSS Input PRTCSS: Reset pin for system power sequencing For more pin details, see Section 6.7. RESET H3 I VDDS33 Input Global chip reset MXI1 L1 I CLOCK S VDDMXI Input Crystal input for system oscillator Note: If an external oscillator is to be used, the external oscillator clock signal should be connected to the MXI1 pin with a 1.8V amplitude. The MXO1 should be left unconnected and the VSS_MX1 signal should be connected to board ground (Vss). MXO1 K1 O CLOCK S VDDMXI Output Output for system oscillator Note: If an external oscillator is to be used, the external oscillator clock signal should be connected to the MXI1 pin with a 1.8V amplitude. The MXO1 should be left unconnected and the VSS_MX1 signal should be connected to board ground (Vss). TCK F4 I EMULA TION VDDS33 IPU Input JTAG test clock input TDI F5 I EMULA TION VDDS33 IPU Input JTAG test data input TDO G4 O EMULA TION VDDS33 42 (1) IPU IPD (3) Description (4) BGA ID Reset State Output JTAG test data output Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name Description (4) BGA ID Type Group Power Supply (2) IPU IPD (3) Reset State TMS G2 I EMULA TION VDDS33 IPU Input JTAG test mode select TRST H5 I EMULA TION VDDS33 IPD Input JTAG test logic reset RTCK F2 O EMULA TION VDDS33 EMU0 G5 I/O EMULA TION VDDS33 EMU1 H4 I/O EMULA TION VDDS33 (1) Output JTAG test clock output IPU Input JTAG emulation 0 I/O IPU Input JTAG emulation 1 I/O EMU[1:0] = 00 - Force Debug Scan chain (ARM and ARM ETB TAPs connected) EMU[1:0] = 11 - Normal Scan chain (ICEpick only) RSV2 R4 I For proper device operation, this pin must be tied to ground. RSV1 R1 O For proper device operation, this pin must be left unconnected. RSV0 A1 O For proper device operation, this pin must be left unconnected. CVDD G6 PWR Core power (1.2-V or 1.35-V). PWR Power supply for RTC oscillator, PRTCSS, and PRTCSS I/O (1.2-V or 1.35-V). G8 H7 H8 H12 J8 J12 J14 K8 K12 L13 M6 M10 M12 M13 VDD12_PRTCSS J6 VDDA18_PLL N4 PWR VDDRAM D4 O VDDS18 G14 PWR Power supply for 1.8-V I/O. K7 Analog power for PLL (1.8 V). Output For proper device operation, this pin must be connected to a 1.0uF (6.2V) capacitor, and the other end of the capacitor must be connected to Vss. Note: this pin is an internal power supply pin and should not be connected to any external power supply.” H11 H14 J7 M14 P7 VDD18_PRTCSS K6 PWR Power supply for PRTCSS (1.8 V). VDDMXI L6 PWR Power supply for PLL oscillator (1.8 V). Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 43 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name VDD18_SLDO VDD18_DDR Type E5 PWR Power supply for internal RAM. For proper device operation, this pin must always be connected to VDDS18. N9 PWR Power supply for DDR (1.8 V). PWR Power supply for 3.3-V I/O. PWR Power supply for switchable AEMIF (3.3/1.8 V). VDD_AEMIF1_18_33 : can be used as a power supply for EM_A[3:13], EM_BA0, EM_BA1, EM_CE[0], EM_ADV, EM_CLK, EM_D[8:15] or as GPIO pins. See AEMIF pin descriptions. (1) Group Power Supply (2) IPU IPD (3) Description (4) BGA ID Reset State N11 P9 P10 P12 R12 VDDS33 F10 F6 F7 H6 H13 L12 N6 P5 P6 VDD_AEMIF1_18_33 P14 R14 VDD_AEMIF2_18_33 K14 PWR L14 VDD_AEMIF2_18_33: can be used as a power supply for EM_A[0:2], EM_CE[1], EM_WE, EM_OE, EM_WAIT, EM_D[0:7] pins, HPI, or GPIO pins. See AEMIF pin descriptions. Example 1: VDD_AEMIF2_18_33 at 1.8-V for 8-bit NAND VDD_AEMIF1_18_33 at 3.3-V for GPIO. Example 2: VDD_AEMIF1_18_33 and VDD_AEMIF2_18_33 at 1.8-V for 16-bit NAND. VDD_ISIF18_33 VPP 44 F12 PWR Power supply for switchable ISIF (3.3/1.8 V). F13 PWR Example 1 VDD_ISIF_18_33 power supply can be at 1.8V for VPFE pin functionality or it can be at 3.3V if other peripherals pin functionality is to be used like SPI3 or GPIO or CLKOUT0, or USBDRVVBUS. R3 PWR For proper device operation, this pin must always be connected to CVDD. Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name Type A19 GND Digital ground L2 GND System oscillator - ground Note: Note: If an external oscillator is used, this pin must be connected to board ground (Vss). VSS_32K H2 GND PRTCSS oscillator - ground VSSA M4 GND Analog ground VSS (1) Group Power Supply (2) IPU IPD (3) Description (4) BGA ID Reset State E14 F14 G11 G12 H9 H10 J9 J10 J11 J13 K9 K10 K11 L7 L8 L9 L10 L11 M7 M8 M9 M11 N8 N12 N14 P8 P13 W1 W19 VSS_MX1 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 45 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 2.9 2.9.1 www.ti.com Device Support Development Tools TI offers an extensive line of development tools for device systems, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tools support documentation is electronically available within the Code Composer Studio™ Integrated Development Environment (IDE). The following products support development of device based applications: Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Hardware Development Tools: Extended Development System (XDS™) Emulator (supports TMS320DM365 DMSoC multiprocessor system debug) EVM (Evaluation Module) For a complete listing of development-support tools for the TMS320DM365 DMSoC platform, visit the Texas Instruments web site on the Worldwide Web at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. 2.9.2 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., ). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications. TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. TMS Fully-qualified production device. Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product. TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate is undefined. Only qualified production devices are to be used in production. 46 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZCE), the temperature range (for example, "Blank" is the commercial temperature range), and the device speed range in megahertz (for example, 202 is 202.5 MHz). The following figure provides a legend for reading the complete device name for any TMS320DM365 DMSoC platform member. TMS 320 DM365 ( ) ZCE ( ) 27 ( ) F = Face Detection PREFIX TMX = Experimental device TMS = Qualified device SPEED GRADE 21 = 216 MHz 27 = 270 MHz 30 = 300 MHZ TEMPERATURE GRADE Blank = 0 to 85C D = -40 to 85C DEVICE FAMILY 320 = TMS320 DSP family DEVICE DM365 (B) (A) PACKAGE TYPE ZCE = 338-pin plastic BGA, with Pb-free soldered balls (C) SILICON REVISION A. BGA = Ball Grid Array. B. For actual device part numbers (P/Ns) and ordering information, contact your nearest TI Sales Representative. C. For more information on silicon revision, see the TMS320DM365 Silicon Errata (literature number SPRZ294). Figure 2-6. Device Nomenclature 2.9.3 Related Documentation From Texas Instruments The following documents describe the TMS320DM36x Digital Media System-on-Chip (DMSoC). Copies of these documents are available on the internet at www.ti.com. SPRZ294 TMS320DM365 DMSoC Silicon Errata Describes the known exceptions to the functional specifications for the TMS320DM365 DMSoC. SPRUFG5 TMS320DM36x Digital Media System-on-Chip (DMSoC) ARM Subsystem Users Guide. This document describes the ARM Subsystem in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the components of the ARM Subsystem, the peripherals, and the external memories. SPRUFG8 TMS320DM36x Digital Media System-on-Chip (DMSoC) Video Processing Front End (VPFE) Users Guide. This document describes the Video Processing Front End (VPFE) in the TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFG9 TMS320DM36x Digital Media System-on-Chip (DMSoC) Video Processing Back End (VPBE) Users Guide. This document describes the Video Processing Back End (VPBE) in the TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFH0 TMS320DM36x Digital Media System-on-Chip (DMSoC) 64-bit Timer Users Guide. This document describes the operation of the software-programmable 64-bit timers in the TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFH1 TMS320DM36x Digital Media System-on-Chip (DMSoC) Serial Peripheral Interface (SPI) Users Guide. This document describes the serial peripheral interface (SPI) in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communication between the DMSoC and external peripherals. Typical applications include an interface to external I/O or peripheral expansion via devices such as Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 47 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com shift registers, display drivers, SPI EPROMs and analog-to-digital converters. 48 SPRUFH2 TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Asynchronous Receiver/Transmitter (UART) Users Guide. This document describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The UART peripheral performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data received from the CPU. SPRUFH3 TMS320DM36x Digital Media System-on-Chip (DMSoC) Inter-Integrated Circuit (I2C) Peripheral Users Guide. This document describes the inter-integrated circuit (I2C) peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The I2C peripheral provides an interface between the DMSoC and other devices compliant with the I2C-bus specification and connected by way of an I2C-bus. SPRUFH5 TMS320DM36x Digital Media System-on-Chip (DMSoC) Multimedia Card (MMC)/Secure Digital (SD) Card Controller Users Guide. This document describes the multimedia card (MMC)/secure digital (SD) card controller in the TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFH6 TMS320DM36x Digital Media System-on-Chip (DMSoC) Pulse-Width Modulator (PWM) Users Guide. This document describes the pulse-width modulator (PWM) peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFH7 TMS320DM36x Digital Media System-on-Chip (DMSoC) Real-Time Out (RTO) Controller Users Guide. This document describes the Real Time Out (RTO) controller in the TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFH8 TMS320DM36x Digital Media System-on-Chip (DMSoC) General-Purpose Input/Output (GPIO) Users Guide. This document describes the general-purpose input/output (GPIO) peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. SPRUFH9 TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Serial Bus (USB) Controller Users Guide. This document describes the universal serial bus (USB) controller in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The USB controller supports data throughput rates up to 480 Mbps. It provides a mechanism for data transfer between USB devices and also supports host negotiation. SPRUFI0 TMS320DM36x Digital Media System-on-Chip (DMSoC) Enhanced Direct Memory Access (EDMA) Controller Users Guide. This document describes the operation of the enhanced direct memory access (EDMA3) controller in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The EDMA controller's primary purpose is to service user-programmed data transfers between two memory-mapped slave endpoints on the DMSoC. SPRUFI1 TMS320DM36x Digital Media System-on-Chip (DMSoC) Asynchronous External Memory Interface (EMIF) Users Guide. This document describes the asynchronous external memory interface (EMIF) in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to a variety of external devices. SPRUFI2 TMS320DM36x Digital Media System-on-Chip (DMSoC) DDR2/Mobile DDR (DDR2/mDDR) Memory Controller Users Guide. This document describes the DDR2/mDDR memory controller in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The DDR2/mDDR memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM and mobile DDR devices. SPRUFI3 TMS320DM36x Digital Media System-on-Chip (DMSoC) Multibuffered Serial Port Interface (McBSP) User's Guide. This document describes the operation of the Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com multibuffered serial host port interface in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The primary audio modes that are supported by the McBSP are the AC97 and IIS modes. In addition to the primary audio modes, the McBSP supports general serial port receive and transmit operation. SPRUFI4 TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Host Port Interface (UHPI) User's Guide. This document describes the operation of the universal host port interface in the TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFI5 TMS320DM36x Digital Media System-on-Chip (DMSoC) Ethernet Media Access Controller (EMAC) User's Guide. This document describes the operation of the ethernet media access controllerface in the TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFI7 TMS320DM36x Digital Media System-on-Chip (DMSoC) Analog to Digital Converter (ADC) User's Guide. This document describes the operation of the analog to digital conversion in the TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFI8 TMS320DM36x Digital Media System-on-Chip (DMSoC) Key Scan User's Guide. This document describes the key scan peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFI9 TMS320DM36x Digital Media System-on-Chip (DMSoC) Voice Codec User's Guide. This document describes the voice codec peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC). This module can access ADC/DAC data with internal FIFO (Read FIFO/Write FIFO). The CPU communicates to the voice codec module using 32-bit-wide control registers accessible via the internal peripheral bus. SPRUFJ0 TMS320DM36x Digital Media System-on-Chip (DMSoC) Power Management and Real-Time Clock Subsystem (PRTCSS) User's Guide. This document provides a functional description of the Power Management and Real-Time Clock Subsystem (PRTCSS) in the TMS320DM36x Digital Media System-on-Chip (DMSoC) and PRTC interface (PRTCIF). Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 49 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 3 Device Configurations This section provides a detailed overview of the device. 3.1 System Module Registers The system module includes status and control registers for configuration of the device. Brief descriptions of the various registers are shown in Table 3-1. For more information on the System Module registers, see the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5). Table 3-1. System Module Register Memory Map HEX ADDRESS DESCRIPTION (1) REGISTER ACRONYM 0x01C4 0000 PINMUX0 Pin Mux 0 (Video In) Pin Mux Register 0x01C4 0004 PINMUX1 Pin Mux 1 (Video Out) Pin Mux Register 0x01C4 0008 PINMUX2 Pin Mux 2 (AEMIF) Pin Mux Register 0x01C4 000C PINMUX3 Pin Mux 3 (GIO/Misc) Pin Mux Register 0x01C4 0010 PINMUX4 Pin Mux 4 (Misc) Pin Mux Register 0x01C4 0014 BOOTCFG Boot Configuration 0x01C4 0018 ARM_INTMUX Multiplexing Control for Interrupts 0x01C4 001C EDMA_EVTMUX Multiplexing Control for EDMA Events 0x01C4 0020 DDR_SLEW DDR Slew Rate 0x01C4 0024 UHPICTL UHPI Control 0x01C4 0028 DEVICE_ID Device ID 0x01C4 002C VDAC_CONFIG Video DAC Configuration 0x01C4 0030 TIMER64_CTL Timer64 Input Control 0x01C4 0034 USB_PHY_CTL USB PHY Control 0x01C4 0038 MISC Miscellaneous Control 0x01C4 003C MSTPRI0 Master Priorities Register 0 0x01C4 0040 MSTPRI1 Master Priorities Register 1 0x01C4 0044 VPSS_CLK_CTL VPSS Clock Mux Control 0x01C4 0048 PERI_CLKCTL Peripheral Clock Control 0x01C4 004C DEEPSLEEP DEEPSLEEP Control 0x01C4 0050 - Reserved 0x01C4 0054 DEBOUNCE0 Debounce for GIO0 Input 0x01C4 0058 DEBOUNCE1 Debounce for GIO1 Input 0x01C4 005C DEBOUNCE2 Debounce for GIO2 Input 0x01C4 0060 DEBOUNCE3 Debounce for GIO3 Input 0x01C4 0064 DEBOUNCE4 Debounce for GIO4 Input 0x01C4 0068 DEBOUNCE5 Debounce for GIO5 Input 0x01C4 006C DEBOUNCE6 Debounce for GIO6 Input 0x01C4 0070 DEBOUNCE7 Debounce for GIO7 Input 0x01C4 0074 VTPIOCR VTP IO Control 0x01C4 0078 PUPDCTL0 IO cell pullup/down on/off control #0 0x01C4 007C PUPDCTL1 IO cell pullup/down on/off control #1 0x01C4 0080 HDVICPBT HDVICP Boot Register 0x01C4 0084 PLL1_CONFIG PLL1 Configuration Register 0x01C4 0088 PLL2_CONFIG PLL2 Configuration Register (1) 50 For more details on the system module registers, see the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5). Device Configurations Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 3.2 Boot Modes The ARM can boot from either Asynchronous EMIF (OneNand/NOR) or from ARM ROM, as determined by the setting of the device configuration pins BTSEL[2:0]. The boot selection pins (BTSEL[2:0]) determine the ARM boot process. After reset (POR, warm reset, or max reset), ARM program execution begins in ARM ROM at 0x0000: 8000, except when BTSEL[2:0] = 001, indicating AEMIF (OneNand/NOR) flash boot. 3.2.1 Boot Modes Overview The ARM ROM boot loader (RBL) executes when the BTSEL[2:0] pins indicate a condition other than the normal ARM EMIF boot. • If BTSEL[2:0] = 001 - Asynchronous EMIF boot mode (NOR or OneNAND). This mode is handled by hardware control and does not involve the ROM. In the case of OneNAND, the user is responsible for putting any necessary boot code in the OneNAND's boot page. This code shall configure the AEMIF module for the OneNAND device. After the AEMIF module is configured, booting will continue immediately after the OneNAND’s boot page with the AEMIF module managing pages thereafter. • The RBL supports 7 distinct boot modes: – BTSEL[2:0] = 000 - NAND Boot mode – BTSEL[2:0] = 010 - MMC0/SD0 Boot mode – BTSEL[2:0] = 011 - UART0 Boot mode – BTSEL[2:0] = 100 - USB Boot mode – BTSEL[2:0] = 101 - SPI0 Boot mode – BTSEL[2:0] = 110 - EMAC Boot mode – BTSEL[2:0] = 111 - HPI Boot mode • If NAND boot fails, then MMC/SD mode is tried. • If MMC/SD boot fails, then MMC/SD boot is tried again. • If UART boot fails, then UART boot is tried again. • If USB boot fails, then USB boot is tried again. • If SPI boot fails, then SPI boot is tried again. • If EMAC boot fails, then EMAC boot is tried again. • If HPI boot fails, then HPI boot is tried again. • RBL shall update boot status (PASS/FAIL) in MISC register bits 8 and 9 in System control module. • ARM ROM Boot - NAND Mode – No support for a full firmware boot. Instead, copies a second stage user boot loader (UBL) from NAND flash to ARM internal RAM (AIM) and transfers control to the user-defined UBL. – Support for NAND with page sizes up to 4096 bytes. – Support for magic number error detection and retry (up to 24 times) when loading UBL – Support for up to 30KB UBL (32KB IRAM - ~2KB for RBL stack) – Optional, user-selectable, support for use of DMA and I-cache during RBL execution (i.e.,while loading UBL) – Supports booting from 8-bit NAND devices (16-bit NAND devices are not supported) – Uses/Requires 4-bit HW ECC (NAND devices with ECC requirements ≤ 4 bits per 512 bytes are supported) – Supports NAND flash that requires chip select to stay low during the tR read time Device Configurations Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 51 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 • • • • • • www.ti.com ARM ROM Boot - MMC/SD Mode – No support for a full firmware boot. Instead, copies a second stage User Boot Loader (UBL) from MMC/SD to ARM Internal RAM (AIM) and transfers control to the user software. – Support for MMC/SD Native protocol (MMC/SD SPI protocol is not supported) – Support for descriptor error detection and retry (up to 24 times) when loading UBL – Support for up to 30KB UBL (32KB - ~2KB for RBL stack) – SDHC boot supported by RBL ARM ROM Boot - UART mode – If the state of BTSEL[2:0] pins at reset is 011, then the UART boot mode executes. This mode enables a small program, referred to here as a user boot loader (UBL), to be downloaded to the on-chip ARM internal RAM via the on-chip serial UART and executed. A host program, (referred to as serial host utility program), manages the interaction with RBL and provides a means for operator feedback and input. The UART boot mode execution assumes the following UART settings: 24 MHz reference clock, Time-Out 500 ms, one-shot Serial RS-232 port 115.2 Kbps, 8-bit, no parity, one stop bit Command, data, and checksum format Everything sent from the host to the device UART RBL must be in ASCII format – No support for a full firmware boot. Instead, loads a second stage user boot loader (UBL) via UART to ARM internal RAM (AIM) and transfers control to the user software. – Support for up to 30KB UBL (32KB - ~2KB for RBL stack) ARM ROM Boot – USB Mode – No support for a full firmware boot. Instead, loads a second stage User Boot Loader (UBL) via USB to ARM Internal RAM (AIM) and transfers control to the users software. ARM ROM Boot – SPI Mode – The device will copy UBL to ARM Internal RAM (AIM) via SPI interface from a SPI peripheral like SPI EEPROM. RBL will then transfer control to the UBL. ARM ROM Boot – EMAC Mode – The device will send a boot request packet and the host/server will respond with the boot packets. RBL will wait for all boot packets to arrive and then transfer control to the UBL which is received via boot packets. In EMAC boot mode an I2C EEPROM or SPI EEPROM is necessary for programming EMAC descriptor (including EMAC address for the device) Note: If a magic number is not found in the EEPROM, then the EMAC boot mode will use a default MAC address. In this case, there will be no magic number support. ARM ROM Boot – HPI Mode – The Host will copy UBL to ARM Internal RAM (AIM) via HPI interface and notify the ROM bootloader after copy is finished. RBL will then transfer control to the UBL. The general boot sequence is shown in Figure 3-1. For more information, refer to the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5). 52 Device Configurations Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Reset AEMIF No RBL Boot ? Yes ROM Boot Loader NAND NAND Boot Boot OK ? Yes MMCSD UART Boot MMCSD Boot No Boot OK ? UART No Yes Boot OK ? Yes USB SPI USB Boot No Boot OK ? EMAC SPI Boot No Boot OK ? Yes EMAC Boot No Yes Boot OK ? Yes HPI HPI Boot No Boot OK ? No Yes UBL One NAND/NOR Boot Figure 3-1. Boot Mode Functional Block Diagram Device Configurations Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 53 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 3.3 3.3.1 www.ti.com Device Clocking Overview The device requires one primary reference clock. The reference clock frequency may be generated either by crystal input or by external oscillator. The reference clock is the clock at the pins named MXI1/MXO1, and which drives two separate PLL controllers (PLLC1 and PLLC2). PLLC1 generates the clocks required by the ARM, EDMA, VPSS and the rest of the peripherals. PLL2 generates the clock required by the DDR PHY interface and is also capable of providing clocks to the ARM, USB, Video, or Voice Codec modules as well as a flexible clocking option. Figure 3-2 represents the clocking architecture for the ARM subsystem. For more information on device clocking and the system PLL controller please see the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5). 54 Device Configurations Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Figure 3-2. Clocking Architecture Oscillator (MXI1/MXO1) 19.2/24/27/36 Mhz UART0 OBSCLK SYSCLK5 SYSCLK3 SYSCLK2 SYSCLK1 SYSCLK1 SYSCLK2 SYSCLK3 SYSCLK4 SYSCLK5 SYSCLK6 SYSCLK7 SYSCLK8 SYSCLK9 SYSCLK4 PLLC2 PLLC1 OBSCLK SYSCLKBP SPI4 I2C CLKOUT0 CLKOUT2 PWM0-3 TIMER0-3/ WDT DIV1 PHYCLKSRC RTO MMC/SD0 USB PHY ADC HDVICP McBSP ARMSS MMC/SD1 CLKOUT1 USB MJCP AEMIF Voice Codec DIV2 VPSS UART1 VENC_CLK_SRC VPSS_MUXSEL SPI0-3 EXTCLK VPBE GPIO PCLK VPFE AINTC EMAC DIV3 HPI EDMA DDRCLKS VCLK KEYSCLKS PRTCCLKS MCLK DDR PHY DDR2 EMIF KeyScan PRTCSS 32 Khz Oscillator 3.3.2 PLL Controller Module Two PLL controllers provide clocks to different components of the chip. The PLL controller 1 (PLLC1) provides clocks to most of the components of the chip. The PLL controller 2 (PLLC2) provides clocks to the DDR PHY and is also capable of providing clocks to the ARM, USB, VPSS or the Voice Codec modules instead as well. As • • • a module, the PLL controller provides the following: Glitch-free transitions (on changing PLL settings) Domain clocks alignment Clock gating Device Configurations Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 55 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 • • www.ti.com PLL bypass PLL power down The various clock outputs given by the PLL controller are as follows: • Domain clocks: SYSCLKn • Bypass domain clock: SYSCLKBP • Auxiliary clock from reference clock: AUXCLK Various dividers that can be used are as follows: • Pre-PLL divider: PREDIV • Post-PLL divider: POSTDIV • SYSCLK divider: PLLDIV1, …, PLLDIVn • SYSCLKBP divider: BPDIV The Multiplier values supported are handled by: • PLL multiplier control: PLLM Notes: • PLLCxSYSCLKy is used to denote post divide clock output SYSCLKy from PLL controller x • 'x', which denotes PLL Controller number, can assume values 1 and 2 • 'y', which denotes post divide clock outputs, can assume values 1 to 9 in case of PLLC1 and 1 to 5 in case of PLLC2 The PLL Controllers for PLL1 and PLL2 are described in detail in the TMS320DM36x ARM Subsystem Reference Guide (literature number SPRUFG5). 56 Device Configurations Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 3.3.3 PLLC1 There are two PLLs on the device, and they are independently controlled. PLLC1 generates the frequencies needed for the ARM, Video Processing Sub System (VPSS), MJCP coprocessor block, EDMA, and peripherals. The reference clock for both PLLs is the single crystal input. Both PLLs will be of the same type . It should be noted that the USB2.0 PHY contains a third PLL embedded within it. Table 3-2, and Figure 3-3 describe the customization of PLLC1. • Provides primary system clock • Software configurable • Accepts clock input or internal oscillator input • PLL pre-divider value is programmable • PLL multiplier value is programmable • PLL post-divider value is programmable . See the data manual for all supported configurations. • Only SYSCLK [9:1] are used Table 3-2. PLLC1 Output Clocks PLLC1SYSCLKy Used By PLLC1SYSCLK1 USB reference clock PLLC1SYSCLK2 ARM926EJ-S, HDVICP block clock PLLC1SYSCLK3 MJCP and HDVICP bus interface clock Programmable PLLC1SYSCLK4 Configuration bus clock, peripheral system interfaces, EDMA Programmable PLLC1SYSCLK5 VPSS clock Programmable PLLC1SYSCLK6 (1) PLLDIV Divider (1) VENC clock Programmable (1) (1) Programmable Programmable PLLC1SYSCLK7 DDR 2x clock (1) Programmable PLLC1SYSCLK8 MMC/SD0 clock Programmable PLLC1SYSCLK9 CLKOUT2 Programmable PLLC1OBSCLK CLKOUT0 Programmable PLLC1SYSCLKBP USB reference clock (1) Programmable These clock outputs are multiplexed with other clocks. Device Configurations Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 57 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Figure 3-3. PLLC1 Configuration OSCIN Pre-DIV (Programmable) Post-DIV (Programmable) PLL PLLM (Programmable) PLLEN PLLDIV1* SYSCLK1 (USB Reference Clock) 1 PLLDIV2* SYSCLK2 (ARM926EJ-S, HDVICP Block Clock) 0 PLLDIV3* SYSCLK3 (MJCP and HDVICP Coprocessors Bus Interface Clock) PLLDIV4* SYSCLK4 (Config Bus, Peripheral System Interfaces, EDMA) PLLDIV5* SYSCLK5 (VPSS) PLLDIV6* SYSCLK6 (VENC Clock) PLLDIV7* SYSCLK7 (DDR 2x Clock) PLLDIV8* SYSCLK8 (MMC/SD0 Clock) PLLDIV9* SYSCLK9 (CLKOUT 2) SYSCLKBP ( USB Reference Clock) BPDIV* OSCDIV1* OBSCLK (CLKOUT0) * – Programmable 3.3.4 PLLC2 PLLC2 provides the USB reference clock, ARM926EJ-S, DDR 2x clock, Voice Codec clock and VENC 27MHz, 74.25MHz clock. The PLLC2 functionality can be programmed via the PLLC2 registers. The following list, Table 3-3, and Figure 3-4 describe the customization of PLLC2. The PLLC2 customization includes the following features: • PLLC2 provides DDR PHY, USB reference clock , ARM926EJ-S clock, VENC 27MHz, 74.25Hz clock and Voice codec clock • Software configurable • Accepts clock input or internal oscillator input (the same input as PLLC1) • PLL pre-divider value is programmable • PLL multiplier value is programmable • PLL post-divider value is programmable • Only SYSCLK [5:1] are used Table 3-3. PLLC2 Output Clocks PLLC2SYSCLKy Used by PLLC2SYSCLK1 USB reference clock (1) PLLDIV Divider PLLC2SYSCLK2 ARM926EJ-S, HDVICP block clock PLLC2SYSCLK3 DDR 2x clock PLLC2SYSCLK4 VENC clock PLLC2OBSCLK CLKOUT1 58 (1) Voice Codec clock PLLC2SYSCLK5 (1) Programmable (1) (1) Programmable Programmable Programmable Programmable Programmable These clock outputs are multiplexed with other clocks. Device Configurations Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com OSCIN Pre-DIV (Programmable) PLL Post-DIV* PLLEN PLLDIV1* SYSCLK1 (USB Reference Clock) 1 PLLDIV2* SYSCLK2 (ARM926EJ-S, HDVICP Block Clock) PLLDIV3* SYSCLK3 (DDR 2x Clock) PLLDIV4* SYSCLK4 (Voice Codec Clock) PLLDIV5* SYSCLK5 (VENC Clock) OSCDIV1* OBSCLK (CLKOUT1) 0 PLLM (Programmable) * – Programmable Figure 3-4. PLLC2 Configuration 3.3.5 Processing, Video, EDMA and DDR EMIF Subsystems Maximum Operating Frequencies Table 3-4 shows the maximum speeds supported for each of the major blocks supported on the different speed grade devices. Table 3-4. Processing, Video, EDMA and DDR EMIF Subsystems Maximum Operating Frequencies DM365 - 216 DM365 - 270 DM365 - 300 ARM926 RISC 216 MHz 270 MHz 300 MHz Co-Processor (HDVICP) 173 MHz 216 MHz 270 MHz Co-Processor (MJCP) 173 MHz 216 MHz 270 MHz DDR2 173 MHz 216 MHz 270 MHz mDDR 168 MHz 168 MHz 168 MHz VPSS Logic Block 173 MHz 216 MHz 270 MHz Peripheral System Bus and EDMA 86.5 MHz 108 MHz 135 MHz VPBE-VENC 27 MHz 74.25 MHz 74.25 MHz VPFE (1) 86.5 MHz 108 MHz 120 MHz (1) The pixel clock (PCLK) of VPFE should meet the following conditions: PCLK OSDWIN0 > VIDWIN1 > VIDWIN0 > background color Support for attenuation of the YCbCr values for the REC601 standard. The following restrictions exist in the OSD module. • If the vertical resize filter is enabled for either of the video windows, the maximum horizontal window dimension cannot be greater than 1024 currently. This is due to the limitation in the size of the line memory. • It is not possible to use both of the CLUT ROMs at the same time. However, a window can use RAM while another uses ROM. Table 6-50 lists the On-Screen Display (OSD) registers, their corresponding acronyms, and the device memory locations (offsets). Table 6-50. On-Screen Display (OSD) Registers Offset Acronym Register Description 0h MODE OSD Mode Setup 4h VIDWINMD Video Window Mode Setup 8h OSDWIN0MD Bitmap Window 0 Mode Setup Ch OSDWIN1MD OSD Window 1 Mode Setup (when used as a second OSD window) Ch OSDATRMD OSD Attribute Window Mode Setup (when used as an attribute window) 10h RECTCUR Rectangular Cursor Setup 14h RSV0 Reserved 18h VIDWIN0OFST Video Window 0 Offset 1Ch VIDWIN1OFST Video Window 1 Offset 20h OSDWIN0OFST Bitmap Window 0 Offset 24h OSDWIN1OFST Bitmap Window 1/Attribute Window Offset 28h VIDWINADH Video Window 0/1 Address - High 2Ch VIDWIN0ADL Video Window 0 Address - Low 30h VIDWIN1ADL Video Window 1 Address - Low 34h OSDWINADH BMP Window 0/1 Address - High 38h OSDWIN0ADL BMP Window 0 Address - Low 3Ch OSDWIN1ADL Bitmap Window 1/Attribute Address - Low 40h BASEPX Base Pixel X Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 139 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-50. On-Screen Display (OSD) Registers (continued) 140 Offset Acronym Register Description 44h BASEPY Base Pixel Y 48h VIDWIN0XP Video Window 0 X-Position 4Ch VIDWIN0YP Video Window 0 Y-Position 50h VIDWIN0XL Video Window 0 X-Size 54h VIDWIN0YL Video Window 0 Y-Size 58h VIDWIN1XP Video Window 1 X-Position 5Ch VIDWIN1YP Video Window 1 Y-Position 60h VIDWIN1XL Video Window 1 X-Size 64h VIDWIN1YL Video Window 1 Y-Size 68h OSDWIN0XP Bitmap Window 0 X-Position 6Ch OSDWIN0YP Bitmap Window 0 Y-Position 70h OSDWIN0XL Bitmap Window 0 X-Size 74h OSDWIN0YL Bitmap Window 0 Y-Size 78h OSDWIN1XP Bitmap Window 1 X-Position 7Ch OSDWIN1YP Bitmap Window 1 Y-Position 80h OSDWIN1XL Bitmap Window 1 X-Size 84h OSDWIN1YL Bitmap Window 1 Y-Size 88h CURXP Rectangular Cursor Window X-Position 8Ch CURYP Rectangular Cursor Window Y-Position 90h CURXL Rectangular Cursor Window X-Size 94h CURYL Rectangular Cursor Window Y-Size 98h RSV1 Reserved 9Ch RSV2 Reserved A0h W0BMP01 Window 0 Bitmap Value to Palette Map 0/1 A4h W0BMP23 Window 0 Bitmap Value to Palette Map 2/3 A8h W0BMP45 Window 0 Bitmap Value to Palette Map 4/5 ACh W0BMP67 Window 0 Bitmap Value to Palette Map 6/7 B0h W0BMP89 Window 0 Bitmap Value to Palette Map 8/9 B4h W0BMPAB Window 0 Bitmap Value to Palette Map A/B B8h W0BMPCD Window 0 Bitmap Value to Palette Map C/D BCh W0BMPEF Window 0 Bitmap Value to Palette Map E/F C0h W1BMP01 Window 1 Bitmap Value to Palette Map 0/1 C4h W1BMP23 Window 1 Bitmap Value to Palette Map 2/3 C8h W1BMP45 Window 1 Bitmap Value to Palette Map 4/5 CCh W1BMP67 Window 1 Bitmap Value to Palette Map 6/7 D0h W1BMP89 Window 1 Bitmap Value to Palette Map 8/9 D4h W1BMPAB Window 1 Bitmap Value to Palette Map A/B D8h W1BMPCD Window 1 Bitmap Value to Palette Map C/D DCh W1BMPEF Window 1 Bitmap Value to Palette Map E/F E0h VBNDRY Test Mode E4h EXTMODE Extended Mode E8h MISCCTL Miscellaneous Control ECh CLUTRAMYCB CLUT RAM Y/Cb Setup F0h CLUTRAMCR CLUT RAM Cr/Mapping Setup F4h TRANSPVALL Transparent Color Code - Lower F8h TRANSPVALU Transparent Color Code - Upper FCh TRANSPBMPIDX Transparent Index Code for Bitmaps Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.12.2.2 Video Encoder / Digital LCD Controller (VENC/DLCD) The VENC/DLCD consists of three major blocks: • Video encoder to generate analog video output • Digital LCD controller to generate digital RGB/YCbCr data output and timing signals • Timing generator The video encoder for analog video supports the following features: • Master Clock Input - 27 MHz or 74.25 MHz • SDTV Support – Composite NTSC-M, PAL-B/D/G/H/I – S-Video (Y/C) – Component YPbPr – RGB – CGMS/WSS – Closed Caption • HDTV Support – 525p/625p/720p/1080i – Component YPbPr – RGB – CGMS/WSS • Master/Slave Operation • Three 10-bit D/A Converters The digital LCD controller supports the following features: • Programmable Timing Generator • Various Output Formats – YCbCr 4:2:2 16-bit – YCbCr 4:2:2 8-bit – Parallel RGB 16/18/24-bit – Serial RGB 8-bit • EAV/SAV insertion • Master/Slave Operation Table 6-51 lists the Video Encoder / Digital LCD Controller (VENC/DLCD) registers, their corresponding acronyms, and the device memory locations (offsets). Table 6-51. Video Encoder (VENC) Registers Offset Acronym Register Description 0h VMOD Video Mode 4h VIOCTL Video Interface I/O Control 8h VDPRO Video Data Processing Ch SYNCCTL Sync Control 10h HSPLS Horizontal Sync Pulse Width 14h VSPLS Vertical Sync Pulse Width 18h HINTVL Horizontal Interval 1Ch HSTART Horizontal Valid Data Start Position 20h HVALID Horizontal Data Valid Range 24h VINTVL Vertical Interval 28h VSTART Vertical Valid Data Start Position Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 141 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-51. Video Encoder (VENC) Registers (continued) Offset 142 Acronym Register Description 2Ch VVALID Vertical Data Valid Range 30h HSDLY Horizontal Sync Delay 34h VSDLY Vertical Sync Delay 38h YCCCTL YCbCr Control 3Ch RGBCTL RGB Control 40h RGBCLP RGB Level Clipping 44h LINECTL Line ID Control 48h CULLLINE Culling Line Control 4Ch LCDOUT LCD Output Signal Control 50h BRT0 Brightness Start Position Signal Control 54h BRT1 Brightness Width Signal Control 58h ACCTL LCD_AC Signal Control 5Ch PWM0 PWM Output Period 60h PWM1 PWM Output Pulse Width 64h DCLKCTL DCLK Control 68h DCLKPTN0 DCLK Pattern 0 6Ch DCLKPTN1 DCLK Pattern 1 70h DCLKPTN2 DCLK Pattern 2 74h DCLKPTN3 DCLK Pattern 3 78h DCLKPTN0A DCLK Auxiliary Pattern 0 7Ch DCLKPTN1A DCLK Auxiliary Pattern 1 80h DCLKPTN2A DCLK Auxiliary Pattern 2 84h DCLKPTN3A DCLK Auxiliary Pattern 3 88h DCLKHSTT Horizontal DCLK Mask Start Position 8Ch DCLKHSTTA Horizontal Auxiliary DCLK Mask Start Position 90h DCLKHVLD Horizontal DCLK Mask Range 94h DCLKVSTT Vertical DCLK Mask Start Position 98h DCLKVVLD Vertical DCLK Mask Range 9Ch CAPCTL Closed Caption Control A0h CAPDO Closed Caption Odd Field Data A4h CAPDE Closed Caption Even Field Data A8h ATR0 Video Attribute Data 0 ACh ATR1 Video Attribute Data 1 B0h ATR2 Video Attribute Data 2 B4h RSV0 Reserved 0 B8h VSTAT Video Status BCh RAMADR GCP/FRC Table RAM Address C0h RAMPORT GCP/FRC Table RAM Data Port C4h DACTST DAC Test C8h YCOLVL YOUT and COUT Levels CCh SCPROG Sub-Carrier Programming D0h RSV1 Reserved 1 D4h RSV2 Reserved 2 D8h RSV3 Reserved 3 DCh CVBS Composite Mode E0h CMPNT Component Mode E4h ETMG0 CVBS Timing Control 0 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-51. Video Encoder (VENC) Registers (continued) Offset Acronym Register Description E8h ETMG1 CVBS Timing Control 1 ECh ETMG2 CVBS Timing Control 2 F0h ETMG3 CVBS Timing Control 3 F4h DACSEL DAC Output Select 100h ARGBX0 Analog RGB Matrix 0 104h ARGBX1 Analog RGB Matrix 1 108h ARGBX2 Analog RGB Matrix 2 10Ch ARGBX3 Analog RGB Matrix 3 110h ARGBX4 Analog RGB Matrix 4 114h DRGBX0 Digital RGB Matrix 0 118h DRGBX1 Digital RGB Matrix 1 11Ch DRGBX2 Digital RGB Matrix 2 120h DRGBX3 Digital RGB Matrix 3 124h DRGBX4 Digital RGB Matrix 4 128h VSTARTA Vertical Data Valid Start Position For Even Field 12Ch OSDCLK0 OSD Clock Control 0 130h OSDCLK1 OSD Clock Control 1 134h HVLDCL0 Horizontal Valid Culling Control 0 138h HVLDCL1 Horizontal Valid Culling Control 1 13Ch OSDHADV OSD Horizontal Sync Advance 140h CLKCTL Clock Control 144h GAMCTL Enable Gamma Correction 148h VVALIDA Vertical Data Valid Area For Even Field 14Ch BATR0 Video Attribute 0 For Type B Packet 150h BATR1 Video Attribute 1 For Type B Packet 154h BATR2 Video Attribute 2 For Type B Packet 158h BATR3 Video Attribute 3 For Type B Packet 15Ch BATR4 Video Attribute 4 For Type B Packet 160h BATR5 Video Attribute 5 For Type B Packet 164h BATR6 Video Attribute 6 For Type B Packet 168h BATR7 Video Attribute 7 For Type B Packet 16Ch BATR8 Video Attribute 8 For Type B Packet 170h DACAMP Gain and Offset 6.12.2.3 VPBE Electrical Data/Timing Table 6-52. Timing Requirements for VPBE CLK Inputs (see Figure 6-35) DEVICE NO. (1) MIN MAX 13.33 160 UNIT 1 tc(PCLK) Cycle time, PCLK (1) 2 tw(PCLKH) Pulse duration, PCLK high 5.7 3 tw(PCLKL) Pulse duration, PCLK low 5.7 4 tt(PCLK) Transition time, PCLK 5 tc(EXTCLK) Cycle time, EXTCLK 6 tw(EXTCLKH) Pulse duration, EXTCLK high 5.7 ns 7 tw(EXTCLKL) Pulse duration, EXTCLK low 5.7 ns 13.33 ns ns ns 3 ns 160 ns For timing specifications relating to PCLK see Table 6-45, Timing Requirements for VPFE PCLK Master/Slave Mode. Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 143 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-52. Timing Requirements for VPBE CLK Inputs (see Figure 6-35) (continued) DEVICE NO. MIN 8 tt(EXTCLK) UNIT MAX Transition time, EXTCLK 3 ns 3 1 2 PCLK 4 6 7 4 5 EXTCLK 8 8 Figure 6-35. VPBE PCLK and EXTCLK Timing Table 6-53. Timing Requirements for VPBE Control Input With Respect to PCLK and EXTCLK (1) Figure 6-36) DEVICE NO. MIN tsu(VCTLV- 9 VCLKIN) 10 th(VCLKIN- Setup time, VCTL valid before VCLKIN edge Hold time, VCTL valid after VCLKIN edge VCTLV) (1) (2) (3) Positive Edge 4 Negative Edge 3 Positive Edge 1 Negative Edge 2 MAX (see UNI T ns ns The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced. VCTL = HSYNC, VSYNC, and FIELD VCLKIN = PCLK or EXTCLK. Positive and Negative Edge apply to PCLK only; EXTCLK does not support Negative Edge clocking. (2) (3) VCLKIN (A) (Positive Edge Clocking) VCLKIN (A) (Negative Edge Clocking) 10 9 VCTL(B) A. VCLKIN = PCLK or EXTCLK. Note Positive and Negative edge apply for PCLK only, EXTCLK does not support negative edge clocking. B. VCTL = HSYNC, VSYNC, and FIELD Figure 6-36. VPBE Input Timing With Respect to PCLK and EXTCLK 144 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-54. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to PCLK and EXTCLK (1) (2) (3) (see Figure 6-37) NO. 11 DEVICE PARAMETER td(VCLKIN- MIN Delay time, VCLKIN edge to VCTL valid VCTLV) 12 td(VCLKIN- MAX Positive Edge 15 Negative Edge 16 Delay time, VCLKIN edge to VCTL invalid 2 UNIT ns ns VCTLIV) 13 td(VCLKIN- VCLKIN = EXTCLK Delay time, VCLKIN edge to VDATA valid 14 td(VCLKIN- 15 VCLKIN = PCLK VDATAV) 17.5 Delay time, VCLKIN edge to VDATA invalid 2 ns ns VDATAIV) (1) (2) (3) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced. VCLKIN = PCLK or EXTCLK. Positive and Negative Edge apply to PCLK only; EXTCLK does not support Negative Edge clocking. VCTL = HSYNC, VSYNC, FIELD, and LCD_OE. VCLKIN (A) (Positive Edge Clocking) VCLKIN (A) (Negative Edge Clocking) 11 12 13 14 VCTL(B) VDATA (C) A. VCLKIN = PCLK or EXTCLK. Note Positive and Negative edge apply for PCLK only, EXTCLK does not support negative edge clocking. B. VCTL = HSYNC, VSYNC, FIELD, and LCD_OE C. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0] Figure 6-37. VPBE Control and Data Output With Respect to PCLK and EXTCLK Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 145 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-55. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to VCLK (1) (2) (3)(see Figure 6-38) NO. DEVICE PARAMETER MIN MAX 13.33 160 17 tc(VCLK) Cycle time, VCLK 18 tw(VCLKH) Pulse duration, VCLK high 5.7 19 tw(VCLKL) Pulse duration, VCLK low 5.7 20 tt(VCLK) Transition time, VCLK 21 td(VCLKINH-VCLKH) Delay time, VCLKIN high to VCLK high 3 22 td(VCLKINL-VCLKL) Delay time, VCLKIN low to VCLK low 3 23 td(VCLK-VCTLV) Delay time, VCLK edge to VCTL valid 24 td(VCLK-VCTLIV) Delay time, VCLK edge to VCTL invalid 25 td(VCLK-VDATAV) Delay time, VCLK edge to VDATA valid 26 td(VCLK-VDATAIV) Delay time, VCLK edge to VDATA invalid (1) (2) (3) UNIT ns ns ns 3 ns 16 ns 16 ns 1.5 ns -1.5 ns 1.5 -1.5 ns ns The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced. VCLKIN = PCLK or EXTCLK. Positive and Negative edge apply for PCLK only, EXTCLK does not support negative edge clocking. For timing specifications relating to PCLK, see Table 6-45, Timing Requirements for VPFE PCLK Master/Slave Mode. VCTL= HSYNC, VSYNC, FIELD and LCD_OE. VCLKIN (A) 21 VCLK 19 17 22 18 (Positive Edge Clocking) VCLK (Negative Edge Clocking) 23 24 25 26 20 20 VCTL(B) VDATA (C) A. VCLKIN = PCLK or EXTCLK. Note Positive and Negative edge apply for PCLK only, EXTCLK does not support negative edge clocking. B. VCTL = HSYNC, VSYNC, FIELD, and LCD_OE C. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0] Figure 6-38. VPBE Control and Data Output Timing With Respect to VCLK 6.12.2.4 High-Definition (HD) DACs and Video Buffer Electrical Data/Timing Three DACs and a video buffer are available on the device. 6.12.2.4.1 HD DACs-Only Option In the HD DACs-only configuration, the internal video buffer is not used and an external video buffer is attached to the DACs. Another solution is to use a Video Amplifier, such as the Texas Instruments' THS7303 which provides a complete solution to the typical output circuit shown in Figure 6-39. Note: HD display mode resolutions are not supported on ARM 216MHz clock rate devices. 146 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com DAC CH-A DAC CH-B DAC CH-C Low-Pass Filter COMPY ~RLOAD = 75 Ω Low-Pass Filter COMPPB ~RLOAD = 75 Ω Low-Pass Filter COMPPR ~RLOAD = 75 Ω Amplifier Gain = 5.6 V/V 75 Ω TV Monitor 75 Ω Amplifier Gain = 5.6 V/V 75 Ω 75 Ω Amplifier Gain = 5.6 V/V 75 Ω 75 Ω IREF RBIAS VREF IDACOUT DC = 0.5 V VFB CBG 0.1 µF TVOUT A. B. C. D. E. RBIAS = 2400Ω. VREF = 0.5V (from external supply). IDACOUT must be connected to Vss or left open for proper device configuration. VFB must be connected to Vss or left open for proper device configuration. TVOUT must be connected to Vss or left open for proper device configuration. Figure 6-39. HD Video DAC Application Example 6.12.2.4.2 DAC With Video Buffer Option In a DAC plus video buffer configuration, one of the DACs may be used along with the video buffer for standard definition TVOUT mode. In the DAC plus video buffer configuration, the DAC and internal video buffer are both used, and a TV cable may be attached directly to the output of the video buffer.Figure 6-40 shows an example of the DAC Plus Video Buffer Option circuit configuration. Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 147 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com COMPY COMPPB DAC CHC COMPPR IREF RBIAS VREF DC = 0.5 V IDACOUT Video Buffer CBG 0.1 µF R1 VFB R2 TV monitor TVOUT RL Figure 6-40. SD Video Buffer Application Example 148 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.13 USB 2.0 The USB2.0 peripheral supports the following features: • USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s) • USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s) • All transfer modes (control, bulk, interrupt, and isochronous) • Four Transmit (TX) and four Receive (RX) endpoints in addition to endpoint 0 • FIFO RAM – 4K bytes shared by all endpoints. – Programmable FIFO size • Includes a DMA sub-module that supports four TX and four RX channels of CPPI 3.0 DMAs • RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB • USB OTG extensions, i.e. session request protocol (SRP) and host negotiation protocol (HNP) The USB2.0 peripheral does not support the following features: • On-chip charge pump • High bandwidth ISO mode is not supported (triple buffering) • RNDIS mode acceleration for USB sizes that are not multiples of 64 bytes • Endpoint max USB packet sizes that do not conform to the USB 2.0 spec (for FS/LS: 8, 16, 32, 64, and 1023 are defined; for HS: 64, 128, 512, and 1024 are defined) 6.13.1 USB Peripheral Register Description(s) Table 6-56 lists the USB registers, their corresponding acronyms, and the device memory locations (offsets). Table 6-56. Universal Serial Bus (USB) Registers Offset Acronym Register Description 4h CTRLR Control Register 8h STATR Status Register 10h RNDISR RNDIS Register 14h AUTOREQ Autorequest Register 20h INTSRCR USB Interrupt Source Register 24h INTSETR USB Interrupt Source Set Register 28h INTCLRR USB Interrupt Source Clear Register 2Ch INTMSKR USB Interrupt Mask Register 30h INTMSKSETR USB Interrupt Mask Set Register 34h INTMSKCLRR USB Interrupt Mask Clear Register 38h INTMASKEDR USB Interrupt Source Masked Register 3Ch EOIR USB End of Interrupt Register 40h INTVECTR USB Interrupt Vector Register 80h TCPPICR Transmit CPPI Control Register 84h TCPPITDR Transmit CPPI Teardown Register 88h TCPPIEOIR Transmit CPPI DMA Controller End of Interrupt Register 8Ch Reserved - 90h TCPPIMSKSR Transmit CPPI Masked Status Register 94h TCPPIRAWSR Transmit CPPI Raw Status Register 98h TCPPIIENSETR Transmit CPPI Interrupt Enable Set Register 9Ch TCPPIIENCLRR Transmit CPPI Interrupt Enable Clear Register C0h RCPPICR Receive CPPI Control Register D0h RCPPIMSKSR Receive CPPI Masked Status Register Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 149 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-56. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description D4h RCPPIRAWSR Receive CPPI Raw Status Register D8h RCPPIENSETR Receive CPPI Interrupt Enable Set Register DCh RCPPIIENCLRR Receive CPPI Interrupt Enable Clear Register E0h RBUFCNT0 Receive Buffer Count 0 Register E4h RBUFCNT1 Receive Buffer Count 1 Register E8h RBUFCNT2 Receive Buffer Count 2 Register ECh RBUFCNT3 Receive Buffer Count 3 Register 100h TCPPIDMASTATEW0 Transmit CPPI DMA State Word 0 104h TCPPIDMASTATEW1 Transmit CPPI DMA State Word 1 108h TCPPIDMASTATEW2 Transmit CPPI DMA State Word 2 10Ch TCPPIDMASTATEW3 Transmit CPPI DMA State Word 3 110h TCPPIDMASTATEW4 Transmit CPPI DMA State Word 4 114h TCPPIDMASTATEW5 Transmit CPPI DMA State Word 5 11Ch TCPPICOMPPTR Transmit CPPI Completion Pointer 120h RCPPIDMASTATEW0 Receive CPPI DMA State Word 0 124h RCPPIDMASTATEW1 Receive CPPI DMA State Word 1 Transmit/Receive CPPI Channel 0 State Block 128h RCPPIDMASTATEW2 Receive CPPI DMA State Word 2 12Ch RCPPIDMASTATEW3 Receive CPPI DMA State Word 3 130h RCPPIDMASTATEW4 Receive CPPI DMA State Word 4 134h RCPPIDMASTATEW5 Receive CPPI DMA State Word 5 138h RCPPIDMASTATEW6 Receive CPPI DMA State Word 6 13Ch RCPPICOMPPTR Receive CPPI Completion Pointer Transmit/Receive CPPI Channel 1 State Block 140h TCPPIDMASTATEW0 Transmit CPPI DMA State Word 0 144h TCPPIDMASTATEW1 Transmit CPPI DMA State Word 1 148h TCPPIDMASTATEW2 Transmit CPPI DMA State Word 2 14Ch TCPPIDMASTATEW3 Transmit CPPI DMA State Word 3 150h TCPPIDMASTATEW4 Transmit CPPI DMA State Word 4 154h TCPPIDMASTATEW5 Transmit CPPI DMA State Word 5 15Ch TCPPICOMPPTR Transmit CPPI Completion Pointer 160h RCPPIDMASTATEW0 Receive CPPI DMA State Word 0 164h RCPPIDMASTATEW1 Receive CPPI DMA State Word 1 168h RCPPIDMASTATEW2 Receive CPPI DMA State Word 2 16Ch RCPPIDMASTATEW3 Receive CPPI DMA State Word 3 170h RCPPIDMASTATEW4 Receive CPPI DMA State Word 4 174h RCPPIDMASTATEW5 Receive CPPI DMA State Word 5 178h RCPPIDMASTATEW6 Receive CPPI DMA State Word 6 17Ch RCPPICOMPPTR Receive CPPI Completion Pointer Transmit/Receive CPPI Channel 2 State Block 150 180h TCPPIDMASTATEW0 Transmit CPPI DMA State Word 0 184h TCPPIDMASTATEW1 Transmit CPPI DMA State Word 1 188h TCPPIDMASTATEW2 Transmit CPPI DMA State Word 2 18Ch TCPPIDMASTATEW3 Transmit CPPI DMA State Word 3 190h TCPPIDMASTATEW4 Transmit CPPI DMA State Word 4 194h TCPPIDMASTATEW5 Transmit CPPI DMA State Word 5 19Ch TCPPICOMPPTR Transmit CPPI Completion Pointer Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-56. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description 1A0h RCPPIDMASTATEW0 Receive CPPI DMA State Word 0 1A4h RCPPIDMASTATEW1 Receive CPPI DMA State Word 1 1A8h RCPPIDMASTATEW2 Receive CPPI DMA State Word 2 1ACh RCPPIDMASTATEW3 Receive CPPI DMA State Word 3 1B0h RCPPIDMASTATEW4 Receive CPPI DMA State Word 4 1B4h RCPPIDMASTATEW5 Receive CPPI DMA State Word 5 1B8h RCPPIDMASTATEW6 Receive CPPI DMA State Word 6 1BCh RCPPICOMPPTR Receive CPPI Completion Pointer Transmit/Receive CPPI Channel 3 State Block 1C0h TCPPIDMASTATEW0 Transmit CPPI DMA State Word 0 1C4h TCPPIDMASTATEW1 Transmit CPPI DMA State Word 1 1C8h TCPPIDMASTATEW2 Transmit CPPI DMA State Word 2 1CCh TCPPIDMASTATEW3 Transmit CPPI DMA State Word 3 1D0h TCPPIDMASTATEW4 Transmit CPPI DMA State Word 4 1D4h TCPPIDMASTATEW5 Transmit CPPI DMA State Word 5 1DCh TCPPICOMPPTR Transmit CPPI Completion Pointer 1E0h RCPPIDMASTATEW0 Receive CPPI DMA State Word 0 1E4h RCPPIDMASTATEW1 Receive CPPI DMA State Word 1 1E8h RCPPIDMASTATEW2 Receive CPPI DMA State Word 2 1ECh RCPPIDMASTATEW3 Receive CPPI DMA State Word 3 1F0h RCPPIDMASTATEW4 Receive CPPI DMA State Word 4 1F4h RCPPIDMASTATEW5 Receive CPPI DMA State Word 5 1F8h RCPPIDMASTATEW6 Receive CPPI DMA State Word 6 1FCh RCPPICOMPPTR Receive CPPI Completion Pointer 400h FADDR Function Address Register 401h POWER Power Management Register 402h INTRTX Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4 404h INTRRX Interrupt Register for Receive Endpoints 1 to 4 406h INTRTXE Interrupt enable register for INTRTX 408h INTRRXE Interrupt Enable Register for INTRRX 40Ah INTRUSB Interrupt Register for Common USB Interrupts 40Bh INTRUSBE Interrupt Enable Register for INTRUSB 40Ch FRAME Frame Number Register 40Eh INDEX Index Register for Selecting the Endpoint Status and Control Registers 40Fh TESTMODE Register to Enable the USB 2.0 Test Modes Common USB Registers Indexed Registers These registers operate on the endpoint selected by the INDEX register 410h TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint. (Index register set to select Endpoints 1-4) 412h PERI_CSR0 Control Status Register for Endpoint 0 in Peripheral Mode. (Index register set to select Endpoint 0) HOST_CSR0 Control Status Register for Endpoint 0 in Host Mode. (Index register set to select Endpoint 0) PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint. (Index register set to select Endpoints 1-4) HOST_TXCSR Control Status Register for Host Transmit Endpoint. (Index register set to select Endpoints 1-4) Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 151 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-56. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description 414h RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint. (Index register set to select Endpoints 1-4) 416h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint. (Index register set to select Endpoints 1-4) HOST_RXCSR Control Status Register for Host Receive Endpoint. (Index register set to select Endpoints 1-4) COUNT0 Number of Received Bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) RXCOUNT Number of Bytes in Host Receive Endpoint FIFO. (Index register set to select Endpoints 1- 4) HOST_TYPE0 Defines the speed of Endpoint 0 HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. (Index register set to select Endpoints 1-4) HOST_NAKLIMIT0 Sets the NAK response timeout on Endpoint 0. (Index register set to select Endpoint 0) HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. (Index register set to select Endpoints 1-4) 41Ch HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. (Index register set to select Endpoints 1-4) 41Dh HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. (Index register set to select Endpoints 1-4) 41Fh CONFIGDATA Returns details of core configuration. (Index register set to select Endpoint 0) 420h FIFO0 Transmit and Receive FIFO Register for Endpoint 0 424h FIFO1 Transmit and Receive FIFO Register for Endpoint 1 428h FIFO2 Transmit and Receive FIFO Register for Endpoint 2 42Ch FIFO3 Transmit and Receive FIFO Register for Endpoint 3 430h FIFO4 Transmit and Receive FIFO Register for Endpoint 4 418h 41Ah 41Bh FIFOn OTG Device Control 460h DEVCTL OTG Device Control Register 462h TXFIFOSZ Transmit Endpoint FIFO Size (Index register set to select Endpoints 1-4) 463h RXFIFOSZ Receive Endpoint FIFO Size (Index register set to select Endpoints 1-4) 464h TXFIFOADDR Transmit Endpoint FIFO Address (Index register set to select Endpoints 1-4) 466h RXFIFOADDR Receive Endpoint FIFO Address (Index register set to select Endpoints 1-4) Dynamic FIFO Control Target Endpoint 0 Control Registers, Valid Only in Host Mode 152 480h TXFUNCADDR Address of the target function that has to be accessed through the associated Transmit Endpoint. 482h TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 483h TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 484h RXFUNCADDR Address of the target function that has to be accessed through the associated Receive Endpoint. Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-56. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description 486h RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 487h RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 488h TXFUNCADDR Address of the target function that has to be accessed through the associated Transmit Endpoint. 48Ah TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 48Bh TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 48Ch RXFUNCADDR Address of the target function that has to be accessed through the associated Receive Endpoint. 48Eh RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 48Fh RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 490h TXFUNCADDR Address of the target function that has to be accessed through the associated Transmit Endpoint. 492h TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 493h TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 494h RXFUNCADDR Address of the target function that has to be accessed through the associated Receive Endpoint. 496h RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 497h RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. Target Endpoint 1 Control Registers, Valid Only in Host Mode Target Endpoint 2 Control Registers, Valid Only in Host Mode Target Endpoint 3 Control Registers, Valid Only in Host Mode 498h TXFUNCADDR Address of the target function that has to be accessed through the associated Transmit Endpoint. 49Ah TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 49Bh TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 49Ch RXFUNCADDR Address of the target function that has to be accessed through the associated Receive Endpoint. 49Eh RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 49Fh RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. Target Endpoint 4 Control Registers, Valid Only in Host Mode Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 153 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-56. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description 4A0h TXFUNCADDR Address of the target function that has to be accessed through the associated Transmit Endpoint. 4A2h TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 4A3h TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 4A4h RXFUNCADDR Address of the target function that has to be accessed through the associated Receive Endpoint. 4A6h RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 4A7h RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 502h PERI_CSR0 Control Status Register for Endpoint 0 in Peripheral Mode HOST_CSR0 Control Status Register for Endpoint 0 in Host Mode Control and Status Register for Endpoint 0 508h COUNT0 Number of Received Bytes in Endpoint 0 FIFO 50Ah HOST_TYPE0 Defines the Speed of Endpoint 0 50Bh HOST_NAKLIMIT0 Sets the NAK Response Timeout on Endpoint 0 50Fh CONFIGDATA Returns details of core configuration. Control and Status Register for Endpoint 1 510h TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint 512h PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode) HOST_TXCSR Control Status Register for Host Transmit Endpoint (host mode) 514h RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint 516h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode) HOST_RXCSR Control Status Register for Host Receive Endpoint (host mode) 518h RXCOUNT Number of Bytes in Host Receive endpoint FIFO 51Ah HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. 51Bh HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. 51Ch HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. 51Dh HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. Control and Status Register for Endpoint 2 154 520h TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint 522h PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode) HOST_TXCSR Control Status Register for Host Transmit Endpoint (host mode) 524h RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint 526h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode) HOST_RXCSR Control Status Register for Host Receive Endpoint (host mode) Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-56. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description 528h RXCOUNT Number of Bytes in Host Receive endpoint FIFO 52Ah HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. 52Bh HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. 52Ch HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. 52Dh HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. 530h TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint 532h PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode) HOST_TXCSR Control Status Register for Host Transmit Endpoint (host mode) 534h RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint 536h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode) HOST_RXCSR Control Status Register for Host Receive Endpoint (host mode) Control and Status Register for Endpoint 3 538h RXCOUNT Number of Bytes in Host Receive endpoint FIFO 53Ah HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. 53Bh HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. 53Ch HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. 53Dh HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. 540h TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint 542h PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode) HOST_TXCSR Control Status Register for Host Transmit Endpoint (host mode) 544h RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint 546h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode) HOST_RXCSR Control Status Register for Host Receive Endpoint (host mode) Control and Status Register for Endpoint 4 548h RXCOUNT Number of Bytes in Host Receive endpoint FIFO 54Ah HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. 54Bh HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. 54Ch HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. 54Dh HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 155 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.13.2 USB2.0 Electrical Data/Timing Table 6-57. Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see Figure 6-41) DEVICE NO. LOW SPEED 1.5 Mbps PARAMETER HIGH SPEED (1) 480 Mbps FULL SPEED 12 Mbps UNIT MIN MAX MIN MAX MIN MAX 1 tr(D) Rise time, USB_DP and USB_DM signals (2) 75 300 4 20 0.5 20 ns 2 tf(D) Fall time, USB_DP and USB_DM signals (2) 75 300 4 20 0.5 20 ns 3 tfrfm Rise/Fall time, matching (3) 80 125 90 111.11 - - % 1.3 2 1.3 2 - - (2) 4 VCRS Output signal cross-over voltage 5 tjr(source)NT Source (Host) Driver jitter, next transition tjr(FUNC)NT Function Driver jitter, next transition 6 tjr(source)PT Source (Host) Driver jitter, paired transition tjr(FUNC)PT Function Driver jitter, paired transition 7 tw(EOPT) Pulse duration, EOP transmitter 8 tw(EOPR) Pulse duration, EOP receiver 9 t(DRATE) Data Rate 10 ZDRV Driver Output Resistance (1) (2) (3) (4) (4) 1250 2 ns 25 2 ns 1 1 ns 10 1 1500 670 160 175 82 1.5 - V 2 - ns - 12 28 - 49.5 40.5 ns ns 480 Mb/s 49.5 Ω For more detailed specification information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Low Speed: CL = 200 pF, Full Speed: CL = 50 pF, High Speed: CL = 50 pF tfrfm = (tr/tf) x 100. [Excluding the first transaction from the Idle state.] tjr = tpx(1) - tpx(0) USB_DM VCRS USB_DP tper − tjr 90% VOH 10% VOL tr tf Figure 6-41. USB2.0 Integrated Transceiver Interface Timing 156 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.14 Universal Asynchronous Receiver/Transmitter (UART) The UART module performs serial-to-parallel conversion on data received from a peripheral device or modem, and parallel-to-serial conversion on data received from the CPU. Each UART also includes a programmable baud rate generator capable of dividing the module's reference clock by divisors from 1 to 65,535 to produce a 16 x clock driving the internal logic. The UART modules support the following features: • Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates • 16-byte storage space for both the transmitter and receiver FIFOs • Unique interrupts, one for each UART • Unique EDMA events, both received and transmitted data for each UART • 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA • Programmable auto-rts and auto-cts for autoflow control (supported on UART1) • Programmable serial data formats – 5, 6, 7, or 8-bit characters – Even, odd, or no parity bit generation and detection – 1, 1.5, or 2 stop bit generation • False start bit detection • Line break generation and detection • Internal diagnostic capabilities – Loopback controls for communications link fault isolation – Break, parity, overrun, and framing error simulation • Modem control functions: CTS, RTS (supported on UART1) 6.14.1 UART Peripheral Register Description(s) Table 6-58 lists the UART registers, their corresponding acronyms, and the device memory locations (offsets). Table 6-58. UART Registers OFFSET ACRONYM REGISTER DESCRIPTION 0h RBR Receiver Buffer Register (read only) 0h THR Transmitter Holding Register (write only) 4h IER Interrupt Enable Register 8h IIR Interrupt Identification Register (read only) 8h FCR FIFO Control Register (write only) Ch LCR Line Control Register 10h MCR Modem Control Register 14h LSR Line Status Register 20h DLL Divisor LSB Latch 24h DLH Divisor MSB Latch 28h PID Peripheral Identification Register 30h PWREMU_MGMT Power and Emulation Management Register 34h MDR Mode Definition Register 6.14.2 UART Electrical Data/Timing Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 157 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-59. Timing Requirements for UARTx Receive (see Figure 6-42) (1) DEVICE NO. (1) MIN MAX UNIT 4 tw(URXDB) Pulse duration, receive data bit (RXDn) .96U 1.05U ns 5 tw(URXSB) Pulse duration, receive start bit .96U 1.05U ns U = UART baud time = 1/programmed baud rate. Table 6-60. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see Figure 6-42) (1) NO. (1) DEVICE PARAMETER MIN MAX UART0 Maximum programmable baud rate 5 UART1 Maximum programmable baud rate 5 UNIT 1 f(baud) MHz 2 tw(UTXDB) Pulse duration, transmit data bit (TXDn) U-2 U+2 ns 3 tw(UTXSB) Pulse duration, transmit start bit U-2 U+2 ns U = UART baud time = 1/programmed baud rate. 3 2 UART_TXDn Start Bit Data Bits 5 4 UART_RXDn Start Bit Data Bits Figure 6-42. UART Transmit/Receive Timing 158 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.15 Serial Port Interface (SPI) The SPI module provides a programmable length shift register which allows serial communication with other SPI devices through a 3 or 4 wire interface (Clock, Data In, Data Out, and Chip-select). The SPI supports the following features: • Master and Slave mode operation is supported on all SPI ports (master mode means that the device provides the serial clock) • 2 chip selects for interfacing to multiple slave SPI devices. • 3 or 4 wire interface (Clock, Data In, Data Out, and Enable) • Unique interrupt for each SPI port (except SPI4) • Separate EDMA events for SPI Receive and Transmit for each SPI port (except SPI4) • 16-bit shift register • Receive buffer register • Programmable character length (2 to 16 bits) • Programmable SPI clock frequency range • 8-bit clock prescaler • Programmable clock phase (delay or no delay) • Programmable clock polarity Note: SPI4 slave mode does not support Chip-select input, only supports 3-wire interface. The SPI modules do not support the following features: • GPIO mode. GPIO functionality is supported by the GIO modules for those SPI pins that are multiplexed with GPIO signals. 6.15.1 SPI Peripheral Register Description(s) Table 6-61 lists the SPI registers, their corresponding acronyms, and the device memory locations (offsets). These offsets apply to all device SPI modules. Table 6-61. SPI Registers OFFSET ACRONYM REGISTER DESCRIPTION 00h SPIGCR0 SPI global control register 0 04h SPIGCR1 SPI global control register 1 08h SPIINT SPI interrupt register 0Ch SPILVL SPI interrupt level register 10h SPIFLG SPI flag register 14h SPIPC0 SPI pin control register 18h - Reserved 1Ch SPIPC2 SPI pin control register 2 20h - 38h - Reserved 3Ch SPIDAT1 SPI shift register 40h SPIBUF SPI buffer register 44h SPIEMU SPI emulation register 48h SPIDELAY SPI delay register 4Ch SPIDEF SPI default chip select register SPIFMT0 SPI data format register 0 60h INTVECT0 SPI interrupt vector register 0 64h INTVECT1 SPI interrupt vector register 1 50h-5Ch Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 159 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.15.2 SPI Electrical Data/Timing Master Mode — General Table 6-62. General Switching Characteristics in Master Mode (1) NO. PARAMETER MIN MAX UNIT greater of 2P or 25 256P ns 1 tc(CLK) Cycle time, SPI_SCLK 2 tw(CLKH) Pulse width, SPI_SCLK high .5(tc(CLK)) 1.25 ns 3 tw(CLKL) Pulse width, SPI_SCLK low .5(tc(CLK)) 1.25 ns Output setup time, SPI_SIMO valid (1st bit) before initial SPI_SCLK rising edge, 3-/4-pin mode, polarity = 0, phase = 0 4 tosu(SIMO-CLK) 6.5 Output setup time, SPI_SIMO valid (1st bit) before initial SPI_SCLK rising edge, 3-/4-pin mode, .5tc(CLK) + 6.5 polarity = 0, phase = 1 Output setup time, SPI_SIMO valid (1st bit) before initial SPI_SCLK falling edge, 3-/4-pin mode, polarity = 1, phase = 0 ns 6.5 Output setup time, SPI_SIMO valid (1st bit) before initial SPI_SCLK falling edge, 3-/4-pin mode, .5tc(CLK) + 6.5 polarity = 1, phase = 1 5 6 (1) 160 td(CLK-SIMO) toh(CLK-SIMO) Delay time, SPI_SCLK transmit rising edge to SPI_SIMO output valid (subsequent bit driven), 3-/4-pin mode, polarity = 0, phase = 0 -3 6 Delay time, SPI_SCLK transmit falling edge to SPI_SIMO output valid (subsequent bit driven), 3-/4-pin mode, polarity = 0, phase = 1 -3 6 Delay time, SPI_SCLK transmit falling edge to SPI_SIMO output valid (subsequent bit driven), 3-/4-pin mode, polarity = 1, phase = 0 -3 6 Delay time, SPI_SCLK transmit rising edge to SPI_SIMO output valid (subsequent bit driven), 3-/4-pin mode, polarity = 1, phase = 1 -3 6 ns Output hold time, SPI_SIMO valid (except final bit) after receive falling edge of SPI_SCLK, 3-/4-pin mode, polarity = 0, phase = 0 9.5 Output hold time, SPI_SIMO valid (except final bit) after receive rising edge of SPI_SCLK, 3-/4-pin mode, polarity = 0, phase = 1 9.5 Output hold time, SPI_SIMO valid (except final bit) after receive rising edge of SPI_SCLK, 3-/4-pin mode, polarity = 1, phase = 0 9.5 Output hold time, SPI_SIMO valid (except final bit) after receive falling edge of SPI_SCLK, 3-/4-pin mode, polarity = 1, phase = 1 9.5 ns T = period of SPI_SCLK; For SPI0, SPI1, SPI2, and SPI3, P = period of SPI core clock (PLL1SYSCLK4). For SPI4, P = period of SPI core clock (OSCIN). Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-63. General Input Timing Requirements in Master Mode NO. 7 8 MIN tsu(SOMI-CLK) th(CLK-SOMI) Setup time, SPI_SOMI valid before receive falling edge of SPI_SCLK, 3-/4-pin mode, polarity = 0, phase = 0 4 Setup time, SPI_SOMI valid before receive rising edge of SPI_SCLK, 3-/4-pin mode, polarity = 0, phase = 1 4 Setup time, SPI_SOMI valid before receive rising edge of SPI_SCLK, 3-/4-pin mode, polarity = 1, phase = 0 4 Setup time, SPI_SOMI valid before receive falling edge of SPI_SCLK, 3-/4-pin mode, polarity = 1, phase = 1 4 Hold time, SPI_SOMI valid after receive falling edge of SPI_SCLK, 3-/4-pin mode, polarity = 0, phase = 0 4 Hold time, SPI_SOMI valid after receive rising edge of SPI_SCLK, 3-/4-pin mode, polarity = 0, phase = 1 4 Hold time, SPI_SOMI valid after receive rising edge of SPI_SCLK, 3-/4-pin mode, polarity = 1, phase = 0 4 Hold time, SPI_SOMI valid after receive falling edge of SPI_SCLK, 3-/4-pin mode, polarity = 1, phase = 1 4 Copyright © 2009–2011, Texas Instruments Incorporated MAX UNIT ns ns Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 161 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Slave Mode — General Table 6-64. General Switching Characteristics in Slave Mode (For 3-/4-Pin Modes) (1) NO. 13 14 (1) 162 PARAMETER td(CLK-SOMI) toh(CLK-SOMI) MIN MAX Delay time, transmit rising edge of SPI_SCLK to SPI_SOMI output valid, 3-/4-pin mode, polarity = 0, phase = 0 2 16.5 Delay time, transmit falling edge of SPI_SCLK to SPI_SOMI output valid, 3-/4-pin mode, polarity = 0, phase = 1 2 16.5 Delay time, transmit falling edge of SPI_SCLK to SPI_SOMI output valid, 3-/4-pin mode, polarity = 1, phase = 0 2 16.5 Delay time, transmit rising edge of SPI_SCLK to SPI_SOMI output valid, 3-/4-pin mode, polarity = 1, phase = 1 2 16.5 Output hold time, SPI_SOMI valid (except final bit) after receive falling edge of SPI_SCLK, 3-/4-pin mode, polarity = 0, phase = 0 4 Output hold time, SPI_SOMI valid (except final bit) after receive rising edge of SPI_SCLK, 3-/4-pin mode, polarity = 0, phase = 1 4 Output hold time, SPI_SOMI valid (except final bit) after receive rising edge of SPI_SCLK, 3-/4-pin mode, polarity = 1, phase = 0 4 Output hold time, SPI_SOMI valid (except final bit) after receive falling edge of SPI_SCLK, 3-/4-pin mode, polarity = 1, phase = 1 4 UNIT ns ns T = period of SPI_SCLK Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-65. General Input Timing Requirements in Slave Mode (1) NO. MAX UNIT 256P ns 9 tc(CLK) Cycle time, SPI_SCLK 10 tw(CLKH) Pulse width, SPI_SCLK high .5(tc(CLK)) 1.25 ns 11 tw(CLKL) Pulse width, SPI_SCLK low .5(tc(CLK)) 1.25 ns 15 16 (1) MIN greater of 2P or 25 tsu(SIMO-CLK) th(CLK-SIMO) Setup time, SPI_SIMO data valid before receive falling edge of SPI_SCLK, 3-/4-pin mode, polarity = 0, phase = 0 4 Setup time, SPI_SIMO data valid before receive rising edge of SPI_SCLK, 3-/4-pin mode, polarity = 0, phase = 1 4 Setup time, SPI_SIMO data valid before receive rising edge of SPI_SCLK, 3-/4-pin mode, polarity = 1, phase = 0 4 Setup time, SPI_SIMO data valid before receive falling edge of SPI_SCLK, 3-/4-pin mode, polarity = 1, phase = 1 4 Hold time, SPI_SIMO data valid after receive falling edge of SPI_SCLK, 3-/4-pin mode, polarity = 0, phase = 0 4 Hold time, SPI_SIMO data valid after receive rising edge of SPI_SCLK, 3-/4-pin mode, polarity = 0, phase = 1 4 Hold time, SPI_SIMO data valid after receive rising edge of SPI_SCLK, 3-/4-pin mode, polarity = 1, phase = 0 4 Hold time, SPI_SIMO data valid after receive falling edge of SPI_SCLK, 3-/4-pin mode, polarity = 1, phase = 1 4 ns ns T = period of SPI_SCLK; For SPI0, SPI1, SPI2, and SPI3, P = period of SPI core clock (PLL1SYSCLK4). For SPI4, P = period of SPI core clock (OSCIN). Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 163 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Master Mode — Additional Table 6-66. Additional Output Switching Characteristics of 4-Pin Chip-Select Option in Master Mode NO. 19 20 (1) PARAMETER tosu(CS-CLK) (1) td(CLK-CS) MIN Output setup time, SPI_SCS[n] active before first SPI_SCLK rising edge, polarity = 0, phase = 0, SPIDELAY.C2TDELAY = 0 (C2TDELAY+2)*P+6 .5 Output setup time, SPI_SCS[n] active before first SPI_SCLK rising edge, polarity = 0, phase = 1, SPIDELAY.C2TDELAY = 0 (C2TDELAY+2)*P + .5tc + 6.5 Output setup time, SPI_SCS[n] active before first SPI_SCLK falling edge, polarity = 1, phase = 0, SPIDELAY.C2TDELAY = 0 (C2TDELAY+2)*P + 6.5 Output setup time, SPI_SCS[n] active before first SPI_SCLK falling edge, polarity = 1, phase = 1, SPIDELAY.C2TDELAY = 0 (C2TDELAY+2)*P + .5tc + 6.5 MAX UNIT ns Delay time, final SPI_SCLK falling edge to master deasserting SPI_SCS[n], polarity = 0, phase = 0, SPIDELAY.T2CDELAY = 0, SPIDAT1.CSHOLD not enabled (T2CDELAY+1)*P 3 Delay time, final SPI_SCLK falling edge to master deasserting SPI_SCS[n], polarity = 0, phase = 1, SPIDELAY.T2CDELAY = 0, SPIDAT1.CSHOLD not enabled (T2CDELAY+1)*P 3 Delay time, final SPI_SCLK rising edge to master deasserting SPI_SCS[n], polarity = 1, phase = 0, SPIDELAY.T2CDELAY = 0, SPIDAT1.CSHOLD not enabled (T2CDELAY+1)*P 3 Delay time, final SPI_SCLK rising edge to master deasserting SPI_SCS[n], polarity = 1, phase = 1, SPIDELAY.T2CDELAY = 0, SPIDAT1.CSHOLD not enabled (T2CDELAY+1)*P 3 ns The Master SPI is ready with new data before SPI_SCS[n] assertion. Slave Mode — Additional Table 6-67. Additional Output Switching Characteristics of 4-Pin Chip-Select Option in Slave Mode (1) NO. (1) 164 PARAMETER 27 td(CSL-SOMI) Delay time, master asserting SPI_SCS[n] to slave driving SPI_SOMI data valid 28 tdis(CSH-SOMI) Disable time, master deasserting SPI_SCS[n] to slave driving SPI_SOMI high impedance MIN MAX UNIT 2P + 16.5 ns 2P + 16.5 ns T = period of SPI_SCLK; For SPI0, SPI1, SPI2, and SPI3, P = period of SPI core clock (PLL1SYSCLK4). For SPI4, P = period of SPI core clock (OSCIN). Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-68. Additional Input Timing Requirements of 4-Pin Chip-Select Option in Slave Mode (1) NO. 25 26 (1) MIN tsu(CSL-CLK) td(CLK-CSH) Setup time, SPI_SCS[n] asserted at slave to first SPI_SCLK edge (rising or falling) at slave MAX 2P + 25 Delay time, final falling edge SPI_SCLK to SPI_SCS[n] deasserted, polarity = 0, phase = 0 .5(tc(CLK)) + 2P - 4 Delay time, final falling edge SPI_SCLK to SPI_SCS[n] deasserted, polarity = 0, phase = 1 2P - 4 UNIT ns ns Delay time, final rising edge SPI_SCLK to SPI_SCS[n] deasserted, polarity = 1, phase = 0 .5(tc(CLK)) + 2P - 4 Delay time, final rising edge SPI_SCLK to SPI_SCS[n] deasserted, polarity = 1, phase = 1 2P - 4 T = period of SPI_SCLK; For SPI0, SPI1, SPI2, and SPI3, P = period of SPI core clock (PLL1SYSCLK4). For SPI4, P = period of SPI core clock (OSCIN). Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 165 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com MASTER MODE POLARITY = 0 PHASE = 0 1 2 3 SPI_CLK 5 4 MO(0) SPI_SIMO 6 MO(1) 7 MO(n-1) MO(n) 8 MI(0) SPI_SOMI MI(n-1) MI(1) MI(n) MASTER MODE POLARITY = 0 PHASE = 1 4 SPI_CLK 5 6 MO(0) SPI_SIMO MO(1) 7 MO(n-1) MO(n) 8 MI(1) MI(0) SPI_SOMI MI(n-1) MI(n) MASTER MODE POLARITY = 1 PHASE = 0 4 SPI_CLK 5 SPI_SIMO MO(0) 7 6 MO(1) MO(n-1) MI(1) MI(n-1) MO(n) 8 SPI_SOMI MI(0) MI(n) MASTER MODE POLARITY = 1 PHASE = 1 SPI_CLK MO(0) SPI_SIMO 7 SPI_SOMI 6 5 4 MO(1) MO(n-1) MI(1) MI(n-1) MO(n) 8 MI(0) MI(n) Figure 6-43. SPI Timings—Master Mode 166 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com SLAVE MODE POLARITY = 0 PHASE = 0 9 10 11 SPI_CLK 16 15 SPI_SIMO SI(0) SI(1) SPI_SOMI SO(0) SI(n) SI(n-1) 13 14 SO(1) SO(n-1) SO(n) SLAVE MODE POLARITY = 0 PHASE = 1 SPI_CLK 16 15 SI(0) SPI_SIMO SI(1) 13 SI(n) SO(n-1) SO(n) 14 SO(0) SPI_SOMI SI(n-1) SO(1) SLAVE MODE POLARITY = 1 PHASE = 0 SPI_CLK 16 15 SI(0) SPI_SIMO SI(1) 13 SPI_SOMI SO(0) SI(n) SI(n-1) 14 SO(n-1) SO(1) SO(n) SLAVE MODE POLARITY = 1 PHASE = 1 SPI_CLK 16 15 SI(0) SPI_SIMO 13 SPI_SOMI A. SO(0) SI(n-1) SI(1) SI(n) 14 SO(1) SO(n-1) SO(n) The first bit of transmit data becomes valid on the SPI_SOMI pin when software writes to the SPIDAT1 register. For more details, see the TMS320DM36x DMSoC Serial Peripheral Interface User's Guide (literature number SPRUFH1). Figure 6-44. SPI Timings—Slave Mode Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 167 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com MASTER MODE 4 PIN WITH CHIP SELECT 19 20 SPI_CLK MO(0) SPI_SIMO MO(1) MI(0) SPI_SOMI MI(1) MO(n-1) MO(n) MI(n-1) MI(n) SPI_SCS[n] Figure 6-45. SPI Timings—Master Mode (4-Pin) SLAVE MODE 4 PIN WITH CHIP SELECT 25 26 SPI_CLK 28 27 SPI_SOMI SPI_SIMO SO(0) SI(0) SO(1) SO(n-1) SI(1) SI(n-1) SO(n) SI(n) SPI_SCS[n] Figure 6-46. SPI Timings—Slave Mode (4-Pin) 168 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.16 Inter-Integrated Circuit (I2C) The inter-integrated circuit (I2C) module provides an interface between the DM365 and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the device through the I2C module. The I2C port supports: • Compatible with Philips I2C Specification Revision 2.1 (January 2000) • Fast Mode up to 400 Kbps (no fail-safe I/O buffers) • Noise Filter to Remove Noise 50 ns or less • Seven- and Ten-Bit Device Addressing Modes • Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality • Events: DMA, Interrupt, or Polling For more detailed information on the I2C peripheral, see the Documentation Support section for the device Inter-Integrated Circuit (I2C) Module Reference Guide. 6.16.1 I2C Peripheral Register Description(s) Table 6-69 lists the I2C registers, their corresponding acronyms, and the device memory locations (offsets). Table 6-69. Inter-Integrated Circuit (I2C) Registers Offset Acronym Register Description 0h ICOAR I2C Own Address Register 4h ICIMR I2C Interrupt Mask Register 8h ICSTR I2C Interrupt Status Register Ch ICCLKL I2C Clock Low-Time Divider Register 10h ICCLKH I2C Clock High-Time Divider Register 14h ICCNT I2C Data Count Register 18h ICDRR I2C Data Receive Register 1Ch ICSAR I2C Slave Address Register 20h ICDXR I2C Data Transmit Register 24h ICMDR I2C Mode Register 28h ICIVR I2C Interrupt Vector Register 2Ch ICEMDR I2C Extended Mode Register 30h ICPSC I2C Prescaler Register 34h REVID1 I2C Revision ID Register 1 38h REVID2 I2C Revision ID Register 2 48h ICPFUNC I2C Pin Function Register 4ch ICPDIR I2C Pin Direction Register 50h ICPDIN I2C Pin Data In Register 54h ICPDOUT I2C Pin Data Out Register 58h ICPDSET I2C Pin Data Set Register 5ch ICPDCLR I2C Pin Data Clear register Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 169 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 6.16.2 6.16.2.1 www.ti.com I2C Electrical Data/Timing Inter-Integrated Circuits (I2C) Timing Table 6-70. Timing Requirements for I2C Timings (1) (see Figure 6-47) DEVICE STANDARD MODE NO. MIN MAX FAST MODE MIN MAX 1 tc(SCL) Cycle time, SCL 10 2.5 μs 2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 μs 3 th(SCLL-SDAL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 μs 4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 μs 5 tw(SCLH) Pulse duration, SCL high 4 0.6 μs 6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100 7 th(SDA-SCLL) Hold time, SDA valid after SCL low (For I2C bus™ devices) 8 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 9 tr(SDA) 0 3.45 0 1000 20 + 0.1C 4.7 Rise time, SDA 10 tr(SCL) Rise time, SCL 1000 tf(SDA) Fall time, SDA 300 tf(SCL) Fall time, SCL 300 (2) tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 14 tw(SP) Pulse duration, spike (must be suppressed) 15 (2) Cb 4 Capacitive load for each bus line (1) 20 + 0.1C b 13 (1) 20 + 0.1C b 12 (1) 20 + 0.1C b 11 ns 0.9 (1) 300 ns 300 ns 300 ns 300 ns μs 0.6 400 μs μs 1.3 b (1) UNIT 50 ns 400 pF The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. 11 9 SDA 6 8 14 4 13 5 10 SCL 1 12 3 2 7 3 Stop Start Repeated Start Stop Figure 6-47. I2C Receive Timings 170 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-71. Switching Characteristics for I2C Timings (1) (see Figure 6-48) DEVICE NO. STANDARD MODE PARAMETER MIN (1) MAX FAST MODE MIN UNIT MAX 16 tc(SCL) Cycle time, SCL 10 2.5 μs 17 td(SCLH-SDAL) Delay time, SCL high to SDA low (for a repeated START condition) 4.7 0.6 μs 18 td(SDAL-SCLL) Delay time, SDA low to SCL low (for a START and a repeated START condition) 4 0.6 μs 19 tw(SCLL) Pulse duration, SCL low 4.7 1.3 μs 20 tw(SCLH) Pulse duration, SCL high μs 21 td(SDAV-SCLH) Delay time, SDA valid to SCL high 22 tv(SCLL-SDAV) Valid time, SDA valid after SCL low (For I2C devices) 23 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 28 td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition) 29 Cp Capacitance for each I2C pin 4 0.6 250 100 0 0 4.7 1.3 4 ns 0.9 μs μs 0.6 10 μs 10 pF Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. CAUTION 2 The I C pins use a standard ±4-mA LVCMOS buffer, not the slow I/OP buffer defined in the I2C specification. Series resistors may be necessary to reduce noise at the system level. SDA 21 23 19 28 20 SCL 16 18 17 22 18 Stop Start Repeated Start Stop Figure 6-48. I2C Transmit Timings Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 171 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.17 Multi-Channel Buffered Serial Port (McBSP) The primary use for the Multi-Channel Buffered Serial Port (McBSP) is for audio interface purposes. The primary audio modes that are supported by the McBSP are the AC97 and IIS modes. In addition to the primary audio modes, the McBSP supports general serial port receive and transmit operation, but is not intended to be used as a high-speed interface. The McBSP supports the following features: • Full-duplex communication • Double-buffered data registers, which allow a continuous data stream • Independent framing and clocking for receive and transmit • External shift clock generation or an internal programmable frequency shift clock • Double-buffered data registers, which allow a continuous data stream • Independent framing and clocking for receive and transmit • Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices • Direct interface to AC97 compliant devices (the necessary multiphase frame synchronization capability is provided) • Direct interface to IIS compliant devices • Direct interface to SPI protocol in master mode only • A wide selection of data sizes, including 8, 12, 16, 20, 24, and 32 bits • μ-Law and A-Law companding • 8-bit data transfers with the option of LSB or MSB first • Programmable polarity for both frame synchronization and data clocks • Highly programmable internal clock and frame generation • Direct interface to T1/E1 Framers • Multi-channel transmit and receive of up to 128 channels For more detailed information on the McBSP peripheral, see the Documentation Support section for the Multi-Channel Buffered Serial Port (McBSP) Reference Guide. 6.17.1 McBSP Peripheral Register Description(s) Table 6-72 lists the McBSP registers, their corresponding acronyms, and the device memory locations (offsets). Table 6-72. McBSP Registers Offset (1) (2) (3) 172 Acronym Register Name - RBR (1) Receive buffer register - RSR (1) Receive shift register - (1) XSR Transmit shift register 00h DRR (2) (3) 04h DXR (3) Data transmit register Data receive register 08h SPCR Serial port control register 0Ch RCR Receive control register 10h XCR Transmit control register 14h SRGR Sample rate generator register 18h MCR Multichannel Control Register 1Ch RCERE0 Enhanced Receive Channel Enable Register 0 Partition A/B The RBR, RSR, and XSR are not directly accessible via the CPUs or the EDMA controller. The CPUs and EDMA controller can only read this register; they cannot write to it. The DRR and DXR are accessible via the CPUs or the EDMA controller. Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-72. McBSP Registers (continued) Offset Acronym Register Name 20h XCERE0 Enhanced Transmit Channel Enable Register 0 Partition A/B 24h PCR Pin control register 28h RCERE1 Enhanced Receive Channel Enable Register 1 Partition C/D 2Ch XCERE1 Enhanced Transmit Channel Enable Register 1 Partition C/D 30h RCERE2 Enhanced Receive Channel Enable Register 2 Partition E/F 34h XCERE2 Enhanced Transmit Channel Enable Register 2 Partition E/F 38h RCERE3 Enhanced Receive Channel Enable Register 3 Partition G/H 3Ch XCERE3 Enhanced Transmit Channel Enable Register 3 Partition G/H Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 173 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 6.17.2 www.ti.com McBSP Electrical Data/Timing 6.17.2.1 Multi-Channel Buffered Serial Port (McBSP) Timing Table 6-73. Timing Requirements for McBSP (1) (2) (see Figure 6-49) DEVICE NO. MIN MAX UNIT 15 (3) tc(CLKS) Cycle time, CLKS CLKS ext 38.5 or 2P ns 16 (4) tw(CLKS) Pulse duration, CLKR/X high or CLKR/X low CLKS ext 19.25 or P ns CLKR int 21 CLKR ext 6 CLKR int 0 CLKR ext 6 CLKR int 21 CLKR ext 6 CLKR int 0 CLKR ext 6 CLKX int 21 CLKX ext 6 CLKX int 0 CLKX ext 10 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low 8 th(CKRL-DRV) Hold time, DR valid after CLKR low 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low 11 th(CKXL-FXH) Hold time, external FSX high after CLKX low (1) (2) (3) (4) 174 ns ns ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 3.3) . Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle. Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-74. Switching Characteristics Over Recommended Operating Conditions for McBSP (1) (see Figure 6-49) NO. 2 (4) (5) 17 3 (6) (1) (2) (3) (4) (5) (6) (7) (8) td(CLKS-CLKRX) Delay time, CLKS high to internal CLKR/X CLKR/X ext Pulse duration, CLKR/X high or CLKR/X low 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid 9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid 12 tdis(CKXHDXHZ) Disable time, DX high impedance following last data bit from CLKX high 14 MIN CLKR/X int Cycle time, CLKR/X tw(CKRX) 13 DEVICE PARAMETER tc(CKRX) td(CKXH-DXV) Delay time, CLKX high to DX valid td(FXH-DXV) Delay time, FSX high to DX valid ONLY applies when in data delay 0 (XDATDLY = 00b) mode (2) (3) MAX 38.5 or 2P CLKR/X int 1 CLKR/X int 19.25 - 1 or P - 1 CLKR/X ext 19.25 or P UNIT ns 24 ns CLKR int -4 8 CLKR ext 3 25 CLKX int -4 8 CLKX ext 3 25 ns ns CLKX int 12 ns CLKX ext 25 ns -5 + D1 (7) 12 + D2 (7) ns (7) (7) ns CLKX int CLKX ext 3 + D1 FSX int 0 + D1 (8) 25 + D2 14 + D2 (8) FSX ext 0 + D1 (8) 25 + D2 (8) ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 3.3) . Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. Use whichever value is greater. C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = SYSCLK3 period) S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even H = (CLKGDV + 1)/2 * S if CLKGDV is odd L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even L = (CLKGDV + 1)/2 * S if CLKGDV is odd CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit. Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. If DXENA = 0, then D1 = D2 = 0 If DXENA = 1, then D1 = 6P, D2 = 12P Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. If DXENA = 0, then D1 = D2 = 0 If DXENA = 1, then D1 = 6P, D2 = 12P Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 175 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 16 15 16 CLKS 2 17 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 8 Bit(n-1) DR (n-2) (n-3) 2 17 3 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13(A) Bit(n-1) 13(A) (n-2) (n-3) A. Parameter No. 13 applies to the first data bitonly when XDATDLY ≠ 0. Figure 6-49. McBSP Timing Table 6-75. McBSP as SPI Timing Requirements CLKSTP = 10b, CLKXP = 0 (see Figure 6-50) MASTER NO. MIN M30 tsu(DRV-CKXL) Setup time, DR valid before CLKX low M31 th(CKXL-DRV) Hold time, DR valid after CLKX low Table 6-76. McBSP as SPI Switching Characteristics (1) MAX UNIT 16 ns 0 ns (2) CLKSTP = 10b, CLKXP = 0 (see Figure 6-50) NO. PARAMETER MASTER MIN MAX 38.5 or 2P UNIT M33 tc(CKX) Cycle time, CLKX M24 td(CKXL-FXH) Delay time, CLKX low to FSX high (2) CLKXP - CLKXP + 2 4 ns M25 td(FXL-CKXH) Delay time, FSX low to CLKX high (3) CLKXL - CLKXL + 2 2 ns M26 td(CKXH-DXV) Delay time, CLKX high to DX valid M27 (1) (2) (3) 176 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low -2 ns 6 ns CLKXL - CLKXL + 3 8 ns P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 3.3) . T = CLKX period = (1 + CLKGDV) × 2P L1 = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × 2P when CLKGDV is even. FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com CLKX M24 M33 M25 FSX M27 DX Bit 0 Bit(n-1) M26 (n-2) Bit(n-1) M31 (n-2) M30 DR Bit 0 (n-3) (n-3) (n-4) (n-4) Figure 6-50. McBSP as SPI: CLKSTP = 10b, CLKXP = 0 Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 177 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-77. McBSP as SPI Timing Requirements CLKSTP = 11b, CLKXP = 0 MASTER NO. MIN M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high M40 th(CKXH-DRV) Hold time, DR valid after CLKX high Table 6-78. McBSP as SPI Switching Characteristics (1) MAX UNIT 16 ns 1 ns (2) CLKSTP = 11b, CLKXP = 0 (see Figure 6-51) NO. MASTER PARAMETER MIN MAX UNIT M42 tc(CKX) Cycle time, CLKX 38.5 or 2P M34 td(CKXL-FXH) Delay time, CLKX low to FSX high (3) CLKXP - 2 CLKXP + 4 ns M35 td(FXL-CKXH) Delay time, FSX low to CLKX high (4) CLKXP - 2 CLKXP + 2 ns M36 td(CKXL-DXV) Delay time, CLKX low to DX valid -2 6 ns M37 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low -3 8 ns M38 td(FXL-DXV) Delay time, FSX low to DX valid CLKXH - 2 CLKXH + 10 ns (1) (2) (3) (4) ns P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 3.3). T = CLKX period = (1 + CLKGDV) × 2P L1 = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × 2P when CLKGDV is even H1 = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × 2P when CLKGDV is even FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). CLKX M34 M35 M37 M38 M42 FSX DX Bit 0 Bit(n-1) M39 DR Bit 0 M36 (n-2) (n-3) (n-4) M40 Bit(n-1) (n-2) (n-3) (n-4) Figure 6-51. McBSP as SPI: CLKSTP = 11b, CLKXP = 0 178 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-79. McBSP as SPI Timing Requirements CLKSTP = 10b, CLKXP = 1 (see Figure 6-52) MASTER NO. MIN M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high M50 th(CKXH-DRV) Hold time, DR valid after CLKX high Table 6-80. McBSP as SPI Switching Characteristics (1) MAX UNIT 16 ns 0 ns (2) CLKSTP = 10b, CLKXP = 1 (see Figure 6-52) NO. (3) (4) MIN MAX UNIT M52 tc(CKX) Cycle time, CLKX 38.5 or 2P M43 td(CKXH-FXH) Delay time, CLKX high to FSX high (3) CLKXP - 2 CLKXP + 4 ns M44 td(FXL-CKXL) Delay time, FSX low to CLKX low (4) CLKXH - 2 CLKXH + 2 ns M45 td(CKXL-DXV) Delay time, CLKX low to DX valid -2 6 ns tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high CLKXH - 3 CLKXL + 8 ns M46 (1) (2) MASTER PARAMETER ns P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 3.3). T = CLKX period = (1 + CLKGDV) × 2P H1 = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × 2P when CLKGDV is even FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). CLKX M43 FSX M44 M52 M46 DX Bit 0 Bit(n-1) M49 DR Bit 0 Bit(n-1) M45 (n-2) M50 (n-2) (n-3) (n-3) (n-4) (n-4) Figure 6-52. McBSP as SPI: CLKSTP = 10b, CLKXP = 1 Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 179 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-81. McBSP as SPI Timing Requirements CLKSTP = 11b, CLKXP = 1 (see Figure 6-53) MASTER NO. MIN M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low M59 th(CKXL-DRV) Hold time, DR valid after CLKX low Table 6-82. McBSP as SPI Switching Characteristics (1) MAX UNIT 16 ns 0 ns (2) CLKSTP = 11b, CLKXP = 1 (see Figure 6-53) NO. MASTER PARAMETER MIN MAX UNIT M62 tc(CKX) Cycle time, CLKX 38.5 or 2P M53 td(CKXH-FXH) Delay time, CLKX high to FSX high (3) CLKXP - 2 CLKXP + 4 ns M54 td(FXL-CKXL) Delay time, FSX low to CLKX low (4) CLKXP - 2 CLKXP + 2 ns M55 td(CKXL-DXV) Delay time, CLKX high to DX valid -2 6 ns M56 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high -3 8 ns M57 td(FXL-DXV) Delay time, FSX low to DX valid CLKXL - 1 CLKXL + 10 ns (1) (2) (3) (4) ns P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 3.3). T = CLKX period = (1 + CLKGDV) × 2P L1 = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × 2P when CLKGDV is even H1 = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × 2P when CLKGDV is even FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). CLKX M53 M54 M62 FSX DX M56 Bit 0 M57 Bit(n-1) M58 DR Bit 0 Bit(n-1) M55 (n-2) M59 (n-2) (n-3) (n-3) (n-4) (n-4) Figure 6-53. McBSP as SPI: CLKSTP = 11b, CLKXP = 1 180 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.18 Timer The device contains four software-programmable timers. Timer 0, Timer 1, Timer 3, and Timer 4 (general-purpose timers) can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit chained mode. Timer 3 supports additional features over the other timers: external clock/event input, period reload, output event tied to Real Time Out (RTO) module, external event capture, and timer counter register read reset. Timer 2 is used only as a watchdog timer. Timer 2 is tied to device reset. • 64-bit count-up counter • Timer modes: – 64-bit general-purpose timer mode (Timer 0, 1, 3, 4) – Dual 32-bit general-purpose timer mode (Timer 0, 1, 3, 4) – Watchdog timer mode (Timer 2) • Two possible clock sources: – Internal clock – External clock/event input via timer input pins (Timer 3) • Three possible operation modes: – One-time operation (timer runs for one period then stops) – Continuous operation (timer automatically resets after each period) – Continuous operation with period reload (Timer 3) • Generates interrupts to the ARM CPU • Generates sync event to EDMA • Generates output event to device reset (Timer 2) • Generates output event to Real Timer Out (RTO) module (Timer 3) • External event capture via timer input pins (Timer 3) For more detailed information, see the TMS320DM36x DMSoC Timer/Watchdog Timer User's Guide (SPRUFH0). 6.18.1 Timer Peripheral Register Description(s) Table 6-83 lists the Timer registers, their corresponding acronyms, and the device memory locations (offsets). Table 6-83. Timer Global Registers Offset Acronym 00h PID12 Register Description 04h EMUMGT 10h TIM12 Timer Counter Register 12 14h TIM34 Timer Counter Register 34 18h PRD12 Timer Period Register 12 1Ch PRD34 Timer Period Register 34 Peripheral Identification Register 12 Emulation Management Register 20h TCR 24h TGCR 28h WDTCR 34h REL12 Timer Reload Register 12 38h REL34 Timer Reload Register 34 3Ch CAP12 Timer Capture Register 12 40h CAP34 Timer Capture Register 34 44h INTCTL_STAT Copyright © 2009–2011, Texas Instruments Incorporated Timer Control Register Timer Global Control Register Watchdog Timer Control Register Timer Interrupt Control and Status Register Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 181 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 6.18.2 www.ti.com Timer Electrical Data/Timing Table 6-84. Timing Requirements for Timer Input (1) (2) (see Figure 6-54) DEVICE NO. MIN MAX 1 tc(TIN) Cycle time, TIM_IN 2 tw(TINPH) Pulse duration, TIM_IN high 0.45C 0.55C ns 3 tw(TINPL) Pulse duration, TIM_IN low 0.45C 0.55C ns 4 tt(TIN) Transition time, TIM_IN 5 ns (1) (2) 4P UNIT ns GPIO001, GPIO002, GPIO003, and GPIO004 can be used as external clock inputs for Timer 3. See the TMS320DM36x DMSoC Timer/Watchdog Timer User's Guide for more information (SPRUFH0). P = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use P = 41.6 ns. 1 2 4 3 4 TIM_IN Figure 6-54. Timer Input Timing 182 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.19 Pulse Width Modulator (PWM) The pulse width modulator (PWM) feature is very common in embedded systems. It provides a way to generate a pulse periodic waveform for motor control or can act as a digital-to-analog converter with some external components. This PWM peripheral is basically a timer with a period counter and a first-phase duration comparator, where bit width of the period and first-phase duration are both programmable. The Pulse Width Modulator (PWM) modules support the following features: • 32-bit period counter • 32-bit first-phase duration counter • 8-bit repeat count for one-shot operation. One-shot operation will produce N + 1 periods of the waveform, where N is the repeat counter value. • Configurable to operate in either one-shot or continuous mode • Buffered period and first-phase duration registers • One-shot operation triggerable by hardware events with programmable edge transitions. (low-to-high or high-to-low). • One-shot operation triggerable by the ISIF VSYNC output of the video processing subsystem (VPSS), which allows any of the PWM instantiations to be used as a ISIF timer. This allows the device module to support the functions provided by the ISIF timer feature (generating strobe and shutter signals). • One-shot operation generates N+1 periods of waveform, N being the repeat count register value • Configurable PWM output pin inactive state • Interrupt and EDMA synchronization events 6.19.1 PWM Peripheral Register Description(s) Table 6-85 lists the PWM registers, their corresponding acronyms, and the device memory locations (offsets). Table 6-85. Pulse Width Modulator (PWM) Registers Offset Acronym Register Description 00h PID PWM Peripheral Identification Register 04h PCR PWM Peripheral Control Register 08h CFG PWM Configuration Register 0Ch START PWM Start Register 10h RPT PWM Repeat Count Register 14h PER PWM Period Register 18h PH1D PWM First-Phase Duration Register 6.19.2 PWM0/1/2/3 Electrical/Timing Data Table 6-86. Switching Characteristics Over Recommended Operating Conditions for PWM0/1/2/3 Outputs (1) (see Figure 6-55 and Figure 6-56) NO. DEVICE MIN 1 tw(PWMH) Pulse duration, PWMx high 37 2 tw(PWML) Pulse duration, PWMx low 37 3 tt(PWM) Transition time, PWMx td(ISIF-PWMV) Delay time, ISIF(VD) trigger event to PWMx valid 4 (1) PARAMETER 0 MAX UNIT ns ns 5 ns 10 ns P = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use P = 41.6 ns. Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 183 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 1 2 PWM0/1/2/3 3 3 Figure 6-55. PWM Output Timing VD(CCDC) 4 PWM0 INVALID VALID 4 PWM1 VALID INVALID 4 PWM2 VALID INVALID 4 PWM3 INVALID VALID Figure 6-56. PWM Output Delay Timing 184 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.20 Real Time Out (RTO) The device uses the Real Time Out (RTO) peripheral to provide appropriate input control signals to external devices such as motor controllers. This peripheral supports the following features: • Four separate outputs • Trigger on Timer3 event 6.20.1 Real Time Out (RTO) Peripheral Register Description(s) Table 6-87 lists the RTO registers, their corresponding acronyms, and the device memory locations (offsets). Table 6-87. Real Time Out (RTO) Registers Offset Acronym Register Description 0h REVID RTO Controller Revision ID Register 04h CTRL_STATUS RTO Controller Control and Status Register 6.20.2 RTO Electrical/Timing Data Table 6-88. Switching Characteristics Over Recommended Operating Conditions for RTO Outputs (see Figure 6-57 and Figure 6-58) (1) NO. MIN MAX UNIT 1 tw(RTOH) Pulse duration, RTOx high 27.7 52.08 3 ns 2 tw(RTOL) Pulse duration, RTOx low .45C .55C ns 3 tt(RTO) Transition time, RTOx .45C .55C ns td(TIMER3-RTOV) Delay time, Timer 3 (TINT12 or TINT34) trigger event to RTOx valid 10 ns 4 (1) DEVICE PARAMETER C = MXI1/CLKIN1 cycle time in ns. For example, when MXI1/CLKIN1 frequency is 24 MHz use C = 41.6 ns. 1 2 RTO0/1/2/3 3 3 Figure 6-57. RTO Output Timing Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 185 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com TINT12/TINT34 (Timer3) 4 RTO0 INVALID VALID 4 RTO1 VALID INVALID 4 RTO2 VALID INVALID 4 RTO3 INVALID VALID Figure 6-58. RTO Output Delay Timing 186 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.21 Ethernet Media Access Controller (EMAC) The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the network. The EMAC supports both 10Base-T (10 Mbits/second [Mbps]) and 100Base-TX (100 Mbps) in either half- or full-duplex mode. The EMAC module also supports hardware flow control and quality of service (QOS) support. The frequencies supported for transmit and receive clocks are fixed by the IEEE 802.3 standard as: • 2.5 MHz for 10Mbps • 25 MHz for 100Mbps The EMAC controls the flow of packet data from the device to the PHY. The MDIO module controls PHY configuration and status monitoring. The EMAC module conforms to the IEEE 802.3-2002 standard, describing the “Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. The IEEE 802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E). Deviation from this standard, the EMAC module does not use the Transmit Coding Error signal MTXER. Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will intentionally generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame will be detected as an error by the network Both the EMAC and the MDIO modules interface to the device through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC control module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to multiplex and control interrupts. For more information on the TMS320DM36x DMSoC Ethernet Media Access Controller User's Guide (literature number SPRUFI5). 6.21.1 EMAC Peripheral Register Description(s) Table 6-89 lists the EMAC registers, their corresponding acronyms, and the device memory locations (offsets). Table 6-89. Ethernet Media Access Controller (EMAC) Control Module Registers Slave VBUS Acronym Address Offset Register Description 0h CMIDVER Identification and Version Register 04h CMSOFTRESET Software Reset Register 08h CMEMCONTROL Emulation Control Register Ch CMINTCTRL Interrupt Control Register 10h CMRXTHRESHINTEN Receive Threshold Interrupt Enable Register 14h CMRXINTEN Receive Interrupt Enable Register 18h CMTXINTEN Transmit Interrupt Enable Register 1Ch CMMISCINTEN Miscellaneous Interrupt Enable Register 40h CMRXTHRESHINTSTAT Receive Threshold Interrupt Status Register 44h CMRXINTSTAT Receive Interrupt Status Register 48h CMTXINTSTAT Transmit Interrupt Status Register 4Ch CMMISCINTSTAT Miscellaneous Interrupt Status Register 70Ch CMRXINTMAX Receive Interrupts Per Millisecond Register 74h CMTXINTMAX Transmit Interrupts Per Millisecond Register Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 187 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-90. Ethernet Media Access Controller (EMAC) Registers 188 Offset Acronym Register Description 0h TXIDVER Transmit Identification and Version Register 4h TXCONTROL Transmit Control Register 8h TXTEARDOWN Transmit Teardown Register 10h RXIDVER Receive Identification and Version Register 14h RXCONTROL Receive Control Register 18h RXTEARDOWN Receive Teardown Register 80h TXINTSTATRAW Transmit Interrupt Status (Unmasked) Register 84h TXINTSTATMASKED Transmit Interrupt Status (Masked) Register 88h TXINTMASKSET Transmit Interrupt Mask Set Register 8Ch TXINTMASKCLEAR Transmit Interrupt Clear Register 90h MACINVECTOR MAC Input Vector Register 94h MACEOIVECTOR MAC End of Interrupt Vector Register A0h RXINTSTATRAW Receive Interrupt Status (Unmasked) Register A4h RXINTSTATMASKED Receive Interrupt Status (Masked) Register A8h RXINTMASKSET Receive Interrupt Mask Set Register ACh RXINTMASKCLEAR Receive Interrupt Mask Clear Register B0h MACINTSTATRAW MAC Interrupt Status (Unmasked) Register B4h MACINTSTATMASKED MAC Interrupt Status (Masked) Register B8h MACINTMASKSET MAC Interrupt Mask Set Register BCh MACINTMASKCLEAR MAC Interrupt Mask Clear Register 100h RXMBPENABLE Receive Multicast/Broadcast/Promiscuous Channel Enable Register 104h RXUNICASTSET Receive Unicast Enable Set Register 108h RXUNICASTCLEAR Receive Unicast Clear Register 10Ch RXMAXLEN Receive Maximum Length Register 110h RXBUFFEROFFSET Receive Buffer Offset Register 114h RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register 120h RX0FLOWTHRESH Receive Channel 0 Flow Control Threshold Register 124h RX1FLOWTHRESH Receive Channel 1 Flow Control Threshold Register 128h RX2FLOWTHRESH Receive Channel 2 Flow Control Threshold Register 12Ch RX3FLOWTHRESH Receive Channel 3 Flow Control Threshold Register 130h RX4FLOWTHRESH Receive Channel 4 Flow Control Threshold Register 134h RX5FLOWTHRESH Receive Channel 5 Flow Control Threshold Register 138h RX6FLOWTHRESH Receive Channel 6 Flow Control Threshold Register 13Ch RX7FLOWTHRESH Receive Channel 7 Flow Control Threshold Register 140h RX0FREEBUFFER Receive Channel 0 Free Buffer Count Register 144h RX1FREEBUFFER Receive Channel 1 Free Buffer Count Register 148h RX2FREEBUFFER Receive Channel 2 Free Buffer Count Register 14Ch RX3FREEBUFFER Receive Channel 3 Free Buffer Count Register 150h RX4FREEBUFFER Receive Channel 4 Free Buffer Count Register 154h RX5FREEBUFFER Receive Channel 5 Free Buffer Count Register 158h RX6FREEBUFFER Receive Channel 6 Free Buffer Count Register 15Ch RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register 160h MACCONTROL MAC Control Register 164h MACSTATUS MAC Status Register 168h EMCONTROL Emulation Control Register 16Ch FIFOCONTROL FIFO Control Register 170h MACCONFIG MAC Configuration Register Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-90. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description 174h SOFTRESET Soft Reset Register 1D0h MACSRCADDRLO MAC Source Address Low Bytes Register 1D4h MACSRCADDRHI MAC Source Address High Bytes Register 1D8h MACHASH1 MAC Hash Address Register 1 1DCh MACHASH2 MAC Hash Address Register 2 1E0h BOFFTEST Back Off Test Register 1E4h TPACETEST Transmit Pacing Algorithm Test Register 1E8h RXPAUSE Receive Pause Timer Register 1ECh TXPAUSE Transmit Pause Timer Register 500h MACADDRLO MAC Address Low Bytes Register, Used in Receive Address Matching 504h MACADDRHI MAC Address High Bytes Register, Used in Receive Address Matching 508h MACINDEX MAC Index Register 600h TX0HDP Transmit Channel 0 DMA Head Descriptor Pointer Register 604h TX1HDP Transmit Channel 1 DMA Head Descriptor Pointer Register 608h TX2HDP Transmit Channel 2 DMA Head Descriptor Pointer Register 60Ch TX3HDP Transmit Channel 3 DMA Head Descriptor Pointer Register 610h TX4HDP Transmit Channel 4 DMA Head Descriptor Pointer Register 614h TX5HDP Transmit Channel 5 DMA Head Descriptor Pointer Register 618h TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register 61Ch TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register 620h RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register 624h RX1HDP Receive Channel 1 DMA Head Descriptor Pointer Register 628h RX2HDP Receive Channel 2 DMA Head Descriptor Pointer Register 62Ch RX3HDP Receive Channel 3 DMA Head Descriptor Pointer Register 630h RX4HDP Receive Channel 4 DMA Head Descriptor Pointer Register 634h RX5HDP Receive Channel 5 DMA Head Descriptor Pointer Register 638h RX6HDP Receive Channel 6 DMA Head Descriptor Pointer Register 63Ch RX7HDP Receive Channel 7 DMA Head Descriptor Pointer Register 640h TX0CP Transmit Channel 0 Completion Pointer Register 644h TX1CP Transmit Channel 1 Completion Pointer Register 648h TX2CP Transmit Channel 2 Completion Pointer Register 64Ch TX3CP Transmit Channel 3 Completion Pointer Register 650h TX4CP Transmit Channel 4 Completion Pointer Register 654h TX5CP Transmit Channel 5 Completion Pointer Register 658h TX6CP Transmit Channel 6 Completion Pointer Register 65Ch TX7CP Transmit Channel 7 Completion Pointer Register 660h RX0CP Receive Channel 0 Completion Pointer Register 664h RX1CP Receive Channel 1 Completion Pointer Register 668h RX2CP Receive Channel 2 Completion Pointer Register 66Ch RX3CP Receive Channel 3 Completion Pointer Register 670h RX4CP Receive Channel 4 Completion Pointer Register 674h RX5CP Receive Channel 5 Completion Pointer Register 678h RX6CP Receive Channel 6 Completion Pointer Register 67Ch RX7CP Receive Channel 7 Completion Pointer Register 200h RXGOODFRAMES Good Receive Frames Register 204h RXBCASTFRAMES Broadcast Receive Frames Register Network Statistics Registers Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 189 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-90. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description 208h RXMCASTFRAMES Multicast Receive Frames Register 20Ch RXPAUSEFRAMES Pause Receive Frames Register 210h RXCRCERRORS Receive CRC Errors Register 214h RXALIGNCODEERRORS Receive Alignment/Code Errors Register 218h RXOVERSIZED Receive Oversized Frames Register 21Ch RXJABBER Receive Jabber Frames Register 220h RXUNDERSIZED Receive Undersized Frames Register 224h RXFRAGMENTS Receive Frame Fragments Register 228h RXFILTERED Filtered Receive Frames Register 22Ch RXQOSFILTERED Receive QOS Filtered Frames Register 230h RXOCTETS Receive Octet Frames Register 234h TXGOODFRAMES Good Transmit Frames Register 238h TXBCASTFRAMES Broadcast Transmit Frames Register 23Ch TXMCASTFRAMES Multicast Transmit Frames Register 240h TXPAUSEFRAMES Pause Transmit Frames Register 244h TXDEFERRED Deferred Transmit Frames Register 248h TXCOLLISION Transmit Collision Frames Register 24Ch TXSINGLECOLL Transmit Single Collision Frames Register 250h TXMULTICOLL Transmit Multiple Collision Frames Register 254h TXEXCESSIVECOLL Transmit Excessive Collision Frames Register 258h TXLATECOLL Transmit Late Collision Frames Register 25Ch TXUNDERRUN Transmit Underrun Error Register 260h TXCARRIERSENSE Transmit Carrier Sense Errors Register 264h TXOCTETS Transmit Octet Frames Register 268h FRAME64 Transmit and Receive 64 Octet Frames Register 26Ch FRAME65T127 Transmit and Receive 65 to 127 Octet Frames Register 270h FRAME128T255 Transmit and Receive 128 to 255 Octet Frames Register 274h FRAME256T511 Transmit and Receive 256 to 511 Octet Frames Register 278h FRAME512T1023 Transmit and Receive 512 to 1023 Octet Frames Register 27Ch FRAME1024TUP Transmit and Receive 1024 to RXMAXLEN Octet Frames Register 280h NETOCTETS Network Octet Frames Register 284h RXSOFOVERRUNS Receive FIFO or DMA Start of Frame Overruns Register 288h RXMOFOVERRUNS Receive FIFO or DMA Middle of Frame Overruns Register 28Ch RXDMAOVERRUNS Receive DMA Overruns Register Table 6-91. EMAC Descriptor Memory HEX ADDRESS RANGE 0x01D0 8000 - 0x01D0 9FFF 190 ACRONYM – DESCRIPTION EMAC Control Module Descriptor Memory Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.21.2 Ethernet Media Access Controller (EMAC) Electrical Data/Timing Table 6-92. Timing Requirements for MRCLK (see Figure 6-59) NO. 10 Mbps 100 Mbps MIN MAX MIN MAX UNIT 1 tc(MRCLK) Cycle time, MRCLK 400 40 ns 2 tw(MRCLKH) Pulse duration, MRCLK high 140 14 ns 3 tw(MRCLKL) Pulse duration, MRCLK low 140 14 ns 1 2 3 MRCLK Figure 6-59. MRCLK Timing (EMAC - Receive) Table 6-93. Timing Requirements for MTCLK (see Figure 6-59) NO. 10 Mbps 100 Mbps MIN MAX MIN MAX UNIT 1 tc(MTCLK) Cycle time, MTCLK 400 40 ns 2 tw(MTCLKH) Pulse duration, MTCLK high 140 14 ns 3 tw(MTCLKL) Pulse duration, MTCLK low 140 14 ns 1 2 3 MTCLK Figure 6-60. MTCLK Timing (EMAC - Transmit) Table 6-94. Timing Requirements for EMAC MII Receive 10/100 Mbit/s (1) (see Figure 6-61) NO. (1) MIN MAX UNIT 1 tsu(MRXD-MRCLKH) Setup time, receive selected signals valid before MRCLK high 8 ns 2 th(MRCLKH-MRXD) Hold time, receive selected signals valid after MRCLK high 8 ns Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER. 1 2 MRCLK (Input) MRXD3−MRXD0, MRXDV, MRXER (Inputs) Figure 6-61. EMAC Receive Interface Timing Table 6-95. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 191 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-95. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s(1) (see Figure 6-62) (continued) 10/100 Mbit/s (1) (see Figure 6-62) NO. 1 (1) td(MTCLKH-MTXD) Delay time, MTCLK high to transmit selected signals valid MIN MAX 5 25 UNIT ns Transmit selected signals include: MTXD3-MTXD0, and MTXEN. 1 MTCLK (Input) MTXD3−MTXD0, MTXEN (Outputs) Figure 6-62. EMAC Transmit Interface Timing 192 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.22 Management Data Input/Output (MDIO) The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. Only one PHY may be connected at any given time. For more detailed information on the MDIO peripheral, see the TMS320DM36x DMSoC Ethernet Media Access Controller User's Guide (literature number SPRUFI5). 6.22.1 MDIO Peripheral Register Description(s) Table 6-96 lists the MDIO registers, their corresponding acronyms, and the device memory locations (offsets). Table 6-96. Management Data Input/Output (MDIO) Registers Offset Acronym Register Description 0h VERSION Identification and Version Register 04h CONTROL MDIO Control Register 08h ALIVE PHY Alive Status register Ch LINK PHY Link Status Register 10h LINKINTRAW MDIO Link Status Change Interrupt (Unmasked) Register 14h LINKINTMASKED MDIO Link Status Change Interrupt (Masked) Register 20h USERINTRAW MDIO User Command Complete Interrupt (Unmasked) Register 24h USERINTMASKED MDIO User Command Complete Interrupt (Masked) Register 28h USERINTMASKSET MDIO User Command Complete Interrupt Mask Set Register 2Ch USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register 80h USERACCESS0 MDIO User Access Register 0 84h USERPHYSEL0 MDIO User PHY Select Register 0 88h USERACCESS1 MDIO User Access Register 1 8Ch USERPHYSEL1 MDIO User PHY Select Register 1 6.22.2 Management Data Input/Output (MDIO) Electrical Data/Timing Table 6-97. Timing Requirements for MDIO Input (see Figure 6-63 and Figure 6-64) DEVICE NO. MIN 1 tc(MDCLK) Cycle time, MDCLK 400 2 tw(MDCLK) Pulse duration, MDCLK high/low 180 3 tt(MDCLK) Transition time, MDCLK 4 tsu(MDIO-MDCLKH) Setup time, MDIO data input valid before MDCLK high 5 th(MDCLKH-MDIO) Hold time, MDIO data input valid after MDCLK high Copyright © 2009–2011, Texas Instruments Incorporated MAX UNIT ns ns 5 ns 10 ns 0 ns Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 193 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 1 3 3 MDCLK 4 5 MDIO (input) Figure 6-63. MDIO Input Timing Table 6-98. Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see Figure 6-64) DEVICE NO. 7 MIN td(MDCLKL-MDIO) Delay time, MDCLK low to MDIO data output valid MAX 100 UNIT ns 1 MDCLK 7 MDIO (output) Figure 6-64. MDIO Output Timing 194 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.23 Host-Port Interface (HPI) Peripheral Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave. 6.23.1 HPI Device-Specific Information The device includes a user-configurable 16-bit Host-port interface (HPI16). • Multiplexed (address/data) operation • Configurable single full-word cycle and dual half-word cycle access modes • Bursting available utilizing 8-word read and write FIFOs • HPIA register supports auto-incrementing • HPID register/FIFOs providing data-path between external host interface and system bus • Multiple strobes and control signals to allow flexible host connection • Software control of data prefetching to the HPID/FIFOs • DMSoC-to-Host interrupt output signal controlled by HPIC accesses • Host-to-DMSoC interrupt controlled by HPIC accesses NOTE: The device HPI does not support the HAS feature. For proper HPI operation if the HAS pin is routed out, the HAS pin must be pulled up via an external resistor. The device HPICTL register (0x01C4 0024) is part of the System Module Registers. The HPICTL register controls write access to the HPI peripheral control and address registers as well as determines the host time-out value. 6.23.2 HPI Bus Master The HPI peripheral includes a bus master interface that allows external device initiated transfers to access the DM365 system bus. See the Master Peripheral Mem Map column in Table 2-3, the device Memory Map. 6.23.3 HPI Peripheral Register Description(s) Table 6-99 lists the HPI registers, their corresponding acronyms, and the device memory locations (offsets). Table 6-99. HPI Registers Offset Acronym Register Description 0h PID Peripheral Identification Register 4h PWREMU_MGMT Power and Emulation Management Register 30h HPIC Host Port Interface Control Register 34h HPIAW Host Port Interface Write Address Register 38h HPIAR Host Port Interface Read Address Register Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 195 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.23.4 HPI Electrical Data/Timing Table 6-100. Timing Requirements for Host-Port Interface Cycles (1) (2) (see Figure 6-65 and Figure 6-66) DEVICE NO. MIN MAX UNIT 1 tsu(SELV-HSTBL) Setup time, select signals (3) valid before HSTROBE low 6 ns 2 th(HSTBL-SELV) Hold time, select signals (3) valid after HSTROBE low 2 ns 3 tw(HSTBL) Pulse duration, HSTROBE active low 15 ns 4 tw(HSTBH) Pulse duration, HSTROBE inactive high between consecutive accesses 2P ns 11 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 5 ns 12 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 2 ns 13 th(HRDYL-HSTBL) Hold time, HSTROBE high after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 2 ns (1) (2) (3) 196 HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = PLLC1.SYSCLK4 period, where SYSCLK4 is an output clock of PLLC1. For more details, see Section 3.3, Device Clocking Select signals include: HCNTLA, HCNTLB, HR/W and HHWIL. Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-101. Switching Characteristics for Host-Port Interface Cycles (1) (see Figure 6-65 and Figure 6-66) NO. PARAMETER (2) (3) DEVICE MIN UNIT MAX For HPI Write, HRDY can go high (not ready) for these HPI Write conditions; otherwise, HRDY stays low (ready): Case 1: Back-to-back HPIA writes (can be either first or second half-word) Case 2: HPIA write following a PREFETCH command (can be either first or second half-word) Case 3: HPID write when FIFO is full or flushing (can be either first or second half-word) Case 4: HPIA write and Write FIFO not empty 5 td(HSTBL-HRDYV) Delay time, HSTROBE low to HRDY valid 6 ten(HSTBL-HDLZ) Enable time, HD driven from HSTROBE low 7 td(HRDYL-HDV) Delay time, HRDY low to HD valid 8 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 14 tdis(HSTBH-HDV) Disable time, HD high-impedance from HSTROBE high 15 (1) (2) (3) For HPI Read, HRDY can go high (not ready) for these HPI Read conditions: Case 1: HPID read (with auto-increment) and data not in Read FIFO (can only happen to first half-word of HPID access) Case 2: First half-word access of HPID Read without auto-increment For HPI Read, HRDY stays low (ready) for these HPI Read conditions: Case 1: HPID read with auto-increment and data is already in Read FIFO (applies to either half-word of HPID access) Case 2: HPID read without auto-increment and data is already in Read FIFO (always applies to second half-word of HPID access) Case 3: HPIC or HPIA read (applies to either half-word access) td(HSTBL-HDV) Delay time, HSTROBE low to HD valid For HPI Read. Applies to conditions where data is already residing in HPID/FIFO: Case 1: HPIC or HPIA read Case 2: First half-word of HPID read with auto-increment and data is already in Read FIFO Case 3: Second half-word of HPID read with or without auto-increment 17 2 ns ns 0 1.5 ns ns 15 ns 18 ns P = PLLC1.SYSCLK4 period, where SYSCLK4 is an output clock of PLLC1. For more details, see Section 3.3, Device Clocking. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low). Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 197 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com HCS HAS (D) 2 2 1 1 HCNTL[B:A] 2 2 1 1 HR/W 2 2 1 1 HHWIL 4 3 3 HSTROBE (A)(C) 15 15 14 6 5 HRDY 6 8 HD[15:0] (output) 13 7 14 1st Half-Word 8 2nd Half-Word (B) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] or HCS. B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are reflected by parameters for HSTROBE. D. For proper HPI operation, HAS must be pulled up via an external resistor. Figure 6-65. HPI16 Read Timing (HAS Not Used, Tied High) 198 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com HCS HAS (D) 2 2 1 1 HCNTL[B:A] 2 2 1 1 HR/W 1 2 2 1 HHWIL 4 3 3 HSTROBE (A)(C) 11 11 12 12 2nd Half-Word 1st Half-Word HD[15:0] (input) HRDY 18 5 13 18 5 13 (B) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are reflected by parameters for HSTROBE. D. For proper HPI operation, HAS must be pulled up via an external resistor. Figure 6-66. HPI16 Write Timing (HAS Not Used, Tied High) 6.24 Key Scan The device contains Key Scan module that supports two types of Key Matrices - 4x4 and 5x3. It also supports the following features : • Supports the following two scan modes – Channel Interval mode – Scan Interval mode • Programmable key scan time – Strobe time – Interval time • Two input detection modes – Direct mode – 3-Data check mode • Supports one interrupt to detect the following: – Key input changes – Periodic time intervals after a key is pressed Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 199 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.24.1 Key Scan Peripheral Register Description(s) Table 6-102 lists the Key Scan registers, their corresponding acronyms, and the device memory locations (offsets). Table 6-102. Key Scan Registers Offset Register Description 0x0 KEYCTRL Module Control register 0x4 INTCENA Interrupt Enable control 0x8 INTFLG Interrupt Flag control 0xC INTCLR Interrupt Clear control 0x10 STRBWIDTH Strobe width 0x14 INTERVALTIME Interval Time 0x18 CONTITIME Continuous timer 0x1C CURRENTST Keyscan current status 0x20 PREVIOUSST Keyscan previous status 0x24 EMUCTRL Emulation control 6.24.2 Key Scan Electrical Data/Timing Table 6-103. Timing Requirements for Keyscan (see Figure 6-63 and Figure 6-64) DEVICE NO . 1 MIN MAX tw(KEYOUTV) 2 tw(KEYOUTL) 3 tsu(KEYOUT-KEYIN) 4 th(KEYOUT-KEYIN) (1) (2) (STWIDTH + 1)*CLK_P-1 (1) Pulse duration, Keyscan out (active low mode) (STWIDTH + Pulse duration, Keyscan out (always out mode) UNIT (2) ns 1)*CLK_P-1 (1) (2) ns 20 ns 0 ns Setup time, Keyscan input (always out mode) Setup time, Keyscan input (active low mode) Hold time, Keyscan input (always out mode) Hold time, Keyscan input (active low mode) STWIDTH = the value programmed into the STRBWIDTH register. CLK_P = 1/(PLLC1.AUXCLK/(DIV3+1)) or 1/(RTCXI), where RTCXI is the PRTCSS oscillator input pin frequency of 32.768kHz. 1 KEY_OUT[3:0] (Active Low) Hi -Z Hi -Z 2 KEY_OUT[3:0] (Always Out) 3 4 KEY_ IN[4:0] Figure 6-67. Key Scan Timing 200 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.25 Analog-to-Digital Converter (ADC) The device has a 6-channel 10-bit Analog-to-Digital Converter (ADC) interface. The analog-to-digital converter (ADC) feature is very common in embedded systems. The following features are supported on the Analog-to-Digital Converter (ADC): • Six configurable analog input selects • Successive Approximation type 10 bit A-D converter • Programmable Sampling / Conversion Time (base clock is AUXCLK) • Channel select by Auto Scan conversion • Mode select by One-shot mode or Free-run mode • Programmable setup (idle) period to secure A/D sampling start time • Supports the clock stop signals to connect the PSC For Analog-to-Digital Converter characteristics, see Section 5.2 and Section 5.3. 6.25.1 Analog-to-Digital Converter (ADC) Peripheral Register Description(s) Table 6-104 lists the ADC registers, their corresponding acronyms, and the device memory locations (offsets). Table 6-104. Analog-to-Digital Converter (ADC) Interface Registers Offset Register Description 0x0 ADCTL Control register 0x4 CMPTGT Comparator target channel 0x8 CMPLDAT Comparison A/D Lower data 0xC CMPUDAT Comparison A/D Upper data 0x10 SETDIV SETUP divide value for start A/D conversion 0x14 CHSEL Analog Input channel select 0x18 AD0DAT A/D conversion data 0 0x1C AD1DAT A/D conversion data 1 0x20 AD2DAT A/D conversion data 2 0x24 AD3DAT A/D conversion data 3 0x28 AD4DAT A/D conversion data 4 0x2C AD5DAT A/D conversion data 5 0x30 EMUCTRL Emulation Control 6.26 Voice Codec The device has Voice Codec with FIFO (Read FIFO/Write FIFO). The following features are supported on the Voice Codec module. • 16bit x 16 word FIFO for Recording/Playback data transfer • Full differential Microphone Amplifier • Monaural single ended Line output • Monaural Speaker Amplifier (BTL) • Dynamic Range: 70dB(DAC) • Dynamic Range: 70dB(ADC) • 200-300mW Speaker output at RL = 8Ω • Sampling frequency: 8 KHz or 16 KHz • Automatic Level Control for Recording Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 201 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 • www.ti.com Programmable Function by Register Control – Digital Attenuator of DAC: 0 dB to -62 dB – Digital gain control for Recording (0/ +6/ +12/ +18dB) – Power Up/Down Control for each module – 20 dB/26 dB Boost Selectable for Microphone Input – Two Stage Notch filter For Voice Codec characteristics, see Section 5.2 and Section 5.3. 6.26.1 Voice Codec Register Description(s) Table 6-105 lists the Voice Codec registers, their corresponding acronyms, and the device memory locations (offsets). Table 6-105. Voice Codec Registers 202 Offset Register 0x00 VC_PID Description VCIF PID 0x04 VC_CTRL VCIF Control Register 0x08 VC_INTEN VCIF Interrupt enable 0x0C VC_INTSTATUS VCIF Interrupt status 0x10 VC_INTCLR 0x14 VC_EMUL_CTRL 0x20 RFIFO VCIF Read FIFO access register 0x24 WFIFO VCIF Write FIFO access register VCIF Interrupt status clear VCIF emulator Control 0x28 FIFOSTAT FIFO Status 0x80 VC_REG00 Notch filter parameter 1 0x84 VC_REG01 Notch filter parameter 1 0x88 VC_REG02 Notch filter parameter 2 0x8C VC_REG03 Notch filter parameter 2 0x90 VC_REG04 Recording side mode control 0x94 VC_REG05 PGM & MIC gain 0x98 VC_REG06 ALC 0xA4 VC_REG09 Digital soft mute/attention 0xA8 VC_REG10 Digital soft mute/attention 0xB0 VC_REG12 Power up/down control Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 6.27 IEEE 1149.1 JTAG The JTAG (1) interface is used for BSDL testing and emulation of the device. The device requires that both TRST and RESET be asserted upon power up to be properly initialized. While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required for proper operation. While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface and device's emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted. RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan instructions work correctly independent of current state of RESET. For maximum reliability, the device includes an internal pulldown (PD) on the TRST pin to ensure that TRST will always be asserted upon power up and the device's internal emulation logic will always be properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the device after power up and externally drive TRST high before attempting any emulation or boundary scan operations. Following the release of RESET, the low-to-high transition of TRST must be "seen" to latch the state of EMU1 and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see the terminal functions section of this data sheet. 6.27.1 JTAG Register Description(s) Table 6-105 shows the DEVICE ID register (which includes the JTAG ID related information), its corresponding acronym, and the device memory location. For more details on the DEVICE ID register bit fields, see the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5). Table 6-106. DEVICE ID Register HEX ADDRESS RANGE 0x01C4 0028 (1) ACRONYM DEVICEID REGISTER NAME JTAG Identification Register COMMENTS Read-only. Provides 32-bit JTAG ID of the device. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. The DEVICE ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the device, the DEVICE ID register resides at address location 0x01C4 0028. The register hex value for the device is: 0xXB70 002F where 'X' denotes the silicon revision of the device. For more details on the silicon revision, see the TMS320DM365 DMSoC Silicon Errata (literature number SPRZ294). Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 203 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 6.27.2 www.ti.com JTAG Test-Port Electrical Data/Timing Table 6-107. Timing Requirements for JTAG Test Port (see Figure 6-68) DEVICE NO. MIN MAX UNIT 1 tc(TCK) Cycle time, TCK 50 ns 2 tw(TCKH) Pulse duration, TCK high 20 ns 3 tw(TCKL) Pulse duration, TCK low 20 ns 4 tsu(TDIV-RTCKH) Setup time, TDI valid before RTCK high 5 ns 5 th(RTCKH-TDIIV) Hold time, TDI valid after RTCK high 10 ns 6 tsu(TMSV-RTCKH) Setup time, TMS valid before RTCK high 5 ns 7 th(RTCKH-TMSV) Hold time, TMS valid after RTCK high 10 ns 1 2 3 TCK RTCK TDO 5 4 TDI 7 6 TMS Figure 6-68. JTAG Input Timing 204 Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com Table 6-108. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see Figure 6-68) NO. DEVICE PARAMETER MIN MAX UNIT 8 tc(RTCK) Cycle time, RTCK 50 ns 9 tw(RTCKH) Pulse duration, RTCK high 20 ns 10 tw(RTCKL) Pulse duration, RTCK low 20 11 tr(all JTAG outputs) Rise time, all JTAG outputs 5 ns 12 tf(all JTAG outputs) Fall time, all JTAG outputs 5 ns 13 td(RTCKL-TDOV) Delay time, TCK low to TDO valid 23 ns 0 ns 8 9 10 RTCK 13 TDO Figure 6-69. JTAG Output Timing Copyright © 2009–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 205 TMS320DM365 SPRS457E – MARCH 2009 – REVISED JUNE 2011 www.ti.com 7 Mechanical Data The following table(s) show the thermal resistance characteristics for the PBGA − ZCE mechanical package. 7.1 Thermal Data for ZCE The following table shows the thermal resistance characteristics for the PBGA − ZCE mechanical package. Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZCE] °C/W (1) NO. (1) 7.2 1 RΘJC Junction-to-case 7.2 2 RΘJB Junction-to-board 11.4 3 RΘJA Junction-to-free air 27.0 4 PsiJT Junction-to-package top 0.1 5 PsiJB Junction-to-board 11.3 The junction-to-case measurement was conducted in a JEDEC defined 2S2P system and will change based on environment as well as application. For more information, see these three EIA/JEDEC standards: • EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) • EIA/JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages Packaging Information The following packaging information reflects the most current data available for the designated device(s). This data is subject to change without notice and without revision of this document. 206 Mechanical Data Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) DM365ZCES ACTIVE NFBGA ZCE 338 160 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE30 570 DM365ZCEW ACTIVE NFBGA ZCE 338 160 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE30 570 DM365ZCEZ ACTIVE NFBGA ZCE 338 160 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE30F 570 TMS320DM365ZCE21 ACTIVE NFBGA ZCE 338 160 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE21 570 TMS320DM365ZCE27 ACTIVE NFBGA ZCE 338 160 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE27 570 TMS320DM365ZCE30 ACTIVE NFBGA ZCE 338 160 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE30 570 TMS320DM365ZCED30 ACTIVE NFBGA ZCE 338 160 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 DM365ZCED30 570 TMS320DM365ZCEF ACTIVE NFBGA ZCE 338 160 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE30F 570 TMS320DM365ZCEZ ACTIVE NFBGA ZCE 338 160 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE30F 570 VCBU65WMCE30 ACTIVE NFBGA ZCE 338 160 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE30 570 VS3673UNION ACTIVE NFBGA ZCE 338 160 RoHS & Green SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE30 570 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of