TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320F2809, TMS320F2808, TMS320F2806,
TMS320F2802,TMS320F28016,
TMS320F2801, TMS320F28015
TMS320C2802,
TMS320C2801,
TMS320C2801,
TMS320F28016,
TMS320F28015
SPRS230P – OCTOBER
2003 – REVISED
FEBRUARY 2021
www.ti.com
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
TMS320F280x, TMS320C280x, TMS320F2801x digital signal processors
1 Features
•
•
•
•
•
•
•
•
•
•
High-performance static CMOS technology
– 100 MHz (10-ns cycle time)
– 60 MHz (16.67-ns cycle time)
– Low-power (1.8-V core, 3.3-V I/O) design
JTAG boundary scan support
– IEEE Standard 1149.1-1990 Standard Test
Access Port and Boundary Scan Architecture
High-performance 32-bit CPU (TMS320C28x)
– 16 × 16 and 32 × 32 MAC operations
– 16 × 16 dual MAC
– Harvard bus architecture
– Atomic operations
– Fast interrupt response and processing
– Unified memory programming model
– Code-efficient (in C/C++ and Assembly)
On-chip memory
– F2809: 128K × 16 flash, 18K × 16 SARAM
F2808: 64K × 16 flash, 18K × 16 SARAM
F2806: 32K × 16 flash, 10K × 16 SARAM
F2802: 32K × 16 flash, 6K × 16 SARAM
F2801: 16K × 16 flash, 6K × 16 SARAM
F2801x: 16K × 16 flash, 6K × 16 SARAM
– 1K × 16 OTP ROM (flash devices only)
– C2802: 32K × 16 ROM, 6K × 16 SARAM
C2801: 16K × 16 ROM, 6K × 16 SARAM
Boot ROM (4K × 16)
– With software boot modes (via SCI, SPI, CAN,
I2C, and parallel I/O)
– Standard math tables
Clock and system control
– On-chip oscillator
– Watchdog timer module
Any GPIO A pin can be connected to one of the
three external core interrupts
Peripheral Interrupt Expansion (PIE) block that
supports all 43 peripheral interrupts
Endianness: Little endian
128-bit security key/lock
– Protects flash/OTP/L0/L1 blocks
– Prevents firmware reverse-engineering
•
•
•
•
•
•
•
•
•
•
Three 32-bit CPU timers
Enhanced control peripherals
– Up to 16 PWM outputs
– Up to 6 HRPWM outputs with 150-ps MEP
resolution
– Up to four capture inputs
– Up to two quadrature encoder interfaces
– Up to six 32-bit/six 16-bit timers
Serial port peripherals
– Up to 4 SPI modules
– Up to 2 SCI (UART) modules
– Up to 2 CAN modules
– One Inter-Integrated-Circuit (I2C) bus
12-bit ADC, 16 channels
– 2 × 8 channel input multiplexer
– Two sample-and-hold
– Single/simultaneous conversions
– Fast conversion rate:
80 ns - 12.5 MSPS (F2809 only)
160 ns - 6.25 MSPS (280x)
267 ns - 3.75 MSPS (F2801x)
– Internal or external reference
Up to 35 individually programmable, multiplexed
GPIO pins with input filtering
Advanced emulation features
– Analysis and breakpoint functions
– Real-time debug via hardware
Development support includes
– ANSI C/C++ compiler/assembler/linker
– Code Composer Studio™ IDE
– SYS/BIOS
– Digital motor control and digital power software
libraries
Low-power modes and power savings
– IDLE, STANDBY, HALT modes supported
– Disable individual peripheral clocks
Package options
– Thin quad flatpack (PZ)
– MicroStar BGA™ (GGM, ZGM)
Temperature options
– A: –40°C to 85°C (PZ, GGM, ZGM)
– S: –40°C to 125°C (PZ, GGM, ZGM)
– Q: –40°C to 125°C (PZ)
(AEC-Q100 qualification for automotive
applications)
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801
TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
1
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
•
2 Applications
•
www.ti.com
Digital power
Motor drive and control
3 Description
The TMS320F2809, TMS320F2809-Q1, TMS320F2808, TMS320F2808-Q1 TMS320F2806, TMS320F2802,
TMS320F2801-Q1, TMS320F28015-Q1, TMS320F28016-Q1, TMS320C2802-Q1, and TMS320C2801 devices,
members of the TMS320C28x DSP generation, are highly integrated, high-performance solutions for demanding
control applications.
Throughout this document, TMS320F2809, TMS320F2809-Q1 TMS320F2808, TMS320F2808-Q1
TMS320F2806, TMS320F2802-Q1, TMS320F2801-Q1, TMS320C2802, TMS320C2801, TMS320F28015-Q1,
and TMS320F28016-Q1 are abbreviated as F2809, F2808, F2806, F2802-Q1, F2801-Q1, C2802, C2801,
F28015-Q1, and F28016-Q1, respectively. TMS320F28015-Q1 and TMS320F28016-Q1 are abbreviated as
F2801x. Device Comparison (100-MHz Devices) and Device Comparison (60-MHz Devices) provide a summary
of features for each device.
Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE
TMS320F2809ZGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320F2808ZGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320F2806ZGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320F2802ZGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320F2801ZGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320C2802ZGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320C2801ZGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320F28016ZGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320F28015ZGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320F2809GGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320F2808GGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320F2806GGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320F2802GGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320F2801GGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320C2802GGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320C2801GGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320F28016GGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320F28015GGM
BGA MicroStar (100)
10.0 mm × 10.0 mm
TMS320F2809PZ
LQFP (100)
14.0 mm × 14.0 mm
TMS320F2808PZ
LQFP (100)
14.0 mm × 14.0 mm
TMS320F2806PZ
LQFP (100)
14.0 mm × 14.0 mm
TMS320F2802PZ
LQFP (100)
14.0 mm × 14.0 mm
TMS320F2801PZ
LQFP (100)
14.0 mm × 14.0 mm
TMS320C2802PZ
LQFP (100)
14.0 mm × 14.0 mm
TMS320C2801PZ
LQFP (100)
14.0 mm × 14.0 mm
TMS320F28016PZ
LQFP (100)
14.0 mm × 14.0 mm
TMS320F28015PZ
LQFP (100)
14.0 mm × 14.0 mm
(1)
2
For more information on these devices, see Mechanical, Packaging, and Orderable Information.
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Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801
TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
4 Functional Block Diagram
Memory Bus
TINT0
32-bit CPU TIMER 0
TINT1
7
32-bit CPU TIMER 1
TINT2
32-bit CPU TIMER 2
INT14
M0 SARAM
1K x 16
PIE
(96 Interrupts)
M1 SARAM
1K x 16
(A)
INT[12:1]
External Interrupt
Control
32
NMI, INT13
L0 SARAM
4K x 16
(0-wait)
4
16
SCI-A/B
FIFO
SPI-A/B/C/D
FIFO
I2C-A
FIFO
L1 SARAM
4K x 16
(0-wait)
2
GPIOs
(35)
GPIO MUX
4
Real-Time JTAG
(TDI, TDO, TRST, TCK,
TMS, EMU0, EMU1)
(B)
H0 SARAM
8K x 16
(0-wait)
(C)
eCAN-A/B (32 mbox)
8
eQEP1/2
4
ROM
32K x 16 (C2802)
16K x 16 (C2801)
C28x CPU
(100 MHz)
eCAP1/2/3/4
(4 32-bit Timers)
12
ePWM1/2/3/4/5/6
(12 PWM Outputs,
6 Trip Zones,
6 16-bit Timers)
6
FLASH
128K x 16 (F2809)
64K x 16 (F2808)
32K x 16 (F2806)
32K x 16 (F2802)
16K x 16 (F2801)
16K x 16 (F2801x)
SYSCLKOUT
32
System Control
RS
XCLKOUT
XRS
XCLKIN
X1
X2
(Oscillator, PLL,
Peripheral Clocking,
Low-Power Modes,
Watchdog)
CLKIN
(D)
OTP
1K x 16
ADCSOCA/B
Boot ROM
4K x 16
(1-wait state)
SOCA/B
12-Bit ADC
16 Channels
Protected by the code-security module.
Peripheral Bus
Copyright © 2016, Texas Instruments Incorporated
A.
B.
C.
D.
43 of the possible 96 interrupts are used on the devices.
Not available in F2802, F2801, C2802, and C2801.
Not available in F2806, F2802, F2801, C2802, and C2801.
The 1K x 16 OTP has been replaced with 1K x 16 ROM for C280x devices.
Figure 4-1. Functional Block Diagram
Copyright © 2021 Texas Instruments Incorporated
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TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
3
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 2
3 Description.......................................................................2
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 5
6 Device Comparison......................................................... 6
6.1 Related Products........................................................ 8
7 Terminal Configuration and Functions..........................9
7.1 Pin Diagrams.............................................................. 9
7.2 Signal Descriptions................................................... 14
8 Specifications................................................................ 20
8.1 Absolute Maximum Ratings...................................... 20
8.2 ESD Ratings – Automotive....................................... 21
8.3 ESD Ratings – Commercial...................................... 21
8.4 Recommended Operating Conditions.......................21
8.5 Power Consumption Summary................................. 23
8.6 Electrical Characteristics...........................................29
8.7 Thermal Resistance Characteristics for F280x
100-Ball GGM Package...............................................31
8.8 Thermal Resistance Characteristics for F280x
100-Pin PZ Package................................................... 31
8.9 Thermal Resistance Characteristics for C280x
100-Ball GGM Package...............................................32
8.10 Thermal Resistance Characteristics for C280x
100-Pin PZ Package................................................... 32
8.11 Thermal Resistance Characteristics for F2809
100-Ball GGM Package...............................................33
8.12 Thermal Resistance Characteristics for F2809
100-Pin PZ Package................................................... 33
4
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8.13 Thermal Design Considerations..............................33
8.14 Timing and Switching Characteristics..................... 34
8.15 On-Chip Analog-to-Digital Converter...................... 60
8.16 Migrating From F280x Devices to C280x Devices..66
8.17 ROM Timing (C280x only).......................................67
9 Detailed Description......................................................68
9.1 Brief Descriptions......................................................68
9.2 Peripherals................................................................75
9.3 Memory Maps ........................................................ 108
9.4 Register Map...........................................................116
9.5 Interrupts................................................................. 119
9.6 System Control....................................................... 124
9.7 Low-Power Modes Block........................................ 130
10 Applications, Implementation, and Layout............. 131
10.1 TI Design or Reference Design.............................131
11 Device and Documentation Support........................132
11.1 Getting Started...................................................... 132
11.2 Device and Development Support Tool
Nomenclature............................................................ 133
11.3 Tools and Software................................................135
11.4 Documentation Support........................................ 136
11.5 Support Resources............................................... 138
11.6 Trademarks........................................................... 138
11.7 Electrostatic Discharge Caution............................ 138
11.8 Glossary................................................................ 138
12 Mechanical, Packaging, and Orderable
Information.................................................................. 139
12.1 Packaging Information.......................................... 139
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801
TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
5 Revision History
Changes from March 11, 2019 to February 3, 2021 (from Revision O (March 2019) to Revision P
(February 2021))
Page
• Global: Updated the numbering format for tables, figures and cross-references throughout the document...... 1
• Decsription: Updated part numbers.................................................................................................................... 2
• Device Comparison: Updated part numbers.......................................................................................................6
• Pin Diagrams: Updated part numbers................................................................................................................ 9
• Device and Development Support Tool Nomenclature: Updated Device Nomenclature image to show -Q1 part
number............................................................................................................................................................133
Copyright © 2021 Texas Instruments Incorporated
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TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
5
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
6 Device Comparison
Table 6-1. Device Comparison (100-MHz Devices)
TYPE(1)
F2809
F2809-Q1
F2808
F2808-Q1
F2806
F2806-Q1
F2802
F2802-Q1
F2801
F2801-Q1
C2802
C2801
–
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
Single-access RAM (SARAM) (16-bit
word)
–
18K
(L0, L1, M0,
M1, H0)
18K
(L0, L1, M0,
M1, H0)
10K
(L0, L1, M0,
M1)
6K
(L0, M0, M1)
6K
(L0, M0, M1)
6K
(L0, M0, M1)
6K
(L0, M0, M1)
3.3-V on-chip flash (16-bit word)
–
128K
64K
32K
32K
16K
–
–
On-chip ROM (16-bit word)
–
–
–
–
–
–
32K
16K
Code security for on-chip flash/
SARAM/OTP blocks
–
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Boot ROM (4K x 16)
–
Yes
Yes
Yes
Yes
Yes
Yes
Yes
One-time programmable (OTP) ROM
(16-bit word)
–
1K
1K
1K
1K
1K
–
–
PWM channels
0
ePWM1/2/3/4 ePWM1/2/3/4 ePWM1/2/3/4
/5/6
/5/6
/5/6
ePWM1/2/3
ePWM1/2/3
ePWM1/2/3
ePWM1/2/3
HRPWM channels
0
ePWM1A/2A/
ePWM1A/2A/ ePWM1A/2A/ ePWM1A/2A/ ePWM1A/2A/ ePWM1A/2A/ ePWM1A/2A/
3A/
3A/4A
3A/4A
3A
3A
3A
3A
4A/5A/6A
32-bit CAPTURE inputs or auxiliary
PWM outputs
0
eCAP1/2/3/4
eCAP1/2/3/4
eCAP1/2/3/4
eCAP1/2
eCAP1/2
eCAP1/2
eCAP1/2
32-bit QEP channels (four inputs/
channel)
0
eQEP1/2
eQEP1/2
eQEP1/2
eQEP1
eQEP1
eQEP1
eQEP1
Watchdog timer
–
Yes
Yes
Yes
Yes
Yes
Yes
Yes
12-Bit, 16-channel ADC conversion time
1
80 ns
160 ns
160 ns
160 ns
160 ns
160 ns
160 ns
32-Bit CPU timers
–
3
3
3
3
3
3
3
Serial Peripheral Interface (SPI)
0
SPI-A/B/C/D
SPI-A/B/C/D
SPI-A/B/C/D
SPI-A/B
SPI-A/B
SPI-A/B
SPI-A/B
Serial Communications Interface (SCI)
0
SCI-A/B
SCI-A/B
SCI-A/B
SCI-A
SCI-A
SCI-A
SCI-A
Enhanced Controller Area Network
(eCAN)
0
eCAN-A/B
eCAN-A/B
eCAN-A
eCAN-A
eCAN-A
eCAN-A
eCAN-A
Inter-Integrated Circuit (I2C)
0
I2C-A
I2C-A
I2C-A
I2C-A
I2C-A
I2C-A
I2C-A
Digital I/O pins (shared)
–
35
35
35
35
35
35
35
External interrupts
–
3
3
3
3
3
3
3
1.8-V Core, 3.3-V
I/O
–
Yes
Yes
Yes
Yes
Yes
Yes
Yes
100-Pin PZ
–
Yes
Yes
Yes
Yes
Yes
Yes
Yes
100-Ball GGM,
ZGM
–
Yes
Yes
Yes
Yes
Yes
Yes
Yes
A: –40°C to 85°C
–
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
S: –40°C to 125°C
–
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
Q: –40°C to 125°C
(AEC-Q100
Qualification)
–
(PZ)
(PZ)
(PZ)
(PZ)
(PZ)
(PZ)
(PZ)
FEATURE
Instruction cycle (at 100 MHz)
Supply voltage
Packaging
Temperature
options
(1)
A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
C2000 real-time control peripherals reference guide and in the peripheral reference guides.
Table 6-2. Device Comparison (60-MHz Devices)
TYPE(1)
F2802-60
F2801-60
F28016
F28016-Q1
F28015
F28015-Q1
–
16.67 ns
16.67 ns
16.67 ns
16.67 ns
Single-access RAM (SARAM) (16-bit word)
–
6K
(L0, M0, M1)
6K
(L0, M0, M1)
6K
(L0, M0, M1)
6K
(L0, M0, M1)
3.3-V on-chip flash (16-bit word)
–
32K
16K
16K
16K
On-chip ROM (16-bit word)
–
–
–
–
–
FEATURE
Instruction cycle (at 60 MHz)
6
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TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
Table 6-2. Device Comparison (60-MHz Devices) (continued)
TYPE(1)
F2802-60
F2801-60
F28016
F28016-Q1
F28015
F28015-Q1
Code security for on-chip flash/SARAM/OTP
blocks
–
Yes
Yes
Yes
Yes
Boot ROM (4K x 16)
–
Yes
Yes
Yes
Yes
One-time programmable (OTP) ROM
(16-bit word)
–
1K
1K
1K
1K
PWM channels
0
ePWM1/2/3
ePWM1/2/3
ePWM1/2/3/4
ePWM1/2/3/4
HRPWM channels
0
ePWM1A/2A/3A
ePWM1A/2A/3A
ePWM1A/2A/3A/4A
ePWM1A/2A/3A/4A
32-bit CAPTURE inputs or auxiliary PWM
outputs
0
eCAP1/2
eCAP1/2
eCAP1/2
eCAP1/2
32-bit QEP channels (four inputs/channel)
0
eQEP1
eQEP1
-
-
Watchdog timer
–
Yes
Yes
Yes
Yes
16
16
16
16
3.75
3.75
3.75
3.75
267 ns
FEATURE
No. of channels
MSPS
12-Bit ADC
1
267 ns
267 ns
267 ns
32-Bit CPU timers
Conversion time
–
3
3
3
3
Serial Peripheral Interface (SPI)
0
SPI-A/B
SPI-A/B
SPI-A
SPI-A
Serial Communications Interface (SCI)
0
SCI-A
SCI-A
SCI-A
SCI-A
Enhanced Controller Area Network (eCAN)
0
eCAN-A
eCAN-A
eCAN-A
-
Inter-Integrated Circuit (I2C)
0
I2C-A
I2C-A
I2C-A
I2C-A
Digital I/O pins (shared)
–
35
35
35
35
External interrupts
–
3
3
3
3
Supply voltage
–
1.8-V Core,
3.3-V I/O
1.8-V Core,
3.3-V I/O
1.8-V Core,
3.3-V I/O
1.8-V Core,
3.3-V I/O
100-Pin PZ
–
Yes
Yes
Yes
Yes
100-Ball GGM, ZGM
–
Yes
Yes
Yes
Yes
A: –40°C to 85°C
–
(PZ, GGM, ZGM)
(PZ, GGM, ZGM)
(PZ, GGM, ZGM)
(PZ, GGM, ZGM)
S: –40°C to 125°C
–
(PZ GGM, ZGM)
(PZ, GGM, ZGM)
(PZ, GGM, ZGM)
(PZ, GGM, ZGM)
Q: –40°C to 125°C
(AEC-Q100
Qualification)
–
(PZ)
(PZ)
(PZ)
(PZ)
Packaging
Temperature options
(1)
A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
C2000 real-time control peripherals reference guide and in the peripheral reference guides.
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7
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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6.1 Related Products
For information about other devices in this family of products, see the following links:
TMS320F2837xS Delfino™ Microcontrollers
The Delfino™ TMS320F2837xS is a powerful 32-bit floating-point microcontroller unit (MCU) designed for
advanced closed-loop control applications such as industrial drives and servo motor control; solar inverters and
converters; digital power; transportation; and power line communications. Complete development packages for
digital power and industrial drives are available as part of the powerSUITE and DesignDRIVE initiatives.
8
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Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801
TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
7 Terminal Configuration and Functions
7.1 Pin Diagrams
GPIO18/SPICLKA/SCITXDB
GPIO5/EPWM3B/SPICLKD/ECAP1
GPIO17/SPISOMIA/CANRXB/TZ6
GPIO4/EPWM3A
54
53
52
51
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
VSS
56
55
GPIO7/EPWM4B/SPISTED/ECAP2
GPIO19/SPISTEA/SCIRXDB
57
59
58
GPIO9/EPWM5B/SCITXDB/ECAP3
GPIO8/EPWM5A/CANTXB/ADCSOCAO
VDD
61
62
60
GPIO10/EPWM6A/CANRXB/ADCSOCBO
GPIO20/EQEP1A/SPISIMOC/CANTXB
VSS
64
63
XCLKOUT
VDDIO
66
65
VDD
GPIO21/EQEP1B/SPISOMIC/CANRXB
67
69
68
GPIO22/EQEP1S/SPICLKC/SCITXDB
GPIO11/EPWM6B/SCIRXDB/ECAP4
VSS
71
72
70
TMS
TDI
GPIO23/EQEP1I/SPISTEC/SCIRXDB
73
XRS
GPIO27/ECAP4/EQEP2S/SPISTEB
TCK
76
75
TDO
VSS
74
The TMS320F2809, TMS320F2808, TMS320F2808-Q1, TMS320F2806, TMS320F2806-Q1, TMS320F2802,
TMS320F2802-Q1, TMS320F2801, TMS320F2801-Q1, TMS320C2802, TMS320C2801, TMS320F28015,
TMS320F28015-Q1, and TMS320F28016, TMS320F28016-Q1 100-pin PZ low-profile quad flatpack (LQFP) pin
assignments are shown in Figure 7-1, Figure 7-2, Figure 7-3, and Figure 7-4. The 100-ball GGM and ZGM ball
grid array (BGA) terminal assignments are shown in Figure 7-5. Table 7-1 describes the function(s) of each pin.
50
49
GPIO16/SPISIMOA/CANTXB/TZ5
VSS
78
48
GPIO3/EPWM2B/SPISOMID
79
47
EMU0
80
46
GPIO0/EPWM1A
VDDIO
EMU1
VDDIO
81
45
GPIO2/EPWM2A
82
44
GPIO1/EPWM1B/SPISIMOD
GPIO24/ECAP1/EQEP2A/SPISIMOB
83
43
TRST
VDD
84
42
GPIO34
VDD
85
41
VSS
X2
VSS
86
40
VDD2A18
87
39
VSS2AGND
X1
VSS
88
38
ADCRESEXT
89
37
ADCREFP
XCLKIN
GPIO25/ECAP2/EQEP2B/SPISOMIB
90
36
ADCREFM
91
35
ADCREFIN
GPIO28/SCIRXDA/TZ5
VDD
92
34
ADCINB7
93
33
ADCINB6
VSS
94
32
ADCINB5
GPIO13/TZ2/CANRXB/SPISOMIB
VDD3VFL
95
31
ADCINB4
96
30
ADCINB3
TEST1
97
29
ADCINB2
TEST2
GPIO26/ECAP3/EQEP2I/SPICLKB
98
28
ADCINB1
99
27
100
26
ADCINB0
VDDAIO
24
ADCLO
VSSAIO
25
22
23
ADCINA1
ADCINA0
20
21
ADCINA2
19
ADCINA4
ADCINA3
17
18
ADCINA6
16
ADCINA7
ADCINA5
14
15
VSSA2
VDDA2
12
13
10
11
VSS
VDD1A18
9
GPIO15/TZ4/SCIRXDB/SPISTEB
VDD
VSS1AGND
7
8
GPIO31/CANTXA
GPIO14/TZ3/SCITXDB/SPICLKB
6
4
5
GPIO29/SCITXDA//TZ6
3
VDDIO
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO30/CANRXA
2
1
GPIO12/TZ1/CANTXB/SPISIMOB
VSS
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
77
Figure 7-1. TMS320F2809, TMS320F2808-Q1 100-Pin PZ LQFP (Top View)
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9
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com
GPIO18/SPICLKA/SCITXDB
GPIO5/EPWM3B/SPICLKD/ECAP1
GPIO17/SPISOMIA/TZ6
GPIO4/EPWM3A
54
53
52
51
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
VSS
56
55
GPIO7/EPWM4B/SPISTED/ECAP2
GPIO19/SPISTEA/SCIRXDB
57
59
58
GPIO9/EPWM5B/SCITXDB/ECAP3
GPIO8/EPWM5A/ADCSOCAO
VDD
61
62
60
GPIO10/EPWM6A/ADCSOCBO
GPIO20/EQEP1A/SPISIMOC
VSS
64
63
XCLKOUT
VDDIO
66
65
VDD
GPIO21/EQEP1B/SPISOMIC
67
69
68
GPIO22/EQEP1S/SPICLKC/SCITXDB
GPIO11/EPWM6B/SCIRXDB/ECAP4
VSS
71
72
70
TMS
TDI
GPIO23/EQEP1I/SPISTEC/SCIRXDB
73
XRS
GPIO27/ECAP4/EQEP2S/SPISTEB
TCK
76
75
TDO
VSS
74
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
50
49
GPIO16/SPISIMOA/TZ5
VSS
78
48
GPIO3/EPWM2B/SPISOMID
79
47
EMU0
80
46
GPIO0/EPWM1A
VDDIO
EMU1
VDDIO
81
45
GPIO2/EPWM2A
82
44
GPIO1/EPWM1B/SPISIMOD
GPIO24/ECAP1/EQEP2A/SPISIMOB
83
43
TRST
VDD
84
42
GPIO34
VDD
85
41
VSS
X2
VSS
86
40
VDD2A18
87
39
VSS2AGND
X1
VSS
88
38
ADCRESEXT
89
37
ADCREFP
XCLKIN
GPIO25/ECAP2/EQEP2B/SPISOMIB
90
36
ADCREFM
91
35
ADCREFIN
GPIO28/SCIRXDA/TZ5
VDD
92
34
ADCINB7
93
33
ADCINB6
VSS
94
32
ADCINB5
GPIO13/TZ2/SPISOMIB
VDD3VFL
95
31
ADCINB4
96
30
ADCINB3
TEST1
97
29
ADCINB2
TEST2
GPIO26/ECAP3/EQEP2I/SPICLKB
98
28
ADCINB1
99
27
100
26
ADCINB0
VDDAIO
24
25
ADCLO
VSSAIO
22
23
ADCINA1
ADCINA0
20
21
ADCINA2
19
ADCINA4
ADCINA3
17
18
ADCINA6
16
ADCINA7
ADCINA5
14
15
VSSA2
VDDA2
12
13
10
11
VSS
VDD1A18
9
GPIO15/TZ4/SCIRXDB/SPISTEB
VDD
VSS1AGND
7
8
GPIO31/CANTXA
GPIO14/TZ3/SCITXDB/SPICLKB
6
4
5
GPIO29/SCITXDA//TZ6
3
VDDIO
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO30/CANRXA
2
1
GPIO12/TZ1/SPISIMOB
VSS
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
77
Figure 7-2. TMS320F2806 100-Pin PZ LQFP (Top View)
10
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TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
GPIO18/SPICLKA
GPIO5/EPWM3B/ECAP1
GPIO17/SPISOMIA/TZ6
GPIO4/EPWM3A
54
53
52
51
GPIO6/EPWMSYNCI/EPWMSYNCO
VSS
56
55
GPIO7/ECAP2
GPIO19/SPISTEA
57
59
58
GPIO9
GPIO8/ADCSOCAO
VDD
61
62
60
GPIO10/ADCSOCBO
GPIO20/EQEP1A
VSS
64
63
XCLKOUT
VDDIO
66
65
VDD
GPIO21/EQEP1B
67
69
68
GPIO22/EQEP1S
GPIO11
VSS
71
72
70
TMS
TDI
GPIO23/EQEP1I
73
XRS
SPISTEB/GPIO27
TCK
76
75
TDO
VSS
74
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
50
49
GPIO16/SPISIMOA/TZ5
VSS
78
48
GPIO3/EPWM2B
79
47
EMU0
80
46
GPIO0/EPWM1A
VDDIO
EMU1
VDDIO
81
45
GPIO2/EPWM2A
82
44
GPIO1/EPWM1B
SPISIMOB/GPIO24/ECAP1
83
43
TRST
VDD
84
42
GPIO34
VDD
85
41
VSS
X2
VSS
86
40
VDD2A18
87
39
VSS2AGND
X1
VSS
88
38
ADCRESEXT
89
37
ADCREFP
XCLKIN
GPIO25/ECAP2/SPISOMIB
90
36
ADCREFM
91
35
ADCREFIN
GPIO28/SCIRXDA/TZ5
VDD
92
34
ADCINB7
93
33
ADCINB6
VSS
94
32
ADCINB5
SPISOMIB/GPIO13/TZ2
95
31
ADCINB4
VDD3VFL
TEST1
96
30
ADCINB3
97
29
ADCINB2
TEST2
SPICLKB/GPIO26
98
28
ADCINB1
99
27
100
26
ADCINB0
VDDAIO
24
ADCLO
VSSAIO
25
22
23
ADCINA1
ADCINA0
20
21
ADCINA2
19
ADCINA4
ADCINA3
17
18
ADCINA6
16
ADCINA7
ADCINA5
14
15
VSSA2
VDDA2
12
13
10
11
VSS
VDD1A18
9
SPISTEB/GPIO15/TZ4
VDD
VSS1AGND
7
8
GPIO31/CANTXA
6
SPICLKB/GPIO14/TZ3
4
5
GPIO29/SCITXDA//TZ6
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO30/CANRXA
3
VDDIO
1
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
2
(A)
77
SPISIMOB/GPIO12/TZ1
VSS
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
A. On the C280x devices, the VDD3VFL pin is VDDIO.
Figure 7-3. TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP (Top View)
Copyright © 2021 Texas Instruments Incorporated
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TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
11
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com
GPIO18/SPICLKA
GPIO5/EPWM3B/ECAP1
GPIO17/SPISOMIA/TZ6
GPIO4/EPWM3A
54
53
52
51
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
VSS
56
55
GPIO7/EPWM4B/ECAP2
GPIO19/SPISTEA
57
59
58
GPIO9
GPIO8/ADCSOCAO
VDD
61
62
60
GPIO10/ADCSOCBO
GPIO20
VSS
64
63
XCLKOUT
VDDIO
66
65
VDD
GPIO21
67
69
68
GPIO22
GPIO11
VSS
71
72
70
TMS
TDI
GPIO23
73
XRS
GPIO27
TCK
76
75
TDO
VSS
74
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
50
49
GPIO16/SPISIMOA/TZ5
VSS
78
48
GPIO3/EPWM2B
79
47
EMU0
80
46
GPIO0/EPWM1A
VDDIO
EMU1
VDDIO
81
45
GPIO2/EPWM2A
82
44
GPIO1/EPWM1B
GPIO24/ECAP1
83
43
TRST
VDD
84
42
GPIO34
VDD
85
41
VSS
X2
VSS
86
40
VDD2A18
87
39
VSS2AGND
X1
VSS
88
38
ADCRESEXT
89
37
ADCREFP
XCLKIN
GPIO25/ECAP2
90
36
ADCREFM
91
35
ADCREFIN
GPIO28/SCIRXDA/TZ5
VDD
92
34
ADCINB7
93
33
ADCINB6
VSS
94
32
ADCINB5
GPIO13/TZ2
95
31
ADCINB4
VDD3VFL
TEST1
96
30
ADCINB3
97
29
ADCINB2
TEST2
98
28
ADCINB1
GPIO26
99
27
100
26
ADCINB0
VDDAIO
24
ADCLO
VSSAIO
25
22
ADCINA2
23
20
21
ADCINA3
ADCINA1
19
ADCINA4
ADCINA0
17
18
ADCINA6
16
ADCINA7
ADCINA5
14
15
VSSA2
VDDA2
12
13
VDD1A18
VSS1AGND
10
11
VSS
9
GPIO15/TZ4
VDD
7
6
8
GPIO31/CANTXA
GPIO14/TZ3
(A)
4
5
GPIO29/SCITXDA//TZ6
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
(A)
3
VDDIO
GPIO30/CANRXA
2
1
GPIO12/TZ1
VSS
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
77
A. CANTXA (pin 7) and CANRXA (pin 6) pins are not applicable for the TMS320F28015.
Figure 7-4. TMS320F2801x 100-Pin PZ LQFP (Top View)
12
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TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
K
VSSAIO
ADCINB0
ADCINB3
ADCINB5
ADCINB7
VSS2AGND
GPIO1
GPIO0
VSS
GPIO16
J
ADCLO
VDDAIO
ADCINB1
ADCINB4
ADCREFIN
VDD2A18
GPIO2
GPIO3
GPIO4
GPIO17
H
ADCINA1
ADCINA0
ADCINB2
ADCINB6
ADCREFM
VSS
VDDIO
GPIO18
GPIO5
VSS
G
ADCINA4
ADCINA3
ADCINA2
ADCINA5
ADCREFP
VDD
GPIO34
GPIO7
GPIO6
GPIO19
F
VSSA2
VDDA2
ADCINA7
ADCINA6
ADCRESEXT
GPIO20
VSS
GPIO9
GPIO8
VDD
E
GPIO15
VDD
VSS
VDD1A18
VSS1AGND
X1
GPIO21
XCLKOUT
VDDIO
GPIO10
D
GPIO31
GPIO30
GPIO14
VDD
GPIO28
VSS
VDD
GPIO22
GPIO11
VSS
C
GPIO33
VDDIO
GPIO29
VDD3VFL
GPIO25
X2
GPIO24
GPIO27
TDI
GPIO23
B
VSS
GPIO12
TEST2
GPIO13
XCLKIN
VDD
EMU1
XRS
TDO
TMS
A
GPIO32
GPIO26
TEST1
VSS
VSS
TRST
VDDIO
EMU0
VSS
TCK
1
2
3
4
5
6
7
8
9
10
Bottom View
Figure 7-5. TMS320F2809, TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801, TMS320F28016,
TMS320F28015, TMS320C2802, TMS320C2801 100-Ball GGM and ZGM MicroStar BGA™ (Bottom View)
Copyright © 2021 Texas Instruments Incorporated
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TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
13
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
www.ti.com
7.2 Signal Descriptions
Table 7-1 describes the signals. All digital inputs are TTL-compatible. All outputs are 3.3 V with CMOS levels.
Inputs are not 5-V tolerant.
Table 7-1. Signal Descriptions
PIN NO.
NAME
PZ
PIN #
GGM/
ZGM
BALL #
DESCRIPTION (1)
JTAG
TRST
84
A6
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the
operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active
high test pin and must be maintained low at all times during normal device operation. An external
pulldown resistor is required on this pin. The value of this resistor should be based on drive strength
of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate
protection. Since this is application-specific, it is recommended that each target board be validated
for proper operation of the debugger and the application. (I, ↓)
TCK
75
A10
JTAG test clock with internal pullup (I, ↑)
TMS
74
B10
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. (I, ↑)
TDI
73
C9
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
or data) on a rising edge of TCK. (I, ↑)
TDO
76
B9
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are
shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
A8
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the device
into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low
state, a rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA
drive ↑)
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.
B7
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the device
into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low
state, a rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA
drive ↑)
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.
EMU0
EMU1
80
81
FLASH
VDD3VFL
96
C4
3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times. On the ROM
parts (C280x), this pin should be connected to VDDIO.
TEST1
97
A3
Test Pin. Reserved for TI. Must be left unconnected. (I/O)
TEST2
98
B3
Test Pin. Reserved for TI. Must be left unconnected. (I/O)
CLOCK
XCLKOUT
66
E8
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0
(XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal
can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is not
placed in high-impedance state during a reset. (O/Z, 8 mA drive).
XCLKIN
90
B5
External Oscillator Input. This pin is used to feed a clock from an external 3.3-V oscillator. In this
case, tie the X1 pin to GND. Alternately, when a crystal/resonator is used (or if an external 1.8-V
oscillator is fed into the X1 pin), tie the XCLKIN pin to GND. (I)
14
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TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
Table 7-1. Signal Descriptions (continued)
PIN NO.
NAME
PZ
PIN #
GGM/
ZGM
BALL #
DESCRIPTION (1)
X1
88
E6
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic
resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital
power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN
pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must
be tied to GND. (I)
X2
86
C6
Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and
X2. If X2 is not used it must be left unconnected. (O)
B8
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑)
The output buffer of this pin is an open-drain with an internal pullup. If this pin is driven by an
external device, it should be done using an open-drain device.
RESET
XRS
78
ADC SIGNALS
ADCINA7
16
F3
ADC Group A, Channel 7 input (I)
ADCINA6
17
F4
ADC Group A, Channel 6 input (I)
ADCINA5
18
G4
ADC Group A, Channel 5 input (I)
ADCINA4
19
G1
ADC Group A, Channel 4 input (I)
ADCINA3
20
G2
ADC Group A, Channel 3 input (I)
ADCINA2
21
G3
ADC Group A, Channel 2 input (I)
ADCINA1
22
H1
ADC Group A, Channel 1 input (I)
ADCINA0
23
H2
ADC Group A, Channel 0 input (I)
ADCINB7
34
K5
ADC Group B, Channel 7 input (I)
ADCINB6
33
H4
ADC Group B, Channel 6 input (I)
ADCINB5
32
K4
ADC Group B, Channel 5 input (I)
ADCINB4
31
J4
ADC Group B, Channel 4 input (I)
ADCINB3
30
K3
ADC Group B, Channel 3 input (I)
ADCINB2
29
H3
ADC Group B, Channel 2 input (I)
ADCINB1
28
J3
ADC Group B, Channel 1 input (I)
ADCINB0
27
K2
ADC Group B, Channel 0 input (I)
ADCLO
24
J1
Low Reference (connect to analog ground) (I)
ADCRESEXT
38
F5
ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.
ADCREFIN
35
J5
External reference input (I)
ADCREFP
37
G5
Internal Reference Positive Output. Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of
2.2 μF to analog ground. (O)
NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is
used in the system.
ADCREFM
36
H5
Internal Reference Medium Output. Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of
2.2 μF to analog ground. (O)
NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is
used in the system.
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Table 7-1. Signal Descriptions (continued)
PIN NO.
PZ
PIN #
GGM/
ZGM
BALL #
15
F2
ADC Analog Power Pin (3.3 V)
VSSA2
14
F1
ADC Analog Ground Pin
VDDAIO
26
J2
ADC Analog I/O Power Pin (3.3 V)
NAME
DESCRIPTION (1)
CPU AND I/O POWER PINS
VDDA2
VSSAIO
25
K1
ADC Analog I/O Ground Pin
VDD1A18
12
E4
ADC Analog Power Pin (1.8 V)
VSS1AGND
13
E5
ADC Analog Ground Pin
VDD2A18
40
J6
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
VSS2AGND
39
K6
VDD
10
E2
VDD
42
G6
VDD
59
F10
VDD
68
D7
VDD
85
B6
VDD
93
D4
VDDIO
3
C2
VDDIO
46
H7
VDDIO
65
E9
VDDIO
82
A7
VSS
2
B1
VSS
11
E3
VSS
41
H6
VSS
49
K9
VSS
55
H10
VSS
62
F7
VSS
69
D10
VSS
77
A9
VSS
87
D6
VSS
89
A5
VSS
94
A4
CPU and Logic Digital Power Pins (1.8 V)
Digital I/O Power Pin (3.3 V)
Digital Ground Pins
GPIOA AND PERIPHERAL SIGNALS (2) (3)
GPIO0
EPWM1A
GPIO1
EPWM1B
SPISIMOD
GPIO2
EPWM2A
-
16
47
44
45
K8
General-purpose input/output 0 (I/O/Z) (4)
Enhanced PWM1 Output A and HRPWM channel (O)
-
K7
General-purpose input/output 1 (I/O/Z)(4)
Enhanced PWM1 Output B (O)
SPI-D slave in, master out (I/O) (not available on 2801, 2802)
-
J7
General-purpose input/output 2 (I/O/Z)(4)
Enhanced PWM2 Output A and HRPWM channel (O)
-
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
Table 7-1. Signal Descriptions (continued)
PIN NO.
NAME
GPIO3
EPWM2B
SPISOMID
GPIO4
EPWM3A
GPIO5
EPWM3B
SPICLKD
ECAP1
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO
GPIO7
EPWM4B
SPISTED
ECAP2
GPIO8
EPWM5A
CANTXB
ADCSOCAO
GPIO9
EPWM5B
SCITXDB
ECAP3
GPIO10
EPWM6A
CANRXB
ADCSOCBO
GPIO11
EPWM6B
SCIRXDB
ECAP4
GPIO12
TZ1
CANTXB
SPISIMOB
GPIO13
TZ2
CANRXB
SPISOMIB
GPIO14
TZ3
SCITXDB
SPICLKB
GPIO15
TZ4
SCIRXDB
SPISTEB
GPIO16
SPISIMOA
CANTXB
TZ5
PZ
PIN #
48
51
53
56
58
60
61
64
70
1
95
8
9
50
GGM/
ZGM
BALL #
DESCRIPTION (1)
J8
General-purpose input/output 3 (I/O/Z)(4)
Enhanced PWM2 Output B (O)
SPI-D slave out, master in (I/O) (not available on 2801, 2802)
-
J9
General-purpose input/output 4 (I/O/Z)(4)
Enhanced PWM3 output A and HRPWM channel (O)
-
H9
General-purpose input/output 5 (I/O/Z)(4)
Enhanced PWM3 output B (O)
SPI-D clock (I/O) (not available on 2801, 2802)
Enhanced capture input/output 1 (I/O)
G9
General-purpose input/output 6 (I/O/Z)(4)
Enhanced PWM4 output A and HRPWM channel (O) (not available on 2801, 2802)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
G8
General-purpose input/output 7 (I/O/Z)(4)
Enhanced PWM4 output B (O) (not available on 2801, 2802)
SPI-D slave transmit enable (I/O) (not available on 2801, 2802)
Enhanced capture input/output 2 (I/O)
F9
General-purpose input/output 8 (I/O/Z)(4)
Enhanced PWM5 output A and HRPWM channel (O) (not available on 2801, 2802)
Enhanced CAN-B transmit (O) (not available on 2801, 2802, F2806)
ADC start-of-conversion A (O)
F8
General-purpose input/output 9 (I/O/Z)(4)
Enhanced PWM5 output B (O) (not available on 2801, 2802)
SCI-B transmit data (O) (not available on 2801, 2802)
Enhanced capture input/output 3 (I/O) (not available on 2801, 2802)
E10
General-purpose input/output 10 (I/O/Z)(4)
Enhanced PWM6 output A and HRPWM channel (O) (not available on 2801, 2802)
Enhanced CAN-B receive (I) (not available on 2801, 2802, F2806)
ADC start-of-conversion B (O)
D9
General-purpose input/output 11 (I/O/Z)(4)
Enhanced PWM6 output B (O) (not available on 2801, 2802)
SCI-B receive data (I) (not available on 2801, 2802)
Enhanced CAP Input/Output 4 (I/O) (not available on 2801, 2802)
B2
General-purpose input/output 12 (I/O/Z)(5)
Trip Zone input 1 (I)
Enhanced CAN-B transmit (O) (not available on 2801, 2802, F2806)
SPI-B Slave in, Master out (I/O)
B4
General-purpose input/output 13 (I/O/Z)(5)
Trip zone input 2 (I)
Enhanced CAN-B receive (I) (not available on 2801, 2802, F2806)
SPI-B slave out, master in (I/O)
D3
General-purpose input/output 14 (I/O/Z)(5)
Trip zone input 3 (I)
SCI-B transmit (O) (not available on 2801, 2802)
SPI-B clock input/output (I/O)
E1
General-purpose input/output 15 (I/O/Z)(5)
Trip zone input 4 (I)
SCI-B receive (I) (not available on 2801, 2802)
SPI-B slave transmit enable (I/O)
K10
General-purpose input/output 16 (I/O/Z)(5)
SPI-A slave in, master out (I/O)
Enhanced CAN-B transmit (O) (not available on 2801, 2802, F2806)
Trip zone input 5 (I)
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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Table 7-1. Signal Descriptions (continued)
PIN NO.
NAME
GPIO17
SPISOMIA
CANRXB
TZ6
GPIO18
SPICLKA
SCITXDB
GPIO19
SPISTEA
SCIRXDB
GPIO20
EQEP1A
SPISIMOC
CANTXB
GPIO21
EQEP1B
SPISOMIC
CANRXB
GPIO22
EQEP1S
SPICLKC
SCITXDB
GPIO23
EQEP1I
SPISTEC
SCIRXDB
GPIO24
ECAP1
EQEP2A
SPISIMOB
GPIO25
ECAP2
EQEP2B
SPISOMIB
GPIO26
ECAP3
EQEP2I
SPICLKB
GPIO27
ECAP4
EQEP2S
SPISTEB
GPIO28
SCIRXDA
TZ5
GPIO29
SCITXDA
TZ6
18
PZ
PIN #
52
54
57
63
67
71
72
83
91
99
79
92
4
GGM/
ZGM
BALL #
DESCRIPTION (1)
J10
General-purpose input/output 17 (I/O/Z)(5)
SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (I) (not available on 2801, 2802, F2806)
Trip zone input 6 (I)
H8
General-purpose input/output 18 (I/O/Z)(5)
SPI-A clock input/output (I/O)
SCI-B transmit (O) (not available on 2801, 2802)
-
G10
General-purpose input/output 19 (I/O/Z)(5)
SPI-A slave transmit enable input/output (I/O)
SCI-B receive (I) (not available on 2801, 2802)
-
F6
General-purpose input/output 20 (I/O/Z)(5)
Enhanced QEP1 input A (I)
SPI-C slave in, master out (I/O) (not available on 2801, 2802)
Enhanced CAN-B transmit (O) (not available on 2801, 2802, F2806)
E7
General-purpose input/output 21 (I/O/Z)(5)
Enhanced QEP1 input A (I)
SPI-C master in, slave out (I/O) (not available on 2801, 2802)
Enhanced CAN-B receive (I) (not available on 2801, 2802, F2806)
D8
General-purpose input/output 22 (I/O/Z)(5)
Enhanced QEP1 strobe (I/O)
SPI-C clock (I/O) (not available on 2801, 2802)
SCI-B transmit (O) (not available on 2801, 2802)
C10
General-purpose input/output 23 (I/O/Z)(5)
Enhanced QEP1 index (I/O)
SPI-C slave transmit enable (I/O) (not available on 2801, 2802)
SCI-B receive (I) (not available on 2801, 2802)
C7
General-purpose input/output 24 (I/O/Z)(5)
Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I) (not available on 2801, 2802)
SPI-B slave in, master out (I/O)
C5
General-purpose input/output 25 (I/O/Z)(5)
Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I) (not available on 2801, 2802)
SPI-B master in, slave out (I/O)
A2
General-purpose input/output 26 (I/O/Z)(5)
Enhanced capture 3 (I/O) (not available on 2801, 2802)
Enhanced QEP2 index (I/O) (not available on 2801, 2802)
SPI-B clock (I/O)
C8
General-purpose input/output 27 (I/O/Z)(5)
Enhanced capture 4 (I/O) (not available on 2801, 2802)
Enhanced QEP2 strobe (I/O) (not available on 2801, 2802)
SPI-B slave transmit enable (I/O)
D5
General-purpose input/output 28. This pin has an 8-mA (typical) output buffer. (I/O/Z)(5)
SCI receive data (I)
Trip zone input 5 (I)
C3
General-purpose input/output 29. This pin has an 8-mA (typical) output buffer. (I/O/Z)(5)
SCI transmit data (O)
Trip zone 6 input (I)
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
Table 7-1. Signal Descriptions (continued)
PIN NO.
NAME
GPIO30
CANRXA
GPIO31
CANTXA
GPIO32
SDAA
EPWMSYNCI
ADCSOCAO
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO
GPIO34
(1)
(2)
(3)
(4)
(5)
PZ
PIN #
6
7
100
5
43
GGM/
ZGM
BALL #
DESCRIPTION (1)
D2
General-purpose input/output 30. This pin has an 8-mA (typical) output buffer. (I/O/Z)(5)
Enhanced CAN-A receive data (I)
-
D1
General-purpose input/output 31. This pin has an 8-mA (typical) output buffer. (I/O/Z)(5)
Enhanced CAN-A transmit data (O)
-
A1
General-purpose input/output 32 (I/O/Z)(5)
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion (O)
C1
General-Purpose Input/Output 33 (I/O/Z)(5)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion (O)
G7
General-Purpose Input/Output 34 (I/O/Z)(5)
-
I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown
Some peripheral functions may not be available in TMS320F2801x devices. See Table 6-2 for details.
All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively enabled/
disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at reset. The
peripheral signals that are listed under them are alternate functions.
The pullups on GPIO0-GPIO11 pins are not enabled at reset.
The pullups on GPIO12-GPIO34 are enabled upon reset.
Note
Some peripheral functions may not be available in TMS320F2801x devices. See Table 6-2 for details.
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
8 Specifications
This section provides the absolute maximum ratings and the recommended operating conditions.
8.1 Absolute Maximum Ratings
Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges. (1) (2)
MIN
MAX
VDDIO, VDD3VFL with respect to VSS
–0.3
4.6
VDDA2, VDDAIO with respect to VSSA
–0.3
4.6
VDD with respect to VSS
–0.3
2.5
VDD1A18, VDD2A18 with respect to VSSA
–0.3
2.5
VSSA2, VSSAIO, VSS1AGND, VSS2AGND with respect
to VSS
–0.3
0.3
VIN
–0.3
4.6
Output voltage
VO
–0.3
4.6
V
Input clamp current
IIK (VIN < 0 or VIN > VDDIO)(3)
–20
20
mA
mA
Supply voltage
Input voltage
Output clamp current
UNIT
V
V
IOK (VO < 0 or VO > VDDIO)
–20
20
A version (GGM, ZGM, PZ)(4)
–40
85
S version (GGM, ZGM, PZ)(4)
–40
125
Q version (PZ)(4)
–40
125
Junction temperature
TJ (4)
–40
150
°C
Storage temperature
Tstg (4)
–65
150
°C
Operating ambient temperature, TA
(1)
(2)
(3)
(4)
20
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 8.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
Continuous clamp current per pin is ±2 mA. This includes the analog inputs which have an internal clamping circuit that clamps the
voltage to a diode drop above VDDA2 or below VSSA2.
Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall
device life. For additional information, see Semiconductor and IC package thermal metrics.
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
8.2 ESD Ratings – Automotive
VALUE
UNIT
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28016, and
TMS320F28015 in 100-pin PZ package
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC-Q100-002(1)
±2000
Charged device model (CDM),
per AEC-Q100-011
All pins
±500
Corner pins on 100-pin PZ:
1, 25, 26, 50, 51, 75, 76, 100
±750
V
AEC-Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
8.3 ESD Ratings – Commercial
VALUE
UNIT
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28016, and
TMS320F28015 in 100-ball ZGM package
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
±500
V
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28016, and
TMS320F28015 in 100-ball GGM package
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Device supply voltage, I/O, VDDIO
3.14
3.3
3.47
V
Device supply voltage CPU, VDD
1.71
1.8
1.89
Supply ground, VSS, VSSIO
0
V
V
ADC supply voltage (3.3 V), VDDA2, VDDAIO
3.14
3.3
3.47
V
ADC supply voltage (1.8 V), VDD1A18, VDD2A18
1.71
1.8
1.89
V
3.14
3.3
3.47
V
100
MHz
MHz
Flash supply voltage, VDD3VFL
Device clock frequency (system clock),
fSYSCLKOUT
100-MHz devices
2
60-MHz devices
2
60
High-level input voltage, VIH
All inputs except X1
2
VDDIO + 0.3
0.7 * VDD – 0.05
VDD
Low-level input voltage, VIL
All inputs except X1
VSS – 0.3
0.8
X1
X1
High-level output source current,
VOH = 2.4 V, IOH
Low-level output sink current,
VOL = VOL MAX, IOL
All I/Os except Group 2
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Group
V
0.3 * VDD + 0.05
All I/Os except Group 2
Group
V
–4
2(1)
mA
–8
4
2(1)
mA
8
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
over operating free-air temperature range (unless otherwise noted)
MIN
Ambient temperature, TA
(1)
22
NOM
MAX
A version
–40
85
S version
–40
125
Q version
(AEC-Q100
Qualification)
–40
125
UNIT
°C
Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, and EMU1
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
8.5 Power Consumption Summary
8.5.1 TMS320F2809, TMS320F2808 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
MODE
TEST CONDITIONS
IDDIO (1)
IDD
IDD3VFL (2)
IDDA18 (3)
IDDA33 (4)
TYP(5)
MAX(6)
TYP(5)
MAX(6)
TYP
MAX(6)
TYP(5)
MAX(6)
TYP(5)
MAX(6)
195 mA
230 mA
15 mA
27 mA
35 mA
40 mA
30 mA
38 mA
1.5 mA
2 mA
IDLE
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
•
eCAN-A
•
SCI-A
•
SPI-A
•
I2C
75 mA
90 mA
500 μA
2 mA
2 μA
10 μA
5 μA
50 μA
15 μA
30 μA
STANDBY
Flash is powered down.
Peripheral clocks are off.
6 mA
12 mA
100 μA
500 μA
2 μA
10 μA
5 μA
50 μA
15 μA
30 μA
HALT
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.
70 μA
60 μA
120 μA
2 μA
10 μA
5 μA
50 μA
15 μA
30 μA
The following peripheral
clocks are enabled:
•
ePWM1/2/3/4/5/6
•
eCAP1/2/3/4
•
eQEP1/2
•
eCAN-A
•
SCI-A/B
•
SPI-A
•
ADC
•
I2C
Operational
(Flash)
(1)
(2)
(3)
(4)
(5)
(6)
All PWM pins are toggled
at 100 kHz.
All I/O pins are left
unconnected.
Data is continuously
transmitted out of the
SCI-A, SCI-B, and
eCAN-A ports. The
hardware multiplier is
exercised.
Code is running out of
flash with 3 wait-states.
XCLKOUT is turned off.
IDDIO current is dependent on the electrical loading on the I/O pins.
The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Section 8.14.6.3. If the user
application involves on-board flash programming, this extra current must be taken into account while architecting the power-supply
stage.
IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
IDDA33 includes current into VDDA2 and VDDAIO pins.
TYP numbers are applicable over room temperature and nominal voltage.
MAX numbers are at 125°C and MAX voltage.
Note
The peripheral - I/O multiplexing implemented in the 280x devices prevents all available peripherals
from being used at the same time. This is because more than one peripheral function may share an
I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although
such a configuration is not useful. If this is done, the current drawn by the device will be more than the
numbers specified in the current consumption tables.
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
8.5.2 TMS320F2806 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
MODE
TEST CONDITIONS
IDDIO (1)
IDD
IDD3VFL (2)
IDDA18 (3)
IDDA33 (4)
TYP(5)
MAX(6)
TYP(5)
MAX(6)
TYP(5)
MAX(6)
TYP(5)
MAX(6)
TYP(5)
MAX(6)
195 mA
230 mA
15 mA
27 mA
35 mA
40 mA
30 mA
38 mA
1.5 mA
2 mA
IDLE
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
•
eCAN-A
•
SCI-A
•
SPI-A
•
I2C
75 mA
90 mA
500 μA
2 mA
2 μA
10 μA
5 μA
50 μA
15 μA
30 μA
STANDBY
Flash is powered down.
Peripheral clocks are off.
6 mA
12 mA
100 μA
500 μA
2 μA
10 μA
5 μA
50 μA
15 μA
30 μA
HALT
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.
70 μA
60 μA
120 μA
2 μA
10 μA
5 μA
50 μA
15 μA
30 μA
Operational
(Flash)
(1)
(2)
(3)
(4)
(5)
(6)
The following peripheral
clocks are enabled:
•
ePWM1/2/3/4/5/6
•
eCAP1/2/3/4
•
eQEP1/2
•
eCAN-A
•
SCI-A/B
•
SPI-A
•
ADC
•
I2C
All PWM pins are toggled at
100 kHz.
All I/O pins are left
unconnected.
Data is continuously
transmitted out of the SCI-A,
SCI-B, and eCAN-A ports.
The hardware multiplier is
exercised.
Code is running out of flash
with 3 wait-states.
XCLKOUT is turned off
IDDIO current is dependent on the electrical loading on the I/O pins.
The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Section 8.14.6.3. If the user
application involves on-board flash programming, this extra current must be taken into account while architecting the power-supply
stage.
IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
IDDA33 includes current into VDDA2 and VDDAIO pins.
TYP numbers are applicable over room temperature and nominal voltage.
MAX numbers are at 125°C and MAX voltage.
Note
The peripheral - I/O multiplexing implemented in the 280x devices prevents all available peripherals
from being used at the same time. This is because more than one peripheral function may share an
I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although
such a configuration is not useful. If this is done, the current drawn by the device will be more than the
numbers specified in the current consumption tables.
24
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
8.5.3 TMS320F2802, TMS320F2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
MODE
TEST CONDITIONS
IDDIO (1)
IDD
IDD3VFL (2)
IDDA18 (3)
IDDA33 (4)
TYP(5)
MAX(6)
TYP(5)
MAX(6)
TYP(5)
MAX(6)
TYP(5)
MAX(6)
TYP(5)
MAX(6)
180 mA
210 mA
15 mA
27 mA
35 mA
40 mA
30 mA
38 mA
1.5 mA
2 mA
IDLE
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
•
eCAN-A
•
SCI-A
•
SPI-A
•
I2C
75 mA
90 mA
500 μA
2 mA
2 μA
10 μA
5 μA
50 μA
15 μA
30 μA
STANDBY
Flash is powered down.
Peripheral clocks are off.
6 mA
12 mA
100 μA
500 μA
2 μA
10 μA
5 μA
50 μA
15 μA
30 μA
HALT
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.
70 μA
60 μA
120 μA
2 μA
10 μA
5 μA
50 μA
15 μA
30 μA
Operational
(Flash)
(1)
(2)
(3)
(4)
(5)
(6)
The following peripheral
clocks are enabled:
•
ePWM1/2/3
•
eCAP1/2
•
eQEP1
•
eCAN-A
•
SCI-A
•
SPI-A
•
ADC
•
I2C
All PWM pins are toggled at
100 kHz.
All I/O pins are left
unconnected.
Data is continuously
transmitted out of the SCI-A,
SCI-B, and eCAN-A ports.
The hardware multiplier is
exercised.
Code is running out of flash
with 3 wait-states.
XCLKOUT is turned off.
IDDIO current is dependent on the electrical loading on the I/O pins.
The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Section 8.14.6.3. If the user
application involves on-board flash programming, this extra current must be taken into account while architecting the power-supply
stage.
IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
IDDA33 includes current into VDDA2 and VDDAIO pins.
TYP numbers are applicable over room temperature and nominal voltage.
MAX numbers are at 125°C and MAX voltage.
Note
The peripheral - I/O multiplexing implemented in the 280x devices prevents all available peripherals
from being used at the same time. This is because more than one peripheral function may share an
I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although
such a configuration is not useful. If this is done, the current drawn by the device will be more than the
numbers specified in the current consumption tables.
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
8.5.4 TMS320C2802, TMS320C2801 Current Consumption by Power-Supply Pins at
100-MHz SYSCLKOUT
MODE
TEST CONDITIONS
IDDIO (1)
IDD
IDDA18 (2)
IDDA33 (3)
TYP(4)
MAX(5)
TYP(4)
MAX(5)
TYP(4)
MAX(5)
TYP(4)
MAX(5)
150 mA
165 mA
5 mA
10 mA
30 mA
38 mA
1.5 mA
2 mA
IDLE
XCLKOUT is turned off.
The following peripheral clocks
are enabled:
•
eCAN-A
•
SCI-A
•
SPI-A
•
I2C
75 mA
90 mA
500 μA
2 mA
5 μA
50 μA
15 μA
30 μA
STANDBY
Peripheral clocks are off.
6 mA
12 mA
100 μA
500 μA
5 μA
50 μA
15 μA
30 μA
HALT
Peripheral clocks are off.
Input clock is disabled.
70 μA
80 μA
120 μA
5 μA
50 μA
15 μA
30 μA
Operational
(ROM)
The following peripheral clocks
are enabled:
•
ePWM1/2/3
•
eCAP1/2
•
eQEP1
•
eCAN-A
•
SCI-A
•
SPI-A
•
ADC
•
I2C
All PWM pins are toggled at
100 kHz.
All I/O pins are left unconnected.
Data is continuously transmitted
out of the SCI-A, SCI-B, and
eCAN-A ports. The hardware
multiplier is exercised.
Code is running out of ROM with
3 wait-states.
XCLKOUT is turned off.
(1)
(2)
(3)
(4)
(5)
IDDIO current is dependent on the electrical loading on the I/O pins.
IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
IDDA33 includes current into VDDA2 and VDDAIO pins.
TYP numbers are applicable over room temperature and nominal voltage.
MAX numbers are at 125°C and MAX voltage.
Note
The peripheral - I/O multiplexing implemented in the 280x devices prevents all available peripherals
from being used at the same time. This is because more than one peripheral function may share an
I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although
such a configuration is not useful. If this is done, the current drawn by the device will be more than the
numbers specified in the current consumption tables.
26
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
8.5.5 Reducing Current Consumption
280x devices have a richer peripheral mix compared to the 281x family. While the McBSP has been removed,
the following new peripherals have been added on the 280x:
• 3 SPI modules
• 1 CAN module
• 1 I2C module
The two event manager modules of the 281x have been enhanced and replaced with separate ePWM (6), eCAP
(4) and eQEP (2) modules, providing tremendous flexibility in applications. Like 281x, 280x DSPs incorporate a
unique method to reduce the device current consumption. Since each peripheral unit has an individual clockenable bit, significant reduction in current consumption can be achieved by turning off the clock to any peripheral
module that is not used in a given application. Furthermore, any one of the three low-power modes could be
taken advantage of to reduce the current consumption even further. Table 8-1 indicates the typical reduction in
current consumption achieved by turning off the clocks.
Table 8-1. Typical Current Consumption by Various
Peripherals (at 100 MHz)
(1)
(2)
(3)
PERIPHERAL
MODULE(1)
IDD CURRENT
REDUCTION (mA)(2)
ADC
8(3)
I2C
5
eQEP
5
ePWM
5
eCAP
2
SCI
4
SPI
5
eCAN
11
All peripheral clocks are disabled upon reset. Writing to/reading
from peripheral registers is possible only after the peripheral
clocks are turned on.
For peripherals with multiple instances, the current quoted is per
module. For example, the 5 mA number quoted for ePWM is for
one ePWM module.
This number represents the current drawn by the digital portion
of the ADC module. Turning off the clock to the ADC module
results in the elimination of the current drawn by the analog
portion of the ADC (IDDA18) as well.
Note
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
Note
The baseline IDD current (current when the core is executing a dummy loop with no peripherals
enabled) is 110 mA, typical. To arrive at the IDD current for a given application, the current-drawn by
the peripherals (enabled by that application) must be added to the baseline IDD current.
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
8.5.6 Current Consumption Graphs
250.0
Current (mA)
200.0
150.0
100.0
50.0
0.0
10
20
30
40
50
60
70
80
90
100
SYSCLKOUT (MHz)
IDD
IDDA18
1.8-V current
IDDIO
IDD3VFL
3.3-V current
Figure 8-1. Typical Operational Current Versus Frequency (F2808)
600.0
500.0
Device Power (mW)
400.0
300.0
200.0
100.0
0.0
10
20
30
40
50
60
70
80
90
100
SYSCLKOUT (MHz)
TOTAL POWER
Figure 8-2. Typical Operational Power Versus Frequency (F2808)
Note
Typical operational current for 60-MHz devices can be estimated from Figure 8-1. For IDD current
alone, subtract the current contribution of non-existent peripherals after scaling the peripheral currents
for 60 MHz. For example, to compute the current of F2801-60 device, the contribution by the following
peripherals must be subtracted from IDD: ePWM4/5/6, eCAP3/4, eQEP2, SCI-B.
28
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
Current Vs SYSCLKOUT
200
180
Current (mA)
160
140
120
100
80
60
40
20
0
10
20
30
40
50
60
70
80
90
10
SYSCLKOUT (MHz)
IDD
IDDA18
1.8v current
IDDIO
IDD3VFL
3.3v current
Figure 8-3. Typical Operational Current Versus Frequency (C280x)
Device Power (mW)
Device Power Vs SYSCLKOUT
400.0
300.0
200.0
100.0
0.0
10
20
30
40
50
60
70
80
90
100
SYSCLKOUT (MHz)
TOTAL POWER
Figure 8-4. Typical Operational Power Versus Frequency (C280x)
8.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
Copyright © 2021 Texas Instruments Incorporated
TEST CONDITIONS
IOH = IOH MAX
IOH = 50 μA
MIN
TYP
MAX
2.4
V
VDDIO – 0.2
IOL = IOL MAX
UNIT
0.4
V
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
over recommended operating conditions (unless otherwise noted)
PARAMETER
IIL
IIH
Input current
(low level)
Input current
(high level)
TEST CONDITIONS
TYP
MAX
–140
–190
VDDIO = 3.3 V, VIN = 0 V
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = 0 V
±2
Pin with pullup
enabled
VDDIO = 3.3 V, VIN = VDDIO
±2
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = VDDIO (F280x)
28
50
80
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = VDDIO (C280x)
80
140
190
Output current, pullup or pulldown
VO = VDDIO or 0 V
disabled
CI
Input capacitance
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All I/Os (including XRS)
–80
UNIT
μA
IOZ
30
MIN
Pin with pullup
enabled
±2
2
μA
μA
pF
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
8.7 Thermal Resistance Characteristics for F280x 100-Ball GGM Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
12.08
N/A
RΘJB
Junction-to-board thermal resistance
16.46
N/A
RΘJA
(High k PCB)
PsiJT
(1)
(2)
Junction-to-free air thermal resistance
Junction-to-package top
30.58
0
29.31
150
28.09
250
26.62
500
0.4184
0
0.32
150
0.3725
250
0.4887
500
These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
8.8 Thermal Resistance Characteristics for F280x 100-Pin PZ Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
12.89
N/A
RΘJB
Junction-to-board thermal resistance
29.58
N/A
48.16
0
40.06
150
37.96
250
RΘJA
(High k PCB)
PsiJT
(1)
(2)
Junction-to-free air thermal resistance
Junction-to-package top
35.17
500
0.3425
0
0.85
150
1.0575
250
1.410
500
These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
8.9 Thermal Resistance Characteristics for C280x 100-Ball GGM Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
14.18
N/A
RΘJB
Junction-to-board thermal resistance
21.36
N/A
RΘJA
(High k PCB)
PsiJT
(1)
(2)
Junction-to-free air thermal resistance
Junction-to-package top
36.33
0
35.01
150
33.81
250
32.31
500
0.57
0
0.43
150
0.52
250
0.67
500
These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
8.10 Thermal Resistance Characteristics for C280x 100-Pin PZ Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
13.52
N/A
RΘJB
Junction-to-board thermal resistance
54.78
N/A
69.81
0
60.34
150
57.46
250
53.63
500
0.42
0
1.23
150
1.54
250
2.11
500
RΘJA
(High k PCB)
PsiJT
(1)
(2)
32
Junction-to-free air thermal resistance
Junction-to-package top
These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
8.11 Thermal Resistance Characteristics for F2809 100-Ball GGM Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
10.36
N/A
RΘJB
Junction-to-board thermal resistance
13.3
N/A
RΘJA
(High k PCB)
PsiJT
(1)
(2)
Junction-to-free air thermal resistance
Junction-to-package top
28.15
0
26.89
150
25.68
250
24.22
500
0.38
0
0.35
150
0.33
250
0.44
500
These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
8.12 Thermal Resistance Characteristics for F2809 100-Pin PZ Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
7.06
N/A
RΘJB
Junction-to-board thermal resistance
28.76
N/A
44.02
0
28.34
150
36.28
250
33.68
500
0.2
0
0.56
150
0.7
250
0.95
500
RΘJA
(High k PCB)
PsiJT
(1)
(2)
Junction-to-free air thermal resistance
Junction-to-package top
These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
8.13 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems with
more than 1 Watt power dissipation may require a product level thermal design. Care should be taken to keep Tj
within specified limits. In the end applications, Tcase should be measured to estimate the operating junction
temperature Tj. Tcase is normally measured at the center of the package top side surface. The thermal
application note Semiconductor and IC package thermal metrics helps to understand the thermal metrics and
definitions.
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8.14 Timing and Switching Characteristics
8.14.1 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
f
fall time
X
Unknown, changing, or don't care level
h
hold time
Z
High impedance
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
8.14.1.1 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For
actual cycle examples, see the appropriate cycle description section of this document.
8.14.1.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
42 W
Data Sheet Timing Reference Point
3.5 nH
Transmission Line
(A)
Output
Under
Test
Z0 = 50 W
4.0 pF
Device Pin
1.85 pF
(B)
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line
effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer)
from the data sheet timing.
Figure 8-5. 3.3-V Test Load Circuit
34
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8.14.1.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 280x DSPs. Section 8.14.1.3.1 and Section 8.14.1.3.2 list the cycle times of various clocks.
8.14.1.3.1 TMS320x280x Clock Table and Nomenclature (100-MHz Devices)
MIN
On-chip oscillator
clock
XCLKIN(1)
SYSCLKOUT
XCLKOUT
HSPCLK(2)
LSPCLK(2)
tc(OSC), Cycle time
UNIT
50
ns
20
35
MHz
tc(CI), Cycle time
10
250
ns
4
100
MHz
10
500
ns
Frequency
tc(SCO), Cycle time
2
100
MHz
tc(XCO), Cycle time
Frequency
10
2000
ns
Frequency
0.5
100
MHz
tc(HCO), Cycle time
10
50(3)
Frequency
tc(LCO), Cycle time
20(3)
10
25(3)
Frequency
100
MHz
ns
100
80
MHz
ns
Frequency (All devices except F2809)
tc(ADCCLK), Cycle time (F2809)
ns
40(3)
12.5
40
MHz
ns
Frequency (F2809)
(1)
(2)
(3)
MAX
Frequency
tc(ADCCLK), Cycle time (All devices except F2809)
ADC clock
NOM
28.6
25
MHz
MAX
UNIT
This also applies to the X1 pin if a 1.8-V oscillator is used.
Lower LSPCLK and HSPCLK will reduce device power consumption.
This is the default reset value if SYSCLKOUT = 100 MHz.
8.14.1.3.2 TMS320x280x/2801x Clock Table and Nomenclature (60-MHz Devices)
MIN
On-chip oscillator
clock
XCLKIN(1)
SYSCLKOUT
XCLKOUT
HSPCLK(2)
LSPCLK(2)
ADC clock
(1)
(2)
(3)
tc(OSC), Cycle time
Frequency
tc(CI), Cycle time
Frequency
tc(SCO), Cycle time
Frequency
tc(XCO), Cycle time
Frequency
tc(HCO), Cycle time
28.6
50
ns
20
35
MHz
16.67
250
ns
4
60
MHz
16.67
500
ns
2
60
MHz
16.67
2000
0.5
60
MHz
60
MHz
60
MHz
7.5
MHz
16.67
16.67
ns
ns
66.7(3)
15(3)
Frequency
tc(ADCCLK), Cycle time
33.3(3)
30(3)
Frequency
tc(LCO), Cycle time
NOM
ns
133.33
ns
Frequency
This also applies to the X1 pin if a 1.8-V oscillator is used.
Lower LSPCLK and HSPCLK will reduce device power consumption.
This is the default reset value if SYSCLKOUT = 60 MHz.
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8.14.2 Power Sequencing
No requirements are placed on the power up/down sequence of the various power pins to ensure the correct
reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers of the I/O pins
are powered prior to the 1.8-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur
on the pin during power up. To avoid this behavior, power the VDD (core voltage) pins prior to or simultaneously
with the VDDIO (input/output voltage) pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins
reach 0.7 V.
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for tw(RSL1) after the input clock is stable (see Section
8.14.2.1). This is to enable the entire device to start from a known condition.
2. During power down, the XRS pin must be pulled low at least 8 μs prior to VDD reaching 1.5 V. This is to
enhance flash reliability.
No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for analog pins, it is
0.7 V above VDDA) prior to powering up the device. Voltages applied to pins on an unpowered device can bias
internal p-n junctions in unintended ways and produce unpredictable results.
36
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8.14.2.1 Reset ( XRS) Timing Requirements
MIN
tw(RSL1)
(1)
Pulse duration, stable XCLKIN to XRS high
tw(RSL2)
Pulse duration, XRS low
tw(WDRS)
Pulse duration, reset pulse generated by
watchdog
td(EX)
Delay time, address/data valid after XRS high
tOSCST
(2)
UNIT
8tc(OSCCLK)
cycles
cycles
512tc(OSCCLK)
cycles
32tc(OSCCLK)
cycles
1
Hold time for boot-mode pins
MAX
8tc(OSCCLK)
Oscillator start-up time
th(boot-mode)
(1)
(2)
Warm reset
NOM
10
200tc(OSCCLK)
ms
cycles
In addition to the tw(RSL1) requirement, XRS has to be low at least for 1 ms after VDD reaches 1.5 V.
Dependent on crystal/resonator and board design.
XCLKIN
X1/X2
OSCCLK/8
XCLKOUT
User-Code Dependent
OSCCLK * 5
tw(RSL2)
XRS
Address/Data/
Control
(Internal)
td(EX)
User-Code Execution
(Don’t Care)
Boot-ROM Execution Starts
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Execution Phase
GPIO Pins as Input
th(boot-mode)(A)
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
Figure 8-6. Warm Reset
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Figure 8-7 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004
and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is
written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is
complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating frequency, OSCCLK x
4.
OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
OSCCLK/2
OSCCLK * 4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, tp) is
131072 OSCCLK Cycles Long.)
(Changed CPU Frequency)
Figure 8-7. Example of Effect of Writing Into PLLCR Register
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8.14.3 Clock Requirements and Characteristics
8.14.3.1 Input Clock Frequency
PARAMETER
MIN
Resonator (X1/X2)
Crystal (X1/X2)
fx
Input clock frequency
fl
Limp mode SYSCLKOUT frequency range (with /2 enabled)
External oscillator/clock
source (XCLKIN or X1 pin)
TYP
MAX UNIT
20
35
20
35
100-MHz device
4
100
60-MHz device
4
MHz
60
1–5
MHz
8.14.3.2 XCLKIN Timing Requirements - PLL Enabled
NO.(1)
MIN
C8
tc(CI)
Cycle time, XCLKIN
C9
tf(CI)
Fall time, XCLKIN
C10
tr(CI)
Rise time, XCLKIN
C11
tw(CIL)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
45%
55%
C12
tw(CIH)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45%
55%
MIN
MAX UNIT
(1)
33.3
MAX UNIT
200
ns
6
ns
6
ns
This applies to the X1 pin also.
8.14.3.3 XCLKIN Timing Requirements - PLL Disabled
NO.(1)
C8
tc(CI)
Cycle time, XCLKIN
C9
tf(CI)
Fall time, XCLKIN
C10
tr(CI)
Rise time, XCLKIN
100-MHz device
60-MHz device
10
250
16.67
250
ns
Up to 20 MHz
6
ns
20 MHz to 100 MHz
2
ns
Up to 20 MHz
6
ns
20 MHz to 100 MHz
2
ns
C11
tw(CIL)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
45%
55%
C12
tw(CIH)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45%
55%
The possible configuration modes are shown in Table 9-33.
8.14.3.4 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
NO.
PARAMETER
(1) (2)
MIN
100-MHz device
tc(XCO)
Cycle time, XCLKOUT
C3
tf(XCO)
Fall time, XCLKOUT
C4
tr(XCO)
Rise time, XCLKOUT
C5
tw(XCOL)
Pulse duration, XCLKOUT low
H–2
tw(XCOH)
Pulse duration, XCLKOUT high
H–2
tp
PLL lock time
C6
(1)
(2)
(3)
MAX
10
C1
60-MHz device
TYP
UNIT
ns
16.67
2
ns
2
ns
H+2
H+2
131072tc(OSCCLK) (3)
ns
ns
cycles
A load of 40 pF is assumed for these parameters.
H = 0.5tc(XCO)
OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
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C10
C9
C8
XCLKIN(A)
C1
C6
C3
C4
C5
XCLKOUT(B)
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate
the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 8-8. Clock Timing
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8.14.4 Peripherals
8.14.4.1 General-Purpose Input/Output (GPIO)
8.14.4.1.1 GPIO - Output Timing
8.14.4.1.1.1 General-Purpose Output Switching Characteristics
PARAMETER
tr(GPO)
MIN
Rise time, GPIO switching low to high
All GPIOs
tf(GPO)
Fall time, GPIO switching high to low
All GPIOs
tfGPO
Toggling frequency, GPO pins
MAX
UNIT
8
ns
8
ns
25
MHz
GPIO
tr(GPO)
tf(GPO)
Figure 8-9. General-Purpose Output Timing
8.14.4.1.2 GPIO - Input Timing
8.14.4.1.2.1 General-Purpose Input Timing Requirements
MIN
tw(SP)
Sampling period
tw(IQSW)
Input qualifier sampling window
tw(GPI) (2)
Pulse duration, GPIO low/high
(1)
(2)
MAX
UNIT
QUALPRD = 0
1tc(SCO)
QUALPRD ≠ 0
2tc(SCO) * QUALPRD
cycles
tw(SP) * (n(1) – 1)
cycles
Synchronous mode
With input qualifier
cycles
2tc(SCO)
cycles
tw(IQSW) + tw(SP) + 1tc(SCO)
cycles
"n" represents the number of qualification samples as defined by GPxQSELn register.
For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
tw(SP)
0
0
0
1
1
1
1
1
1
1
1
1
Sampling Period determined
by GPxCTRL[QUALPRD](B)
tw(IQSW)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5(C))
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in
2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).
B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
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D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other
words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to
occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 8-10. Sampling Mode
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8.14.4.1.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0
SYSCLK
GPIOxn
tw(GPI)
Figure 8-11. General-Purpose Input Timing
Note
The pulse-width requirement for general-purpose input is applicable for the XINT2_ADCSOC signal as
well.
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8.14.4.1.4 Low-Power Mode Wakeup Timing
Section 8.14.4.1.4.1 shows the timing requirements, Section 8.14.4.1.4.2 shows the switching characteristics,
and Figure 8-12 shows the timing diagram for IDLE mode.
8.14.4.1.4.1 IDLE Mode Timing Requirements
MIN(1)
tw(WAKE-INT)
(1)
Pulse duration, external wake-up signal
Without input qualifier
MAX
2tc(SCO)
With input qualifier
UNIT
cycles
5tc(SCO) + tw(IQSW)
For an explanation of the input qualifier parameters, see Section 8.14.4.1.2.1.
8.14.4.1.4.2 IDLE Mode Switching Characteristics
PARAMETER(1)
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, external wake signal to program
execution resume (2)
•
td(WAKE-IDLE)
•
•
Wake-up from Flash
– Flash module in active state
Wake-up from Flash
– Flash module in sleep state
Wake-up from SARAM
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
(1)
(2)
20tc(SCO)
20tc(SCO) + tw(IQSW)
1050tc(SCO)
1050tc(SCO) + tw(IQSW)
20tc(SCO)
20tc(SCO) + tw(IQSW)
cycles
cycles
cycles
For an explanation of the input qualifier parameters, see Section 8.14.4.1.2.1.
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
td(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE−INT)
WAKE
INT(A)
A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 8-12. IDLE Entry and Exit Timing
44
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8.14.4.1.4.3 STANDBY Mode Timing Requirements
TEST CONDITIONS
tw(WAKE-INT)
(1)
Pulse duration, external
wake-up signal
MIN
Without input qualification
With input qualification(1)
MAX
3tc(OSCCLK)
UNIT
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
QUALSTDBY is a 6-bit field in the LPMCR0 register.
8.14.4.1.4.4 STANDBY Mode Switching Characteristics
PARAMETER
td(IDLE-XCOL)
TEST CONDITIONS
Delay time, IDLE instruction
executed to XCLKOUT low
MIN
MAX
UNIT
32tc(SCO)
45tc(SCO)
cycles
Delay time, external wake signal to
program execution resume(1)
•
td(WAKE-STBY)
•
•
Wake up from flash
Without input qualifier
– Flash module in active state With input qualifier
Wake up from flash
– Flash module in sleep state
100tc(SCO)
100tc(SCO) + tw(WAKE-INT)
Without input qualifier
1125tc(SCO)
With input qualifier
1125tc(SCO) + tw(WAKE-INT)
Without input qualifier
Wake up from SARAM
100tc(SCO)
With input qualifier
(1)
100tc(SCO) + tw(WAKE-INT)
cycles
cycles
cycles
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
(A)
(C)
(B)
Device
Status
STANDBY
(E)
(D)
(F)
STANDBY
Normal Execution
Flushing Pipeline
Wake−up
Signal
tw(WAKE-INT)
td(WAKE-STBY)
X1/X2 or
X1 or
XCLKIN
XCLKOUT
td(IDLE−XCOL)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles (if CLKINDIV = 0) or 64 cycles (if
CLKINDIV = 1) before being turned off. This delay enables the CPU pipe and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode.
D. The external wake-up signal is driven active.
E. After a latency period, the STANDBY mode is exited.
F. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 8-13. STANDBY Entry and Exit Timing Diagram
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8.14.4.1.4.5 HALT Mode Timing Requirements
MIN
tw(WAKE-GPIO)
Pulse duration, GPIO wake-up signal
tw(WAKE-XRS)
Pulse duration, XRS wakeup signal
(1)
MAX
UNIT
toscst + 2tc(OSCCLK) (1)
cycles
toscst + 8tc(OSCCLK)
cycles
See Section 8.14.2.1 for an explanation of toscst.
8.14.4.1.4.6 HALT Mode Switching Characteristics
PARAMETER
td(IDLE-XCOL)
Delay time, IDLE instruction executed to XCLKOUT low
tp
PLL lock-up time
td(WAKE-HALT)
Delay time, PLL lock to program execution resume
• Wake up from flash
– Flash module in sleep state
•
MIN
MAX
UNIT
32tc(SCO)
45tc(SCO)
cycles
131072tc(OSCCLK)
cycles
1125tc(SCO)
cycles
35tc(SCO)
cycles
Wake up from SARAM
(A)
(C)
Device
Status
(D)
HALT
Flushing Pipeline
(G)
(E)
(B)
(F)
HALT
PLL Lock-up Time
Wake-up Latency
Normal
Execution
GPIOn
td(WAKE−HALT)
tw(WAKE-GPIO)
tp
X1/X2
or XCLKIN
Oscillator Start-up Time
XCLKOUT
td(IDLE−XCOL)
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for approximately 32 cycles (if CLKINDIV = 0) or 64 cycles (if
CLKINDIV = 1) before the oscillator is turned off and the CLKIN to the core is stopped. This delay enables the CPU pipe and any other
pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence
is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal
during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup process, care should be taken
to maintain a low noise environment prior to entering and during HALT mode.
E. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 131,072 OSCCLK (X1/X2 or X1 or XCLKIN) cycles.
Note that these 131,072 clock cycles are applicable even when the PLL is disabled (that is, code execution will be delayed by this
duration even when the PLL is disabled).
F. Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the interrupt (if enabled), after
a latency.
G. Normal operation resumes.
Figure 8-14. HALT Wake-Up Using GPIOn
46
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8.14.4.2 Enhanced Control Peripherals
8.14.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
PWM refers to PWM outputs on ePWM1–6. Section 8.14.4.2.1.1 shows the PWM timing requirements and
Section 8.14.4.2.1.2, switching characteristics.
8.14.4.2.1.1 ePWM Timing Requirements
TEST CONDITIONS(1)
tw(SYCIN)
Sync input pulse width
MAX
UNIT
Asynchronous
2tc(SCO)
cycles
Synchronous
2tc(SCO)
cycles
1tc(SCO) + tw(IQSW)
cycles
With input qualifier
(1)
MIN
For an explanation of the input qualifier parameters, see Section 8.14.4.1.2.1.
8.14.4.2.1.2 ePWM Switching Characteristics
PARAMETER
tw(PWM)
TEST CONDITIONS
MIN
Pulse duration, PWMx output high/low
tw(SYNCOUT)
Sync output pulse width
td(PWM)tza
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
MAX
20
UNIT
ns
8tc(SCO)
cycles
no pin load
25
ns
20
ns
MAX
UNIT
8.14.4.2.2 Trip-Zone Input Timing
8.14.4.2.2.1 Trip-Zone input Timing Requirements
MIN(1)
tw(TZ)
Pulse duration, TZx input low
Asynchronous
1tc(SCO)
cycles
Synchronous
2tc(SCO)
cycles
1tc(SCO) + tw(IQSW)
cycles
With input qualifier
(1)
For an explanation of the input qualifier parameters, see Section 8.14.4.1.2.1.
SYSCLK
tw(TZ)
(A)
TZ
td(TZ-PWM)HZ
(B)
PWM
A. TZ: TZ1, TZ2, TZ3, TZ4 , TZ5, TZ6
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.
Figure 8-15. PWM Hi-Z Characteristics
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8.14.4.2.3 High-Resolution PWM Timing
Section 8.14.4.2.3.1 shows the high-resolution PWM switching characteristics.
8.14.4.2.3.1 High-Resolution PWM Characteristics at SYSCLKOUT = 60–100 MHz
MIN
Micro Edge Positioning (MEP) step
(1)
size(1)
TYP
MAX
UNIT
150
310
ps
The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
8.14.4.2.4 Enhanced Capture (eCAP) Timing
Section 8.14.4.2.4.1 shows the eCAP timing requirement and Section 8.14.4.2.4.2 shows the eCAP switching
characteristics.
8.14.4.2.4.1 Enhanced Capture (eCAP) Timing Requirement
TEST CONDITIONS(1)
tw(CAP)
Capture input pulse width
Asynchronous
2tc(SCO)
Synchronous
2tc(SCO)
With input qualifier
(1)
MIN
MAX
UNIT
cycles
1tc(SCO) + tw(IQSW)
For an explanation of the input qualifier parameters, see Section 8.14.4.1.2.1.
8.14.4.2.4.2 eCAP Switching Characteristics
PARAMETER
tw(APWM)
TEST CONDITIONS
MIN
Pulse duration, APWMx output high/low
MAX
20
UNIT
ns
8.14.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
Section 8.14.4.2.5.1 shows the eQEP timing requirement and Section 8.14.4.2.5.2 shows the eQEP switching
characteristics.
8.14.4.2.5.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
TEST CONDITIONS(1)
tw(QEPP)
QEP input period
tw(INDEXH)
QEP Index Input High time
tw(INDEXL)
QEP Index Input Low time
tw(STROBH)
QEP Strobe High time
tw(STROBL)
QEP Strobe Input Low time
(1)
(2)
MIN
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO)
With input qualifier
2tc(SCO)
cycles
2tc(SCO) +tw(IQSW)
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO)
cycles
2tc(SCO) + tw(IQSW)
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO)
cycles
2tc(SCO) + tw(IQSW)
Asynchronous(2)/synchronous
UNIT
cycles
2[1tc(SCO) + tw(IQSW)]
Asynchronous(2)/synchronous
With input qualifier
MAX
2tc(SCO)
cycles
2tc(SCO) +tw(IQSW)
For an explanation of the input qualifier parameters, see Section 8.14.4.1.2.1.
Refer to the TMS320F280x, TMS320C280x, TMS320F2801x DSPs silicon errata for limitations in the asynchronous mode.
8.14.4.2.5.2 eQEP Switching Characteristics
PARAMETER
td(CNTR)xin
48
TEST CONDITIONS
MIN
Delay time, external clock to counter increment
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MAX
UNIT
4tc(SCO)
cycles
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PARAMETER
td(PCS-OUT)QEP
TEST CONDITIONS
MIN
Delay time, QEP input edge to position compare sync output
Copyright © 2021 Texas Instruments Incorporated
MAX
UNIT
6tc(SCO)
cycles
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8.14.4.2.6 ADC Start-of-Conversion Timing
8.14.4.2.6.1 External ADC Start-of-Conversion Switching Characteristics
PARAMETER
tw(ADCSOCAL)
MIN
Pulse duration, ADCSOCAO low
MAX
32tc(HCO )
UNIT
cycles
tw(ADCSOCAL)
ADCSOCAO
or
ADCSOCBO
Figure 8-16. ADCSOCAO or ADCSOCBO Timing
8.14.4.3 External Interrupt Timing
8.14.4.3.1 External Interrupt Timing Requirements
MIN(1)
tw(INT) (2)
(1)
(2)
Pulse duration, INT input low/high
Synchronous
1tc(SCO)
With qualifier
1tc(SCO) + tw(IQSW)
MAX
UNIT
cycles
For an explanation of the input qualifier parameters, see Section 8.14.4.1.2.1.
This timing is applicable to any GPIO pin configured for ADCSOC functionality.
8.14.4.3.2 External Interrupt Switching Characteristics
PARAMETER(1)
td(INT)
(1)
Delay time, INT low/high to interrupt-vector fetch
MIN
MAX
UNIT
tw(IQSW) + 12tc(SCO)
cycles
For an explanation of the input qualifier parameters, see Section 8.14.4.1.2.1.
tw(INT)
XNMI, XINT1, XINT2
td(INT)
Address bus
(internal)
Interrupt Vector
Figure 8-17. External Interrupt Timing
50
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8.14.4.4 I2C Electrical Specification and Timing
8.14.4.4.1 I2C Timing
TEST CONDITIONS
fSCL
SCL clock frequency
Vil
Low level input voltage
Vih
High level input voltage
MIN
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
MAX
UNIT
400
kHz
0.3 VDDIO
0.7 VDDIO
V
V
Vhys
Input hysteresis
Vol
Low level output voltage
3 mA sink current
tLOW
Low period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
1.3
μs
tHIGH
High period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
0.6
μs
lI
Input current with an input voltage
between 0.1 VDDIO and 0.9 VDDIO MAX
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0.05 VDDIO
0
–10
V
0.4
10
V
μA
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8.14.4.5 Serial Peripheral Interface (SPI) Timing
This section contains both Master Mode and Slave Mode timing data.
8.14.4.5.1 SPI Master Mode Timing
Section 8.14.4.5.1.1 lists the master mode timing (clock phase = 0) and Section 8.14.4.5.1.2 lists the master
mode timing (clock phase = 1). Figure 8-18 and Figure 8-19 show the timing waveforms.
8.14.4.5.1.1 SPI Master Mode External Timing (Clock Phase = 0)
NO.(5)
BRR EVEN
(4) (3) (2)
PARAMETER
(1)
1
(1)
(2)
(3)
(4)
(5)
52
tc(SPC)M
Cycle time, SPICLK
2
tw(SPC1)M
Pulse duration, SPICLK first
pulse
3
tw(SPC2)M
Pulse duration, SPICLK second
pulse
4
td(SIMO)M
Delay time, SPICLK to
SPISIMO valid
5
tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK
8
tsu(SOMI)M
Setup time, SPISOMI before
SPICLK
9
th(SOMI)M
Hold time, SPISOMI valid after
SPICLK
23
td(SPC)M
24
td(STE)M
BRR ODD
MIN
MAX
MIN
MAX
4tc(LSPCLK)
128tc(LSPCLK)
UNIT
5tc(LSPCLK)
127tc(LSPCLK)
ns
0.5tc(SPC)M – 10
0.5tc(SPC)M + 0.5tc(LSPCLK)
0.5tc(SPC)M + 10
– 10
0.5tc(SPC)M +
0.5tc(LSPCLK) + 10
ns
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M –
0.5tc(LSPCLK) + 10
ns
10
ns
10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
ns
35
35
ns
0
0
ns
Delay time, SPISTE active to
SPICLK
1.5tc(SPC)M –
3tc(SYSCLK) – 10
1.5tc(SPC)M –
3tc(SYSCLK) – 10
ns
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)M – 10
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
ns
The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
tc(LCO) = LSPCLK cycle time
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
23
24
SPISTE
Figure 8-18. SPI Master Mode External Timing (Clock Phase = 0)
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8.14.4.5.1.2 SPI Master Mode External Timing (Clock Phase = 1)
NO.(1)
BRR EVEN
(2) (3) (4)
PARAMETER
(5)
1
(1)
(2)
(3)
(4)
(5)
BRR ODD
MIN
MAX
4tc(LSPCLK)
UNIT
MIN
MAX
128tc(LSPCLK)
5tc(LSPCLK)
127tc(LSPCLK)
ns
0.5tc(SPC)M –
0.5tc(LSPCLK) + 10
ns
0.5tc(SPC)M +
0.5tc(LSPCLK) + 10
ns
tc(SPC)M
Cycle time, SPICLK
2
tw(SPC1)M
Pulse duration, SPICLK first
pulse
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M –
0.5tc(LSPCLK) – 10
3
tw(SPC2)M
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M +
0.5tc(LSPCLK) – 10
6
td(SIMO)M
Delay time, SPISIMO valid to
SPICLK
0.5tc(SPC)M – 10
0.5tc(SPC)M +
0.5tc(LSPCLK) – 10
ns
7
tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M – 10
0.5tc(SPC)M –
0.5tc(LSPCLK) – 10
ns
10
tsu(SOMI)M
Setup time, SPISOMI before
SPICLK
35
35
ns
11
th(SOMI)M
Hold time, SPISOMI valid after
SPICLK
0
0
ns
23
td(SPC)M
Delay time, SPISTE active to
SPICLK
2tc(SPC)M –
3tc(SYSCLK) – 10
2tc(SPC)M –
3tc(SYSCLK) – 10
ns
24
td(STE)M
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC) – 10
0.5tc(SPC) –
0.5tc(LSPCLK) – 10
ns
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
Master Out Data Is Valid
SPISIMO
10
11
Master In Data Must
Be Valid
SPISOMI
24
23
SPISTE
Figure 8-19. SPI Master Mode External Timing (Clock Phase = 1)
54
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8.14.4.5.2 SPI Slave Mode Timing
Section 8.14.4.5.2.1 lists the slave mode timing (clock phase = 0) and Section 8.14.4.5.2.2 lists the slave mode
timing (clock phase = 1). Figure 8-20 and Figure 8-21 show the timing waveforms.
8.14.4.5.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
NO.
(1) (2)
PARAMETER
(4) (3)
MIN
MAX
UNIT
(5)
12
tc(SPC)S
Cycle time, SPICLK
4tc(SYSCLK)
13
tw(SPC1)S
Pulse duration, SPICLK first pulse
2tc(SYSCLK) – 1
ns
14
tw(SPC2)S
Pulse duration, SPICLK second pulse
2tc(SYSCLK) – 1
ns
15
td(SOMI)S
Delay time, SPICLK to SPISOMI valid
16
tv(SOMI)S
Valid time, SPISOMI data valid after SPICLK
ns
35
ns
0
ns
19
tsu(SIMO)S
Setup time, SPISIMO valid before SPICLK
1.5tc(SYSCLK)
ns
20
th(SIMO)S
Hold time, SPISIMO data valid after SPICLK
1.5tc(SYSCLK)
ns
25
tsu(STE)S
Setup time, SPISTE active before SPICLK
1.5tc(SYSCLK)
ns
26
th(STE)S
Hold time, SPISTE inactive after SPICLK
1.5tc(SYSCLK)
ns
(1)
(2)
(3)
(4)
(5)
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
tc(LCO) = LSPCLK cycle time
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
SPISOMI
16
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
25
26
SPISTE
Figure 8-20. SPI Slave Mode External Timing (Clock Phase = 0)
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8.14.4.5.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
NO.
(1) (2)
PARAMETER
(3) (4)
MIN
MAX
UNIT
12
tc(SPC)S
Cycle time, SPICLK
13
tw(SPC1)S
14
tw(SPC2)S
17
td(SOMI)S
Delay time, SPICLK to SPISOMI valid
18
tv(SOMI)S
Valid time, SPISOMI data valid after SPICLK
21
tsu(SIMO)S
Setup time, SPISIMO valid before SPICLK
22
th(SIMO)S
Hold time, SPISIMO data valid after SPICLK
1.5tc(SYSCLK)
ns
25
tsu(STE)S
Setup time, SPISTE active before SPICLK
1.5tc(SYSCLK)
ns
26
th(STE)S
Hold time, SPISTE inactive after SPICLK
1.5tc(SYSCLK)
ns
(1)
(2)
(3)
(4)
4tc(SYSCLK)
ns
Pulse duration, SPICLK first pulse
2tc(SYSCLK) – 1
ns
Pulse duration, SPICLK second pulse
2tc(SYSCLK) – 1
ns
35
ns
0
ns
1.5tc(SYSCLK)
ns
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
SPISOMI
Data Valid
SPISOMI Data Is Valid
Data Valid
18
21
22
SPISIMO Data
Must Be Valid
SPISIMO
26
25
SPISTE
Figure 8-21. SPI Slave Mode External Timing (Clock Phase = 1)
56
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
8.14.5 Emulator Connection Without Signal Buffering for the DSP
Figure 8-22 shows the connection between the DSP and JTAG header for a single-processor configuration. If the
distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals must be
buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 8-22 shows the simpler,
no-buffering situation. For the pullup/pulldown resistor values, see Section 7.2.
6 inches or less
VDDIO
EMU0
EMU1
TRST
TMS
TDI
TDO
TCK
VDDIO
13
14
2
1
3
7
11
9
EMU0
PD
5
EMU1
TRST
GND
TMS
GND
TDI
GND
TDO
GND
TCK
GND
4
6
8
10
12
TCK_RET
DSP
JTAG Header
Figure 8-22. Emulator Connection Without Signal Buffering for the DSP
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8.14.6 Flash Timing
8.14.6.1 Flash Endurance for A and S Temperature Material
ERASE/PROGRAM
TEMPERATURE(1)
Nf
Flash endurance for the array (write/erase cycles)
0°C to 85°C (ambient)
NOTP
OTP endurance for the array (write cycles)
0°C to 85°C (ambient)
(1)
MIN
TYP
20000
50000
MAX
UNIT
cycles
1
write
Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
8.14.6.2 Flash Endurance for Q Temperature Material
ERASE/PROGRAM
TEMPERATURE(1)
Nf
Flash endurance for the array (write/erase cycles)
–40°C to 125°C (ambient)
NOTP
OTP endurance for the array (write cycles)
–40°C to 125°C (ambient)
(1)
MIN
TYP
20000
50000
MAX
UNIT
cycles
1
write
Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
8.14.6.3 Flash Parameters at 100-MHz SYSCLKOUT
PARAMETER
TEST CONDITIONS
16-Bit Word
Program
Time(1)
500
250
2000(2)
ms
125
2000(2)
ms
2
15(2)
s
8K Sector
2
15(2)
s
4K Sector
2
15(2)
IDDP (4)
VDD current consumption during Erase/
Program cycle
IDDIOP (4)
VDDIO current consumption during Erase/
Program cycle
(4)
μs
8K Sector
VDD3VFL current consumption during the Erase/
Program cycle
(2)
(3)
UNIT
16K Sector
IDD3VFLP (4)
(1)
MAX
2000(2)
16K Sector
Erase
TYP
50
4K Sector
Time(3)
MIN
ms
s
Erase
75
mA
Program
35
mA
140
mA
20
mA
Program time is at the maximum device frequency. The programming time indicated in this table is applicable only when all the
required code/data is available in the device RAM, ready for programming. Program time includes overhead of the flash state machine
but does not include the time to transfer the following into RAM:
• the code that uses flash API to program the flash
• the Flash API itself
• Flash data to be programmed
The parameters mentioned in the MAX column are for the first 100 Erase/Program cycles.
The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
before programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brownout or interruption to power during erasing/
programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during flash
programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed during
the programming process.
8.14.6.4 Flash/OTP Access Timing
PARAMETER
MIN
MAX
UNIT
ta(fp)
Paged flash access time
36
ns
ta(fr)
Random flash access time
36
ns
58
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PARAMETER
ta(OTP)
MIN
OTP access time
MAX
60
UNIT
ns
8.14.6.5 Flash Data Retention Duration
PARAMETER
tretention
TEST CONDITIONS
Data retention duration
MIN
TJ = 55°C
15
MAX
UNIT
years
Table 8-2. Minimum Required Flash/OTP Wait-States at Different Frequencies
SYSCLKOUT
(MHz)
(1)
SYSCLKOUT (ns)
FLASH PAGE
WAIT-STATE
FLASH RANDOM
WAIT-STATE(1)
OTP WAIT-STATE
100
10
3
3
5
75
13.33
2
2
4
60
16.67
2
2
3
50
20
1
1
2
30
33.33
1
1
1
25
40
0
1
1
15
66.67
0
1
1
4
250
0
1
1
Random wait-state must be greater than or equal to 1.
Equations to compute the Flash page wait-state and random wait-state in Table 8-2 are as follows:
Flash Page Wait-State +
ƪǒ Ǔ ƫ
ƪǒ Ǔ ƫ
ta(fp)
t c(SCO)
Flash Random Wait-State +
*1
ta(fr)
t c(SCO)
(round up to the next highest integer) or 0, whichever is larger
* 1 (round up to the next highest integer) or 1, whichever is larger
Equation to compute the OTP wait-state in Table 8-2 is as follows:
OTP Wait-State +
ƪǒ
ta(OTP)
t c(SCO)
Ǔ ƫ
* 1 (round up to the next highest integer) or 1, whichever is larger
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
8.15 On-Chip Analog-to-Digital Converter
8.15.1 ADC Electrical Characteristics
over recommended operating conditions
PARAMETER(1) (2)
MIN
TYP
MAX
UNIT
DC SPECIFICATIONS
Resolution
12
ADC clock
Bits
60-MHz device
0.001
7.5
100-MHz device
0.001
12.5
100-MHz device (F2809 only)
0.001
25
MHz
ACCURACY
1–12.5 MHz ADC clock (6.25 MSPS)
INL (Integral nonlinearity)
±1.5
12.5–25 MHz ADC clock (12.5 MSPS)
±2
DNL (Differential nonlinearity)(3)
Offset
error(4)
–60
Offset error with hardware trimming
Overall gain error with internal
±1
LSB
+60
LSB
±4
reference(5)
Overall gain error with external reference
LSB
LSB
–60
+60
LSB
–60
+60
LSB
Channel-to-channel offset variation
±4
LSB
Channel-to-channel gain variation
±4
LSB
ANALOG INPUT
Analog input voltage (ADCINx to ADCLO)(6)
0
ADCLO
–5
Input capacitance
0
3
V
5
mV
10
Input leakage current
pF
±5
μA
INTERNAL VOLTAGE REFERENCE (5)
VADCREFP - ADCREFP output voltage at the pin
based on internal reference
1.275
V
VADCREFM - ADCREFM output voltage at the pin
based on internal reference
0.525
V
0.75
V
Voltage difference, ADCREFP - ADCREFM
Temperature coefficient
50
PPM/°C
EXTERNAL VOLTAGE REFERENCE (5) (7)
VADCREFIN - External reference voltage input on
ADCREFIN pin 0.2% or better accurate
reference recommended
ADCREFSEL[15:14] = 11b
1.024
V
ADCREFSEL[15:14] = 10b
1.500
V
ADCREFSEL[15:14] = 01b
2.048
V
67.5
dB
AC SPECIFICATIONS
SINAD (100 kHz) Signal-to-noise ratio +
distortion
SNR (100 kHz) Signal-to-noise ratio
68
dB
THD (100 kHz) Total harmonic distortion
–79
dB
ENOB (100 kHz) Effective number of bits
10.9
Bits
83
dB
SFDR (100 kHz) Spurious free dynamic range
(1)
(2)
(3)
(4)
(5)
60
Tested at 12.5 MHz ADCCLK.
All voltages listed in this table are with respect to VSSA2.
TI specifies that the ADC will have no missing codes.
1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
A single internal/external band gap reference sources both ADCREFP and ADCREFM signals, and hence, these voltages track
together. The ADC converter uses the difference between these two as its reference. The total gain error listed for the internal
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(6)
(7)
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
reference is inclusive of the movement of the internal bandgap over temperature. Gain error over temperature for the external
reference option will depend on the temperature profile of the source used.
Voltages above VDDA + 0.3 V or below VSS - 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin.
To avoid this, the analog inputs should be kept within these limits.
TI recommends using high precision external reference TI part REF3020/3120 or equivalent for 2.048-V reference.
8.15.2 ADC Power-Up Control Bit Timing
ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
td(BGR)
PWDNADC
td(PWD)
Request for
ADC
Conversion
Figure 8-23. ADC Power-Up Control Bit Timing
8.15.2.1 ADC Power-Up Delays
PARAMETER(1)
MIN
td(BGR)
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3 register
(ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled.
td(PWD)
Delay time for power-down control to be stable. Bit delay time for band-gap reference
to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0) must be set to
1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3 register
(PWDNADC)must be set to 1 before any ADC conversions are initiated.
(1)
TYP
MAX
5
20
50
UNIT
ms
μs
1
ms
Timings maintain compatibility to the 281x ADC module. The 280x ADC also supports driving all 3 bits at the same time and waiting
td(BGR) ms before first conversion.
8.15.2.2 Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK)
ADC OPERATING MODE(1)
CONDITIONS
(2)
VDDA18
VDDA3.3
UNIT
Mode A (Operational Mode):
•
•
BG and REF enabled
PWD disabled
30
2
mA
Mode B:
•
•
•
ADC clock enabled
BG and REF enabled
PWD enabled
9
0.5
mA
Mode C:
•
•
•
ADC clock enabled
BG and REF disabled
PWD enabled
5
20
μA
Mode D:
•
•
•
ADC clock disabled
BG and REF disabled
PWD enabled
5
15
μA
(1)
(2)
Test Conditions:
SYSCLKOUT = 100 MHz
ADC module clock = 12.5 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
VDDA18 includes current into VDD1A18 and VDD2A18. VDDA3.3 includes current into VDDA2 and VDDAIO.
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Rs
Source
Signal
ADCIN0
Ron
1 kΩ
Switch
Cp
10 pF
ac
Ch
1.64 pF
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (Ron):
Sampling Capacitor (Ch):
Parasitic Capacitance (Cp):
Source Resistance (Rs):
1 kΩ
1.64 pF
10 pF
50 Ω
Figure 8-24. ADC Analog Input Impedance Model
8.15.3 Definitions
Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC.
Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at a time.
These inputs are software-selectable.
Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with low
power consumption.
Conversion Modes
The conversion can be performed in two different conversion modes:
• Sequential sampling mode (SMODE = 0)
• Simultaneous sampling mode (SMODE = 1)
62
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8.15.4 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax to Bx).
The ADC can start conversions on event triggers from the ePWM, software trigger, or from an external ADCSOC
signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on every Sample/Hold pulse.
The conversion time and latency of the Result register update are explained below. The ADC interrupt flags are
set a few SYSCLKOUT cycles after the Result register update. The selected channels will be sampled at every
falling edge of the Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock
wide (minimum) or 16 ADC clocks wide (maximum).
Sample n+2
Sample n+1
Analog Input on
Channel Ax or Bx
Sample n
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
td(SH)
tdschx_n+1
tdschx_n
ADC Event Trigger from
ePWM or Other Sources
tSH
Figure 8-25. Sequential Sampling Mode (Single-Channel) Timing
8.15.4.1 Sequential Sampling Mode Timing
SAMPLE n
SAMPLE n + 1
AT 12.5 MHz
ADC CLOCK,
tc(ADCCLK) = 80 ns
td(SH)
Delay time from event trigger to
sampling
2.5tc(ADCCLK)
tSH
Sample/Hold width/Acquisition
Width
(1 + Acqps) *
tc(ADCCLK)
80 ns with Acqps = 0
td(schx_n)
Delay time for first result to appear
in Result register
4tc(ADCCLK)
320 ns
td(schx_n+1)
Delay time for successive results to
appear in Result register
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(2 + Acqps) *
tc(ADCCLK)
REMARKS
Acqps value = 0–15
ADCTRL1[8:11]
160 ns
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8.15.5 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels (A0/B0 to
A7/B7). The ADC can start conversions on event triggers from the ePWM, software trigger, or from an external
ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected channels on every Sample/
Hold pulse. The conversion time and latency of the result register update are explained below. The ADC interrupt
flags are set a few SYSCLKOUT cycles after the Result register update. The selected channels will be sampled
simultaneously at the falling edge of the Sample/Hold pulse. The Sample/Hold pulse width can be programmed
to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
Note
In simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7, and not in
other combinations (such as A1/B3, and so forth).
Sample n
Sample n+1
Analog Input on
Channel Ax
Analog Input on
Channel Bx
Sample n+2
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
td(SH)
tdschA0_n+1
tSH
ADC Event Trigger from
ePWM or Other Sources
tdschA0_n
tdschB0_n+1
tdschB0_n
Figure 8-26. Simultaneous Sampling Mode Timing
8.15.5.1 Simultaneous Sampling Mode Timing
SAMPLE n
SAMPLE n + 1
AT 12.5 MHz
ADC CLOCK,
tc(ADCCLK) = 80 ns
td(SH)
Delay time from event trigger to
sampling
2.5tc(ADCCLK)
tSH
Sample/Hold width/Acquisition
Width
(1 + Acqps) *
tc(ADCCLK)
80 ns with Acqps = 0
td(schA0_n)
Delay time for first result to
appear in Result register
4tc(ADCCLK)
320 ns
td(schB0_n )
Delay time for first result to
appear in Result register
5tc(ADCCLK)
400 ns
td(schA0_n+1)
Delay time for successive results
to appear in Result register
(3 + Acqps) * tc(ADCCLK)
240 ns
td(schB0_n+1 )
Delay time for successive results
to appear in Result register
(3 + Acqps) * tc(ADCCLK)
240 ns
REMARKS
Acqps value = 0–15
ADCTRL1[8:11]
8.15.6 Detailed Descriptions
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as
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level one-half LSB beyond the last code transition. The deviation is measured from the center of each particular
code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A
differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The last
transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is the
deviation of the actual difference between first and last code transitions and the ideal difference between first
and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
(SINAD * 1.76)
N+
6.02
it is possible to get a measure of performance expressed as N, the effective number of
bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated
directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured input
signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
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8.16 Migrating From F280x Devices to C280x Devices
8.16.1 Migration Issues
The migration issues to be considered while migrating from the F280x devices to C280x devices are as follows:
• The 1K OTP memory available in F280x devices has been replaced by 1K ROM C280x devices.
• Current consumption differs for F280x and C280x devices for all four possible modes. See the appropriate
electrical section for exact numbers.
• The VDD3VFL pin is the 3.3-V Flash core power pin in F280x devices but is a VDDIO pin in C280x devices.
• F280x and C280x devices are pin-compatible and code-compatible; however, they are electrically different
with different EMI/ESD profiles. Before ramping production with C280x devices, evaluate performance of the
hardware design with both devices.
• Addresses 0x3D 7BFC through 0x3D 7BFF in the OTP and addresses 0x3F 7FF0 through 0x3F 7FF5 in the
main ROM array are reserved for ROM part-specific information and are not available for user applications.
• The paged and random wait-state specifications for the Flash and ROM parts are different. While migrating
from Flash to ROM parts, the same wait-state values must be used for best-performance compatibility (for
example, in applications that use software delay loops or where precise interrupt latencies are critical).
• The analog input switch resistance is smaller in C280x devices compared to F280x devices. While migrating
from a Flash to a ROM device care should be taken to design the analog input circuits to meet the application
performance required by the sampling network.
• The PART-ID register value is different for Flash and ROM parts.
• From a silicon functionality/errata standpoint, rev A ROM devices are equivalent to rev C flash devices. See
the errata applicable to 280x devices for details.
• As part of the ROM code generation process, all unused memory locations in the customer application are
automatically filled with 0xFFFF. Unused locations should not be manually filled with any other data.
Note
Requests for ROM versions of the F280x device are not accepted by TI anymore.
For errata applicable to 280x devices, see the TMS320F280x, TMS320C280x, TMS320F2801x DSPs silicon
errata.
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8.17 ROM Timing (C280x only)
8.17.1 ROM/OTP Access Timing
PARAMETER
MIN
MAX
UNIT
ta(rp)
Paged ROM access time
19
ns
ta(rr)
Random ROM access time
19
ns
ta(ROM)
ROM (OTP area) access time (1)
60
ns
(1)
In C280x devices, a 1K X 16 ROM block replaces the OTP block found in Flash devices.
Table 8-3. ROM/ROM (OTP area) Minimum Required
Wait-States at Different Frequencies
SYSCLKOUT
(MHz)
(1)
SYSCLKOUT
(ns)
PAGE WAITSTATE
RANDOM WAITSTATE(1)
100
10
1
1
75
13.33
1
1
50
20
0
1
30
33.33
0
1
25
40
0
1
15
66.67
0
1
4
250
0
1
Random wait-state must be greater than or equal to 1.
Equations to compute the page wait-state and random wait-state in Table 8-3 are as follows:
ROM Page Wait-State +
ƪǒ
ROM Random Wait-State +
t a(rp)
t c(SCO)
ƪǒ
Ǔ ƫ
*1
t a(rr)
t c(SCO)
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(round up to the next highest integer) or 0, whichever is larger
Ǔ ƫ
* 1 (round up to the next highest integer) or 1, whichever is larger
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9 Detailed Description
9.1 Brief Descriptions
9.1.1 C28x CPU
The C28x DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is a very
efficient C/C++ engine, enabling users to develop not only their system control software in a high-level language,
but also enables math algorithms to be developed using C/C++. The C28x is as efficient in DSP math tasks as it
is in system control tasks that typically are handled by microcontroller devices. This efficiency removes the need
for a second processor in many systems. The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing
capabilities, enable the C28x to efficiently handle higher numerical resolution problems that would otherwise
demand a more expensive floating-point processor solution. Add to this the fast interrupt response with
automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous
events with minimal latency. The C28x has an 8-level-deep protected pipeline with pipelined memory accesses.
This pipelining enables the C28x to execute at high speeds without resorting to expensive high-speed memories.
Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store
conditional operations further improve performance.
9.1.2 Memory Bus (Harvard Bus Architecture)
As with many DSP type devices, multiple busses are used to move data between the memories and peripherals
and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write
bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses
consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit
operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an
instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to
the memory bus will prioritize memory accesses. Generally, the priority of memory bus accesses can be
summarized as follows:
Highest:
Data Writes
(Simultaneous data and program writes cannot occur on the memory bus.)
Program Writes
(Simultaneous data and program writes cannot occur on the memory bus.)
Data Reads
Lowest:
Program Reads
(Simultaneous program reads and fetches cannot occur on the memory bus.)
Fetches
(Simultaneous program reads and fetches cannot occur on the memory bus.)
9.1.3 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the 280x
devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the
various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16
or 32 data lines and associated control signals. Two versions of the peripheral bus are supported on the 280x.
One version only supports 16-bit accesses (called peripheral frame 2). The other version supports both 16- and
32-bit accesses (called peripheral frame 1).
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9.1.4 Real-Time JTAG and Analysis
The 280x implements the standard IEEE 1149.1 JTAG interface. Additionally, the 280x supports real-time mode
of operation whereby the contents of memory, peripheral and register locations can be modified while the
processor is running and executing code and servicing interrupts. The user can also single step through nontime critical code while enabling time-critical interrupts to be serviced without interference. The 280x implements
the real-time mode in hardware within the CPU. This is a unique feature to the 280x, no software monitor is
required. Additionally, special analysis hardware is provided which allows the user to set hardware breakpoint or
data/address watch-points and generate various user-selectable break events when a match occurs.
9.1.5 Flash
The F2809 contains 128K x 16 of embedded flash memory, segregated into eight 16K x 16 sectors. The F2808
contains 64K x 16 of embedded flash memory, segregated into four 16K x 16 sectors. The F2806 and F2802
have 32K x 16 of embedded flash, segregated into four 8K x 16 sectors. The F2801 device contains 16K x 16 of
embedded flash, segregated into four 4K x 16 sectors. All five devices also contain a single 1K x 16 of OTP
memory at address range 0x3D 7800 – 0x3D 7BFF. The user can individually erase, program, and validate a
flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or
the OTP to execute flash algorithms that erase/program other sectors. Special memory pipelining is provided to
enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data
space; therefore, it can be used to execute code or store data information. Note that addresses 0x3F7FF0 –
0x3F7FF5 are reserved for data variables and should not contain program code.
Note
The F2809/F2808/F2806/F2802/F2801 Flash and OTP wait-states can be configured by the
application. This allows applications running at slower frequencies to configure the flash to use fewer
wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options
register. With this mode enabled, effective performance of linear code execution will be much faster
than the raw performance indicated by the wait-state configuration alone. The exact performance gain
when using the Flash pipeline mode is application-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see the
TMS320x280x, 2801x, 2804x DSP system control and interrupts reference guide.
9.1.6 ROM
The C2802 contains 32K x 16 of ROM, while the C2801 contains 16K x 16 of ROM.
Note
Requests for ROM devices are not accepted by TI anymore.
9.1.7 M0, M1 SARAMs
All 280x devices contain these two blocks of single-access memory, each 1K x 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x
devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or
for data variables. The partitioning is performed within the linker. The C28x device presents a unified memory
map to the programmer. This makes for easier programming in high-level languages.
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9.1.8 L0, L1, H0 SARAMs
The F2809 and F2808 each contain an additional 16K x 16 of single-access RAM, divided into three blocks
(L0-4K, L1-4K, H0-8K). The F2806 contains an additional 8K x 16 of single-access RAM, divided into two blocks
(L0-4K, L1-4K). The F2802, F2801, C2802, and C2801 each contain an additional 4K x 16 of single-access RAM
(L0-4K). Each block can be independently accessed to minimize CPU pipeline stalls. Each block is mapped to
both program and data space.
9.1.9 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the
bootloader software what boot mode to use on power up. The user can select to boot normally or to download
new software from an external connection or to select boot software that is programmed in the internal Flash/
ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math related
algorithms.
Table 9-1. Boot Mode Selection
MODE
DESCRIPTION
GPIO18
SPICLKA
SCITXDB
GPIO29
SCITXDA
GPIO34
Boot to Flash/ROM
Jump to Flash/ROM address 0x3F 7FF6
You must have programmed a branch instruction here prior
to reset to redirect code execution as desired.
1
1
1
SCI-A Boot
Load a data stream from SCI-A
1
1
0
SPI-A Boot
Load from an external serial SPI EEPROM on SPI-A
1
0
1
I2C Boot
Load data from an external EEPROM at address 0x50 on
the I2C bus
1
0
0
eCAN-A Boot
Call CAN_Boot to load from eCAN-A mailbox 1.
0
1
1
Boot to M0 SARAM
Jump to M0 SARAM address 0x00 0000.
0
1
0
Boot to OTP
Jump to OTP address 0x3D 7800
0
0
1
Parallel I/O Boot
Load data from GPIO0 - GPIO15
0
0
0
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9.1.10 Security
The 280x devices support high levels of security to protect the user firmware from being reverse engineered.
The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the flash.
One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks. The security
feature prevents unauthorized users from examining the memory contents via the JTAG port, executing code
from external memory or trying to boot-load some undesirable software that would export the secure memory
contents. To enable access to the secure blocks, the user must write the correct 128-bit KEY value, which
matches the value stored in the password locations within the Flash.
Note
The 128-bit password (at 0x3F 7FF8 – 0x3F 7FFF) must not be programmed to zeros. Doing so would
permanently lock the device.
Note
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR
FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS
STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS
FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.
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9.1.11 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block
can support up to 96 peripheral interrupts. On the 280x, 43 of the possible 96 interrupts are used by peripherals.
The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to
INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that can be
overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes 8 CPU
clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt
events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be
enabled/disabled within the PIE block.
9.1.12 External Interrupts (XINT1, XINT2, XNMI)
The 280x supports three masked external interrupts (XINT1, XINT2, XNMI). XNMI can be connected to the
INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or both negative
and positive edge triggering and can also be enabled/disabled (including the XNMI). The masked interrupts also
contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is detected. This
counter can be used to accurately time stamp the interrupt. Unlike the 281x devices, there are no dedicated pins
for the external interrupts. Rather, any Port A GPIO pin can be configured to trigger any external interrupt.
9.1.13 Oscillator and PLL
The 280x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A PLL
is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software,
enabling the user to scale back on operating frequency if lower power operation is desired. See Section 8 for
timing details. The PLL block can be set in bypass mode.
9.1.14 Watchdog
The 280x devices contain a watchdog timer. The user software must regularly reset the watchdog counter within
a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can be
disabled if necessary.
9.1.15 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN) and the ADC
blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled from
increasing CPU clock speeds.
9.1.16 Low-Power Modes
The 280x devices are full static CMOS devices. Three low-power modes are provided:
72
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that
need to function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog
timer will wake the processor from IDLE mode.
STANDBY:
Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt
event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the
interrupt event
HALT:
Turns off the internal oscillator. This mode basically shuts down the device and places it in the lowest possible
power consumption mode. A reset or external signal can wake the device from this mode.
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9.1.17 Peripheral Frames 0, 1, 2 (PFn)
The 280x segregate peripherals into three sections. The mapping of peripherals is as follows:
PF0:
PF1:
PF2:
PIE:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash:
Flash Control, Programming, Erase, Verify Registers
Timers:
CPU-Timers 0, 1, 2 Registers
CSM:
Code Security Module KEY Registers
ADC:
ADC Result Registers (dual-mapped)
eCAN:
eCAN Mailbox and Control Registers
GPIO:
GPIO MUX Configuration and Control Registers
ePWM:
Enhanced Pulse Width Modulator Module and Registers
eCAP:
Enhanced Capture Module and Registers
eQEP:
Enhanced Quadrature Encoder Pulse Module and Registers
SYS:
System Control Registers
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
SPI:
Serial Port Interface (SPI) Control and RX/TX Registers
ADC:
ADC Status, Control, and Result Register
I2C:
Inter-Integrated Circuit Module and Registers
9.1.18 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This enables
the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured
as inputs. The user can individually program each pin for GPIO mode or peripheral signal mode. For specific
inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches.
The GPIO signals can also be used to bring the device out of specific low-power modes.
9.1.19 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The
counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches
zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for the SYS/BIOS RealTime OS, and is connected to INT14 of the CPU. If SYS/BIOS is not being used, CPU-Timer 2 is available for
general use. CPU-Timer 1 is for general use and can be connected to INT13 of the CPU. CPU-Timer 0 is also for
general use and is connected to the PIE block.
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9.1.20 Control Peripherals
The 280x devices support the following peripherals which are used for embedded control and communication:
ePWM:
The enhanced PWM peripheral supports independent/complementary PWM generation, adjustable dead-band
generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. Some of the PWM pins support
HRPWM features.
eCAP:
The enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in
continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
eQEP:
The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed measurement using capture
unit and high-speed measurement using a 32-bit unit timer.
This peripheral has a watchdog timer to detect motor stall and input error detection logic to identify simultaneous
edge transition in QEP signals.
ADC:
The ADC block is a 12-bit converter, single-ended, 16-channels. It contains two sample-and-hold units for
simultaneous sampling.
9.1.21 Serial Port Peripherals
The 280x devices support the following serial communication peripherals:
74
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time stamping of messages, and is
compliant with ISO11898-1 (CAN 2.0B).
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to
sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used
for communications between the DSP controller and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as shift registers, display drivers,
and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. On the 280x,
the SPI contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.
SCI:
The serial communications interface is a two-wire asynchronous serial port, commonly known as UART. On the
280x, the SCI contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.
I2C:
The inter-integrated circuit (I2C) module provides an interface between a DSP and other devices compliant with
Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus.
External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP
through the I2C module. On the 280x, the I2C contains a 16-level receive and transmit FIFO for reducing
interrupt servicing overhead.
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9.2 Peripherals
The integrated peripherals of the 280x are described in the following subsections:
• Three 32-bit CPU-Timers
• Up to six enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6)
• Up to four enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4)
• Up to two enhanced QEP modules (eQEP1, eQEP2)
• Enhanced analog-to-digital converter (ADC) module
• Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B)
• Up to two serial communications interface modules (SCI-A, SCI-B)
• Up to four serial peripheral interface (SPI) modules (SPI-A, SPI-B, SPI-C, SPI-D)
• Inter-integrated circuit module (I2C)
• Digital I/O and shared pin functions
9.2.1 32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on the 280x devices (CPU-TIMER0/1/2).
CPU-Timer 0 and CPU-Timer 1 can be used in user applications. Timer 2 is reserved for SYS/BIOS. These
timers are different from the timers that are present in the ePWM modules.
Note
If the application is not using SYS/BIOS, then CPU-Timer 2 can be used in the application.
Reset
Timer Reload
16-Bit Timer Divide-Down
TDDRH:TDDR
SYSCLKOUT
TCR.4
(Timer Start Status)
32-Bit Timer Period
PRDH:PRD
16-Bit Prescale Counter
PSCH:PSC
Borrow
32-Bit Counter
TIMH:TIM
Borrow
TINT
Figure 9-1. CPU-Timers
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In the 280x devices, the timer interrupt signals ( TINT0, TINT1, TINT2) are connected as shown in Figure 9-2.
INT1
to
INT12
PIE
TINT0
CPU-TIMER 0
C28x
TINT1
INT13
CPU-TIMER 1
XINT13
CPU-TIMER 2
(Reserved for
SYS/BIOS)
TINT2
INT14
A. The timer registers are connected to the memory bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 9-2. CPU-Timer Interrupt Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the value
in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the C28x.
When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in
Table 9-2 are used to configure the timers. For more information, see the TMS320x280x, 2801x, 2804x DSP
system control and interrupts reference guide.
Table 9-2. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
ADDRESS
SIZE (x16)
TIMER0TIM
0x0C00
1
CPU-Timer 0, Counter Register
DESCRIPTION
TIMER0TIMH
0x0C01
1
CPU-Timer 0, Counter Register High
TIMER0PRD
0x0C02
1
CPU-Timer 0, Period Register
TIMER0PRDH
0x0C03
1
CPU-Timer 0, Period Register High
TIMER0TCR
0x0C04
1
CPU-Timer 0, Control Register
Reserved
0x0C05
1
Reserved
TIMER0TPR
0x0C06
1
CPU-Timer 0, Prescale Register
TIMER0TPRH
0x0C07
1
CPU-Timer 0, Prescale Register High
TIMER1TIM
0x0C08
1
CPU-Timer 1, Counter Register
TIMER1TIMH
0x0C09
1
CPU-Timer 1, Counter Register High
TIMER1PRD
0x0C0A
1
CPU-Timer 1, Period Register
TIMER1PRDH
0x0C0B
1
CPU-Timer 1, Period Register High
TIMER1TCR
0x0C0C
1
CPU-Timer 1, Control Register
Reserved
0x0C0D
1
Reserved
TIMER1TPR
0x0C0E
1
CPU-Timer 1, Prescale Register
TIMER1TPRH
0x0C0F
1
CPU-Timer 1, Prescale Register High
TIMER2TIM
0x0C10
1
CPU-Timer 2, Counter Register
TIMER2TIMH
0x0C11
1
CPU-Timer 2, Counter Register High
TIMER2PRD
0x0C12
1
CPU-Timer 2, Period Register
TIMER2PRDH
0x0C13
1
CPU-Timer 2, Period Register High
TIMER2TCR
0x0C14
1
CPU-Timer 2, Control Register
Reserved
0x0C15
1
Reserved
TIMER2TPR
0x0C16
1
CPU-Timer 2, Prescale Register
76
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Table 9-2. CPU-Timers 0, 1, 2 Configuration and Control Registers (continued)
NAME
TIMER2TPRH
Reserved
ADDRESS
SIZE (x16)
0x0C17
1
CPU-Timer 2, Prescale Register High
DESCRIPTION
0x0C18 –
0x0C3F
40
Reserved
9.2.2 Enhanced PWM Modules (ePWM1/2/3/4/5/6)
The 280x device contains up to six enhanced PWM modules (ePWM). Figure 9-3 shows a block diagram of
multiple ePWM modules. Figure 9-4 shows the signal interconnections with the ePWM. See the TMS320x280x,
2801x, 2804x Enhanced Pulse Width Modulator (ePWM) module reference guide for more details.
EPWM1SYNCI
EPWM1SYNCI
EPWM1INT
EPWM1SOC
EPWM1A
ePWM1 Module
EPWM1B
TZ1 to TZ6
To eCAP1
Module
(Sync in)
EPWM1SYNCO
EPWM1SYNCO
EPWM2SYNCI
EPWM2INT
EPWM2SOC
PIE
EPWM2A
ePWM2 Module
EPWM2B
TZ1 to TZ6
EPWM2SYNCO
GPIO
MUX
EPWMxSYNCI
EPWMxINT
EPWMxSOC
EPWMxA
ePWMx Module
EPWMxB
TZ1 to TZ6
EPWMxSYNCO
ADCSOCx0
Peripheral Bus
ADC
Copyright © 2016, Texas Instruments Incorporated
Figure 9-3. Multiple PWM Modules in a 280x System
Table 9-3 shows the complete ePWM register set per module.
Table 9-3. ePWM Control and Status Registers
NAME
TBCTL
ePWM1
ePWM2
ePWM3
ePWM4
ePWM5
ePWM6
SIZE (x16) /
#SHADOW
0x6800
0x6840
0x6880
0x68C0
0x6900
0x6940
1/0
Copyright © 2021 Texas Instruments Incorporated
DESCRIPTION
Time Base Control Register
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Table 9-3. ePWM Control and Status Registers (continued)
NAME
ePWM1
ePWM2
ePWM3
ePWM4
ePWM5
ePWM6
SIZE (x16) /
#SHADOW
DESCRIPTION
TBSTS
0x6801
0x6841
0x6881
0x68C1
0x6901
0x6941
1/0
Time Base Status Register
TBPHSH
R
0x6802
0x6842
0x6882
0x68C2
N/A
N/A
1/0
Time Base Phase HRPWM Register
TBPHS
0x6803
0x6843
0x6883
0x68C3
0x6903
0x6943
1/0
Time Base Phase Register
TBCTR
0x6804
0x6844
0x6884
0x68C4
0x6904
0x6944
1/0
Time Base Counter Register
TBPRD
0x6805
0x6845
0x6885
0x68C5
0x6905
0x6945
1/1
Time Base Period Register Set
CMPCTL
0x6807
0x6847
0x6887
0x68C7
0x6907
0x6947
1/0
Counter Compare Control Register
CMPAHR
0x6808
0x6848
0x6888
0x68C8
N/A
N/A
1/1
Time Base Compare A HRPWM Register
CMPA
0x6809
0x6849
0x6889
0x68C9
0x6909
0x6949
1/1
Counter Compare A Register Set
CMPB
0x680A
0x684A
0x688A
0x68CA
0x690A
0x694A
1/1
Counter Compare B Register Set
AQCTLA
0x680B
0x684B
0x688B
0x68CB
0x690B
0x694B
1/0
Action Qualifier Control Register For
Output A
AQCTLB
0x680C
0x684C
0x688C
0x68CC
0x690C
0x694C
1/0
Action Qualifier Control Register For
Output B
AQSFRC
0x680D
0x684D
0x688D
0x68CD
0x690D
0x694D
1/0
Action Qualifier Software Force Register
AQCSFR
C
0x680E
0x684E
0x688E
0x68CE
0x690E
0x694E
1/1
Action Qualifier Continuous S/W Force
Register Set
DBCTL
0x680F
0x684F
0x688F
0x68CF
0x690F
0x694F
1/1
Dead-Band Generator Control Register
DBRED
0x6810
0x6850
0x6890
0x68D0
0x6910
0x6950
1/0
Dead-Band Generator Rising Edge Delay
Count Register
DBFED
0x6811
0x6851
0x6891
0x68D1
0x6911
0x6951
1/0
Dead-Band Generator Falling Edge Delay
Count Register
TZSEL
0x6812
0x6852
0x6892
0x68D2
0x6912
0x6952
1/0
Trip Zone Select Register(1)
TZCTL
0x6814
0x6854
0x6894
0x68D4
0x6914
0x6954
1/0
Trip Zone Control Register(1)
TZEINT
0x6815
0x6855
0x6895
0x68D5
0x6915
0x6955
1/0
Trip Zone Enable Interrupt Register(1)
TZFLG
0x6816
0x6856
0x6896
0x68D6
0x6916
0x6956
1/0
Trip Zone Flag Register
TZCLR
0x6817
0x6857
0x6897
0x68D7
0x6917
0x6957
1/0
Trip Zone Clear Register(1)
TZFRC
0x6818
0x6858
0x6898
0x68D8
0x6918
0x6958
1/0
Trip Zone Force Register(1)
ETSEL
0x6819
0x6859
0x6899
0x68D9
0x6919
0x6959
1/0
Event Trigger Selection Register
ETPS
0x681A
0x685A
0x689A
0x68DA
0x691A
0x695A
1/0
Event Trigger Prescale Register
ETFLG
0x681B
0x685B
0x689B
0x68DB
0x691B
0x695B
1/0
Event Trigger Flag Register
ETCLR
0x681C
0x685C
0x689C
0x68DC
0x691C
0x695C
1/0
Event Trigger Clear Register
ETFRC
0x681D
0x685D
0x689D
0x68DD
0x691D
0x695D
1/0
Event Trigger Force Register
PCCTL
0x681E
0x685E
0x689E
0x68DE
0x691E
0x695E
1/0
PWM Chopper Control Register
0x68E0
0x6920(2)
0x6960(2)
1/0
HRPWM Configuration Register(1)
HRCNFG
(1)
(2)
78
0x6820
0x6860
0x68A0
Registers that are EALLOW protected.
Applicable to F2809 only
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Time-Base (TB)
CTR = ZERO
TBPRD Shadow (16)
CTR = CMPB
TBPRD Active (16)
Disabled
CTR = PRD
Sync
In/Out
Select
Mux
EPWMxSYNCO
TBCTL[SYNCOSEL]
TBCTL[PHSEN]
EPWMxSYNCI
Counter
Up/Down
(16-Bit)
TBCTL[SWFSYNC]
(Software-Forced Sync)
CTR = ZERO
TBCNT
Active (16)
CTR_Dir
TBPHSHR (8)
16
8
TBPHS Active (24)
CTR = PRD
Phase
Control
CTR = ZERO
CTR = CMPA
Counter Compare (CC)
CTR = CMPA
CMPAHR (8)
16
CTR = CMPB
CTR_Dir
Event
Trigger
and
Interrupt
(ET)
EPWMxINT
EPWMxSOCA
EPWMxSOCB
Action
Qualifier
(AQ)
8
HiRes PWM (HRPWM)
CMPA Active (24)
EPWMxAO
EPWMA
CMPA Shadow (24)
Dead
Band
(DB)
CTR = CMPB
PWM
Chopper
(PC)
16
EPWMxBO
EPWMB
CMPB Active (16)
CMPB Shadow (16)
Trip
Zone
(TZ)
EPWMxTZINT
CTR = ZERO
TZ1 to TZ6
Copyright © 2016, Texas Instruments Incorporated
Figure 9-4. ePWM Sub-Modules Showing Critical Internal Signal Interconnections
9.2.3 Hi-Resolution PWM (HRPWM)
The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• Typically used when effective PWM resolution falls below ~ 9–10 bits. This occurs at PWM frequencies
greater than ~200 kHz when using a CPU/System clock of 100 MHz.
• This capability can be utilized in both duty cycle and phase-shift control methods.
• Finer time granularity control or edge positioning is controlled via extensions to the Compare A and Phase
registers of the ePWM module.
• HRPWM capabilities are offered only on the A signal path of an ePWM module (that is, on the EPWMxA
output). EPWMxB output has conventional PWM capabilities.
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9.2.4 Enhanced CAP Modules (eCAP1/2/3/4)
The 280x device contains up to four enhanced capture (eCAP) modules. Figure 9-5 shows a functional block
diagram of a module. See the TMS320x280x, 2801x, 2804x Enhanced Capture (eCAP) module reference guide
for more details.
SYNC
CTRPHS
(Phase Register - 32-bit)
SYNCIn
SYNCOut
TSCTR
(Counter - 32-bit)
APWM Mode
CTR_OVF
OVF
RST
Delta Mode
CTR [0-31]
PWM
Compare
Logic
PRD [0-31]
CMP [0-31]
32
CTR=PRD
CTR [0-31]
CTR=CMP
32
CAP1
(APRD Active)
APRD
Shadow
32
32
32
LD1
Polarity
Select
CMP [0-31]
CAP2
(ACMP Active)
32
LD
MODE SELECT
32
PRD [0-31]
LD
32
CAP3
(APRD Shadow)
LD
32
CAP4
(ACMP Shadow)
LD
Polarity
Select
LD2
Event
Qualifier
ACMP
Shadow
eCAPx
Event
Prescale
LD3
Polarity
Select
LD4
Polarity
Select
4
Capture Events
4
CEVT[1:4]
to PIE
Interrupt
Trigger
and
Flag
Control
CTR_OVF
Continuous/
One-Shot
Capture Control
CTR=PRD
CTR=CMP
Copyright © 2016, Texas Instruments Incorporated
Figure 9-5. eCAP Functional Block Diagram
80
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The eCAP modules are clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1/2/3/4ENCLK) in the PCLKCR1 register are used to turn off the eCAP modules
individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, and
ECAP4ENCLK are set to low, indicating that the peripheral clock is off.
Table 9-4. eCAP Control and Status Registers
NAME
SIZE
(x16)
eCAP1
eCAP2
eCAP3
eCAP4
DESCRIPTION
TSCTR
0x6A00
0x6A20
0x6A40
0x6A60
2
Time-Stamp Counter
CTRPHS
0x6A02
0x6A22
0x6A42
0x6A62
2
Counter Phase Offset Value Register
CAP1
0x6A04
0x6A24
0x6A44
0x6A64
2
Capture 1 Register
CAP2
0x6A06
0x6A26
0x6A46
0x6A66
2
Capture 2 Register
CAP3
0x6A08
0x6A28
0x6A48
0x6A68
2
Capture 3 Register
CAP4
0x6A0A
0x6A2A
0x6A4A
0x6A6A
2
Capture 4 Register
0x6A0C –
0x6A12
0x6A2C –
0x6A32
0x6A4C –
0x6A52
0x6A6C –
0x6A72
8
Reserved
Reserved
ECCTL1
0x6A14
0x6A34
0x6A54
0x6A74
1
Capture Control Register 1
ECCTL2
0x6A15
0x6A35
0x6A55
0x6A75
1
Capture Control Register 2
ECEINT
0x6A16
0x6A36
0x6A56
0x6A76
1
Capture Interrupt Enable Register
ECFLG
0x6A17
0x6A37
0x6A57
0x6A77
1
Capture Interrupt Flag Register
ECCLR
0x6A18
0x6A38
0x6A58
0x6A78
1
Capture Interrupt Clear Register
ECFRC
0x6A19
0x6A39
0x6A59
0x6A79
1
Capture Interrupt Force Register
0x6A1A –
0x6A1F
0x6A3A –
0x6A3F
0x6A5A –
0x6A5F
0x6A7A –
0x6A7F
6
Reserved
Reserved
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TMS320C2801, TMS320F28016, TMS320F28015
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
9.2.5 Enhanced QEP Modules (eQEP1/2)
The 280x device contains up to two enhanced quadrature encoder (eQEP) modules. See the TMS320x280x,
2801x, 2804x Enhanced Quadrature Encoder Pulse (eQEP) module reference guide for more details.
System Control
Registers
To CPU
EQEPxENCLK
Data Bus
SYSCLKOUT
QCPRD
QCAPCTL
QCTMR
16
16
16
Quadrature
Capture
Unit
(QCAP)
QCTMRLAT
QCPRDLAT
Registers
Used by
Multiple Units
QUTMR
QWDTMR
QUPRD
QWDPRD
32
16
QEPCTL
QEPSTS
UTIME
QFLG
UTOUT
QWDOG
QDECCTL
16
WDTOUT
PIE
EQEPxAIN
QCLK
EQEPxINT
QDIR
16
QPOSLAT
EQEPxIIN
QI
Position Counter/
Control Unit
(PCCU)
EQEPxB/XDIR
EQEPxIOUT
QS Quadrature
Decoder
PHE
(QDU)
PCSOUT
QPOSSLAT
EQEPxA/XCLK
EQEPxBIN
EQEPxIOE
GPIO
MUX
EQEPxSIN
EQEPxSOUT
QPOSILAT
EQEPxSOE
32
32
QPOSCNT
QPOSINIT
QPOSMAX
QPOSCMP
EQEPxI
EQEPxS
16
QEINT
QFRC
QCLR
QPOSCTL
Enhanced QEP (eQEP) Peripheral
Copyright © 2016, Texas Instruments Incorporated
Figure 9-6. eQEP Functional Block Diagram
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TMS320C2801, TMS320F28016, TMS320F28015
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
Table 9-5 provides a summary of the eQEP registers.
Table 9-5. eQEP Control and Status Registers
eQEP1
ADDRESS
eQEP2
ADDRESS
eQEP1
SIZE(x16)/
#SHADOW
QPOSCNT
0x6B00
0x6B40
2/0
eQEP Position Counter
QPOSINIT
0x6B02
0x6B42
2/0
eQEP Initialization Position Count
QPOSMAX
0x6B04
0x6B44
2/0
eQEP Maximum Position Count
QPOSCMP
0x6B06
0x6B46
2/1
eQEP Position-compare
NAME
REGISTER DESCRIPTION
QPOSILAT
0x6B08
0x6B48
2/0
eQEP Index Position Latch
QPOSSLAT
0x6B0A
0x6B4A
2/0
eQEP Strobe Position Latch
QPOSLAT
0x6B0C
0x6B4C
2/0
eQEP Position Latch
QUTMR
0x6B0E
0x6B4E
2/0
eQEP Unit Timer
QUPRD
0x6B10
0x6B50
2/0
eQEP Unit Period Register
QWDTMR
0x6B12
0x6B52
1/0
eQEP Watchdog Timer
QWDPRD
0x6B13
0x6B53
1/0
eQEP Watchdog Period Register
QDECCTL
0x6B14
0x6B54
1/0
eQEP Decoder Control Register
QEPCTL
0x6B15
0x6B55
1/0
eQEP Control Register
QCAPCTL
0x6B16
0x6B56
1/0
eQEP Capture Control Register
QPOSCTL
0x6B17
0x6B57
1/0
eQEP Position-compare Control Register
QEINT
0x6B18
0x6B58
1/0
eQEP Interrupt Enable Register
QFLG
0x6B19
0x6B59
1/0
eQEP Interrupt Flag Register
QCLR
0x6B1A
0x6B5A
1/0
eQEP Interrupt Clear Register
QFRC
0x6B1B
0x6B5B
1/0
eQEP Interrupt Force Register
QEPSTS
0x6B1C
0x6B5C
1/0
eQEP Status Register
QCTMR
0x6B1D
0x6B5D
1/0
eQEP Capture Timer
QCPRD
0x6B1E
0x6B5E
1/0
eQEP Capture Period Register
QCTMRLAT
0x6B1F
0x6B5F
1/0
eQEP Capture Timer Latch
QCPRDLAT
0x6B20
0x6B60
1/0
eQEP Capture Period Latch
Reserved
0x6B21–
0x6B3F
0x6B61 –
0x6B7F
31/0
Reserved
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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9.2.6 Enhanced Analog-to-Digital Converter (ADC) Module
A simplified functional block diagram of the ADC module is shown in Figure 9-7. The ADC module consists of a
12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:
• 12-bit ADC core with built-in S/H
• Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)
• Fast conversion rate: Up to 80 ns at 25-MHz ADC clock, 12.5 MSPS
• 16-channel, MUXed inputs
• Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion can be
programmed to select anyone of 16 input channels
• Sequencer can be operated as two independent 8-channel sequencers or as one large 16-channel
sequencer (that is, two cascaded 8-channel sequencers)
• Sixteen result registers (individually addressable) to store conversion values
– The digital value of the input analog voltage is derived by:
, when ADCIN £ ADCLO
Digital Value = 0
(
Digital Value = floor 4096 ´
Digital Value = 4095
ADCIN - ADCLO
3
(
, when ADCLO < ADCIN < 3 V
, when ADCIN ³ 3 V
A. All fractional values are truncated.
•
•
•
•
•
Multiple triggers as sources for the start-of-conversion (SOC) sequence
– S/W - software immediate start
– ePWM start of conversion
– XINT2 ADC start of conversion
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS.
Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to synchronize
conversions.
SOCA and SOCB triggers can operate independently in dual-sequencer mode.
Sample-and-hold (S/H) acquisition time window has separate prescale control.
The ADC module in the 280x has been enhanced to provide flexible interface to ePWM peripherals. The ADC
interface is built around a fast, 12-bit ADC module with a fast conversion rate of up to 80 ns at 25-MHz ADC
clock. The ADC module has a 16-channel sequencer, configurable as two independent 8-channel sequencers.
The two independent 8-channel sequencers can be cascaded to form a 16-channel sequencer. Although there
are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 9-7
shows the block diagram of the ADC module.
The two 8-channel sequencer modules have the capability to autosequence a series of conversions, each
module has the choice of selecting any one of the respective eight channels available through an analog MUX.
In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer,
once the conversion is complete, the selected channel value is stored in its respective RESULT register.
Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform
oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.
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TMS320C2801, TMS320F28016, TMS320F28015
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
System
Control Block
ADCENCLK
SYSCLKOUT
High-Speed
Prescaler
DSP
HSPCLK
HALT
Analog
MUX
Result Registers
Result Reg 0
ADCINA0
70A8h
Result Reg 1
S/H
ADCINA7
12-Bit
ADC
Module
Result Reg 7
70AFh
Result Reg 8
70B0h
Result Reg 15
70B7h
ADCINB0
S/H
ADCINB7
ADC Control Registers
S/W
EPWMSOCA
Sequencer 1
SOC
Sequencer 2
SOC
GPIO/XINT2_
ADCSOC
S/W
EPWMSOCB
Figure 9-7. Block Diagram of the ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible,
traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize
switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation
techniques must be used to isolate the ADC module power pins (VDD1A18, VDD2A18, VDDA2, VDDAIO) from the
digital supply. Figure 9-8 and Figure 9-9 show the ADC pin connections for the 280x devices.
Note
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module
is controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as
follows:
• ADCENCLK: On reset, this signal will be low. While reset is active-low ( XRS) the clock to the
register will still function. This is necessary to make sure all registers and modes go into their
default reset state. The analog module, however, will be in a low-power inactive state. As soon
as reset goes high, then the clock to the registers will be disabled. When the user sets the
ADCENCLK signal high, then the clocks to the registers will be enabled and the analog module
will be enabled. There will be a certain time delay (ms range) before the ADC is stable and can
be used.
• HALT: This mode only affects the analog module. It does not affect the registers. In this mode,
the ADC module goes into low-power mode. This mode also will stop the clock to the CPU,
which will stop the HSPCLK; therefore, the ADC register logic will be turned off indirectly.
Figure 9-8 shows the ADC pin-biasing for internal reference and Figure 9-9 shows the ADC pin-biasing for
external reference.
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
ADC 16-Channel Analog Inputs
ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCREFIN
ADC External Current Bias Resistor
ADCRESEXT
ADC Reference Positive Output
ADCREFP
ADC Reference Medium Output
ADCREFM
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Analog input 0-3 V with respect to ADCLO
Connect to analog ground
Float or ground if internal reference is used
22 k
(A)
ADC Power
ADC Analog and Reference I/O Power
2.2 μF
(A)
2.2 μF
ADCREFP and ADCREFM should not
be loaded by external circuitry
VDD1A18
VDD2A18
VSS1AGND
VSS2AGND
ADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
ADC Analog Ground Pin
VDDA2
ADC Analog Power Pin (3.3 V)
VSSA2
ADC Analog Ground Pin
VDDAIO
VSSAIO
ADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin
A. TAIYO YUDEN LMK212BJ225MG-T or equivalent
B. External decoupling capacitors are recommended on all power pins.
C. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
Figure 9-8. ADC Pin Connections With Internal Reference
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
ADC 16-Channel Analog Inputs
ADC External Current Bias Resistor
ADCRESEXT
ADC Reference Positive Output
ADCREFP
ADC Reference Medium Output
ADCREFM
ADC Analog Power
ADC Analog and Reference I/O Power
A.
B.
C.
D.
ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCREFIN
Analog input 0-3 V with respect to ADCLO
Connect to Analog Ground
(D)
Connect to 1.500, 1.024, or 2.048-V precision source
22 k
(A)
2.2 μF
(A)
2.2 μF
ADCREFP and ADCREFM should not
be loaded by external circuitry
VDD1A18
VDD2A18
VSS1AGND
VSS2AGND
ADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
ADC Analog Ground Pin
VDDA2
VSSA2
ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin
VDDAIO
VSSAIO
ADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin
TAIYO YUDEN LMK212BJ225MG-T or equivalent
External decoupling capacitors are recommended on all power pins.
Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
External voltage on ADCREFIN is enabled by changing bits 15:14 in the ADC Reference Select register depending on the voltage used
on this pin. TI recommends TI part REF3020 or equivalent for 2.048-V generation. Overall gain accuracy will be determined by accuracy
of this voltage source.
Figure 9-9. ADC Pin Connections With External Reference
Note
The temperature rating of any recommended component must match the rating of the end product.
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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9.2.6.1 ADC Connections if the ADC Is Not Used
It is recommended to keep the connections for the analog power pins, even if the ADC is not used. Following is a
summary of how the ADC pins should be connected, if the ADC is not used in an application:
• VDD1A18/VDD2A18 – Connect to VDD
• VDDA2, VDDAIO – Connect to VDDIO
• VSS1AGND/VSS2AGND, VSSA2, VSSAIO – Connect to VSS
• ADCLO – Connect to VSS
• ADCREFIN – Connect to VSS
• ADCREFP/ADCREFM – Connect a 100-nF cap to VSS
• ADCRESEXT – Connect a 20-kΩ resistor (very loose tolerance) to VSS.
• ADCINAn, ADCINBn - Connect to VSS
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power savings.
When the ADC module is used in an application, unused ADC input pins should be connected to analog ground
(VSS1AGND/VSS2AGND)
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TMS320C2801, TMS320F28016, TMS320F28015
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
9.2.6.2 ADC Registers
The ADC operation is configured, controlled, and monitored by the registers listed in Table 9-6.
Table 9-6. ADC Registers
NAME(1)
ADDRESS(1)
ADCTRL1
0x7100
ADDRESS(2)
SIZE (x16)
1
DESCRIPTION
ADC Control Register 1
ADCTRL2
0x7101
1
ADC Control Register 2
ADCMAXCONV
0x7102
1
ADC Maximum Conversion Channels Register
ADCCHSELSEQ1
0x7103
1
ADC Channel Select Sequencing Control Register 1
ADCCHSELSEQ2
0x7104
1
ADC Channel Select Sequencing Control Register 2
ADCCHSELSEQ3
0x7105
1
ADC Channel Select Sequencing Control Register 3
ADCCHSELSEQ4
0x7106
1
ADC Channel Select Sequencing Control Register 4
(1)
(2)
ADCASEQSR
0x7107
1
ADC Auto-Sequence Status Register
ADCRESULT0
0x7108
0x0B00
1
ADC Conversion Result Buffer Register 0
ADCRESULT1
0x7109
0x0B01
1
ADC Conversion Result Buffer Register 1
ADCRESULT2
0x710A
0x0B02
1
ADC Conversion Result Buffer Register 2
ADCRESULT3
0x710B
0x0B03
1
ADC Conversion Result Buffer Register 3
ADCRESULT4
0x710C
0x0B04
1
ADC Conversion Result Buffer Register 4
ADCRESULT5
0x710D
0x0B05
1
ADC Conversion Result Buffer Register 5
ADCRESULT6
0x710E
0x0B06
1
ADC Conversion Result Buffer Register 6
ADCRESULT7
0x710F
0x0B07
1
ADC Conversion Result Buffer Register 7
ADCRESULT8
0x7110
0x0B08
1
ADC Conversion Result Buffer Register 8
ADCRESULT9
0x7111
0x0B09
1
ADC Conversion Result Buffer Register 9
ADCRESULT10
0x7112
0x0B0A
1
ADC Conversion Result Buffer Register 10
ADCRESULT11
0x7113
0x0B0B
1
ADC Conversion Result Buffer Register 11
ADCRESULT12
0x7114
0x0B0C
1
ADC Conversion Result Buffer Register 12
ADCRESULT13
0x7115
0x0B0D
1
ADC Conversion Result Buffer Register 13
ADCRESULT14
0x7116
0x0B0E
1
ADC Conversion Result Buffer Register 14
ADCRESULT15
0x7117
0x0B0F
1
ADC Conversion Result Buffer Register 15
ADCTRL3
0x7118
1
ADC Control Register 3
ADCST
0x7119
1
ADC Status Register
Reserved
0x711A –
0x711B
2
Reserved
ADCREFSEL
0x711C
1
ADC Reference Select Register
ADCOFFTRIM
0x711D
1
ADC Offset Trim Register
Reserved
0x711E –
0x711F
2
Reserved
The registers in this column are Peripheral Frame 2 Registers.
The ADC result registers are dual mapped in the 280x DSP. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait-states and
left justified. Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 0 wait sates and right justified. During high-speed/continuous
conversion use of the ADC, use the 0 wait-state locations for fast transfer of ADC results to user memory.
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9.2.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
The CAN module has the following features:
• Fully compliant with CAN protocol, version 2.0B
• Supports data rates up to 1 Mbps
• Thirty-two mailboxes, each with the following properties:
– Configurable as receive or transmit
– Configurable with standard or extended identifier
– Has a programmable receive mask
– Supports data and remote frame
– Composed of 0 to 8 bytes of data
– Uses a 32-bit time stamp on receive and transmit message
– Protects against reception of new message
– Holds the dynamically programmable priority of transmit message
– Employs a programmable interrupt scheme with two interrupt levels
– Employs a programmable alarm on transmission or reception time-out
• Low-power mode
• Programmable wake-up on bus activity
• Automatic reply to a remote request message
• Automatic retransmission of a frame in case of loss of arbitration or error
• 32-bit local network time counter synchronized by a specific message (communication in conjunction with
mailbox 16)
• Self-test mode
– Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided, thereby
eliminating the need for another node to provide the acknowledge bit.
Note
For a SYSCLKOUT of 100 MHz, the smallest bit rate possible is 15.625 kbps.
For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 9.375 kbps.
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
eCAN0INT
eCAN1INT
Controls Address
Data
Enhanced CAN Controller
32
Message Controller
Mailbox RAM
(512 Bytes)
32-Message Mailbox
of 4 x 32-Bit Words
Memory Management
Unit
32
CPU Interface,
Receive Control Unit,
Timer Management Unit
32
eCAN Memory
(512 Bytes)
Registers and
Message Objects Control
32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 9-10. eCAN Block Diagram and Interface Circuit
Table 9-7. 3.3-V eCAN Transceivers
PART NUMBER
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
VREF
OTHER
TA
SN65HVD230
3.3 V
Standby
Adjustable
Yes
–
–40°C to 85°C
SN65HVD230Q
3.3 V
Standby
Adjustable
Yes
–
–40°C to 125°C
SN65HVD231
3.3 V
Sleep
Adjustable
Yes
–
–40°C to 85°C
SN65HVD231Q
3.3 V
Sleep
Adjustable
Yes
–
–40°C to 125°C
SN65HVD232
3.3 V
None
None
None
–
–40°C to 85°C
SN65HVD232Q
3.3 V
None
None
None
–
–40°C to 125°C
SN65HVD233
3.3 V
Standby
Adjustable
None
Diagnostic
Loopback
–40°C to 125°C
SN65HVD234
3.3 V
Standby & Sleep
Adjustable
None
–
–40°C to 125°C
SN65HVD235
3.3 V
Standby
Adjustable
None
Autobaud
Loopback
–40°C to 125°C
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eCAN-A Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
Abort Acknowledge - CANAA
eCAN-A Memory (512 Bytes)
6000h
Received Message Pending - CANRMP
Control and Status Registers
603Fh
6040h
607Fh
6080h
60BFh
60C0h
60FFh
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Local Acceptance Masks (LAM)
(32 x 32-Bit RAM)
Global Acceptance Mask - CANGAM
Message Object Time Stamps (MOTS)
(32 x 32-Bit RAM)
Bit-Timing Configuration - CANBTC
Message Object Time-Out (MOTO)
(32 x 32-Bit RAM)
Transmit Error Counter - CANTEC
Master Control - CANMC
Error and Status - CANES
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
eCAN-A Memory RAM (512 Bytes)
6100h-6107h
Mailbox 0
6108h-610Fh
Mailbox 1
6110h-6117h
Mailbox 2
6118h-611Fh
Mailbox 3
6120h-6127h
Mailbox 4
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Time Stamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
61E0h-61E7h
Mailbox 28
61E8h-61EFh
Mailbox 29
61F0h-61F7h
Mailbox 30
61F8h-61FFh
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
61E8h-61E9h
Message Identifier - MSGID
61EAh-61EBh
Message Control - MSGCTRL
61ECh-61EDh
Message Data Low - MDL
61EEh-61EFh
Message Data High - MDH
Figure 9-11. eCAN-A Memory Map
Note
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and
mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for
this.
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
eCAN-B Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
Abort Acknowledge - CANAA
eCAN-B Memory (512 Bytes)
6200h
Received Message Pending - CANRMP
Control and Status Registers
623Fh
6240h
627Fh
6280h
62BFh
62C0h
62FFh
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Local Acceptance Masks (LAM)
(32 x 32-Bit RAM)
Global Acceptance Mask - CANGAM
Message Object Time Stamps (MOTS)
(32 x 32-Bit RAM)
Bit-Timing Configuration - CANBTC
Message Object Time-Out (MOTO)
(32 x 32-Bit RAM)
Transmit Error Counter - CANTEC
Master Control - CANMC
Error and Status - CANES
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
eCAN-B Memory RAM (512 Bytes)
6300h-6307h
Mailbox 0
6308h-630Fh
Mailbox 1
6310h-6317h
Mailbox 2
6318h-631Fh
Mailbox 3
6320h-6327h
Mailbox 4
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Time Stamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
63E0h-63E7h
Mailbox 28
63E8h-63EFh
Mailbox 29
63F0h-63F7h
Mailbox 30
63F8h-63FFh
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
63E8h-63E9h
Message Identifier - MSGID
63EAh-63EBh
Message Control - MSGCTRL
63ECh-63EDh
Message Data Low - MDL
63EEh-63EFh
Message Data High - MDH
Figure 9-12. eCAN-B Memory Map
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The CAN registers listed in Table 9-8 are used by the CPU to configure and control the CAN controller and the
message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be
accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 9-8. CAN Register Map
(1)
94
REGISTER
NAME(1)
eCAN-A
ADDRESS
eCAN-B
ADDRESS
SIZE
(x32)
CANME
0x6000
0x6200
1
Mailbox enable
DESCRIPTION
CANMD
0x6002
0x6202
1
Mailbox direction
CANTRS
0x6004
0x6204
1
Transmit request set
CANTRR
0x6006
0x6206
1
Transmit request reset
CANTA
0x6008
0x6208
1
Transmission acknowledge
CANAA
0x600A
0x620A
1
Abort acknowledge
CANRMP
0x600C
0x620C
1
Receive message pending
CANRML
0x600E
0x620E
1
Receive message lost
CANRFP
0x6010
0x6210
1
Remote frame pending
CANGAM
0x6012
0x6212
1
Global acceptance mask
CANMC
0x6014
0x6214
1
Master control
CANBTC
0x6016
0x6216
1
Bit-timing configuration
CANES
0x6018
0x6218
1
Error and status
CANTEC
0x601A
0x621A
1
Transmit error counter
CANREC
0x601C
0x621C
1
Receive error counter
CANGIF0
0x601E
0x621E
1
Global interrupt flag 0
CANGIM
0x6020
0x6220
1
Global interrupt mask
CANGIF1
0x6022
0x6222
1
Global interrupt flag 1
CANMIM
0x6024
0x6224
1
Mailbox interrupt mask
CANMIL
0x6026
0x6226
1
Mailbox interrupt level
CANOPC
0x6028
0x6228
1
Overwrite protection control
CANTIOC
0x602A
0x622A
1
TX I/O control
CANRIOC
0x602C
0x622C
1
RX I/O control
CANTSC
0x602E
0x622E
1
Time stamp counter (Reserved in SCC mode)
CANTOC
0x6030
0x6230
1
Time-out control (Reserved in SCC mode)
CANTOS
0x6032
0x6232
1
Time-out status (Reserved in SCC mode)
These registers are mapped to Peripheral Frame 1.
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9.2.8 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B)
The 280x devices include two serial communications interface (SCI) modules. The SCI modules support digital
communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero
(NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and
interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data
integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is
programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
Note
NOTE: Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:
•
•
•
•
•
•
•
•
Baud rate =
LSPCLK
(BRR + 1) * 8
when BRR ¹ 0
Baud rate =
LSPCLK
16
when BRR = 0
Data-word format
– One start bit
– Data-word length programmable from one to eight bits
– Optional even/odd/no parity bit
– One or two stop bits
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
100 MHz
Max bit rate =
= 6.25 ´ 106 b/s (for 100 - MHz devices)
16
60 MHz
= 3.75 ´ 106 b/s (for 60 - MHz devices)
16
NRZ (non-return-to-zero) format
Ten SCI module control registers located in the control register frame beginning at address 7050h
Max bit rate =
•
•
Note
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read
as zeros. Writing to the upper byte has no effect.
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Enhanced features:
• Auto baud-detect hardware logic
• 16-level transmit/receive FIFO
The SCI port operation is configured and controlled by the registers listed in Table 9-9 and Table 9-10.
Table 9-9. SCI-A Registers
(1)
(2)
NAME(1)
ADDRESS
SIZE (x16)
SCICCRA
0x7050
1
SCI-A Communications Control Register
DESCRIPTION
SCICTL1A
0x7051
1
SCI-A Control Register 1
SCIHBAUDA
0x7052
1
SCI-A Baud Register, High Bits
SCILBAUDA
0x7053
1
SCI-A Baud Register, Low Bits
SCICTL2A
0x7054
1
SCI-A Control Register 2
SCIRXSTA
0x7055
1
SCI-A Receive Status Register
SCIRXEMUA
0x7056
1
SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA
0x7057
1
SCI-A Receive Data Buffer Register
SCITXBUFA
0x7059
1
SCI-A Transmit Data Buffer Register
SCIFFTXA(2)
0x705A
1
SCI-A FIFO Transmit Register
SCIFFRXA(2)
0x705B
1
SCI-A FIFO Receive Register
SCIFFCTA(2)
0x705C
1
SCI-A FIFO Control Register
SCIPRIA
0x705F
1
SCI-A Priority Control Register
Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
These registers are new registers for the FIFO mode.
Table 9-10. SCI-B Registers
(1)
(2)
NAME(1) (2)
ADDRESS
SIZE (x16)
DESCRIPTION
SCICCRB
0x7750
1
SCI-B Communications Control Register
SCICTL1B
0x7751
1
SCI-B Control Register 1
SCIHBAUDB
0x7752
1
SCI-B Baud Register, High Bits
SCILBAUDB
0x7753
1
SCI-B Baud Register, Low Bits
SCICTL2B
0x7754
1
SCI-B Control Register 2
SCIRXSTB
0x7755
1
SCI-B Receive Status Register
SCIRXEMUB
0x7756
1
SCI-B Receive Emulation Data Buffer Register
SCIRXBUFB
0x7757
1
SCI-B Receive Data Buffer Register
SCITXBUFB
0x7759
1
SCI-B Transmit Data Buffer Register
SCIFFTXB(2)
0x775A
1
SCI-B FIFO Transmit Register
SCIFFRXB(2)
0x775B
1
SCI-B FIFO Receive Register
SCIFFCTB(2)
0x775C
1
SCI-B FIFO Control Register
SCIPRIB
0x775F
1
SCI-B Priority Control Register
Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
These registers are new registers for the FIFO mode.
Figure 9-13 shows the SCI module block diagram.
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
SCICTL1.1
SCITXD
TXSHF
Register
Frame Format and Mode
Parity
Even/Odd
Enable
TX EMPTY
SCICTL2.6
8
SCICCR.6 SCICCR.5
TXRDY
SCICTL2.7
Transmitter-Data
Buffer Register
SCICTL2.0
TXINT
TX FIFO _0
TX Interrupt Logic
TX FIFO _1
1
-----
TX FIFO _15
WUT
TX
FIFO
Interrupts
SCITXBUF.7-0
TX FIFO Registers
SCIFFENA
To CPU
SCI TX Interrupt Select Logic
AutoBaud Detect Logic
SCIFFTX.14
SCIHBAUD. 15 - 8
SCIRXD
Baud Rate
MSbyte
Register
LSPCLK
TX INT ENA
8
TXWAKE
SCICTL1.3
SCITXD
TXENA
SCIRXD
RXSHF Register
RXWAKE
SCIRXST.1
SCILBAUD. 7 - 0
RXENA
8
Baud Rate
LSbyte
Register
SCICTL1.0
SCICTL2.1
RXRDY
Receive-Data
Buffer Register
SCIRXBUF.7-0
RX/BK INT ENA
SCIRXST.6
BRKDT
8
SCIRXST.5
RX FIFO _15
-----
RX FIFO _1
RX FIFO _0
RX
FIFO
Interrupts
RX Interrupt Logic
SCIRXBUF.7-0
RX FIFO Registers
RXFFOVF
SCIRXST.7
SCIRXST.4 - 2
RX Error
FE OE PE
RXINT
To CPU
SCIFFRX.15
RX Error
RX ERR INT ENA
SCI RX Interrupt Select Logic
SCICTL1.6
Figure 9-13. Serial Communications Interface (SCI) Module Block Diagram
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9.2.9 Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)
The 280x devices include the four-pin serial peripheral interface (SPI) module. Up to four SPI modules (SPI-A,
SPI-B, SPI-C, and SPI-D) are available. The SPI is a high-speed, synchronous serial I/O port that allows a serial
bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable
bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external
peripherals or another processor. Typical applications include external I/O or peripheral expansion through
devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the
master/slave operation of the SPI.
The SPI module features include:
• Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin
Note
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
•
Two operational modes: master and slave
Baud rate: 125 different programmable rates.
Baud rate =
LSPCLK
(SPIBRR + 1)
when SPIBRR = 3 to 127
LSPCLK
when SPIBRR = 0, 1, 2
4
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
Baud rate =
•
•
•
•
•
Note
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read
as zeros. Writing to the upper byte has no effect.
Enhanced feature:
• 16-level transmit/receive FIFO
• Delayed transmit control
98
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
The SPI port operation is configured and controlled by the registers listed in Table 9-11 through Table 9-14 .
Table 9-11. SPI-A Registers
(1)
DESCRIPTION(1)
NAME
ADDRESS
SIZE (x16)
SPICCR
0x7040
1
SPI-A Configuration Control Register
SPICTL
0x7041
1
SPI-A Operation Control Register
SPISTS
0x7042
1
SPI-A Status Register
SPIBRR
0x7044
1
SPI-A Baud Rate Register
SPIRXEMU
0x7046
1
SPI-A Receive Emulation Buffer Register
SPIRXBUF
0x7047
1
SPI-A Serial Input Buffer Register
SPITXBUF
0x7048
1
SPI-A Serial Output Buffer Register
SPIDAT
0x7049
1
SPI-A Serial Data Register
SPIFFTX
0x704A
1
SPI-A FIFO Transmit Register
SPIFFRX
0x704B
1
SPI-A FIFO Receive Register
SPIFFCT
0x704C
1
SPI-A FIFO Control Register
SPIPRI
0x704F
1
SPI-A Priority Control Register
Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Table 9-12. SPI-B Registers
(1)
DESCRIPTION(1)
NAME
ADDRESS
SIZE (x16)
SPICCR
0x7740
1
SPI-B Configuration Control Register
SPICTL
0x7741
1
SPI-B Operation Control Register
SPISTS
0x7742
1
SPI-B Status Register
SPIBRR
0x7744
1
SPI-B Baud Rate Register
SPIRXEMU
0x7746
1
SPI-B Receive Emulation Buffer Register
SPIRXBUF
0x7747
1
SPI-B Serial Input Buffer Register
SPITXBUF
0x7748
1
SPI-B Serial Output Buffer Register
SPIDAT
0x7749
1
SPI-B Serial Data Register
SPIFFTX
0x774A
1
SPI-B FIFO Transmit Register
SPIFFRX
0x774B
1
SPI-B FIFO Receive Register
SPIFFCT
0x774C
1
SPI-B FIFO Control Register
SPIPRI
0x774F
1
SPI-B Priority Control Register
Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
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Table 9-13. SPI-C Registers
(1)
DESCRIPTION(1)
NAME
ADDRESS
SIZE (x16)
SPICCR
0x7760
1
SPI-C Configuration Control Register
SPICTL
0x7761
1
SPI-C Operation Control Register
SPISTS
0x7762
1
SPI-C Status Register
SPIBRR
0x7764
1
SPI-C Baud Rate Register
SPIRXEMU
0x7766
1
SPI-C Receive Emulation Buffer Register
SPIRXBUF
0x7767
1
SPI-C Serial Input Buffer Register
SPITXBUF
0x7768
1
SPI-C Serial Output Buffer Register
SPIDAT
0x7769
1
SPI-C Serial Data Register
SPIFFTX
0x776A
1
SPI-C FIFO Transmit Register
SPIFFRX
0x776B
1
SPI-C FIFO Receive Register
SPIFFCT
0x776C
1
SPI-C FIFO Control Register
SPIPRI
0x776F
1
SPI-C Priority Control Register
Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Table 9-14. SPI-D Registers
NAME
(1)
ADDRESS
DESCRIPTION(1)
SIZE (x16)
SPICCR
0x7780
1
SPI-D Configuration Control Register
SPICTL
0x7781
1
SPI-D Operation Control Register
SPISTS
0x7782
1
SPI-D Status Register
SPIBRR
0x7784
1
SPI-D Baud Rate Register
SPIRXEMU
0x7786
1
SPI-D Receive Emulation Buffer Register
SPIRXBUF
0x7787
1
SPI-D Serial Input Buffer Register
SPITXBUF
0x7788
1
SPI-D Serial Output Buffer Register
SPIDAT
0x7789
1
SPI-D Serial Data Register
SPIFFTX
0x778A
1
SPI-D FIFO Transmit Register
SPIFFRX
0x778B
1
SPI-D FIFO Receive Register
SPIFFCT
0x778C
1
SPI-D FIFO Control Register
SPIPRI
0x778F
1
SPI-D Priority Control Register
Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Figure 9-14 is a block diagram of the SPI in slave mode.
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
SPIFFENA
SPIFFTX.14
Overrun
INT ENA
Receiver
Overrun Flag
RX FIFO Registers
SPIRXBUF
RX FIFO _0
RX FIFO _1
----RX FIFO _15
SPISTS.7
SPICTL.4
RX
FIFO
Interrupt
RX Interrupt
Logic
16
SPIINT/SPIRXINT
SPIFFOVF
FLAG
SPIRXBUF Buffer Register
To CPU
SPIFFRX.15
TX FIFO Registers
SPITXBUF
TX
FIFO
Interrupt
TX Interrupt
Logic
TX FIFO _15
----TX FIFO _1
TX FIFO _0
16
SPI
INT FLAG
SPITXINT
SPI
INT ENA
SPISTS.6
SPICTL.0
16
SPITXBUF Buffer Register
16
M
M
S
SPIDAT Data Register
S
SW1
SPISIMO
M
M
SPIDAT.15 - 0
S
S
SW2
SPISOMI
Talk
SPICTL.1
(A)
SPISTE
State Control
Master/Slave
SPI Char
SPICCR.3 - 0
3
2
1
SW3
M
SPI Bit Rate
LSPCLK
SPIBRR.6 - 0
6
5
4
3
SPICTL.2
S
0
2
1
0
S
Clock
Polarity
SPICCR.6
Clock
Phase
SPICTL.3
SPICLK
M
A. SPISTE is driven low by the master for a slave device.
Figure 9-14. SPI Module Block Diagram (Slave Mode)
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9.2.10 Inter-Integrated Circuit (I2C)
The 280x device contains one I2C Serial Port. Figure 9-15 shows how the I2C peripheral module interfaces
within the 280x device.
The I2C module has the following features:
• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
• One 16-word receive FIFO and one 16-word transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following
conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability
• Free data format mode
102
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
System Control Block
C28x CPU
I2CAENCLK
SYSCLKOUT
Peripheral Bus
SYSRS
Control
Data[16]
SDAA
GPIO
MUX
Data[16]
I2C-A
Addr[16]
SCLA
I2CINT1A
PIE
Block
I2CINT2A
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the
SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power operation. Upon reset,
I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 9-15. I2C Peripheral Module Interfaces
The registers in Table 9-15 configure and control the I2C port operation.
Table 9-15. I2C-A Registers
NAME
ADDRESS
I2COAR
0x7900
I2C own address register
DESCRIPTION
I2CIER
0x7901
I2C interrupt enable register
I2CSTR
0x7902
I2C status register
I2CCLKL
0x7903
I2C clock low-time divider register
I2CCLKH
0x7904
I2C clock high-time divider register
I2CCNT
0x7905
I2C data count register
I2CDRR
0x7906
I2C data receive register
I2CSAR
0x7907
I2C slave address register
I2CDXR
0x7908
I2C data transmit register
I2CMDR
0x7909
I2C mode register
I2CISRC
0x790A
I2C interrupt source register
I2CPSC
0x790C
I2C prescaler register
I2CFFTX
0x7920
I2C FIFO transmit register
I2CFFRX
0x7921
I2C FIFO receive register
I2CRSR
-
I2C receive shift register (not accessible to the CPU)
I2CXSR
-
I2C transmit shift register (not accessible to the CPU)
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9.2.11 GPIO MUX
On the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in
addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin is shown in
Figure 9-16. Because of the open-drain capabilities of the I2C pins, the GPIO MUX block diagram for these pins
differ. See the TMS320x280x, 2801x, 2804x DSP system control and interrupts reference guide for details.
GPIOXINT1SEL
GPIOLMPSEL
GPIOXINT2SEL
LPMCR0
GPIOXNMISEL
Low-Power
Modes Block
External Interrupt
MUX
PIE
GPxDAT (read)
Asynchronous
path
GPxQSEL1/2
GPxCTRL
GPxPUD
Input
Qualification
Internal
Pullup
00
N/C
01
Peripheral 1 Input
10
Peripheral 2 Input
11
Peripheral 3 Input
Asynchronous path
GPxTOGGLE
GPxCLEAR
GPxSET
GPIOx pin
00
GPxDAT (latch)
01
Peripheral 1 Output
10
Peripheral 2 Output
11
Peripheral 3 Output
High-Impedance
Output Control
00
0 = Input, 1 = Output
XRS
= Default at Reset
GPxDIR (latch)
01
Peripheral 1 Output Enable
10
Peripheral 2 Output Enable
11
Peripheral 3 Output Enable
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular
GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
Figure 9-16. GPIO MUX Block Diagram
104
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The 280x supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to
enable 32-bit operations on the registers (along with 16-bit operations). Table 9-16 shows the GPIO register
mapping.
Table 9-16. GPIO Registers
NAME
ADDRESS
GPACTRL
0x6F80
SIZE (x16)
DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
2
GPIO A Control Register (GPIO0 to 31)
GPAQSEL1
0x6F82
2
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL2
0x6F84
2
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX1
0x6F86
2
GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX2
0x6F88
2
GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR
0x6F8A
2
GPIO A Direction Register (GPIO0 to 31)
GPAPUD
0x6F8C
2
GPIO A Pull Up Disable Register (GPIO0 to 31)
Reserved
0x6F8E –
0x6F8F
2
Reserved
GPBCTRL
0x6F90
2
GPIO B Control Register (GPIO32 to 35)
GPBQSEL1
0x6F92
2
GPIO B Qualifier Select 1 Register (GPIO32 to 35)
GPBQSEL2
0x6F94
2
Reserved
GPBMUX1
0x6F96
2
GPIO B MUX 1 Register (GPIO32 to 35)
GPBMUX2
0x6F98
2
Reserved
GPBDIR
0x6F9A
2
GPIO B Direction Register (GPIO32 to 35)
GPBPUD
0x6F9C
2
GPIO B Pull Up Disable Register (GPIO32 to 35)
Reserved
0x6F9E –
0x6F9F
2
Reserved
Reserved
0x6FA0 –
0x6FBF
32
Reserved
GPADAT
0x6FC0
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
2
GPIO Data Register (GPIO0 to 31)
GPASET
0x6FC2
2
GPIO Data Set Register (GPIO0 to 31)
GPACLEAR
0x6FC4
2
GPIO Data Clear Register (GPIO0 to 31)
GPATOGGLE
0x6FC6
2
GPIO Data Toggle Register (GPIO0 to 31)
GPBDAT
0x6FC8
2
GPIO Data Register (GPIO32 to 35)
GPBSET
0x6FCA
2
GPIO Data Set Register (GPIO32 to 35)
GPBCLEAR
0x6FCC
2
GPIO Data Clear Register (GPIO32 to 35)
GPBTOGGLE
0x6FCE
2
GPIO Data Toggle Register (GPIO32 to 35)
Reserved
0x6FD0 –
0x6FDF
16
Reserved
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
0x6FE0
1
XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL
0x6FE1
1
XINT2 GPIO Input Select Register (GPIO0 to 31)
GPIOXNMISEL
0x6FE2
1
XNMI GPIO Input Select Register (GPIO0 to 31)
Reserved
0x6FE3 –
0x6FE7
5
Reserved
GPIOLPMSEL
0x6FE8
2
LPM GPIO Select Register (GPIO0 to 31)
Reserved
0x6FEA –
0x6FFF
22
Reserved
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
Table 9-17. F2808 GPIO MUX Table
GPAMUX1/2(3)
REGISTER
BITS
DEFAULT AT RESET
PRIMARY I/O
FUNCTION
(GPxMUX1/2
BITS = 0,0)
PERIPHERAL
SELECTION 1(1)
(GPxMUX1/2 BITS = 0,1)
1–0
GPIO0
3–2
PERIPHERAL
SELECTION 2
(GPxMUX1/2 BITS = 1,0)
PERIPHERAL
SELECTION 3
(GPxMUX1/2 BITS = 1,1)
EPWM1A (O)
Reserved(2)
Reserved(2)
GPIO1
EPWM1B (O)
SPISIMOD (I/O)
Reserved(2)
5–4
GPIO2
EPWM2A (O)
Reserved(2)
Reserved(2)
7–6
GPIO3
EPWM2B (O)
SPISOMID (I/O)
Reserved(2)
9–8
GPIO4
EPWM3A (O)
Reserved(2)
Reserved(2)
GPAMUX1
11–10
GPIO5
EPWM3B (O)
SPICLKD (I/O)
ECAP1 (I/O)
13–12
GPIO6
EPWM4A (O)
EPWMSYNCI (I)
EPWMSYNCO (O)
15–14
GPIO7
EPWM4B (O)
SPISTED (I/O)
ECAP2 (I/O)
17–16
GPIO8
EPWM5A (O)
CANTXB (O)
ADCSOCAO (O)
19–18
GPIO9
EPWM5B (O)
SCITXDB (O)
ECAP3 (I/O)
21–20
GPIO10
EPWM6A (O)
CANRXB (I)
ADCSOCBO (O)
23–22
GPIO11
EPWM6B (O)
SCIRXDB (I)
ECAP4 (I/O)
25–24
GPIO12
TZ1 (I)
CANTXB (O)
SPISIMOB (I/O)
27–26
GPIO13
TZ2 (I)
CANRXB (I)
SPISOMIB (I/O)
29–28
GPIO14
TZ3 (I)
SCITXDB (O)
SPICLKB (I/O)
31–30
GPIO15
TZ4 (I)
SCIRXDB (I)
SPISTEB (I/O)
GPAMUX2
1–0
GPIO16
SPISIMOA (I/O)
CANTXB (O)
TZ5 (I)
3–2
GPIO17
SPISOMIA (I/O)
CANRXB (I)
TZ6 (I)
5–4
GPIO18
SPICLKA (I/O)
SCITXDB (O)
Reserved(2)
7–6
GPIO19
SPISTEA (I/O)
SCIRXDB (I)
Reserved(2)
9–8
GPIO20
EQEP1A (I)
SPISIMOC (I/O)
CANTXB (O)
11–10
GPIO21
EQEP1B (I)
SPISOMIC (I/O)
CANRXB (I)
13–12
GPIO22
EQEP1S (I/O)
SPICLKC (I/O)
SCITXDB (O)
15–14
GPIO23
EQEP1I (I/O)
SPISTEC (I/O)
SCIRXDB (I)
17–16
GPIO24
ECAP1 (I/O)
EQEP2A (I)
SPISIMOB (I/O)
19–18
GPIO25
ECAP2 (I/O)
EQEP2B (I)
SPISOMIB (I/O)
21–20
GPIO26
ECAP3 (I/O)
EQEP2I (I/O)
SPICLKB (I/O)
23–22
GPIO27
ECAP4 (I/O)
EQEP2S (I/O)
SPISTEB (I/O)
TZ5 (I)
25–24
GPIO28
SCIRXDA (I)
Reserved(2)
27–26
GPIO29
SCITXDA (O)
Reserved(2)
TZ6 (I)
CANRXA (I)
Reserved(2)
Reserved(2)
Reserved(2)
Reserved(2)
29–28
GPIO30
31–30
GPIO31
CANTXA (O)
1–0
GPIO32
SDAA (I/OC)
EPWMSYNCI (I)
ADCSOCAO (O)
3–2
GPIO33
SCLA (I/OC)
EPWMSYNCO (O)
ADCSOCBO (O)
5–4
GPIO34
Reserved(2)
Reserved(2)
Reserved(2)
GPBMUX1
(1)
(2)
(3)
106
This table pertains to the 2808 device. Some peripherals may not be available in the 2809, 2806, 2802, or 2801 devices. See the pin
descriptions for more detail.
The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
GPxMUX1/2 refers to the appropriate MUX register for the pin; GPAMUX1, GPAMUX2 or GPBMUX1.
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The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from four
choices:
• Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0,0): This is the default mode of all GPIO pins at
reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
• Qualification Using Sampling Window (GPxQSEL1/2 = 0,1 and 1,0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the
input is allowed to change.
Time Between Samples
GPyCTRL Reg
SYNC
GPIOx
Qualification
Input Signal
Qualified by
3 or 6 Samples
GPxQSEL
SYSCLKOUT
Number of Samples
•
•
Figure 9-17. Qualification Using Sampling Window
The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling
window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the
same (all 0s or all 1s) as shown in Figure 8-10 (for 6-sample mode).
No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not
required (synchronization is performed within the peripheral).
Due to the multi-level multiplexing that is required on the 280x device, there may be cases where a peripheral
input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input
signal will default to either a 0 or 1 state, depending on the peripheral.
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9.3 Memory Maps
Block Start
Address
Prog Space
Data Space
0x00 0000
M0 Vector − RAM (32 x 32)
(Enabled if VMAP = 0)
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
0x00 0040
0x00 0400
M0 SARAM (1K y 16)
M1 SARAM (1K y 16)
0x00 0800
Low 64K [0000 − FFFF]
(24x/240x equivalent data space)
Peripheral Frame 0
0x00 0D00
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
Reserved
0x00 0E00
Reserved
0x00 6000
0x00 7000
Peripheral Frame 1
(protected)
Reserved
Peripheral Frame 2
(protected)
0x00 8000
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
0x00 9000
0x00 A000
L1 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
H0 SARAM (0-wait)
(8K y 16, Dual-Mapped)
0x00 C000
Reserved
0x3D 7800
0x3D 7C00
OTP
(1K y 16, Secure Zone)
Reserved
0x3D 8000
High 64K [3F0000 − 3FFFFF]
(24x/240x equivalent program space)
FLASH
(128K y 16, Secure Zone)
0x3F 7FF8
128-bit Password
0x3F 8000
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
0x3F 9000
0x3F A000
0x3F C000
L1 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
H0 SARAM (0-wait)
(8K y 16, Dual-Mapped)
Reserved
0x3F F000
Boot ROM (4K y 16)
0x3F FFC0
Vectors (32 y 32)
(enabled if VMAP = 1, ENPIE = 0)
A. Memory blocks are not to scale.
B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
C. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
D. Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 9-18. F2809 Memory Map
108
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
Block Start
Address
Prog Space
Data Space
0x00 0000
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
M0 Vector − RAM (32 x 32)
(Enabled if VMAP = 0)
0x00 0040
M0 SARAM (1K y 16)
0x00 0400
M1 SARAM (1K y 16)
0x00 0800
Low 64K [0000 − FFFF]
(24x/240x equivalent data space)
Peripheral Frame 0
0x00 0D00
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
Reserved
0x00 0E00
Reserved
0x00 6000
0x00 7000
Peripheral Frame 1
(protected)
Reserved
Peripheral Frame 2
(protected)
0x00 8000
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
0x00 9000
0x00 A000
L1 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
H0 SARAM (0-wait)
(8K y 16, Dual-Mapped)
0x00 C000
Reserved
0x3D 7800
OTP
(1K y 16, Secure Zone)
0x3D 7C00
Reserved
0x3E 8000
High 64K [3F0000 − 3FFFFF]
(24x/240x equivalent program space)
FLASH
(64K y 16, Secure Zone)
0x3F 7FF8
128-bit Password
0x3F 8000
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
0x3F 9000
0x3F A000
0x3F C000
L1 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
H0 SARAM (0-wait)
(8K y 16, Dual-Mapped)
Reserved
0x3F F000
Boot ROM (4K y 16)
0x3F FFC0
Vectors (32 y 32)
(enabled if VMAP = 1, ENPIE = 0)
A. Memory blocks are not to scale.
B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
C. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
D. Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 9-19. F2808 Memory Map
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
Block Start
Address
0x00 0000
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Prog Space
Data Space
M0 Vector − RAM (32 x 32)
(Enabled if VMAP = 0)
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
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0x00 0040
M0 SARAM (1K y 16)
0x00 0400
M1 SARAM (1K y 16)
Low 64K [0000−FFFF]
(24x/240x equivalent data space)
0x00 0800
Peripheral Frame 0
0x00 0D00
0x00 0E00
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
Reserved
Reserved
0x00 6000
Peripheral Frame 1
(protected)
0x00 7000
Peripheral Frame 2
(protected)
0x00 8000
0x00 9000
0x00 A000
Reserved
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
L1 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
Reserved
0x3D 7800
OTP
(1K y 16, Secure Zone)
0x3D 7C00
Reserved
High 64K [3F0000 −3FFFF]
(24x/240x equivalent program space)
0x3F 0000
0x3F 7FF8
FLASH
(32K y 16, Secure Zone)
128-bit Password
0x3F 8000
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
0x3F 9000
L1 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
0x3F A000
Reserved
0x3F F000
Boot ROM (4K y 16)
0x3F FFC0
Vectors (32 y 32)
(enabled if VMAP = 1, ENPIE = 0)
A. Memory blocks are not to scale.
B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
C. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
D. Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 9-20. F2806 Memory Map
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Block Start
Address
0x00 0000
Data Space
Prog Space
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M0 Vector − RAM (32 x 32)
(Enabled if VMAP = 0)
0x00 0040
M0 SARAM (1K y 16)
Low 64K [0000−FFFF]
(24x/240x equivalent data space)
0x00 0400
0x00 0800
M1 SARAM (1K y 16)
Peripheral Frame 0
0x00 0D00
0x00 0E00
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
Reserved
Reserved
0x00 6000
Peripheral Frame 1
(protected)
0x00 7000
0x00 8000
0x00 9000
Reserved
Peripheral Frame 2
(protected)
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
Reserved
0x3D 7800
0x3D 7C00
OTP (F2802 Only)(A)
(1K y 16, Secure Zone)
Reserved
High 64K [3F0000 −3FFFF]
(24x/240x equivalent program space)
0x3F 0000
0x3F 7FF8
0x3F 8000
FLASH (F2802) or ROM (C2802)
(32K y 16, Secure Zone)
128-bit Password
L0 (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
0x3F 9000
Reserved
0x3F F000
0x3F FFC0
Boot ROM (4K y 16)
Vectors (32 y 32)
(enabled if VMAP = 1, ENPIE = 0)
A. The 1K x 16 OTP has been replaced with 1K x 16 ROM in C2802.
B. Memory blocks are not to scale.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
D. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
F. Some locations in ROM are reserved for TI. See Table 9-22 for more information.
Figure 9-21. F2802, C2802 Memory Map
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Block Start
Address
0x00 0000
Data Space
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Prog Space
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M0 Vector − RAM (32 x 32)
(Enabled if VMAP = 0)
0x00 0040
Low 64K [0000−FFFF]
(24x/240x equivalent data space)
0x00 0400
0x00 0800
M0 SARAM (1K y 16)
M1 SARAM (1K y 16)
Peripheral Frame 0
0x00 0D00
0x00 0E00
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
Reserved
Reserved
0x00 6000
Peripheral Frame 1
(protected)
0x00 7000
0x00 8000
0x00 9000
Reserved
Peripheral Frame 2
(protected)
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
Reserved
0x3D 7800
0x3D 7C00
OTP (F2801/F2801x Only)(A)
(1K y 16, Secure Zone)
Reserved
High 64K [3F0000 −3FFFF]
(24x/240x equivalent program space)
0x3F 4000
0x3F 7FF8
0x3F 8000
FLASH (F2801) or ROM (C2801)
(16K y 16, Secure Zone)
128-bit Password
L0 (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
0x3F 9000
Reserved
0x3F F000
0x3F FFC0
Boot ROM (4K y 16)
Vectors (32 y 32)
(enabled if VMAP = 1, ENPIE = 0)
A. The 1K x 16 OTP has been replaced with 1K x 16 ROM in C2801.
B. Memory blocks are not to scale.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
D. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
F. Some locations in ROM are reserved for TI. See Table 9-22 for more information.
Figure 9-22. F2801, F28015, F28016, C2801 Memory Map
Table 9-18. Addresses of Flash Sectors in F2809
112
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3D 8000 – 0x3D BFFF
Sector H (16K x 16)
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Table 9-18. Addresses of Flash Sectors in F2809 (continued)
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3D C000 – 0x3D FFFF
Sector G (16K x 16)
0x3E 0000 – 0x3E 3FFF
Sector F (16K x 16)
0x3E 4000 – 0x3E 7FFF
Sector E (16K x 16)
0x3E 8000 – 0x3E BFFF
Sector D (16K x 16)
0x3E C000 – 0x3E FFFF
Sector C (16K x 16)
0x3F 0000 – 0x3F 3FFF
Sector B (16K x 16)
0x3F 4000 – 0x3F 7F7F
Sector A (16K x 16)
0x3F 7F80 – 0x3F 7FF5
Program to 0x0000 when using the
Code Security Module
0x3F 7FF6 – 0x3F 7FF7
Boot-to-Flash Entry Point
(program branch instruction here)
0x3F 7FF8 – 0x3F 7FFF
Security Password (128-Bit)
(Do not program to all zeros)
Table 9-19. Addresses of Flash Sectors in F2808
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3E 8000 – 0x3E BFFF
Sector D (16K x 16)
0x3E C000 – 0x3E FFFF
Sector C (16K x 16)
0x3F 0000 – 0x3F 3FFF
Sector B (16K x 16)
0x3F 4000 – 0x3F 7F7F
Sector A (16K x 16)
0x3F 7F80 – 0x3F 7FF5
Program to 0x0000 when using the
Code Security Module
0x3F 7FF6 – 0x3F 7FF7
Boot-to-Flash Entry Point
(program branch instruction here)
0x3F 7FF8 – 0x3F 7FFF
Security Password (128-Bit)
(Do not program to all zeros)
Table 9-20. Addresses of Flash Sectors in F2806, F2802
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3F 0000 – 0x3F 1FFF
Sector D (8K x 16)
0x3F 2000 – 0x3F 3FFF
Sector C (8K x 16)
0x3F 4000 – 0x3F 5FFF
Sector B (8K x 16)
0x3F 6000 – 0x3F 7F7F
Sector A (8K x 16)
0x3F 7F80 – 0x3F 7FF5
Program to 0x0000 when using the
Code Security Module
0x3F 7FF6 – 0x3F 7FF7
Boot-to-Flash Entry Point
(program branch instruction here)
0x3F 7FF8 – 0x3F 7FFF
Security Password (128-Bit)
(Do not program to all zeros)
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Table 9-21. Addresses of Flash Sectors in F2801, F28015, F28016
•
•
•
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3F 4000 – 0x3F 4FFF
Sector D (4K x 16)
0x3F 5000 – 0x3F 5FFF
Sector C (4K x 16)
0x3F 6000 – 0x3F 6FFF
Sector B (4K x 16)
0x3F 7000 – 0x3F 7F7F
Sector A (4K x 16)
0x3F 7F80 – 0x3F 7FF5
Program to 0x0000 when using the
Code Security Module
0x3F 7FF6 – 0x3F 7FF7
Boot-to-Flash Entry Point
(program branch instruction here)
0x3F 7FF8 – 0x3F 7FFF
Security Password (128-Bit)
(Do not program to all zeros)
Note
When the code-security passwords are programmed, all addresses between 0x3F7F80 and
0x3F7FF5 cannot be used as program code or data. These locations must be programmed to
0x0000.
If the code security feature is not used, addresses 0x3F7F80 through 0x3F7FEF may be used for
code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data and should not contain
program code.
On ROM devices, addresses 0x3F7FF0 – 0x3F7FF5 and 0x3D7BFC – 0x3D7BFF are reserved for
TI, irrespective of whether code security has been used or not. User application should not use
these locations in any way.
Table 9-22 shows how to handle these memory locations.
Table 9-22. Impact of Using the Code Security Module
ADDRESS
FLASH
Code security enabled
0x3F 7F80 – 0x3F 7FEF
0x3F 7FF0 – 0x3F 7FF5
0x3D 7BFC – 0x3D 7BFF
Fill with 0x0000
ROM
Code security disabled
Code security enabled
Code security disabled
Application code and data
Fill with 0x0000
Application code and data
Reserved for data only
Application code and data
Reserved for TI. Do not use.
Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to be write/read
peripheral block protected. The protected mode ensures that all accesses to these blocks happen as written.
Because of the C28x pipeline, a write immediately followed by a read, to different memory locations, will appear
in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications
where the user expected the write to occur first (as written). The C28x CPU supports a block protection mode
where a region of memory can be protected so as to make sure that operations occur as written (the penalty is
extra cycles are added to align the operations). This mode is programmable and by default, it will protect the
selected zones.
114
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The wait-states for the various spaces in the memory map area are listed in Table 9-23.
Table 9-23. Wait-states
AREA
WAIT-STATES
COMMENTS
M0 and M1 SARAMs
0-wait
Fixed
Peripheral Frame 0
0-wait
Fixed
Peripheral Frame 1
0-wait (writes)
2-wait (reads)
Fixed. The eCAN peripheral can extend a cycle as
needed. Back-to-back writes will introduce a 1-cycle delay.
Peripheral Frame 2
0-wait (writes)
2-wait (reads)
Fixed
L0 and L1 SARAMs
0-wait
OTP
Programmed via the Flash registers. 1-wait-state
Programmable,
operation is possible at a reduced CPU frequency. See
1-wait minimum
Section 9.1.5 for more information.
Flash
Programmed via the Flash registers. 0-wait-state
Programmable, operation is possible at reduced CPU frequency. The CSM
0-wait minimum password locations are hardwired for 16 wait-states. See
Section 9.1.5 for more information.
H0 SARAM
0-wait
Fixed
Boot-ROM
1-wait
Fixed
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9.4 Register Map
The 280x devices contain three peripheral register spaces. The spaces are categorized as follows:
Peripheral
Frame 0:
These are peripherals that are mapped directly to the CPU memory bus.
See Table 9-24.
Peripheral
Frame 1
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 9-25 .
Peripheral
Frame 2:
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 9-26 .
Table 9-24. Peripheral Frame 0 Registers
NAME(1) (2)
ACCESS TYPE(3)
ADDRESS RANGE
SIZE (x16)
Device Emulation Registers
0x0880 – 0x09FF
384
EALLOW protected
FLASH Registers(4)
0x0A80 – 0x0ADF
96
EALLOW protected
CSM Protected
Code Security Module Registers
0x0AE0 – 0x0AEF
16
EALLOW protected
ADC Result Registers (dual-mapped)
0x0B00 – 0x0B0F
16
Not EALLOW protected
CPU-TIMER0/1/2 Registers
0x0C00 – 0x0C3F
64
Not EALLOW protected
PIE Registers
0x0CE0 – 0x0CFF
32
Not EALLOW protected
PIE Vector Table
0x0D00 – 0x0DFF
256
EALLOW protected
(1)
(2)
(3)
(4)
116
Registers in Frame 0 support 16-bit and 32-bit accesses.
Missing segments of memory space are reserved and should not be used in applications.
If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
The Flash Registers are also protected by the Code Security Module (CSM).
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Table 9-25. Peripheral Frame 1 Registers
NAME(1) (2)
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
eCANA Registers
0x6000 – 0x60FF
256
Some eCAN control registers (and selected
bits in other eCAN control registers) are
EALLOW-protected.
eCANA Mailbox RAM
0x6100 – 0x61FF
256
Not EALLOW-protected
eCANB Registers
0x6200 – 0x62FF
256
Some eCAN control registers (and selected
bits in other eCAN control registers) are
EALLOW-protected.
eCANB Mailbox RAM
0x6300 – 0x63FF
256
Not EALLOW-protected
ePWM1 Registers
0x6800 – 0x683F
64
ePWM2 Registers
0x6840 – 0x687F
64
ePWM3 Registers
0x6880 – 0x68BF
64
ePWM4 Registers
0x68C0 – 0x68FF
64
ePWM5 Registers
0x6900 – 0x693F
64
ePWM6 Registers
0x6940 – 0x697F
64
eCAP1 Registers
0x6A00 – 0x6A1F
32
eCAP2 Registers
0x6A20 – 0x6A3F
32
eCAP3 Registers
0x6A40 – 0x6A5F
32
eCAP4 Registers
0x6A60 – 0x6A7F
32
eQEP1 Registers
0x6B00 – 0x6B3F
64
eQEP2 Registers
0x6B40 – 0x6B7F
64
GPIO Control Registers
0x6F80 – 0x6FBF
128
EALLOW protected
GPIO Data Registers
0x6FC0 – 0x6FDF
32
Not EALLOW protected
GPIO Interrupt and LPM Select Registers
0x6FE0 – 0x6FFF
32
EALLOW protected
(1)
(2)
Some ePWM registers are EALLOW
protected. See Table 9-3.
Not EALLOW protected
The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
Missing segments of memory space are reserved and should not be used in applications.
Table 9-26. Peripheral Frame 2 Registers
NAME(1) (2)
ADDRESS RANGE
SIZE (x16)
System Control Registers
0x7010 – 0x702F
32
SPI-A Registers
0x7040 – 0x704F
16
SCI-A Registers
0x7050 – 0x705F
16
External Interrupt Registers
0x7070 – 0x707F
16
ADC Registers
0x7100 – 0x711F
32
SPI-B Registers
0x7740 – 0x774F
16
SCI-B Registers
0x7750 – 0x775F
16
SPI-C Registers
0x7760 – 0x776F
16
SPI-D Registers
0x7780 – 0x778F
16
I2C Registers
0x7900 – 0x792F
48
(1)
(2)
ACCESS TYPE
EALLOW Protected
Not EALLOW Protected
Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
Missing segments of memory space are reserved and should not be used in applications.
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9.4.1 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. The registers are defined in Table 9-27.
Table 9-27. Device Emulation Registers
ADDRESS
RANGE
SIZE (x16)
DEVICECNF
0x0880
0x0881
2
Device Configuration Register
PARTID
0x0882
1
Part ID Register
0x002C(1) - F2801
0x0024 – F2802
0x0034 – F2806
0x003C – F2808
0x00FE – F2809
0x0014 – F28016
0x001C – F28015
0xFF2C – C2801
0xFF24 – C2802
REVID
0x0883
1
Revision ID Register
0x0000 – Silicon Rev. 0 – TMX
0x0001 – Silicon Rev. A – TMX
0x0002 – Silicon Rev. B – TMS
0x0003 – Silicon Rev. C – TMS
Revision ID Register
0x0000 – Silicon rev. 0 – TMS (F2809 only)
0x0001 – Silicon rev. A – TMS (F2809 only)
NAME
DESCRIPTION
PROTSTART
0x0884
1
Block Protection Start Address Register
PROTRANGE
0x0885
1
Block Protection Range Address Register
(1)
118
The first byte (00) denotes flash devices. FF denotes ROM devices. Other values are reserved for future devices.
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9.5 Interrupts
Figure 9-23 shows how the various interrupt sources are multiplexed within the 280x devices.
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts
per group equals 96 possible interrupts. On the 280x, 43 of these are used by peripherals as shown in Table
9-28.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to
the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by the reset vector.
The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when
the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service
routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from
INT1.1, TRAP #2 fetches the vector from INT2.1 and so forth.
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Peripherals
(SPI, SCI, I2C, eCAN, ePWM, eCAP, eQEP, ADC)
WDINT
WAKEINT
XINT1
XINT1
Interrupt Control
Low-Power Modes
MUX
LPMINT
Watchdog
96 Interrupts
XINT1CTR(15:0)
GPIOXINT1SEL(4:0)
ADC
XINT2
XINT2SOC
XINT2
Interrupt Control
MUX
INT1
to
INT12
PIE
XINT1CR(15:0)
XINT2CR(15:0)
C28x
CPU
XINT2CTR(15:0)
GPIOXINT2SEL(4:0)
TINT0
CPU TIMER 0
TINT2
INT14
CPU TIMER 2 (Reserved for SYS/BIOS)
TINT1
MUX
INT13
CPU TIMER 1
int13_select
GPIO0.int
XNMI_XINT13
MUX
NMI
Interrupt Control
MUX
nmi_select
GPIO
MUX
XNMICR(15:0)
GPIO31.int
1
XNMICTR(15:0)
GPIOXNMISEL(4:0)
Figure 9-23. External and PIE Interrupt Sources
120
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IFR[12:1]
INTM
IER[12:1]
INT1
INT2
1
CPU
MUX
0
INT11
INT12
(Flag)
INTx
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
MUX
PIEACKx
(Enable/Flag)
Global
Enable
(Enable)
(Enable)
(Flag)
PIEIERx[8:1]
PIEIFRx[8:1]
From
Peripherals
or
External
Interrupts
Figure 9-24. Multiplexing of Interrupts Using the PIE Block
Table 9-28. PIE Peripheral Interrupts
CPU
INTERRUPTS
(1)
(2)
PIE INTERRUPTS
(1)
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
INT1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT(2)
(ADC)
XINT2
XINT1
Reserved
SEQ2INT
(ADC)
SEQ1INT
(ADC)
INT2
Reserved
Reserved
INT3
Reserved
Reserved
EPWM6_INT
(ePWM6)
EPWM5_INT
(ePWM5)
EPWM4_INT
(ePWM4)
EPWM3_INT
(ePWM3)
EPWM2_INT
(ePWM2)
EPWM1_INT
(ePWM1)
INT4
Reserved
Reserved
Reserved
Reserved
ECAP4_INT
(eCAP4)
ECAP3_INT
(eCAP3)
ECAP2_INT
(eCAP2)
ECAP1_INT
(eCAP1)
INT5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EQEP2_INT
(eQEP2)
EQEP1_INT
(eQEP1)
INT6
SPITXINTD
(SPI-D)
SPIRXINTD
(SPI-D)
SPITXINTC
(SPI-C)
SPIRXINTC
(SPI-C)
SPITXINTB
(SPI-B)
SPIRXINTB
(SPI-B)
SPITXINTA
(SPI-A)
SPIRXINTA
(SPI-A)
INT7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I2CINT1A
(I2C-A)
EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT
(ePWM6)
(ePWM5)
(ePWM4)
(ePWM3)
(ePWM2)
(ePWM1)
INT8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I2CINT2A
(I2C-A)
INT9
ECAN1_INTB
(CAN-B)
ECAN0_INTB
(CAN-B)
ECAN1_INTA
(CAN-A)
ECAN0_INTA
(CAN-A)
SCITXINTB
(SCI-B)
SCIRXINTB
(SCI-B)
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
INT10
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
INT11
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
INT12
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Out of the 96 possible interrupts, 43 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group
is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 12).
ADCINT is sourced as a logical "OR" of both the SEQ1INT and SEQ2INT signals. This is to support backward compatibility with the
implementation found on the TMS320F281x series of devices, where SEQ1INT and SEQ2INT did not exist, only ADCINT. For new
implementations, TI recommends using SEQ1INT and SEQ2INT and not enabling ADCINT in the PIEIER register.
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Table 9-29. PIE Configuration and Control Registers
NAME
PIECTRL
SIZE (x16)
0x0CE0
1
DESCRIPTION(1)
PIE, Control Register
PIEACK
0x0CE1
1
PIE, Acknowledge Register
PIEIER1
0x0CE2
1
PIE, INT1 Group Enable Register
PIEIFR1
0x0CE3
1
PIE, INT1 Group Flag Register
PIEIER2
0x0CE4
1
PIE, INT2 Group Enable Register
PIEIFR2
0x0CE5
1
PIE, INT2 Group Flag Register
PIEIER3
0x0CE6
1
PIE, INT3 Group Enable Register
PIEIFR3
0x0CE7
1
PIE, INT3 Group Flag Register
PIEIER4
0x0CE8
1
PIE, INT4 Group Enable Register
PIEIFR4
0x0CE9
1
PIE, INT4 Group Flag Register
PIEIER5
0x0CEA
1
PIE, INT5 Group Enable Register
PIEIFR5
0x0CEB
1
PIE, INT5 Group Flag Register
PIEIER6
0x0CEC
1
PIE, INT6 Group Enable Register
PIEIFR6
0x0CED
1
PIE, INT6 Group Flag Register
PIEIER7
0x0CEE
1
PIE, INT7 Group Enable Register
PIEIFR7
0x0CEF
1
PIE, INT7 Group Flag Register
PIEIER8
0x0CF0
1
PIE, INT8 Group Enable Register
PIEIFR8
0x0CF1
1
PIE, INT8 Group Flag Register
PIEIER9
0x0CF2
1
PIE, INT9 Group Enable Register
PIEIFR9
0x0CF3
1
PIE, INT9 Group Flag Register
PIEIER10
0x0CF4
1
PIE, INT10 Group Enable Register
PIEIFR10
0x0CF5
1
PIE, INT10 Group Flag Register
PIEIER11
0x0CF6
1
PIE, INT11 Group Enable Register
PIEIFR11
0x0CF7
1
PIE, INT11 Group Flag Register
PIEIER12
0x0CF8
1
PIE, INT12 Group Enable Register
PIEIFR12
0x0CF9
1
PIE, INT12 Group Flag Register
Reserved
0x0CFA –
0x0CFF
6
Reserved
(1)
122
ADDRESS
The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector
table is protected.
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9.5.1 External Interrupts
Table 9-30. External Interrupt Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
XINT1CR
0x7070
1
XINT1 control register
XINT2CR
0x7071
1
XINT2 control register
Reserved
0x7072 – 0x7076
5
Reserved
XNMICR
0x7077
1
XNMI control register
XINT1CTR
0x7078
1
XINT1 counter register
XINT2CTR
0x7079
1
XINT2 counter register
Reserved
0x707A – 0x707E
5
Reserved
XNMICTR
0x707F
1
XNMI counter register
Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the TMS320x280x, 2801x, 2804x DSP system control and interrupts
reference guide.
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9.6 System Control
This section describes the 280x oscillator, PLL and clocking mechanisms, the watchdog function and the low
power modes. Figure 9-25 shows the various clock and reset domains in the 280x devices that will be discussed.
Reset
XRS
Watchdog
Block
(A)
SYSCLKOUT
Peripheral Reset
CLKIN
X1
(A)
28x
CPU
PLL
Peripheral
Registers
Peripheral Bus
System
Control
Registers
OSC
Power
Modes
Control
CPU
Timers
X2
XCLKIN
Clock Enables
Peripheral
Registers
ePWM 1/2/3/4/5/6
eCAP 1/2/3/4 eQEP 1/2
I/O
Peripheral
Registers
eCAN-A/B
I2C-A
I/O
GPIO
MUX
GPIOs
Low-Speed Prescaler
LSPCLK
Peripheral
Registers
Low-Speed Peripherals
SCI-A/B, SPI-A/B/C/D
I/O
High-Speed Prescaler
HSPCLK
ADC
Registers
12-Bit ADC
16 ADC Inputs
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as SYSCLKOUT).
Figure 9-25. Clock and Reset Domains
124
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The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 9-31.
Table 9-31. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME(1)
ADDRESS
SIZE (x16)
DESCRIPTION
XCLK
0x7010
1
XCLKOUT Pin Control, X1 and XCLKIN Status Register
PLLSTS
0x7011
1
PLL Status Register
Reserved
0x7012 – 0x7019
8
Reserved
HISPCP
0x701A
1
High-Speed Peripheral Clock Prescaler Register (for HSPCLK)
LOSPCP
0x701B
1
Low-Speed Peripheral Clock Prescaler Register (for LSPCLK)
PCLKCR0
0x701C
1
Peripheral Clock Control Register 0
PCLKCR1
0x701D
1
Peripheral Clock Control Register 1
LPMCR0
0x701E
1
Low-Power Mode Control Register 0
Reserved
0x701F – 0x7020
1
Reserved
PLLCR
0x7021
1
PLL Control Register
SCSR
0x7022
1
System Control and Status Register
WDCNTR
0x7023
1
Watchdog Counter Register
Reserved
0x7024
1
Reserved
WDKEY
0x7025
1
Watchdog Reset Key Register
0x7026 – 0x7028
3
Reserved
0x7029
1
Watchdog Control Register
0x702A – 0x702F
6
Reserved
Reserved
WDCR
Reserved
(1)
All of the registers in this table are EALLOW protected.
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9.6.1 OSC and PLL Block
Figure 9-26 shows the OSC and PLL block on the 280x.
XCLKIN
(3.3-V Clock Input)
OSCCLK
OSCCLK
XOR
PLLSTS[OSCOFF]
PLL
VCOCLK
OSCCLK
or
VCOCLK
0
n
n
CLKIN
0
/2
PLLSTS[PLLOFF]
PLLSTS[CLKINDIV]
X1
On-Chip
Oscillator
4-bit PLL Select
(PLLCR)
X2
Figure 9-26. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the 280x devices using the X1 and X2
pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the following
configurations:
1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low. The logic-high level in this case should not exceed VDDIO.
2. A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left unconnected
and the XCLKIN pin tied low. The logic-high level in this case should not exceed VDD.
The three possible input-clock configurations are shown in Figure 9-27 through Figure 9-29.
XCLKIN
X1
X2
NC
External Clock Signal
(Toggling 0-VDDIO)
Figure 9-27. Using a 3.3-V External Oscillator
XCLKIN
X1
X2
External Clock Signal
(Toggling 0-VDD)
NC
Figure 9-28. Using a 1.8-V External Oscillator
XCLKIN
X1
X2
CL1
CL2
Crystal
Figure 9-29. Using the Internal Oscillator
126
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9.6.1.1 External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 20 MHz are listed below:
• Fundamental mode, parallel resonant
• CL (load capacitance) = 12 pF
• CL1 = CL2 = 24 pF
• Cshunt = 6 pF
• ESR range = 30 to 60 Ω
TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with
the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor
can also advise the customer regarding the proper tank component values that will produce proper start up and
stability over the entire operating range.
9.6.1.2 PLL-Based Clock Module
The 280x devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking
signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV]
to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR
register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 131072 OSCCLK
cycles.
Table 9-32. PLLCR Register Bit Definitions
SYSCLKOUT
(CLKIN)(2)
PLLCR[DIV](1)
(1)
(2)
0000 (PLL bypass)
OSCCLK/n
0001
(OSCCLK*1)/n
0010
(OSCCLK*2)/n
0011
(OSCCLK*3)/n
0100
(OSCCLK*4)/n
0101
(OSCCLK*5)/n
0110
(OSCCLK*6)/n
0111
(OSCCLK*7)/n
1000
(OSCCLK*8)/n
1001
(OSCCLK*9)/n
1010
(OSCCLK*10)/n
1011–1111
Reserved
This register is EALLOW protected.
CLKIN is the input clock to the CPU. SYSCLKOUT is the output
clock from the CPU. The frequency of SYSCLKOUT is the same
as CLKIN. If CLKINDIV = 0, n = 2; if CLKINDIV = 1, n = 1.
Note
PLLSTS[CLKINDIV] enables or bypasses the divide-by-two block before the clock is fed to the core.
This bit must be 0 before writing to the PLLCR and must only be set after PLLSTS[PLLLOCKS] = 1.
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The PLL-based clock module provides two modes of operation:
• Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base to the
device.
• External clock source operation - This mode allows the internal oscillator to be bypassed. The device clocks
are generated from an external clock source input on the X1 or the XCLKIN pin.
Table 9-33. Possible PLL Configuration Modes
PLLSTS[CLKINDIV
]
SYSCLKOUT
(CLKIN)
0
OSCCLK/2
PLL Off
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
1
OSCCLK
0
OSCCLK/2
PLL Bypass
PLL Bypass is the default PLL configuration upon power-up or after an external
reset ( XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
1
OSCCLK
PLL Enable
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
0
OSCCLK*n/2
PLL MODE
REMARKS
9.6.1.3 Loss of Input Clock
In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still issue a
limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1–
5 MHz. Limp mode is not specified to work from power-up, only after input clocks have been present initially. In
PLL bypass mode, the limp mode clock from the PLL is automatically routed to the CPU if the input clock is
removed or absent.
Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog reset or
WDINT interrupt. However, when the external input clock fails, the watchdog counter stops decrementing (that is,
the watchdog counter does not change with the limp-mode clock). In addition to this, the device will be reset and
the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions could be used by the application
firmware to detect the input clock failure and initiate necessary shut-down procedure for the system.
Note
Applications in which the correct CPU operating frequency is absolutely critical should implement a
mechanism by which the DSP will be held in reset, should the input clocks ever fail. For example, an
R-C circuit may be used to trigger the XRS pin of the DSP, should the capacitor ever get fully charged.
An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully
charged. Such a circuit would also help in detecting failure of the flash memory and the VDD3VFL rail.
128
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9.6.2 Watchdog Block
The watchdog block on the 280x is similar to the one used on the 240x and 281x devices. The watchdog module
generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has
reached its maximum value. To prevent this, the user disables the counter or the software must periodically write
a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog counter. Figure 9-30
shows the various functional blocks within the watchdog module.
WDCR (WDPS[2:0])
WDCR (WDDIS)
WDCNTR[7:0]
OSCCLK
Watchdog
Prescaler
/512
WDCLK
8-Bit
Watchdog
Counter
CLR
Clear Counter
Internal
Pullup
WDKEY[7:0]
Watchdog
55 + AA
Key Detector
Generate
Output Pulse
(512 OSCCLKs)
Good Key
WDRST
WDINT
XRS
Core-reset
Bad
WDCHK
Key
SCSR (WDENINT)
WDCR (WDCHK[2:0])
(A)
WDRST
1
0
1
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 9-30. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is
the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the LPM block so that
it can wake the device from STANDBY (if enabled). See Section 9.7, Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE
mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the
WATCHDOG.
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129
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
9.7 Low-Power Modes Block
The low-power modes on the 280x are similar to the 240x devices. Table 9-34 summarizes the various modes.
Table 9-34. Low-Power Modes
EXIT(1)
MODE
LPMCR0(1:0)
OSCCLK
CLKIN
SYSCLKOUT
IDLE
00
On
On
On(2)
XRS, Watchdog interrupt, any enabled
interrupt, XNMI
STANDBY
01
On
(watchdog still running)
Off
Off
XRS, Watchdog interrupt, GPIO Port A
signal, debugger(3), XNMI
HALT
1X
Off
(oscillator and PLL turned off,
watchdog not functional)
Off
Off
XRS, GPIO Port A signal, XNMI,
debugger(3)
(1)
(2)
(3)
The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will
exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the
IDLE mode will not be exited and the device will go back into the indicated low power mode.
The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is
still functional while on the 24x/240x the clock is turned off.
On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor. The
LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode:
Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must
select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are
also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the
LPMCR0 register.
HALT Mode:
Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT mode. The
user selects the signal in the GPIOLPMSEL register.
Note
The low-power modes do not affect the state of the output pins (PWM pins included). They will be in
whatever state the code left them in when the IDLE instruction was executed. See the TMS320x280x,
2801x, 2804x DSP system control and interrupts reference guide for more details.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
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SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
10 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 TI Design or Reference Design
TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at TIDesigns.
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131
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
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11 Device and Documentation Support
11.1 Getting Started
This section gives a brief overview of the steps to take when first developing for a C28x device. For more detail
on each of these steps, see the following:
• C2000 Real-Time Control MCUs – Getting started
• C2000 Real-Time Control MCUs – Tools & software
Step 1. Acquire the appropriate development tools
The quickest way to begin working with a C28x device is to acquire an eZdsp™ kit for initial development, which,
in one package, includes:
• On-board JTAG emulation via USB or parallel port
• Appropriate emulation driver
• Code Composer Studio™ IDE for eZdsp
Once you have become familiar with the device and begin developing on your own hardware, purchase Code
Composer Studio™ IDE separately for software development and a JTAG emulation tool to get started on your
project.
Step 2. Download starter software
To simplify programming for C28x devices, it is recommended that users download and use the C/C++ Header
Files and Example(s) to begin developing software for the C28x devices and their various peripherals.
After downloading the appropriate header file package for your device, refer to the following resources for stepby-step instructions on how to run the peripheral examples and use the header file structure for your own
software
• The Quick Start Readme in the /doc directory to run your first application.
• Programming TMS320x28xx and 28xxx peripherals in C/C++ application report
Step 3. Download flash programming software
Many C28x devices include on-chip flash memory and tools that allow you to program the flash with your
software IP.
• Flash Tools: C28x Flash Tools
• TMS320F281x™ flash programming solutions
• Running an application from internal flash memory on the TMS320F28xxx DSP
Step 4. Move on to more advanced topics
For more application software and other advanced topics, visit C2000 real-time control MCUs – Tools &
software.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
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11.2 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ DSP devices and support tools. Each TMS320™ DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS (for example, TMS 320F2808). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages
of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/
tools (TMS/TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device's electrical specifications
TMP
Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability
verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification testing
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PZ) and temperature range (for example, S). Figure 11-1 provides a legend for reading the
complete device name for any family member.
For device part numbers and further ordering information, see the Package Option Addendum of this document,
the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F280x,
TMS320C280x, TMS320F2801x DSPs silicon errata.
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133
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
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Figure 11-1. Example of TMS320x280x/2801x Device Nomenclature
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
11.3 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions are listed below. To view all available tools and software, visit
the Tools & software page for each device.
Software
C28x IQMath Library - A Virtual Floating Point Engine
Texas Instruments TMS320C28x IQmath Library is collection of highly optimized and high precision
mathematical Function Library for C/C++ programmers to seamlessly port the floating-point algorithm into fixed
point code on TMS320C28x devices. These routines are typically used in computationally intensive real-time
applications where optimal execution speed & high accuracy is critical. By using these routines you can achieve
execution speeds considerable faster than equivalent code written in standard ANSI C language. In addition, by
providing ready-to-use high precision functions, TI IQmath library can shorten significantly your DSP application
development time. (Please find the IQ Math User's Guide in the /docs folder once the file is extracted and
installed).
C280x, C2801x C/C++ Header Files and Peripheral Examples
This utility contains Hardware Abstraction Layer (HAL) for TMS320x280x and TMS320x280xx DSP devices. This
HAL facilitates peripheral configuration using "C". It also contains a simple test program for each peripheral to
exemplify the usage of HAL to control & configure the on-chip peripheral.
Development Tools
C2000 Gang Programmer
The C2000 Gang Programmer is a C2000 device programmer that can program up to eight identical C2000
devices at the same time. The C2000 Gang Programmer connects to a host PC using a standard RS-232 or
USB connection and provides flexible programming options that allow the user to fully customize the process.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user
through each step of the application development flow. Familiar tools and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework
with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development
environment for embedded developers.
Uniflash Standalone Flash Tool
CCS Uniflash is a standalone tool used to program on-chip flash memory on TI MCUs.
Models
Various models are available for download from the product Tools & Software pages. These include I/O Buffer
Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all
available models, visit the Models section of the Tools & Software page for each device.
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www.ti.com
11.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral is
listed below.
Errata
TMS320F280x, TMS320C280x, TMS320F2801x DSPs silicon errata describes the advisories and usage notes
for different versions of silicon.
CPU User's Guides
TMS320C28x CPU and instruction set reference guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also
describes emulation features available on these DSPs.
TMS320x280x, 2801x, 2804x DSP system control and interrupts reference guide describes the various interrupts
and system control features of the 280x digital signal processors (DSPs).
Peripheral Guides
C2000 real-time control peripherals reference guide describes the peripheral reference guides of the 28x digital
signal processors (DSPs).
TMS320x280x, 2801x, 2804x DSP Analog-to-Digital Converter (ADC) reference guide describes how to
configure and use the on-chip ADC module, which is a 12-bit pipelined ADC.
TMS320x280x, 2801x, 2804x Enhanced Pulse Width Modulator (ePWM) module reference guide describes the
main areas of the enhanced pulse width modulator that include digital motor control, switch mode power supply
control, UPS (uninterruptible power supplies), and other forms of power conversion.
TMS320x280x, 2801x, 2804x Enhanced Quadrature Encoder Pulse (eQEP) module reference guide describes
the eQEP module, which is used for interfacing with a linear or rotary incremental encoder to get position,
direction, and speed information from a rotating machine in high performance motion and position control
systems. It includes the module description and registers.
TMS320x280x, 2801x, 2804x Enhanced Capture (eCAP) module reference guide describes the enhanced
capture module. It includes the module description and registers.
TMS320x280x, 2801x, 2804x High Resolution Pulse Width Modulator (HRPWM) reference guide describes the
operation of the high-resolution extension to the pulse width modulator (HRPWM).
TMS320x280x/2801x Enhanced Controller Area Network (eCAN) reference guide describes the enhanced
controller area network (eCAN) on the x280x and x2801x devices.
TMS320x280x, 2801x, 2804x Serial Communications Interface (SCI) reference guide describes the features and
operation of the serial communication interface (SCI) module that is available on the TMS320x280x, 2801x,
2804x devices.
TMS320x280x, 2801x, 2804x Serial Peripheral Interface reference guide describes how the serial peripheral
interface works.
TMS320x280x, 2801x, 2804x Inter-Integrated Circuit (I2C) module reference guide describes the features and
operation of the inter-integrated circuit (I2C) module.
TMS320x280x, 2801x, 2804x Boot ROM reference guide describes the purpose and features of the bootloader
(factory-programmed boot-loading software). It also describes other contents of the device on-chip boot ROM
and identifies where all of the information is located within that memory.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com
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Tools Guides
TMS320C28x Assembly language tools v18.12.0.LTS user's guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x optimizing C/C++ compiler v18.12.0.LTS user's guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
TMS320C28x DSP/BIOS 5.x Application Programming Interface (API) reference guide describes development
using DSP/BIOS.
Application Reports
TMS320x281x to TMS320x2833x or 2823x migration overview describes how to migrate from the 281x device
design to 2833x or 2823x designs.
TMS320x280x to TMS320x2833x or 2823x migration overview describes how to migrate from a 280x device
design to 2833x or 2823x designs.
TMS320C28x FPU primer provides an overview of the floating-point unit (FPU) in the C2000™ Delfino
microcontroller devices.
Running an application from internal flash memory on the TMS320F28xxx DSP covers the requirements needed
to properly configure application software for execution from on-chip flash memory. Requirements for both DSP/
BIOS and non-DSP/BIOS projects are presented. Example code projects are included.
Programming TMS320x28xx and 28xxx peripherals in C/C++ explores a hardware abstraction layer
implementation to make C/C++ coding easier on 28x DSPs. This method is compared to traditional #define
macros and topics of code efficiency and special case registers are also addressed.
Using PWM output as a Digital-to-Analog Converter on a TMS320F280x Digital Signal Controller presents a
method for using the on-chip pulse width modulated (PWM) signal generators on the TMS320F280x family of
digital signal controllers as a digital-to-analog converter (DAC).
TMS320F280x digital signal controller USB connectivity using the TUSB3410 USB-to-UART bridge chip
presents hardware connections as well as software preparation and operation of the development system using
a simple communication echo program.
Using the Enhanced Quadrature Encoder Pulse (eQEP) module in TMS320x280x, 28xxx as a dedicated capture
provides a guide for the use of the eQEP module as a dedicated capture unit and is applicable to the
TMS320x280x, 28xxx family of processors.
Using the ePWM module for 0% - 100% duty cycle control provides a guide for the use of the ePWM module to
provide 0% to 100% duty cycle control and is applicable to the TMS320x280x family of processors.
TMS320x280x and TMS320F2801x ADC calibration describes a method for improving the absolute accuracy of
the 12-bit ADC found on the TMS320x280x and TMS320F2801x devices. Inherent gain and offset errors affect
the absolute accuracy of the ADC. The methods described in this report can improve the absolute accuracy of
the ADC to levels better than 0.5%. This application report has an option to download an example program that
executes from RAM on the F2808 EzDSP.
Online stack overflow detection on the TMS320C28x DSP presents the methodology for online stack overflow
detection on the TMS320C28x DSP. C-source code is provided that contains functions for implementing the
overflow detection on both DSP/BIOS and non-DSP/BIOS applications.
TMS320x281x to TMS320x280x migration overview describes differences between the Texas Instruments
TMS320x281x and the TMS320x280x/2801x/2804x DSPs to assist in application migration.
Semiconductor packing methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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An introduction to IBIS (I/O Buffer Information Specification) modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures and future trends.
Calculating useful lifetimes of embedded processors provides a methodology for calculating the useful lifetime of
TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general engineers
who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
Semiconductor and IC package thermal metrics describes traditional and new thermal metrics and puts their
application in perspective with respect to system-level junction temperature estimation.
Calculating FIT for a mission profile explains how use TI’s reliability de-rating tools to calculate a component
level FIT under power on conditions for a system mission profile.
Serial flash programming of C2000™ microcontrollers discusses using a flash kernel and ROM loaders for serial
programming a device.
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 Trademarks
Code Composer Studio™, MicroStar BGA™, Delfino™, TMS320C2000™, TMS320™, TI E2E™ are trademarks of
Texas Instruments.
eZdsp™ is a trademark of Spectrum Digital.
All trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.8 Glossary
TI Glossary
138
This glossary lists and explains terms, acronyms, and definitions.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
12 Mechanical, Packaging, and Orderable Information
12.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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139
PACKAGE OPTION ADDENDUM
www.ti.com
16-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
TMS320C2801PZA
NRND
LQFP
PZ
100
TBD
Call TI
TMS320C2802PZA
NRND
LQFP
PZ
100
TBD
Call TI
Call TI
TMS320F28015NMFA
ACTIVE
NFBGA
NMF
100
184
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
TMS320
F28015NMFA
TMS320F28015PZA
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
320F28015PZA
TMS
TMS320F28015PZQ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F28015PZQ
TMS
TMS320F28015PZS
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F28015PZS
TMS
TMS320F28015PZSR
ACTIVE
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F28015PZS
TMS
TMS320F28016PZA
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
320F28016PZA
TMS
TMS320F28016PZQ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F28016PZQ
TMS
TMS320F28016PZS
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F28016PZS
TMS
TMS320F2801NMFA
ACTIVE
NFBGA
NMF
100
184
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
TMS320
F2801NMFA
TMS320F2801PZA
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
320F2801PZA
TMS
TMS320F2801PZA-60
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
320F2801PZA-60
TMS
TMS320F2801PZQ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F2801PZQ
TMS
TMS320F2801PZS
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F2801PZS
TMS
TMS320F2801PZS-60
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F2801PZS-60
TMS
TMS320F2802PZA
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
320F2802PZA
TMS
Addendum-Page 1
Call TI
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
16-Dec-2021
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
TMS320F2802PZA-60
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
320F2802PZA-60
TMS
TMS320F2802PZQ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F2802PZQ
TMS
TMS320F2802PZS
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F2802PZS
TMS
TMS320F2802PZS-60
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F2802PZS-60
TMS
TMS320F2806NMFA
ACTIVE
NFBGA
NMF
100
184
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
TMS320
F2806NMFA
TMS320F2806NMFAR
ACTIVE
NFBGA
NMF
100
1000
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
TMS320
F2806NMFA
TMS320F2806NMFS
ACTIVE
NFBGA
NMF
100
184
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 125
TMS320
F2806NMFS
TMS320F2806PZA
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
320F2806PZA
TMS
TMS320F2806PZQ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F2806PZQ
TMS
TMS320F2806PZS
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F2806PZS
TMS
TMS320F2808GBAA
ACTIVE
NFBGA
GBA
100
184
Non-RoHS
& Green
SNPB
Level-3-220C-168 HR
-40 to 85
TMS320
F2808GBAA
TMS320F2808GBAS
ACTIVE
NFBGA
GBA
100
184
Non-RoHS
& Green
SNPB
Level-3-220C-168 HR
-40 to 125
TMS320
F2808GBAS
TMS320F2808NMFA
ACTIVE
NFBGA
NMF
100
184
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
TMS320
F2808NMFA
TMS320F2808NMFS
ACTIVE
NFBGA
NMF
100
184
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 125
TMS320
F2808NMFS
TMS320F2808PZA
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
320F2808PZA
TMS
TMS320F2808PZAR
ACTIVE
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
320F2808PZA
TMS
TMS320F2808PZQ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F2808PZQ
TMS
TMS320F2808PZS
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F2808PZS
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
16-Dec-2021
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMS
TMS320F2809NMFA
ACTIVE
NFBGA
NMF
100
184
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
TMS320
F2809NMFA
TMS320F2809PZA
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
320F2809PZA
TMS
TMS320F2809PZQ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F2809PZQ
TMS
TMS320F2809PZS
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
320F2809PZS
TMS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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