TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
TMS320F2805x Real-Time Microcontrollers
1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High-efficiency 32-bit CPU (TMS320C28x)
– 60 MHz (16.67-ns cycle time)
– 16 × 16 and 32 × 32 Multiply and Accumulate
(MAC) operations
– 16 × 16 dual MAC
– Harvard bus architecture
– Atomic operations
– Fast interrupt response and processing
– Unified memory programming model
– Code-efficient (in C/C++ and Assembly)
Programmable Control Law Accelerator (CLA)
– 32-bit floating-point math accelerator
– Executes code independently of the main CPU
Dual-zone security module
Endianness: Little endian
Low device and system cost:
– Single 3.3-V supply
– No power sequencing requirement
– Integrated power-on reset and brownout reset
– Low power
– No analog support pins
Clocking:
– Two internal zero-pin oscillators
– On-chip crystal oscillator and external clock
input
– Watchdog timer module
– Missing clock detection circuitry
Up to 42 individually programmable, multiplexed
General-Purpose Input/Output (GPIO) pins with
input filtering
JTAG boundary scan support
– IEEE Standard 1149.1-1990 Standard Test
Access Port and Boundary Scan Architecture
Peripheral Interrupt Expansion (PIE) block that
supports all peripheral interrupts
Three 32-bit CPU timers
Independent 16-bit timer in each ePWM module
On-chip memory
– Flash, SARAM, Message RAM, OTP, CLA Data
ROM, Boot ROM, Secure ROM available
128-bit security key and lock
– Protects secure memory blocks
– Prevents firmware reverse-engineering
Serial port peripherals
– Three Serial Communications Interface (SCI)
(Universal Asynchronous Receiver/Transmitter
[UART]) modules
– One Serial Peripheral Interface (SPI) module
– One Inter-Integrated-Circuit (I2C) bus
•
•
•
•
•
– One Enhanced Controller Area Network
(eCAN) bus
Enhanced control peripherals
– Enhanced Pulse Width Modulator (ePWM)
– Enhanced Capture (eCAP) module
– Enhanced Quadrature Encoder Pulse (eQEP)
module
Analog peripherals
– One 12-bit Analog-to-Digital Converter (ADC)
– One on-chip temperature sensor for oscillator
compensation
– Up to seven comparators with up to three
integrated Digital-to-Analog Converters (DACs)
– One buffered reference DAC
– Up to four Programmable Gain Amplifiers
(PGAs)
– Up to four digital filters
Advanced debug features
– Analysis and breakpoint functions
– Real-time debug through hardware
80-pin PN Low-Profile Quad Flatpack (LQFP)
Temperature options
– T: –40°C to 105°C
– S: –40°C to 125°C
– Q: –40°C to 125°C
(AEC Q100 qualification for automotive
applications)
2 Applications
•
•
•
•
•
•
Air conditioner outdoor unit
Door operator drive control
Inverter & motor control
AC drive control module
AC-input BLDC motor drive
DC-input BLDC motor drive
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
3 Description
C2000™ real-time control MCUs are optimized for processing, sensing, and actuation to improve closed-loop
performance in real-time control applications such as industrial motor drives; solar inverters and digital power;
electrical vehicles and transportation; motor control; and sensing and signal processing. The C2000 line includes
the Premium performance MCUs and the Entry performance MCUs.
The F2805x family of microcontrollers (MCUs) provides the power of the C28x core and CLA coupled with highly
integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based
code, and also provides a high level of analog integration.
An internal voltage regulator allows for single-rail operation. Analog comparators with internal 6-bit references
have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed
full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for
low overhead and latency.
The Analog Front End (AFE) contains up to seven comparators with up to three integrated DACs, one VREFOUTbuffered DAC, up to four PGAs, and up to four digital filters. The PGAs can amplify the input signal in three
discrete gain modes. The actual number of AFE peripherals will depend upon the TMS320F2805x device
number. See Device Comparison for more details.
To learn more about the C2000 MCUs, visit the C2000™ real-time control MCUs page.
Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE
TMS320F28055PN
LQFP (80)
12.0 mm × 12.0 mm
TMS320F28054PN
LQFP (80)
12.0 mm × 12.0 mm
TMS320F28053PN
LQFP (80)
12.0 mm × 12.0 mm
TMS320F28052PN
LQFP (80)
12.0 mm × 12.0 mm
TMS320F28051PN
LQFP (80)
12.0 mm × 12.0 mm
TMS320F28050PN
LQFP (80)
12.0 mm × 12.0 mm
(1)
2
For more information on these devices, see Mechanical, Packaging, and Orderable Information.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
www.ti.com
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
3.1 Functional Block Diagram
A.
B.
Stores Secure Copy Code Functions on all devices.
Not all peripheral pins are available at the same time due to multiplexing.
Figure 3-1. Functional Block Diagram
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
3
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................2
3.1 Functional Block Diagram........................................... 3
4 Revision History.............................................................. 4
5 Device Comparison......................................................... 5
5.1 Related Products........................................................ 6
6 Terminal Configuration and Functions..........................7
6.1 Pin Diagram................................................................ 7
6.2 Signal Descriptions..................................................... 8
7 Specifications................................................................ 16
7.1 Absolute Maximum Ratings...................................... 16
7.2 ESD Ratings – Commercial...................................... 16
7.3 ESD Ratings – Automotive....................................... 16
7.4 Recommended Operating Conditions.......................17
7.5 Power Consumption Summary................................. 18
7.6 Electrical Characteristics...........................................21
7.7 Thermal Resistance Characteristics for PN
Package...................................................................... 22
7.8 Thermal Design Considerations................................22
7.9 JTAG Debug Probe Connection Without Signal
Buffering for the MCU..................................................23
7.10 Parameter Information............................................ 24
7.11 Test Load Circuit..................................................... 24
7.12 Power Sequencing..................................................25
7.13 Clock Specifications................................................28
7.14 Flash Timing............................................................31
8 Detailed Description......................................................34
8.1 Overview................................................................... 34
8.2 Memory Maps........................................................... 45
8.3 Register Map.............................................................52
8.4 Device Emulation Registers......................................54
8.5 VREG, BOR, POR.................................................... 57
8.6 System Control......................................................... 59
8.7 Low-power Modes Block...........................................67
8.8 Interrupts...................................................................68
8.9 Peripherals................................................................73
9 Applications, Implementation, and Layout............... 140
9.1 TI Reference Design............................................... 140
10 Device and Documentation Support........................141
10.1 Getting Started......................................................141
10.2 Device and Development Support Tool
Nomenclature............................................................ 141
10.3 Tools and Software............................................... 142
10.4 Documentation Support........................................ 144
10.5 Support Resources............................................... 145
10.6 Trademarks........................................................... 145
10.7 Electrostatic Discharge Caution............................145
10.8 Glossary................................................................145
11 Mechanical, Packaging, and Orderable
Information.................................................................. 146
11.1 Packaging Information.......................................... 146
4 Revision History
Changes from February 2, 2021 to September 13, 2021 (from Revision E (February 2021) to
Revision F (September 2021))
Page
• Table 5-1, Device Comparison: Changed "SCI" to "SCI/UART". Updated footnote about TMS320F2805xM
and TMS320F2805xF. Added device numbers in Temperature options section. ...............................................5
• Section 6.2.1, Signal Descriptions: Updated DESCRIPTION of VREGENZ...................................................... 8
• Section 7.2, ESD Ratings – Commercial: Updated device numbers................................................................ 16
• Section 7.3, ESD Ratings – Automotive: Updated device numbers................................................................. 16
• Section 7.13.1.3, Internal Zero-Pin Oscillator (INTOSC1, INTOSC2) Characteristics: Updated footnote about
oscillator frequency........................................................................................................................................... 29
• Section 8.1.10, Security: Updated section........................................................................................................37
• Figure 8-1, 28055 and 28054 Memory Map: Changed “Secure Zone + ECSL” to “Secure Zone”................... 45
• Figure 8-2, 28053 and 28052 Memory Map: Changed “Secure Zone + ECSL” to “Secure Zone”................... 45
• Figure 8-3, 28051 Memory Map: Changed “Secure Zone + ECSL” to “Secure Zone”..................................... 45
• Figure 8-4, 28050 Memory Map: Changed “Secure Zone + ECSL” to “Secure Zone”..................................... 45
• Section 10.1, Getting Started: Updated reference page link.......................................................................... 141
• Section 10.3, Tools and Software: Updated section....................................................................................... 142
4
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
5 Device Comparison
Table 5-1 lists the features of the TMS320F2805x devices.
Table 5-1. Device Comparison
FEATURE
Package type
Instruction cycle
28055
(60 MHz)
28054
28054-Q1
28054M (1)
28054M-Q1
28054F (1)
28054F-Q1
(60 MHz)
28053
(60 MHz)
28052
28052-Q1
28052M (1)
28052M-Q1
28052F (1)
28052F-Q1
(60 MHz)
28051
(60 MHz)
28050
(60 MHz)
80-pin PN
LQFP
80-pin PN
LQFP
80-pin PN
LQFP
80-pin PN
LQFP
80-pin PN
LQFP
80-pin PN
LQFP
16.67 ns
16.67 ns
16.67 ns
16.67 ns
16.67 ns
16.67 ns
CLA
Yes
No
Yes
No
No
No
On-chip flash (16-bit word)
64K
64K
32K
32K
32K
16K
On-chip SARAM (16-bit word)
10K
10K (28054)
8K (28054M)
8K (28054F)
10K
10K (28052)
8K (28052M)
8K (28052F)
8K
6K
Dual-zone security for on-chip flash,
SARAM, OTP, and secure ROM
blocks
Yes
Yes
Yes
Yes
Yes
Yes
Boot ROM (12K × 16)
Yes
Yes
Yes
Yes
Yes
Yes
One-time programmable (OTP) ROM
(16-bit word)
1K
1K
1K
1K
1K
1K
ePWM channels
14
14
14
14
14
14
eCAP inputs
1
1
1
1
1
1
eQEP modules
1
1
1
1
1
1
Yes
Watchdog timer
Yes
Yes
Yes
Yes
Yes
3.75
3.75
3.75
3.75
2
2
267 ns
267 ns
267 ns
267 ns
500 ns
500 ns
Channels
16
16
16
16
16
16
Temperature
sensor
Yes
Yes
Yes
Yes
Yes
Yes
Dual
sample-and-hold
Yes
Yes
Yes
Yes
Yes
Yes
PGA (Gain ≈ 3, 6, or 11)
4
4
4
4
4
3
Fixed Gain Amplifier (Gain ≈ 3)
3
3
3
3
3
4
Comparators
7
7
7
7
7
6
Internal comparator reference DACs
3
3
3
3
3
2
Buffered reference DAC
1
1
1
1
1
1
32-Bit CPU timers
3
3
3
3
3
3
I2C
1
1
1
1
1
1
eCAN
1
1
1
1
1
1
SPI
1
1
1
1
1
1
SCI/UART
3
3
3
3
3
3
0-pin oscillators
2
2
2
2
2
2
42
42
42
42
42
42
MSPS
Conversion time
12-Bit ADC
I/O pins (shared)
GPIO
External interrupts
Supply voltage (nominal)
3
3
3
3
3
3
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
5
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Table 5-1. Device Comparison (continued)
28055
(60 MHz)
28054
28054-Q1
28054M (1)
28054M-Q1
28054F (1)
28054F-Q1
(60 MHz)
T: –40°C to 105°C
28055
S: –40°C to 125°C
FEATURE
Temperature
options
Q: –40°C to
125°C(2)
(1)
(2)
28053
(60 MHz)
28052
28052-Q1
28052M (1)
28052M-Q1
28052F (1)
28052F-Q1
(60 MHz)
28051
(60 MHz)
28050
(60 MHz)
28054
28054M
28054F
28053
28052
28052M
28052F
28051
28050
28055
28054 only
28053
28052 only
28051
28050
–
28054-Q1
28054M-Q1
28054F-Q1
–
28052-Q1
28052M-Q1
28052F-Q1
–
–
TMS320F2805xF devices are InstaSPIN-FOC-enabled MCUs. TMS320F2805xM devices are InstaSPIN-MOTION-enabled MCUs.
However, InstaSPIN-MOTION is no longer recommended for new designs and will not have application support. On these devices, TI
has secured Zone1 and allocated RAML0 to Zone1. Because of this, Zone1 and RAML0 are not available for customer applications;
only Zone2 is available. For more information, see Section 10.4 for a list of InstaSPIN Technical Reference Manuals.
The letter Q refers to AEC Q100 qualification for automotive applications.
5.1 Related Products
For information about similar products, see the following links:
TMS320F2802x Real-Time Microcontrollers
The F2802x series offers the lowest pin-count and Flash memory size options. InstaSPIN-FOC™ versions are
available.
TMS320F2803x Real-Time Microcontrollers
The F2803x series increases the pin-count and memory size options. The F2803x series also introduces the
parallel control law accelerator (CLA) option.
TMS320F2805x Real-Time Microcontrollers
The F2805x series is similar to the F2803x series but adds on-chip programmable gain amplifiers (PGAs).
InstaSPIN-FOC and InstaSPIN-MOTION™ versions are available.
TMS320F2806x Real-Time Microcontrollers
The F2806x series is the first to include a floating-point unit (FPU). The F2806x series also increases the
pin-count, memory size options, and the quantity of peripherals. InstaSPIN-FOC™ and InstaSPIN-MOTION™
versions are available.
TMS320F2807x Real-Time Microcontrollers
The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral options.
The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog technology.
TMS320F28004x Real-Time Microcontrollers
The F28004x series is a reduced version of the F2807x series with the latest generational enhancements.
InstaSPIN-FOC and configurable logic block (CLB) versions are available.
6
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
6 Terminal Configuration and Functions
6.1 Pin Diagram
GPIO18/SPICLKA/SCITXDB/XCLKOUT
GPIO28/SCIRXDA/SDAA/TZ2
GPIO29/SCITXDA/SCLA/TZ3/CTRIPPFCOUT
42
41
GPIO17/SPISOMIA/EQEP1I/TZ3/CTRIPPFCOUT
44
43
GPIO25
GPIO8/EPWM5A/ADCSOCAO
46
47
45
GPIO12/TZ1/CTRIPM1OUT/SCITXDA
GPIO16/SPISIMOA/EQEP1S/TZ2
48
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
GPIO7/EPWM4B/SCIRXDA
50
49
X1
X2
VSS
51
VDD
54
53
52
GPIO39/SCIRXDC/CTRIPPFCOUT
GPIO19/XCLKIN/SPISTEA/SCIRXDB/ECAP1
56
57
55
GPIO37/TDO
GPIO38/TCK/XCLKIN
58
GPIO36/TMS
GPIO35/TDI
60
59
Figure 6-1 shows the 80-pin PN Low-Profile Quad Flatpack pin assignments.
GPIO15/TZ1/CTRIPM1OUT/SCIRXDB
75
26
ADCINB4 (op-amp)
GPIO13/TZ2
76
25
ADCINB3
GPIO14/TZ3/CTRIPPFCOUT/SCITXDB
77
24
ADCINA7
GPIO20/EQEP1A/EPWM7A/CTRIPM1OUT
78
23
ADCINA6 (op-amp)
GPIO21/EQEP1B/EPWM7B
79
22
VREFLO
GPIO23/EQEP1I/SCIRXDB
80
21
VSSA
20
M2GND
VDDA
27
19
74
VREFHI
ADCINB5
GPIO34/CTRIPPFCOUT
17
28
18
73
ADCINB1 (op-amp)
ADCINB6 (op-amp)
VDD
ADCINA0/VREFOUT
29
15
72
16
ADCINB0
VSS
M1GND
30
ADCINB2
71
13
ADCINB7 (op-amp)
VREGENZ
14
31
ADCINA2
70
ADCINA1 (op-amp)
PFCGND
VDDIO
11
32
12
69
ADCINA4
GPIO27/SCITXDC
GPIO0/EPWM1A
ADCINA3 (op-amp)
33
10
68
ADCINA5
GPIO31/CANTXA/SCITXDB/EPWM7B
GPIO1/EPWM1B/CTRIPM1OUT
9
GPIO30/CANRXA/SCIRXDB/EPWM7A
34
TRST
35
67
7
66
GPIO2/EPWM2A
8
GPIO3/EPWM2B/SPISOMIA
VSS
GPIO9/EPWM5B/SCITXDB
XRS
36
5
65
6
VSS
GPIO10/EPWM6A/ADCSOCBO
VDD
37
GPIO42/EPWM7B/SCITXDC/CTRIPM1OUT
64
3
VDDIO
GPIO40/EPWM7A
4
38
GPIO24/ECAP1/EPWM7A
63
GPIO33/SCLA/EPWMSYNCO/EQEP1I
TEST2
GPIO4/EPWM3A
1
GPIO26/SCIRXDC
39
2
40
62
GPIO22/EQEP1S/SCITXDB
61
GPIO32/SDAA/EPWMSYNCI/EQEP1S
GPIO11/EPWM6B/SCIRXDB
GPIO5/EPWM3B/SPISIMOA/ECAP1
Figure 6-1. 2805x 80-Pin PN Low-Profile Quad Flatpack (Top View)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
7
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
6.2 Signal Descriptions
Section 6.2.1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at
reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions.
Some peripheral functions may not be available in all devices. See Table 5-1 for details. Inputs are not 5-V
tolerant. All GPIO pins are I/O/Z and have an internal pullup (PU), which can be selectively enabled or disabled
on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pins are not enabled at
reset, except as noted in Section 6.2.1. The pullups on other GPIO pins are enabled upon reset.
Note
When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38 pins
could glitch during power up. This potential glitch will finish before the boot mode pins are read and
will not affect boot behavior. If glitching is unacceptable in an application, 1.8 V could be supplied
externally. Alternatively, adding a current-limiting resistor (for example, 470 Ω) in series with these pins
and any external driver could be considered to limit the potential for degradation to the pin and/or
external circuitry. There is no power-sequencing requirement when using an external 1.8-V supply.
However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered prior to
the 1.8-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin
during power up. To avoid this behavior, power the VDD pins prior to or simultaneously with the VDDIO
pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V.
6.2.1 Signal Descriptions
TERMINAL
NAME
PN
PIN NO.
I/O/Z(1)
DESCRIPTION
JTAG
9
I
JTAG test reset with internal pulldown (PD). TRST, when driven high, gives the scan system
control of the operations of the device. If this signal is not connected or driven low, the device
operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an
active high test pin and must be maintained low at all times during normal device operation. An
external pulldown resistor is required on this pin. The value of this resistor should be based on
drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers
adequate protection. Because the value of the resistor is application-specific, TI recommends
that each target board be validated for proper operation of the debugger and the application.
(↓)
TCK
See
GPIO38
I
See GPIO38. JTAG test clock with internal pullup. (↑)
TMS
See
GPIO36
I
See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is
clocked into the TAP controller on the rising edge of TCK.. (↑)
TDI
See
GPIO35
I
See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK. (↑)
TDO
See
GPIO37
O/Z
See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected register
(instruction or data) are shifted out of TDO on the falling edge of TCK. (8 mA drive)
39
I/O
Test Pin. Reserved for TI. Must be left unconnected.
TRST
FLASH
TEST2
8
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
TERMINAL
NAME
PN
PIN NO.
I/O/Z(1)
DESCRIPTION
CLOCK
XCLKOUT
See
GPIO18
O/Z
See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same
frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. The value of
XCLKOUT is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT
= SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The
mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.
See
GPIO19
and
GPIO38
I
See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by the
XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a clock
from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to GND
and the on-chip crystal oscillator must be disabled through bit 14 in the CLKCTL register. If a
crystal/resonator is used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register.
NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock for normal
device operation may need to incorporate some hooks to disable this path during debug using
the JTAG connector. This action is to prevent contention with the TCK signal, which is active
during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to
clock the device.
X1
52
I
On-chip 1.8-V crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic
resonator must be connected across X1 and X2. In this case, the XCLKIN path must be
disabled by bit 13 in the CLKCTL register. If this pin is not used, this pin must be tied to GND.
(I)
X2
51
O
On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected
across X1 and X2. If X2 is not used, X2 must be left unconnected. (O)
XCLKIN
RESET
XRS
8
I/OD
Copyright © 2022 Texas Instruments Incorporated
Device Reset (in) and Watchdog Reset (out). These devices have a built-in power-on reset
(POR) and brownout reset (BOR) circuitry. During a power-on or brownout condition, this pin
is driven low by the device. An external circuit may also drive this pin to assert a device reset.
This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset,
the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor
with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is
placed between XRS and VSS for noise filtering, it should be 100 nF or smaller. These values
will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when
the watchdog reset is asserted. Regardless of the source, a device reset causes the device
to terminate execution. The program counter points to the address contained at the location
0x3F FFC0. When reset is deactivated, execution begins at the location designated by the
program counter. The output buffer of this pin is an open-drain with an internal pullup. (↑) If this
pin is driven by an external device, it should be done using an open-drain device.
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
9
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
TERMINAL
NAME
PN
PIN NO.
I/O/Z(1)
DESCRIPTION
ADC, COMPARATOR, ANALOG I/O
ADCINA7
24
I
ADC Group A, Channel 7 input
ADCINA6
(op-amp)
23
I
ADC Group A, Channel 6 input
ADCINA5
10
I
ADC Group A, Channel 5 input
ADCINA4
11
I
ADC Group A, Channel 4 input
ADCINA3
(op-amp)
12
I
ADC Group A, Channel 3 input
ADCINA2
13
I
ADC Group A, Channel 2 input
ADCINA1
(op-amp)
14
I
ADC Group A, Channel 1 input
18
I
VREFHI
19
I
ADC External Reference – used when in ADC external reference mode and used as VREFOUT
reference
ADCINB7
(op-amp)
31
I
ADC Group B, Channel 7 input
ADCINB6
(op-amp)
29
I
ADC Group B, Channel 6 input
ADCINB5
28
I
ADC Group B, Channel 5 input
ADCINB4
(op-amp)
26
I
ADC Group B, Channel 4 input
ADCINB3
25
I
ADC Group B, Channel 3 input
ADCINB2
16
I
ADC Group B, Channel 2 input
ADCINB1
(op-amp)
17
I
ADC Group B, Channel 1 input
ADCINB0
30
I
ADC Group B, Channel 0 input
VREFLO
22
I
ADC Low Reference (always tied to ground)
ADCINA0
VREFOUT
ADC Group A, Channel 0 input
Voltage Reference out from buffered DAC
CPU AND I/O POWER
VDDA
20
Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin.
VSSA
21
Analog Ground Pin
VDD
54
6
73
38
VDDIO
70
CPU and Logic Digital Power Pins. When using internal VREG, place one 1.2-µF capacitor
between each VDD pin and ground. Higher value capacitors may be used.
Digital I/O Buffers and Flash Memory Power Pin. Single supply source when VREG is enabled.
Place a decoupling capacitor on each pin. The exact value should be determined by the
system voltage regulation solution.
7
37
VSS
53
Digital Ground Pins
72
M1GND
15
Ground pin for amplifier (channels A1, A3, B1)
M2GND
27
Ground pin for amplifier (channels A6, B4, B6)
PFCGND
32
Ground pin for amplifier (channel B7)
10
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
TERMINAL
NAME
PN
PIN NO.
I/O/Z(1)
DESCRIPTION
VOLTAGE REGULATOR CONTROL SIGNAL
VREGENZ
71
I
Internal voltage regulator (VREG) enable with internal pulldown. Tie directly to VSS (low) to
enable the internal 1.8-V VREG. Tie directly to VDDIO (high) to disable the VREG and use an
external 1.8-V supply.
GPIO AND PERIPHERAL SIGNALS (2)
GPIO0
EPWM1A
Reserved
I/O/Z
69
Reserved
GPIO1
EPWM1B
Reserved
CTRIPM1OUT
GPIO2
EPWM2A
Reserved
67
GPIO3
SPISOMIA
66
63
GPIO5
SPISIMOA
Reserved
Enhanced PWM1 Output B
–
Reserved
O
CTRIPM1 CTRIPxx output
General-purpose input/output 2
O
Enhanced PWM2 Output A
–
Reserved
–
Reserved
General-purpose input/output 3
O
Enhanced PWM2 Output B
I/O
SPI-A slave out, master in
Reserved
General-purpose input/output 4
O
Enhanced PWM3 output A
–
Reserved
–
Reserved
I/O/Z
62
General-purpose input/output 1
O
I/O/Z
Reserved
EPWM3B
–
–
GPIO4
Reserved
Reserved
I/O/Z
Reserved
EPWM3A
Enhanced PWM1 Output A
–
I/O/Z
Reserved
EPWM2B
O
I/O/Z
68
General-purpose input/output 0
General-purpose input/output 5
O
Enhanced PWM3 output B
I/O
SPI-A slave in, master out
ECAP1
I/O
Enhanced Capture input/output 1
GPIO6
I/O/Z
EPWM4A
EPWMSYNCI
50
EPWMSYNCO
GPIO7
EPWM4B
SCIRXDA
Reserved
GPIO8
EPWM5A
Reserved
45
GPIO9
SCITXDB
Reserved
External ePWM sync pulse input
O
External ePWM sync pulse output
Enhanced PWM4 output B
I
SCI-A receive data
–
Reserved
General-purpose input/output 8
O
Enhanced PWM5 output A
–
Reserved
O
ADC start-of-conversion A
I/O/Z
36
General-purpose input/output 7
O
I/O/Z
ADCSOCAO
EPWM5B
Enhanced PWM4 output A
I
I/O/Z
49
General-purpose input/output 6
O
General-purpose input/output 9
O
Enhanced PWM5 output B
O
SCI-B transmit data
–
Reserved
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
11
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
TERMINAL
PN
PIN NO.
NAME
I/O/Z(1)
GPIO10
I/O/Z
EPWM6A
65
Reserved
ADCSOCBO
GPIO11
61
SCIRXDB
Reserved
GPIO12
Enhanced PWM6 output A
–
Reserved
O
ADC start-of-conversion B
General-purpose input/output 11
O
Enhanced PWM6 output B
I
SCI-B receive data
–
Reserved
I/O/Z
TZ1
General-purpose input/output 10
O
I/O/Z
EPWM6B
DESCRIPTION
General-purpose input/output 12
I
Trip Zone input 1
O
CTRIPM1 CTRIPxx output
SCITXDA
O
SCI-A transmit data
Reserved
–
Reserved
CTRIPM1OUT
48
GPIO13
I/O/Z
TZ2
76
Reserved
Reserved
GPIO14
Trip zone input 2
–
Reserved
–
Reserved
I/O/Z
TZ3
General-purpose input/output 13
I
General-purpose input/output 14
I
Trip zone input 3
O
CTRIPPFC output
SCITXDB
O
SCI-B transmit data
Reserved
–
Reserved
CTRIPPFCOUT
77
GPIO15
I/O/Z
TZ1
General-purpose input/output 15
I
Trip zone input 1
O
CTRIPM1 CTRIPxx output
SCIRXDB
I
SCI-B receive data
Reserved
–
Reserved
CTRIPM1OUT
75
GPIO16
I/O/Z
SPISIMOA
47
EQEP1S
TZ2
SPI-A slave in, master out
I/O
Enhanced QEP1 strobe
I
GPIO17
I/O/Z
SPISOMIA
44
EQEP1I
TZ3
CTRIPPFCOUT
GPIO18
General-purpose input/output 16
I/O
Trip Zone input 2
General-purpose input/output 17
I/O
SPI-A slave out, master in
I/O
Enhanced QEP1 index
I
Trip zone input 3
O
CTRIPPFC output
I/O/Z
General-purpose input/output 18
SPICLKA
I/O
SPI-A clock input/output
SCITXDB
O
SCI-B transmit data
XCLKOUT
12
43
Submit Document Feedback
O/Z
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, or one-fourth the frequency of SYSCLKOUT. The value of XCLKOUT is controlled
by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The
XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18
must also be set to XCLKOUT for this signal to propogate to the pin.
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
TERMINAL
NAME
PN
PIN NO.
I/O/Z(1)
GPIO19
I/O/Z
XCLKIN
I
55
SPISTEA
I/O
SCIRXDB
I
DESCRIPTION
General-purpose input/output 19
External Oscillator Input. The path from this pin to the clock block is not gated by the mux
function of this pin. Care must be taken not to enable this path for clocking if this path is being
used for the other periperhal functions
SPI-A slave transmit enable input/output
SCI-B receive data
ECAP1
I/O
GPIO20
I/O/Z
EQEP1A
I
Enhanced QEP1 input A
O
Enhanced PWM7 output A
O
CTRIPM1 CTRIPxx output
EPWM7A
78
CTRIPM1OUT
Enhanced Capture input/output 1
General-purpose input/output 20. Internal pullup enabled by default.
GPIO21
I/O/Z
EQEP1B
I
Enhanced QEP1 input B
O
Enhanced PWM7 output B
–
Reserved
EPWM7B
79
Reserved
GPIO22
EQEP1S
Reserved
I/O/Z
1
SCITXDB
GPIO23
EQEP1I
Reserved
I/O
SCIRXDB
General-purpose input/output 22
Enhanced QEP1 strobe
–
Reserved
O
SCI-B transmit data
I/O/Z
80
General-purpose input/output 21. Internal pullup enabled by default.
I/O
General-purpose input/output 23
Enhanced QEP1 index
–
Reserved
I
SCI-B receive data
GPIO24
I/O/Z
ECAP1
I/O
Enhanced Capture input/output 1
O
Enhanced PWM7 output A
–
Reserved
EPWM7A
4
Reserved
GPIO25
Reserved
Reserved
I/O/Z
46
Reserved
GPIO26
Reserved
SCIRXDC
Reserved
GPIO27
Reserved
SCITXDC
Reserved
GPIO28
SCIRXDA
SDAA
TZ2
Reserved
–
Reserved
–
Reserved
Reserved
I
SCI-C receive data
–
Reserved
General-purpose input/output 27
–
Reserved
O
SCI-C transmit data
–
Reserved
I/O/Z
42
General-purpose input/output 26
–
I/O/Z
33
General-purpose input/output 25
–
I/O/Z
40
General-purpose input/output 24. Internal pullup enabled by default.
I
I/OD
I
Copyright © 2022 Texas Instruments Incorporated
General-purpose input/output 28
SCI-A receive data
I2C data open-drain bidirectional port
Trip zone input 2
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
13
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
TERMINAL
PN
PIN NO.
NAME
I/O/Z(1)
GPIO29
I/O/Z
SCITXDA
O
SCLA
41
TZ3
CTRIPPFCOUT
GPIO30
I/OD
35
SCIRXDB
EPWM7A
General-purpose input/output 29
SCI-A transmit data
I2C clock open-drain bidirectional port
I
Trip zone input 3
O
CTRIPPFC output
I/O/Z
CANRXA
DESCRIPTION
General-purpose input/output 30. Internal pullup enabled by default.
I
CAN receive
I
SCI-B receive data
O
Enhanced PWM7 output A
GPIO31
I/O/Z
CANTXA
O
CAN transmit
O
SCI-B transmit data
O
Enhanced PWM7 output B
34
SCITXDB
EPWM7B
General-purpose input/output 31. Internal pullup enabled by default.
GPIO32
I/O/Z
General-purpose input/output 32
SDAA
I/OD
I2C data open-drain bidirectional port
2
EPWMSYNCI
I
Enhanced PWM external sync pulse input
EQEP1S
I/O
GPIO33
I/O/Z
General-Purpose Input/Output 33
I/OD
I2C clock open-drain bidirectional port
SCLA
3
EPWMSYNCO
Enhanced QEP1 strobe
O
Enhanced PWM external synch pulse output
EQEP1I
I/O
Enhanced QEP1 index
GPIO34
I/O/Z
Reserved
74
Reserved
CTRIPPFCOUT
GPIO35
Reserved
Reserved
–
Reserved
O
CTRIPPFC output
I/O/Z
TDI
59
Reserved
Reserved
GPIO36
General-Purpose Input/Output 35
I
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK
–
Reserved
–
Reserved
–
Reserved
I/O/Z
TMS
General-Purpose Input/Output 34
–
General-Purpose Input/Output 36
I
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the
TAP controller on the rising edge of TCK.
–
Reserved
Reserved
–
Reserved
Reserved
–
Reserved
Reserved
60
GPIO37
I/O/Z
General-Purpose Input/Output 37
TDO
O/Z
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or
data) are shifted out of TDO on the falling edge of TCK (8 mA drive)
Reserved
58
–
Reserved
Reserved
–
Reserved
Reserved
–
Reserved
14
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
TERMINAL
PN
PIN NO.
NAME
GPIO38
I/O/Z(1)
I/O/Z
57
General-Purpose Input/Output 38
I
External Oscillator Input. The path from this pin to the clock block is not gated by the mux
function of this pin. Care must be taken to not enable this path for clocking if this path is being
used for the other functions.
XCLKIN
TCK
DESCRIPTION
I
JTAG test clock with internal pullup
Reserved
–
Reserved
Reserved
–
Reserved
Reserved
–
Reserved
GPIO39
I/O/Z
Reserved
56
SCIRXDC
CTRIPPFCOUT
GPIO40
EPWM7A
Reserved
Reserved
GPIO42
EPWM7B
SCITXDC
CTRIPM1OUT
(1)
(2)
–
Reserved
I
SCI-C receive data
O
CTRIPPFC output
I/O/Z
64
General-Purpose Input/Output 40. Internal pullup enabled by default.
O
Enhanced PWM7 output A
–
Reserved
–
Reserved
I/O/Z
5
General-Purpose Input/Output 39
General-Purpose Input/Output 42. Internal pullup enabled by default.
O
Enhanced PWM7 output B
O
SCI-C transmit data
O
CTRIPM1 CTRIPxx output
I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown
The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate
functions. For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output
path from the GPIO block and the path to the JTAG block from a pin is enabled or disabled based on the condition of the TRST signal.
For details, see the System Control and Interrupts chapter of the TMS320x2805x Real-Time Microcontrollers Technical Reference
Manual.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
15
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
7 Specifications
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those indicated under the Recommended Operating Conditions is not implied. Exposure to absolute-maximumrated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS,
unless otherwise noted.
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VDDIO (I/O and flash) with respect to VSS
–0.3
4.6
VDD with respect to VSS
–0.3
2.5
VDDA with respect to VSSA
–0.3
4.6
VIN (3.3 V)
–0.3
4.6
VIN (X1)
–0.3
2.5
VO
–0.3
4.6
Digital input (per pin), IIK (VIN < VSS or VIN > VDDIO)(1)
–20
20
Analog input (per pin), IIKANALOG
(VIN < VSSA or VIN > VDDA)
–20
20
Total for all inputs, IIKTOTAL
(VIN < VSS/VSSA or VIN > VDDIO/VDDA)
–20
20
Output clamp current
IOK (VO < 0 or VO > VDDIO)
–20
20
mA
Junction temperature(2)
TJ
–40
150
°C
Tstg
–65
150
°C
Supply voltage
Analog voltage
Input voltage
Output voltage
Input clamp current
Storage
(1)
(2)
temperature(2)
UNIT
V
V
V
V
mA
Continuous clamp current per pin is ±2 mA.
Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see the Semiconductor and IC Package Thermal Metrics Application Report.
7.2 ESD Ratings – Commercial
VALUE
UNIT
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053, TMS320F28052, TMS320F28052M,
TMS320F28052F, TMS320F28051, TMS320F28050 in 80-pin PN package
V(ESD)
(1)
(2)
Electrostatic discharge (ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 or ANSI/ESDA/JEDEC JS-002(2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 ESD Ratings – Automotive
VALUE
UNIT
TMS320F28054-Q1, TMS320F28054M-Q1, TMS320F28054F-Q1, TMS320F28052-Q1, TMS320F28052M-Q1, TMS320F28052F-Q1
in 80-pin PN package
Human body model (HBM), per
AEC Q100-002(1)
V(ESD)
(1)
16
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
All pins
±2000
All pins
±500
Corner pins on 80-pin PN:
1, 20, 21, 40, 41, 60, 61, 80
±750
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
7.4 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Device supply voltage, I/O, VDDIO
2.97
3.3
3.63
V
Device supply voltage CPU, VDD (When internal VREG is
disabled and 1.8 V is supplied externally)
1.71
1.8
1.995
V
Supply ground, VSS
0
Analog supply voltage, VDDA
2.97
Analog ground, VSSA
V
3.3
3.63
0
V
V
Device clock frequency (system clock)
2
60
High-level input voltage, VIH (3.3 V)
2
VDDIO + 0.3
V
VSS – 0.3
0.8
V
Low-level input voltage, VIL (3.3 V)
High-level output source current, VOH = VOH(MIN) , IOH
Low-level output sink current, VOL = VOL(MAX), IOL
Junction temperature, TJ
(1)
All GPIO pins
–4
Group 2(1)
–8
All GPIO pins
Group
4
2(1)
8
T version
–40
105
S version
–40
125
Q version
(AEC Q100 qualification)
–40
125
MHz
mA
mA
°C
Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO28, GPIO29, GPIO30, GPIO31, GPIO36, GPIO37
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
17
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
7.5 Power Consumption Summary
Section 7.5.1 lists the current consumption at 60-MHz SYSCLKOUT.
7.5.1 TMS320F2805x Current Consumption at 60-MHz SYSCLKOUT
VREG ENABLED
MODE
TEST CONDITIONS
IDDIO (1)
TYP(3)
VREG DISABLED
IDDA (2)
MAX
TYP(3)
95 mA(7)
132 mA
14 mA
IDDIO (1)
IDD
MAX
TYP(3)
40 mA
60 mA
27 mA
15 μA
15 mA
IDDA (2)
MAX
TYP(3)
MAX
TYP(3)
MAX
85 mA(7)
110 mA
14 mA
25 mA
40 mA
60 mA
25 μA
14 mA
27 mA
120 μA
450 μA
15 μA
25 μA
15 μA
25 μA
9 mA
15 mA
120 μA
450 μA
15 μA
25 μA
15 μA
25 μA
50 μA
15 μA
25 μA
The following peripheral clocks are
enabled:
•
ePWM1, ePWM2, ePWM3,
ePWM4, ePWM5, ePWM6,
ePWM7
Operational
(flash)
•
eCAP1
•
eQEP1
•
eCAN-A
•
CLA
•
SCI-A, SCI-B, SCI-C
•
SPI-A
•
ADC
•
I2C-A
•
COMPA1, COMPA3,
COMPB1, COMPB7
•
CPU-Timer 0,
CPU-Timer 1,
CPU-Timer 2
All PWM pins are toggled at 60 kHz.
All I/O pins are left unconnected.(4)
(6)
Code is running out of flash with
2 wait-states.
XCLKOUT is turned off.
IDLE
Flash is powered down.
XCLKOUT is turned off.
All peripheral clocks are turned off.
STANDBY
Flash is powered down.
Peripheral clocks are off.
9 mA
HALT
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.(5)
300 μA
(1)
(2)
(3)
(4)
(5)
(6)
(7)
18
24 μA
IDDIO current is dependent on the electrical loading on the I/O pins.
To realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to
the PCLKCR0 register.
The TYP numbers are applicable over room temperature and nominal voltage.
The following is done in a loop:
• Data is continuously transmitted out of SPI-A, SCI-A, SCI-B, SCI-C, eCAN-A, and I2C-A ports.
• The hardware multiplier is exercised.
• Watchdog is reset.
• ADC is performing continuous conversion.
• GPIO17 is toggled.
If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.
CLA is continuously performing polynomial calculations.
For F2805x devices that do not have CLA, subtract the IDD current number for CLA (see Table 7-1) from the IDD (VREG disabled)/IDDIO
(VREG enabled) current numbers listed in Section 7.5.1 for operational mode.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Note
The peripheral-I/O multiplexing implemented in the device prevents simultaneous use of all available
peripherals because more than one peripheral function may share an I/O pin. It is, however, possible
to turn on the clocks to all the peripherals at the same time, although such a configuration is not
useful. If the clocks to all the peripherals are turned on at the same time, the current drawn by the
device will be more than the numbers specified in the current consumption tables.
7.5.2 Reducing Current Consumption
The 2805x devices incorporate a method to reduce the device current consumption. Because each peripheral
unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning
off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the
three low-power modes could be taken advantage of to reduce the current consumption even further. Table 7-1
indicates the typical reduction in current consumption achieved by turning off the clocks.
Table 7-1. Typical Current Consumption by Various
Peripherals (at 60 MHz)
(1)
(2)
(3)
PERIPHERAL
MODULE(1) (2)
IDD CURRENT
REDUCTION (mA)
ADC
2(3)
I2C
3
ePWM
2
eCAP
2
eQEP
2
SCI
2
SPI
2
COMP/DAC
1
PGA
2
CPU-TIMER
1
Internal zero-pin oscillator
0.5
CAN
2.5
CLA
20
All peripheral clocks (except CPU Timer clock) are disabled
upon reset. Writing to or reading from peripheral registers is
possible only after the peripheral clocks are turned on.
For peripherals with multiple instances, the current quoted is per
module. For example, the 2 mA value quoted for ePWM is for
one ePWM module.
This number represents the current drawn by the digital portion
of the ADC module. Turning off the clock to the ADC module
results in the elimination of the current drawn by the analog
portion of the ADC (IDDA) as well.
Note
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
Note
The baseline IDD current (current when the core is executing a dummy loop with no peripherals
enabled) is 40 mA, typical. To arrive at the IDD current for a given application, the current-drawn by the
peripherals (enabled by that application) must be added to the baseline IDD current.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
19
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Following are other methods to reduce power consumption further:
• The flash module may be powered down if code is run off SARAM. This method results in a current reduction
of 18 mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail.
• Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function.
• To realize the lowest VDDA current consumption in a low-power mode, see the respective analog chapter
of the TMS320x2805x Real-Time Microcontrollers Technical Reference Manual to ensure each module is
powered down as well.
• Power savings can be achieved by powering down the flash. This must be done by code running off RAM
(not flash).
7.5.3 Current Consumption Graphs (VREG Enabled)
Operational Current vs Frequency
140
Operational Current (mA)
120
100
80
60
40
20
0
0
10
20
30
40
50
60
70
SYSCLKOUT (MHz)
IDDIO
IDDA
Figure 7-1. Typical Operational Current Versus Frequency (F2805x)
Operational Power vs Frequency
Operational Power (mW)
500
450
400
350
300
250
200
0
10
20
30
40
50
60
70
SYSCLKOUT (MHz)
Figure 7-2. Typical Operational Power Versus Frequency (F2805x)
20
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Typical CLA operational current vs SYSCLKOUT
CLA operational IDDIO current (mA)
25
20
15
10
5
0
10
15
20
25
30
35
40
45
50
55
60
SYSCLKOUT (MHz)
Figure 7-3. Typical CLA Operational Current Versus SYSCLKOUT
7.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
VOH
High-level output voltage
VOL
Low-level output voltage
IIL
IIH
Input current
(low level)
Input current
(high level)
TEST CONDITIONS
IOH = IOH MAX
MIN
MAX UNIT
2.4
IOH = 50 μA
V
VDDIO – 0.2
IOL = IOL MAX
0.4
All GPIO pins
–80
–140
–205
–230
–300
–375
Pin with pullup
enabled
VDDIO = 3.3 V, VIN = 0 V
Pin with pullup
disabled
VDDIO = 3.3 V, VIN = 0 V
±2
Pin with pulldown
disabled
VDDIO = 3.3 V, VIN = VDDIO
±2
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = VDDIO
Output current, pullup or pulldown
VO = VDDIO or 0 V
disabled
CI
Input capacitance
VDDIO BOR trip point
XRS pin
V
μA
μA
IOZ
28
50
80
±2
Falling VDDIO
VDDIO BOR hysteresis
(1)
TYP
2
pF
2.78
V
35
Supervisor reset release delay
time
Time after BOR/POR/OVR event is removed to XRS
release
VREG VDD output
Internal VREG on
μA
400
mV
800
μs
1.9
V
When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage
(VDD) go out of range.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
21
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
7.7 Thermal Resistance Characteristics for PN Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
14.2
0
RΘJB
Junction-to-board thermal resistance
21.9
0
RΘJA
(High k PCB)
PsiJT
PsiJB
(1)
(2)
Junction-to-free air thermal resistance
Junction-to-package top
Junction-to-board
49.9
0
38.3
150
36.7
250
34.4
500
0.8
0
1.18
150
1.34
250
1.62
500
21.6
0
20.7
150
20.5
250
20.1
500
These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
7.8 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems
that exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical
factor that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature.
Hence, care should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the
operating junction temperature T J. Tcase is normally measured at the center of the package top-side surface. The
Semiconductor and IC Package Thermal Metrics Application Report helps to understand the thermal metrics and
definitions.
22
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
7.9 JTAG Debug Probe Connection Without Signal Buffering for the MCU
Figure 7-4 shows the connection between the MCU and JTAG header for a single-processor configuration. If
the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals must be
buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 7-4 shows the simpler,
no-buffering situation. For the pullup and pulldown resistor values, see Section 6.2.
6 inches or less
VDDIO
VDDIO
13
14
2
TRST
1
TMS
3
TDI
7
TDO
11
TCK
9
EMU0
PD
EMU1
TRST
GND
TMS
GND
TDI
GND
TDO
GND
TCK
GND
5
4
6
8
10
12
TCK_RET
MCU
JTAG Header
A.
See Figure 8-42 for JTAG/GPIO multiplexing.
Figure 7-4. JTAG Debug Probe Connection Without Signal Buffering for the MCU
Note
The 2805x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header onboard,
the EMU0/EMU1 pins on the header must be tied to VDDIO through a 4.7-kΩ (typical) resistor.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
23
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
7.10 Parameter Information
7.10.1 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
f
fall time
X
Unknown, changing, or don't care level
h
hold time
Z
High impedance
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
7.10.2 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For
actual cycle examples, see the appropriate cycle description section of this document.
7.11 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
42 W
Data Sheet Timing Reference Point
3.5 nH
Transmission Line
(A)
Output
Under
Test
Z0 = 50 W
4.0 pF
A.
B.
Device Pin
1.85 pF
(B)
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line
effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer)
from the data sheet timing.
Figure 7-5. 3.3-V Test Load Circuit
24
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
7.12 Power Sequencing
There is no power sequencing requirement needed to ensure the device is in the proper state after reset or
to prevent the I/Os from glitching during power up or power down (GPIO19, GPIO34 to GPIO38 do not have
glitch-free I/Os). No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin
(for analog pins, this value is 0.7 V above VDDA) before powering up the device. Voltages applied to pins on an
unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results.
VDDIO, VDDA
(3.3 V)
VDD (1.8 V)
INTOSC1
tINTOSCST
X1/X2
tOSCST
(B)
(A)
XCLKOUT
User-code dependent
tw(RSL1)
XRS
(D)
Address/data valid, internal boot-ROM code execution phase
Address/Data/
Control
(Internal)
td(EX)
th(boot-mode)(C)
Boot-Mode
Pins
User-code execution phase
User-code dependent
GPIO pins as input
Peripheral/GPIO function
Based on boot code
Boot-ROM execution starts
(E)
I/O Pins
GPIO pins as input (state depends on internal PU/PD)
User-code dependent
A.
B.
C.
D.
E.
Upon power up, SYSCLKOUT is OSCCLK/4. Because the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0,
SYSCLKOUT is further divided by 4 before SYSCLKOUT appears at XCLKOUT. XCLKOUT = OSCCLK/16 during this phase.
Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. XCLKOUT will not be visible at the
pin until explicitly configured by user code.
After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
Using the XRS pin is optional due to the on-chip POR circuitry.
The internal pullup or pulldown will take effect when BOR is driven high.
Figure 7-6. Power-on Reset
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
25
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
7.12.1 Reset ( XRS) Timing Requirements
MIN
th(boot-mode)
Hold time for boot-mode pins
tw(RSL2)
Pulse duration, XRS low on warm reset
MAX
UNIT
1000tc(SCO)
cycles
32tc(OSCCLK)
cycles
7.12.2 Reset ( XRS) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
tw(RSL1)
Pulse duration, XRS driven by device
tw(WDRS)
Pulse duration, reset pulse generated by watchdog
td(EX)
Delay time, address/data valid after XRS high
tINTOSCST
Start-up time, internal zero-pin oscillator
tOSCST (1)
On-chip crystal-oscillator start-up time
(1)
TYP
MAX
600
1
UNIT
μs
512tc(OSCCLK)
cycles
32tc(OSCCLK)
cycles
3
μs
10
ms
Dependent on crystal/resonator and board design.
INTOSC1
X1/X2
XCLKOUT
User-Code Dependent
tw(RSL2)
XRS
Address/Data/
Control
(Internal)
td(EX)
User-Code Execution
Boot-ROM Execution Starts
Boot-Mode
Pins
User-Code Execution Phase
Peripheral/GPIO Function
GPIO Pins as Input
th(boot-mode)(A)
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A.
After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
Figure 7-7. Warm Reset
26
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Figure 7-8 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004
and SYSCLKOUT = OSCCLK × 2. The PLLCR is then written with 0x0008. Immediately after the PLLCR register
is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is
complete, SYSCLKOUT reflects the new operating frequency, OSCCLK × 4.
OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
(Current CPU
Frequency)
OSCCLK/2
(CPU frequency while PLL is stabilizing
with the desired frequency. This period
(PLL lock-up time tp) is 1 ms long.)
OSCCLK * 4
(Changed CPU frequency)
Figure 7-8. Example of Effect of Writing Into PLLCR Register
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
27
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
7.13 Clock Specifications
7.13.1 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 2805x MCUs. Section 7.13.1.1 lists the cycle times of various clocks.
7.13.1.1 2805x Clock Table and Nomenclature (60-MHz Devices)
MIN
tc(SCO), Cycle time
SYSCLKOUT
Frequency
tc(LCO), Cycle time
LSPCLK(1)
tc(ADCCLK), Cycle time
(1)
(2)
MAX
UNIT
16.67
500
ns
2
60
MHz
60
MHz
60
MHz
MAX
UNIT
200
ns
5
20
MHz
33.3
200
ns
16.67
66.67(2)
15(2)
Frequency
ADC clock
NOM
ns
16.67
ns
Frequency
Lower LSPCLK will reduce device power consumption.
This value is the default reset value if SYSCLKOUT = 60 MHz.
7.13.1.2 Device Clocking Requirements/Characteristics
MIN
On-chip oscillator (X1/X2 pins)
(Crystal/Resonator)
tc(OSC), Cycle time
External oscillator/clock source
(XCLKIN pin) — PLL Enabled
tc(CI), Cycle time (C8)
External oscillator/clock source
(XCLKIN pin) — PLL Disabled
tc(CI), Cycle time (C8)
Limp mode SYSCLKOUT
(with /2 enabled)
Frequency
5
30
MHz
33.33
250
ns
4
30
MHz
Frequency range
Frequency
PLL lock time(1)
28
Frequency
tc(XCO), Cycle time (C1)
XCLKOUT
(1)
Frequency
NOM
50
1 to 5
MHz
66.67
2000
0.5
15
MHz
1
ms
tp
ns
The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are
used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum).
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
7.13.1.3 Internal Zero-Pin Oscillator (INTOSC1, INTOSC2) Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
30°C(1) (2)
Frequency
10.000
MHz
Internal zero-pin oscillator 2 (INTOSC2) at 30°C(1) (2)
Frequency
10.000
MHz
Internal zero-pin oscillator 1 (INTOSC1) at
Accuracy using oscillator
compensation(1) (2)
±1%
Step size (coarse trim)
55
Step size (fine trim)
14
Temperature drift(3)
3.03
Voltage (VDD) drift(3)
175
(1)
(2)
(3)
kHz
kHz
4.85
kHz/°C
Hz/mV
Oscillator frequency will vary over temperature, see Figure 7-9. To compensate for oscillator temperature drift, see the Oscillator
Compensation Guide and C2000Ware for C2000 MCUs.
Frequency range is ensured only when VREG is enabled, VREGENZ = VSS.
Output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (VDD) gradient. For
example:
•
•
An increase in temperature causes the output frequency to increase according to the temperature coefficient.
A decrease in voltage (VDD) causes the output frequency to decrease according to the voltage coefficient.
Zero-Pin Oscillator Frequency Movement With Temperature
10.6
10.5
Output Frequency (MHz)
10.4
10.3
10.2
10.1
10
9.9
9.8
9.7
9.6
–40
–30
–20
–10
Typical
0
10
20
30
40
50
60
70
80
90
100
110
120
Temperature (°C)
Max
Figure 7-9. Zero-Pin Oscillator Frequency Movement With Temperature
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
29
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
7.13.2 Clock Requirements and Characteristics
7.13.2.1 XCLKIN Timing Requirements - PLL Enabled
NO.
MIN
MAX UNIT
C9
tf(CI)
Fall time, XCLKIN
6
ns
C10
tr(CI)
Rise time, XCLKIN
C11
tw(CIL)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
45%
55%
6
ns
C12
tw(CIH)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45%
55%
7.13.2.2 XCLKIN Timing Requirements - PLL Disabled
NO.
MIN
C9
tf(CI)
C10
Fall time, XCLKIN
tr(CI)
Rise time, XCLKIN
MAX UNIT
Up to 20 MHz
6
20 MHz to 30 MHz
2
Up to 20 MHz
6
20 MHz to 30 MHz
2
C11
tw(CIL)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
45%
55%
C12
tw(CIH)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45%
55%
ns
ns
The possible configuration modes are shown in Table 8-21.
7.13.2.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
NO.
C3
tf(XCO)
Fall time, XCLKOUT
C4
tr(XCO)
Rise time, XCLKOUT
C5
tw(XCOL)
Pulse duration, XCLKOUT low
C6
(1)
(2)
tw(XCOH)
MIN
Pulse duration, XCLKOUT high
MAX
UNIT
5
ns
5
ns
H – 2(2)
H + 2(2)
ns
2(2)
2(2)
ns
H–
H+
A load of 40 pF is assumed for these parameters.
H = 0.5tc(XCO)
C10
C9
C8
XCLKIN(A)
C1
C6
C3
C4
C5
XCLKOUT(B)
A.
B.
The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to
illustrate the timing parameters only and may differ based on actual configuration.
XCLKOUT configured to reflect SYSCLKOUT.
Figure 7-10. Clock Timing
30
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
7.14 Flash Timing
7.14.1 Flash/OTP Endurance for T Temperature Material
ERASE/PROGRAM
TEMPERATURE(1)
Nf
Flash endurance for the array (write/erase cycles)
0°C to 105°C (ambient)
NOTP
OTP endurance for the array (write cycles)
0°C to 30°C (ambient)
(1)
MIN
TYP
20000
50000
MAX
UNIT
cycles
1
write
Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
7.14.2 Flash/OTP Endurance for S Temperature Material
ERASE/PROGRAM
TEMPERATURE(1)
Nf
Flash endurance for the array (write/erase cycles)
0°C to 125°C (ambient)
NOTP
OTP endurance for the array (write cycles)
0°C to 30°C (ambient)
(1)
MIN
TYP
20000
50000
MAX
UNIT
cycles
1
write
Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
7.14.3 Flash/OTP Endurance for Q Temperature Material
ERASE/PROGRAM
TEMPERATURE(1)
Nf
Flash endurance for the array (write/erase cycles)
–40°C to 125°C (ambient)
NOTP
OTP endurance for the array (write cycles)
–40°C to 30°C (ambient)
(1)
MIN
TYP
20000
50000
MAX
UNIT
cycles
1
write
Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
31
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
7.14.4 Flash Parameters at 60-MHz SYSCLKOUT
PARAMETER
Program Time(3)
TEST
CONDITIONS
MIN
TYP
250 2000(2)
ms
4K Sector
125 2000(2)
ms
50
8K Sector
4K Sector
IDDP (4)
VDD current consumption during Erase/Program cycle
IDDIOP (4)
VDDIO current consumption during Erase/Program cycle
IDDIOP (4)
VDDIO current consumption during Erase/Program cycle
(1)
(2)
(3)
(4)
UNIT
8K Sector
16-Bit Word
Erase Time(1)
MAX
VREG disabled
μs
2
12(2)
s
2
12(2)
s
80
mA
60
VREG enabled
120
mA
The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
Maximum flash parameter mentioned are for the first 100 program and erase cycles.
Program time is at the maximum device frequency. The programming time indicated in this table is applicable only when all the
required code/data is available in the device RAM, ready for programming. Program time includes overhead of the flash state machine
but does not include the time to transfer the following into RAM:
• the code that uses flash API to program the flash
• the Flash API itself
• Flash data to be programmed
Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain
a stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at
all times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board
(during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands
placed during the programming process.
7.14.5 Flash/OTP Access Timing
PARAMETER
MIN
MAX
UNIT
ta(fp)
Paged flash access time
40
ns
ta(fr)
Random flash access time
40
ns
ta(OTP)
OTP access time
60
ns
7.14.6 Flash Data Retention Duration
PARAMETER
tretention
32
Data retention duration
Submit Document Feedback
TEST CONDITIONS
TJ = 55°C
MIN
15
MAX
UNIT
years
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Table 7-2. Minimum Required Flash/OTP Wait-States at Different Frequencies
(1)
SYSCLKOUT
(MHz)
SYSCLKOUT
(ns)
PAGE
WAIT-STATE(1)
RANDOM
WAIT-STATE(1)
OTP
WAIT-STATE
60
16.67
2
2
3
55
18.18
2
2
3
50
20
1
1
2
45
22.22
1
1
2
40
25
1
1
2
35
28.57
1
1
2
30
33.33
1
1
1
Page and random wait-state must be ≥ 1.
The equations to compute the Flash page wait-state and random wait-state in Table 7-2 are as follows:
ù
éæ t a( f · p ) ö
÷ - 1ú round up to the next highest integer
Flash Page Wait State = êç
úû
êëçè t c (SCO ) ÷ø
éæ t a(f ×r) ö ù
÷ - 1ú round up to the next highest integer, or 1, whichever is larger
Flash Random Wait State = êç
êëçè t c(SCO) ÷ø úû
The equation to compute the OTP wait-state in Table 7-2 is as follows:
éæ t a(OTP) ö ù
÷ - 1ú round up to the next highest integer, or 1, whichever is larger
OTP Wait State = êç
êëçè t c(SCO) ÷ø úû
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
33
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
8 Detailed Description
8.1 Overview
8.1.1 CPU
The 2805x (C28x) family is a member of the TMS320C2000™ MCU platform. The C28x-based controllers have
the same 32-bit fixed-point architecture as existing C28x MCUs. Each C28x-based controller, including the
2805x device, is a very efficient C/C++ engine, enabling users to develop not only their system control software
in a high-level language, but also enabling development of math algorithms using C/C++. The device is as
efficient at MCU math tasks as it is at system control tasks. This efficiency removes the need for a second
processor in many systems. The 32 × 32-bit MAC 64-bit processing capabilities enable the controller to handle
higher numerical resolution problems efficiently. Add to this feature the fast interrupt response with automatic
context save of critical registers, resulting in a device that can service many asynchronous events with minimal
latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining
enables the device to execute at high speeds without resorting to expensive high-speed memories. Special
branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional
operations further improve performance.
8.1.2 Control Law Accelerator
The C28x CLA is a single-precision (32-bit) floating-point unit that extends the capabilities of the C28x CPU by
adding parallel processing. The CLA is an independent processor with its own bus structure, fetch mechanism,
and pipeline. Eight individual CLA tasks, or routines, can be specified. Each task is started by software or
a peripheral such as the ADC, ePWM, eCAP, eQEP, or CPU-Timer 0. The CLA executes one task at a
time to completion. When a task completes the main CPU is notified by an interrupt to the PIE and the
CLA automatically begins the next highest-priority pending task. The CLA can directly access the ADC Result
registers, ePWM, eCAP, eQEP, and the Comparator and DAC registers. Dedicated message RAMs provide a
method to pass additional data between the main CPU and the CLA.
8.1.3 Memory Bus (Harvard Bus Architecture)
As with many MCU-type devices, multiple buses are used to move data between the memories and peripherals
and the CPU. The memory bus architecture contains a program read bus, data read bus, and data write bus.
The program read bus consists of 22 address lines and 32 data lines. The data read and write buses consist
of 32 address lines and 32 data lines each. The 32-bit-wide data buses enable single cycle 32-bit operations.
The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a
data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus
prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows:
Highest:
Data Writes
(Simultaneous data and program writes cannot occur on the memory bus.)
Program Writes
(Simultaneous data and program writes cannot occur on the memory bus.)
Data Reads
Lowest:
34
Program Reads
(Simultaneous program reads and fetches cannot occur on the
memory bus.)
Fetches
(Simultaneous program reads and fetches cannot occur on the
memory bus.)
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.1.4 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the devices
adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various
buses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16
or 32 data lines and associated control signals. Three versions of the peripheral bus are supported. One
version supports only 16-bit accesses (called peripheral frame 2). Another version supports both 16- and 32-bit
accesses (called peripheral frame 1). The third version supports CLA access and both 16- and 32-bit accesses
(called peripheral frame 3).
8.1.5 Real-Time JTAG and Analysis
The devices implement the standard IEEE 1149.1 (IEEE Standard 1149.1-1990 Standard Test Access Port
and Boundary Scan Architecture) JTAG interface for in-circuit based debug. Additionally, the devices support
real-time mode of operation allowing modification of the contents of memory, peripheral, and register locations
while the processor is running and executing code and servicing interrupts. The user can also single step
through non-time-critical code while enabling time-critical interrupts to be serviced without interference. The
device implements the real-time mode in hardware within the CPU. This feature is unique to the 28x family of
devices, and requires no software monitor. Additionally, special analysis hardware is provided that allows setting
of hardware breakpoint or data/address watch-points and generating various user-selectable break events when
a match occurs.
8.1.6 Flash
The F28055 and F28054 devices contain 64K × 16 of embedded flash memory, segregated into six 8K × 16
sectors and four 4K × 16 sectors. The F28053, F28052, and F28051 devices contain 32K × 16 of embedded
flash memory, segregated into three 8K × 16 sectors and two 4K × 16 sectors. The F28050 device contains 16K
× 16 of embedded flash memory, segregated into one 8K × 16 sector and two 4K × 16 sectors. The devices also
contain a single 1K × 16 of OTP memory at address range 0x3D 7800 to 0x3D 7BFF. The user can individually
erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible
to use one sector of the flash or the OTP to execute flash algorithms that erase or program other sectors.
Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP
is mapped to both program and data space; therefore, the flash/OTP can be used to execute code or store data
information.
Note
The Flash and OTP wait-states can be configured by the application. This feature allows applications
running at slower frequencies to configure the flash to use fewer wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options
register. With this mode enabled, effective performance of linear code execution will be much faster
than the raw performance indicated by the wait-state configuration alone. The exact performance gain
when using the flash pipeline mode is application-dependent.
For more information on the flash options, Flash wait-state, and OTP wait-state registers, see the
System Control and Interrupts chapter of the TMS320x2805x Real-Time Microcontrollers Technical
Reference Manual.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
35
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.1.7 M0, M1 SARAMs
All devices contain these two blocks of single access memory, each 1K × 16 in size. The stack pointer points
to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices,
are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data
variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the
programmer, which makes for easier programming in high-level languages.
8.1.8 L0 SARAM, and L1, L2, and L3 DPSARAMs
The device contains up to 8K × 16 of single-access RAM. To ascertain the exact size for a given device, see the
device-specific memory map figures in Section 8.2. This block is mapped to both program and data space. Block
L0 is 2K in size and is dual mapped to both program and data space. Blocks L1 and L2 are both 1K in size, and
together with L0, are shared with the CLA which can use these blocks for its data space. Block L3 is 4K in size
and is shared with the CLA which can use this block for its program space. DPSARAM refers to the dual-port
configuration of these blocks.
8.1.9 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the
bootloader software what boot mode to use on power up. The user can select to boot normally or to download
new software from an external connection or to select boot software that is programmed in the internal flash/
ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math-related
algorithms. Table 8-1 provides the boot mode selection.
Table 8-1. Boot Mode Selection
MODE
GPIO37/TDO
GPIO34/COMP2OUT/
COMP3OUT
TRST
3
1
1
0
GetMode
2
1
0
0
Wait (see Section 8.1.10 for description)
1
0
1
0
SCI
0
0
0
0
Parallel IO
EMU
x
x
1
Emulation Boot
MODE
8.1.9.1 Emulation Boot
When the JTAG debug probe is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In
this case, the boot ROM detects that a JTAG debug probe is connected and uses the contents of two reserved
SARAM locations in the PIE vector table to determine the boot mode. If the content of either location is invalid,
then the Wait boot option is used. All boot mode options can be accessed in emulation boot.
8.1.9.2 GetMode
The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another boot
option by programming two locations in the OTP. If the content of either OTP location is invalid, then boot to flash
is used. One of the following loaders can be specified: SCI, SPI, I2C, CAN, or OTP.
36
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.1.9.3 Peripheral Pins Used by the Bootloader
Table 8-2 lists the GPIO pins that are used by each peripheral bootloader. See the GPIO mux table to see if
these conflict with any of the peripherals you want to use in your application.
Table 8-2. Peripheral Bootload Pins
BOOTLOADER
PERIPHERAL LOADER PINS
SCI
SCIRXDA (GPIO28)
SCITXDA (GPIO29)
Parallel Boot
Data (GPIO31,30,5:0)
28x Control (GPIO26)
Host Control (GPIO27)
SPI
SPISIMOA (GPIO16)
SPISOMIA (GPIO17)
SPICLKA (GPIO18)
SPISTEA (GPIO19)
I2C
SDAA (GPIO28)
SCLA (GPIO29)
CAN
CANRXA (GPIO30)
CANTXA (GPIO31)
8.1.10 Security
The TMS320F2805x device supports high levels of security with a dual-zone (Z1/Z2) feature to protect user's
firmware from being reverse-engineered. The dual-zone feature enables the user to co-develop application
software with a third-party or subcontractor by preventing visibility into each other's software IP. The security
features a 128-bit password (hardcoded for 16 wait states) for each zone, which the user programs into the
USER-OTP. Each zone has its own dedicated USER-OTP, which must be programmed by the user with the
required security settings, including the 128-bit password. Because OTP cannot be erased, to provide the user
with the flexibility of changing security-related settings and passwords multiple times, a 32-bit link pointer is
stored at the beginning of each USER-OTP. Because the user can only flip a 1 in USER-OTP to 0, the most
significant bit position in the link pointer, programmed as 0, defines the USER-OTP region (zone-select) for
each zone in which security-related settings and passwords are stored. Table 8-3 provides the location of the
zone-select block based on the link pointer. Table 8-4 shows the zone-select block organization in USER-OTP.
Table 8-3. Location of Zone-Select Block Based on Link Pointer
Zx LINK POINTER VALUE
ADDRESS OFFSET FOR ZONE-SELECT
32’bxx111111111111111111111111111111
0x10
32’bxx111111111111111111111111111110
0x20
32’bxx11111111111111111111111111110x
0x30
32’bxx1111111111111111111111111110xx
0x40
32’bxx111111111111111111111111110xxx
0x50
32’bxx11111111111111111111111110xxxx
0x60
32’bxx1111111111111111111111110xxxxx
0x70
32’bxx111111111111111111111110xxxxxx
0x80
32’bxx11111111111111111111110xxxxxxx
0x90
32’bxx1111111111111111111110xxxxxxxx
0xa0
32’bxx111111111111111111110xxxxxxxxx
0xb0
32’bxx11111111111111111110xxxxxxxxxx
0xc0
32’bxx1111111111111111110xxxxxxxxxxx
0xd0
32’bxx111111111111111110xxxxxxxxxxxx
0xe0
32’bxx11111111111111110xxxxxxxxxxxxx
0xf0
32’bxx1111111111111110xxxxxxxxxxxxxx
0x100
32’bxx111111111111110xxxxxxxxxxxxxxx
0x110
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
37
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
Table 8-3. Location of Zone-Select Block Based on Link Pointer (continued)
Zx LINK POINTER VALUE
ADDRESS OFFSET FOR ZONE-SELECT
32’bxx11111111111110xxxxxxxxxxxxxxxx
0x120
32’bxx1111111111110xxxxxxxxxxxxxxxxx
0x130
32’bxx111111111110xxxxxxxxxxxxxxxxxx
0x140
32’bxx11111111110xxxxxxxxxxxxxxxxxxx
0x150
32’bxx1111111110xxxxxxxxxxxxxxxxxxxx
0x160
32’bxx111111110xxxxxxxxxxxxxxxxxxxxx
0x170
32’bxx11111110xxxxxxxxxxxxxxxxxxxxxx
0x180
32’bxx1111110xxxxxxxxxxxxxxxxxxxxxxx
0x190
32’bxx111110xxxxxxxxxxxxxxxxxxxxxxxx
0x1a0
32’bxx11110xxxxxxxxxxxxxxxxxxxxxxxxx
0x1b0
32’bxx1110xxxxxxxxxxxxxxxxxxxxxxxxxx
0x1c0
32’bxx110xxxxxxxxxxxxxxxxxxxxxxxxxxx
0x1d0
32’bxx10xxxxxxxxxxxxxxxxxxxxxxxxxxxx
0x1e0
32’bxx0xxxxxxxxxxxxxxxxxxxxxxxxxxxxx
0x1f0
Table 8-4. Zone-Select Block Organization in USER-OTP
16-BIT ADDRESS OFFSET
(WITH RESPECT TO OFFSET OF ZONESELECT)
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
CONTENT
Zx-EXEONLYRAM
Zx-EXEONLYSECT
Zx-GRABRAM
Zx-GRABSECT
Zx-CSMPSWD0
Zx-CSMPSWD1
Zx-CSMPSWD2
Zx-CSMPSWD3
The Dual Code Security Module (DCSM) is used to protect the flash/OTP/Lx SARAM blocks/CLA/Secure ROM
content. Individual flash sectors and SARAM blocks can be attached to any of the secure zone at start-up
time. Secure ROM and the CLA are always attached to Z1. Resources attached to (owned by) one zone do
not have any access to code running in the other zone when it is secured. Individual flash sectors, as well
as SARAM blocks, can be further protected by enabling the EXEONLY protection. EXEONLY flash sectors or
SARAM blocks do not have READ/WRITE access. Only code execution is allowed from such memory blocks.
The security feature prevents unauthorized users from examining memory contents through the JTAG port,
executing code from external memory, or trying to boot load an undesirable software that would export the
secure memory contents. To enable access to the secure blocks of a particular zone, the user must write a
128-bit value in the CSMKEY registers of the zone; this value must match the values stored in the password
locations in USER-OTP. If the 128 bits of the password locations in USER-OTP of a particular zone are all 1s
38
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
www.ti.com
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
(unprogrammed), then the security for that zone gets UNLOCKED as soon as a dummy read is done to the
password locations in USER-OTP (the value in the CSMKEY register becomes "Don’t care" in this case).
In addition to the DCSM, the Emulation Code Security Logic (ECSL) has been implemented for each zone to
prevent unauthorized users from stepping through secure code. A halt inside secure code will trip the ECSL and
break the emulation connection. To allow emulation of secure code while maintaining DCSM protection against
secure memory reads, the user must write the lower 64 bits of the USER-OTP password into the CSMKEY
register of the zone to disable the ECSL. Dummy reads of all 128 bits of the password for that particular zone
in USER-OTP must still be performed. If the lower 64 bits of the password locations of a particular zone are all
zeros, then the ECSL for that zone gets disabled as soon as a dummy read is done to the password locations in
USER-OTP (the value in the CSMKEY register becomes "Don’t care" in this case).
When power is applied to a secure device that is connected to a JTAG debug probe, the CPU will start executing
and may execute an instruction that performs an access to a protected area. If this happens, the ECSL will
trip and cause the JTAG circuitry to be deactivated. Under this condition, a host (such as a computer running
CCS or flash programming software) would not be able to establish connection with the device. The solution
is to use the Wait boot option. In this mode, the device loops around a software breakpoint to allow a JTAG
debug probe to be connected without tripping security. The user can then exit this mode once the JTAG debug
probe is connected by using one of the emulation boot options as described in the Boot ROM chapter of the
TMS320x2805x Real-Time Microcontrollers Technical Reference Manual. The 2805x devices do not support
hardware wait-in-reset mode.
Note
If reprogramming of a secure device via JTAG may be needed in future, it is important to design
the board in such a way that the device could be put in Wait boot mode upon power-up (when
reprogramming is warranted). Otherwise, ECSL may deactivate the JTAG circuitry and prevent
connection to the device, as mentioned earlier. If reconfiguring the device for Wait boot mode in
the field is not practical, some mechanism must be implemented in the firmware to detect when a
firmware update is warranted. Code could then branch to the desired bootloader in the boot ROM. It
could also branch to the Wait boot mode, at which point the JTAG debug probe could be connected,
device unsecured and programming accomplished through JTAG itself.
To prevent reverse-engineering of the code in secure zone, unauthorized users are prevented from looking at the
CPU registers in the CCS Expressions Window. The values in the Expressions Window for all of these registers,
except for PC and some status bits, display false values when code is running from a secure zone. This feature
gets disabled if the zone is unlocked.
•
•
•
Note
The USER-OTP contains security-related settings for their respective zone. Execution is not
allowed from the USER-OTP; therefore, the user should not keep any code/data in this region.
The 128-bit password must not be programmed to zeros. Doing so would permanently lock the
device.
The user must try not to write into the CPU registers through the debugger watch window when
code is running/halted from/inside secure zone. This may corrupt the execution of the actual
program.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
39
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
Dual Code Security Module Disclaimer
THE DUAL CODE SECURITY MODULE (DCSM) INCLUDED ON THIS DEVICE WAS DESIGNED
TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM
OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS
STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS
FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE DCSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE DCSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE DCSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED
OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT
LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF
BUSINESS OR OTHER ECONOMIC LOSS.
8.1.11 Peripheral Interrupt Expansion Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block
can support up to 96 peripheral interrupts. On the F2805x devices, 54 of the possible 96 interrupts are used by
peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines
(INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that
can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. Eight
CPU clock cycles are needed to fetch the vector and save critical CPU registers. Hence the CPU can quickly
respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual
interrupt can be enabled or disabled within the PIE block.
40
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.1.12 External Interrupts (XINT1 to XINT3)
The devices support three masked external interrupts (XINT1 to XINT3). Each of the interrupts can be selected
for negative, positive, or both negative and positive edge triggering and can also be enabled or disabled. These
interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is
detected. This counter can be used to accurately time-stamp the interrupt. There are no dedicated pins for the
external interrupts. XINT1, XINT2, and XINT3 interrupts can accept inputs from the GPIO0 to GPIO31 pins.
8.1.13 Internal Zero-Pin Oscillators, Oscillator, and PLL
The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a crystal
attached to the on-chip oscillator circuit. A PLL is provided supporting up to 12 input-clock-scaling ratios. The
PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower
power operation is desired. See Section 7.13 for timing details. The PLL block can be set in bypass mode.
8.1.14 Watchdog
Each device contains two watchdogs: CPU-watchdog that monitors the core and NMI-watchdog that is a missing
clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a certain time
frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog can be disabled if
necessary. The NMI-watchdog engages only in case of a clock failure and can either generate an interrupt or a
device reset.
8.1.15 Peripheral Clocking
The clocks to each individual peripheral can be enabled or disabled to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled relative to
the CPU clock.
8.1.16 Low-power Modes
The devices are full-static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU in low-power mode. Peripheral clocks may be turned off selectively and only
those peripherals that must function during IDLE are left operating. An enabled interrupt
from an active peripheral or the watchdog timer will wake the processor from IDLE mode.
STANDBY:
Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.
An external interrupt event will wake the processor and the peripherals. Execution begins
on the next valid cycle after detection of the interrupt event
HALT:
This mode basically shuts down the device and places the device in the lowest possible
power consumption mode. If the internal zero-pin oscillators are used as the clock source,
the HALT mode turns them off, by default. To keep these oscillators from shutting down,
the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin oscillators may
thus be used to clock the CPU-watchdog in this mode. If the on-chip crystal oscillator is
used as the clock source, the crystal oscillator is shut down in this mode. A reset or an
external signal (through a GPIO pin) or the CPU-watchdog can wake the device from this
mode.
The CPU clock (OSCCLK) and WDCLK should be from the same clock source before trying to put the device
into HALT or STANDBY.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
41
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
8.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
The device segregates peripherals into four sections. The mapping of peripherals is as follows:
PF0:
PF1:
PF2:
PF3:
PIE:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash:
Flash Waitstate Registers
Timers:
CPU-Timers 0, 1, 2 Registers
DCSM:
Dual Zone Security Module Registers
ADC:
ADC Result Registers
CLA
CLA Registers and Message RAMs
GPIO:
GPIO MUX Configuration and Control Registers
eCAN:
eCAN Configuration and Control Registers
eCAP:
eCAP Module and Registers
eQEP:
eQEP Module and Registers
SYS:
System Control Registers
SCI:
SCI Control and RX/TX Registers
SPI:
SPI Control and RX/TX Registers
ADC:
ADC Status, Control, and Configuration Registers
I2C:
I2C Module and Registers
XINT:
External Interrupt Registers
ePWM:
ePWM Module and Registers
AFE:
Comparator Modules, Digital Filters, and PGA Control Registers
eCAP:
eCAP Module and Registers
eQEP:
eQEP Module and Registers
ADC:
ADC Status, Control, and Configuration Registers
ADC:
ADC Result Registers
DAC:
DAC Control Registers
8.1.18 General-Purpose Input/Output Multiplexer
Most of the peripheral signals are multiplexed with GPIO signals. This muxing enables the user to use a pin as
GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured as inputs. The user
can individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can
also select the number of input qualification cycles. This selection is to filter unwanted noise glitches. The GPIO
signals can also be used to bring the device out of specific low-power modes.
42
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.1.19 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling.
The timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The
counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches
zero, the counter is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and
can be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS™. CPU-Timer 2 is connected to
INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
• SYSCLKOUT (default)
• Internal zero-pin oscillator 1 (INTOSC1)
• Internal zero-pin oscillator 2 (INTSOC2)
• External clock source
8.1.20 Control Peripherals
The devices support the following peripherals that are used for embedded control and communication:
ePWM:
The ePWM peripheral supports independent/complementary PWM generation,
adjustable dead-band generation for leading/trailing edges, latched/cycle-bycycle trip mechanism. The type 1 module found on 2805x devices also
supports increased dead-band resolution, enhanced SOC and interrupt
generation, and advanced triggering including trip functions based on
comparator outputs.
eCAP:
The eCAP peripheral uses a 32-bit time base and registers up to four
programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
eQEP:
The eQEP peripheral uses a 32-bit position counter, supports low-speed
measurement using capture unit and high-speed measurement using a 32-bit
unit timer. This peripheral has a watchdog timer to detect motor stall and input
error detection logic to identify simultaneous edge transition in QEP signals.
ADC:
The ADC block is a 12-bit converter. The ADC has up to 16 single-ended
channels pinned out, depending on the device. The ADC also contains two
sample-and-hold units for simultaneous sampling. Some ADC channels also
have PGAs, which can amplify the input signal by 3, 6, or 11.
Comparator and
Digital Filter
Subsystems:
Each comparator block consists of one analog comparator along with an
internal 6-bit reference for supplying one input of the comparator. The
comparator output signal filtering is achieved using the digital filter present
on each input line and qualifies the output of the COMP/DAC subsystem. The
filtered or unfiltered output of the COMP/DAC subsystem can be configured to
be an input to the Digital Compare submodule of the ePWM peripheral. There
is also a configurable option to bring the output of the COMP/DAC subsystem
onto the GPIOs.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
43
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
8.1.21 Serial Port Peripherals
The devices support the following serial communication peripherals:
44
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream
of programmed length (1 to 16 bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between
the MCU and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multi-device communications are supported by the master/slave
operation of the SPI. The SPI contains a 4-level receive and transmit FIFO for reducing
interrupt servicing overhead.
SCI:
The SCI is a 2-wire asynchronous serial port, commonly known as UART. The SCI
contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead.
I2C:
The I2C module provides an interface between an MCU and other devices compliant
with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and
connected by way of an I2C-bus. External components attached to this 2-wire serial
bus can transmit and receive up to 8-bit data to and from the MCU through the I2C
module. The I2C contains a 4-level receive and transmit FIFO for reducing interrupt
servicing overhead.
eCAN:
The eCAN is the enhanced version of the CAN peripheral. The eCAN supports 32
mailboxes, time-stamping of messages, and is compliant with ISO 11898-1 (CAN 2.0B).
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.2 Memory Maps
In Figure 8-1, Figure 8-2, Figure 8-3, and Figure 8-4, the following apply:
• Memory blocks are not to scale.
• Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are
restricted to data memory only. A user program cannot access these memory maps in program space.
• Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline order.
• Certain memory ranges are EALLOW protected against spurious writes after configuration.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
45
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Data Space
Prog Space
0x00 0000
M0 Vector RAM (Enabled if VMAP = 0)
0x00 0040
M0 SARAM (1K ´ 16, 0-Wait)
0x00 0400
0x00 0800
0x00 0D00
0x00 0E00
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
Peripheral Frame 0
0x00 1400
CLA Registers
0x00 1480
CLA-to-CPU Message RAM
0x00 1500
CPU-to-CLA Message RAM
0x00 1580
Peripheral Frame 0
0x00 2000
Reserved
0x00 6000
Peripheral Frame 1
(1K ´ 16, Protected)
0x00 6400
Peripheral Frame 3
(1.5K ´ 16, Protected)
0x00 6A00
Peripheral Frame 1
(1.5K ´ 16, Protected)
0x00 7000
Peripheral Frame 2
(4K ´ 16, Protected)
0x00 8000
0x00 8800
0x00 8C00
0x00 9000
www.ti.com
Reserved
L0 DPSARAM (2K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone, CLA Data RAM 2)
L1 DPSARAM (1K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone, CLA Data RAM 0)
L2 DPSARAM (1K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone, CLA Data RAM 1)
L3 DPSARAM (4K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone, CLA Prog RAM)
0x00 A000
Reserved
0x00 F000
CLA Data ROM (4K ´ 16)
0x01 0000
Reserved
0x3D 7800
User OTP, Zone 2 Passwords (512 ´ 16)
0x3D 7A00
User OTP, Zone 1 Passwords (512 ´ 16)
0x3D 7C00
Reserved
0x3D 7E00
0x3D 7FCB
Calibration Data
Configuration Data
0x3D 7FF0
Reserved
0x3E 8000
FLASH
(64K ´ 16, 10 Sectors, Dual Secure Zone)
(Z1/Z2 User-Selectable Security Zone Per Sector)
0x3F 7FFF
0x3F 8000
0x3F 8400
Zone 1 Secure Copy Code ROM
(1K ´ 16)
Zone 2 Secure Copy Code ROM
(1K ´ 16)
0x3F 8800
0x3F D000
0x3F FFC0
A.
Reserved
Boot ROM (12K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
CLA-specific registers and RAM apply to the 28055 device only.
Figure 8-1. 28055 and 28054 Memory Map
46
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
www.ti.com
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Data Space
Prog Space
0x00 0000
M0 Vector RAM (Enabled if VMAP = 0)
0x00 0040
M0 SARAM (1K ´ 16, 0-Wait)
0x00 0400
0x00 0800
0x00 0D00
0x00 0E00
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
Peripheral Frame 0
0x00 1400
CLA Registers
0x00 1480
CLA-to-CPU Message RAM
0x00 1500
CPU-to-CLA Message RAM
0x00 1580
Peripheral Frame 0
0x00 2000
Reserved
0x00 6000
Peripheral Frame 1
(1K ´ 16, Protected)
0x00 6400
Peripheral Frame 3
(1.5K ´ 16, Protected)
0x00 6A00
Peripheral Frame 1
(1.5K ´ 16, Protected)
0x00 7000
Peripheral Frame 2
(4K ´ 16, Protected)
0x00 8000
0x00 8800
0x00 8C00
0x00 9000
Reserved
L0 DPSARAM (2K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone, CLA Data RAM 2)
L1 DPSARAM (1K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone, CLA Data RAM 0)
L2 DPSARAM (1K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone, CLA Data RAM 1)
L3 DPSARAM (4K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone, CLA Prog RAM)
0x00 A000
Reserved
0x00 F000
CLA Data ROM (4K ´ 16)
0x01 0000
Reserved
0x3D 7800
User OTP, Zone 2 Passwords (512 ´ 16)
0x3D 7A00
User OTP, Zone 1 Passwords (512 ´ 16)
0x3D 7C00
Reserved
0x3D 7E00
0x3D 7FCB
Calibration Data
Configuration Data
0x3D 7FF0
Reserved
0x3F 0000
FLASH
(32K ´ 16, 5 Sectors, Dual Secure Zone)
(Z1/Z2 User-Selectable Security Zone Per Sector)
0x3F 7FFF
0x3F 8000
0x3F 8400
Zone 1 Secure Copy Code ROM
(1K ´ 16)
Zone 2 Secure Copy Code ROM
(1K ´ 16)
0x3F 8800
0x3F D000
0x3F FFC0
A.
Reserved
Boot ROM (12K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
CLA-specific registers and RAM apply to the 28053 device only.
Figure 8-2. 28053 and 28052 Memory Map
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
47
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Data Space
Prog Space
0x00 0000
M0 Vector RAM (Enabled if VMAP = 0)
0x00 0040
M0 SARAM (1K ´ 16, 0-Wait)
0x00 0400
0x00 0800
0x00 0D00
0x00 0E00
www.ti.com
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
Peripheral Frame 0
0x00 1400
CLA Registers
0x00 1480
CLA-to-CPU Message RAM
0x00 1500
CPU-to-CLA Message RAM
0x00 1580
Peripheral Frame 0
0x00 2000
Reserved
0x00 6000
Peripheral Frame 1
(1K ´ 16, Protected)
0x00 6400
Peripheral Frame 3
(1.5K ´ 16, Protected)
0x00 6A00
Peripheral Frame 1
(1.5K ´ 16, Protected)
0x00 7000
Peripheral Frame 2
(4K ´ 16, Protected)
Reserved
0x00 8000
Reserved
0x00 8800
0x00 8C00
0x00 9000
L1 DPSARAM (1K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone, CLA Data RAM 0)
L2 DPSARAM (1K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone, CLA Data RAM 1)
L3 DPSARAM (4K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone, CLA Prog RAM)
0x00 A000
Reserved
0x00 F000
CLA Data ROM (4K ´ 16)
0x01 0000
Reserved
0x3D 7800
User OTP, Zone 2 Passwords (512 ´ 16)
0x3D 7A00
User OTP, Zone 1 Passwords (512 ´ 16)
0x3D 7C00
Reserved
0x3D 7E00
0x3D 7FCB
0x3D 7FF0
Calibration Data
Configuration Data
Reserved
0x3F 0000
FLASH
(32K ´ 16, 5 Sectors, Dual Secure Zone)
(Z1/Z2 User-Selectable Security Zone Per Sector)
0x3F 7FFF
0x3F 8000
0x3F 8400
0x3F 8800
0x3F D000
0x3F FFC0
Zone 1 Secure Copy Code ROM
(1K ´ 16)
Zone 2 Secure Copy Code ROM
(1K ´ 16)
Reserved
Boot ROM (12K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
Figure 8-3. 28051 Memory Map
48
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
www.ti.com
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Data Space
Prog Space
0x00 0000
M0 Vector RAM (Enabled if VMAP = 0)
0x00 0040
M0 SARAM (1K ´ 16, 0-Wait)
0x00 0400
0x00 0800
0x00 0D00
0x00 0E00
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
Peripheral Frame 0
0x00 1400
Reserved
0x00 1580
Peripheral Frame 0
0x00 2000
Reserved
0x00 6000
Peripheral Frame 1
(1K ´ 16, Protected)
0x00 6400
Peripheral Frame 3
(1.5K ´ 16, Protected)
0x00 6A00
Peripheral Frame 1
(1.5K ´ 16, Protected)
0x00 7000
Peripheral Frame 2
(4K ´ 16, Protected)
0x00 8000
0x00 8800
0x00 8C00
Reserved
L0 DPSARAM (2K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone)
L1 DPSARAM (1K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone)
L2 DPSARAM (1K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone)
0x00 9000
Reserved
0x00 A000
Reserved
0x00 F000
Reserved
0x01 0000
Reserved
0x3D 7800
User OTP, Zone 2 Passwords (512 ´ 16)
0x3D 7A00
User OTP, Zone 1 Passwords (512 ´ 16)
0x3D 7C00
Reserved
0x3D 7E00
0x3D 7FCB
0x3D 7FF0
Calibration Data
Configuration Data
Reserved
0x3F 4000
FLASH
(16K ´ 16, 3 Sectors, Dual Secure Zone)
(Z1/Z2 User-Selectable Security Zone Per Sector)
0x3F 7FFF
0x3F 8000
0x3F 8400
0x3F 8800
0x3F D000
0x3F FFC0
Zone 1 Secure Copy Code ROM
(1K ´ 16)
Zone 2 Secure Copy Code ROM
(1K ´ 16)
Reserved
Boot ROM (12K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
Figure 8-4. 28050 Memory Map
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
49
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
Table 8-5, Table 8-6, and Table 8-7 list the addresses of flash sectors on the TMS320F2805x devices.
Table 8-5. Addresses of Flash Sectors in F28055 and F28054
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3E 8000 to 0x3E 8FFF
Sector J (4K × 16)
0x3E 9000 to 0x3E 9FFF
Sector I (4K × 16)
0x3E A000 to 0x3E BFFF
Sector H (8K × 16)
0x3E C000 to 0x3E DFFF
Sector G (8K × 16)
0x3E E000 to 0x3E FFFF
Sector F (8K × 16)
0x3F 0000 to 0x3F 1FFF
Sector E (8K × 16)
0x3F 2000 to 0x3F 3FFF
Sector D (8K × 16)
0x3F 4000 to 0x3F 5FFF
Sector C (8K × 16)
0x3F 6000 to 0x3F 6FFF
Sector B (4K × 16)
0x3F 7000 to 0x3F 7FFF
Sector A (4K × 16)
Table 8-6. Addresses of Flash Sectors in F28053, F28052, and F28051
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3F 0000 to 0x3F 1FFF
Sector E (8K × 16)
0x3F 2000 to 0x3F 3FFF
Sector D (8K × 16)
0x3F 4000 to 0x3F 5FFF
Sector C (8K × 16)
0x3F 6000 to 0x3F 6FFF
Sector B (4K × 16)
0x3F 7000 to 0x3F 7FFF
Sector A (4K × 16)
Table 8-7. Addresses of Flash Sectors in F28050
50
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3F 4000 to 0x3F 5FFF
Sector C (8K × 16)
0x3F 6000 to 0x3F 6FFF
Sector B (4K × 16)
0x3F 7000 to 0x3F 7FFF
Sector A (4K × 16)
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these blocks
to be write/read peripheral block protected. The protected mode makes sure that all accesses to these blocks
happen as written. Because of the pipeline, a write immediately followed by a read to different memory locations
will appear in reverse order on the memory bus of the CPU. This action can cause problems in certain peripheral
applications where the user expected the write to occur first (as written). The CPU supports a block protection
mode where a region of memory can be protected so that operations occur as written (the penalty is extra cycles
are added to align the operations). This mode is programmable, and by default, it protects the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 8-8.
Table 8-8. Wait-States
AREA
WAIT-STATES (CPU)
M0 and M1 SARAMs
0-wait
COMMENTS
Fixed
Peripheral Frame 0
0-wait
Peripheral Frame 1
0-wait (writes)
Cycles can be extended by peripheral generated ready.
2-wait (reads)
Back-to-back write operations to Peripheral Frame 1 registers will incur
a 1-cycle stall (1-cycle delay).
0-wait (writes)
Fixed. Cycles cannot be extended by the peripheral.
Peripheral Frame 2
2-wait (reads)
Peripheral Frame 3
0-wait (writes)
Assumes no conflict between CPU and CLA.
2-wait (reads)
Cycles can be extended by peripheral-generated ready.
L0 SARAM
0-wait data and program
Assumes no CPU conflicts
L1 SARAM
0-wait data and program
Assumes no CPU conflicts
L2 SARAM
0-wait data and program
Assumes no CPU conflicts
L3 SARAM
0-wait data and program
Assumes no CPU conflicts
OTP
Programmable
Programmed through the Flash registers.
1-wait minimum
1-wait is minimum number of wait states allowed.
Programmable
Programmed through the Flash registers.
Flash
0-wait Paged min
1-wait Random min
Random ≥ Paged
Flash Password
16-wait fixed
Boot-ROM
0-wait
Secure ROM
0-wait
Copyright © 2022 Texas Instruments Incorporated
Wait states of password locations are fixed.
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
51
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.3 Register Map
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.
See Table 8-9.
Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See Table
8-10.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See Table
8-11.
Peripheral Frame 3: These are peripherals that are mapped to CLA in addition to their respective
Peripheral Frame. See Table 8-12.
Table 8-9. Peripheral Frame 0 Registers
NAME(1)
ADDRESS RANGE
SIZE (×16)
EALLOW PROTECTED(2)
Device Emulation Registers
0x00 0880 to 0x00 0984
261
Yes
System Power Control Registers
0x00 0985 to 0x00 0987
3
Yes
0x00 0A80 to 0x00 0ADF
96
Yes
0x00 0B00 to 0x00 0B0F
16
No
DCSM Zone 1 Registers
0x00 0B80 to 0x00 0BBF
64
Yes
DCSM Zone 2 Registers
0x00 0BC0 to 0x00 0BEF
48
Yes
CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
Registers
0x00 0C00 to 0x00 0C3F
64
No
PIE Registers
0x00 0CE0 to 0x00 0CFF
32
No
PIE Vector Table
0x00 0D00 to 0x00 0DFF
256
No
CLA Registers
0x00 1400 to 0x00 147F
128
Yes
CLA to CPU Message RAM (CPU writes ignored)
0x00 1480 to 0x00 14FF
128
NA
CPU to CLA Message RAM (CLA writes ignored)
0x00 1500 to 0x00 157F
128
NA
FLASH
Registers(3)
ADC registers (0 wait read only)
(1)
(2)
(3)
Registers in Frame 0 support 16-bit and 32-bit accesses.
If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
The Flash Registers are also protected by the Dual Code Security Module.
Table 8-10. Peripheral Frame 1 Registers
ADDRESS RANGE
SIZE (×16)
EALLOW PROTECTED
eCAN-A Registers
NAME
0x00 6000 to 0x00 61FF
512
(1)
eCAP1 Registers
0x00 6A00 to 0x00 6A1F
32
No
eQEP1 Registers
0x00 6B00 to 0x00 6B3F
64
(1)
GPIO Registers
0x00 6F80 to 0x00 6FFF
128
(1)
(1)
52
Some registers are EALLOW protected. See the module reference guide for more information.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Table 8-11. Peripheral Frame 2 Registers
NAME
ADDRESS RANGE
SIZE (×16)
EALLOW PROTECTED
System Control Registers
0x00 7010 to 0x00 702F
32
Yes
SPI-A Registers
0x00 7040 to 0x00 704F
16
No
SCI-A Registers
0x00 7050 to 0x00 705F
16
No
SCI-B Registers
0x00 7750 to 0x00 775F
16
No
SCI-C Registers
0x00 7770 to 0x00 777F
16
No
NMI Watchdog Interrupt Registers
0x00 7060 to 0x00 706F
16
Yes
External Interrupt Registers
0x00 7070 to 0x00 707F
16
Yes
ADC Registers
0x00 7100 to 0x00 717F
128
(1)
I2C-A Registers
0x00 7900 to 0x00 793F
64
(1)
(1)
Some registers are EALLOW protected. See the module reference guide for more information.
Table 8-12. Peripheral Frame 3 Registers
NAME
ADDRESS RANGE
SIZE (×16)
EALLOW PROTECTED
ADC registers (0 wait read only)
0x00 0B00 to 0x00 0B0F
16
No
DAC Control Registers
0x00 6400 to 0x00 640F
16
Yes
DAC, PGA, Comparator, and Filter Enable
Registers
0x00 6410 to 0x00 641F
16
Yes
SWITCH Registers
0x00 6420 to 0x00 642F
16
Yes
Digital Filter and Comparator Control Registers
0x00 6430 to 0x00 647F
80
Yes
LOCK Registers
0x00 64F0 to 0x00 64FF
16
Yes
ePWM1 registers
0x00 6800 to 0x00 683F
64
(1)
ePWM2 registers
0x00 6840 to 0x00 687F
64
(1)
ePWM3 registers
0x00 6880 to 0x00 68BF
64
(1)
ePWM4 registers
0x00 68C0 to 0x00 68FF
64
(1)
ePWM5 registers
0x00 6900 to 0x00 693F
64
(1)
ePWM6 registers
0x00 6940 to 0x00 697F
64
(1)
ePWM7 registers
0x00 6980 to 0x00 69BF
64
(1)
eCAP1 Registers
0x00 6A00 to 0x00 6A1F
32
No
eQEP1 Registers
0x00 6B00 to 0x00 6B3F
64
(1)
(1)
Some registers are EALLOW protected. See the module reference guide for more information.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
53
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.4 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. Table 8-13 defines the registers.
Table 8-13. Device Emulation Registers
NAME
DEVICECNF
PARTID
REVID(1)
ADDRESS
RANGE
SIZE (×16)
EALLOW
PROTECTED
DESCRIPTION
0x0880 to
0x0881
2
Device Configuration Register
0x0882
1
PARTID Register
Yes
TMS320F28055
0x0105
TMS320F28054
0x0104
TMS320F28054M
0x0184
TMS320F28054F
0x0144
TMS320F28053
0x0103
TMS320F28052
0x0102
TMS320F28052M
0x0182
TMS320F28052F
0x0142
TMS320F28051
0x0101
TMS320F28050
0x0100
0x0000 - Silicon Rev. 0 - TMX
No
0x0883
1
Revision ID
Register
No
DC1
0x0886 to
0x0887
2
Device Capability Register 1.
The Device Capability Register is predefined by the part and
can be used to verify features. If any bit is 0 in this register, the
module is not present. See Table 8-14.
Yes
DC2
0x0888 to
0x0889
2
Device Capability Register 2.
The Device Capability Register is predefined by the part and
can be used to verify features. If any bit is 0 in this register, the
module is not present. See Table 8-15.
Yes
DC3
0x088A to
0x088B
2
Device Capability Register 3.
The Device Capability Register is predefined by the part and
can be used to verify features. If any bit is 0 in this register, the
module is not present. See Table 8-16.
Yes
0x0000 - Silicon Rev. A - TMS
(1)
54
Boot-ROM contents changed from Rev. 0 silicon to Rev. A silicon. For more details, see the TMS320x2805x Real-Time
Microcontrollers Technical Reference Manual.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Table 8-14. Device Capability Register 1 (DC1) Field Descriptions
(1)
BIT(1)
FIELD
TYPE
31:30
RSVD
R=0
29:22
PARTNO
R
21:14
RSVD
R=0
13
CLA
R
12:7
RSVD
R=0
6
L3
R
L3 is present when this bit is set.
5
L2
R
L2 is present when this bit is set.
4
L1
R
L1 is present when this bit is set.
L0 is present when this bit is set.
DESCRIPTION
Reserved
These 8 bits set the PARTNO field value in the PARTID register for the device. They
are readable in the PARTID[7:0] register bits.
Reserved
CLA is present when this bit is set.
Reserved
3
L0
R
2
RSVD
R=0
Reserved
1:0
RSVD
R=0
Reserved
All reserved bits should not be written to, but if any use case demands that reserved bits must be written to, then software must write
the same value that is read back from the reserved bits. These bits are reserved for future enhancements.
Table 8-15. Device Capability Register 2 (DC2) Field Descriptions
(1)
BIT(1)
FIELD
TYPE
31:28
RSVD
R=0
27
eCAN-A
R
26:17
RSVD
R=0
16
EQEP-1
R
15:13
RSVD
R=0
12
ECAP-1
R
11:9
RSVD
R=0
8
I2C-A
R
7:5
RSVD
R=0
DESCRIPTION
Reserved
eCAN-A is present when this bit is set.
Reserved
eQEP-1 is present when this bit is set.
Reserved
eCAP-1 is present when this bit is set.
Reserved
I2C-A is present when this bit is set.
Reserved
4
SPI-A
R
3
RSVD
R=0
SPI-A is present when this bit is set.
2
SCI-C
R
SCI-C is present when this bit is set.
1
SCI-B
R
SCI-B is present when this bit is set.
0
SCI-A
R
SCI-A is present when this bit is set.
Reserved
All reserved bits should not be written to, but if any use case demands that reserved bits must be written to, then software must write
the same value that is read back from the reserved bits. These bits are reserved for future enhancements.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
55
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
Table 8-16. Device Capability Register 3 (DC3) Field Descriptions
(1)
56
BIT(1)
FIELD
TYPE
31:20
RSVD
R=0
19
CTRIPFIL7
R
CTRIPFIL7(B7) is present when this bit is set.
18
CTRIPFIL6
R
CTRIPFIL6(B6) is present when this bit is set.
17
CTRIPFIL5
R
CTRIPFIL5(B4) is present when this bit is set.
16
CTRIPFIL4
R
CTRIPFIL4(A6) is present when this bit is set.
15
CTRIPFIL3
R
CTRIPFIL3(B1) is present when this bit is set.
14
CTRIPFIL2
R
CTRIPFIL2(A3) is present when this bit is set.
13
CTRIPFIL1
R
CTRIPFIL1(A1) is present when this bit is set.
12:8
RSVD
R=0
Reserved
7
RSVD
R=0
Reserved
6
ePWM7
R
ePWM7 is present when this bit is set.
5
ePWM6
R
ePWM6 is present when this bit is set.
4
ePWM5
R
ePWM5 is present when this bit is set.
3
ePWM4
R
ePWM4 is present when this bit is set.
2
ePWM3
R
ePWM3 is present when this bit is set.
1
ePWM2
R
ePWM2 is present when this bit is set.
0
ePWM1
R
ePWM1 is present when this bit is set.
DESCRIPTION
Reserved
All reserved bits should not be written to, but if any use case demands that reserved bits must be written to, then software must write
the same value that is read back from the reserved bits. These bits are reserved for future enhancements.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.5 VREG, BOR, POR
Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip voltage
regulator (VREG) to generate the VDD voltage from the VDDIO supply. This feature eliminates the cost and space
of a second external regulator on an application board. Additionally, internal power-on reset (POR) and brownout
reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode.
8.5.1 On-chip VREG
A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors are
required on each VDD pin to stabilize the generated voltage, supplying power to these pins is not needed
to operate the device. Conversely, the VREG can be disabled, if power or redundancy becomes the primary
concern of the application.
8.5.1.1 Using the On-chip VREG
To use the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended operating
voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by the core logic
will be generated by the VREG. Each VDD pin requires approximately 1.2 μF (minimum) capacitance for proper
regulation of the VREG. These capacitors should be located as close as possible to the VDD pins.
8.5.1.2 Disabling the On-chip VREG
To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to the VDD
pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied high.
8.5.2 On-chip Power-On Reset and Brownout Reset Circuit
The purpose of the POR is to create a clean reset throughout the device during the entire power-up procedure.
The trip point is a looser, lower trip point than the BOR, which watches for dips in the VDD or VDDIO rail during
device operation. The POR function is present on both VDD and VDDIO rails at all times. After initial device
power-up, the BOR function is present on VDDIO at all times, and on VDD when the internal VREG is enabled
( VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the voltages is below its respective
trip point. Additionally, when the internal voltage regulator is enabled, an overvoltage protection circuit will tie
XRS low if the VDD rail rises above its trip point. See Section 7.6 for the various trip points as well as the delay
time for the device to release the XRS pin after the undervoltage or overvoltage condition is removed. Figure 8-5
shows the VREG, POR, and BOR. To disable both the VDD and VDDIO BOR functions, a bit is provided in the
BORCFG register. For details, see the System Control and Interrupts chapter of the TMS320x2805x Real-Time
Microcontrollers Technical Reference Manual.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
57
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
In
I/O Pin
Out
(Force Hi-Z When High)
DIR (0 = Input, 1 = Output)
Internal
Weak Pullup
SYSRS
SYSCLKOUT
Deglitch
Filter
Sync RS
WDRST
MCLKRS
PLL
+
Clocking
Logic
XRS
Pin
C28x
Core
JTAG
TCK
Detect
Logic
VREGHALT
(A)
WDRST
(B)
PBRS
A.
B.
POR/BOR
Generating
Module
On-Chip
Voltage
Regulator
(VREG)
VREGENZ
WDRST is the reset signal from the CPU-watchdog.
PBRS is the reset signal from the POR/BOR module.
Figure 8-5. VREG + POR + BOR + Reset Signal Connectivity
58
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.6 System Control
This section describes the oscillator and clocking mechanisms, the watchdog function and the low power modes.
Table 8-17 lists the PLL, clocking, watchdog, and low-power mode registers.
Table 8-17. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME
DESCRIPTION(1)
ADDRESS
SIZE (×16)
BORCFG
0x00 0985
1
BOR Configuration register
XCLK
0x00 7010
1
XCLKOUT Control
PLLSTS
0x00 7011
1
PLL Status register
CLKCTL
0x00 7012
1
Clock Control register
PLLLOCKPRD
0x00 7013
1
PLL Lock Period
INTOSC1TRIM
0x00 7014
1
Internal Oscillator 1 Trim register
INTOSC2TRIM
0x00 7016
1
Internal Oscillator 2 Trim register
LOSPCP
0x00 701B
1
Low-Speed Peripheral Clock Prescaler register
PCLKCR0
0x00 701C
1
Peripheral Clock Control Register 0
PCLKCR1
0x00 701D
1
Peripheral Clock Control Register 1
LPMCR0
0x00 701E
1
Low Power Mode Control Register 0
PCLKCR3
0x00 7020
1
Peripheral Clock Control Register 3
PLLCR
0x00 7021
1
PLL Control register
SCSR
0x00 7022
1
System Control and Status register
WDCNTR
0x00 7023
1
Watchdog Counter register
PCLKCR4
0x00 7024
1
Peripheral Clock Control Register 4
WDKEY
0x00 7025
1
Watchdog Reset Key register
WDCR
0x00 7029
1
Watchdog Control register
(1)
All registers in this table are EALLOW protected.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
59
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Figure 8-6 shows the various clock domains that are discussed. Figure 8-7 shows the various clock sources
(both internal and external) that can provide a clock for device operation.
SYSCLKOUT
LOSPCP
(System Ctrl Regs)
PCLKCR0/1/3/4
(System Ctrl Regs)
Clock Enables
I/O
C28x Core
CLKIN
LSPCLK
SPI-A, SCI-A, SCI-B, SCI-C
Peripheral
Registers
Clock Enables
I/O
eCAP1, eQEP1
Peripheral
Registers
/2
GPIO
Mux
I/O
eCAN-A
Peripheral
Registers
Clock Enables
I/O
ePWM1, ePWM2,
ePWM3, ePWM4,
ePWM5, ePWM6, ePWM7
Peripheral
Registers
Clock Enables
I/O
I2C-A
Peripheral
Registers
Clock Enables
9 Ch
12-Bit ADC
ADC
Registers
Analog
Clock Enables
7 Ch
A.
AFE
AFE
Registers
CLKIN is the clock into the CPU. CLKIN is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as
SYSCLKOUT).
Figure 8-6. Clock and Reset Domains
60
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
www.ti.com
A.
B.
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Register loaded from TI OTP-based calibration function.
See Section 8.6.4 for details on missing clock detection.
Figure 8-7. Clock Tree
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
61
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.6.1 Internal Zero-Pin Oscillators
The F2805x devices contain two independent internal zero-pin oscillators. By default both oscillators are turned
on at power up, and internal oscillator 1 is the default clock source at this time. For power savings, unused
oscillators may be powered down by the user. The center frequency of these oscillators is determined by their
respective oscillator trim registers, written to in the calibration routine as part of the boot ROM execution. See
Section 7.13.1 for more information on these oscillators.
8.6.2 Crystal Oscillator Option
The on-chip crystal oscillator X1 and X2 pins are 1.8-V level signals and must never have 3.3-V level signals
applied to them. If a system 3.3-V external oscillator is to be used as a clock source, it should be connected to
the XCLKIN pin only. The X1 pin is not intended to be used as a single-ended clock input, it should be used with
X2 and a crystal.
Table 8-18 lists the typical specifications for the external quartz crystal (fundamental mode, parallel resonant).
Furthermore, ESR range = 30 to 150 Ω. For Table 8-18, Cshunt should be less than or equal to 5 pF.
Table 8-18. Typical Specifications for External Quartz Crystal
FREQUENCY (MHz)
Rd (Ω)
CL1 (pF)
CL2 (pF)
5
2200
18
18
10
470
15
15
15
0
15
15
20
0
12
12
XCLKIN/GPIO19/38
Turn off
XCLKIN path
in CLKCTL
register
X1
X2
Rd
Crystal
CL1
CL2
Figure 8-8. Using the On-chip Crystal Oscillator
Note
1. CL1 and CL2 are the total capacitance of the circuit board and components excluding the IC and
crystal. The value is usually approximately twice the value of the load capacitance of the crystal.
2. The load capacitance of the crystal is described in the crystal specifications of the manufacturers.
3. TI recommends that customers have the resonator/crystal vendor characterize the operation of
their device with the MCU chip. The resonator/crystal vendor has the equipment and expertise
to tune the tank circuit. The vendor can also advise the customer regarding the proper tank
component values that will produce proper start-up and stability over the entire operating range.
XCLKIN/GPIO19/38
External Clock Signal
(Toggling 0−VDDIO)
X1
X2
NC
Figure 8-9. Using a 3.3-V External Oscillator
62
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.6.3 PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals
for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to
select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register.
The watchdog module can be re-enabled (if needed) after the PLL module has stabilized, which takes 1 ms.
The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL
(VCOCLK) is at least 50 MHz.
Table 8-19. PLL Settings
PLLCR[DIV] VALUE(2) (3)
0000 (PLL bypass)
(1)
(2)
(3)
SYSCLKOUT (CLKIN)
PLLSTS[DIVSEL] = 0 or 1(1)
OSCCLK/4
(Default)(2)
PLLSTS[DIVSEL] = 2
PLLSTS[DIVSEL] = 3
OSCCLK/2
OSCCLK
0001
(OSCCLK × 1)/4
(OSCCLK × 1)/2
(OSCCLK × 1)/1
0010
(OSCCLK × 2)/4
(OSCCLK × 2)/2
(OSCCLK × 2)/1
0011
(OSCCLK × 3)/4
(OSCCLK × 3)/2
(OSCCLK × 3)/1
0100
(OSCCLK × 4)/4
(OSCCLK × 4)/2
(OSCCLK × 4)/1
0101
(OSCCLK × 5)/4
(OSCCLK × 5)/2
(OSCCLK × 5)/1
0110
(OSCCLK × 6)/4
(OSCCLK × 6)/2
(OSCCLK × 6)/1
0111
(OSCCLK × 7)/4
(OSCCLK × 7)/2
(OSCCLK × 7)/1
1000
(OSCCLK × 8)/4
(OSCCLK × 8)/2
(OSCCLK × 8)/1
1001
(OSCCLK × 9)/4
(OSCCLK × 9)/2
(OSCCLK × 9)/1
1010
(OSCCLK × 10)/4
(OSCCLK × 10)/2
(OSCCLK × 10)/1
1011
(OSCCLK × 11)/4
(OSCCLK × 11)/2
(OSCCLK × 11)/1
1100
(OSCCLK × 12)/4
(OSCCLK × 12)/2
(OSCCLK × 12)/1
By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes the PLLSTS[DIVSEL] configuration to /1.) PLLSTS[DIVSEL]
must be 0 before writing to the PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.
The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic has no effect.
This register is EALLOW protected. For more information, see the System Control and Interrupts chapter of the TMS320x2805x
Real-Time Microcontrollers Technical Reference Manual.
Table 8-20. CLKIN Divide Options
PLLSTS [DIVSEL]
CLKIN DIVIDE
0
/4
1
/4
2
/2
3
/1
The PLL-based clock module provides four modes of operation:
• INTOSC1 (Internal Zero-pin Oscillator 1): INTOSC1 is the on-chip internal oscillator 1. INTOSC1 can
provide the clock for the Watchdog block, core and CPU-Timer 2.
• INTOSC2 (Internal Zero-pin Oscillator 2): INTOSC2 is the on-chip internal oscillator 2. INTOSC2 can
provide the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be
independently chosen for the Watchdog block, core and CPU-Timer 2.
• Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external crystal/
resonator attached to the device to provide the time base. The crystal/resonator is connected to the X1/X2
pins. Some devices may not have the X1/X2 pins. See Section 6.2.1 for details.
• External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows the on-chip
(crystal) oscillator to be bypassed. The device clocks are generated from an external clock source input on
the XCLKIN pin. The XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected
as GPIO19 or GPIO38 through the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit disables
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
63
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
this clock input (forced low). If the clock source is not used or the respective pins are used as GPIOs, the
user should disable at boot time.
Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that clock
source must be disabled (using the CLKCTL register) before switching clocks.
Table 8-21. Possible PLL Configuration Modes
PLLSTS[DIVSEL]
CLKIN AND
SYSCLKOUT
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL
block is disabled in this mode. The PLL block being disabled can be useful in
reducing system noise and for low-power operation. The PLLCR register must
first be set to 0x0000 (PLL Bypass) before entering this mode. The CPU clock
(CLKIN) is derived directly from the input clock on either X1/X2, X1 or XCLKIN.
0, 1
OSCCLK/4
2
OSCCLK/2
3
OSCCLK/1
PLL Bypass is the default PLL configuration upon power-up or after an external
reset ( XRS). This mode is selected when the PLLCR register is set to 0x0000
or while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL is bypassed but is not turned off.
0, 1
OSCCLK/4
2
OSCCLK/2
3
OSCCLK/1
0, 1
OSCCLK × n/4
2
OSCCLK × n/2
3
OSCCLK × n/1
PLL MODE
PLL Off
PLL Bypass
PLL Enable
REMARKS
Achieved by writing a nonzero value n into the PLLCR register. Upon writing to
the PLLCR the device will switch to PLL Bypass mode until the PLL locks.
8.6.4 Loss of Input Clock (NMI-watchdog Function)
The 2805x devices may be clocked from either one of the internal zero-pin oscillators (INTOSC1 or INTOSC2),
the on-chip crystal oscillator, or from an external clock input. Regardless of the clock source, in PLL-enabled and
PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will issue a limp-mode clock at its output. This
limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1–5 MHz.
When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt.
Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired immediately
or the NMI-watchdog counter can issue a reset when the counter overflows. In addition to this action, the Missing
Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect the input clock
failure and initiate necessary corrective action such as switching over to an alternative clock source (if available)
or initiate a shutdown procedure for the system.
If software does not respond to the clock-fail condition, the NMI-watchdog triggers a reset after a
preprogrammed time interval. Figure 8-10 shows the interrupt mechanisms involved.
64
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
NMIFLG[NMINT]
NMIFLGCLR[NMINT]
Clear
Latch
Set Clear
XRS
NMINT
Generate
Interrupt
Pulse
When
Input = 1
1
0
NMIFLG[CLOCKFAIL]
Clear
Latch
Clear Set
0
NMIFLGCLR[CLOCKFAIL]
CLOCKFAIL
SYNC?
SYSCLKOUT
NMICFG[CLOCKFAIL]
XRS
NMIFLGFRC[CLOCKFAIL]
SYSCLKOUT
SYSRS
NMIWDPRD[15:0]
NMIWDCNT[15:0]
NMI Watchdog
NMIRS
See System
Control Section
Figure 8-10. NMI-watchdog
8.6.5 CPU-watchdog Module
The CPU-watchdog module on the 2805x device is similar to the one used on the 281x, 280x, and 283xx
devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this occurrence, the user must disable the
counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that
resets the watchdog counter. Figure 8-11 shows the various functional blocks within the watchdog module.
Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPU-watchdog
reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog counter stops
decrementing (that is, the watchdog counter does not change with the limp-mode clock).
Note
The CPU-watchdog is different from the NMI-watchdog. The CPU-watchdog is the legacy watchdog
that is present in all 28x devices.
Note
Applications in which the correct CPU operating frequency is absolutely critical should implement a
mechanism by which the MCU will be held in reset, should the input clocks ever fail. For example,
an R-C circuit may be used to trigger the XRS pin of the MCU, should the capacitor ever get fully
charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent the
capacitor from getting fully charged. Such a circuit would also help detect failure of the flash memory.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
65
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
A.
www.ti.com
The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 8-11. CPU-watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is
the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM block so that the
signal can wake the device from STANDBY (if enabled). For more details, see Section 8.7, Low-power Modes
Block.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, through the PIE, to take the CPU out of
IDLE mode.
In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset.
66
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.7 Low-power Modes Block
Table 8-22 summarizes the various modes.
Table 8-22. Low-power Modes
EXIT(1)
MODE
LPMCR0(1:0)
OSCCLK
CLKIN
SYSCLKOUT
IDLE
00
On
On
On
XRS, CPU-watchdog interrupt, any
enabled interrupt
STANDBY
01
On
(CPU-watchdog still running)
Off
Off
XRS, CPU-watchdog interrupt, GPIO
Port A signal, debugger(2)
1X
Off
(on-chip crystal oscillator and PLL
turned off, zero-pin oscillator and
CPU-watchdog state dependent
on user code.)
Off
Off
XRS, GPIO Port A signal, debugger(2),
CPU-watchdog
HALT(3)
(1)
(2)
(3)
The EXIT column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits
the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the
low-power mode will not be exited and the device will go back into the indicated low power mode.
The JTAG port can still function even if the CPU clock (CLKIN) is turned off.
The WDCLK must be active for the device to go into HALT mode.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt that is recognized by the processor.
The LPM block performs no tasks during this mode as long as the LPMCR0(LPM)
bits are set to 0,0.
STANDBY Mode:
Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode.
The user must select which signals will wake the device in the GPIOLPMSEL
register. The selected signals are also qualified by the OSCCLK before waking
the device. The number of OSCCLKs is specified in the LPMCR0 register.
HALT Mode:
CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake the
device from HALT mode. The user selects the signal in the GPIOLPMSEL
register.
Note
The low-power modes do not affect the state of the output pins (PWM pins included). They will be in
whatever state the code left them in when the IDLE instruction was executed. For more information,
see the System Control and Interrupts chapter of the TMS320x2805x Real-Time Microcontrollers
Technical Reference Manual.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
67
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.8 Interrupts
Figure 8-12 shows how the various interrupt sources are multiplexed.
Peripherals
(SPI, SCI, ePWM, I2C, eCAP, ADC, eQEP, CLA, eCAN)
WDINT
WAKEINT
LPMINT
Watchdog
Low Power Modes
SYSCLKOUT
XINT1
Interrupt Control
MUX
XINT1
Sync
C28
Core
GPIOXINT1SEL(4:0)
ADC
XINT2
XINT2SOC
MUX
PIE
INT1
to
INT12
Up to 96 Interrupts
XINT1CR(15:0)
XINT1CTR(15:0)
XINT2
Interrupt Control
XINT2CR(15:0)
XINT2CTR(15:0)
GPIOXINT2SEL(4:0)
MUX
GPIO0.int
XINT3
XINT3
Interrupt Control
XINT3CR(15:0)
GPIO
MUX
GPIO31.int
XINT3CTR(15:0)
GPIOXINT3SEL(4:0)
TINT0
INT13
TINT1
INT14
TINT2
NMI
CPU TIMER 0
CPU TIMER 1
CPU TIMER 2
NMI interrupt with watchdog function
(See the NMI Watchdog section.)
CPUTMR2CLK
CLOCKFAIL
NMIRS
System Control
(See the System
Control section.)
Figure 8-12. External and PIE Interrupt Sources
68
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts
per group equals 96 possible interrupts. Table 8-23 shows the interrupts used by 2805x devices.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine (ISR)
corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address pointed
to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0
should not be used when the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 to TRAP #12 will transfer program control to the ISR corresponding to the
first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the
vector from INT2.1, and so forth.
IFR[12:1]
IER[12:1]
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
(Flag)
INTx
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
MUX
PIEACKx
(Enable/Flag)
Global
Enable
(Enable)
(Enable)
(Flag)
PIEIERx[8:1]
PIEIFRx[8:1]
From
Peripherals
or
External
Interrupts
Figure 8-13. Multiplexing of Interrupts Using the PIE Block
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
69
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
In Table 8-23, out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for
future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level,
provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in
from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there
are two safe cases when the reserved interrupts could be used as software interrupts:
1. No peripheral within the group is asserting interrupts.
2. No peripheral interrupts are assigned to the group (for example, PIE group 7).
Table 8-23. PIE MUXed Peripheral Interrupt Vector Table
INT1.y
INT2.y
INT3.y
INT4.y
INT5.y
INT6.y
INT7.y
INT8.y
INT9.y
INT10.y
INT11.y
INT12.y
70
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
WAKEINT
TINT0
ADCINT9
XINT2
XINT1
Reserved
ADCINT2
ADCINT1
(LPM/WD)
(TIMER 0)
(ADC)
Ext. int. 2
Ext. int. 1
–
(ADC)
(ADC)
0xD4E
0xD4C
0xD4A
0xD48
0xD46
0xD44
0xD42
0xD40
Reserved
EPWM7_TZINT
EPWM6_TZINT
EPWM5_TZINT
EPWM4_TZINT
EPWM3_TZINT
EPWM2_TZINT
EPWM1_TZINT
–
(ePWM7)
(ePWM6)
(ePWM5)
(ePWM4)
(ePWM3)
(ePWM2)
(ePWM1)
0xD5E
0xD5C
0xD5A
0xD58
0xD56
0xD54
0xD52
0xD50
Reserved
EPWM7_INT
EPWM6_INT
EPWM5_INT
EPWM4_INT
EPWM3_INT
EPWM2_INT
EPWM1_INT
(ePWM1)
–
(ePWM7)
(ePWM6)
(ePWM5)
(ePWM4)
(ePWM3)
(ePWM2)
0xD6E
0xD6C
0xD6A
0xD68
0xD66
0xD64
0xD62
0xD60
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ECAP1_INT
(eCAP1)
–
–
–
–
–
–
–
0xD7E
0xD7C
0xD7A
0xD78
0xD76
0xD74
0xD72
0xD70
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EQEP1_INT
(eQEP1)
–
–
–
–
–
–
–
0xD8E
0xD8C
0xD8A
0xD88
0xD86
0xD84
0xD82
0xD80
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SPITXINTA
SPIRXINTA
(SPI-A)
–
–
–
–
–
–
(SPI-A)
0xD9E
0xD9C
0xD9A
0xD98
0xD96
0xD94
0xD92
0xD90
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
–
–
–
–
–
–
–
–
0xDAE
0xDAC
0xDAA
0xDA8
0xDA6
0xDA4
0xDA2
0xDA0
Reserved
Reserved
SCITXINTC
SCIRXINTC
Reserved
Reserved
I2CINT2A
I2CINT1A
–
–
(SCI-C)
(SCI-C)
–
–
(I2C-A)
(I2C-A)
0xDBE
0xDBC
0xDBA
0xDB8
0xDB6
0xDB4
0xDB2
0xDB0
Reserved
Reserved
ECAN1_INTA
ECAN0_INTA
SCITXINTB
SCIRXINTB
SCITXINTA
SCIRXINTA
(SCI-A)
–
–
(CAN-A)
(CAN-A)
(SCI-B)
(SCI-B)
(SCI-A)
0xDCE
0xDCC
0xDCA
0xDC8
0xDC6
0xDC4
0xDC2
0xDC0
ADCINT8
ADCINT7
ADCINT6
ADCINT5
ADCINT4
ADCINT3
ADCINT2
ADCINT1
(ADC)
(ADC)
(ADC)
(ADC)
(ADC)
(ADC)
(ADC)
(ADC)
(ePWM16)
(ePWM15)
(ePWM14)
(ePWM13)
(ePWM12)
(ePWM11)
(ePWM10)
(ePWM9)
0xDDE
0xDDC
0xDDA
0xDD8
0xDD6
0xDD4
0xDD2
0xDD0
CLA1_INT8
CLA1_INT7
CLA1_INT6
CLA1_INT5
CLA1_INT4
CLA1_INT3
CLA1_INT2
CLA1_INT1
(CLA)
(CLA)
(CLA)
(CLA)
(CLA)
(CLA)
(CLA)
(CLA)
(ePWM16)
(ePWM15)
(ePWM14)
(ePWM13)
(ePWM12)
(ePWM11)
(ePWM10)
(ePWM9)
0xDEE
0xDEC
0xDEA
0xDE8
0xDE6
0xDE4
0xDE2
0xDE0
LUF
LVF
Reserved
Reserved
Reserved
Reserved
Reserved
XINT3
(CLA)
(CLA)
–
–
–
–
–
Ext. Int. 3
0xDFE
0xDFC
0xDFA
0xDF8
0xDF6
0xDF4
0xDF2
0xDF0
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Table 8-24. PIE Configuration and Control Registers
NAME
DESCRIPTION(1)
ADDRESS
SIZE (×16)
PIECTRL
0x0CE0
1
PIE, Control register
PIEACK
0x0CE1
1
PIE, Acknowledge register
PIEIER1
0x0CE2
1
PIE, INT1 Group Enable register
PIEIFR1
0x0CE3
1
PIE, INT1 Group Flag register
PIEIER2
0x0CE4
1
PIE, INT2 Group Enable register
PIEIFR2
0x0CE5
1
PIE, INT2 Group Flag register
PIEIER3
0x0CE6
1
PIE, INT3 Group Enable register
PIEIFR3
0x0CE7
1
PIE, INT3 Group Flag register
PIEIER4
0x0CE8
1
PIE, INT4 Group Enable register
PIEIFR4
0x0CE9
1
PIE, INT4 Group Flag register
PIEIER5
0x0CEA
1
PIE, INT5 Group Enable register
PIEIFR5
0x0CEB
1
PIE, INT5 Group Flag register
PIEIER6
0x0CEC
1
PIE, INT6 Group Enable register
PIEIFR6
0x0CED
1
PIE, INT6 Group Flag register
PIEIER7
0x0CEE
1
PIE, INT7 Group Enable register
PIEIFR7
0x0CEF
1
PIE, INT7 Group Flag register
PIEIER8
0x0CF0
1
PIE, INT8 Group Enable register
PIEIFR8
0x0CF1
1
PIE, INT8 Group Flag register
PIEIER9
0x0CF2
1
PIE, INT9 Group Enable register
PIEIFR9
0x0CF3
1
PIE, INT9 Group Flag register
PIEIER10
0x0CF4
1
PIE, INT10 Group Enable register
PIEIFR10
0x0CF5
1
PIE, INT10 Group Flag register
PIEIER11
0x0CF6
1
PIE, INT11 Group Enable register
PIEIFR11
0x0CF7
1
PIE, INT11 Group Flag register
PIEIER12
0x0CF8
1
PIE, INT12 Group Enable register
PIEIFR12
0x0CF9
1
PIE, INT12 Group Flag register
Reserved
0x0CFA –
0x0CFF
6
Reserved
(1)
The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector
table is protected.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
71
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.8.1 External Interrupts
Table 8-25. External Interrupt Registers
NAME
ADDRESS
SIZE (×16)
DESCRIPTION
XINT1CR
0x00 7070
1
XINT1 configuration register
XINT2CR
0x00 7071
1
XINT2 configuration register
XINT3CR
0x00 7072
1
XINT3 configuration register
XINT1CTR
0x00 7078
1
XINT1 counter register
XINT2CTR
0x00 7079
1
XINT2 counter register
XINT3CTR
0x00 707A
1
XINT3 counter register
Each external interrupt can be enabled, disabled, or qualified using positive, negative, or both positive and
negative edge. For more information, see the System Control and Interrupts chapter of the TMS320x2805x
Real-Time Microcontrollers Technical Reference Manual.
8.8.1.1 External Interrupt Electrical Data/Timing
8.8.1.1.1 External Interrupt Timing Requirements
TEST CONDITIONS
tw(INT) (1) (2) Pulse duration, INT input low/high
(1)
(2)
MIN
MAX
UNIT
Synchronous
1tc(SCO)
cycles
With qualifier
1tc(SCO) + tw(IQSW)
cycles
For an explanation of the input qualifier parameters, see Section 8.9.12.3.2.1.
This timing is applicable to any GPIO pin configured for ADCSOC functionality.
8.8.1.1.2 External Interrupt Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
td(INT) (1)
(1)
Delay time, INT low/high to interrupt-vector fetch
MIN
MAX
UNIT
tw(IQSW) + 12tc(SCO)
cycles
For an explanation of the input qualifier parameters, see Section 8.9.12.3.2.1.
tw(INT)
XINT1, XINT2, XINT3
td(INT)
Address bus
(internal)
Interrupt Vector
Figure 8-14. External Interrupt Timing
72
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9 Peripherals
8.9.1 Control Law Accelerator
8.9.1.1 CLA Device-Specific Information
The CLA extends the capabilities of the C28x CPU by adding parallel processing. Time-critical control loops
serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables faster system
response and higher frequency control loops. Using the CLA for time-critical tasks frees up the main CPU to
perform other system and communication functions concurently. The following is a list of major features of the
CLA.
• Clocked at the same rate as the main CPU (SYSCLKOUT).
• An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
• Program address bus and program data bus
• Data address bus, data read bus, and data write bus
– Independent eight-stage pipeline.
– 12-bit program counter (MPC)
– Four 32-bit result registers (MR0–MR3)
– Two 16-bit auxillary registers (MAR0, MAR1)
– Status register (MSTF)
• Instruction set includes:
– IEEE single-precision (32-bit) floating-point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions.
– Conditional branch and call
– Data load and store operations
• The CLA program code can consist of up to eight tasks or ISRs.
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the CLA program memory space.
– One task is serviced at a time through to completion. There is no nesting of tasks.
– Upon task completion, a task-specific interrupt is flagged within the PIE.
– When a task finishes, the next highest-priority pending task is automatically started.
• Task trigger mechanisms:
– C28x CPU through the IACK instruction
– Task1 to Task7: the corresponding ADC, ePWM, eQEP, or eCAP module interrupt. For example:
• Task1: ADCINT1 or EPWM1_INT
• Task2: ADCINT2 or EPWM2_INT
• Task4: ADCINT4 or EPWM4_INT or EQEPx_INT or ECAPx_INT
• Task7: ADCINT7 or EPWM7_INT or EQEPx_INT or ECAPx_INT
– Task8: ADCINT8 or by CPU Timer 0 or EQEPx_INT or ECAPx_INT
• Memory and Shared Peripherals:
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
– The CLA has direct access to the CLA Data ROM that stores the math tables required by the routines in
the CLA Math Library.
– The CLA has direct access to the ADC Result registers, comparator and DAC registers, eCAP, eQEP, and
ePWM registers.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
73
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Peripheral Interrupts
IACK
CLA Control
Registers
ADCINT1 to ADCINT8
EPWM1_INT to EPWM7_INT
EQEP1_INT
CPU Timer 0
MIFR
MIOVF
MICLR
MICLROVF
MIFRC
MIER
MIRUN
MPISRCSEL1
CLA
Program
Memory
CLA Program Address Bus
CLA Program Data Bus
PU BUS
Map to CLA or
CPU Space
SYSCLKOUT
CLAENCLK
SYSRS
INT11
INT12
PIE
Main
28x
CPU
LVF
LUF
Main CPU Read/Write Data Bus
MVECT1
MVECT2
MVECT3
MVECT4
MVECT5
MVECT6
MVECT7
MVECT8
MMEMCFG
CLA
Data
Memory
Map to CLA or
CPU Space
MCTL
CLA
Data
ROM
CLA Execution
Registers
Main CPU Read Data Bus
CLA_INT1 to CLA_INT8
MPC(12)
MSTF(32)
MR0(32)
MR1(32)
MR2(32)
MR3(32)
MAR0(32)
MAR1(32)
CLA
Shared
Message
RAMs
MEALLOW
CLA Data Read Address Bus
CLA Data Read Data Bus
CLA Data Write Address Bus
CLA Data Write Data Bus
ADC
Result
Registers
Main CPU Bus
MPERINT1
to
MPERINT8
CLA Data Bus
ECAP1_INT
eCAP
Registers
eQEP
Registers
ePWM
Registers
Comparator
+ DAC
Registers
Figure 8-15. CLA Block Diagram
74
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.1.2 CLA Register Descriptions
Table 8-26. CLA Control Registers
(1)
(2)
REGISTER NAME
CLA1
ADDRESS
SIZE (×16)
EALLOW
PROTECTED
MVECT1
0x1400
1
Yes
CLA Interrupt/Task 1 Start Address
MVECT2
0x1401
1
Yes
CLA Interrupt/Task 2 Start Address
MVECT3
0x1402
1
Yes
CLA Interrupt/Task 3 Start Address
MVECT4
0x1403
1
Yes
CLA Interrupt/Task 4 Start Address
MVECT5
0x1404
1
Yes
CLA Interrupt/Task 5 Start Address
MVECT6
0x1405
1
Yes
CLA Interrupt/Task 6 Start Address
MVECT7
0x1406
1
Yes
CLA Interrupt/Task 7 Start Address
MVECT8
0x1407
1
Yes
CLA Interrupt/Task 8 Start Address
DESCRIPTION(1)
MCTL
0x1410
1
Yes
CLA Control register
MMEMCFG
0x1411
1
Yes
CLA Memory Configure register
MPISRCSEL1
0x1414
2
Yes
Peripheral Interrupt Source Select Register 1
MIFR
0x1420
1
Yes
Interrupt Flag register
MIOVF
0x1421
1
Yes
Interrupt Overflow register
MIFRC
0x1422
1
Yes
Interrupt Force register
MICLR
0x1423
1
Yes
Interrupt Clear register
MICLROVF
0x1424
1
Yes
Interrupt Overflow Clear register
MIER
0x1425
1
Yes
Interrupt Enable register
MIRUN
0x1426
1
Yes
Interrupt RUN register
MPC(2)
0x1428
1
–
CLA Program Counter
MAR0(2)
0x142A
1
–
CLA Aux Register 0
MAR1(2)
0x142B
1
–
CLA Aux Register 1
MSTF(2)
0x142E
2
–
CLA STF register
MR0(2)
0x1430
2
–
CLA R0H register
MR1(2)
0x1434
2
–
CLA R1H register
MR2(2)
0x1438
2
–
CLA R2H register
MR3(2)
0x143C
2
–
CLA R3H register
All registers in this table are DCSM protected.
The main C28x CPU has read only access to this register for debug purposes. The main CPU cannot perform CPU or debugger writes
to this register.
Table 8-27. CLA Message RAM
ADDRESS RANGE
SIZE (×16)
DESCRIPTION
0x1480 to 0x14FF
128
CLA to CPU Message RAM
0x1500 to 0x157F
128
CPU to CLA Message RAM
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
75
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
8.9.2 Analog Block
8.9.2.1 Analog-to-Digital Converter
8.9.2.1.1 ADC Device-Specific Information
The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sample-andhold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to 16
analog input channels. The converter can be configured to run with an internal bandgap reference to create truevoltage-based conversions or with a pair of external voltage references (VREFHI/VREFLO) to create ratiometricbased conversions.
Contrary to previous ADC types, this ADC is not sequencer-based. The user can easily create a series of
conversions from a single trigger. However, the basic principle of operation is centered around the configurations
of individual conversions, called SOCs, or Start-Of-Conversions.
Functions of the ADC module include:
•
•
•
12-bit ADC core with built-in dual sample-and-hold (S/H)
Simultaneous sampling or sequential sampling modes
Full range analog input: 0 V to 3.3 V fixed, or VREFHI/VREFLO ratiometric. The digital value of the input analog
voltage is derived by:
– Internal Reference (VREFLO = VSSA. VREFHI must not exceed VDDA when using either internal or external
reference modes.)
Digital Value = 0,
Digital Value = 4096 ´
when input £ 0 V
Input Analog Voltage - VREFLO
3.3
Digital Value = 4095,
when 0 V < input < 3.3 V
when input ³ 3.3 V
– External Reference (VREFHI/VREFLO connected to external references. VREFHI must not exceed VDDA when
using either internal or external reference modes.)
when input £ 0 V
Digital Value = 0,
Digital Value = 4096 ´
Input Analog Voltage - VREFLO
VREFHI - VREFLO
Digital Value = 4095,
•
•
•
•
•
76
when 0 V < input < VREFHI
when input ³ VREFHI
Up to 16-channel, multiplexed inputs
16 SOCs, configurable for trigger, sample window, and channel
16 result registers (individually addressable) to store conversion values
Multiple trigger sources
– S/W – software immediate start
– ePWM 1–7
– GPIO XINT2
– CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
– ADCINT1, ADCINT2
9 flexible PIE interrupts, can configure interrupt request after any conversion
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Table 8-28. ADC Configuration and Control Registers
ADDRESS
SIZE
(×16)
EALLOW
PROTECTE
D
ADCCTL1
0x7100
1
Yes
Control 1 register
ADCCTL2
0x7101
1
Yes
Control 2 register
ADCINTFLG
0x7104
1
No
Interrupt Flag register
ADCINTFLGCLR
0x7105
1
No
Interrupt Flag Clear register
ADCINTOVF
0x7106
1
No
Interrupt Overflow register
ADCINTOVFCLR
0x7107
1
No
Interrupt Overflow Clear register
INTSEL1N2
0x7108
1
Yes
Interrupt 1 and 2 Selection register
INTSEL3N4
0x7109
1
Yes
Interrupt 3 and 4 Selection register
INTSEL5N6
0x710A
1
Yes
Interrupt 5 and 6 Selection register
INTSEL7N8
0x710B
1
Yes
Interrupt 7 and 8 Selection register
INTSEL9N10
0x710C
1
Yes
Interrupt 9 Selection register (reserved Interrupt 10 Selection)
SOCPRICTL
0x7110
1
Yes
SOC Priority Control register
ADCSAMPLEMODE
0x7112
1
Yes
Sampling Mode register
ADCINTSOCSEL1
0x7114
1
Yes
Interrupt SOC Selection 1 register (for 8 channels)
ADCINTSOCSEL2
0x7115
1
Yes
Interrupt SOC Selection 2 register (for 8 channels)
ADCSOCFLG1
0x7118
1
No
SOC Flag 1 register (for 16 channels)
ADCSOCFRC1
0x711A
1
No
SOC Force 1 register (for 16 channels)
ADCSOCOVF1
0x711C
1
No
SOC Overflow 1 register (for 16 channels)
REGISTER NAME
ADCSOCOVFCLR1
DESCRIPTION
0x711E
1
No
SOC Overflow Clear 1 register (for 16 channels)
0x7120 to
0x712F
1
Yes
SOC0 Control Register to SOC15 Control register
0x7140
1
Yes
Reference Trim register
ADCOFFTRIM
0x7141
1
Yes
Offset Trim register
ADCREV
0x714F
1
No
Revision register
ADCSOC0CTL to
ADCSOC15CTL
ADCREFTRIM
Table 8-29. ADC Result Registers (Mapped to PF0)
REGISTER NAME
ADDRESS
SIZE
(×16)
EALLOW
PROTECTED
ADCRESULT0 to ADCRESULT15
0xB00 to
0xB0F
1
No
Copyright © 2022 Texas Instruments Incorporated
DESCRIPTION
ADC Result 0 register to ADC Result 15 register
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
77
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
0-Wait
Result
Registers
PF0 (CPU)
PF2 (CPU)
SYSCLKOUT
ADCENCLK
ADCINT 1
PIE
ADCINT 9
ADCTRIG 1
ADCTRIG 2
ADC
Channels
ADC
Core
12-Bit
ADCTRIG 3
ADCTRIG 4
ADCTRIG 5
ADCTRIG 6
ADCTRIG 7
ADCTRIG 8
ADCTRIG 9
ADCTRIG 10
ADCTRIG 11
ADCTRIG 12
ADCTRIG 13
ADCTRIG 14
ADCTRIG 15
ADCTRIG 16
ADCTRIG 17
ADCTRIG 18
TINT 0
TINT 1
TINT 2
XINT 2SOC
CPUTIMER 0
CPUTIMER 1
CPUTIMER 2
XINT 2
SOCA 1
SOCB 1
EPWM 1
SOCA 2
SOCB 2
EPWM 2
SOCA 3
SOCB 3
EPWM 3
SOCA 4
SOCB 4
EPWM 4
SOCA 5
SOCB 5
EPWM 5
SOCA 6
SOCB 6
EPWM 6
SOCA 7
SOCB 7
EPWM 7
Figure 8-16. ADC Connections
ADC Connections if the ADC is Not Used
TI recommends keeping the connections for the analog power pins, even if the ADC is not used. Following is a
summary of how the ADC pins should be connected, if the ADC is not used in an application:
• VDDA – Connect to VDDIO
• VSSA – Connect to VSS
• VREFLO – Connect to VSS
• ADCINAn, ADCINBn, VREFHI – Connect to VSSA
When the ADC module is used in an application, unused ADC input pins should be connected to analog ground
(VSSA).
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power savings.
78
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.2.1.2 ADC Electrical Data/Timing
8.9.2.1.2.1 ADC Electrical Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
DC SPECIFICATIONS
Resolution
12
ADC clock
Sample Window (see Table 8-30)
Bits
0.5
60
28055, 28054, 28053,
28052
MHz
10
63
28051, 28050
24
63
–4
4.5
LSB
–1
1.5
LSB
ADC clocks
ACCURACY
INL (Integral nonlinearity)(1)
DNL (Differential nonlinearity), no missing codes
Offset error (2)
Executing a single selfrecalibration(3)
–20
0
20
Executing periodic selfrecalibration(4)
–4
0
4
LSB
Overall gain error with internal reference
–60
60
LSB
Overall gain error with external reference
–40
40
LSB
Channel-to-channel offset variation
–4
4
LSB
Channel-to-channel gain variation
–4
4
LSB
ADC temperature coefficient with internal reference
–50
ppm/°C
ADC temperature coefficient with external reference
–20
ppm/°C
VREFLO
–100
µA
VREFHI
100
µA
ANALOG INPUT
Analog input voltage with internal reference
0
3.3
V
Analog input voltage with external reference
VREFLO
VREFHI
V
VSSA
0.66
V
2.64
VDDA
1.98
VDDA
VREFLO input voltage
VREFHI input voltage(5)
with VREFLO = VSSA
Input capacitance
Input leakage current
(1)
(2)
(3)
(4)
(5)
V
5
pF
±2
μA
INL will degrade when the ADC input voltage goes above VDDA.
1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external
reference.
For more details, see the TMS320F2805x Real-Time MCUs Silicon Errata.
Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be
performed as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset
Calibration" section in the Analog-to-Digital Converter and Comparator chapter of the TMS320x2805x Real-Time Microcontrollers
Technical Reference Manual.
VREFHI must not exceed VDDA when using either internal or external reference modes.
Table 8-30. ACQPS Values
Non-PGA
PGA
(1)
OVERLAP MODE(1)
NONOVERLAP MODE(1)
{9, 10, 23, 36, 49, 62}
{15, 16, 28, 29, 41, 42, 54, 55}
{23, 36, 49, 62}
{15, 16, 28, 29, 41, 42, 54, 55}
ACQPS = 6 can be used for the first sample if it is thrown away.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
79
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.2.1.2.2 ADC Power Modes
IDDA
UNITS
Mode A – Operating Mode
ADC OPERATING MODE
ADC Clock Enabled
Bandgap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 1)
ADC Powered Up (ADCPWDN = 1)
CONDITIONS
13
mA
Mode B – Quick Wake Mode
ADC Clock Enabled
Bandgap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 1)
ADC Powered Up (ADCPWDN = 0)
4
mA
Mode C – Comparator-Only Mode
ADC Clock Enabled
Bandgap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 0)
ADC Powered Up (ADCPWDN = 0)
1.5
mA
Mode D – Off Mode
ADC Clock Enabled
Bandgap On (ADCBGPWD = 0)
Reference On (ADCREFPWD = 0)
ADC Powered Up (ADCPWDN = 0)
0.075
mA
8.9.2.1.2.3 External ADC Start-of-Conversion Electrical Data/Timing
8.9.2.1.2.3.1 External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
tw(ADCSOCL)
MIN
Pulse duration, ADCSOCxO low
MAX
32tc(HCO)
UNIT
cycles
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 8-17. ADCSOCAO or ADCSOCBO Timing
8.9.2.1.2.4 Internal Temperature Sensor
8.9.2.1.2.4.1 Temperature Sensor Coefficient
PARAMETER(1) (2)
TSLOPE
Degrees C of temperature movement per measured ADC LSB change
of the temperature sensor
TOFFSET
ADC output at 0°C of the temperature sensor
(1)
(2)
(3)
(4)
80
MIN
TYP
MAX
0.18(4) (3)
1750
UNIT
°C/LSB
LSB
The accuracy of the temperature sensor for sensing absolute temperature (temperature in degrees) is not specified. The primary use
of the temperature sensor should be to compensate the internal oscillator for temperature drift (this operation is assured as per Section
7.13.1.3).
The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be
adjusted accordingly in external reference mode to the external reference voltage.
Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing
temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values
relative to an initial value.
ADC temperature coeffieicient is accounted for in this specification
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.2.1.2.5 ADC Power-Up Control Bit Timing
8.9.2.1.2.5.1 ADC Power-Up Delays
PARAMETER(1)
td(PWD)
(1)
MIN
MAX
Delay time for the ADC to be stable after power up
1
UNIT
ms
Timings maintain compatibility to the ADC module. The 2805x ADC supports driving all 3 bits at the same time td(PWD) ms before first
conversion.
ADCPWDN/
ADCBGPWD/
ADCREFPWD/
ADCENABLE
td(PWD)
Request for ADC
Conversion
Figure 8-18. ADC Conversion Timing
Rs
Source
Signal
ADCIN
Ron
3.4 kW
Switch
Cp
5 pF
ac
Ch
1.6 pF
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (Ron): 3.4 k W
Sampling Capacitor (Ch): 1.6 pF
Parasitic Capacitance (Cp): 5 pF
Source Resistance (Rs): 50 W
Figure 8-19. ADC Input Impedance Model
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
81
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.2.1.2.6 ADC Sequential and Simultaneous Timings
Analog Input
SOC0 Sample
Window
0
12
2
18
SOC1 Sample
Window
27 28
SOC2 Sample
Window
43
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
S/H Window Pulse to Core
SOC0
ADCRESULT0
SOC1
SOC2
Result 0 Latched
2 ADC clocks
ADCRESULT1
EOC0 Pulse
EOC0 Pulse
ADCINTFLG.ADCINTx
Minimum
10 ADC clocks
Conversion 0
13 ADC clocks
6
ADC clocks
Minimum
10 ADC clocks
1 ADC clock
Conversion 1
13 ADC clocks
Figure 8-20. Timing Example for Sequential Mode / Late Interrupt Pulse
82
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Analog Input
SOC0 Sample
Window
0
2
12
18
SOC1 Sample
Window
27 28
SOC2 Sample
Window
43
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
S/H Window Pulse to Core
SOC0
SOC1
ADCRESULT0
SOC2
Result 0 Latched
ADCRESULT1
EOC0 Pulse
EOC0 Pulse
ADCINTFLG.ADCINTx
Minimum
10 ADC clocks
Conversion 0
13 ADC clocks
6
ADC clocks
Minimum
10 ADC clocks
2 ADC clocks
Conversion 1
13 ADC clocks
Figure 8-21. Timing Example for Sequential Mode / Early Interrupt Pulse
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
83
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Analog Input A
SOC0 Sample
A Window
SOC2 Sample
A Window
SOC0 Sample
B Window
SOC2 Sample
B Window
Analog Input B
0
2
25 27
12
31
40 43
56
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
S/H Window Pulse to Core
SOC0 (A/B)
SOC2 (A/B)
2 ADC clocks
ADCRESULT0
Result 0 (A) Latched
ADCRESULT1
Result 0 (B) Latched
ADCRESULT2
EOC0 Pulse
1 ADC clock
EOC1 Pulse
EOC2 Pulse
ADCINTFLG.ADCINTx
Minimum
10 ADC clocks
Conversion 0 (A)
13 ADC clocks
19
ADC clocks
Conversion 0 (B)
13 ADC clocks
2 ADC clocks
Minimum
10 ADC clocks
Conversion 1 (A)
13 ADC clocks
Figure 8-22. Timing Example for Simultaneous Mode / Late Interrupt Pulse
84
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Analog Input A
SOC0 Sample
A Window
SOC2 Sample
A Window
SOC0 Sample
B Window
SOC2 Sample
B Window
Analog Input B
0
2
25 27
12
40
56
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
S/H Window Pulse to Core
SOC0 (A/B)
SOC2 (A/B)
2 ADC clocks
ADCRESULT0
Result 0 (A) Latched
ADCRESULT1
Result 0 (B) Latched
ADCRESULT2
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
ADCINTFLG.ADCINTx
Minimum
10 ADC clocks
Conversion 0 (A)
13 ADC clocks
19
ADC clocks
Conversion 0 (B)
13 ADC clocks
Minimum
10 ADC clocks
2 ADC clocks
Conversion 1 (A)
13 ADC clocks
Figure 8-23. Timing Example for Simultaneous Mode / Early Interrupt Pulse
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
85
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
8.9.2.2 Analog Front End
8.9.2.2.1 AFE Device-Specific Information
The AFE contains up to seven comparators with up to three integrated DACs, one VREFOUT-buffered DAC, up to
four PGAs, and up to four digital filters. Figure 8-24 and Figure 8-25 show the AFE.
The comparator output signal filtering is achieved using the digital filter present on selective input line and
qualifies the output of the COMP/DAC subsystem (see Figure 8-27). The filtered or unfiltered output of the
COMP/DAC subsystem can be configured to be an input to the Digital Compare submodule of the ePWM
peripheral.
Note
The analog inputs are brought in through the AFE subsystem rather than through an AIO Mux, which
is not present.
The ADCINSWITCH register is used to control ADC inputs dynamically, and the setting of this register is
separate from the AFE and digital filter initialization.
86
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
VREFHI
VREFOUT/A0
VREFHI
A0
_
+Cmp
RPD
COMPB7
DFSS
B7
PGA
G » 3, 6, or 11
VSSA
_
Amp
+
Buffered
DAC Output
6-bit DAC
B7
DAC5 6-bit
PFCGND
B0
A2
A4
B2
B0
A2
A4
B2
DAC1 6-bit
_
Cmp
+
A1
DFSS
PGA
G » 3, 6, or 11
M1GND
_
PGA
G » 3, 6, or 11
M1GND
+Cmp
COMPA1L
DFSS
ADCINSWITCH
COMPA3H
DFSS
_
+Cmp
COMPA3L
DFSS
A3
_
Cmp
+
B1
_
A1
+Cmp
A3
COMPA1H
PGA
G » 3, 6, or 11
COMPB1H
DFSS
_
+Cmp
COMPB1L
DFSS
B1
ADCINSWITCH
DAC2 6-bit
ADC
Temp Sensor
M1GND
A5
A5
ADCCTL1.TEMPCONV
VREFLO
VREFLO
B5
B5
ADCCTL1.REFLOCONV
A7
A7
B3
B3
ADCINSWITCH
GAIN AMP
G»3
A6
A6
M2GND
GAIN AMP
G»3
B4
B4
M2GND
GAIN AMP
G»3
B6
Legend
B6
ADCINSWITCH
M2GND
Cmp - Comparator
GAIN AMP - Fixed Gain Amplifier
DFSS - Comparator Trip/Digital Filter Subsystem Block
PGA - Programmable Gain Amplifier
Figure 8-24. 28055, 28054, 28053, 28052, and 28051 Analog Front End
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
87
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
VREFHI
VREFOUT/A0
VREFHI
A0
_
RPD
GAIN AMP
G»3
B7
Amp
+
Buffered
DAC Output
VSSA
6-bit DAC
B7
PFCGND
B0
A2
A4
B2
B0
A2
A4
B2
DAC1 6-bit
_
Cmp
+
A1
DFSS
PGA
G » 3, 6, or 11
_
+Cmp
PGA
G » 3, 6, or 11
+Cmp
COMPA1L
DFSS
ADCINSWITCH
COMPA3H
DFSS
_
+Cmp
COMPA3L
DFSS
A3
M1GND
_
Cmp
+
B1
_
A1
M1GND
A3
COMPA1H
PGA
G » 3, 6, or 11
COMPB1H
_
+Cmp
COMPB1L
DFSS
DFSS
B1
ADCINSWITCH
DAC2 6-bit
ADC
Temp Sensor
M1GND
A5
A5
ADCCTL1.TEMPCONV
VREFLO
VREFLO
B5
B5
ADCCTL1.REFLOCONV
A7
A7
B3
B3
ADCINSWITCH
GAIN AMP
G»3
A6
A6
M2GND
GAIN AMP
G»3
B4
B4
M2GND
GAIN AMP
G»3
B6
Legend
B6
ADCINSWITCH
M2GND
Cmp - Comparator
GAIN AMP - Fixed Gain Amplifier
DFSS - Comparator Trip/Digital Filter Subsystem Block
PGA - Programmable Gain Amplifier
Figure 8-25. 28050 Analog Front End
88
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
VREFHI
6-bit
DAC
+
Op Amp
_
RPD
VSSA
VSSA
Figure 8-26. VREFOUT
ePWM 1-7
COMPxINPEN
CTRIPxx0CTLREGISTER
ENABLES
COMPxxPOL
CTRIPEN
CTRIPFILCTRL
REGISTER
COMPxxH
0
1
Digital Filter
1
COMPxxPOL
CTRIPBYP
SYSCLK
COMPxxL
(to all ePWM modules)
0
D
C
T
R
I
P
S
E
L
DCAH
DCAL
DCBH
DCBL
0
CTRIPOUTBYP
1
1
0
CTRIPxxOUTEN
CTRIPOUTxxSTS
0
CTRIPOUTxxFLG
CTRIPOUTLATEN
1
GPIO
MUX
CTRIPOUTPOL
Figure 8-27. Comparator Trip/Digital Filter Subsystem
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
89
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.2.2.2 AFE Register Descriptions
Table 8-31. DAC Control Registers
ADDRESS
SIZE
(×16)
EALLOW
PROTECTE
D
DAC1CTL
0x6400
1
Yes
DAC1 Control register
DAC2CTL
0x6401
1
Yes
DAC2 Control register
DAC5CTL
0x6404
1
Yes
DAC5 Control register
VREFOUTCTL
0x6405
1
Yes
VREF Output Control Register
REGISTER NAME
DESCRIPTION
Table 8-32. DAC, PGA, Comparator, and Filter Enable Registers
ADDRESS
SIZE
(×16)
EALLOW
PROTECTE
D
DACEN
0x6410
1
Yes
DAC Enables register
VREFOUTEN
0x6411
1
Yes
VREF Out Enable Register
PGAEN
0x6412
1
Yes
Programmable Gain Amplifier Enable register
COMPEN
0x6413
1
Yes
Comparator Enable register
AMPM1_GAIN
0x6414
1
Yes
Motor Unit 1 PGA Gain Controls register
AMP_PFC_GAIN
0x6416
1
Yes
PFC PGA Gain Controls register
REGISTER NAME
DESCRIPTION
Table 8-33. SWITCH Registers
REGISTER NAME
ADCINSWITCH
Reserved
COMPHYSTCTL
ADDRESS
SIZE
(×16)
EALLOW
PROTECTE
D
0x6421
1
Yes
ADC Input-Select Switch Control register
0x6422 to
0x6428
7
Yes
Reserved
0x6429
1
Yes
Comparator Hysteresis Control register
DESCRIPTION
Table 8-34. Digital Filter and Comparator Control Registers
ADDRESS
SIZE
(×16)
EALLOW
PROTECTE
D
CTRIPA1ICTL
0x6430
1
Yes
CTRIPA1 Filter Input and Function Control register
CTRIPA1FILCTL
0x6431
1
Yes
CTRIPA1 Filter Parameters register
CTRIPA1FILCLKCTL
0x6432
1
Yes
CTRIPA1 Filter Sample Clock Control register
Reserved
0x6433
1
Yes
Reserved
CTRIPA3ICTL
0x6434
1
Yes
CTRIPA3 Filter Input and Function Control register
CTRIPA3FILCTL
0x6435
1
Yes
CTRIPA3 Filter Parameters register
CTRIPA3FILCLKCTL
0x6436
1
Yes
CTRIPA3 Filter Sample Clock Control register
Reserved
0x6437
1
Yes
Reserved
CTRIPB1ICTL
0x6438
1
Yes
CTRIPB1 Filter Input and Function Control register
CTRIPB1FILCTL
0x6439
1
Yes
CTRIPB1 Filter Parameters register
CTRIPB1FILCLKCTL
0x643A
1
Yes
CTRIPB1 Filter Sample Clock Control register
Reserved
0x643B
1
Yes
Reserved
Reserved
0x643C
1
Yes
Reserved
CTRIPM1OCTL
0x643D
1
Yes
CTRIPM1 CTRIP Filter Output Control register
CTRIPM1STS
0x643E
1
Yes
CTRIPM1 CTRIPxx Outputs Status register
0x643F
1
Yes
CTRIPM1 CTRIPxx Flag Clear register
0x6440 to
0x645F
16
Yes
Reserved
REGISTER NAME
CTRIPM1FLGCLR
Reserved
90
Submit Document Feedback
DESCRIPTION
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Table 8-34. Digital Filter and Comparator Control Registers (continued)
ADDRESS
SIZE
(×16)
EALLOW
PROTECTE
D
0x6460 to
0x646F
16
Yes
Reserved
CTRIPB7ICTL
0x6470
1
Yes
CTRIPB7 Filter Input and Function Control register
CTRIPB7FILCTL
0x6471
1
Yes
CTRIPB7 Filter Parameters register
CTRIPB7FILCLKCTL
0x6472
1
Yes
CTRIPB7 Filter Sample Clock Control register
Reserved
0x6473 to
0x647B
9
Yes
Reserved
Reserved
0x647C
1
Yes
Reserved
CTRIPPFCOCTL
0x647D
1
Yes
CTRIPPFC CTRIPxx Outputs Status register
CTRIPPFCSTS
0x647E
1
Yes
CTRIPPFC CTRIPxx Flag Clear register
CTRIPPFCFLGCLR
0x647F
1
Yes
CTRIPPFC COMP Test Control register
REGISTER NAME
Reserved
DESCRIPTION
Table 8-35. LOCK Registers
ADDRESS
SIZE
(×16)
EALLOW
PROTECTE
D
LOCKCTRIP
0x64F0
1
Yes
Lock Register for CTRIP Filters register
Reserved
0x64F1
1
Yes
Reserved
LOCKDAC
0x64F2
1
Yes
Lock Register for DACs register
Reserved
0x64F3
1
Yes
Reserved
LOCKAMPCOMP
0x64F4
1
Yes
Lock Register for Amplifiers and Comparators register
Reserved
0x64F5
1
Yes
Reserved
LOCKSWITCH
0x64F6
1
Yes
Lock Register for Switches register
REGISTER NAME
Copyright © 2022 Texas Instruments Incorporated
DESCRIPTION
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
91
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.2.2.3 PGA Electrical Data/Timing
Table 8-36. Op-Amp Linear Output and ADC Sampling Time Across Gain Settings
INTERNAL RESISTOR RATIO
EQUIVALENT GAIN FROM
INPUT TO OUTPUT
LINEAR OUTPUT RANGE
OF OP-AMP
MINIMUM
ADC SAMPLING TIME
TO ACHIEVE SETTLING
ACCURACY
10
11
0.6 V to VDDA – 0.6 V
384 ns (ACQPS = 23)
5
6
0.6 V to VDDA – 0.6 V
384 ns (ACQPS = 23)
2
3
0.6 V to VDDA – 0.6 V
384 ns (ACQPS = 23)
Table 8-37. PGA Gain Stage: DC Accuracy Across Gain Settings
INTERNAL RESISTOR RATIO
EQUIVALENT GAIN FROM
INPUT TO OUTPUT
COMPENSATED
GAIN-ERROR ACROSS
TEMPERATURE AND SUPPLY
VARIATIONS
COMPENSATED INPUT
OFFSET-ERROR ACROSS
TEMPERATURE AND SUPPLY
VARIATIONS IN mV
10
11
< ±2.5%
< ±8 mV
5
6
< ±1.5%
< ±8 mV
2
3
< ±1.0%
< ±8 mV
8.9.2.2.4 Comparator Block Electrical Data/Timing
8.9.2.2.4.1 Electrical Characteristics of the Comparator/DAC
PARAMETER
MIN
TYP
MAX
UNITS
Comparator
Comparator Input Range
Comparator response time to PWM Trip Zone (Async)
Comparator large step response time to PWM Trip Zone (Async)
VSSA – VDDA
V
65
ns
95
ns
VDDA / 26 – VDDA
V
DAC
DAC Output Range
DAC resolution
6
DAC Gain
bits
–1.5%
DAC Offset
10
Monotonic
Yes
INL
0.2
mV
LSB
8.9.2.2.5 VREFOUT Buffered DAC Electrical Data
8.9.2.2.5.1 Electrical Characteristics of VREFOUT Buffered DAC
PARAMETER
VREFOUT Programmable Range
MIN
VREFOUT resolution
MAX
56
6
VREFOUT Gain
UNITS
LSB
bits
–1.5%
VREFOUT Offset
10
Monotonic
mV
Yes
INL
±0.2
LSB
3
Load
kΩ
100
RPD
92
TYP
6
20
Submit Document Feedback
pF
kΩ
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.3 Detailed Descriptions
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as
level one-half LSB beyond the last code transition. The deviation is measured from the center of each particular
code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A
differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
Zero error is the difference between the ideal input voltage and the actual input voltage that just causes a
transition from an output code of zero to an output code of one.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The last
transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is the
deviation of the actual difference between first and last code transitions and the ideal difference between first
and last code transitions.
Signal-to-Noise Ratio + Distortion
Signal-to-noise ratio + distortion (SINAD) is the ratio of the rms value of the measured input signal to the rms
sum of all other spectral components below the Nyquist frequency, including harmonics but excluding DC. The
value for SINAD is expressed in decibels.
Effective Number of Bits
(SINAD - 1.76)
N=
6.02
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the formula
it is possible to get a measure of performance expressed as N, the effective number of bits (ENOB). Thus, the
ENOB for a device for sine wave inputs at a given input frequency can be calculated directly from its measured
SINAD.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of the first nine harmonic components to the rms
value of the measured input signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range
Spurious free dynamic range (SFDR) is the difference in dB between the rms amplitude of the input signal and
the peak spurious signal.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
93
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
8.9.4 Serial Peripheral Interface
8.9.4.1 SPI Device-Specific Information
The device includes the four-pin SPI module. The SPI is a high-speed, synchronous serial I/O port that allows a
serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmable
bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals
or another processor. Typical applications include external I/O or peripheral expansion through devices such
as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave
operation of the SPI.
The SPI module features include:
• Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin
Note
All four pins can be used as GPIO if the SPI module is not used.
•
Two operational modes: master and slave
Baud rate: 125 different programmable rates.
Baud rate =
LSPCLK
(SPIBRR + 1)
when SPIBRR = 3 to 127
LSPCLK
when SPIBRR = 0, 1, 2
4
Data word length: 1 to 16 data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
Baud rate =
•
•
•
•
•
Note
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read
as zeros. Writing to the upper byte has no effect.
94
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Enhanced feature:
• 4-level transmit/receive FIFO
• Delayed transmit control
• Bi-directional 3-wire SPI mode support
• Audio data receive support through SPISTE inversion
Figure 8-28 is a block diagram of the SPI in slave mode.
SPIFFENA
SPIFFTX.14
Receiver
Overrun Flag
RX FIFO Registers
SPISTS.7
Overrun
INT ENA
SPICTL.4
SPIRXBUF
RX FIFO _0
RX FIFO _1
-----
SPIINT
RX FIFO Interrupt
RX FIFO _3
RX Interrupt
Logic
16
SPIRXBUF
Buffer Register
SPIFFOVF
FLAG
SPIFFRX.15
To CPU
TX FIFO Registers
SPITXBUF
TX FIFO _3
SPITX
16
16
TX Interrupt
Logic
TX FIFO Interrupt
----TX FIFO _1
TX FIFO _0
SPI INT
ENA
SPI INT FLAG
SPITXBUF
Buffer Register
SPISTS.6
SPICTL.0
TRIWIRE
SPIPRI.0
16
M
M
SPIDAT
Data Register
TW
S
S
SPIDAT.15 - 0
SW1
SPISIMO
M TW
M
TW
SPISOMI
S
S
STEINV
SW2
SPIPRI.1
Talk
STEINV
SPICTL.1
SPISTE
State Control
Master/Slave
SPICCR.3 - 0
SPI Char
3
2
M
SPI Bit Rate
SW3
S
SPIBRR.6 - 0
LSPCLK
6
A.
SPICTL.2
S
0
1
5
4
3
2
1
Clock
Polarity
Clock
Phase
SPICCR.6
SPICTL.3
SPICLK
M
0
SPISTE is driven low by the master for a slave device.
Figure 8-28. SPI Module Block Diagram (Slave Mode)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
95
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.4.2 SPI Register Descriptions
The SPI port operation is configured and controlled by the registers listed in Table 8-38.
Table 8-38. SPI-A Registers
(1)
96
DESCRIPTION(1)
NAME
ADDRESS
SIZE (×16)
EALLOW PROTECTED
SPICCR
0x7040
1
No
SPI-A Configuration Control register
SPICTL
0x7041
1
No
SPI-A Operation Control register
SPISTS
0x7042
1
No
SPI-A Status register
SPIBRR
0x7044
1
No
SPI-A Baud Rate register
SPIRXEMU
0x7046
1
No
SPI-A Receive Emulation Buffer register
SPIRXBUF
0x7047
1
No
SPI-A Serial Input Buffer register
SPITXBUF
0x7048
1
No
SPI-A Serial Output Buffer register
SPIDAT
0x7049
1
No
SPI-A Serial Data register
SPIFFTX
0x704A
1
No
SPI-A FIFO Transmit register
SPIFFRX
0x704B
1
No
SPI-A FIFO Receive register
SPIFFCT
0x704C
1
No
SPI-A FIFO Control register
SPIPRI
0x704F
1
No
SPI-A Priority Control register
Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.4.3 SPI Master Mode Electrical Data/Timing
Section 8.9.4.3.1 lists the master mode timing (clock phase = 0) and Section 8.9.4.3.2 lists the master mode
timing (clock phase = 1). Figure 8-29 and Figure 8-30 show the timing waveforms.
8.9.4.3.1 SPI Master Mode External Timing (Clock Phase = 0)
1
(1)
(2)
(3)
(4)
(5)
BRR EVEN
PARAMETER(1) (2) (3) (4) (5)
NO.
tc(SPC)M
Cycle time, SPICLK
2
tw(SPC1)M
Pulse duration, SPICLK first
pulse
3
tw(SPC2)M
Pulse duration, SPICLK second
pulse
4
td(SIMO)M
Delay time, SPICLK to
SPISIMO valid
5
tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK
8
tsu(SOMI)M
Setup time, SPISOMI before
SPICLK
9
th(SOMI)M
Hold time, SPISOMI valid after
SPICLK
23
td(SPC)M
24
td(STE)M
BRR ODD
MIN
MAX
MIN
MAX
4tc(LSPCLK)
128tc(LSPCLK)
UNIT
5tc(LSPCLK)
127tc(LSPCLK)
ns
0.5tc(SPC)M – 10
0.5tc(SPC)M + 0.5tc(LSPCLK)
0.5tc(SPC)M + 10
– 10
0.5tc(SPC)M +
0.5tc(LSPCLK) + 10
ns
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M –
0.5tc(LSPCLK) + 10
ns
10
ns
10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
ns
26
26
ns
0
0
ns
Delay time, SPISTE active to
SPICLK
1.5tc(SPC)M –
3tc(SYSCLK) – 10
1.5tc(SPC)M –
3tc(SYSCLK) – 10
ns
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)M – 10
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
ns
The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
tc(LCO) = LSPCLK cycle time
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
23
24
SPISTE
Figure 8-29. SPI Master Mode External Timing (Clock Phase = 0)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
97
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.4.3.2 SPI Master Mode External Timing (Clock Phase = 1)
1
(1)
(2)
(3)
(4)
(5)
BRR EVEN
PARAMETER(1) (2) (3) (4) (5)
NO.
BRR ODD
MIN
MAX
4tc(LSPCLK)
UNIT
MIN
MAX
128tc(LSPCLK)
5tc(LSPCLK)
127tc(LSPCLK)
ns
0.5tc(SPC)M –
0.5tc(LSPCLK) + 10
ns
0.5tc(SPC)M +
0.5tc(LSPCLK) + 10
ns
tc(SPC)M
Cycle time, SPICLK
2
tw(SPC1)M
Pulse duration, SPICLK first
pulse
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M –
0.5tc(LSPCLK) – 10
3
tw(SPC2)M
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M +
0.5tc(LSPCLK) – 10
6
td(SIMO)M
Delay time, SPISIMO valid to
SPICLK
0.5tc(SPC)M – 10
0.5tc(SPC)M +
0.5tc(LSPCLK) – 10
ns
7
tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M – 10
0.5tc(SPC)M –
0.5tc(LSPCLK) – 10
ns
10
tsu(SOMI)M
Setup time, SPISOMI before
SPICLK
26
26
ns
11
th(SOMI)M
Hold time, SPISOMI valid after
SPICLK
0
0
ns
23
td(SPC)M
Delay time, SPISTE active to
SPICLK
2tc(SPC)M –
3tc(SYSCLK) – 10
2tc(SPC)M –
3tc(SYSCLK) – 10
ns
24
td(STE)M
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC) – 10
0.5tc(SPC) –
0.5tc(LSPCLK) – 10
ns
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
Master Out Data Is Valid
SPISIMO
10
11
Master In Data Must
Be Valid
SPISOMI
24
23
SPISTE
Figure 8-30. SPI Master Mode External Timing (Clock Phase = 1)
98
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.4.4 SPI Slave Mode Electrical Data/Timing
Section 8.9.4.4.1 lists the slave mode timing (clock phase = 0) and Section 8.9.4.4.2 lists the slave mode timing
(clock phase = 1). Figure 8-31 and Figure 8-32 show the timing waveforms.
8.9.4.4.1 SPI Slave Mode External Timing (Clock Phase = 0)
PARAMETER(1) (2) (3) (4) (5)
NO.
12
tc(SPC)S
Cycle time, SPICLK
13
tw(SPC1)S
14
tw(SPC2)S
15
td(SOMI)S
Delay time, SPICLK to SPISOMI valid
16
tv(SOMI)S
Valid time, SPISOMI data valid after SPICLK
19
tsu(SIMO)S
20
th(SIMO)S
25
26
(1)
(2)
(3)
(4)
(5)
MIN
MAX
UNIT
4tc(SYSCLK)
ns
Pulse duration, SPICLK first pulse
2tc(SYSCLK) – 1
ns
Pulse duration, SPICLK second pulse
2tc(SYSCLK) – 1
ns
21
ns
0
ns
Setup time, SPISIMO valid before SPICLK
1.5tc(SYSCLK)
ns
Hold time, SPISIMO data valid after SPICLK
1.5tc(SYSCLK)
ns
tsu(STE)S
Setup time, SPISTE active before SPICLK
1.5tc(SYSCLK)
ns
th(STE)S
Hold time, SPISTE inactive after SPICLK
1.5tc(SYSCLK)
ns
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
tc(LCO) = LSPCLK cycle time
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
SPISOMI
16
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
25
26
SPISTE
Figure 8-31. SPI Slave Mode External Timing (Clock Phase = 0)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
99
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.4.4.2 SPI Slave Mode External Timing (Clock Phase = 1)
PARAMETER(1) (2) (3) (4) (5)
NO.
MIN
12
tc(SPC)S
Cycle time, SPICLK
13
tw(SPC1)S
14
tw(SPC2)S
17
td(SOMI)S
Delay time, SPICLK to SPISOMI valid
18
tv(SOMI)S
Valid time, SPISOMI data valid after SPICLK
21
tsu(SIMO)S
22
th(SIMO)S
25
26
(1)
(2)
(3)
(4)
(5)
MAX
UNIT
4tc(SYSCLK)
ns
Pulse duration, SPICLK first pulse
2tc(SYSCLK) – 1
ns
Pulse duration, SPICLK second pulse
2tc(SYSCLK) – 1
ns
21
ns
0
ns
Setup time, SPISIMO valid before SPICLK
1.5tc(SYSCLK)
ns
Hold time, SPISIMO data valid after SPICLK
1.5tc(SYSCLK)
ns
tsu(STE)S
Setup time, SPISTE active before SPICLK
1.5tc(SYSCLK)
ns
th(STE)S
Hold time, SPISTE inactive after SPICLK
1.5tc(SYSCLK)
ns
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
tc(LCO) = LSPCLK cycle time
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
SPISOMI
Data Valid
SPISOMI Data Is Valid
Data Valid
18
21
22
SPISIMO Data
Must Be Valid
SPISIMO
26
25
SPISTE
Figure 8-32. SPI Slave Mode External Timing (Clock Phase = 1)
100
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
www.ti.com
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.5 Serial Communications Interface
8.9.5.1 SCI Device-Specific Information
The 2805x devices include three SCI modules (SCI-A, SCI-B, SCI-C). Each SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero
(NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and
interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data
integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is
programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
•
Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
Note
Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:
•
•
•
•
•
•
•
•
Baud rate =
LSPCLK
(BRR + 1) * 8
when BRR ¹ 0
Baud rate =
LSPCLK
16
when BRR = 0
Data-word format
– One start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– 1 or 2 stop bits
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ format
Note
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read
as zeros. Writing to the upper byte has no effect.
Enhanced features:
• Auto baud-detect hardware logic
• 4-level transmit/receive FIFO
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
101
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Figure 8-33 shows the SCI module block diagram.
TXENA
SCICTL1.1
TXSHF
Register
Frame
Format and Mode
SCITXD
8
Parity
Even/Odd
0
TXEMPTY
1
SCICCR.6
SCICTL2.6
8
Enable
TX FIFO_0
SCICCR.5
88
TX FIFO_1
TX Interrupt
Logic
TX FIFO Interrupts
TXINT
To CPU
TX FIFO_N
TXINTENA
8
0
TXWAKE
SCICTL2.0
TXRDY
1
SCICTL2.7
SCICTL1.3
SCI TX Interrupt Select Logic
8
WUT
Transmit Data
Buffer Register
SCITXBUF.7-0
Auto Baud Detect Logic
RXENA
LSPCLK
Baud Rate
MSB/LSB
Registers
SCICTL1.0
RXSHF
Register
SCIHBAUD.15-8
SCIRXD
RXWAKE
8
SCILBAUD.7-0
SCIRXST.1
0
1
8
SCIFFENA
RX FIFO_0
SCIFFTX.14
8
RX FIFO_1
RX FIFO Interrupts
RX Interrupt
Logic
RXINT
To CPU
RX FIFO_N
RXFFOVF
8
0
SCIFFRX.15
1
RXBKINTENA
SCICTL2.1
RXRDY
SCIRXST.6
RXENA
BRKDT
SCICTL1.0
RXERRINTENA
SCIRXST.5
8
SCICTL1.6
SCI RX Interrupt Select Logic
SCIRXST.5-2
Receive Data
Buffer Register
SCIRXBUF.7-0
BRKDT
FE OE PE
RXERROR
SCIRXST.7
Figure 8-33. SCI Module Block Diagram
102
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.5.2 SCI Register Descriptions
The SCI port operation is configured and controlled by the registers listed in Table 8-39, Table 8-40, and Table
8-41.
Table 8-39. SCI-A Registers
(1)
(2)
NAME(1)
ADDRESS
SIZE (×16)
EALLOW
PROTECTED
DESCRIPTION
SCICCRA
0x7050
1
No
SCI-A Communications Control register
SCICTL1A
0x7051
1
No
SCI-A Control Register 1
SCIHBAUDA
0x7052
1
No
SCI-A Baud register, high bits
SCILBAUDA
0x7053
1
No
SCI-A Baud register, low bits
SCICTL2A
0x7054
1
No
SCI-A Control Register 2
SCIRXSTA
0x7055
1
No
SCI-A Receive Status register
SCIRXEMUA
0x7056
1
No
SCI-A Receive Emulation Data Buffer register
SCIRXBUFA
0x7057
1
No
SCI-A Receive Data Buffer register
SCITXBUFA
0x7059
1
No
SCI-A Transmit Data Buffer register
SCIFFTXA(2)
0x705A
1
No
SCI-A FIFO Transmit register
SCIFFRXA(2)
0x705B
1
No
SCI-A FIFO Receive register
SCIFFCTA(2)
0x705C
1
No
SCI-A FIFO Control register
SCIPRIA
0x705F
1
No
SCI-A Priority Control register
Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. All 32-bit accesses produce
undefined results.
These registers are new registers for the FIFO mode.
Table 8-40. SCI-B Registers
(1)
(2)
NAME(1)
ADDRESS
SIZE (×16)
EALLOW
PROTECTED
DESCRIPTION
SCICCRB
0x7750
1
No
SCI-B Communications Control register
SCICTL1B
0x7751
1
No
SCI-B Control Register 1
SCIHBAUDB
0x7752
1
No
SCI-B Baud register, high bits
SCILBAUDB
0x7753
1
No
SCI-B Baud register, low bits
SCICTL2B
0x7754
1
No
SCI-B Control Register 2
SCIRXSTB
0x7755
1
No
SCI-B Receive Status register
SCIRXEMUB
0x7756
1
No
SCI-B Receive Emulation Data Buffer register
SCIRXBUFB
0x7757
1
No
SCI-B Receive Data Buffer register
SCITXBUFB
0x7759
1
No
SCI-B Transmit Data Buffer register
SCIFFTXB(2)
0x775A
1
No
SCI-B FIFO Transmit register
SCIFFRXB(2)
0x775B
1
No
SCI-B FIFO Receive register
SCIFFCTB(2)
0x775C
1
No
SCI-B FIFO Control register
SCIPRIB
0x775F
1
No
SCI-B Priority Control register
Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. All 32-bit accesses produce
undefined results.
These registers are new registers for the FIFO mode.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
103
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Table 8-41. SCI-C Registers
(1)
(2)
104
NAME(1)
ADDRESS
SIZE (×16)
EALLOW
PROTECTED
DESCRIPTION
SCICCRC
0x7770
1
No
SCI-C Communications Control register
SCICTL1C
0x7771
1
No
SCI-C Control Register 1
SCIHBAUDC
0x7772
1
No
SCI-C Baud register, high bits
SCILBAUDC
0x7773
1
No
SCI-C Baud register, low bits
SCICTL2C
0x7774
1
No
SCI-C Control Register 2
SCIRXSTC
0x7775
1
No
SCI-C Receive Status register
SCIRXEMUC
0x7776
1
No
SCI-C Receive Emulation Data Buffer register
SCIRXBUFC
0x7777
1
No
SCI-C Receive Data Buffer register
SCITXBUFC
0x7779
1
No
SCI-C Transmit Data Buffer register
SCIFFTXC(2)
0x777A
1
No
SCI-C FIFO Transmit register
SCIFFRXC(2)
0x777B
1
No
SCI-C FIFO Receive register
SCIFFCTC(2)
0x777C
1
No
SCI-C FIFO Control register
SCIPRIC
0x777F
1
No
SCI-C Priority Control register
Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. All 32-bit accesses produce
undefined results.
These registers are new registers for the FIFO mode.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
www.ti.com
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.6 Enhanced Controller Area Network
8.9.6.1 eCAN Device-Specific Information
The CAN module (eCAN-A) has the following features:
• Fully compliant with CAN protocol, version 2.0B
• Supports data rates up to 1 Mbps
• Thirty-two mailboxes, each with the following properties:
– Configurable as receive or transmit
– Configurable with standard or extended identifier
– Has a programmable receive mask
– Supports data and remote frame
– Composed of 0 to 8 bytes of data
– Uses a 32-bit timestamp on receive and transmit message
– Protects against reception of new message
– Holds the dynamically programmable priority of transmit message
– Employs a programmable interrupt scheme with two interrupt levels
– Employs a programmable alarm on transmission or reception time-out
• Low-power mode
• Programmable wakeup on bus activity
• Automatic reply to a remote request message
• Automatic retransmission of a frame in case of loss of arbitration or error
• 32-bit local network time counter synchronized by a specific message (communication in conjunction with
mailbox 16)
• Self-test mode
– Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided, thereby
eliminating the need for another node to provide the acknowledge bit.
Note
For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 4.6875 kbps.
The F2805x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and
exceptions.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
105
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
eCAN0INT
eCAN1INT
Controls Address
Data
Enhanced CAN Controller
32
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
32-Message Mailbox
of 4 ´ 32-Bit Words
32
CPU Interface,
Receive Control Unit,
Timer Management Unit
32
eCAN Memory
(512 Bytes)
Registers and
Message Objects Control
32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 8-34. eCAN Block Diagram and Interface Circuit
Table 8-42. 3.3-V eCAN Transceivers
PART NUMBER
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
VREF
OTHER
TA
SN65HVD230
3.3 V
Standby
Adjustable
Yes
–
–40°C to 85°C
SN65HVD230Q
3.3 V
Standby
Adjustable
Yes
–
–40°C to 125°C
SN65HVD231
3.3 V
Sleep
Adjustable
Yes
–
–40°C to 85°C
SN65HVD231Q
3.3 V
Sleep
Adjustable
Yes
–
–40°C to 125°C
SN65HVD232
3.3 V
None
None
None
–
–40°C to 85°C
SN65HVD232Q
3.3 V
None
None
None
–
–40°C to 125°C
SN65HVD233
3.3 V
Standby
Adjustable
None
Diagnostic Loopback
–40°C to 125°C
SN65HVD234
3.3 V
Standby and Sleep
Adjustable
None
–
–40°C to 125°C
SN65HVD235
3.3 V
Standby
Adjustable
None
Autobaud Loopback
–40°C to 125°C
None
Built-in Isolation
Low Prop Delay
Thermal Shutdown
Failsafe Operation
Dominant Time-Out
–55°C to 105°C
ISO1050
106
3–5.5 V
Submit Document Feedback
None
None
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
eCAN-A Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
Abort Acknowledge - CANAA
eCAN-A Memory (512 Bytes)
6000h
Received Message Pending - CANRMP
Control and Status Registers
603Fh
6040h
607Fh
6080h
60BFh
60C0h
60FFh
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Local Acceptance Masks (LAM)
(32 ´ 32-Bit RAM)
Global Acceptance Mask - CANGAM
Message Object Time Stamps (MOTS)
(32 ´ 32-Bit RAM)
Bit-Timing Configuration - CANBTC
Master Control - CANMC
Error and Status - CANES
Message Object Time-Out (MOTO)
(32 ´ 32-Bit RAM)
Transmit Error Counter - CANTEC
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
eCAN-A Memory RAM (512 Bytes)
6100h-6107h
Mailbox 0
6108h-610Fh
Mailbox 1
6110h-6117h
Mailbox 2
6118h-611Fh
Mailbox 3
6120h-6127h
Mailbox 4
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Time Stamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
61E0h-61E7h
Mailbox 28
61E8h-61EFh
Mailbox 29
61F0h-61F7h
Mailbox 30
61F8h-61FFh
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
61E8h-61E9h
Message Identifier - MSGID
61EAh-61EBh
Message Control - MSGCTRL
61ECh-61EDh
Message Data Low - MDL
61EEh-61EFh
Message Data High - MDH
Figure 8-35. eCAN-A Memory Map
Note
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and
mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled if the
eCAN RAM (LAM, MOTS, MOTO, and mailbox RAM) is used as general-purpose RAM.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
107
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
8.9.6.2 eCAN Register Descriptions
The CAN registers listed in Table 8-43 are used by the CPU to configure and control the CAN controller and
the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be
accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 8-43. CAN Register Map
REGISTER NAME(1)
eCAN-A
ADDRESS
SIZE (×32)
(1)
108
DESCRIPTION
CANME
0x6000
1
Mailbox enable
CANMD
0x6002
1
Mailbox direction
CANTRS
0x6004
1
Transmit request set
CANTRR
0x6006
1
Transmit request reset
CANTA
0x6008
1
Transmission acknowledge
CANAA
0x600A
1
Abort acknowledge
CANRMP
0x600C
1
Receive message pending
CANRML
0x600E
1
Receive message lost
CANRFP
0x6010
1
Remote frame pending
CANGAM
0x6012
1
Global acceptance mask
CANMC
0x6014
1
Master control
CANBTC
0x6016
1
Bit-timing configuration
CANES
0x6018
1
Error and status
CANTEC
0x601A
1
Transmit error counter
CANREC
0x601C
1
Receive error counter
CANGIF0
0x601E
1
Global interrupt flag 0
CANGIM
0x6020
1
Global interrupt mask
CANGIF1
0x6022
1
Global interrupt flag 1
CANMIM
0x6024
1
Mailbox interrupt mask
CANMIL
0x6026
1
Mailbox interrupt level
CANOPC
0x6028
1
Overwrite protection control
CANTIOC
0x602A
1
TX I/O control
CANRIOC
0x602C
1
RX I/O control
CANTSC
0x602E
1
Timestamp counter (Reserved in SCC mode)
CANTOC
0x6030
1
Time-out control (Reserved in SCC mode)
CANTOS
0x6032
1
Time-out status (Reserved in SCC mode)
These registers are mapped to Peripheral Frame 1.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
www.ti.com
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.7 Inter-Integrated Circuit
8.9.7.1 I2C Device-Specific Information
The device contains one I2C serial port. Figure 8-36 shows how the I2C peripheral module interfaces within the
device.
The I2C module has the following features:
• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
• One 4-word receive FIFO and one 4-word transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following
conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability
• Free data format mode
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
109
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
I2C Module
I2CXSR
I2CDXR
TX FIFO
FIFO Interrupt to
CPU/PIE
SDA
RX FIFO
Peripheral Bus
I2CRSR
SCL
Clock
Synchronizer
I2CDRR
Control/Status
Registers
CPU
Prescaler
Noise Filters
I2C INT
Interrupt to
CPU/PIE
Arbitrator
A.
B.
The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the
SYSCLKOUT rate.
The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power operation. Upon reset,
I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 8-36. I2C Peripheral Module Interfaces
110
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.7.2 I2C Register Descriptions
The registers in Table 8-44 configure and control the I2C port operation.
Table 8-44. I2C-A Registers
NAME
ADDRESS
EALLOW
PROTECTED
I2COAR
0x7900
No
I2C own address register
I2CIER
0x7901
No
I2C interrupt enable register
I2CSTR
0x7902
No
I2C status register
DESCRIPTION
I2CCLKL
0x7903
No
I2C clock low-time divider register
I2CCLKH
0x7904
No
I2C clock high-time divider register
I2CCNT
0x7905
No
I2C data count register
I2CDRR
0x7906
No
I2C data receive register
I2CSAR
0x7907
No
I2C slave address register
I2CDXR
0x7908
No
I2C data transmit register
I2CMDR
0x7909
No
I2C mode register
I2CISRC
0x790A
No
I2C interrupt source register
I2CPSC
0x790C
No
I2C prescaler register
I2CFFTX
0x7920
No
I2C FIFO transmit register
I2CFFRX
0x7921
No
I2C FIFO receive register
I2CRSR
–
No
I2C receive shift register (not accessible to the CPU)
I2CXSR
–
No
I2C transmit shift register (not accessible to the CPU)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
111
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.7.3 I2C Electrical Data/Timing
Section 8.9.7.3.1 shows the I2C timing requirements. Section 8.9.7.3.2 shows the I2C switching characteristics.
8.9.7.3.1 I2C Timing Requirements
MIN
MAX
UNIT
th(SDA-SCL)START
Hold time, START condition, SCL fall delay
after SDA fall
0.6
µs
tsu(SCL-SDA)START
Setup time, Repeated START, SCL rise
before SDA fall delay
0.6
µs
th(SCL-DAT)
Hold time, data after SCL fall
0
µs
tsu(DAT-SCL)
Setup time, data before SCL rise
tr(SDA)
Rise time, SDA
Input tolerance
20
300
ns
tr(SCL)
Rise time, SCL
Input tolerance
20
300
ns
tf(SDA)
Fall time, SDA
Input tolerance
11.4
300
ns
tf(SCL)
Fall time, SCL
Input tolerance
11.4
300
ns
tsu(SCL-SDA)STOP
Setup time, STOP condition, SCL rise before
SDA rise delay
100
ns
0.6
µs
8.9.7.3.2 I2C Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
UNIT
400
kHz
SCL clock frequency
Vil
Low level input voltage
Vih
High level input voltage
Vhys
Input hysteresis
Vol
Low level output voltage
3 mA sink current
tLOW
Low period of SCL clock
I2C clock module frequency is from 7 MHz to
12 MHz and I2C prescaler and clock divider
registers are configured appropriately.
1.3
μs
tHIGH
High period of SCL clock
I2C clock module frequency is from 7 MHz to
12 MHz and I2C prescaler and clock divider
registers are configured appropriately.
0.6
μs
lI
Input current with an input voltage from
0.1 VDDIO to 0.9 VDDIO MAX
112
Submit Document Feedback
I2C clock module frequency is from 7 MHz to
12 MHz and I2C prescaler and clock divider
registers are configured appropriately.
MAX
fSCL
0.3 VDDIO
0.7 VDDIO
V
0.05 VDDIO
0
–10
V
V
0.4
10
V
μA
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.8 Enhanced Pulse Width Modulator
8.9.8.1 ePWM Device-Specific Information
The devices contain up to seven enhanced PWM modules (ePWM1 to ePWM7). Figure 8-37 shows a block
diagram of multiple ePWM modules. Figure 8-38 shows the signal interconnections with the ePWM. For more
details, see the Enhanced Pulse Width Modulator (ePWM) Module chapter of the TMS320x2805x Real-Time
Microcontrollers Technical Reference Manual.
EPWMSYNCI
EPWM1SYNCI
EPWM1B
EPWM1TZINT
EPWM1
Module
EPWM1INT
EPWM2TZINT
PIE
TZ1 to TZ3
TZ4
EPWM2INT
TZ5
EPWMxTZINT
TZ6
EPWMxINT
EQEP1ERR
CLOCKFAIL
EMUSTOP
EPWM1ENCLK
TBCLKSYNC
eCAPI
EPWM1SYNCO
EPWM1SYNCO
EPWM2SYNCI
CTRIP
Output
Subsystem
TZ1 to TZ3
EPWM2B
EPWM2
Module
CTRIPxx
TZ4
TZ5
TZ6
EQEP1ERR
EPWM1A
CLOCKFAIL
EPWM2A
EMUSTOP
EPWM2ENCLK
EPWMxA
TBCLKSYNC
G
P
I
O
Peripheral Bus
EPWM2SYNCO
SOCA1
ADC
SOCB1
SOCA2
M
U
X
EPWMxB
EPWMxSYNCI
SOCB2
SOCAx
TZ1 to TZ3
EPWMx
Module
SOCBx
TZ4
TZ5
TZ6
EQEP1ERR
EQEP1ERR
CLOCKFAIL
EMUSTOP
eQEP1
EPWMxENCLK
TBCLKSYNC
System Control
C28x CPU
SOCA1
SOCA2
SPCAx
Pulse Stretch
(32 SYSCLKOUT Cycles, Active-Low Output)
ADCSOCAO
SOCB1
SOCB2
SPCBx
Pulse Stretch
(32 SYSCLKOUT Cycles, Active-Low Output)
ADCSOCBO
Copyright © 2017, Texas Instruments Incorporated
Figure 8-37. ePWM
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
113
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Time-Base (TB)
CTR=ZERO
TBPRD Shadow (24)
Sync
In/Out
Select
Mux
CTR=CMPB
Disabled
TBPRD Active (24)
EPWMxSYNCO
CTR=PRD
TBCTL[SYNCOSEL]
TBCTL[PHSEN]
Counter
Up/Down
(16 Bit)
TBCTL[SWFSYNC]
(Software Forced
Sync)
CTR=ZERO
TCBNT
Active (16)
CTR_Dir
CTR=PRD
CTR=ZERO
CTR=PRD or ZERO
CTR=CMPA
16
TBPHS Active (24)
Phase
Control
CTR=CMPB
CTR_Dir
DCAEVT1.soc
DCBEVT1.soc
CTR=CMPA
EPWMxSYNCI
DCAEVT1.sync
DCBEVT1.sync
(A)
EPWMxINT
Event
Trigger
and
Interrupt
(ET)
EPWMxSOCA
EPWMxSOCB
EPWMxSOCA
ADC
(A)
EPWMxSOCB
Action
Qualifier
(AQ)
16
CMPA Active (24)
CMPA Shadow (24)
Dead
Band
(DB)
CTR=CMPB
16
EPWMxA
EPWMA
PWM
Chopper
(PC)
Trip
Zone
(TZ)
EPWMxB
EPWMB
EPWMxTZINT
CMPB Active (16)
TZ1 to TZ3
CMPB Shadow (16)
CTR=ZERO
DCAEVT1.inter
DCBEVT1.inter
DCAEVT2.inter
DCBEVT2.inter
EMUSTOP
CLOCKFAIL
EQEP1ERR
DCAEVT1.force
DCAEVT2.force
DCBEVT1.force
DCBEVT2.force
(A)
(A)
(A)
(A)
Copyright © 2017, Texas Instruments Incorporated
A.
These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the COMPxOUT and TZ
signals.
Figure 8-38. ePWM Submodules Showing Critical Internal Signal Interconnections
114
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.8.2 ePWM Register Descriptions
Table 8-45 and Table 8-46 show the complete ePWM register set per module.
Table 8-45. ePWM1–ePWM4 Control and Status Registers
ePWM1
ePWM2
ePWM3
ePWM4
SIZE (×16) /
#SHADOW
TBCTL
0x6800
0x6840
0x6880
0x68C0
1/0
Time Base Control register
TBSTS
0x6801
0x6841
0x6881
0x68C1
1/0
Time Base Status register
Reserved
0x6802
0x6842
0x6882
0x68C2
1/0
Reserved
TBPHS
0x6803
0x6843
0x6883
0x68C3
1/0
Time Base Phase register
TBCTR
0x6804
0x6844
0x6884
0x68C4
1/0
Time Base Counter register
TBPRD
0x6805
0x6845
0x6885
0x68C5
1/1
Time Base Period Register Set
Reserved
0x6806
0x6846
0x6886
0x68C6
1/1
Reserved
CMPCTL
0x6807
0x6847
0x6887
0x68C7
1/0
Counter Compare Control register
Reserved
0x6808
0x6848
0x6888
0x68C8
1/1
Reserved
NAME
DESCRIPTION
CMPA
0x6809
0x6849
0x6889
0x68C9
1/1
Counter Compare A Register Set
CMPB
0x680A
0x684A
0x688A
0x68CA
1/1
Counter Compare B Register Set
AQCTLA
0x680B
0x684B
0x688B
0x68CB
1/0
Action Qualifier Control register for output A
AQCTLB
0x680C
0x684C
0x688C
0x68CC
1/0
Action Qualifier Control register for output B
AQSFRC
0x680D
0x684D
0x688D
0x68CD
1/0
Action Qualifier Software Force register
AQCSFRC
0x680E
0x684E
0x688E
0x68CE
1/1
Action Qualifier Continuous S/W Force Register Set
DBCTL
0x680F
0x684F
0x688F
0x68CF
1/1
Dead-Band Generator Control register
DBRED
0x6810
0x6850
0x6890
0x68D0
1/0
Dead-Band Generator Rising Edge Delay Count register
DBFED
0x6811
0x6851
0x6891
0x68D1
1/0
Dead-Band Generator Falling Edge Delay Count register
TZSEL
0x6812
0x6852
0x6892
0x68D2
1/0
Trip Zone Select register(1)
TZDCSEL
0x6813
0x6853
0x6893
0x98D3
1/0
Trip Zone Digital Compare register
TZCTL
0x6814
0x6854
0x6894
0x68D4
1/0
Trip Zone Control register(1)
TZEINT
0x6815
0x6855
0x6895
0x68D5
1/0
Trip Zone Enable Interrupt register(1)
TZFLG
0x6816
0x6856
0x6896
0x68D6
1/0
Trip Zone Flag register (1)
TZCLR
0x6817
0x6857
0x6897
0x68D7
1/0
Trip Zone Clear register(1)
TZFRC
0x6818
0x6858
0x6898
0x68D8
1/0
Trip Zone Force register(1)
ETSEL
0x6819
0x6859
0x6899
0x68D9
1/0
Event Trigger Selection register
ETPS
0x681A
0x685A
0x689A
0x68DA
1/0
Event Trigger Prescale register
ETFLG
0x681B
0x685B
0x689B
0x68DB
1/0
Event Trigger Flag register
ETCLR
0x681C
0x685C
0x689C
0x68DC
1/0
Event Trigger Clear register
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053 TMS320F28052 TMS320F28052M TMS320F28052F
TMS320F28051 TMS320F28050
115
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Table 8-45. ePWM1–ePWM4 Control and Status Registers (continued)
ePWM1
ePWM2
ePWM3
ePWM4
SIZE (×16) /
#SHADOW
ETFRC
0x681D
0x685D
0x689D
0x68DD
1/0
Event Trigger Force register
PCCTL
0x681E
0x685E
0x689E
0x68DE
1/0
PWM Chopper Control register
Reserved
0x6820
0x6860
0x68A0
0x68E0
1/0
Reserved
Reserved
0x6821
-
-
-
1/0
Reserved
Reserved
0x6826
-
-
-
1/0
Reserved
Reserved
0x6828
0x6868
0x68A8
0x68E8
1/0
Reserved
NAME
W(2)
Reserved
0x682A
0x686A
0x68AA
0x68EA
1/
TBPRDM
0x682B
0x686B
0x68AB
0x68EB
1 / W(2)
W(2)
DESCRIPTION
Reserved
Time Base Period Register Mirror
Reserved
0x682C
0x686C
0x68AC
0x68EC
1/
CMPAM
0x682D
0x686D
0x68AD
0x68ED
1 / W(2)
DCTRIPSEL
0x6830
0x6870
0x68B0
0x68F0
1/0
Digital Compare Trip Select register (1)
DCACTL
0x6831
0x6871
0x68B1
0x68F1
1/0
Digital Compare A Control register(1)
DCBCTL
0x6832
0x6872
0x68B2
0x68F2
1/0
Digital Compare B Control register(1)
DCFCTL
0x6833
0x6873
0x68B3
0x68F3
1/0
Digital Compare Filter Control register(1)
DCCAPCT
0x6834
0x6874
0x68B4
0x68F4
1/0
Digital Compare Capture Control register(1)
DCFOFFSET
0x6835
0x6875
0x68B5
0x68F5
1/1
Digital Compare Filter Offset register
DCFOFFSETCNT
0x6836
0x6876
0x68B6
0x68F6
1/0
Digital Compare Filter Offset Counter register
DCFWINDOW
0x6837
0x6877
0x68B7
0x68F7
1/0
Digital Compare Filter Window register
DCFWINDOWCNT
0x6838
0x6878
0x68B8
0x68F8
1/0
Digital Compare Filter Window Counter register
DCCAP
0x6839
0x6879
0x68B9
0x68F9
1/1
Digital Compare Counter Capture register
(1)
(2)
Reserved
Compare A Register Mirror
Registers that are EALLOW protected.
W = Write to shadow register
Table 8-46. ePWM5–ePWM7 Control and Status Registers
ePWM5
ePWM6
ePWM7
SIZE (×16) /
#SHADOW
TBCTL
0x6900
0x6940
0x6980
1/0
Time Base Control register
TBSTS
0x6901
0x6941
0x6981
1/0
Time Base Status register
Reserved
0x6902
0x6942
0x6982
1/0
Reserved
TBPHS
0x6903
0x6943
0x6983
1/0
Time Base Phase register
TBCTR
0x6904
0x6944
0x6984
1/0
Time Base Counter register
TBPRD
0x6905
0x6945
0x6985
1/1
Time Base Period Register Set
Reserved
0x6906
0x6946
0x6986
1/1
Reserved
NAME
116
Submit Document Feedback
DESCRIPTION
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053 TMS320F28052 TMS320F28052M TMS320F28052F
TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Table 8-46. ePWM5–ePWM7 Control and Status Registers (continued)
ePWM5
ePWM6
ePWM7
SIZE (×16) /
#SHADOW
CMPCTL
0x6907
0x6947
0x6987
1/0
Counter Compare Control register
Reserved
0x6908
0x6948
0x6988
1/1
Reserved
NAME
DESCRIPTION
CMPA
0x6909
0x6949
0x6989
1/1
Counter Compare A Register Set
CMPB
0x690A
0x694A
0x698A
1/1
Counter Compare B Register Set
AQCTLA
0x690B
0x694B
0x698B
1/0
Action Qualifier Control register for output A
AQCTLB
0x690C
0x694C
0x698C
1/0
Action Qualifier Control register for output B
AQSFRC
0x690D
0x694D
0x698D
1/0
Action Qualifier Software Force register
AQCSFRC
0x690E
0x694E
0x698E
1/1
Action Qualifier Continuous S/W Force Register Set
DBCTL
0x690F
0x694F
0x698F
1/1
Dead-Band Generator Control register
DBRED
0x6910
0x6950
0x6990
1/0
Dead-Band Generator Rising Edge Delay Count register
DBFED
0x6911
0x6951
0x6991
1/0
Dead-Band Generator Falling Edge Delay Count register
TZSEL
0x6912
0x6952
0x6992
1/0
Trip Zone Select register(1)
TZDCSEL
0x6913
0x6953
0x6993
1/0
Trip Zone Digital Compare register
TZCTL
0x6914
0x6954
0x6994
1/0
Trip Zone Control register(1)
TZEINT
0x6915
0x6955
0x6995
1/0
Trip Zone Enable Interrupt register(1)
TZFLG
0x6916
0x6956
0x6996
1/0
Trip Zone Flag register (1)
TZCLR
0x6917
0x6957
0x6997
1/0
Trip Zone Clear register(1)
TZFRC
0x6918
0x6958
0x6998
1/0
Trip Zone Force register(1)
ETSEL
0x6919
0x6959
0x6999
1/0
Event Trigger Selection register
ETPS
0x691A
0x695A
0x699A
1/0
Event Trigger Prescale register
ETFLG
0x691B
0x695B
0x699B
1/0
Event Trigger Flag register
ETCLR
0x691C
0x695C
0x699C
1/0
Event Trigger Clear register
ETFRC
0x691D
0x695D
0x699D
1/0
Event Trigger Force register
PCCTL
0x691E
0x695E
0x699E
1/0
PWM Chopper Control register
Reserved
0x6920
0x6960
0x69A0
1/0
Reserved
Reserved
-
-
-
1/0
Reserved
Reserved
-
-
-
1/0
Reserved
Reserved
0x6928
0x6968
0x69A8
1/0
Reserved
Reserved
0x692A
0x696A
0x69AA
1 / W(2)
Reserved
W(2)
TBPRDM
0x692B
0x696B
0x69AB
1/
Reserved
0x692C
0x696C
0x69AC
1 / W(2)
0x69AD
W(2)
CMPAM
0x692D
Copyright © 2022 Texas Instruments Incorporated
0x696D
1/
Time Base Period Register Mirror
Reserved
Compare A Register Mirror
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053 TMS320F28052 TMS320F28052M TMS320F28052F
TMS320F28051 TMS320F28050
117
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Table 8-46. ePWM5–ePWM7 Control and Status Registers (continued)
ePWM5
ePWM6
ePWM7
SIZE (×16) /
#SHADOW
DCTRIPSEL
0x6930
0x6970
0x69B0
1/0
Digital Compare Trip Select register (1)
DCACTL
0x6931
0x6971
0x69B1
1/0
Digital Compare A Control register(1)
DCBCTL
0x6932
0x6972
0x69B2
1/0
Digital Compare B Control register(1)
DCFCTL
0x6933
0x6973
0x69B3
1/0
Digital Compare Filter Control register(1)
DCCAPCT
0x6934
0x6974
0x69B4
1/0
Digital Compare Capture Control register(1)
DCFOFFSET
0x6935
0x6975
0x69B5
1/1
Digital Compare Filter Offset register
DCFOFFSETCNT
0x6936
0x6976
0x69B6
1/0
Digital Compare Filter Offset Counter register
DCFWINDOW
0x6937
0x6977
0x69B7
1/0
Digital Compare Filter Window register
DCFWINDOWCNT
0x6938
0x6978
0x69B8
1/0
Digital Compare Filter Window Counter register
DCCAP
0x6939
0x6979
0x69B9
1/1
Digital Compare Counter Capture register
NAME
(1)
(2)
118
DESCRIPTION
Registers that are EALLOW protected.
W = Write to shadow register
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053 TMS320F28052 TMS320F28052M TMS320F28052F
TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.8.3 ePWM Electrical Data/Timing
PWM refers to PWM outputs on ePWM1 to ePWM7. Section 8.9.8.3.1 shows the PWM timing requirements and
Section 8.9.8.3.2, switching characteristics.
8.9.8.3.1 ePWM Timing Requirements
MIN
Asynchronous
tw(SYCIN) (1)
Sync input pulse width
(1)
UNIT
cycles
2tc(SCO)
cycles
1tc(SCO) + tw(IQSW)
cycles
Synchronous
With input qualifier
MAX
2tc(SCO)
For an explanation of the input qualifier parameters, see Section 8.9.12.3.2.1.
8.9.8.3.2 ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
tw(PWM)
Pulse duration, PWMx output high/low
tw(SYNCOUT)
Sync output pulse width
td(PWM)tza
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
TEST CONDITIONS
MIN
MAX
33.33
UNIT
ns
8tc(SCO)
cycles
no pin load
25
ns
20
ns
MAX
UNIT
8.9.8.3.3 Trip-Zone Input Timing
8.9.8.3.3.1 Trip-Zone Input Timing Requirements
MIN
tw(TZ) (1)
Pulse duration, TZx input low
Asynchronous
2tc(TBCLK)
cycles
Synchronous
2tc(TBCLK)
cycles
2tc(TBCLK) + tw(IQSW)
cycles
With input qualifier
(1)
For an explanation of the input qualifier parameters, see Section 8.9.12.3.2.1.
SYSCLK
t w(TZ)
(A)
TZ
t d(TZ-PWM)HZ
(B)
PWM
A.
B.
TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery
software.
Figure 8-39. PWM Hi-Z Characteristics
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
119
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.9 Enhanced Capture Module
8.9.9.1 eCAP Module Device-Specific Information
SYNC
The device contains an enhanced capture module (eCAP1). Figure 8-40 shows a functional block diagram of a
module.
SYNCIn
CTRPHS
(phase register−32 bit)
SYNCOut
TSCTR
(counter−32 bit)
APWM mode
OVF
RST
CTR_OVF
Delta−mode
CTR [0−31]
PRD [0−31]
CMP [0−31]
PWM
compare
logic
32
CTR=PRD
CTR [0−31]
CTR=CMP
32
32
CAP1
(APRD active)
APRD
shadow
32
LD
LD1
MODE SELECT
PRD [0−31]
Polarity
select
32
CMP [0−31]
32
CAP2
(ACMP active)
32
LD
LD2
Polarity
select
Event
qualifier
ACMP
shadow
32
CAP3
(APRD shadow)
LD
32
CAP4
(ACMP shadow)
LD
eCAPx
Event
Prescale
Polarity
select
LD3
LD4
Polarity
select
4
Capture events
4
CEVT[1:4]
to PIE
Interrupt
Trigger
and
Flag
control
CTR_OVF
Continuous /
Oneshot
Capture Control
CTR=PRD
CTR=CMP
Copyright © 2017, Texas Instruments Incorporated
Figure 8-40. eCAP Functional Block Diagram
120
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
The eCAP module is clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for low
power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
8.9.9.2 eCAP Module Register Descriptions
Table 8-47 shows the eCAP Control and Status Registers.
Table 8-47. eCAP Control and Status Registers
NAME
eCAP1
SIZE (×16)
TSCTR
0x6A00
2
EALLOW PROTECTED
Timestamp Counter
DESCRIPTION
CTRPHS
0x6A02
2
Counter Phase Offset Value register
CAP1
0x6A04
2
Capture 1 register
CAP2
0x6A06
2
Capture 2 register
CAP3
0x6A08
2
Capture 3 register
CAP4
0x6A0A
2
Capture 4 register
Reserved
0x6A0C to 0x6A12
8
Reserved
ECCTL1
0x6A14
1
Capture Control Register 1
ECCTL2
0x6A15
1
Capture Control Register 2
ECEINT
0x6A16
1
Capture Interrupt Enable register
ECFLG
0x6A17
1
Capture Interrupt Flag register
ECCLR
0x6A18
1
Capture Interrupt Clear register
ECFRC
0x6A19
1
Capture Interrupt Force register
Reserved
0x6A1A to 0x6A1F
6
Reserved
8.9.9.3 eCAP Module Electrical Data/Timing
Section 8.9.9.3.1 provides the eCAP timing requirement and Section 8.9.9.3.2 provides the eCAP switching
characteristics.
8.9.9.3.1 eCAP Timing Requirement
MIN
tw(CAP) (1)
Capture input pulse width
UNIT
Asynchronous
2tc(SCO)
cycles
Synchronous
2tc(SCO)
cycles
1tc(SCO) + tw(IQSW)
cycles
With input qualifier
(1)
MAX
For an explanation of the input qualifier parameters, see Section 8.9.12.3.2.1.
8.9.9.3.2 eCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
tw(APWM)
Pulse duration, APWMx output high/low
Copyright © 2022 Texas Instruments Incorporated
MIN
MAX
20
UNIT
ns
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
121
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.10 Enhanced Quadrature Encoder Pulse
8.9.10.1 eQEP Device-Specific Information
The device contains one eQEP module. Figure 8-41 shows the eQEP functional block diagram.
System Control
Registers
To CPU
EQEPxENCLK
Data Bus
SYSCLKOUT
QCPRD
QCAPCTL
QCTMR
16
16
16
Quadrature
Capture
Unit
(QCAP)
QCTMRLAT
QCPRDLAT
Registers
Used by
Multiple Units
QUTMR
QWDTMR
QUPRD
QWDPRD
32
16
QEPCTL
QEPSTS
UTIME
QFLG
UTOUT
QWDOG
QDECCTL
16
WDTOUT
PIE
EQEPxAIN
QCLK
EQEPxINT
16
QPOSLAT
EQEPxIIN
QI
Position Counter/
Control Unit
(PCCU)
EQEPxB/XDIR
EQEPxIOUT
QS Quadrature
Decoder
PHE
(QDU)
PCSOUT
QPOSSLAT
EQEPxA/XCLK
EQEPxBIN
QDIR
EQEPxIOE
GPIO
MUX
EQEPxSIN
EQEPxSOUT
QPOSILAT
EQEPxSOE
32
QPOSCNT
32
QPOSCMP
EQEPxI
EQEPxS
16
QEINT
QPOSINIT
QFRC
QPOSMAX
QCLR
QPOSCTL
eQEP Peripheral
Copyright © 2017, Texas Instruments Incorporated
Figure 8-41. eQEP Functional Block Diagram
122
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.10.2 eQEP Register Descriptions
Table 8-48 lists the eQEP Control and Status Registers.
Table 8-48. eQEP Control and Status Registers
eQEP1
ADDRESS
eQEP1
SIZE(×16)/
#SHADOW
QPOSCNT
0x6B00
2/0
eQEP Position Counter
QPOSINIT
0x6B02
2/0
eQEP Initialization Position Count
QPOSMAX
0x6B04
2/0
eQEP Maximum Position Count
QPOSCMP
0x6B06
2/1
eQEP Position-compare
QPOSILAT
0x6B08
2/0
eQEP Index Position Latch
QPOSSLAT
0x6B0A
2/0
eQEP Strobe Position Latch
QPOSLAT
0x6B0C
2/0
eQEP Position Latch
QUTMR
0x6B0E
2/0
eQEP Unit Timer
QUPRD
0x6B10
2/0
eQEP Unit Period register
QWDTMR
0x6B12
1/0
eQEP Watchdog Timer
QWDPRD
0x6B13
1/0
eQEP Watchdog Period register
QDECCTL
0x6B14
1/0
eQEP Decoder Control register
QEPCTL
0x6B15
1/0
eQEP Control register
QCAPCTL
0x6B16
1/0
eQEP Capture Control register
QPOSCTL
0x6B17
1/0
eQEP Position-compare Control register
QEINT
0x6B18
1/0
eQEP Interrupt Enable register
QFLG
0x6B19
1/0
eQEP Interrupt Flag register
QCLR
0x6B1A
1/0
eQEP Interrupt Clear register
QFRC
0x6B1B
1/0
eQEP Interrupt Force register
QEPSTS
0x6B1C
1/0
eQEP Status register
QCTMR
0x6B1D
1/0
eQEP Capture Timer
QCPRD
0x6B1E
1/0
eQEP Capture Period register
QCTMRLAT
0x6B1F
1/0
eQEP Capture Timer Latch
QCPRDLAT
0x6B20
1/0
eQEP Capture Period Latch
0x6B21 to
0x6B3F
31/0
NAME
Reserved
Copyright © 2022 Texas Instruments Incorporated
REGISTER DESCRIPTION
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
123
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.10.3 eQEP Electrical Data/Timing
Section 8.9.10.3.1 provides the eQEP timing requirement and Section 8.9.10.3.2 provides the eQEP switching
characteristics.
8.9.10.3.1 eQEP Timing Requirements
TEST CONDITIONS
tw(QEPP)
With input qualifier(2)
tw(INDEXH)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
cycles
2tc(SCO)
cycles
2tc(SCO) +tw(IQSW)
cycles
2tc(SCO)
cycles
2tc(SCO) + tw(IQSW)
cycles
2tc(SCO)
qualifier(2)
cycles
2tc(SCO) + tw(IQSW)
cycles
2tc(SCO)
cycles
2tc(SCO) +tw(IQSW)
cycles
Asynchronous(1)/Synchronous
With input
(1)
(2)
2[1tc(SCO) + tw(IQSW)]
Asynchronous(1)/Synchronous
With input
tw(STROBL)
qualifier(2)
qualifier(2)
UNIT
cycles
Asynchronous(1)/Synchronous
With input
tw(STROBH)
qualifier(2)
MAX
2tc(SCO)
Asynchronous(1)/Synchronous
With input
tw(INDEXL)
MIN
Asynchronous(1)/Synchronous
QEP input period
See the TMS320F2805x Real-Time MCUs Silicon Errata for limitations in the asynchronous mode.
For an explanation of the input qualifier parameters, see Section 8.9.12.3.2.1.
8.9.10.3.2 eQEP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
MAX
UNIT
td(CNTR)xin
Delay time, external clock to counter increment
PARAMETER
4tc(SCO)
cycles
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync output
6tc(SCO)
cycles
124
Submit Document Feedback
MIN
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.11 JTAG Port
8.9.11.1 JTAG Port Device-Specific Information
On the 2805x device, the JTAG port is reduced to 5 pins ( TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS
and TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the pins
in Figure 8-42. During emulation/debug, the GPIO function of these pins are not available. If the GPIO38/TCK/
XCLKIN pin is used to provide an external clock, an alternate clock source should be used to clock the device
during emulation/debug because this pin will be needed for the TCK function.
Note
In 2805x devices, the JTAG pins may also be used as GPIO pins. Care should be taken in the board
design to ensure that the circuitry connected to these pins do not affect the emulation capabilities of
the JTAG pin function. Any circuitry connected to these pins should not prevent the JTAG debug probe
from driving (or being driven by) the JTAG pins for successful debug.
TRST = 0: JTAG Disabled (GPIO Mode)
TRST = 1: JTAG Mode
TRST
TRST
XCLKIN
GPIO38_in
TCK
TCK/GPIO38
GPIO38_out
C28x
Core
GPIO37_in
TDO/GPIO37
1
0
TDO
GPIO37_out
GPIO36_in
1
TMS/GPIO36
GPIO36_out
1
TMS
0
GPIO35_in
1
TDI/GPIO35
GPIO35_out
1
TDI
0
Figure 8-42. JTAG/GPIO Multiplexing
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
125
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.12 General-Purpose Input/Output
8.9.12.1 GPIO Device-Specific Information
The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to
providing individual pin bit-banging I/O capability.
Table 8-49. GPIOA MUX
DEFAULT AT RESET
PRIMARY I/O
FUNCTION
PERIPHERAL
SELECTION 1(1) (2)
PERIPHERAL
SELECTION 2(1) (2)
PERIPHERAL
SELECTION 3(1) (2)
GPAMUX1 REGISTER
BITS
(GPAMUX1 BITS = 00)
(GPAMUX1 BITS = 01)
(GPAMUX1 BITS = 10)
(GPAMUX1 BITS = 11)
1:0
GPIO0
EPWM1A (O)
Reserved
Reserved
3:2
GPIO1
EPWM1B (O)
Reserved
CTRIPM1OUT (O)
5:4
GPIO2
EPWM2A (O)
Reserved
Reserved
7:6
GPIO3
EPWM2B (O)
SPISOMIA (I/O)
Reserved
9:8
GPIO4
EPWM3A (O)
Reserved
Reserved
126
11:10
GPIO5
EPWM3B (O)
SPISIMOA (I/O)
ECAP1 (I/O)
13:12
GPIO6
EPWM4A (O)
EPWMSYNCI (I)
EPWMSYNCO (O)
15:14
GPIO7
EPWM4B (O)
SCIRXDA (I)
Reserved
17:16
GPIO8
EPWM5A (O)
Reserved
ADCSOCAO (O)
19:18
GPIO9
EPWM5B (O)
SCITXDB (O)
Reserved
21:20
GPIO10
EPWM6A (O)
Reserved
ADCSOCBO (O)
23:22
GPIO11
EPWM6B (O)
SCIRXDB (I)
Reserved
25:24
GPIO12
TZ1 (I)/
CTRIPM1OUT (O)
SCITXDA (O)
Reserved
27:26
GPIO13
TZ2 (I)
Reserved
Reserved
29:28
GPIO14
TZ3 (I)/
CTRIPPFCOUT (O)
SCITXDB (O)
Reserved
31:30
GPIO15
TZ1 (I)/
CTRIPM1OUT (O)
SCIRXDB (I)
Reserved
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Table 8-49. GPIOA MUX (continued)
DEFAULT AT RESET
PRIMARY I/O
FUNCTION
PERIPHERAL
SELECTION 1(1) (2)
PERIPHERAL
SELECTION 2(1) (2)
PERIPHERAL
SELECTION 3(1) (2)
GPAMUX2 REGISTER
BITS
(GPAMUX2 BITS = 00)
(GPAMUX2 BITS = 01)
(GPAMUX2 BITS = 10)
(GPAMUX2 BITS = 11)
1:0
GPIO16
SPISIMOA (I/O)
EQEP1S (I/O)
TZ2 (I)
3:2
GPIO17
SPISOMIA (I/O)
EQEP1I (I/O)
TZ3 (I)/
CTRIPPFCOUT (O)
5:4
GPIO18
SPICLKA (I/O)
SCITXDB (O)
XCLKOUT (O/Z)
7:6
GPIO19/XCLKIN
SPISTEA (I/O)
SCIRXDB (I)
ECAP1 (I/O)
9:8
GPIO20
EQEP1A (I)
EPWM7A (O)
CTRIPM1OUT (O)
(1)
(2)
11:10
GPIO21
EQEP1B (I)
EPWM7B (O)
Reserved
13:12
GPIO22
EQEP1S (I/O)
Reserved
SCITXDB (O)
15:14
GPIO23
EQEP1I (I/O)
Reserved
SCIRXDB (I)
17:16
GPIO24
ECAP1 (I/O)
EPWM7A (O)
Reserved
19:18
GPIO25
Reserved
Reserved
Reserved
21:20
GPIO26
Reserved
SCIRXDC (I)
Reserved
23:22
GPIO27
Reserved
SCITXDC (O)
Reserved
25:24
GPIO28
SCIRXDA (I)
SDAA (I/OD)
TZ2 (I)
27:26
GPIO29
SCITXDA (O)
SCLA (I/OD)
TZ3 (I)/
CTRIPPFCOUT (O)
29:28
GPIO30
CANRXA (I)
SCIRXDB (I)
EPWM7A (O)
31:30
GPIO31
CANTXA (O)
SCITXDB (O)
EPWM7B (O)
The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. If the Reserved GPxMUX1/2
register setting is selected, the state of the pin will be undefined and the pin may be driven. This selection is a reserved configuration
for future expansion.
I = Input, O = Output, Z = High Impedance, OD = Open Drain
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
127
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Table 8-50. GPIOB MUX
DEFAULT AT RESET
PRIMARY I/O FUNCTION
PERIPHERAL
SELECTION 1(1)
PERIPHERAL
SELECTION 2(1)
PERIPHERAL
SELECTION 3(1)
GPBMUX1 REGISTER
BITS
(GPBMUX1 BITS = 00)
(GPBMUX1 BITS = 01)
(GPBMUX1 BITS = 10)
(GPBMUX1 BITS = 11)
1:0
GPIO32
SDAA (I/OD)
EPWMSYNCI (I)
EQEP1S (I/O)
3:2
GPIO33
SCLA (I/OD)
EPWMSYNCO (O)
EQEP1I (I/O)
5:4
GPIO34
Reserved
Reserved
CTRIPPFCOUT (O)
7:6
GPIO35 (TDI)
Reserved
Reserved
Reserved
(1)
9:8
GPIO36 (TMS)
Reserved
Reserved
Reserved
11:10
GPIO37 (TDO)
Reserved
Reserved
Reserved
13:12
GPIO38/XCLKIN (TCK)
Reserved
Reserved
Reserved
15:14
GPIO39
Reserved
SCIRXDC (I)
CTRIPPFCOUT (O)
17:16
GPIO40
EPWM7A (O)
Reserved
Reserved
19:18
Reserved
Reserved
Reserved
Reserved
21:20
GPIO42
EPWM7B (O)
SCITXDC (O)
CTRIPM1OUT (O)
23:22
Reserved
Reserved
Reserved
Reserved
25:24
Reserved
Reserved
Reserved
Reserved
27:26
Reserved
Reserved
Reserved
Reserved
29:28
Reserved
Reserved
Reserved
Reserved
31:30
Reserved
Reserved
Reserved
Reserved
I = Input, O = Output, OD = Open Drain
The user can select the type of input qualification for each GPIO pin through the GPxQSEL1/2 registers from
four choices:
• Synchronization to SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This mode is the default mode of all GPIO pins
at reset and this mode simply synchronizes the input signal to the system clock (SYSCLKOUT).
• Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the
input is allowed to change.
• The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. The sampling period specifies a multiple of SYSCLKOUT cycles for sampling the input
signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when
ALL samples are the same (all 0s or all 1s) as shown in Figure 8-45 (for 6 sample mode).
• No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not
required (synchronization is performed within the peripheral).
Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral input
signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will
default to either a 0 or 1 state, depending on the peripheral.
128
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
GPIOXINT1SEL
GPIOLMPSEL
GPIOXINT2SEL
LPMCR0
GPIOXINT3SEL
External Interrupt
MUX
Low-Power
Modes Block
Asynchronous
path
PIE
GPxDAT (read)
GPxQSEL1/2
GPxCTRL
GPxPUD
Input
Qualification
Internal
Pullup
00
N/C
01
Peripheral 1 Input
10
Peripheral 2 Input
11
Peripheral 3 Input
GPxTOGGLE
Asynchronous path
GPIOx pin
GPxCLEAR
GPxSET
00
01
GPxDAT (latch)
Peripheral 1 Output
10
Peripheral 2 Output
11
Peripheral 3 Output
High Impedance
Output Control
00
0 = Input, 1 = Output
XRS
= Default at Reset
A.
B.
C.
GPxDIR (latch)
01
Peripheral 1 Output Enable
10
Peripheral 2 Output Enable
11
Peripheral 3 Output Enable
GPxMUX1/2
The letter x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the
particular GPIO pin selected.
GPxDAT latch/read are accessed at the same memory location.
This diagram is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the Systems Control and
Interrupts chapter of the TMS320x2805x Real-Time Microcontrollers Technical Reference Manual for pin-specific variations.
Figure 8-43. GPIO Multiplexing
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
129
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
8.9.12.2 GPIO Register Descriptions
The device supports 42 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to
enable 32-bit operations on the registers (along with 16-bit operations). Table 8-51 provides the GPIO register
mapping.
Table 8-51. GPIO Registers
NAME
ADDRESS
SIZE (×16)
DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL
0x6F80
2
GPIO A Control register (GPIO0 to 31)
GPAQSEL1
0x6F82
2
GPIO A Qualifier Select 1 register (GPIO0 to 15)
GPAQSEL2
0x6F84
2
GPIO A Qualifier Select 2 register (GPIO16 to 31)
GPAMUX1
0x6F86
2
GPIO A MUX 1 register (GPIO0 to 15)
GPAMUX2
0x6F88
2
GPIO A MUX 2 register (GPIO16 to 31)
GPADIR
0x6F8A
2
GPIO A Direction register (GPIO0 to 31)
GPAPUD
0x6F8C
2
GPIO A Pull Up Disable register (GPIO0 to 31)
GPBCTRL
0x6F90
2
GPIO B Control register (GPIO32 to 44)
GPBQSEL1
0x6F92
2
GPIO B Qualifier Select 1 register (GPIO32 to 44)
GPBMUX1
0x6F96
2
GPIO B MUX 1 register (GPIO32 to 44)
GPBDIR
0x6F9A
2
GPIO B Direction register (GPIO32 to 44)
GPBPUD
0x6F9C
2
GPIO B Pull Up Disable register (GPIO32 to 44)
Reserved
0x6FB6
2
Reserved
Reserved
0x6FBA
2
Reserved
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT
0x6FC0
2
GPIO A Data register (GPIO0 to 31)
GPASET
0x6FC2
2
GPIO A Data Set register (GPIO0 to 31)
GPACLEAR
0x6FC4
2
GPIO A Data Clear register (GPIO0 to 31)
GPATOGGLE
0x6FC6
2
GPIO A Data Toggle register (GPIO0 to 31)
GPBDAT
0x6FC8
2
GPIO B Data register (GPIO32 to 44)
GPBSET
0x6FCA
2
GPIO B Data Set register (GPIO32 to 44)
GPBCLEAR
0x6FCC
2
GPIO B Data Clear register (GPIO32 to 44)
GPBTOGGLE
0x6FCE
2
GPIO B Data Toggle register (GPIO32 to 44)
Reserved
0x6FD8
2
Reserved
Reserved
0x6FDA
2
Reserved
Reserved
0x6FDC
2
Reserved
Reserved
0x6FDE
2
Reserved
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
0x6FE0
1
XINT1 GPIO Input Select register (GPIO0 to 31)
GPIOXINT2SEL
0x6FE1
1
XINT2 GPIO Input Select register (GPIO0 to 31)
GPIOXINT3SEL
0x6FE2
1
XINT3 GPIO Input Select register (GPIO0 to 31)
GPIOLPMSEL
0x6FE8
2
LPM GPIO Select register (GPIO0 to 31)
Note
There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn and GPxQSELn
registers occurs to when the action is valid.
130
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.12.3 GPIO Electrical Data/Timing
8.9.12.3.1 GPIO - Output Timing
8.9.12.3.1.1 General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
tr(GPO)
Rise time, GPIO switching low to high
tf(GPO)
Fall time, GPIO switching high to low
tfGPO
Toggling frequency
(1)
MAX
UNIT
All GPIOs
MIN
13(1)
ns
All GPIOs
13(1)
15
ns
MHz
Rise time and fall time vary with electrical loading on I/O pins. Values given in Section 8.9.12.3.1.1 are applicable for a 40-pF load on
I/O pins.
GPIO
t f(GPO)
t r(GPO)
Figure 8-44. General-Purpose Output Timing
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
131
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.12.3.2 GPIO - Input Timing
8.9.12.3.2.1 General-Purpose Input Timing Requirements
MIN
tw(SP)
Sampling period
tw(IQSW)
tw(GPI) (2)
(1)
(2)
UNIT
QUALPRD = 0
1tc(SCO)
cycles
QUALPRD ≠ 0
2tc(SCO) * QUALPRD
cycles
Input qualifier sampling window
tw(SP) *
With input qualifier
(n(1)
– 1)
cycles
2tc(SCO)
cycles
tw(IQSW) + tw(SP) + 1tc(SCO)
cycles
Synchronous mode
Pulse duration, GPIO low/high
MAX
The letter n represents the number of qualification samples as defined by GPxQSELn register.
For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
tw(SP)
0
0
0
1
1
1
1
1
Sampling Window
1
1
1
Sampling Period determined
by GPxCTRL[QUALPRD]
tw(IQSW)
1
[(SYSCLKOUT cycle * 2 * QUALPRD) * 5
(B)
(C)
]
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A.
B.
C.
D.
This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. The QUALPRD bit
field value can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value n, the
qualification sampling period in 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).
The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other
words, the inputs should be stable for (5 × QUALPRD × 2) SYSCLKOUT cycles. This condition would ensure 5 sampling periods for
detection to occur. Because external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 8-45. Sampling Mode
132
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.12.3.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 × QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the preceding equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. The number of samples is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 5, if QUALPRD = 0
SYSCLK
GPIOxn
t w(GPI)
Figure 8-46. General-Purpose Input Timing
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
133
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
VDDIO
> 1 MS
2 pF
VSS
VSS
Figure 8-47. Input Resistance Model for a GPIO Pin With an Internal Pullup
134
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.12.3.4 Low-Power Mode Wakeup Timing
Section 8.9.12.3.4.1 provides the timing requirements, Section 8.9.12.3.4.2 provides the switching
characteristics, and Figure 8-48 shows the timing diagram for IDLE mode.
8.9.12.3.4.1 IDLE Mode Timing Requirements
MIN
tw(WAKE-INT) (1) Pulse duration, external wake-up signal
(1)
Without input qualifier
MAX
2tc(SCO)
With input qualifier
UNIT
cycles
5tc(SCO) + tw(IQSW)
For an explanation of the input qualifier parameters, see Section 8.9.12.3.2.1.
8.9.12.3.4.2 IDLE Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Delay time, external wake signal to program execution resume
•
td(WAKE-IDLE) (1) •
•
Wake up from flash
Without input qualifier
–
With input qualifier
Flash module in active state
Wake up from flash
Without input qualifier
–
With input qualifier
Flash module in sleep state
Wake up from SARAM
MIN
Without input qualifier
With input qualifier
(1)
(2)
MAX
(2)
UNIT
cycles
20tc(SCO)
20tc(SCO) + tw(IQSW)
1050tc(SCO)
1050tc(SCO) + tw(IQSW)
20tc(SCO)
20tc(SCO) + tw(IQSW)
cycles
cycles
cycles
For an explanation of the input qualifier parameters, see Section 8.9.12.3.2.1.
This delay time is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR
(triggered by the wakeup) signal involves additional latency.
td(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE−INT)
WAKE INT
A.
B.
(A)(B)
WAKE INT can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles
(minimum) is needed before the wake-up signal could be asserted.
From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at
least 4 OSCCLK cycles have elapsed.
Figure 8-48. IDLE Entry and Exit Timing
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
135
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.12.3.4.3 STANDBY Mode Timing Requirements
MIN
tw(WAKE-INT)
(1)
Pulse duration, external
wake-up signal
Without input qualification
With input qualification(1)
MAX
3tc(OSCCLK)
UNIT
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
QUALSTDBY is a 6-bit field in the LPMCR0 register.
8.9.12.3.4.4 STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
td(IDLE-XCOL)
TEST CONDITIONS
Delay time, IDLE instruction
executed to XCLKOUT low
MIN
MAX
UNIT
32tc(SCO)
45tc(SCO)
cycles
Delay time, external wake signal to program execution
resume(1)
•
Wake up from flash
–
td(WAKE-STBY)
•
•
Without input qualifier
Flash module in active state With input qualifier
Wake up from flash
Without input qualifier
–
With input qualifier
Flash module in sleep state
Wake up from SARAM
Without input qualifier
With input qualifier
(1)
136
cycles
100tc(SCO)
100tc(SCO) + tw(WAKE-INT)
1125tc(SCO)
1125tc(SCO) + tw(WAKE-INT)
100tc(SCO)
100tc(SCO) + tw(WAKE-INT)
cycles
cycles
cycles
This delay time is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR
(triggered by the wake up signal) involves additional latency.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
(C)
(A)
(B)
Device
Status
(F)
(D)(E)
STANDBY
STANDBY
(G)
Normal Execution
Flushing Pipeline
Wake-up
(H)
Signal
tw(WAKE-INT)
td(WAKE-STBY)
X1/X2 or
XCLKIN
XCLKOUT
td(IDLE−XCOL)
A.
B.
IDLE instruction is executed to put the device into STANDBY mode.
The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated as follows before being turned
off:
•
•
•
C.
D.
E.
F.
G.
H.
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly.
Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After
the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
The external wake-up signal is driven active.
The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the
device may not exit low-power mode for subsequent wake-up pulses.
After a latency period, the STANDBY mode is exited.
Normal execution resumes. The device will respond to the interrupt (if enabled).
From the time the IDLE instruction is executed to place the device into low-power mode, wakeup should not be initiated until at least 4
OSCCLK cycles have elapsed.
Figure 8-49. STANDBY Entry and Exit Timing Diagram
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
137
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
8.9.12.3.4.5 HALT Mode Timing Requirements
MIN
MAX
UNIT
tw(WAKE-GPIO)
Pulse duration, GPIO wake-up signal
toscst + 2tc(OSCCLK)
cycles
tw(WAKE-XRS)
Pulse duration, XRS wake-up signal
toscst + 8tc(OSCCLK)
cycles
8.9.12.3.4.6 HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
td(IDLE-XCOL)
Delay time, IDLE instruction executed to XCLKOUT low
tp
PLL lock-up time
MIN
MAX
UNIT
32tc(SCO)
45tc(SCO)
cycles
1
ms
Delay time, PLL lock to program execution resume
•
td(WAKE-HALT)
–
•
138
Wake up from flash
1125tc(SCO)
cycles
35tc(SCO)
cycles
Flash module in sleep state
Wake up from SARAM
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
(C)
(A)
(F)
(B)
Device
Status
HALT
Flushing Pipeline
(H)
(G)
(D)(E)
HALT
PLL Lock-up Time
Wake-up Latency
Normal
Execution
(I)
GPIOn
td(WAKE−HALT )
tw(WAKE-GPIO)
tp
X1/X2 or
XCLKIN
Oscillator Start-up Time
XCLKOUT
td(IDLE−XCOL)
A.
B.
IDLE instruction is executed to put the device into HALT mode.
The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated as follows before oscillator is
turned off and the CLKIN to the core is stopped:
•
•
•
C.
D.
E.
F.
G.
H.
I.
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly.
Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power. It is possible to
keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT mode. Keeping INTOSC1, INTOSC2,
and the watchdog alive in HALT mode is done by writing to the appropriate bits in the CLKCTL register. After the IDLE instruction is
executed, a delay of 5 OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up
sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized, which enables the provision of a clean
clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wake-up procedure,
care should be taken to maintain a low noise environment prior to entering and during HALT mode.
The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the
device may not exit low-power mode for subsequent wake-up pulses.
Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms.
When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now exited.
Normal operation resumes.
From the time the IDLE instruction is executed to place the device into low-power mode, wakeup should not be initiated until at least 4
OSCCLK cycles have elapsed.
Figure 8-50. HALT Wake-Up Using GPIOn
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
139
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
9 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 TI Reference Design
The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at the Select TI reference designs page.
Single-axis Motor Control Reference Design with Integrated Power Factor Correction
This reference design demonstrates best practices for integrating both single-axis motor control and power
factor correction (PFC) into a single microcontroller. This practice is popular when designing variable-frequency
compressors, particularly for HVAC systems. This implementation is optimized to perform using a sensorless
Field Oriented Control (FOC) algorithm to drive a permanent magnet synchronous motor (PMSM) and two phase
interleaved PFC on the TMS320F2805x microcontroller. The FOC algorithm maintains efficiency in a wide range
of speeds and considers torque changes with transient phases by processing a dynamic model of the motor.
140
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
10 Device and Documentation Support
10.1 Getting Started
To get started with C2000 real-time microcontrollers, see the C2000 real-time microcontrollers – Design &
development page.
10.2 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ MCU devices and support tools. Each TMS320 MCU commercial family member has one of three
prefixes: TMX, TMP, or TMS (for example, TMS320F28055). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages
of product development from engineering prototypes (with TMX for devices and TMDX for tools) through fully
qualified production devices and tools (with TMS for devices and TMDS for tools).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
TMP Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
TMS Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package
type (for example, PN) and temperature range (for example, T). Figure 10-1 provides a legend for reading the
complete device name for any family member.
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI
sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F2805x Real-Time
MCUs Silicon Errata.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
141
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
Figure 10-1. Device Nomenclature
10.3 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance
of the device, generate code, and develop solutions are listed here. To view all available tools and software for
C2000™ real-time control MCUs, visit the C2000 real-time control MCUs – Design & development page.
Development Tools
controlCARD with TMS320F28054MPNT, InstaSPIN-FOC and InstaSPIN-MOTION enabled
Featuring the TMS320F28054M MCU, capable of running the InstaSPIN-FOC™ and InstaSPIN-MOTION™
solutions from on-chip ROM, the TMDSCNCD28054MISO controlCARD provides a convenient and standardized
hardware interface to begin experimentation with the latest motor control technology from Texas Instruments.
F2805x Isolated USB controlCARD
C2000™ controlCARDs from Texas Instruments are a unique set of daughtercards enabling experimentation
with C2000’s broad portfolio of MCUs for device evaluation and application development. Designed with a
DIM100 or larger, plug-in connector, controlCARDs are easily interchangeable throughout C2000’s collection of
development kits, giving users the ability to experiment with various C2000 MCUs to find the correct MCU fit
for an application. controlCARDs give access to all digital I/Os, analog I/Os, and JTAG signals from the C2000
MCU, providing a simple, modular, and standardized board-level interface to the C2000 MCU. Software, support,
and documentation, are provided completely free through C2000’s C2000Ware software platform. Learn more
and download C2000Ware today by visiting the C2000Ware for C2000 MCUs page.
F2805x Experimenter Kit
C2000™ Experimenters Kits from Texas Instruments are device evaluation kits, providing a platform for initial
device exploration and prototyping. Each Experimenters Kit includes a docking station and a plug-in compatible
controlCARD, which docks directly onto the docking station. The docking station features onboard USB JTAG
emulation, access to all C2000 MCU signals from the controlCARD, breadboard areas for experimentation,
and JTAG and RS-232 connectors. For software development, Code Composer Studio (CCS) Integrated
Development Environment (IDE) is included for free with use of the onboard XDS100 USB JTAG debug
probe. Device software, support, example projects, libraries, and documentation are provided completely free
through the C2000 C2000Ware software platform. Learn more and download C2000Ware today by visiting the
C2000Ware for C2000 MCUs page.
142
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
Software Tools
C2000Ware for C2000 MCUs
C2000Ware for C2000 microcontrollers is a cohesive set of development software and documentation designed
to minimize software development time. From device-specific drivers and libraries to device peripheral examples,
C2000Ware provides a solid foundation to begin development and evaluation. C2000Ware is the recommended
content delivery tool versus controlSUITE™.
Code Composer Studio (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller
and Embedded Processors portfolio. CCS comprises a suite of tools used to develop and debug embedded
applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger,
profiler, and many other features. The intuitive IDE provides a single user interface taking the user through
each step of the application development flow. Familiar tools and interfaces let users get started faster than
ever before. CCS combines the advantages of the Eclipse software framework with advanced embedded debug
capabilities from TI resulting in a compelling feature-rich development environment for embedded developers.
Pin Mux Tool
The Pin Mux Utility is a software tool which provides a Graphical User Interface for configuring pin multiplexing
settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting
interface.
C2000 Third-party search tool TI has partnered with multiple companies to offer a wide range of solutions and
services for TI C2000 devices. These companies can accelerate your path to production using C2000 devices.
Download this search tool to quickly browse third-party details and find the right third-party to meet your needs.
Models
Various models are available for download from the product Tools & Software pages. These include I/O Buffer
Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all
available models, visit the Models section of the Tools & Software page for each device.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable
hands-on workshops provides an easy means for gaining a complete working knowledge of the C2000
microcontroller family. These training resources have been designed to decrease the learning curve, while
reducing development time, and accelerating product time to market. For more information on the various
training resources, visit the C2000™ real-time control MCUs – Support & training site.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
143
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
10.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral is
listed here.
Errata
TMS320F2805x Real-Time MCUs Silicon Errata describes known advisories on silicon and provides
workarounds.
InstaSPIN Technical Reference Manuals
InstaSPIN-FOC™ and InstaSPIN-MOTION™ User's Guide describes the InstaSPIN-FOC and InstaSPINMOTION devices.
TMS320F28054F, TMS320F28052F InstaSPIN-FOC™ Software Technical Reference Manual describes
TMS320F28054F and TMS320F28052F InstaSPIN-FOC software.
TMS320F28054M, TMS320F28052M InstaSPIN-MOTION™ Software Technical Reference Manual describes
TMS320F28054M and TMS320F28052M InstaSPIN-MOTION software.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This reference
guide also describes emulation features available on these DSPs.
Peripheral Guides and Technical Reference Manuals
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
digital signal processors (DSPs).
TMS320x2805x Real-Time Microcontrollers Technical Reference Manual details the integration, the
environment, the functional description, and the programming models for each peripheral and subsystem in
the 2805x microcontrollers.
Tools Guides
TMS320C28x Assembly Language Tools v21.6.0.LTS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v21.6.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Reports
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
Semiconductor and IC Package Thermal Metrics describes traditional and new thermal metrics and puts their
application in perspective with respect to system-level junction temperature estimation.
144
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
MCU CAN Module Operation Using the On-Chip Zero-Pin Oscillator.
The TMS320F2803x/TMS320F2805x/TMS320F2806x series of microcontrollers have an on-chip zero-pin
oscillator that needs no external components. This application report describes how to use the CAN module
with this oscillator to operate at the maximum bit rate and bus length without the added cost of an external clock
source.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for
serial programming a device.
10.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.6 Trademarks
TMS320C2000™, DSP/BIOS™, TMS320™, InstaSPIN-FOC™, InstaSPIN-MOTION™, controlSUITE™, and TI
E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
10.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
145
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797F – NOVEMBER 2012 – REVISED SEPTEMBER 2021
www.ti.com
11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
146
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMS320F28050PNS
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F28050PNS
TMS320
TMS320F28051PNS
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F28051PNS
TMS320
TMS320F28051PNT
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
F28051PNT
TMS320
TMS320F28052FPNQ
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F28052FPNQ
TMS320
TMS320F28052FPNT
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
F28052FPNT
TMS320
TMS320F28052MPNQ
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F28052MPNQ
TMS320
TMS320F28052MPNT
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
F28052MPNT
TMS320
TMS320F28052PNQ
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F28052PNQ
TMS320
TMS320F28052PNS
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F28052PNS
TMS320
TMS320F28052PNT
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
F28052PNT
TMS320
TMS320F28053PNS
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F28053PNS
TMS320
TMS320F28054FPNQ
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F28054FPNQ
TMS320
TMS320F28054FPNT
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
F28054FPNT
TMS320
TMS320F28054MPNQ
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F28054MPNQ
TMS320
TMS320F28054MPNT
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
F28054MPNT
TMS320
TMS320F28054PNQ
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F28054PNQ
TMS320
TMS320F28054PNS
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F28054PNS
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
16-Mar-2021
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMS320
TMS320F28055PNS
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
F28055PNS
TMS320
TMS320F28055PNT
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
F28055PNT
TMS320
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of