TMS320R2811, TMS320R2812
Digital Signal Processors
Data Manual
Literature Number: SPRS257C
June 2004 − Revised June 2006
!
!
Revision History
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS257B
device-specific data sheet to make it an SPRS257C revision.
PAGE
NO.
ADDITIONS/CHANGES/DELETIONS
13
Changed Temperature Options bullet in Features list
15
Added a separate row to Table 2−1 Hardware Features to modify Q temperature options
20
Modified symbol (§) note in Table 2−2
23
Modified Note in description of TRST in Table 2−2
23−24
Modified description of EMU0 and EMU1 in Table 2−2
31
Modified memory map in Figure 3−2
32
Modified memory map in Figure 3−3
87
Added the ZHH package to the Absolute Maximum Ratings table (6.1)
88
Added X1 to XCLKIN in the Recommended Operating Conditions table (6.2)
93
Modified XCLKIN values in Table 6−3
100
Modified note under Table 6−9
100
Modified note under Table 6−10 and changed values from MIN to MAX
100
Moved values from MIN to MAX in Table 6−12
101
Moved values from MIN to MAX in Table 6−14
102
Modified note C in Figure 6−13
103
Modified the last symbol note (||) in Table 6−16
109
Modified note in Figure 6−22
111
Modified note in Figure 6−23
105
Modified note on Table 6−19
105
Modified note on Table 6−20
113
Modified note on Figure 6−24
127
Deleted last sentence in the fifth paragraph under section 6.27 XHOLD and XHOLDA
131
Modified gain error and internal voltage reference values in Table 6−41
June 2004 − Revised June 2006
SPRS257C
3
Revision History
This page intentionally left blank.
4
SPRS257C
June 2004 − Revised June 2006
Contents
Contents
Section
1
2
3
4
Page
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Device Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1
Terminal Assignments for the GHH and ZHH Packages . . . . . . . . . . . . . . . . . . .
2.3.2
Pin Assignments for the PGF Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3
Pin Assignments for the PBK Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Brief Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1
C28x CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2
Memory Bus (Harvard Bus Architecture) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3
Peripheral Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4
Real-Time JTAG and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5
External Interface (XINTF) (2812 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6
M0, M1 SARAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.7
L0, L1, L2, L3, H0 SARAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.8
Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.9
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.10
Peripheral Interrupt Expansion (PIE) Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.11
External Interrupts (XINT1, 2, 13, XNMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.12
Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.13
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.14
Peripheral Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.15
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.16
Peripheral Frames 0, 1, 2 (PFn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.17
General-Purpose Input/Output (GPIO) Multiplexer . . . . . . . . . . . . . . . . . . . . . . . .
3.2.18
32-Bit CPU-Timers (0, 1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.19
Control Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.20
Serial Port Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Device Emulation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
External Interface, XINTF (2812 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1
Timing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2
XREVISION Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7
System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1
OSC and PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.2
Loss of Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3
PLL-Based Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.4
External Reference Oscillator Clock Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.5
Watchdog Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.6
Low-Power Modes Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
32-Bit CPU-Timers 0/1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
June 2004 − Revised June 2006
SPRS257C
13
14
14
15
16
16
17
18
19
30
31
34
34
34
34
35
35
35
35
35
36
36
36
36
36
37
37
37
37
37
38
38
38
40
41
41
41
43
46
47
48
49
50
50
51
51
53
53
5
Contents
4.2
5
6
6
Event Manager Modules (EVA, EVB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.2.1
General-Purpose (GP) Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.2.2
Full-Compare Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.3
Programmable Deadband Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.4
PWM Waveform Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.5
Double Update PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.6
PWM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.7
Capture Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.2.8
Quadrature-Encoder Pulse (QEP) Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.2.9
External ADC Start-of-Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.3
Enhanced Analog-to-Digital Converter (ADC) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.4
Enhanced Controller Area Network (eCAN) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.5
Multichannel Buffered Serial Port (McBSP) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.6
Serial Communications Interface (SCI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.7
Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.8
GPIO MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.1
Device and Development Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.2
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.2
Recommended Operating Conditions† . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3
Electrical Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.4
Current Consumption by Power-Supply Pins Over Recommended Operating Conditions
During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320R281x) . . . . . . . . . . . . . . . . . . 89
6.5
Current Consumption Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.6
Reducing Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.7
Power Sequencing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.8
Signal Transition Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.9
Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.10
General Notes on Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.11
Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.12
Device Clock Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.13
Clock Requirements and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.13.1
Input Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.13.2
Output Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.14
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.15
Low-Power Mode Wakeup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.16
Event Manager Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.16.1
PWM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.16.2
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.17
General-Purpose Input/Output (GPIO) − Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.18
General-Purpose Input/Output (GPIO) − Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.19
SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.20
SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.21
External Interface (XINTF) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.22
XINTF Signal Alignment to XCLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.23
External Interface Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.24
External Interface Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
SPRS257C
June 2004 − Revised June 2006
Contents
6.25
6.26
6.27
6.28
6.29
7
8
External Interface Ready-on-Read Timing With One External Wait State . . . . . . . . . . . . . . . . 121
External Interface Ready-on-Write Timing With One External Wait State . . . . . . . . . . . . . . . . 124
XHOLD and XHOLDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
XHOLD/XHOLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
On-Chip Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.29.1
ADC Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
6.29.2
ADC Electrical Characteristics Over Recommended Operating Conditions . . 131
6.29.3
Current Consumption for Different ADC Configurations
(at 25-MHz ADCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.29.4
ADC Power-Up Control Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.29.5
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.29.5.1
Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.29.5.2
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.29.5.3
Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.29.5.4
Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.29.6
Sequential Sampling Mode (Single-Channel) (SMODE = 0) . . . . . . . . . . . . . . . 134
6.29.7
Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) . . . . . . . . . . . . . . 136
6.29.8
Definitions of Specifications and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.30
Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.30.1
McBSP Transmit and Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.30.2
McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Migration From F281x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
June 2004 − Revised June 2006
SPRS257C
7
Figures
List of Figures
Figure
Page
Figure 2−1. TMS320R2812 179-Ball GHH and ZHH MicroStar BGA (Bottom View) . . . . . . . . . . . . . . . . . . . . . . 16
Figure 2−2. TMS320R2812 176-Pin PGF LQFP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 2−3. TMS320R2811 128-Pin PBK LQFP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3−1. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 3−2. R2812 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 3−3. R2811 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 3−4. External Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 3−5. Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 3−6. Multiplexing of Interrupts Using the PIE Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 3−7. Clock and Reset Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 3−8. OSC and PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 3−9. Recommended Crystal/ Clock Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 3−10. Watchdog Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 4−1. CPU-Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 4−2. CPU-Timer Interrupts Signals and Output Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 4−3. Event Manager A Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 4−4. Block Diagram of the R281x ADC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 4−5. ADC Pin Connections With Internal Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 4−6. ADC Pin Connections With External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 4−7. eCAN Block Diagram and Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 4−8. eCAN Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 4−9. McBSP Module With FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 4−10. Serial Communications Interface (SCI) Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 4−11. Serial Peripheral Interface Module Block Diagram (Slave Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 4−12. GPIO/Peripheral Pin MUXing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 5−1. TMS320x28x Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 6−1. Typical Current Consumption Over Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 6−2. Typical Power Consumption Over Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 6−3. Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 6−4. Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 6−5. 3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 6−6. Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 6−7. Power-on Reset in Microcomputer Mode (XMP/MC = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 6−8. Power-on Reset in Microprocessor Mode (XMP/MC = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 6−9. Warm Reset in Microcomputer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 6−10. Effect of Writing Into PLLCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 6−11. IDLE Entry and Exit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 6−12. STANDBY Entry and Exit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 6−13. HALT Wakeup Using XNMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 6−14. PWM Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8
SPRS257C
June 2004 − Revised June 2006
Figures
Figure 6−15.
Figure 6−16.
Figure 6−17.
Figure 6−18.
Figure 6−19.
Figure 6−20.
Figure 6−21.
Figure 6−22.
Figure 6−23.
Figure 6−24.
Figure 6−25.
Figure 6−26.
Figure 6−27.
Figure 6−28.
Figure 6−29.
Figure 6−30.
Figure 6−31.
Figure 6−32.
Figure 6−33.
Figure 6−34.
Figure 6−35.
Figure 6−36.
Figure 6−37.
Figure 6−38.
Figure 6−39.
Figure 6−40.
Figure 6−41.
Figure 6−42.
Figure 6−43.
Figure 6−44.
TDIRx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
EVASOC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
EVBSOC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
General-Purpose Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
GPIO Input Qualifier − Example Diagram for QUALPRD = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
General-Purpose Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SPI Master Mode External Timing (Clock Phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SPI Master External Timing (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
SPI Slave Mode External Timing (Clock Phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SPI Slave Mode External Timing (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Relationship Between XTIMCLK and SYSCLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Example Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Example Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Example Read With Synchronous XREADY Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Example Read With Asynchronous XREADY Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Write With Synchronous XREADY Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Write With Asynchronous XREADY Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
External Interface Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) . . . . . . . . . . . . . . . . . . . . . 129
ADC Analog Input Impedance Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
ADC Power-Up Control Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Sequential Sampling Mode (Single-Channel) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Simultaneous Sampling Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
McBSP Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
McBSP Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . 141
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . 142
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . 143
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . 144
June 2004 − Revised June 2006
SPRS257C
9
Tables
List of Tables
Table
Page
Table 2−1. Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2−2. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3−1. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 3−2. Boot Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 3−3. Peripheral Frame 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 3−4. Peripheral Frame 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 3−5. Peripheral Frame 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 3−6. Device Emulation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 3−7. XINTF Configuration and Control Register Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 3−8. XREVISION Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 3−9. PIE Peripheral Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 3−10. PIE Configuration and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 3−11. External Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 3−12. PLL, Clocking, Watchdog, and Low-Power Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 3−13. PLLCR Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 3−14. Possible PLL Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 3−15. R281x Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 4−1. CPU-Timers 0, 1, 2 Configuration and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 4−2. Module and Signal Names for EVA and EVB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 4−3. EVA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 4−4. ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 4−5. 3.3-V eCAN Transceivers for the R281x DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 4−6. CAN Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 4−7. McBSP Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 4−8. SCI-A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 4−9. SCI-B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 4−10. SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 4−11. GPIO MUX Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 4−12. GPIO Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 6−1. Typical Current Consumption by Various Peripherals (at 150 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 6−2. TMS320R281x Clock Table and Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 6−3. Input Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 6−4. XCLKIN Timing Requirements − PLL Bypassed or Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 6−5. XCLKIN Timing Requirements − PLL Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 6−6. Possible PLL Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 6−7. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 6−8. Reset (XRS) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 6−9. IDLE Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 6−10. IDLE Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 6−11. STANDBY Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 6−12. STANDBY Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 6−13. HALT Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 6−14. HALT Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 6−15. PWM Switching Characteristics†‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 6−16. Timer and Capture Unit Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 6−17. External ADC Start-of-Conversion − EVA − Switching Characteristics† . . . . . . . . . . . . . . . . . . . . . 104
10
SPRS257C
June 2004 − Revised June 2006
Tables
Table 6−18. External ADC Start-of-Conversion − EVB − Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 104
Table 6−19. Interrupt Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 6−20. Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 6−21. General-Purpose Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 6−22. General-Purpose Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 6−23. SPI Master Mode External Timing (Clock Phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 6−24. SPI Master Mode External Timing (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 6−25. SPI Slave Mode External Timing (Clock Phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 6−26. SPI Slave Mode External Timing (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 6−27. Relationship Between Parameters Configured in XTIMING and Duration of Pulse . . . . . . . . . . . . 115
Table 6−28. XINTF Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 6−29. External Memory Interface Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 6−30. External Memory Interface Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 6−31. External Memory Interface Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 6−32. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) . . . . 121
Table 6−33. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) . . . . . . 121
Table 6−34. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) . . . . . . . . . . . . . . . 121
Table 6−35. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) . . . . . . . . . . . . . . 121
Table 6−36. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) . . . 124
Table 6−37. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) . . . . . . . . . . . . . . . 124
Table 6−38. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) . . . . . . . . . . . . . . 124
Table 6−39. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 6−40. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) . . . . . . . . . . . . . . . . . . . . . . 129
Table 6−41. DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 6−42. AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 6−43. ADC Power-Up Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 6−44. Sequential Sampling Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 6−45. Simultaneous Sampling Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 6−46. McBSP Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 6−47. McBSP Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 6−48. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . 141
Table 6−49. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . . 141
Table 6−50. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . . 142
Table 6−51. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . 142
Table 6−52. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . 143
Table 6−53. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . . 143
Table 6−54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . . 144
Table 6−55. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . 144
Table 6−56. Feature Comparison Between F281x and R281x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 7−1. Thermal Resistance Characteristics for 179-GHH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 7−2. Thermal Resistance Characteristics for 179-ZHH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 7−3. Thermal Resistance Characteristics for 176-PGF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 7−4. Thermal Resistance Characteristics for 128-PBK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
June 2004 − Revised June 2006
SPRS257C
11
Tables
12
SPRS257C
June 2004 − Revised June 2006
Features
1
Features
D High-Performance Static CMOS Technology
D
D
D
D
D
D
D
− 150 MHz (6.67-ns Cycle Time)
− Low-Power (1.8-V Core @135 MHz, 1.9-V
Core @150 MHz, 3.3-V I/O) Design
JTAG Boundary Scan Support†
High-Performance 32-Bit CPU
(TMS320C28x)
− 16 x 16 and 32 x 32 MAC Operations
− 16 x 16 Dual MAC
− Harvard Bus Architecture
− Atomic Operations
− Fast Interrupt Response and Processing
− Unified Memory Programming Model
− 4M Linear Program/Data Address Reach
− Code-Efficient (in C/C++ and Assembly)
− Code and Pin Compatible to F2810,
F2811, and F2812 devices
− TMS320F24x/LF240x Processor Source
Code Compatible
On-Chip Memory
− 20K x 16 Total Single-Access RAM
(SARAM)
− L0 and L1: 2 Blocks of 4K x 16 Each
SARAM
− L2 and L3: 2 Blocks of 1K X 16 SARAM
− H0: 1 Block of 8K x 16 SARAM
− M0 and M1: 2 Blocks of 1K x 16 Each
SARAM
SPI, SCI, and GPIO Boot Loader Modes to
Support Loading Code From Off-chip
Sources to On-chip RAM. SPI Boot Mode
Supports Loading From an External Serial
EEPROM.
Boot ROM (4K x 16)
− With Software Boot Modes
− Standard Math Tables
External Interface (2812)
− Up to 1M Total Memory
− Programmable Wait States
− Programmable Read/Write Strobe Timing
− Three Individual Chip Selects
Clock and System Control
− Dynamic PLL Ratio Changes Supported
− On-Chip Oscillator
− Watchdog Timer Module
D Three External Interrupts
D Peripheral Interrupt Expansion (PIE) Block
D
D
D
D
D
D
D
D
D
D
That Supports 45 Peripheral Interrupts
Three 32-Bit CPU-Timers
Motor Control Peripherals
− Two Event Managers (EVA, EVB)
− Compatible to 240xA Devices
Serial Port Peripherals
− Serial Peripheral Interface (SPI)
− Two Serial Communications Interfaces
(SCIs), Standard UART
− Enhanced Controller Area Network
(eCAN)
− Multichannel Buffered Serial Port
(McBSP)
12-Bit ADC, 16 Channels
− 2 x 8 Channel Input Multiplexer
− Two Sample-and-Hold
− Single/Simultaneous Conversions
− Fast Conversion Rate: 80 ns/12.5 MSPS
Up to 56 General Purpose I/O (GPIO) Pins
Advanced Emulation Features
− Analysis and Breakpoint Functions
− Real-Time Debug via Hardware
Development Tools Include
− ANSI C/C++ Compiler/Assembler/Linker
− Code Composer Studio IDE
− DSP/BIOS
− JTAG Scan Controllers†
Low-Power Modes and Power Savings
− IDLE, STANDBY, HALT Modes Supported
− Disable Individual Peripheral Clocks
Package Options
− 179-Ball MicroStar BGA With External
Memory Interface (GHH), (ZHH) (2812)
− 176-Pin Low-Profile Quad Flatpack
(LQFP) With External Memory Interface
(PGF) (2812)
− 128-Pin LQFP Without External Memory
Interface (PBK) (2811)
Temperature Options:
− A: −40°C to 85°C (GHH, ZHH, PGF, PBK)
− S: −40°C to 125°C (GHH, ZHH, PGF, PBK)
− Q: −40°C to 125°C (PGF, PBK)
TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
† IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port
June 2004 − Revised June 2006
SPRS257C
13
Introduction
2
Introduction
This section provides a summary of each device’s features, lists the pin assignments, and describes the
function of each pin. This document also provides detailed descriptions of peripherals, electrical
specifications, parameter measurement information, and mechanical data about the available packaging.
2.1
Description
The TMS320R2811 and TMS320R2812 devices, members of the TMS320C28x DSP generation, are highly
integrated, high-performance solutions for demanding control applications. The functional blocks and the
memory maps are described in Section 3, Functional Overview.
Throughout this document, TMS320R2811 and TMS320R2812 are abbreviated as R2811 and R2812,
respectively.
TMS320C28x is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
14
SPRS257C
June 2004 − Revised June 2006
Introduction
2.2
Device Summary
Table 2−1 provides a summary of each device’s features.
Table 2−1. Hardware Features†
FEATURE
R2811
R2812
Instruction Cycle (at 150 MHz)
6.67 ns
6.67 ns
Single-Access RAM (SARAM)
(16-bit word)
20K
20K
Boot ROM
Yes
Yes
—
Yes
EVA, EVB
EVA, EVB
External Memory Interface
Event Managers A and B
(EVA and EVB)
S
General-Purpose (GP) Timers
4
4
S
Compare (CMP)/PWM
16
16
S
Capture (CAP)/QEP Channels
6/2
6/2
Watchdog Timer
Yes
Yes
12-Bit ADC
Yes
Yes
16
16
3
3
S
Channels
32-Bit CPU Timers
SPI
Yes
Yes
SCIA, SCIB
SCIA, SCIB
CAN
Yes
Yes
McBSP
Yes
Yes
Digital I/O Pins (Shared)
56
56
3
3
SCIA, SCIB
External Interrupts
Supply Voltage
1.8-V Core, (135 MHz) 1.9-V Core (150 MHz), 3.3-V I/O
128-pin PBK
179-ball GHH
179-ball ZHH
176-pin PGF
A: −40°C to 85°C
Yes
Yes
S: −40°C to 125°C
Yes
Yes
Q: −40°C to 125°C
Yes
PGF package only
Packaging
Temperature Options
Product Status†
TMS
† See Section 5.1, Device and Development Support Nomenclature for descriptions of product development stages.
June 2004 − Revised June 2006
TMS
SPRS257C
15
Introduction
2.3
Pin Assignments
Figure 2−1 illustrates the ball locations for the 179-ball GHH and ZHH ball grid array (BGA) packages.
Figure 2−2 shows the pin assignments for the 176-pin PGF low-profile quad flatpack (LQFP) and Figure 2−3
shows the pin assignments for the 128-pin PBK LQFP. Table 2−2 describes the function(s) of each pin.
2.3.1
Terminal Assignments for the GHH and ZHH Packages
See Table 2−2 for a description of each terminal’s function(s).
P
XZCS0AND1 PWM8
PWM10
VSS
VDD
CAP6
_QEPI2
XD[8]
VSS
VDD
N
SPISOMIA
PWM7
PWM9
XR/W
T4PWM
_T4CMP
C4TRIP
TEST2
VDDIO
XD[11]
XA[2]
XWE
M
SPISIMOA
XA[1]
XRD
PWM12
CAP4
_QEP3
CAP5
_QEP4
TEST1
XD[9]
X2
VSS
XA[3]
L
VDD
VSS
XD[6]
PWM11
XD[7]
C5TRIP
VDDIO
TDIRB
XD[10]
VDDIO
K
VSS
SPICLKA
XD[4]
SPISTEA
T3PWM
_T3CMP
VSS
C6TRIP
TCLKINB
X1/
XCLKIN
J
MCLKXA
MFSRA
XD[3]
VDDIO
H
VDD
MCLKRA
XD[1]
G
MDXA
MDRA
F
XMP/MC
ADCRESEXT
E
AVDDAVSSADCREFP
ADCREFM ADCINA5 ADCXHOLD
REFBG
REFBG
BGREFIN
SCITXDB
PWM1
SCIRXDB
PWM2
VSS
PWM3
PWM4
XD[12]
XHOLDA
PWM5
VDD
VSS
PWM6
XD[5]
XD[13]
T1PWM
_T1CMP
XA[4]
T2PWM
_T2CMP
VSS
MFSXA
XD[2]
CAP1
_QEP1
CAP2
_QEP2
CAP3
_QEPI1
XA[5]
T1CTRIP
_PDPINTA
XD[0]
VSS
XA[0]
T2CTRIP/
EVASOC
VDDIO
VDD
VSS
XA[6]
VSSA1
VDDA1
ADCINB7
C3TRIP XCLKOUT
XA[7]
TCLKINA
TDIRA
C
ADCINB3 ADCINB0 ADCINB1 ADCINA2
B
ADCINB2 VDDAIO
VSSA2
3
4
XNMI
_XINT13
VDDIO
XA[13]
C2TRIP
XA[8]
C1TRIP
VSS
XRS
XA[18]
XINT2
_ADCSOC
XINT1
_XBIO
VSS
EMU0
TDO
TMS
XA[9]
VSS1
SCITXDA
VDD
EMU1
VSS
XA[12]
XA[10]
TDI
VDD
XA[17]
VSS
XA[15]
VDD
XD[14]
TRST
ADCLO ADCINA3 ADCINA7 XREADY
VSSAIO ADCINA0 ADCINA4
2
XZCS2
VDDIO
ADCINB6 ADCINB5 ADCINB4 ADCINA1 ADCINA6
1
VDD
CANTXA CANRXA
D
A
T3CTRIP T4CTRIP/
_PDPINTB EVBSOC
XZCS6AND7 VSS
VDDA2
VDD1
SCIRXDA
XA[16]
XD[15]
XA[14]
XF
_XPLLDIS
TCK
TESTSEL
XA[11]
5
6
7
8
9
10
11
12
13
14
Figure 2−1. TMS320R2812 179-Ball GHH and ZHH MicroStar BGA (Bottom View)
16
SPRS257C
June 2004 − Revised June 2006
Introduction
2.3.2
Pin Assignments for the PGF Package
XA[11]
TDI
XA[10]
V SS
V DD
TDO
TMS
XA[9]
C3TRIP
C2TRIP
C1TRIP
XA[8]
V SS
XCLKOUT
XA[7]
TCLKINA
TDIRA
T2CTRIP / EVASOC
V DDIO
V SS
V DD
XA[6]
T1CTRIP_PDPINTA
CAP3_QEPI1
XA[5]
CAP2_QEP2
CAP1_QEP1
V SS
T2PWM_T2CMP
XA[4]
T1PWM_T1CMP
PWM6
V DD
V SS
PWM5
XD[13]
XD[12]
PWM4
PWM3
PWM2
PWM1
SCIRXDB
SCITXDB
CANRXA
The TMS320R2812 176-pin PGF low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2−2.
See Table 2−2 for a description of each pin’s function(s).
132
89
88
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
133
XZCS6AND7
TESTSEL
TRST
TCK
EMU0
XA[12]
XD[14]
XF_XPLLDIS
XA[13]
VSS
VDD
XA[14]
VDDIO
EMU1
XD[15]
XA[15]
XINT1_XBIO
XNMI_XINT13
XINT2_ADCSOC
XA[16]
VSS
VDD
SCITXDA
XA[17]
SCIRXDA
XA[18]
XHOLD
XRS
XREADY
VDD1
VSS1
ADCBGREFIN
VSSA2
VDDA2
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
VSSAIO
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
XZCS2
CANTXA
VSS
XA[3]
XWE
T4CTRIP/EVBSOC
XHOLDA
VDDIO
XA[2]
T3CTRIP_PDPINTB
VSS
X1/XCLKIN
X2
VDD
XD[11]
XD[10]
TCLKINB
TDIRB
VSS
VDDIO
XD[9]
TEST1
TEST2
XD[8]
VDDIO
C6TRIP
C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
VSS
CAP4_QEP3
VDD
T4PWM_T4CMP
XD[7]
T3PWM_T3CMP
VSS
XR/W
PWM12
PWM11
PWM10
PWM9
PWM8
PWM7
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
1
45
V DDAIO
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINB6
ADCINB7
ADCREFM
ADCREFP
AVSSREFBG
AVDDREFBG
V DDA1
V SSA1
ADCRESEXT
XMP/ MC
XA[0]
V SS
MDRA
XD[0]
MDXA
V DD
XD[1]
MCLKRA
MFSXA
XD[2]
MCLKXA
MFSRA
XD[3]
V DDIO
V SS
XD[4]
SPICLKA
SPISTEA
XD[5]
V DD
V SS
XD[6]
SPISIMOA
SPISOMIA
XRD
XA[1]
XZCS0AND1
44
Figure 2−2. TMS320R2812 176-Pin PGF LQFP (Top View)
June 2004 − Revised June 2006
SPRS257C
17
Introduction
2.3.3
Pin Assignments for the PBK Package
TDI
VSS
VDD
TDO
TMS
C3TRIP
C2TRIP
C1TRIP
VSS
XCLKOUT
TCLKINA
TDIRA
T2CTRIP/ EVASOC
VDDIO
VDD
T1CTRIP_PDPINTA
CAP3_QEPI1
CAP2_QEP2
CAP1_QEP1
T2PWM_T2CMP
T1PWM_T1CMP
PWM6
VDD
VSS
PWM5
PWM4
PWM3
PWM2
PWM1
SCIRXDB
SCITXDB
CANRXA
The TMS320R2811 128-pin PBK low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2−3.
See Table 2−2 for a description of each pin’s function(s).
96
65
64
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
97
TESTSEL
TRST
TCK
EMU0
XF_XPLLDIS
VDD
VSS
VDDIO
EMU1
XINT1_XBIO
XNMI_XINT13
XINT2_ADCSOC
VSS
VDD
SCITXDA
SCIRXDA
XRS
VDD1
VSS1
ADCBGREFIN
VSSA2
VDDA2
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
VSSAIO
CANTXA
VDD
VSS
T4CTRIP/EVBSOC
T3CTRIP_PDPINTB
VSS
X1/XCLKIN
X2
VDD
TCLKINB
TDIRB
VSS
VDDIO
TEST1
TEST2
VDDIO
C6TRIP
C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
CAP4_QEP3
VDD
T4PWM_T4CMP
T3PWM_T3CMP
VSS
PWM12
PWM11
PWM10
PWM9
PWM8
PWM7
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
1
33
VDDAIO
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINB6
ADCINB7
ADCREFM
ADCREFP
AVSSREFBG
AVDDREFBG
VDDA1
VSSA1
ADCRESEXT
VSS
MDRA
MDXA
VDD
MCLKRA
MFSXA
MCLKXA
MFSRA
VDDIO
VSS
SPICLKA
SPISTEA
VDD
VSS
SPISIMOA
SPISOMIA
32
Figure 2−3. TMS320R2811 128-Pin PBK LQFP
(Top View)
18
SPRS257C
June 2004 − Revised June 2006
Introduction
2.4
Signal Descriptions
Table 2−2 specifies the signals on the R281x devices. All digital inputs are TTL-compatible. All outputs are
3.3 V with CMOS levels. Inputs are not 5-V tolerant.
June 2004 − Revised June 2006
SPRS257C
19
Introduction
Table 2−2. Signal Descriptions†
PIN NO.
NAME
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
DESCRIPTION
XINTF SIGNALS (2812 ONLY)
XA[18]
D7
158
−
O/Z
−
XA[17]
B7
156
−
O/Z
−
XA[16]
A8
152
−
O/Z
−
XA[15]
B9
148
−
O/Z
−
XA[14]
A10
144
−
O/Z
−
XA[13]
E10
141
−
O/Z
−
XA[12]
C11
138
−
O/Z
−
XA[11]
A14
132
−
O/Z
XA[10]
C12
130
−
O/Z
−
XA[9]
D14
125
−
O/Z
−
XA[8]
E12
121
−
O/Z
−
XA[7]
F12
118
−
O/Z
−
XA[6]
G14
111
−
O/Z
−
XA[5]
H13
108
−
O/Z
−
XA[4]
J12
103
−
O/Z
−
XA[3]
M11
85
−
O/Z
−
XA[2]
N10
80
−
O/Z
−
XA[1]
M2
43
−
O/Z
−
XA[0]
G5
18
−
O/Z
XD[15]
A9
147
−
I/O/Z
PU
XD[14]
B11
139
−
I/O/Z
PU
XD[13]
J10
97
−
I/O/Z
PU
XD[12]
L14
96
−
I/O/Z
PU
XD[11]
N9
74
−
I/O/Z
PU
XD[10]
L9
73
−
I/O/Z
PU
XD[9]
M8
68
−
I/O/Z
PU
XD[8]
P7
65
−
I/O/Z
PU
XD[7]
L5
54
−
I/O/Z
PU
XD[6]
L3
39
−
I/O/Z
PU
XD[5]
J5
36
−
I/O/Z
PU
XD[4]
K3
33
−
I/O/Z
PU
XD[3]
J3
30
−
I/O/Z
PU
XD[2]
H5
27
−
I/O/Z
PU
XD[1]
H3
24
−
I/O/Z
PU
19-bit XINTF Address Bus
16-bit XINTF Data Bus
XINTF SIGNALS (2812 ONLY) (CONTINUED)
XD[0]
G3
21
−
I/O/Z
PU
16-bit XINTF Data Bus
† Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡ I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.
20
SPRS257C
June 2004 − Revised June 2006
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
NAME
179-PIN
GHH
AND
ZHH
XMP/MC
XHOLD
F1
E7
176-PIN
PGF
17
159
128-PIN
PBK
−
−
I/O/Z‡
I
I
PU/PD§
DESCRIPTION
PD
Microprocessor/Microcomputer Mode Select. Switches
between microprocessor and microcomputer mode.
When high, Zone 7 is enabled on the external interface.
When low, Zone 7 is disabled from the external interface,
and on-chip boot ROM may be accessed instead. This
signal is latched into the XINTCNF2 register on a reset and
the user can modify this bit in software. The state of the
XMP/MC pin is ignored after reset.
PU
External Hold Request. XHOLD, when active (low),
requests the XINTF to release the external bus and place
all buses and strobes into a high-impedance state. The
XINTF will release the bus when any current access is
complete and there are no pending accesses on the
XINTF.
XHOLDA
K10
82
−
O/Z
−
External Hold Acknowledge. XHOLDA is driven active
(low) when the XINTF has granted a XHOLD request. All
XINTF buses and strobe signals will be in a
high-impedance state. XHOLDA is released when the
XHOLD signal is released. External devices should only
drive the external bus when XHOLDA is active (low).
XZCS0AND1
P1
44
−
O/Z
−
XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1 is
active (low) when an access to the XINTF Zone 0 or
Zone 1 is performed.
XZCS2
P13
88
−
O/Z
−
XINTF Zone 2 Chip Select. XZCS2 is active (low) when an
access to the XINTF Zone 2 is performed.
XZCS6AND7
B13
133
−
O/Z
−
XINTF Zone 6 and Zone 7 Chip Select. XZCS6AND7 is
active (low) when an access to the XINTF Zone 6 or
Zone 7 is performed.
XWE
N11
84
−
O/Z
−
Write Enable. Active-low write strobe. The write strobe
waveform is specified, per zone basis, by the Lead, Active,
and Trail periods in the XTIMINGx registers.
XRD
M3
42
−
O/Z
−
Read Enable. Active-low read strobe. The read strobe
waveform is specified, per zone basis, by the Lead, Active,
and Trail periods in the XTIMINGx registers. NOTE: The
XRD and XWE signals are mutually exclusive.
XR/W
N4
51
−
O/Z
−
Read Not Write Strobe. Normally held high. When low,
XR/W indicates write cycle is active; when high, XR/W
indicates read cycle is active.
PU
Ready Signal. Indicates peripheral is ready to complete
the access when asserted to 1. XREADY can be
configured to be a synchronous or an asynchronous input.
See the timing diagrams for more details.
XREADY
B6
161
−
I
† Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡ I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.
June 2004 − Revised June 2006
SPRS257C
21
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
NAME
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
DESCRIPTION
JTAG AND MISCELLANEOUS SIGNALS
X1/XCLKIN
K9
77
58
I
Oscillator Input − input to the internal oscillator. This pin is
also used to feed an external clock. The 28x can be
operated with an external clock source, provided that the
proper voltage levels be driven on the X1/XCLKIN pin. It
should be noted that the X1/XCLKIN pin is referenced to
the 1.8-V (or 1.9-V) core digital power supply (VDD), rather
than the 3.3-V I/O supply (VDDIO). A clamping diode may
be used to clamp a buffered clock signal to ensure that the
logic-high level does not exceed VDD (1.8 V or 1.9 V) or a
1.8-V oscillator may be used.
X2
M9
76
57
O
Oscillator Output
XCLKOUT
F11
119
87
O
−
Output clock derived from SYSCLKOUT to be used for
external wait-state generation and as a general-purpose
clock source. XCLKOUT is either the same frequency, 1/2
the frequency, or 1/4 the frequency of SYSCLKOUT. At
reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT
signal can be turned off by setting bit 3 (CLKOFF) of the
XINTCNF2 register to 1. Unlike other GPIO pins, the
XCLKOUT pin is not placed in a high impedance state
during reset.
TESTSEL
A13
134
97
I
PD
Test Pin. Reserved for TI. Must be connected to ground.
Device Reset (in) and Watchdog Reset (out).
XRS
D6
160
113
I/O
PU
Device reset. XRS causes the device to terminate
execution. The PC will point to the address contained at
the location 0x3FFFC0. When XRS is brought to a high
level, execution begins at the location pointed to by the
PC. This pin is driven low by the DSP when a watchdog
reset occurs. During watchdog reset, the XRS pin will be
driven low for the watchdog reset duration of 512 XCLKIN
cycles.
The output buffer of this pin is an open-drain with an
internal pullup (100 µA, typical). It is recommended that
this pin be driven by an open-drain device.
TEST1
M7
67
51
I/O
−
This pin is a “no connect (NC)” (i.e., this pin is not
connected to any circuitry internal to the device).
TEST2
N7
66
50
I/O
−
This pin is a “no connect (NC)” (i.e., this pin is not
connected to any circuitry internal to the device).
† Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡ I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.
22
SPRS257C
June 2004 − Revised June 2006
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
NAME
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
DESCRIPTION
JTAG
JTAG test reset with internal pulldown. TRST, when driven
high, gives the scan system control of the operations of the
device. If this signal is not connected or driven low, the
device operates in its functional mode, and the test reset
signals are ignored.
NOTE: Do not use pullup resistors on TRST; it has an
internal pulldown device. TRST is an active high test pin
and must be maintained low at all times during normal
device operation. In a low-noise environment, TRST may
be left floating. In other instances, an external pulldown
resistor is highly recommended. The value of this resistor
should be based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally offers
adequate protection. Since this is application-specific, it is
recommended that each target board be validated for
proper operation of the debugger and the application.
TRST
B12
135
98
I
PD
TCK
A12
136
99
I
PU
JTAG test clock with internal pullup
TMS
D13
126
92
I
PU
JTAG test-mode select (TMS) with internal pullup. This
serial control input is clocked into the TAP controller on the
rising edge of TCK.
TDI
C13
131
96
I
PU
JTAG test data input (TDI) with internal pullup. TDI is
clocked into the selected register (instruction or data) on
a rising edge of TCK.
TDO
D12
127
93
O/Z
−
JTAG scan out, test data output (TDO). The contents of
the selected register (instruction or data) is shifted out of
TDO on the falling edge of TCK.
EMU0
D11
137
100
I/O/Z
PU
Emulator pin 0. When TRST is driven high, this pin is
used as an interrupt to or from the emulator system and
is defined as input/output through the JTAG scan. This
pin is also used to put the device into boundary-scan
mode. With the EMU0 pin at a logic-high state and the
EMU1 pin at a logic-low state, a rising edge on the
TRST pin would latch the device into boundary-scan
mode.
NOTE: An external pullup resistor is recommended on
this pin. The value of this resistor should be based on
the drive strength of the debugger pods applicable to
the design. A 2.2-kΩ to 4.7-kΩ resistor is generally
adequate. Since this is application-specific, it is
recommended that each target board be validated for
proper operation of the debugger and the application.
† Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡ I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.
June 2004 − Revised June 2006
SPRS257C
23
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
NAME
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
DESCRIPTION
JTAG (CONTINUED)
EMU1
C9
146
105
I/O/Z
PU
Emulator pin 1. When TRST is driven high, this pin is
used as an interrupt to or from the emulator system and
is defined as input/output through the JTAG scan. This
pin is also used to put the device into boundary-scan
mode. With the EMU0 pin at a logic-high state and the
EMU1 pin at a logic-low state, a rising edge on the
TRST pin would latch the device into boundary-scan
mode.
NOTE: An external pullup resistor is recommended on
this pin. The value of this resistor should be based on
the drive strength of the debugger pods applicable to
the design. A 2.2-kΩ to 4.7-kΩ resistor is generally
adequate. Since this is application-specific, it is
recommended that each target board be validated for
proper operation of the debugger and the application.
ADC ANALOG INPUT SIGNALS
ADCINA7
B5
167
119
I
ADCINA6
D5
168
120
I
ADCINA5
E5
169
121
I
ADCINA4
A4
170
122
I
ADCINA3
B4
171
123
I
ADCINA2
C4
172
124
I
ADCINA1
D4
173
125
I
ADCINA0
A3
174
126
I
ADCINB7
F5
9
9
I
ADCINB6
D1
8
8
I
ADCINB5
D2
7
7
I
ADCINB4
D3
6
6
I
ADCINB3
C1
5
5
I
ADCINB2
B1
4
4
I
ADCINB1
C3
3
3
I
ADCINB0
C2
2
2
I
ADCREFP
E2
11
11
I/O
8-Channel analog inputs for Sample-and-Hold A. The
ADC pins should not be driven before VDDA1, VDDA2, and
VDDAIO pins have been fully powered up.
8-Channel Analog Inputs for Sample-and-Hold B. The
ADC pins should not be driven before the VDDA1, VDDA2,
and VDDAIO pins have been fully powered up.
ADC Voltage Reference Output (2 V). Requires a low ESR
(50 mΩ − 1.5 Ω) ceramic bypass capacitor of 10 µF to
analog ground. (Can accept external reference input (2 V)
if the software bit is enabled for this mode. 1−10 µF low
ESR capacitor can be used in the external reference
mode.)
† Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡ I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.
24
SPRS257C
June 2004 − Revised June 2006
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
NAME
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
DESCRIPTION
ADC ANALOG INPUT SIGNALS (CONTINUED)
ADCREFM
E4
10
10
I/O
ADC Voltage Reference Output (1 V). Requires a low ESR
(50 mΩ − 1.5 Ω) ceramic bypass capacitor of 10 µF to
analog ground. (Can accept external reference input (1 V)
if the software bit is enabled for this mode. 1−10 µF low
ESR capacitor can be used in the external reference
mode.)
ADCRESEXT
F2
16
16
O
ADC External Current Bias Resistor (24.9 kΩ ±5%)
ADCBGREFIN
E6
164
116
I
Test Pin. Reserved for TI. Must be left unconnected.
AVSSREFBG
E3
12
12
I
ADC Analog GND
AVDDREFBG
E1
13
13
I
ADC Analog Power (3.3-V)
ADCLO
B3
175
127
I
Common Low Side Analog Input. Connect to analog
ground.
VSSA1
VSSA2
F3
15
15
I
ADC Analog GND
C5
165
117
I
ADC Analog GND
VDDA1
VDDA2
F4
14
14
I
ADC Analog 3.3-V Supply
A5
166
118
I
ADC Analog 3.3-V Supply
VSS1
VDD1
C6
163
115
I
ADC Digital GND
A6
162
114
I
ADC Digital 1.8-V (or 1.9-V) Supply
VDDAIO
VSSAIO
B2
1
1
A2
176
128
3.3-V Analog I/O Power Pin
Analog I/O Ground Pin
POWER SIGNALS
VDD
VDD
H1
23
20
L1
37
29
VDD
VDD
P5
56
42
P9
75
56
VDD
VDD
P12
−
63
K12
100
74
VDD
VDD
G12
112
82
C14
128
94
1.8-V or 1.9-V Core Digital Power Pins. See Section 6.2,
Recommended Operating Conditions, for voltage
requirements.
VDD
B10
143
102
VDD
C8
154
110
† Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡ I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.
June 2004 − Revised June 2006
SPRS257C
25
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
NAME
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
DESCRIPTION
POWER SIGNALS (CONTINUED)
VSS
VSS
G4
19
17
K1
32
26
VSS
VSS
L2
38
30
39
P4
52
VSS
VSS
K6
58
−
P8
70
53
VSS
VSS
M10
78
59
L11
86
62
VSS
VSS
K13
99
73
J14
105
−
VSS
VSS
G13
113
−
E14
120
88
VSS
VSS
B14
129
95
D10
142
−
C10
−
103
B8
153
109
VSS
VSS
VDDIO
VDDIO
J4
31
25
L7
64
49
VDDIO
VDDIO
L10
81
−
N14
−
−
VDDIO
VDDIO
G11
114
83
E9
145
104
VDDIO
N8
69
52
Core and Digital I/O Ground Pins
3.3-V I/O Digital Power Pins
GPIO OR EVA SIGNALS
GPIOA0
PWM1 (O)
M12
92
68
I/O/Z
PU
GPIO or PWM Output Pin #1
GPIOA1
PWM2 (O)
M14
93
69
I/O/Z
PU
GPIO or PWM Output Pin #2
GPIOA2
PWM3 (O)
L12
94
70
I/O/Z
PU
GPIO or PWM Output Pin #3
GPIOA3
PWM4 (O)
L13
95
71
I/O/Z
PU
GPIO or PWM Output Pin #4
GPIOA4/PWM5 (O)
K11
98
72
I/O/Z
PU
GPIO or PWM Output Pin #5
GPIOA5
PWM6 (O)
K14
101
75
I/O/Z
PU
GPIO or PWM Output Pin #6
GPIOA6
T1PWM_T1CMP (I)
J11
102
76
I/O/Z
PU
GPIO or Timer 1 Output
† Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡ I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.
26
SPRS257C
June 2004 − Revised June 2006
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
NAME
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
J13
104
77
I/O/Z
PU
GPIOA7
T2PWM_T2CMP (I)
DESCRIPTION
GPIO or Timer 2 Output
GPIO OR EVA SIGNALS (CONTINUED)
GPIOA8
CAP1_QEP1 (I)
H10
106
78
I/O/Z
PU
GPIO or Capture Input #1
GPIOA9
CAP2_QEP2 (I)
H11
107
79
I/O/Z
PU
GPIO or Capture Input #2
GPIOA10/
CAP3_QEPI1 (I)
H12
109
80
I/O/Z
PU
GPIO or Capture Input #3
GPIOA11
TDIRA (I)
F14
116
85
I/O/Z
PU
GPIO or Timer Direction
GPIOA12
TCLKINA (I)
F13
117
86
I/O/Z
PU
GPIO or Timer Clock Input
GPIOA13
C1TRIP (I)
E13
122
89
I/O/Z
PU
GPIO or Compare 1 Output Trip
GPIOA14
C2TRIP (I)
E11
123
90
I/O/Z
PU
GPIO or Compare 2 Output Trip
GPIOA15
C3TRIP (I)
F10
124
91
I/O/Z
PU
GPIO or Compare 3 Output Trip
GPIOB OR EVB SIGNALS
GPIOB0
PWM7 (O)
N2
45
33
I/O/Z
PU
GPIO or PWM Output Pin #7
GPIOB1
PWM8 (O)
P2
46
34
I/O/Z
PU
GPIO or PWM Output Pin #8
GPIOB2
PWM9 (O)
N3
47
35
I/O/Z
PU
GPIO or PWM Output Pin #9
GPIOB3
PWM10 (O)
P3
48
36
I/O/Z
PU
GPIO or PWM Output Pin #10
GPIOB
PWM11 (O)
L4
49
37
I/O/Z
PU
GPIO or PWM Output Pin #11
GPIOB5
PWM12 (O)
M4
50
38
I/O/Z
PU
GPIO or PWM Output Pin #12
GPIOB6/
T3PWM_T3CMP (I)
K5
53
40
I/O/Z
PU
GPIO or Timer 3 Output
GPIOB7/
T4PWM_T4CMP (I)
N5
55
41
I/O/Z
PU
GPIO or Timer 4 Output
GPIOB8/CAP4_QEP3 (I)
M5
57
43
I/O/Z
PU
GPIO or Capture Input #4
GPIOB9/CAP5_QEP4 (I)
M6
59
44
I/O/Z
PU
GPIO or Capture Input #5
GPIOB10/CAP6_QEPI2 (I)
P6
60
45
I/O/Z
PU
GPIO or Capture Input #6
GPIOB11/TDIRB (I)
L8
71
54
I/O/Z
PU
GPIO or Timer Direction
GPIOB12/TCLKINB (I)
K8
72
55
I/O/Z
PU
GPIO or Timer Clock Input
† Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡ I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.
June 2004 − Revised June 2006
SPRS257C
27
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
N6
61
46
I/O/Z
PU
GPIO or Compare 4 Output Trip
GPIOB14/C5TRIP (I)
L6
62
47
I/O/Z
PU
GPIO or Compare 5 Output Trip
GPIOB15/C6TRIP (I)
K7
63
48
I/O/Z
PU
GPIO or Compare 6 Output Trip
NAME
GPIOB13/C4TRIP (I)
DESCRIPTION
GPIOD OR EVA SIGNALS
GPIOD0/
T1CTRIP_PDPINTA (I)
H14
110
81
I/O/Z
PU
Timer 1 Compare Output Trip
GPIOD1/
T2CTRIP/EVASOC (I)
G10
115
84
I/O/Z
PU
Timer 2 Compare Output
Start-of-Conversion EV-A
Trip
or
External
ADC
Trip
or
External
ADC
GPIOD OR EVB SIGNALS
GPIOD5/
T3CTRIP_PDPINTB (I)
P10
79
60
I/O/Z
PU
Timer 3 Compare Output Trip
GPIOD6/
T4CTRIP/EVBSOC (I)
P11
83
61
I/O/Z
PU
Timer 4 Compare Output
Start-of-Conversion EV-B
GPIOE OR INTERRUPT SIGNALS
GPIOE0/XINT1_XBIO (I)
D9
149
106
I/O/Z
−
GPIO or XINT1 or XBIO input
GPIOE1/
XINT2_ADCSOC (I)
D8
151
108
I/O/Z
−
GPIO or XINT2 or ADC start of conversion
GPIOE2
XNMI_XINT13 (I)
E8
150
107
I/O/Z
PU
GPIO or XNMI or XINT13
GPIOF OR SPI SIGNALS
GPIOF0
SPISIMOA (O)
M1
40
31
I/O/Z
−
GPIO or SPI slave in, master out
GPIOF1
SPISOMIA (I)
N1
41
32
I/O/Z
−
GPIO or SPI slave out, master in
GPIOF2
SPICLKA (I/O)
K2
34
27
I/O/Z
−
GPIO or SPI clock
GPIOF3
SPISTEA (I/O)
K4
35
28
I/O/Z
−
GPIO or SPI slave transmit enable
GPIOF OR SCI-A SIGNALS
GPIOF4
SCITXDA (O)
C7
155
111
I/O/Z
PU
GPIO or SCI asynchronous serial port TX data
GPIOF5
SCIRXDA (I)
A7
157
112
I/O/Z
PU
GPIO or SCI asynchronous serial port RX data
GPIOF OR CAN SIGNALS
GPIOF6
CANTXA (O)
N12
87
64
I/O/Z
PU
GPIO or eCAN transmit data
GPIOF7
CANRXA (I)
N13
89
65
I/O/Z
PU
GPIO or eCAN receive data
GPIOF OR McBSP SIGNALS
† Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡ I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.
28
SPRS257C
June 2004 − Revised June 2006
Introduction
Table 2−2. Signal Descriptions† (Continued)
PIN NO.
179-PIN
GHH
AND
ZHH
176-PIN
PGF
128-PIN
PBK
I/O/Z‡
PU/PD§
GPIOF8
MCLKXA (I/O)
J1
28
23
I/O/Z
PU
GPIO or transmit clock
GPIOF9
MCLKRA (I/O)
H2
25
21
I/O/Z
PU
GPIO or receive clock
GPIOF10
MFSXA (I/O)
H4
26
22
I/O/Z
PU
GPIO or transmit frame synch
GPIOF11
MFSRA (I/O)
J2
29
24
I/O/Z
PU
GPIO or receive frame synch
GPIOF12
MDXA (O)
G1
22
19
I/O/Z
−
GPIOF13
MDRA (I)
G2
20
18
I/O/Z
PU
NAME
DESCRIPTION
GPIO or transmitted serial data
GPIO or received serial data
GPIOF OR XF CPU OUTPUT SIGNAL
This pin has three functions:
GPIOF14
XF_XPLLDIS (O)
A11
140
101
I/O/Z
1)
XF − General-purpose output pin.
2)
XPLLDIS − This pin will be sampled during reset to
check if the PLL needs to be disabled. The PLL will
be disabled if this pin is sensed low. HALT and
STANDBY modes cannot be used when the PLL is
disabled.
3)
GPIO − GPIO function
PU
GPIOG OR SCI-B SIGNALS
GPIOG4/SCITXDB (O)
P14
90
66
I/O/Z
−
GPIO or SCI asynchronous serial port transmit data
GPIOG5/SCIRXDB (I)
M13
91
67
I/O/Z
−
GPIO or SCI asynchronous serial port receive data
† Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡ I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled
in boundary-scan mode.
NOTE:
Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached
recommended operating conditions. However, it is acceptable for an I/O pin to ramp along with
the 3.3-V supply.
June 2004 − Revised June 2006
SPRS257C
29
Functional Overview
3
Functional Overview
Memory Bus
TINT0
CPU-Timer 0
CPU-Timer 1
Real-Time JTAG
CPU-Timer 2
TINT2
INT14
Control
PIE
(96 interrupts)†
TINT1
INT[12:1]
External
Interface
(XINTF)‡
Address(19)
Data(16)
XINT13
XNMI
External Interrupt
Control
(XINT1/2/13, XNMI)
INT13
NMI
G
P
I
GPIO Pins
O
SCIA/SCIB
FIFO
SPI
FIFO
McBSP
FIFO
C28x CPU
M
U
X
M0 SARAM
1K x 16
M1 SARAM
1K x 16
L0 SARAM
4K x 16
L1 SARAM
4K x 16
eCAN
EVA/EVB
L2 SARAM
1K X 16
L3 SARAM
1K X 16
16 Channels
XRS
X1/XCLKIN
X2
XF_XPLLDIS
12-Bit ADC
System Control
(Oscillator and PLL
+
Peripheral Clocking
+
Low-Power
Modes
+
WatchDog)
RS
CLKIN
H0 SARAM
8K × 16
Memory Bus
Boot ROM
4K × 16
Peripheral Bus
† 45 of the possible 96 interrupts are used on the devices.
‡ XINTF is available on the R2812 devices only.
Figure 3−1. Functional Block Diagram
30
SPRS257C
June 2004 − Revised June 2006
Functional Overview
3.1
Memory Map
Block
Start Address
On-Chip Memory
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍ
Data Space
0x00 0000
0x00 0040
0x00 0400
Low 64K
(24x/240x Equivalent Data Space)
0x00 0800
0x00 0D00
0x00 0E00
0x00 2000
Prog Space
0x00 7000
0x00 8000
0x00 9000
0x00 A000
0x00 A400
0x00 A800
Data Space
Prog Space
M0 Vector − RAM (32 × 32)
(Enabled if VMAP = 0)
M0 SARAM (1K × 16)
M1 SARAM (1K × 16)
Peripheral Frame 0
PIE Vector - RAM
(256 × 16)
(Enabled if VMAP
= 1, ENPIE = 1)
Reserved
Reserved
Reserved
Reserved
0x00 6000
External Memory XINTF
XINTF Zone 0 (8K × 16, XZCS0AND1)
0x00 2000
XINTF Zone 1 (8K × 16, XZCS0AND1) (Protected)
0x00 4000
Peripheral Frame 1
(Protected)
Peripheral Frame 2
(Protected)
Reserved
Reserved
L0 SARAM (4K × 16)
L1 SARAM (4K × 16)
L2 SARAM (1K × 16)
L3 SARAM (1K × 16)
XINTF Zone 2 (0.5M × 16, XZCS2)
0x08 0000
XINTF Zone 6 (0.5M × 16, XZCS6AND7)
0x10 0000
0x18 0000
Reserved
Reserved
High 64K
(24x/240x Equivalent
Program Space)
0x3F7FF8
0x3F 8000
0x3F A000
128-bit Password (see Note H)
H0 SARAM (8K × 16)
Reserved
0x3F F000
0x3F FFC0
Boot ROM (4K × 16)
(Enabled if MP/MC = 0)
BROM Vector - ROM (32 × 32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
0x3F C000
XINTF Zone 7 (16K × 16, XZCS6AND7)
(Enabled if MP/MC = 1)
XINTF Vector - RAM (32 × 32)
(Enabled if VMAP = 1, MP/MC = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
NOTES: A.
B.
C.
D.
E.
F.
G.
H.
Memory blocks are not to scale.
Reserved locations are reserved for future expansion. Application should not access these areas.
Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both.
Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
“Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
Certain memory ranges are EALLOW protected against spurious writes after configuration.
Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.
The passwords are set to all ones.
Figure 3−2. R2812 Memory Map (See Notes A through H)
June 2004 − Revised June 2006
SPRS257C
31
Functional Overview
Block
Start Address
On-Chip Memory
Data Space
M0 Vector − RAM (32 × 32)
(Enabled if VMAP = 0)
0x00 0040
M0 SARAM (1K × 16)
0x00 0400
Low 64K
(24x/240x Equivalent Data Space)
Prog Space
0x00 0000
0x00 0800
ÍÍÍÍÍÍ
ÍÍÍÍÍÍ
ÍÍÍÍÍÍ
ÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍ
ÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍ
ÍÍÍÍÍÍ
ÍÍÍÍÍÍ
ÍÍÍÍÍÍ
M1 SARAM (1K × 16)
Peripheral Frame 0
0x00 0D00
0x00 0E00
0x00 2000
PIE Vector - RAM
(256 × 16)
(Enabled if VMAP
= 1, ENPIE = 1)
Reserved
Reserved
Reserved
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x00 A000
0x00 A400
0x00 A800
Peripheral Frame 1
(Protected)
Reserved
Peripheral Frame 2
(Protected)
L0 SARAM (4K × 16,)
L1 SARAM (4K × 16)
ÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍ
L2 SARAM (1K × 16)
L3 SARAM (1K × 16)
Reserved
0x3F 7FF8
High 64K
(24x/240x Equivalent
Program Space)
0x3F 8000
LEGEND:
0x3F A000
128-bit Password (see Note F)
H0 SARAM (8K × 16)
Reserved
0x3F F000
0x3F FFC0
Boot ROM (4K × 16)
(Enabled if MP/MC = 0)
BROM Vector - ROM (32 × 32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
NOTES: A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
D. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
F. The passwords are set to all ones.
Figure 3−3. R2811 Memory Map (See Notes A through F)
32
SPRS257C
June 2004 − Revised June 2006
Functional Overview
The low 64K of the memory-address range maps into the data space of the 240x. The “High 64K” of the
memory address range maps into the program space of the 24x/240x. 24x/240x-compatible code will only
execute from the “High 64K” memory area. Hence, the top 32K of H0 SARAM block can be used to run
24x/240x-compatible code (if MP/MC mode is low) or, on the 2812, code can be executed from XINTF Zone 7
(if MP/MC mode is high).
The XINTF consists of five independent zones. One zone has its own chip select and the remaining four zones
share two chip selects. Each zone can be programmed with its own timing (wait states) and to either sample
or ignore external ready signal. This makes interfacing to external peripherals easy and glueless.
NOTE:
The chip selects of XINTF Zone 0 and Zone 1 are merged together into a single chip select
(XZCS0AND1); and the chip selects of XINTF Zone 6 and Zone 7 are merged together into
a single chip select (XZCS6AND7). See Section 3.5, “External Interface, XINTF (2812 only)”,
for details.
Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together so as to enable these blocks
to be “write/read peripheral block protected”. The “protected” mode ensures that all accesses to these blocks
happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory
locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain
peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports
a block protection mode where a region of memory can be protected so as to make sure that operations occur
as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by
default, it will protect the selected zones.
On the 2812, at reset, XINTF Zone 7 is accessed if the XMP/MC pin is pulled high. This signal selects
microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high
memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In
microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows the
user to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC signal on reset
is stored in an MP/MC mode bit in the XINTCNF2 register. The user can change this mode in software and
hence control the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are affected by
XMP/MC.
I/O space is not supported on the 2812 XINTF.
The wait states for the various spaces in the memory map area are listed in Table 3−1.
Table 3−1. Wait States
AREA
WAIT-STATES
M0 and M1 SARAMs
0-wait
Fixed
Peripheral Frame 0
0-wait
Fixed
Peripheral Frame 1
0-wait (writes)
2-wait (reads)
Fixed
Peripheral Frame 2
0-wait (writes)
2-wait (reads)
Fixed
L0, L1, L2, and L3 SARAMs
0-wait
H0 SARAM
0-wait
Fixed
Boot-ROM
1-wait
Fixed
XINTF
Programmable,
1-wait minimum
June 2004 − Revised June 2006
COMMENTS
Programmed via the XINTF registers.
Cycles can be extended by external memory or peripheral.
0-wait operation is not possible.
SPRS257C
33
Functional Overview
3.2
3.2.1
Brief Descriptions
C28x CPU
The C28x DSP generation is the newest member of the TMS320C2000 DSP platform. The C28x is source
code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant
software investment. Additionally, the C28x is a very efficient C/C++ engine, hence enabling users to develop
not only their system control software in a high-level language, but also enables math algorithms to be
developed using C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically
are handled by microcontroller devices. This efficiency removes the need for a second processor in many
systems. The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x
to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive
floating-point processor solution. Add to this the fast interrupt response with automatic context save of critical
registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency.
The C28x has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables
the C28x to execute at high speeds without resorting to expensive high-speed memories. Special
branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional
operations further improve performance.
3.2.2
Memory Bus (Harvard Bus Architecture)
As with many DSP type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The R28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and
write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single
cycle 32-bit operations. The multiple-bus architecture, commonly termed “Harvard Bus”, enables the R28x
to fetch an instruction, read a data value, and write a data value in a single cycle. All peripherals and memories
attached to the memory bus prioritize memory accesses.
Generally, the priority of memory bus accesses can be summarized as follows:
Highest:
Data Writes (Simultaneous data and program writes cannot occur
on the memory bus.)
Program Writes (Simultaneous data and program writes cannot occur
on the memory bus.)
Data Reads
Program Reads (Simultaneous program reads and fetches cannot occur
on the memory bus.)
Lowest:
3.2.3
Fetches
(Simultaneous program reads and fetches cannot occur
on the memory bus.)
Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, R281x
adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the
various busses that make up the processor “Memory Bus” into a single bus consisting of 16 address lines and
16 or 32 data lines and associated control signals. Two versions of the peripheral bus are supported on R281x.
One version only supports 16-bit accesses (called peripheral frame 2) and this retains compatibility with
C240x-compatible peripherals. The other version supports both 16- and 32-bit accesses (called peripheral
frame 1).
C28x and TMS320C2000 are trademarks of Texas Instruments.
34
SPRS257C
June 2004 − Revised June 2006
Functional Overview
3.2.4
Real-Time JTAG and Analysis
R281x implements the standard IEEE 1149.1 JTAG interface. Additionally, R281x supports real-time mode
of operation whereby the contents of memory, peripheral and register locations can be modified while the
processor is running and executing code and servicing interrupts. The user can also single step through
non-time critical code while enabling time-critical interrupts to be serviced without interference. R281x
implements the real-time mode in hardware within the CPU. This is a unique feature to R281x, no software
monitor is required. Additionally, special analysis hardware is provided which allows the user to set hardware
breakpoint or data/address watch-points and generate various user selectable break events when a match
occurs.
3.2.5
External Interface (XINTF) (2812 Only)
This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The
chip-select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single
chip-select; Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed with
a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for
extending wait states externally or not. The programmable wait-state, chip-select and programmable strobe
timing enables glueless interface to external memories and peripherals.
3.2.6
M0, M1 SARAMs
All C28x devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 block overlaps the 240x device B0, B1, B2 RAM blocks
and hence the mapping of data variables on the 240x devices can remain at the same physical address on
C28x devices. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both
program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The
partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer.
This makes for easier programming in high-level languages.
3.2.7
L0, L1, L2, L3, H0 SARAMs
R281x contains an additional 18K x 16 of single-access RAM (SARAM), divided into 5 blocks (4K + 4K +1K
+1K+ 8K). Each block can be independently accessed, minimizing pipeline stalls. Each block is mapped to
both program and data space.
3.2.8
Boot ROM
The Boot ROM is factory-programmed with boot-loading software. The Boot ROM program executes after
device reset and checks several GPIO pins to determine which boot mode to enter. For example, the user can
select to download new software to internal RAM through one of several serial ports. Other boot modes exist
as well. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math-related
algorithms. Table 3−2 shows the details of how various boot modes may be invoked. See the TMS320F28x
DSP Boot ROM Reference Guide (literature number SPRS095), for more information.
June 2004 − Revised June 2006
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Functional Overview
Table 3−2. Boot Mode Selection
GPIOF4/
(SCITXDA)
GPIOF12/
(MDXA)
GPIOF3/
(SPISTEA)
GPIOF2/
(SPICLK)‡
PU
No PU
No PU
No PU
Reserved
1
x
x
x
Call SPI_Boot to load from an external serial SPI EEPROM
0
1
x
x
Call SCI_Boot to load from SCI-A
0
0
1
1
Jump to H0 SARAM address 0x3F 8000§
0
0
1
0
Reserved
0
0
0
1
Call Parallel_Boot to load from GPIO Port B
0
0
0
0
BOOT MODE SELECTED
(Internal PU status†)
† PU = pin has an internal pullup No PU = pin does not have an internal pullup
‡ Extra care must be taken due to any effect toggling SPICLK to select a boot mode may have on external logic.
§ If the boot mode selected is H0, then no external code is loaded by the bootloader.
3.2.9
Security
R281x devices contain a non−utilizable code security module for compatibility with C281x and F281x devices.
The passwords for the security module are hard-wired in the device as all 0xFFFF. After a device reset, the
L0 and L1 SARAM blocks are in a locked condition until a dummy read of the passwords is performed. The
R281x Boot ROM performs a dummy read of the password locations. If execution after reset begins directly
in external memory on R2812 devices (i.e., MP/MC =1 ), the user should perform 8 dummy reads, one each
from address 0x3F7FF8 through 0x3F7FFF.
3.2.10 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE
block can support up to 96 peripheral interrupts. On R281x, 45 of the possible 96 interrupts are used by
peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt
lines (INT1 to INT12). Each of the 96 interrupts is, supported by its own vector stored in a dedicated RAM block
that can be overwritten by the user. The vector is, automatically fetched by the CPU on servicing the interrupt.
It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly
respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual
interrupt can be enabled/disabled within the PIE block.
3.2.11
External Interrupts (XINT1, 2, 13, XNMI)
R281x supports three masked external interrupts (XINT1, 2, 13). XINT13 is combined with one non-masked
external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the interrupts can be selected
for negative or positive edge triggering and can also be enabled/disabled (including the XNMI). The masked
interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is
detected. This counter can be used to accurately time stamp the interrupt.
3.2.12 Oscillator and PLL
R281x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A PLL
is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed on-the-fly in
software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer
to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.
3.2.13 Watchdog
R281x supports a watchdog timer. The user software must regularly reset the watchdog counter within a
certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can be
disabled if necessary.
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Functional Overview
3.2.14 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when
a peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and the event
managers, CAP and QEP blocks can be scaled relative to the CPU clock. This enables the timing of
peripherals to be decoupled from increasing CPU clock speeds.
3.2.15 Low-Power Modes
R281x devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only
those peripherals that need to function during IDLE are left operating. An enabled interrupt
from an active peripheral will wake the processor from IDLE mode.
STANDBY:
Turn off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.
An external interrupt event will wake the processor and the peripherals. Execution begins
on the next valid cycle after detection of the interrupt event.
HALT:
Turn off oscillator. This mode basically shuts down the device and places it in the lowest
possible power consumption mode. Only a reset or XNMI will wake the device from this
mode.
3.2.16 Peripheral Frames 0, 1, 2 (PFn)
R281x segregates peripherals into three sections. The mapping of peripherals is as follows:
PF0:
XINTF:
External Interface Configuration Registers (2812 only)
PIE:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Timers:
CPU-Timers 0, 1, 2 Registers
PF1:
eCAN:
eCAN Mailbox and Control Registers
PF2:
SYS:
System Control Registers
GPIO:
GPIO MUX Configuration and Control Registers
EV:
Event Manager (EVA/EVB) Control Registers
McBSP:
McBSP Control and TX/RX Registers
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
SPI:
Serial Peripheral Interface (SPI) Control and RX/TX Registers
ADC:
12-Bit ADC Registers
3.2.17 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This enables the user
to use a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are configured
as inputs. The user can then individually program each pin for GPIO mode or Peripheral Signal mode. For
specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise
glitches.
3.2.18 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling.
The timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero.
The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter
reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for Real-Time
OS (RTOS)/BIOS applications. CPU-Timer 2 is reserved for the DSP/BIOS real-time operating system
(DSP/BIOS RTOS), and is connected to INT14 of the CPU. CPU-Timer 1 is for general use, and is connected
to INT13 of the CPU. CPU-Timer 0 is also for general use, and is connected to the PIE block.
June 2004 − Revised June 2006
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Functional Overview
3.2.19 Control Peripherals
R281x supports the following peripherals which are used for embedded control and communication:
EV:
The event manager module includes general-purpose timers, full-compare/PWM units,
capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event
managers are provided which enable two three-phase motors to be driven or four
two-phase motors. The event managers on R281x are compatible to the event managers
on the 240x devices (with some minor enhancements).
ADC:
The ADC block is a 12-bit converter, single ended, 16-channels. It contains two
sample-and-hold units for simultaneous sampling.
3.2.20 Serial Port Peripherals
R281x supports the following serial communication peripherals:
3.3
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time stamping
of messages, and is CAN 2.0B-compliant.
McBSP:
This is the multichannel buffered serial port that is used to connect to E1/T1 lines,
phone-quality codecs for modem applications or high-quality stereo-quality Audio DAC
devices. The McBSP receive and transmit registers are supported by a 16-level FIFO. This
significantly reduces the overhead for servicing this peripheral.
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display drivers,
and ADCs. Multi-device communications are supported by the master/slave operation of
the SPI. On R281x, the port supports a 16-level, receive and transmit FIFO for reducing
servicing overhead.
SCI:
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On R281x, the port supports a 16-level, receive and transmit FIFO for
reducing servicing overhead.
Register Map
R281x devices contain three peripheral register spaces. The spaces are categorized as follows:
38
•
Peripheral Frame 0:
These are peripherals that are mapped directly to the CPU memory bus.
See Table 3−3.
•
Peripheral Frame 1:
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 3−4.
•
Peripheral Frame 2:
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 3−5.
SPRS257C
June 2004 − Revised June 2006
Functional Overview
Table 3−3. Peripheral Frame 0 Registers†
NAME
ACCESS TYPE‡
ADDRESS RANGE
SIZE (x16)
Device Emulation Registers
0x00 0880
0x00 09FF
384
reserved
0x00 0A00
0x00 0B1F
288
XINTF Registers
0x00 0B20
0x00 0B3F
32
reserved
0x00 0B40
0x00 0BFF
192
CPU-TIMER0/1/2 Registers
0x00 0C00
0x00 0C3F
64
reserved
0x00 0C40
0x00 0CDF
160
PIE Registers
0x00 0CE0
0x00 0CFF
32
Not EALLOW protected
PIE Vector Table
0x00 0D00
0x00 0DFF
256
EALLOW protected
Reserved
0x00 0E00
0x00 0FFF
512
EALLOW protected
Not EALLOW protected
Not EALLOW protected
† Registers in Frame 0 support 16-bit and 32-bit accesses.
‡ If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS instruction
disables writes. This prevents stray code or pointers from corrupting register contents.
Table 3−4. Peripheral Frame 1 Registers¶
NAME
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
eCAN Registers
0x00 6000
0x00 60FF
256
(128 x 32)
Some eCAN control registers (and selected bits in other eCAN
control registers) are EALLOW-protected.
eCAN Mailbox RAM
0x00 6100
0x00 61FF
256
(128 x 32)
Not EALLOW-protected
reserved
0x00 6200
0x00 6FFF
3584
¶ The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
Table 3−5. Peripheral Frame 2 Registers†
NAME
ADDRESS RANGE
SIZE (x16)
reserved
0x00 7000
0x00 700F
16
System Control Registers
0x00 7010
0x00 702F
32
reserved
0x00 7030
0x00 703F
16
SPI-A Registers
0x00 7040
0x00 704F
16
ACCESS TYPE
EALLOW Protected
Not EALLOW Protected
† Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
June 2004 − Revised June 2006
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Functional Overview
Peripheral Frame 2 Registers† (Continued)
NAME
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
SCI-A Registers
0x00 7050
0x00 705F
16
reserved
0x00 7060
0x00 706F
16
External Interrupt Registers
0x00 7070
0x00 707F
16
reserved
0x00 7080
0x00 70BF
64
GPIO MUX Registers
0x00 70C0
0x00 70DF
32
EALLOW Protected
GPIO Data Registers
0x00 70E0
0x00 70FF
32
Not EALLOW Protected
ADC Registers
0x00 7100
0x00 711F
32
Not EALLOW Protected
reserved
0x00 7120
0x00 73FF
736
EV-A Registers
0x00 7400
0x00 743F
64
reserved
0x00 7440
0x00 74FF
192
EV-B Registers
0x00 7500
0x00 753F
64
reserved
0x00 7540
0x00 774F
528
SCI-B Registers
0x00 7750
0x00 775F
16
reserved
0x00 7760
0x00 77FF
160
McBSP Registers
0x00 7800
0x00 783F
64
reserved
0x00 7840
0x00 7FFF
1984
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
† Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
3.4
Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. The registers are defined in Table 3−6.
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Functional Overview
Table 3−6. Device Emulation Registers
NAME
ADDRESS RANGE
SIZE (x16)
DEVICECNF
0x00 0880
0x00 0881
2
Device Configuration Register
PARTID
0x00 0882
1
0x0003 − R281x
REVID
0x00 0883
1
Revision ID Register (0x0001 − Silicon Rev. A)
Revision ID Register (0x0002 − Silicon Rev. B)
PROTSTART
0x00 0884
1
Block Protection Start Address Register
PROTRANGE
0x00 0885
1
Block Protection Range Address Register
reserved
0x00 0886
0x00 09FF
378
3.5
DESCRIPTION
External Interface, XINTF (2812 Only)
This section gives a top-level view of the external interface (XINTF) that is implemented on the 2812 devices.
The external interface is a non-multiplexed asynchronous bus, similar to the C240x external interface. The
external interface on the 2812 is mapped into five fixed zones shown in Figure 3−4.
Figure 3−4 shows the 2812 XINTF signals.
The operation and timing of the external interface, can be controlled by the registers listed in Table 3−7.
Table 3−7. XINTF Configuration and Control Register Mappings
ADDRESS
SIZE (x16)
DESCRIPTION
XTIMING0
NAME
0x00 0B20
2
XINTF Timing Register, Zone 0 can access as two 16-bit registers or one 32-bit register
XTIMING1
0x00 0B22
2
XINTF Timing Register, Zone 1 can access as two 16-bit registers or one 32-bit register
XTIMING2
0x00 0B24
2
XINTF Timing Register, Zone 2 can access as two 16-bit registers or one 32-bit register
XTIMING6
0x00 0B2C
2
XINTF Timing Register, Zone 6 can access as two 16-bit registers or one 32-bit register
XTIMING7
0x00 0B2E
2
XINTF Timing Register, Zone 7 can access as two 16-bit registers or one 32-bit register
XINTCNF2
0x00 0B34
2
XINTF Configuration Register can access as two 16-bit registers or one 32-bit register
XBANK
0x00 0B38
1
XINTF Bank Control Register
XREVISION
0x00 0B3A
1
XINTF Revision Register
3.5.1
Timing Registers
XINTF signal timing can be tuned to match specific external device requirements such as setup and hold times
to strobe signals for contention avoidance and maximizing bus efficiency. The timing parameters can be
configured individually for each zone. This allows the programmer to maximize the efficiency of the bus, based
on the type of memory or peripheral that the user needs to access. All XINTF timing values are with respect
to XTIMCLK, which is equal to or one-half of the SYSCLKOUT rate, as shown in Figure 6−26.
For detailed information on the XINTF timing and configuration register bit fields, see the TMS320F28x DSP
External Interface (XINTF) Reference Guide (literature number SPRU067).
3.5.2
XREVISION Register
The XREVISION register contains a unique number to identify the particular version of XINTF used in the
product. For the 2812, this register will be configured as described in Table 3−8.
Table 3−8. XREVISION Register Bit Definitions
BIT(S)
15−0
NAME
TYPE
REVISION
June 2004 − Revised June 2006
R
RESET
DESCRIPTION
0x0004
Current XINTF Revision. For internal use/reference. Test purposes only. Subject to
change.
SPRS257C
41
Functional Overview
Data Space
Prog Space
0x00 0000
XD(15:0)
XA(18:0)
0x00 2000
0x00 4000
XINTF Zone 0
(8K × 16)
XINTF Zone 1
(8K × 16)
XZCS0
XZCS1
XZCS0AND1
0x00 6000
0x08 0000
XINTF Zone 2
(512K × 16)
XZCS2
0x10 0000
XINTF Zone 6
(512K × 16)
XZCS6
XZCS6AND7
0x18 0000
0x3F C000
0x40 0000
XINTF Zone 7
(16K × 16)
(mapped here if MP/MC = 1)
XZCS7
XWE
XRD
XR/W
XREADY
XMP/MC
XHOLD
XHOLDA
XCLKOUT (see Note E)
NOTES: A. The mapping of XINTF Zone 7 is dependent on the XMP/MC device input signal and the MP/MC mode bit (bit 8 of XINTCNF2
register). Zones 0, 1, 2, and 6 are always enabled.
B. Each zone can be programmed with different wait states, setup and hold timing, and is supported by zone chip selects
(XZCS0AND1, XZCS2, XZCS6AND7), which toggle when an access to a particular zone is performed. These features enable
glueless connection to many external memories and peripherals.
C. The chip selects for Zone 0 and 1 are ANDed internally together to form one chip select (XZCS0AND1). Any external memory
that is connected to XZCS0AND1 is dually mapped to both Zones 0 and Zone 1.
D. The chip selects for Zone 6 and 7 are ANDed internally together to form one chip select (XZCS6AND7). Any external memory
that is connected to XZCS6AND7 is dually mapped to both Zones 6 and Zone 7. This means that if Zone 7 is disabled (via the
MP/MC mode) then any external memory is still accessible via Zone 6 address space.
E. XCLKOUT is also pinned out on the 2810 and 2811.
Figure 3−4. External Interface Block Diagram
42
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June 2004 − Revised June 2006
Functional Overview
3.6
Interrupts
Figure 3−5 shows how the various interrupt sources are multiplexed within R281x devices.
Peripherals (SPI, SCI, McBSP, CAN, EV, ADC)
(41 Interrupts)
WDINT
WAKEINT
INT1 to INT12
96 Interrupts†
LPMINT
PIE
Interrupt Control
Watchdog
Low-Power Modes
XINT1
XINT1CR(15:0)
XINT1CTR(15:0)
Interrupt Control
XINT2
XINT2CR(15:0)
C28x CPU
XINT2CTR(15:0)
TINT0
TIMER 0
TINT2
INT14
TIMER 2 (for RTOS)
TINT1
TIMER 1
MUX
INT13
GPIO
MUX
select
enable
NMI
Interrupt Control
XNMI_XINT13
XNMICR(15:0)
XNMICTR(15:0)
† Out of a possible 96 interrupts, 45 are currently used by peripherals.
Figure 3−5. Interrupt Sources
Figure 3−6 shows how the interrupts are multiplexed using the PIE block. Eight PIE block interrupts are
grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96
possible interrupts. On R281x, 45 of these are used by peripherals as shown in Table 3−9.
June 2004 − Revised June 2006
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Functional Overview
IFR(12:1)
INTM
IER(12:1)
INT1
INT2
1
CPU
MUX
0
INT11
INT12
(Flag)
INTx
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
MUX
PIEACKx
(Enable/Flag)
Global
Enable
(Enable)
(Enable)
(Flag)
PIEIERx(8:1)
PIEIFRx(8:1)
From
Peripherals or
External
Interrupts
Figure 3−6. Multiplexing of Interrupts Using the PIE Block
Table 3−9. PIE Peripheral Interrupts†
CPU
INTERRUPTS
PIE INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INT1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
XINT2
INT2
reserved
T1OFINT
(EV-A)
T1UFINT
(EV-A)
INT3
reserved
CAPINT3
(EV-A)
INT4
reserved
INT5
INTx.4
INTx.3
INTx.2
INTx.1
XINT1
reserved
PDPINTB
(EV-B)
PDPINTA
(EV-A)
T1CINT
(EV-A)
T1PINT
(EV-A)
CMP3INT
(EV-A)
CMP2INT
(EV-A)
CMP1INT
(EV-A)
CAPINT2
(EV-A)
CAPINT1
(EV-A)
T2OFINT
(EV-A)
T2UFINT
(EV-A)
T2CINT
(EV-A)
T2PINT
(EV-A)
T3OFINT
(EV-B)
T3UFINT
(EV-B)
T3CINT
(EV-B)
T3PINT
(EV-B)
CMP6INT
(EV-B)
CMP5INT
(EV-B)
CMP4INT
(EV-B)
reserved
CAPINT6
(EV-B)
CAPINT5
(EV-B)
CAPINT4
(EV-B)
T4OFINT
(EV-B)
T4UFINT
(EV-B)
T4CINT
(EV-B)
T4PINT
(EV-B)
INT6
reserved
reserved
MXINT
(McBSP)
MRINT
(McBSP)
reserved
reserved
SPITXINTA
(SPI)
SPIRXINTA
(SPI)
INT7
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
INT8
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
ECAN0INT
(CAN)
SCITXINTB
(SCI-B)
SCIRXINTB
(SCI-B)
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
INT9
reserved
reserved
ECAN1INT
(CAN)
INT10
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
INT11
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
INT12
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
† Out of the 96 possible interrupts, 45 interrupts are currently used. The remaining interrupts are reserved for future devices. These interrupts can
be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a
peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR.
To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 12).
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Functional Overview
Table 3−10. PIE Configuration and Control Registers
NAME
ADDRESS
Size (x16)
DESCRIPTION
PIECTRL
0x0000−0CE0
1
PIE, Control Register
PIEACK
0x0000−0CE1
1
PIE, Acknowledge Register
PIEIER1
0x0000−0CE2
1
PIE, INT1 Group Enable Register
PIEIFR1
0x0000−0CE3
1
PIE, INT1 Group Flag Register
PIEIER2
0x0000−0CE4
1
PIE, INT2 Group Enable Register
PIEIFR2
0x0000−0CE5
1
PIE, INT2 Group Flag Register
PIEIER3
0x0000−0CE6
1
PIE, INT3 Group Enable Register
PIEIFR3
0x0000−0CE7
1
PIE, INT3 Group Flag Register
PIEIER4
0x0000−0CE8
1
PIE, INT4 Group Enable Register
PIEIFR4
0x0000−0CE9
1
PIE, INT4 Group Flag Register
PIEIER5
0x0000−0CEA
1
PIE, INT5 Group Enable Register
PIEIFR5
0x0000−0CEB
1
PIE, INT5 Group Flag Register
PIEIER6
0x0000−0CEC
1
PIE, INT6 Group Enable Register
PIEIFR6
0x0000−0CED
1
PIE, INT6 Group Flag Register
PIEIER7
0x0000−0CEE
1
PIE, INT7 Group Enable Register
PIEIFR7
0x0000−0CEF
1
PIE, INT7 Group Flag Register
PIEIER8
0x0000−0CF0
1
PIE, INT8 Group Enable Register
PIEIFR8
0x0000−0CF1
1
PIE, INT8 Group Flag Register
PIEIER9
0x0000−0CF2
1
PIE, INT9 Group Enable Register
PIEIFR9
0x0000−0CF3
1
PIE, INT9 Group Flag Register
PIEIER10
0x0000−0CF4
1
PIE, INT10 Group Enable Register
PIEIFR10
0x0000−0CF5
1
PIE, INT10 Group Flag Register
PIEIER11
0x0000−0CF6
1
PIE, INT11 Group Enable Register
PIEIFR11
0x0000−0CF7
1
PIE, INT11 Group Flag Register
PIEIER12
0x0000−0CF8
1
PIE, INT12 Group Enable Register
PIEIFR12
0x0000−0CF9
1
PIE, INT12 Group Flag Register
Reserved
0x0000−0CFA
0x0000−0CFF
6
Reserved
Note:
The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected.
June 2004 − Revised June 2006
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Functional Overview
3.6.1
External Interrupts
Table 3−11. External Interrupt Registers
ADDRESS
SIZE (x16)
XINT1CR
NAME
0x00 7070
1
XINT1 control register
DESCRIPTION
XINT2CR
0x00 7071
1
XINT2 control register
reserved
0x00 7072
0x00 7076
5
XNMICR
0x00 7077
1
XNMI control register
XINT1CTR
0x00 7078
1
XINT1 counter register
XINT2CTR
0x00 7079
1
XINT2 counter register
reserved
0x00 707A
0x00 707E
5
XNMICTR
0x00 707F
1
XNMI counter register
Each external interrupt can be enabled/disabled or qualified using positive or negative going edge. For more
information, see the TMS320F28x System Control and Interrupts Reference Guide (literature number
SPRU078).
46
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Functional Overview
3.7
System Control
This section describes R281x oscillator, PLL and clocking mechanisms, the watchdog function and the low
power modes. Figure 3−7 shows the various clock and reset domains in R281x devices that will be discussed.
Reset
XRS
Watchdog
Block
SYSCLKOUT
Peripheral Reset
CLKIN
X1/XCLKIN
C28x
CPU
PLL
OSC
Power
Modes
Control
System
Control
Registers
eCAN
Peripheral Bus
Low-Speed Prescaler
I/O
LSPCLK
Low-Speed Peripherals
SCI-A/B, SPI, McBSP
I/O
GPIOs
GPIO
MUX
HSPCLK
High-Speed Prescaler
Peripheral
Registers
XF_XPLLDIS
Clock Enables
Peripheral
Registers
Peripheral
Registers
X2
High-Speed Peripherals
EV-A/B
I/O
HSPCLK
ADC
Registers
12-Bit ADC
16 ADC Inputs
NOTE A: CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.
Figure 3−7. Clock and Reset Domains
The PLL, clocking, watchdog and low-power modes are controlled by the registers listed in Table 3−12.
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47
Functional Overview
Table 3−12. PLL, Clocking, Watchdog, and Low-Power Mode Registers†
NAME
ADDRESS
SIZE (x16)
reserved
0x00 7010
0x00 7017
8
reserved
0x00 7018
1
reserved
0x00 7019
1
HISPCP
0x00 701A
1
High-Speed Peripheral Clock Prescaler Register for HSPCLK clock
LOSPCP
DESCRIPTION
0x00 701B
1
Low-Speed Peripheral Clock Prescaler Register for LSPCLK clock
PCLKCR
0x00 701C
1
Peripheral Clock Control Register
reserved
0x00 701D
1
LPMCR0
0x00 701E
1
Low Power Mode Control Register 0
LPMCR1
0x00 701F
1
Low Power Mode Control Register 1
reserved
0x00 7020
1
PLLCR
0x00 7021
1
PLL Control Register‡
SCSR
0x00 7022
1
System Control & Status Register
WDCNTR
0x00 7023
1
Watchdog Counter Register
reserved
0x00 7024
1
WDKEY
0x00 7025
1
reserved
0x00 7026
0x00 7028
3
WDCR
0x00 7029
1
reserved
0x00 702A
0x00 702F
6
Watchdog Reset Key Register
Watchdog Control Register
† All of the above registers can only be accessed, by executing the EALLOW instruction.
‡ The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio) will not
reset PLLCR.
3.7.1
OSC and PLL Block
Figure 3−8 shows the OSC and PLL block on R281x.
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Functional Overview
XPLLDIS
Latch
XF_XPLLDIS
XRS
OSCCLK (PLL Disabled)
X1/XCLKIN
XCLKIN
0
CLKIN
On-Chip
Oscillator
(OSC)
PLL
Bypass
/2
CPU
SYSCLKOUT
1
4-Bit PLL Select
X2
PLL
4-Bit PLL Select
PLL Block
Figure 3−8. OSC and PLL Block
The on-chip oscillator circuit enables a crystal to be attached to R281x devices using the X1/XCLKIN and X2
pins. If a crystal is not used, then an external oscillator can be directly connected to the X1/XCLKIN pin and
the X2 pin is left unconnected. The logic-high level in this case should not exceed VDD. The PLLCR bits [3:0]
set the clocking ratio.
Table 3−13. PLLCR Register Bit Definitions
BIT(S)
NAME
TYPE
XRS RESET†
15:4
reserved
R=0
0:0
DESCRIPTION
SYSCLKOUT = (XCLKIN * n)/2, where n is the PLL multiplication factor.
3:0
DIV
R/W
0,0,0,0
Bit Value
n
SYSCLKOUT
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PLL Bypassed
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
XCLKIN/2
XCLKIN/2
XCLKIN
XCLKIN * 1.5
XCLKIN * 2
XCLKIN * 2.5
XCLKIN * 3
XCLKIN * 3.5
XCLKIN * 4
XCLKIN * 4.5
XCLKIN * 5
Reserved
Reserved
Reserved
Reserved
Reserved
† The PLLCR register is reset to a known state by the XRS reset line. If a reset is issued by the debugger, the PLL clocking ratio is not changed.
3.7.2
Loss of Input Clock
In PLL enabled mode, if the input clock XCLKIN or the oscillator clock is removed or absent, the PLL will still
issue a “limp-mode” clock. The limp-mode clock will continue to clock the CPU and peripherals at a typical
frequency of 1−4 MHz. The PLLCR register should have been written to with a non-zero value for this feature
to work.
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49
Functional Overview
Normally, when the input clocks are present, the watchdog counter will decrement to initiate a watchdog reset
or WDINT interrupt. However, when the external input clock fails, the watchdog counter will stop decrementing
(i.e., the watchdog counter does not change with the limp-mode clock). This condition could be used by the
application firmware to detect the input clock failure and initiate necessary shut-down procedure for the
system.
3.7.3
PLL-Based Clock Module
R281x has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for
the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control to select different
CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be
re-enabled (if need be) after the PLL module has stabilized, which takes 131 072 XCLKIN cycles.
The PLL-based clock module provides two modes of operation:
•
Crystal-operation
This mode allows the use of an external crystal/resonator to provide the time base to the device.
•
External clock source operation
This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external
clock source input on the X1/XCLKIN pin.
X1/XCLKIN
CL1
(see Note A)
X2
Crystal
X1/XCLKIN
CL2
(see Note A)
(a)
X2
External Clock Signal
(Toggling 0 −VDD)
NC
(b)
NOTE A: TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The
resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding
the proper tank component values that will ensure start-up and stability over the entire operating range.
Figure 3−9. Recommended Crystal / Clock Connection
Table 3−14. Possible PLL Configuration Modes
PLL MODE
REMARKS
SYSCLKOUT
PLL Disabled
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely
disabled. Clock input to the CPU (CLKIN) is directly derived from the clock
signal present at the X1/XCLKIN pin.
PLL Bypassed
Default PLL configuration upon power-up, if PLL is not disabled. The PLL
itself is bypassed. However, the /2 module in the PLL block divides the clock
input at the X1/XCLKIN pin by two before feeding it to the CPU.
XCLKIN/2
PLL Enabled
Achieved by writing a non-zero value “n” into PLLCR register. The /2 module
in the PLL block now divides the output of the PLL by two before feeding it to
the CPU.
(XCLKIN * n) / 2
3.7.4
XCLKIN
External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:
50
•
Fundamental mode, parallel resonant
•
CL (load capacitance) = 12 pF
•
CL1 = CL2 = 24 pF
•
Cshunt = 6 pF
•
ESR range = 25 to 40 Ω
SPRS257C
June 2004 − Revised June 2006
Functional Overview
3.7.5
Watchdog Block
The watchdog block on R281x is identical to the one used on the 240x devices. The watchdog module
generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter
has reached its maximum value. To prevent this, the user disables the counter or the software must
periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog
counter. Figure 3−10 shows the various functional blocks within the watchdog module.
WDCR (WDPS(2:0))
WDCR (WDDIS)
WDCNTR(7:0)
OSCCLK
Watchdog
Prescaler
/512
WDCLK
8-Bit
Watchdog
Counter
CLR
Clear Counter
Internal
Pullup
WDKEY(7:0)
Generate
Output Pulse
(512 OSCCLKs)
Bad Key
Watchdog
55 + AA
Key Detector
Good Key
WDRST
WDINT
XRS
Core-reset
WDCR (WDCHK(2:0))
WDRST
(See Note A)
1
0
Bad
WDCHK
Key
SCSR (WDENINT)
1
NOTE A: The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3−10. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional
is the watchdog. The Watchdog module will run off the PLL clock or the oscillator clock. The WDINT signal
is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 3.7.6,
Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is
the WATCHDOG.
3.7.6
Low-Power Modes Block
The low-power modes on R281x are similar to the 240x devices. Table 3−15 summarizes the various modes.
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Functional Overview
Table 3−15. R281x Low-Power Modes
EXIT†
MODE
LPM(1:0)
OSCCLK
CLKIN
SYSCLKOUT
Normal
X,X
on
on
on
−
on‡
XRS,
WDINT,
Any Enabled Interrupt,
XNMI
Debugger§
off
off
XRS,
WDINT,
XINT1,
XNMI,
T1/2/3/4CTRIP,
C1/2/3/4/5/6TRIP,
SCIRXDA,
SCIRXDB,
CANRX,
Debugger§
off
off
XRS,
XNMI,
Debugger§
IDLE
0,0
on
on
on
STANDBY
0,1
(watchdog still running)
off
HALT
1,X
(oscillator and PLL turned off,
watchdog not functional)
† The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will exit the
low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the IDLE mode will not
be exited and the device will go back into the indicated low power mode.
‡ The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is still functional
while on the 24x/240x the clock is turned off.
§ On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt or an XNMI that is
recognized by the processor. The LPM block performs no tasks during
this mode as long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode:
All other signals (including XNMI) will wake the device from STANDBY
mode if selected by the LPMCR1 register. The user will need to select
which signal(s) will wake the device. The selected signal(s) are also
qualified by the OSCCLK before waking the device. The number of
OSCCLKs is specified in the LPMCR0 register.
HALT Mode:
Only the XRS and XNMI external signals can wake the device from
HALT mode. The XNMI input to the core has an enable/disable bit.
Hence, it is safe to use the XNMI signal for this function.
NOTE: The low-power modes do not affect the state of the output pins (PWM pins included). They will be
in whatever state the code left them when the IDLE instruction was executed.
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Peripherals
4
Peripherals
The integrated peripherals of R281x are described in the following subsections:
4.1
•
Three 32-bit CPU-Timers
•
Two event-manager modules (EVA, EVB)
•
Enhanced analog-to-digital converter (ADC) module
•
Enhanced controller area network (eCAN) module
•
Multichannel buffered serial port (McBSP) module
•
Serial communications interface modules (SCI-A, SCI-B)
•
Serial peripheral interface (SPI) module
•
Digital I/O and shared pin functions
32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on R281x devices (CPU-TIMER0/1/2).
CPU-Timer 1 is reserved for TI system functions and Timer 2 is reserved for DSP/BIOS. CPU-Timer 0 can be
used in user applications. These timers are different from the general-purpose (GP) timers that are present
in the Event Manager modules (EVA, EVB).
NOTE: If the application is not using DSP/BIOS, then CPU-Timers 1 and 2 can be used in the
application.
Reset
Timer Reload
16-Bit Timer Divide-Down
TDDRH:TDDR
SYSCLKOUT
TCR.4
(Timer Start Status)
32-Bit Timer Period
PRDH:PRD
16-Bit Prescale Counter
PSCH:PSC
Borrow
32-Bit Counter
TIMH:TIM
Borrow
TINT
Figure 4−1. CPU-Timers
June 2004 − Revised June 2006
SPRS257C
53
Peripherals
In R281x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4−2.
INT1
to
INT12
PIE
TINT0
CPU-TIMER 0
C28x
TINT1
INT13
CPU-TIMER 1
(Reserved for TI
system functions)
XINT13
INT14
TINT2
CPU-TIMER 2
(Reserved for
DSP/BIOS)
NOTES: A. The timer registers are connected to the Memory Bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 4−2. CPU-Timer Interrupts Signals and Output Signal (See Notes A and B)
The general operation of the timer is as follows: The 32-bit counter register “TIMH:TIM” is loaded with the value
in the period register “PRDH:PRD”. The counter register, decrements at the SYSCLKOUT rate of the C28x.
When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed
in Table 4−1 are used to configure the timers. For more information, see the TMS320F28x System Control
and Interrupts Reference Guide (literature number SPRU078).
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Peripherals
Table 4−1. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
ADDRESS
SIZE (x16)
TIMER0TIM
0x00 0C00
1
CPU-Timer 0, Counter Register
TIMER0TIMH
0x00 0C01
1
CPU-Timer 0, Counter Register High
TIMER0PRD
0x00 0C02
1
CPU-Timer 0, Period Register
TIMER0PRDH
0x00 0C03
1
CPU-Timer 0, Period Register High
TIMER0TCR
0x00 0C04
1
CPU-Timer 0, Control Register
reserved
0x00 0C05
1
TIMER0TPR
0x00 0C06
1
CPU-Timer 0, Prescale Register
TIMER0TPRH
0x00 0C07
1
CPU-Timer 0, Prescale Register High
TIMER1TIM
0x00 0C08
1
CPU-Timer 1, Counter Register
TIMER1TIMH
0x00 0C09
1
CPU-Timer 1, Counter Register High
TIMER1PRD
0x00 0C0A
1
CPU-Timer 1, Period Register
TIMER1PRDH
0x00 0C0B
1
CPU-Timer 1, Period Register High
TIMER1TCR
0x00 0C0C
1
CPU-Timer 1, Control Register
reserved
0x00 0C0D
1
TIMER1TPR
0x00 0C0E
1
CPU-Timer 1, Prescale Register
TIMER1TPRH
0x00 0C0F
1
CPU-Timer 1, Prescale Register High
TIMER2TIM
0x00 0C10
1
CPU-Timer 2, Counter Register
TIMER2TIMH
0x00 0C11
1
CPU-Timer 2, Counter Register High
TIMER2PRD
0x00 0C12
1
CPU-Timer 2, Period Register
TIMER2PRDH
0x00 0C13
1
CPU-Timer 2, Period Register High
TIMER2TCR
0x00 0C14
1
CPU-Timer 2, Control Register
reserved
0x00 0C15
1
TIMER2TPR
0x00 0C16
1
CPU-Timer 2, Prescale Register
TIMER2TPRH
0x00 0C17
1
CPU-Timer 2, Prescale Register High
reserved
0x00 0C18
0x00 0C3F
40
4.2
DESCRIPTION
Event Manager Modules (EVA, EVB)
The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units,
and quadrature-encoder pulse (QEP) circuits. EVA and EVB timers, compare units, and capture units function
identically. However, timer/unit names differ for EVA and EVB. Table 4−2 shows the module and signal names
used. Table 4−2 shows the features and functionality available for the event-manager modules and highlights
EVA nomenclature.
Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting
at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and
QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function—however,
module/signal names would differ. Table 4−3 lists the EVA registers. For more information, see the
TMS320F28x DSP Event Manager (EV) Reference Guide (literature number SPRU065).
June 2004 − Revised June 2006
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55
Peripherals
Table 4−2. Module and Signal Names for EVA and EVB
EVA
EVENT MANAGER MODULES
EVB
MODULE
SIGNAL
MODULE
SIGNAL
GP Timers
GP Timer 1
GP Timer 2
T1PWM/T1CMP
T2PWM/T2CMP
GP Timer 3
GP Timer 4
T3PWM/T3CMP
T4PWM/T4CMP
Compare Units
Compare 1
Compare 2
Compare 3
PWM1/2
PWM3/4
PWM5/6
Compare 4
Compare 5
Compare 6
PWM7/8
PWM9/10
PWM11/12
Capture Units
Capture 1
Capture 2
Capture 3
CAP1
CAP2
CAP3
Capture 4
Capture 5
Capture 6
CAP4
CAP5
CAP6
QEP Channels
QEP1
QEP2
QEPI1
QEP1
QEP2
QEP3
QEP4
QEPI2
QEP3
QEP4
Direction
External Clock
TDIRA
TCLKINA
Direction
External Clock
TDIRB
TCLKINB
Compare
C1TRIP
C2TRIP
C3TRIP
Compare
C4TRIP
C5TRIP
C6TRIP
External Clock Inputs
External Trip Inputs
External Trip Inputs
T1CTRIP_PDPINTA†
T2CTRIP/EVASOC
T3CTRIP_PDPINTB†
T4CTRIP/EVBSOC
† In the 24x/240x-compatible mode, the T1CTRIP_PDPINTA pin functions as PDPINTA and the T3CTRIP_PDPINTB pin functions as PDPINTB.
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Peripherals
Table 4−3. EVA Registers†
NAME
ADDRESS
SIZE
(x16)
GPTCONA
0x00 7400
1
GP Timer Control Register A
DESCRIPTION
T1CNT
0x00 7401
1
GP Timer 1 Counter Register
T1CMPR
0x00 7402
1
GP Timer 1 Compare Register
T1PR
0x00 7403
1
GP Timer 1 Period Register
T1CON
0x00 7404
1
GP Timer 1 Control Register
T2CNT
0x00 7405
1
GP Timer 2 Counter Register
T2CMPR
0x00 7406
1
GP Timer 2 Compare Register
T2PR
0x00 7407
1
GP Timer 2 Period Register
T2CON
0x00 7408
1
GP Timer 2 Control Register
EXTCONA‡
0x00 7409
1
GP Extension Control Register A
COMCONA
0x00 7411
1
Compare Control Register A
ACTRA
0x00 7413
1
Compare Action Control Register A
DBTCONA
0x00 7415
1
Dead-Band Timer Control Register A
CMPR1
0x00 7417
1
Compare Register 1
CMPR2
0x00 7418
1
Compare Register 2
CMPR3
0x00 7419
1
Compare Register 3
CAPCONA
0x00 7420
1
Capture Control Register A
CAPFIFOA
0x00 7422
1
Capture FIFO Status Register A
CAP1FIFO
0x00 7423
1
Two-Level Deep Capture FIFO Stack 1
CAP2FIFO
0x00 7424
1
Two-Level Deep Capture FIFO Stack 2
CAP3FIFO
0x00 7425
1
Two-Level Deep Capture FIFO Stack 3
CAP1FBOT
0x00 7427
1
Bottom Register Of Capture FIFO Stack 1
CAP2FBOT
0x00 7428
1
Bottom Register Of Capture FIFO Stack 2
CAP3FBOT
0x00 7429
1
Bottom Register Of Capture FIFO Stack 3
EVAIMRA
0x00 742C
1
Interrupt Mask Register A
EVAIMRB
0x00 742D
1
Interrupt Mask Register B
EVAIMRC
0x00 742E
1
Interrupt Mask Register C
EVAIFRA
0x00 742F
1
Interrupt Flag Register A
EVAIFRB
0x00 7430
1
Interrupt Flag Register B
EVAIFRC
0x00 7431
1
Interrupt Flag Register C
† The EV-B register set is identical except the address range is from 0x00−7500 to 0x00−753F. The above registers are mapped to Zone 2. This
space allows only 16-bit accesses. 32-bit accesses produce undefined results.
‡ New register compared to 24x/240x
June 2004 − Revised June 2006
SPRS257C
57
Peripherals
Peripheral Write Bus
TX FIFO
Interrupt
MXINT
To CPU
TX FIFO _15
TX Interrupt Logic
McBSP Transmit
Interrupt Select Logic
TX FIFO _15
—
—
TX FIFO _1
TX FIFO _1
TX FIFO _0
TX FIFO _0
TX FIFO Registers
16
DXR2 Transmit Buffer
LSPCLK
McBSP Registers
and Control Logic
16
DXR1 Transmit Buffer
FSX
16
16
Compand Logic
CLKX
XSR2
XSR1
DX
RSR2
RSR1
DR
16
CLKR
16
Expand Logic
FSR
McBSP
RBR2 Register
RBR1 Register
16
16
DRR2 Receive Buffer
DRR1 Receive Buffer
16
McBSP Receive
Interrupt Select Logic
MRINT
RX Interrupt Logic
RX FIFO
Interrupt
To CPU
16
RX FIFO _15
RX FIFO _15
—
—
RX FIFO _1
RX FIFO _1
RX FIFO _0
RX FIFO _0
RX FIFO Registers
Peripheral Read Bus
Figure 4−3. Event Manager A Functional Block Diagram (See Note A)
4.2.1
General-Purpose (GP) Timers
There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:
58
•
A 16-bit timer, up-/down-counter, TxCNT, for reads or writes
•
A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes
•
A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes
•
A 16-bit timer-control register,TxCON, for reads or writes
•
Selectable internal or external input clocks
SPRS257C
June 2004 − Revised June 2006
Peripherals
•
A programmable prescaler for internal or external clock inputs
•
Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period
interrupts
•
A selectable direction input pin (TDIRx) (to count up or down when directional up- / down-count mode is
selected)
The GP timers can be operated independently or synchronized with each other. The compare register
associated with each GP timer can be used for compare function and PWM-waveform generation. There are
three continuous modes of operations for each GP timer in up- or up / down-counting operations. Internal or
external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the
time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP
timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering of the period
and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse
width as needed.
4.2.2
Full-Compare Units
There are three full-compare units on each event manager. These compare units use GP timer1 as the time
base and generate six outputs for compare and PWM-waveform generation using programmable deadband
circuit. The state of each of the six outputs is configured independently. The compare registers of the compare
units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.
4.2.3
Programmable Deadband Generator
Deadband generation can be enabled/disabled for each compare unit output individually. The
deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit
output signal. The output states of the deadband generator are configurable and changeable as needed by
way of the double-buffered ACTRx register.
4.2.4
PWM Waveform Generation
Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three
independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two
independent PWMs by the GP-timer compares.
4.2.5
Double Update PWM Mode
The R281x Event Manager supports “Double Update PWM Mode.” This mode refers to a PWM operation
mode in which the position of the leading edge and the position of the trailing edge of a PWM pulse are
independently modifiable in each PWM period. To support this mode, the compare register that determines
the position of the edges of a PWM pulse must allow (buffered) compare value update once at the beginning
of a PWM period and another time in the middle of a PWM period. The compare registers in R281x Event
Managers are all buffered and support three compare value reload/update (value in buffer becoming active)
modes. These modes have earlier been documented as compare value reload conditions. The reload
condition that supports double update PWM mode is reloaded on Underflow (beginning of PWM period) OR
Period (middle of PWM period). Double update PWM mode can be achieved by using this condition for
compare value reload.
4.2.6
PWM Characteristics
Characteristics of the PWMs are as follows:
•
16-bit registers
•
Wide range of programmable deadband for the PWM output pairs
•
Change of the PWM carrier frequency for PWM frequency wobbling as needed
June 2004 − Revised June 2006
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59
Peripherals
•
Change of the PWM pulse widths within and after each PWM period as needed
•
External-maskable power and drive-protection interrupts
•
Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space
vector PWM waveforms
•
Minimized CPU overhead using auto-reload of the compare and period registers
•
The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after
PDPINTx signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx
register.
•
4.2.7
−
PDPINTA pin status is reflected in bit 8 of COMCONA register.
−
PDPINTB pin status is reflected in bit 8 of COMCONB register.
EXTCON register bits provide options to individually trip control for each PWM pair of signals
Capture Unit
The capture unit provides a logging function for different events or transitions. The values of the selected GP
timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected
on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of
three capture circuits.
•
4.2.8
Capture units include the following features:
−
One 16-bit capture control register, CAPCONx (R/W)
−
One 16-bit capture FIFO status register, CAPFIFOx
−
Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base
−
Three 16-bit 2-level-deep FIFO stacks, one for each capture unit
−
Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit. [All
inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the input
must hold at its current level to meet the input qualification circuitry requirements. The input pins
CAP1/2 and CAP4/5 can also be used as QEP inputs to the QEP circuit.]
−
User-specified transition (rising edge, falling edge, or both edges) detection
−
Three maskable interrupt flags, one for each capture unit
−
The capture pins can also be used as general-purpose interrupt pins, if they are not used for the
capture function.
Quadrature-Encoder Pulse (QEP) Circuit
Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip
QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip.
Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented
by the rising and falling edges of the two input signals (four times the frequency of either input pulse).
With EXTCONA register bits, the EVA QEP circuit can use CAP3 as a capture index pin as well. Similarly, with
EXTCONB register bits, the EVB QEP circuit can use CAP6 as a capture index pin.
4.2.9
External ADC Start-of-Conversion
EVA/EVB start-of-conversion (SOC) can be sent to an external pin (EVASOC/EVBSOC) for external ADC
interface. EVASOC and EVBSOC are MUXed with T2CTRIP and T4CTRIP, respectively.
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Peripherals
4.3
Enhanced Analog-to-Digital Converter (ADC) Module
A simplified functional block diagram of the ADC module is shown in Figure 4−4. The ADC module consists
of a 12-bit ADC with a built-in sample-and-hold (S / H) circuit. Functions of the ADC module include:
•
12-bit ADC core with built-in S/H
•
Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)
•
Fast conversion rate: 80 ns at 25-MHz ADC clock, 12.5 MSPS
•
16-channel, MUXed inputs
•
Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can
be programmed to select any 1 of 16 input channels
•
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer
(i.e., two cascaded 8-state sequencers)
•
Sixteen result registers (individually addressable) to store conversion values
−
The digital value of the input analog voltage is derived by:
when input ≤ 0 V
Digital Value + 0,
Digital Value + 4096
4095
Input Analog Voltage * ADCLO,
3
Digital Value + 4095,
•
when 0 V < input < 3 V
when input ≥ 3 V
Multiple triggers as sources for the start-of-conversion (SOC) sequence
−
S/W − software immediate start
−
EVA − Event manager A (multiple event sources within EVA)
−
EVB − Event manager B (multiple event sources within EVB)
•
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
•
Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize
conversions
•
EVA and EVB triggers can operate independently in dual-sequencer mode
•
Sample-and-hold (S/H) acquisition time window has separate prescale control
The ADC module in R281x has been enhanced to provide flexible interface to event managers A and B. The
ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 80 ns at 25-MHz ADC
clock. The ADC module has 16 channels, configurable as two independent 8-channel modules to service
event managers A and B. The two independent 8-channel modules can be cascaded to form a 16-channel
module. Although there are multiple input channels and two sequencers, there is only one converter in the
ADC module. Figure 4−4 shows the block diagram of the R281x ADC module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module has
the choice of selecting any one of the respective eight channels available through an analog MUX. In the
cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once
the conversion is complete, the selected channel value is stored in its respective RESULT register.
Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform
oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.
June 2004 − Revised June 2006
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61
Peripherals
System
Control Block
SYSCLKOUT
High-Speed
Prescaler
ADCENCLK
C28x
HSPCLK
Analog
MUX
Result Registers
Result Reg 0
ADCINA0
70A8h
Result Reg 1
S/H
ADCINA7
12-Bit
ADC
Module
Result Reg 7
70AFh
Result Reg 8
70B0h
Result Reg 15
70B7h
ADCINB0
S/H
ADCINB7
ADC Control Registers
S/W
EVA
SOC
Sequencer 1
Sequencer 2
ADCSOC
SOC
S/W
EVB
Figure 4−4. Block Diagram of the R281x ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible,
traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize
switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation
techniques must be used to isolate the ADC module power pins (VDDA1/VDDA2 , AVDDREFBG ) from the digital
supply. Figure 4−5 shows the ADC pin connections for R281x devices.
Notes:
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is
controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:
ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the clock to the register will
still function. This is necessary to make sure all registers and modes go into their default reset state. The
analog module will however be in a low-power inactive state. As soon as reset goes high, then the clock to
the registers will be disabled. When the user sets the ADCENCLK signal high, then the clocks to the
registers will be enabled and the analog module will be enabled. There will be a certain time delay (ms
range) before the ADC is stable and can be used.
HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC module is
powered. If high, the ADC module goes into low-power mode. The HALT mode will stop the clock to the
CPU, which will stop the HSPCLK. Therefore the ADC register logic will be turned off indirectly.
Figure 4−5 shows the ADC pin-biasing for internal reference and Figure 4−6 shows the ADC pin-biasing for
external reference.
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Peripherals
ADCINA[7:0]
ADCINB[7:0]
ADCLO
Test Pin ADCBGREFIN†
ADC 16-Channel Analog Inputs
Analog input 0−3 V with respect to ADCLO
Connect to Analog Ground
24.9 kW§
ADC External Current Bias Resistor
ADCRESEXT
ADC Reference Positive Output
ADCREFP
ADC Reference Medium Output
ADCREFM
ADC Analog Power
VDDA1
VDDA2
VSSA1
VSSA2
Analog 3.3 V
Analog 3.3 V
ADC Reference Power
AVDDREFBG
AVSSREFBG
Analog 3.3 V
ADC Analog I/O Power
VDDAIO
VSSAIO
ADC Digital Power
VDD1
VSS1
10 mF‡
10 mF‡
ADCREFP and ADCREFM should not
be loaded by external circuitry
Analog 3.3 V
Analog Ground
1.8 V can use the same 1.8 V (or 1.9 V) supply as
Digital Ground
the digital core but separate the two with a
ferrite bead or a filter
† Provide access to this pin in PCB layouts. Intended for test purposes only.
‡ TAIYO YUDEN EMK325F106ZH, EMK325BJ106MD, or equivalent ceramic capacitor
§ 24.9-kΩ resistor is applicable for the full range of the ADC.
NOTES: A. External decoupling capacitors are recommended on all power pins.
B. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
Figure 4−5. ADC Pin Connections With Internal Reference (See Notes A and B)
NOTE:
The temperature rating of any recommended component must match the rating of the end
product.
June 2004 − Revised June 2006
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63
Peripherals
Test Pin
ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCBGREFIN
ADC External Current Bias Resistor
ADCRESEXT
ADC Reference Positive Input
ADCREFP
2V
ADC Reference Medium Input
ADCREFM
1V
ADC 16-Channel Analog Inputs
Analog Input 0−3 V With Respect to ADCLO
Connect to Analog Ground
24.9 kW
1 mF − 10 mF
ADC Analog Power
VDDA1
VDDA2
VSSA1
VSSA2
Analog 3.3 V
Analog 3.3 V
ADC Reference Power
AVDDREFBG
AVSSREFBG
Analog 3.3 V
ADC Analog I/O Power
VDDAIO
VSSAIO
ADC Digital Power
VDD1
VSS1
(See
Note C)
1 mF −10 mF
Analog 3.3 V
Analog Ground
1.8 V Can use the same 1.8-V (or 1.9-V)
Digital Ground
supply as the digital core but separate the
two with a ferrite bead or a filter
NOTES: A. External decoupling capacitors are recommended on all power pins.
B. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
C. It is recommended that buffered external references be provided with a voltage difference of (ADCREFP−ADCREFM)
= 1 V $ 0.1% or better.
External reference is enabled using bit 8 in the ADCTRL3 Register at ADC power up. In this mode, the accuracy of
external reference is critical for overall gain. The voltage ADCREFP−ADCREFM will determine the overall accuracy.
Do not enable internal references when external references are connected to ADCREFP and ADCREFM. See the
TMS320F28x DSP Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060) for more
information.
Figure 4−6. ADC Pin Connections With External Reference
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Peripherals
The ADC operation is configured, controlled, and monitored by the registers listed in Table 4−4.
Table 4−4. ADC Registers†
NAME
ADDRESS
SIZE
(x16)
ADCTRL1
0x00 7100
1
ADC Control Register 1
ADCTRL2
0x00 7101
1
ADC Control Register 2
ADCMAXCONV
0x00 7102
1
ADC Maximum Conversion Channels Register
ADCCHSELSEQ1
0x00 7103
1
ADC Channel Select Sequencing Control Register 1
ADCCHSELSEQ2
0x00 7104
1
ADC Channel Select Sequencing Control Register 2
ADCCHSELSEQ3
0x00 7105
1
ADC Channel Select Sequencing Control Register 3
ADCCHSELSEQ4
0x00 7106
1
ADC Channel Select Sequencing Control Register 4
ADCASEQSR
0x00 7107
1
ADC Auto-Sequence Status Register
ADCRESULT0
0x00 7108
1
ADC Conversion Result Buffer Register 0
ADCRESULT1
0x00 7109
1
ADC Conversion Result Buffer Register 1
ADCRESULT2
0x00 710A
1
ADC Conversion Result Buffer Register 2
ADCRESULT3
0x00 710B
1
ADC Conversion Result Buffer Register 3
ADCRESULT4
0x00 710C
1
ADC Conversion Result Buffer Register 4
ADCRESULT5
0x00 710D
1
ADC Conversion Result Buffer Register 5
ADCRESULT6
0x00 710E
1
ADC Conversion Result Buffer Register 6
ADCRESULT7
0x00 710F
1
ADC Conversion Result Buffer Register 7
ADCRESULT8
0x00 7110
1
ADC Conversion Result Buffer Register 8
ADCRESULT9
0x00 7111
1
ADC Conversion Result Buffer Register 9
ADCRESULT10
0x00 7112
1
ADC Conversion Result Buffer Register 10
ADCRESULT11
0x00 7113
1
ADC Conversion Result Buffer Register 11
ADCRESULT12
0x00 7114
1
ADC Conversion Result Buffer Register 12
ADCRESULT13
0x00 7115
1
ADC Conversion Result Buffer Register 13
ADCRESULT14
0x00 7116
1
ADC Conversion Result Buffer Register 14
ADCRESULT15
0x00 7117
1
ADC Conversion Result Buffer Register 15
ADCTRL3
0x00 7118
1
ADC Control Register 3
ADCST
0x00 7119
1
ADC Status Register
reserved
0x00 711C
0x00 711F
4
DESCRIPTION
† The above registers are Peripheral Frame 2 Registers.
June 2004 − Revised June 2006
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65
Peripherals
4.4
Enhanced Controller Area Network (eCAN) Module
The CAN module has the following features:
•
Fully compliant with CAN protocol, version 2.0B
•
Supports data rates up to 1 Mbps
•
Thirty-two mailboxes, each with the following properties:
−
Configurable as receive or transmit
−
Configurable with standard or extended identifier
−
Has a programmable receive mask
−
Supports data and remote frame
−
Composed of 0 to 8 bytes of data
−
Uses a 32-bit time stamp on receive and transmit message
−
Protects against reception of new message
−
Holds the dynamically programmable priority of transmit message
−
Employs a programmable interrupt scheme with two interrupt levels
−
Employs a programmable alarm on transmission or reception time-out
•
Low-power mode
•
Programmable wake-up on bus activity
•
Automatic reply to a remote request message
•
Automatic retransmission of a frame in case of loss of arbitration or error
•
32-bit local network time counter synchronized by a specific message (communication in conjunction with
mailbox 16)
•
Self-test mode
−
Operates in a loopback mode receiving its own message. A “dummy” acknowledge is provided,
thereby eliminating the need for another node to provide the acknowledge bit.
NOTE: For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 23.4 kbps.
The 28x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for further details.
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Peripherals
eCAN0INT
Controls Address
eCAN1INT
Data
32
Enhanced CAN Controller
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
32-Message Mailbox
of 4 × 32-Bit Words
32
CPU Interface,
Receive Control Unit,
Timer Management Unit
32
eCAN Memory
(512 Bytes)
Registers and Message
Objects Control
32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 4−7. eCAN Block Diagram and Interface Circuit
Table 4−5. 3.3-V eCAN Transceivers for the R281x DSPs
PART NUMBER
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
VREF
OTHER
TA
SN65HVD230
3.3 V
Standby
Adjustable
Yes
−−
−40°C to 85°C
SN65HVD230Q
3.3 V
Standby
Adjustable
Yes
−−
−40°C to 125°C
SN65HVD231
3.3 V
Sleep
Adjustable
Yes
−−
−40°C to 85°C
SN65HVD231Q
3.3 V
Sleep
Adjustable
Yes
−−
−40°C to 125°C
SN65HVD232
3.3 V
None
None
None
−−
−40°C to 85°C
SN65HVD232Q
3.3 V
None
None
None
−−
−40°C to 125°C
SN65HVD233
3.3 V
Standby
Adjustable
None
Diagnostic
Loopback
−40°C to 125°C
June 2004 − Revised June 2006
SPRS257C
67
Peripherals
Table 4−5. 3.3-V eCAN Transceivers for the TMS320R281x DSPs (Continued)
PART NUMBER
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
VREF
OTHER
TA
SN65HVD234
3.3 V
Standby & Sleep
Adjustable
None
−−
−40°C to 125°C
SN65HVD235
3.3 V
Standby
Adjustable
None
Autobaud
Loopback
−40°C to 125°C
eCAN Control and Status Registers
Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
eCAN Memory (512 Bytes)
6000h
Abort Acknowledge − CANAA
Received Message Pending − CANRMP
Control and Status Registers
Received Message Lost − CANRML
603Fh
6040h
607Fh
6080h
60BFh
60C0h
60FFh
Remote Frame Pending − CANRFP
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
Global Acceptance Mask − CANGAM
Message Object Time Stamps (MOTS)
(32 × 32-Bit RAM)
Bit-Timing Configuration − CANBTC
Master Control − CANMC
Error and Status − CANES
Message Object Time-Out (MOTO)
(32 × 32-Bit RAM)
Transmit Error Counter − CANTEC
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Global Interrupt Flag 1 − CANGIF1
eCAN Memory RAM (512 Bytes)
6100h−6107h
Mailbox 0
6108h−610Fh
Mailbox 1
6110h−6117h
Mailbox 2
6118h−611Fh
Mailbox 3
6120h−6127h
Mailbox 4
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Time-Out Control − CANTOC
Time-Out Status − CANTOS
61E0h−61E7h
Mailbox 28
61E8h−61EFh
Mailbox 29
61F0h−61F7h
Mailbox 30
61F8h−61FFh
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
61E8h−61E9h
Message Identifier − MSGID
61EAh−61EBh
Message Control − MSGCTRL
61ECh−61EDh
Message Data Low − MDL
61EEh−61EFh
Message Data High − MDH
Figure 4−8. eCAN Memory Map
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Peripherals
The CAN registers listed in Table 4−6 are used by the CPU to configure and control the CAN controller and
the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be
accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 4−6. CAN Registers Map†
REGISTER NAME
ADDRESS
SIZE
(x32)
CANME
0x00 6000
1
Mailbox enable
DESCRIPTION
CANMD
0x00 6002
1
Mailbox direction
CANTRS
0x00 6004
1
Transmit request set
CANTRR
0x00 6006
1
Transmit request reset
CANTA
0x00 6008
1
Transmission acknowledge
CANAA
0x00 600A
1
Abort acknowledge
CANRMP
0x00 600C
1
Receive message pending
CANRML
0x00 600E
1
Receive message lost
CANRFP
0x00 6010
1
Remote frame pending
CANGAM
0x00 6012
1
Global acceptance mask
CANMC
0x00 6014
1
Master control
CANBTC
0x00 6016
1
Bit-timing configuration
CANES
0x00 6018
1
Error and status
CANTEC
0x00 601A
1
Transmit error counter
CANREC
0x00 601C
1
Receive error counter
CANGIF0
0x00 601E
1
Global interrupt flag 0
CANGIM
0x00 6020
1
Global interrupt mask
CANGIF1
0x00 6022
1
Global interrupt flag 1
CANMIM
0x00 6024
1
Mailbox interrupt mask
CANMIL
0x00 6026
1
Mailbox interrupt level
CANOPC
0x00 6028
1
Overwrite protection control
CANTIOC
0x00 602A
1
TX I/O control
CANRIOC
0x00 602C
1
RX I/O control
CANTSC
0x00 602E
1
Time stamp counter (Reserved in SCC mode)
CANTOC
0x00 6030
1
Time-out control (Reserved in SCC mode)
CANTOS
0x00 6032
1
Time-out status (Reserved in SCC mode)
† These registers are mapped to Peripheral Frame 1.
June 2004 − Revised June 2006
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69
Peripherals
4.5
Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
•
Compatible to McBSP in TMS320C54x /TMS320C55x DSP devices, except the DMA features
•
Full-duplex communication
•
Double-buffered data registers which allow a continuous data stream
•
Independent framing and clocking for receive and transmit
•
External shift clock generation or an internal programmable frequency shift clock
•
A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits
•
8-bit data transfers with LSB or MSB first
•
Programmable polarity for both frame synchronization and data clocks
•
HIghly programmable internal clock and frame generation
•
Support A-bis mode
•
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
•
Works with SPI-compatible devices
•
Two 16 x 16-level FIFO for Transmit channel
•
Two 16 x 16-level FIFO for Receive channel
The following application interfaces can be supported on the McBSP:
•
T1/E1 framers
•
MVIP switching-compatible and ST-BUS-compliant devices including:
•
−
MVIP framers
−
H.100 framers
−
SCSA framers
−
IOM-2 compliant devices
−
AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
−
IIS-compliant devices
McBSP clock rate = CLKG =
CLKSRG
, where CLKSRG source could be LSPCLK, CLKX, or CLKR.
(1 ) CLKGDIV)
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such
that the peripheral speed is less than the I/O buffer speed limit—20-MHz maximum.
Figure 4−9 shows the block diagram of the McBSP module with FIFO, interfaced to the R281x version of
Peripheral Frame 2.
TMS320C54x and TMS320C55x are trademarks of Texas Instruments.
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Peripherals
Peripheral Write Bus
TX FIFO
Interrupt
MXINT
To CPU
TX Interrupt Logic
McBSP Transmit
Interrupt Select Logic
TX FIFO _15
TX FIFO _15
—
—
TX FIFO _1
TX FIFO _1
TX FIFO _0
TX FIFO _0
TX FIFO Registers
16
DXR2 Transmit Buffer
LSPCLK
McBSP Registers
and Control Logic
16
DXR1 Transmit Buffer
16
16
FSX
Compand Logic
CLKX
XSR2
XSR1
DX
RSR2
RSR1
DR
16
CLKR
16
Expand Logic
FSR
McBSP
RBR2 Register
RBR1 Register
16
16
DRR2 Receive Buffer
DRR1 Receive Buffer
16
McBSP Receive
Interrupt Select Logic
MRINT
RX Interrupt Logic
To CPU
RX FIFO
Interrupt
16
RX FIFO _15
RX FIFO _15
—
—
RX FIFO _1
RX FIFO _1
RX FIFO _0
RX FIFO _0
RX FIFO Registers
Peripheral Read Bus
Figure 4−9. McBSP Module With FIFO
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71
Peripherals
Table 4−7 provides a summary of the McBSP registers.
Table 4−7. McBSP Register Summary
NAME
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
DESCRIPTION
DATA REGISTERS, RECEIVE, TRANSMIT†
−
−
−
0x0000
McBSP Receive Buffer Register
−
−
−
0x0000
McBSP Receive Shift Register
−
−
−
0x0000
McBSP Transmit Shift Register
DRR2
00
R
0x0000
McBSP Data Receive Register 2
− Read First if the word size is greater than 16 bits,
else ignore DRR2
DRR1
01
R
0x0000
McBSP Data Receive Register 1
− Read Second if the word size is greater than 16 bits,
else read DRR1 only
DXR2
02
W
0x0000
McBSP Data Transmit Register 2
− Write First if the word size is greater than 16 bits,
else ignore DXR2
DXR1
03
W
0x0000
McBSP Data Transmit Register 1
− Write Second if the word size is greater than 16 bits,
else write to DXR1 only
McBSP CONTROL REGISTERS
SPCR2
04
R/W
0x0000
McBSP Serial Port Control Register 2
SPCR1
05
R/W
0x0000
McBSP Serial Port Control Register 1
RCR2
06
R/W
0x0000
McBSP Receive Control Register 2
RCR1
07
R/W
0x0000
McBSP Receive Control Register 1
XCR2
08
R/W
0x0000
McBSP Transmit Control Register 2
XCR1
09
R/W
0x0000
McBSP Transmit Control Register 1
SRGR2
0A
R/W
0x0000
McBSP Sample Rate Generator Register 2
SRGR1
0B
R/W
0x0000
McBSP Sample Rate Generator Register 1
MULTICHANNEL CONTROL REGISTERS
MCR2
0C
R/W
0x0000
McBSP Multichannel Register 2
MCR1
0D
R/W
0x0000
McBSP Multichannel Register 1
RCERA
0E
R/W
0x0000
McBSP Receive Channel Enable Register Partition A
RCERB
0F
R/W
0x0000
McBSP Receive Channel Enable Register Partition B
XCERA
10
R/W
0x0000
McBSP Transmit Channel Enable Register Partition A
XCERB
11
R/W
0x0000
McBSP Transmit Channel Enable Register Partition B
PCR
12
R/W
0x0000
McBSP Pin Control Register
RCERC
13
R/W
0x0000
McBSP Receive Channel Enable Register Partition C
RCERD
14
R/W
0x0000
McBSP Receive Channel Enable Register Partition D
XCERC
15
R/W
0x0000
McBSP Transmit Channel Enable Register Partition C
XCERD
16
R/W
0x0000
McBSP Transmit Channel Enable Register Partition D
† DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
‡ FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
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Peripherals
Table 4−7. McBSP Register Summary (Continued)
ADDRESS
0x00 78xxh
NAME
TYPE
(R/W)
RESET VALUE
(HEX)
DESCRIPTION
MULTICHANNEL CONTROL REGISTERS (CONTINUED)
RCERE
17
R/W
0x0000
McBSP Receive Channel Enable Register Partition E
RCERF
18
R/W
0x0000
McBSP Receive Channel Enable Register Partition F
XCERE
19
R/W
0x0000
McBSP Transmit Channel Enable Register Partition E
XCERF
1A
R/W
0x0000
McBSP Transmit Channel Enable Register Partition F
RCERG
1B
R/W
0x0000
McBSP Receive Channel Enable Register Partition G
RCERH
1C
R/W
0x0000
McBSP Receive Channel Enable Register Partition H
XCERG
1D
R/W
0x0000
McBSP Transmit Channel Enable Register Partition G
XCERH
1E
R/W
0x0000
McBSP Transmit Channel Enable Register Partition H
FIFO MODE REGISTERS (applicable only in FIFO mode)
FIFO Data Registers‡
DRR2
00
R
0x0000
McBSP Data Receive Register 2 − Top of receive FIFO
− Read First FIFO pointers will not advance
DRR1
01
R
0x0000
McBSP Data Receive Register 1 − Top of receive FIFO
− Read Second for FIFO pointers to advance
DXR2
02
W
0x0000
McBSP Data Transmit Register 2 − Top of transmit FIFO
− Write First FIFO pointers will not advance
DXR1
03
W
0x0000
McBSP Data Transmit Register 1 − Top of transmit FIFO
− Write Second for FIFO pointers to advance
MFFTX
20
R/W
0xA000
McBSP Transmit FIFO Register
MFFRX
21
R/W
0x201F
McBSP Receive FIFO Register
MFFCT
22
R/W
0x0000
McBSP FIFO Control Register
MFFINT
23
R/W
0x0000
McBSP FIFO Interrupt Register
FIFO Control Registers
MFFST
24
R/W
0x0000
McBSP FIFO Status Register
† DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
‡ FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
4.6
Serial Communications Interface (SCI) Module
R281x devices include two serial communications interface (SCI) modules. The SCI modules support digital
communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex
mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing
errors. The bit rate is programmable to over 65 000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
•
Two external pins:
−
SCITXD: SCI transmit-output pin
−
SCIRXD: SCI receive-input pin
NOTE:
Both pins can be used as GPIO if not used for SCI.
June 2004 − Revised June 2006
SPRS257C
73
Peripherals
•
Baud rate programmable to 64K different rates
−
Baud rate =
=
LSPCLK , when BRR ≠ 0
(BRR ) 1) * 8
LSPCLK ,
when BRR = 0
16
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such
that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum.
•
Data-word format
−
One start bit
−
Data-word length programmable from one to eight bits
−
Optional even/odd/no parity bit
−
One or two stop bits
•
Four error-detection flags: parity, overrun, framing, and break detection
•
Two wake-up multiprocessor modes: idle-line and address bit
•
Half- or full-duplex operation
•
Double-buffered receive and transmit functions
•
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
−
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and
TX EMPTY flag (transmitter-shift register is empty)
−
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
•
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
•
Max bit rate + 150 MHz + 9.375
2 8
•
NRZ (non-return-to-zero) format
•
Ten SCI module control registers located in the control register frame beginning at address 7050h
10 6 bńs
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is
accessed, the register data is in the lower byte (7−0), and the upper byte (15−8) is read as zeros. Writing
to the upper byte has no effect.
Enhanced features:
74
•
Auto baud-detect hardware logic
•
16-level transmit/receive FIFO
SPRS257C
June 2004 − Revised June 2006
Peripherals
Figure 4−10 shows the SCI module block diagram.
SCICTL1.1
SCITXD
Frame Format and Mode
Parity
Even/Odd Enable
TXSHF
Register
TXENA
8
SCICCR.6 SCICCR.5
TXRDY
TXWAKE
SCICTL1.3
1
Transmitter−Data
Buffer Register
8
TX INT ENA
SCICTL2.7
SCICTL2.0
TX FIFO
Interrupts
TX FIFO _0
SCITXD
TX EMPTY
SCICTL2.6
TXINT
TX Interrupt
Logic
TX FIFO _1
−−−−−
To CPU
TX FIFO _15
WUT
SCI TX Interrupt select logic
SCITXBUF.7−0
TX FIFO registers
SCIFFENA
AutoBaud Detect logic
SCIFFTX.14
SCIHBAUD. 15 − 8
Baud Rate
MSbyte
Register
SCIRXD
RXSHF
Register
SCIRXD
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 − 0
Baud Rate
LSbyte
Register
RXENA
8
SCICTL1.0
SCICTL2.1
Receive Data
Buffer register
SCIRXBUF.7−0
RXRDY
SCIRXST.6
8
RX FIFO _15
BRKDT
−−−−−
SCIRXST.5
RX FIFO_1
RX FIFO _0
SCIRXBUF.7−0
RX/BK INT ENA
RX FIFO
Interrupts
RX Interrupt
Logic
To CPU
RX FIFO registers
SCIRXST.7
SCIRXST.4 − 2
RX Error
FE OE PE
RXINT
RXFFOVF
SCIFFRX.15
RX Error
RX ERR INT ENA
SCICTL1.6
SCI RX Interrupt select logic
Figure 4−10. Serial Communications Interface (SCI) Module Block Diagram
June 2004 − Revised June 2006
SPRS257C
75
Peripherals
The SCI port operation is configured and controlled by the registers listed in Table 4−8 and Table 4−9.
Table 4−8. SCI-A Registers†
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
SCICCRA
0x00 7050
1
SCI-A Communications Control Register
SCICTL1A
0x00 7051
1
SCI-A Control Register 1
SCIHBAUDA
0x00 7052
1
SCI-A Baud Register, High Bits
SCILBAUDA
0x00 7053
1
SCI-A Baud Register, Low Bits
SCICTL2A
0x00 7054
1
SCI-A Control Register 2
SCIRXSTA
0x00 7055
1
SCI-A Receive Status Register
SCIRXEMUA
0x00 7056
1
SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA
0x00 7057
1
SCI-A Receive Data Buffer Register
SCITXBUFA
0x00 7059
1
SCI-A Transmit Data Buffer Register
SCIFFTXA
0x00 705A
1
SCI-A FIFO Transmit Register
SCIFFRXA
0x00 705B
1
SCI-A FIFO Receive Register
SCIFFCTA
0x00 705C
1
SCI-A FIFO Control Register
SCIPRIA
0x00 705F
1
SCI-A Priority Control Register
† Shaded registers are new registers for the FIFO mode.
Table 4−9. SCI-B Registers†‡
NAME
ADDRESS
SIZE (x16)
SCICCRB
0x00 7750
1
SCI-B Communications Control Register
DESCRIPTION
SCICTL1B
0x00 7751
1
SCI-B Control Register 1
SCIHBAUDB
0x00 7752
1
SCI-B Baud Register, High Bits
SCILBAUDB
0x00 7753
1
SCI-B Baud Register, Low Bits
SCICTL2B
0x00 7754
1
SCI-B Control Register 2
SCIRXSTB
0x00 7755
1
SCI-B Receive Status Register
SCIRXEMUB
0x00 7756
1
SCI-B Receive Emulation Data Buffer Register
SCIRXBUFB
0x00 7757
1
SCI-B Receive Data Buffer Register
SCITXBUFB
0x00 7759
1
SCI-B Transmit Data Buffer Register
SCIFFTXB
0x00 775A
1
SCI-B FIFO Transmit Register
SCIFFRXB
0x00 775B
1
SCI-B FIFO Receive Register
SCIFFCTB
0x00 775C
1
SCI-B FIFO Control Register
SCIPRIB
0x00 775F
1
SCI-B Priority Control Register
† Shaded registers are new registers for the FIFO mode.
‡ Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.
4.7
Serial Peripheral Interface (SPI) Module
R281x devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed,
synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be
shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the DSP controller and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.
76
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June 2004 − Revised June 2006
Peripherals
The SPI module features include:
•
Four external pins:
−
SPISOMI: SPI slave-output/master-input pin
−
SPISIMO: SPI slave-input/master-output pin
−
SPISTE: SPI slave transmit-enable pin
−
SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
•
Two operational modes: master and slave
•
Baud rate: 125 different programmable rates
−
LSPCLK
, when BRR ≠ 0
(SPIBRR ) 1)
when BRR = 0, 1, 2, 3
= LSPCLK ,
4
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted
such that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum.
Baud rate =
•
Data word length: one to sixteen data bits
•
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
−
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
−
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
−
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
−
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
•
Simultaneous receive and transmit operation (transmit function can be disabled in software)
•
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
•
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register
is accessed, the register data is in the lower byte (7−0), and the upper byte (15−8) is read as zeros. Writing
to the upper byte has no effect.
Enhanced feature:
•
16-level transmit/receive FIFO
•
Delayed transmit control
June 2004 − Revised June 2006
SPRS257C
77
Peripherals
The SPI port operation is configured and controlled by the registers listed in Table 4−10.
Table 4−10. SPI Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
SPICCR
0x00 7040
1
SPI Configuration Control Register
SPICTL
0x00 7041
1
SPI Operation Control Register
SPISTS
0x00 7042
1
SPI Status Register
SPIBRR
0x00 7044
1
SPI Baud Rate Register
SPIRXEMU
0x00 7046
1
SPI Receive Emulation Buffer Register
SPIRXBUF
0x00 7047
1
SPI Serial Input Buffer Register
SPITXBUF
0x00 7048
1
SPI Serial Output Buffer Register
SPIDAT
0x00 7049
1
SPI Serial Data Register
SPIFFTX
0x00 704A
1
SPI FIFO Transmit Register
SPIFFRX
0x00 704B
1
SPI FIFO Receive Register
SPIFFCT
0x00 704C
1
SPI FIFO Control Register
SPIPRI
0x00 704F
1
SPI Priority Control Register
NOTE: The registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
78
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June 2004 − Revised June 2006
Peripherals
Figure 4−11 is a block diagram of the SPI in slave mode.
SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO registers
SPISTS.7
SPICTL.4
SPIRXBUF
RX FIFO _0
RX FIFO _1
−−−−−
SPIINT/SPIRXINT
RX FIFO Interrupt
RX Interrupt
Logic
RX FIFO _15
16
SPIRXBUF
Buffer Register
SPIFFOVF FLAG
SPIFFRX.15
To CPU
TX FIFO registers
SPITXBUF
TX FIFO _15
−−−−−
TX Interrupt
Logic
TX FIFO Interrupt
TX FIFO _1
TX FIFO _0
SPITXINT
16
SPI INT FLAG
SPITXBUF
Buffer Register
16
SPI INT
ENA
SPISTS.6
SPICTL.0
16
M
M
SPIDAT
Data Register
S
S
SW1
SPISIMO
M
M
SPIDAT.15 − 0
S
S
SW2
SPISOMI
Talk
SPICTL.1
SPISTE†
State Control
Master/Slave
SPI Char
SPICCR.3 − 0
3
2
1
0
SW3
M
SPI Bit Rate
LSPCLK
SPICTL.2
S
S
SPIBRR.6 − 0
6
5
4
3
2
1
0
Clock
Polarity
Clock
Phase
SPICCR.6
SPICTL.3
SPICLK
M
† SPISTE is driven low by the master for a slave device.
Figure 4−11. Serial Peripheral Interface Module Block Diagram (Slave Mode)
June 2004 − Revised June 2006
SPRS257C
79
Peripherals
4.8
GPIO MUX
The GPIO MUX registers, are used to select the operation of shared pins on R281x devices. The pins can be
individually selected to operate as “Digital I/O” or connected to “Peripheral I/O” signals (via the GPxMUX
registers). If selected for “Digital I/O” mode, registers are provided to configure the pin direction (via the
GPxDIR registers) and to qualify the input signal to remove unwanted noise (via the GPxQUAL) registers).
Table 4−11 lists the GPIO MUX Registers.
Table 4−11. GPIO MUX Registers†‡§
NAME
ADDRESS
SIZE (x16)
GPAMUX
0x00 70C0
1
GPIO A MUX Control Register
REGISTER DESCRIPTION
GPADIR
0x00 70C1
1
GPIO A Direction Control Register
GPAQUAL
0x00 70C2
1
GPIO A Input Qualification Control Register
reserved
0x00 70C3
1
GPBMUX
0x00 70C4
1
GPIO B MUX Control Register
GPBDIR
0x00 70C5
1
GPIO B Direction Control Register
GPBQUAL
0x00 70C6
1
GPIO B Input Qualification Control Register
reserved
0x00 70C7
1
reserved
0x00 70C8
1
reserved
0x00 70C9
1
reserved
0x00 70CA
1
reserved
0x00 70CB
1
GPDMUX
0x00 70CC
1
GPIO D MUX Control Register
GPDDIR
0x00 70CD
1
GPIO D Direction Control Register
GPDQUAL
0x00 70CE
1
GPIO D Input Qualification Control Register
reserved
0x00 70CF
1
GPEMUX
0x00 70D0
1
GPIO E MUX Control Register
GPEDIR
0x00 70D1
1
GPIO E Direction Control Register
GPEQUAL
0x00 70D2
1
GPIO E Input Qualification Control Register
reserved
0x00 70D3
1
GPFMUX
0x00 70D4
1
GPIO F MUX Control Register
GPFDIR
0x00 70D5
1
GPIO F Direction Control Register
reserved
0x00 70D6
1
reserved
0x00 70D7
1
GPGMUX
0x00 70D8
1
GPIO G MUX Control Register
GPGDIR
0x00 70D9
1
GPIO G Direction Control Register
reserved
0x00 70DA
1
reserved
0x00 70DB
1
reserved
0x00 70DC
0x00 70DF
4
† Reserved locations will return undefined values and writes will be ignored.
‡ Not all inputs will support input signal qualification.
§ These registers are EALLOW protected. This prevents spurious writes from overwriting the contents and corrupting the system.
80
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June 2004 − Revised June 2006
Peripherals
If configured for digital I/O mode, additional registers are provided for setting individual I/O signals (via the
GPxSET registers), for clearing individual I/O signals (via the GPxCLEAR registers), for toggling individual I/O
signals (via the GPxTOGGLE registers), or for reading/writing to the individual I/O signals (via the GPxDAT
registers). Table 4−12 lists the GPIO Data Registers. For more information, see the TMS320F28x System
Control and Interrupts Reference Guide (literature number SPRU078).
Table 4−12. GPIO Data Registers†‡
NAME
ADDRESS
SIZE (x16)
REGISTER DESCRIPTION
GPADAT
0x00 70E0
1
GPIO A Data Register
GPASET
0x00 70E1
1
GPIO A Set Register
GPACLEAR
0x00 70E2
1
GPIO A Clear Register
GPATOGGLE
0x00 70E3
1
GPIO A Toggle Register
GPBDAT
0x00 70E4
1
GPIO B Data Register
GPBSET
0x00 70E5
1
GPIO B Set Register
GPBCLEAR
0x00 70E6
1
GPIO B Clear Register
GPBTOGGLE
0x00 70E7
1
GPIO B Toggle Register
reserved
0x00 70E8
1
reserved
0x00 70E9
1
reserved
0x00 70EA
1
reserved
0x00 70EB
1
GPDDAT
0x00 70EC
1
GPIO D Data Register
GPDSET
0x00 70ED
1
GPIO D Set Register
GPDCLEAR
0x00 70EE
1
GPIO D Clear Register
GPDTOGGLE
0x00 70EF
1
GPIO D Toggle Register
GPEDAT
0x00 70F0
1
GPIO E Data Register
GPESET
0x00 70F1
1
GPIO E Set Register
GPECLEAR
0x00 70F2
1
GPIO E Clear Register
GPETOGGLE
0x00 70F3
1
GPIO E Toggle Register
GPFDAT
0x00 70F4
1
GPIO F Data Register
GPFSET
0x00 70F5
1
GPIO F Set Register
GPFCLEAR
0x00 70F6
1
GPIO F Clear Register
GPFTOGGLE
0x00 70F7
1
GPIO F Toggle Register
GPGDAT
0x00 70F8
1
GPIO G Data Register
GPGSET
0x00 70F9
1
GPIO G Set Register
GPGCLEAR
0x00 70FA
1
GPIO G Clear Register
GPGTOGGLE
0x00 70FB
1
GPIO G Toggle Register
reserved
0x00 70FC
0x00 70FF
4
† Reserved locations will return undefined values and writes will be ignored.
‡ These registers are NOT EALLOW protected. The above registers will typically be accessed regularly by the user.
June 2004 − Revised June 2006
SPRS257C
81
Peripherals
Figure 4−12 shows how the various register bits select the various modes of operation for GPIO function.
GPxDAT/SET/CLEAR/TOGGLE
Register Bit(s)
GPxQUAL
Register
Digital I/O
GPxMUX
Register Bit
0
Peripheral I/O
HighImpedance
Control
GPxDIR
Register Bit
0
1
MUX
1
MUX
SYSCLKOUT
Input Qualification
High-Impedance
Enable (1)
XRS
Internal (Pullup or Pulldown)
PIN
NOTES: A. In the GPIO mode, when the GPIO pin is configured for output operation, reading the GPxDAT data register only gives the value
written, not the value at the pin. In the peripheral mode, the state of the pin can be read through the GPxDAT register, provided the
corresponding direction bit is zero (input mode).
B. Some selected input signals are qualified by the SYSCLKOUT. The GPxQUAL register specifies the qualification sampling period.
The sampling window is 6 samples wide and the output is only changed when all samples are the same (all 0’s or all 1’s). This feature
removes unwanted spikes from the input signal.
Figure 4−12. GPIO/Peripheral Pin MUXing
NOTE:
The input function of the GPIO pin and the input path to the peripheral are always enabled.
It is the output function of the GPIO pin that is multiplexed with the output path of the primary
(peripheral) function. Since the output buffer of a pin connects back to the input buffer, any
GPIO signal present at the pin will be propagated to the peripheral module as well. Therefore,
when a pin is configured for GPIO operation, the corresponding peripheral functionality (and
interrupt-generating capability) must be disabled. Otherwise, interrupts may be inadvertently
triggered. This is especially critical when the PDPINTA and PDPINTB pins are used as GPIO
pins, since a value of zero for GPDDAT.0 or GPDDAT.5 (PDPINTx) will put PWM pins in a
high-impedance state. The CxTRIP and TxCTRIP pins will also put the corresponding PWM
pins in high impedance, if they are driven low (as GPIO pins) and bit EXTCONx.0 = 1.
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June 2004 − Revised June 2006
Development Support
5
Development Support
Texas Instruments (TI) offers an extensive line of development tools for the C28x generation of DSPs,
including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of R281x-based applications:
Software Development Tools
•
Code Composer Studio Integrated Development Environment (IDE)
−
C/C++ Compiler
−
Code generation tools
−
Assembler/Linker
−
Cycle Accurate Simulator
•
Application algorithms
•
Sample applications code
Hardware Development Tools
5.1
•
R2812 eZdsp
•
JTAG-based emulators − SPI515, XDS510PP, XDS510PP Plus, XDS510 USB
•
Universal 5-V dc power supply
•
Documentation and cables
Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
[TMS320] DSP devices and support tools. Each [TMS320] DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS (e.g., TMS320R2812GHH). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary
stages of product development from engineering prototypes (TMX/ TMDX) through fully qualified production
devices/tools (TMS / TMDS).
TMX
Experimental device that is not necessarily representative of the final device’s electrical specifications
TMP
Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development−support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.“
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
TMS320 is a trademark of Texas Instruments.
June 2004 − Revised June 2006
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Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package
type (for example, PBK) and temperature range (for example, A). Figure 5−1 provides a legend for reading
the complete device name for any TMS320x28x family member.
TMS 320
R
2812
PBK
A
PREFIX
TMX = experimental device
TMP = prototype device
TMS = qualified device
DEVICE FAMILY
320 = TMS320 DSP Family
TECHNOLOGY
F = Flash EEPROM (1.8-V/1.9-V Core/3.3-V I/O)
C = ROM (1.8-V/1.9-V Core/3.3-V I/O)
R = RAM only (1.8-V/1.9-V Core/3.3-V I/O)
TEMPERATURE RANGE
A
= −40°C to 85°C
S
= −40°C to 125°C
Q = −40°C to 125°C − Q100
fault grading
PACKAGE TYPE†‡
GHH = 179-ball MicroStar BGA
ZHH = 179-ball MicroStar BGA (lead-free)
PGF = 176-pin LQFP
PBK = 128-pin LQFP
DEVICE
2811
2812
† BGA = Ball Grid Array
LQFP = Low-Profile Quad Flatpack
‡ LQFP package not yet available lead (Pb)-free. For estimated conversion dates, go to www.ti.com/leadfree
Figure 5−1. TMS320x28x Device Nomenclature
5.2
Documentation Support
Extensive documentation supports all of the TMS320 DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data sheets
and data manuals, with design specifications; and hardware and software applications. Useful reference
documentation includes:
TMS320C28x DSP CPU and Instruction Set Reference Guide (literature number SPRU430) describes the
central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital
signal processors (DSPs). It also describes emulation features available on these DSPs.
TMS320x281x Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060)
describes the ADC module. The module is a 12-bit pipelined ADC. The analog circuits of this converter,
referred to as the core in this document, include the front-end analog multiplexers (MUXs), sample-and-hold
(S/H) circuits, the conversion core, voltage regulators, and other analog supporting circuits. Digital circuits,
referred to as the wrapper in this document, include programmable conversion sequencer, result registers,
interface to analog circuits, interface to device peripheral bus, and interface to other on-chip modules.
TMS320x281x Boot ROM Reference Guide (literature number SPRU095) describes the purpose and
features of the bootloader (factory-programmed boot-loading software). It also describes other contents of the
device on-chip boot ROM and identifies where all of the information is located within that memory.
TMS320x281x Event Manager (EV) Reference Guide (literature number SPRU065) describes the EV
modules that provide a broad range of functions and features that are particularly useful in motion control and
motor control applications. The EV modules include general-purpose (GP) timers, full-compare/PWM units,
capture units, and quadrature-encoder pulse (QEP) circuits.
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TMS320x281x External Interface (XINTF) Reference Guide (literature number SPRU067) describes the
external interface (XINTF) of the 281x digital signal processors (DSPs).
TMS320x281x Multi-channel Buffered Serial Ports (McBSPs) Reference Guide (literature number
SPRU061) describes the McBSP) available on the 281x devices. The McBSPs allow direct interface between
a DSP and other devices in a system.
TMS320x281x System Control and Interrupts Reference Guide (literature number SPRU078) describes
the various interrupts and system control features of the 281x digital signal processors (DSPs).
TMS320x281x, 280x Enhanced Controller Area Network (eCAN) Reference Guide (literature number
SPRU074) describes the eCAN that uses established protocol to communicate serially with other controllers
in electrically noisy environments. With 32 fully configurable mailboxes and time-stamping feature, the eCAN
module provides a versatile and robust serial communication interface. The eCAN module implemented in
the C28x DSP is compatible with the CAN 2.0B standard (active).
TMS320x281x, 280x Peripheral Reference Guide (literature number SPRU566) describes the peripheral
reference guides of the 28x digital signal processors (DSPs).
TMS320x281x, 280x Serial Communication Interface (SCI) Reference Guide (literature number
SPRU051) describes the SCI that is a two-wire asynchronous serial port, commonly known as a UART. The
SCI modules support digital communications between the CPU and other asynchronous peripherals that use
the standard non-return-to-zero (NRZ) format.
TMS320x281x, 280x Serial Peripheral Interface (SPI) Reference Guide (literature number SPRU059)
describes the SPI − a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer
rate. The SPI is used for communications between the DSP controller and external peripherals or another
controller.
3.3 V DSP for Digital Motor Control Application Report (literature number SPRA550). New generations
of motor control digital signal processors (DSPs) lower their supply voltages from 5 V to 3.3 V to offer higher
performance at lower cost. Replacing traditional 5-V digital control circuitry by 3.3-V designs introduce no
additional system cost and no significant complication in interfacing with TTL and CMOS compatible
components, as well as with mixed voltage ICs such as power transistor gate drivers. Just like 5-V based
designs, good engineering practice should be exercised to minimize noise and EMI effects by proper
component layout and PCB design when 3.3-V DSP, ADC, and digital circuitry are used in a mixed signal
environment, with high and low voltage analog and switching signals, such as a motor control system. In
addition, software techniques such as Random PWM method can be used by special features of the Texas
Instruments (TI) TMS320x24xx DSP controllers to significantly reduce noise effects caused by EMI radiation.
This application report reviews designs of 3.3-V DSP versus 5-V DSP for low HP motor control applications.
The application report first describes a scenario of a 3.3-V-only motor controller indicating that for most
applications, no significant issue of interfacing between 3.3 V and 5 V exists. Cost-effective 3.3-V − 5-V
interfacing techniques are then discussed for the situations where such interfacing is needed. On-chip 3.3-V
ADC versus 5-V ADC is also discussed. Sensitivity and noise effects in 3.3-V and 5-V ADC conversions are
addressed. Guidelines for component layout and printed circuit board (PCB) design that can reduce system’s
noise and EMI effects are summarized in the last section.
The TMS320C28x Instruction Set Simulator Technical Overview (literature number SPRU608) describes
the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the
instruction set of the C28x core.
TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guide (literature number
SPRU625) describes development using DSP/BIOS.
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TMS320C28x Assembly Language Tools User’s Guide (literature number SPRU513) describes the
assembly language tools (assembler and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x
device.
TMS320C28x Optimizing C Compiler User’s Guide (literature number SPRU514) describes the
TMS320C28x C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces
TMS320 DSP assembly language source code for the TMS320C28x device.
Programming Examples for the TMS320F281x eCAN (literature number SPRA876) contains several
programming examples to illustrate how the eCAN module is set up for different modes of operation. The
objective is to help you come up to speed quickly in programming the eCAN. All programs have been
extensively commented to aid easy understanding. The CANalyzer tool from Vector CANtech, Inc. was used
to monitor and control the bus operation. All projects and CANalyzer configuration files are included in the
attached SPRA876.zip file.
TMS320F2810, TMS320F2811, TMS320F2812 ADC Calibration (literature number SPRA989) describes a
method for improving the absolute accuracy of the 12-bit analog-to-digital converter (ADC) found on the
F2810/F2811/F2812 devices. Due to inherent gain and offset errors, the absolute accuracy of the ADC is
impacted. The methods described in this application note can improve the absolute accuracy of the ADC to
achieve levels better than 0.5%. This application note is accompanied by an example program
(ADCcalibration.zip) that executes from RAM on the F2812 EzDSP.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Updated information on the TMS320 DSP controllers can be found on the worldwide web at:
http://www.ti.com.
To send comments regarding this data manual, use the comments@books.sc.ti.com email address, which is
a repository for feedback. For questions and support, contact the Product Information Center listed at the
http://www.ti.com/sc/docs/pic/home.htm site.
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6
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320R281x DSPs.
6.1
Absolute Maximum Ratings
Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature
ranges. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated under Section 6.2 is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability. All voltage values are with respect to VSS.
Supply voltage range, VDDIO , VDDA1, VDDA2, VDDAIO, and AVDDREFBG . . . . . . . . . . . . . − 0.3 V to 4.6 V
Supply voltage range, VDD, VDD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 2.5 V
Input voltage range, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
Input clamp current, IIK (VIN < 0 or VIN > VDDIO)† . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Operating ambient temperature ranges, TA: A version (GHH, ZHH, PGF, PBK)‡ . . . . . . . . . − 40°C to 85°C
TA: S/Q version (GHH, ZHH, PGF, PBK)‡ . . . . . − 40°C to 125°C
TA: Q version (PGF, PBK)‡ . . . . . . . . . . . . . . . . . . − 40°C to 125°C
†
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
† Continuous clamp current per pin is± 2 mA
‡ Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device life.
For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for
TMS320LF24x and TMS320F281x Devices Application Report (literature number SPRA963).
§ Replaced by Q temperature option from silicon revision E onwards
June 2004 − Revised June 2006
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Electrical Specifications
Recommended Operating Conditions†
6.2
MIN
VDDIO
Device supply voltage, I/O
VDD , VDD1
Device supply voltage, CPU
VSS
VDDA1 , VDDA2 ,
AVDDREFBG, VDDAIO
Supply ground
NOM
MAX
UNIT
3.14
3.3
3.47
1.8 V (135 MHz)
1.71
1.8
1.89
1.9 V (150 MHz)
1.81
1.9
2
0
ADC supply voltage
3.14
3.3
3.47
2
150
2
135
All inputs except X1/XCLKIN
2
VDDIO
VDD
Device clock frequency
(system clock)
VIH
High-level input voltage
X1/XCLKIN (@ 50 µA max)
VIL
Low-level input voltage
X1/XCLKIN (@ 50 µA max)
IOH
High-level output source current,
VOH = 2.4 V
All I/Os except Group 2
Group 2‡
IOL
Low-level output sink current,
VOL = VOL MAX
All I/Os except Group 2
Group 2‡
TA
Ambient
temperature
V
V
VDD = 1.9 V ± 5%
VDD = 1.8 V ± 5%
fSYSCLKOUT
V
0.7VDD
All inputs except X1/XCLKIN
V
MHz
V
0.8
0.3VDD
−4
−8
V
mA
4
8
mA
A version
− 40
85
°C
Q version
− 40
125
°C
MAX
UNIT
† See Section 6.7 for power sequencing of VDDIO , VDDAIO , VDD , VDDA1 , VDDA2 , and AVDDREFBG .
‡ Group 2 pins are as follows: XINTF pins, T1CTRIP_PDPINTA, TDO, XCLKOUT, XF, EMU0, and EMU1.
6.3
Electrical Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted)
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
IIL
Input
current
(low level)
With pullup
TEST CONDITIONS
MIN
IOH = IOHMAX
2.4
IOH = 50 µA
IOL = IOLMAX
VDDIO = 3.3 V,
VIN = 0 V
TYP
V
VDDIO − 0.2
0.4
−80
−140
−190
With pulldown
VDDIO = 3.3 V, VIN = 0 V
±2
With pullup
VDDIO = 3.3 V, VIN = VDD
±2
With pulldown¶
VDDIO = 3.3 V,
VIN = VDD
IIH
Input
current
(high level)
IOZ
Output current,
high-impedance state
(off-state)
Ci
Input capacitance
V
µA
µA
28
50
80
±2
VO = VDDIO or 0 V
2
µA
pF
Co
Output capacitance
3
pF
§ The following pins have no internal PU/PD: GPIOE0, GPIOE1, GPIOF0, GPIOF1, GPIOF2, GPIOF3, GPIOF12, GPIOG4, and GPIOG5.
¶ The following pins have an internal pulldown: XMP/MC, TESTSEL, and TRST.
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6.4
Current Consumption by Power-Supply Pins Over Recommended Operating Conditions
During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320R281x)
MODE
TEST CONDITIONS
IDD
IDDA†
IDDIO
TYP
MAX‡
TYP
MAX‡
TYP
MAX‡
Operational
All peripheral clocks are enabled. All PWM pins are toggled
at 100 kHz.
Data is continuously transmitted out of the SCIA, SCIB, and
CAN ports. The hardware multiplier is exercised.
Code is running out of internal SARAM.
210 mA
260 mA
20 mA
30mA
40 mA
50 mA
IDLE
− XCLKOUT is turned off
− All peripheral clocks are on, except ADC
140 mA
155 mA
20 mA
30 mA
5 µA
10 µA
STANDBY
− Peripheral clocks are turned off
− Pins without an internal PU/PD are tied high/low
5 mA
10 mA
5 µA
20 µA
5 µA
10 µA
HALT
− Peripheral clocks are turned off
− Pins without an internal PU/PD are tied high/low
− Input clock is disabled
70 µA
5 µA
10 µA
1 µA
† IDDA includes current into VDDA1, VDDA2, VDD1, AVDDREFBG , and VDDAIO pins.
‡ MAX numbers are at 125°C, and max voltage (VDD = 2.0 V; VDDIO, VDDA = 3.6 V).
NOTE:
HALT and STANDBY modes cannot be used when the PLL is disabled.
6.5
Current Consumption Graphs
250
Current (mA)
200
150
100
50
0
0
20
40
IDD
60
IDDIO
80
100
SYSCLKOUT (MHz)
IDDA
120
140
160
Total 3.3−V current
NOTES: A. Test conditions are as defined in Table 6−4 for operational currents.
B. IDD represents the total current drawn from the 1.8-V rail (VDD). It includes a small amount of current ( 3
LSPCLK
‡ tc(SPC) = SPI clock cycle time = LSPCLK or
4
(SPIBRR ) 1)
tc(LCO) = LSPCLK cycle time
§ The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than the I/O buffer speed limit (20 MHz).
† The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
11§
10§
7§
6§
3§
2§
1
NO.
Table 6−24. SPI Master Mode External Timing (Clock Phase = 1)†‡
ns
ns
ns
ns
ns
ns
ns
UNIT
Electrical Specifications
June 2004 − Revised June 2006
Electrical Specifications
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
Data Valid
Master Out Data Is Valid
SPISIMO
10
11
Master In Data
Must Be Valid
SPISOMI
SPISTE†
† In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active
between back-to-back transmit words in both FIFO and nonFIFO modes..
Figure 6−23. SPI Master External Timing (Clock Phase = 1)
June 2004 − Revised June 2006
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Electrical Specifications
6.20 SPI Slave Mode Timing
Table 6−25. SPI Slave Mode External Timing (Clock Phase = 0)†‡
NO.
12
13§
14§
15§
MAX
tc(SPC)S
tw(SPCH)S
Cycle time, SPICLK
tw(SPCL)S
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
td(SPCH-SOMI)S
Delay time, SPICLK high to SPISOMI valid
(clock polarity = 0)
0.375tc(SPC)S −10
td(SPCL-SOMI)S
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
0.375tc(SPC)S −10
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =0)
0.75tc(SPC)S
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =1)
0.75tc(SPC)S
16§
19§
MIN
4tc(LCO)‡
tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 0)
ns
0.5tc(SPC)S −10
0.5tc(SPC)S −10
0.5tc(SPC)S
0.5tc(SPC)S
ns
0.5tc(SPC)S −10
0.5tc(SPC)S −10
0.5tc(SPC)S
0.5tc(SPC)S
ns
ns
ns
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
0
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
0
ns
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
0.5tc(SPC)S
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
0.5tc(SPC)S
20§
UNIT
ns
† The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
LSPCLK
‡ tc(SPC) = SPI clock cycle time = LSPCLK or
4
(SPIBRR ) 1)
tc(LCO) = LSPCLK cycle time
§ The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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Electrical Specifications
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE†
† In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and remain
low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6−24. SPI Slave Mode External Timing (Clock Phase = 0)
June 2004 − Revised June 2006
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113
Electrical Specifications
Table 6−26. SPI Slave Mode External Timing (Clock Phase = 1)†‡
NO.
12
13§
14§
17§
MIN
tc(SPC)S
tw(SPCH)S
Cycle time, SPICLK
tw(SPCL)S
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
tw(SPCH)S
tsu(SOMI-SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
tsu(SOMI-SPCL)S
Setup time, SPISOMI before SPICLK low (clock polarity = 1)
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =0)
0.75tc(SPC)S
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =1)
0.75tc(SPC)S
18§
21§
MAX
tsu(SIMO-SPCH)S
tsu(SIMO-SPCL)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 0)
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
8tc(LCO)
0.5tc(SPC)S −10
0.5tc(SPC)S −10
0.5tc(SPC)S
0.5tc(SPC)S
ns
0.5tc(SPC)S −10
0.5tc(SPC)S −10
0.5tc(SPC)S
0.5tc(SPC)S
ns
ns
0.125tc(SPC)S
0.125tc(SPC)S
ns
ns
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
0
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
0
ns
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
0.5tc(SPC)S
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
0.5tc(SPC)S
22§
UNIT
ns
† The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
LSPCLK
‡ tc(SPC) = SPI clock cycle time = LSPCLK or
4
(SPIBRR ) 1)
tc(LCO) = LSPCLK cycle time
§ The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
18
SPISOMI
Data Valid
SPISOMI Data Is Valid
21
22
SPISIMO
SPISIMO Data
Must Be Valid
SPISTE†
† In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6−25. SPI Slave Mode External Timing (Clock Phase = 1)
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Electrical Specifications
6.21 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail
wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 6−27 shows
the relationship between the parameters configured in the XTIMING register and the duration of the pulse in
terms of XTIMCLK cycles.
Table 6−27. Relationship Between Parameters Configured in XTIMING and Duration of Pulse†‡
DURATION (ns)
DESCRIPTION
X2TIMING = 0
X2TIMING = 1
XRDLEAD x tc(XTIM)
(XRDACTIVE + WS + 1) x tc(XTIM)
(XRDLEAD x 2) x tc(XTIM)
(XRDACTIVE x 2 + WS + 1) x tc(XTIM)
LR
Lead period, read access
AR
Active period, read access
TR
Trail period, read access
XRDTRAIL x tc(XTIM)
(XRDTRAIL x 2) x tc(XTIM)
LW
Lead period, write access
AW
Active period, write access
XWRLEAD x tc(XTIM)
(XWRACTIVE + WS + 1) x tc(XTIM)
(XWRLEAD x 2) x tc(XTIM)
(XWRACTIVE x 2 + WS + 1) x tc(XTIM)
TW
Trail period, write access
XWRTRAIL x tc(XTIM)
(XWRTRAIL x 2) x tc(XTIM)
† tc(XTIM) − Cycle time, XTIMCLK
‡ WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY (USEREADY = 0),
then WS = 0.
Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No internal
device hardware is included to detect illegal settings.
•
If the XREADY signal is ignored (USEREADY = 0), then:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
1. Lead:
These requirements result in the following XTIMING register configuration restrictions§:
XRDLEAD
XRDACTIVE
≥1
XRDTRAIL
≥0
XWRLEAD
≥0
XWRACTIVE
≥1
≥0
XWRTRAIL
X2TIMING
≥0
0, 1
§ No hardware to detect illegal XTIMING configurations
Examples of valid and invalid timing when not sampling XREADY§:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
0
0
0
0
0
0
0, 1
Valid
1
0
0
1
0
0
0, 1
§ No hardware to detect illegal XTIMING configurations
June 2004 − Revised June 2006
SPRS257C
115
Electrical Specifications
•
If the XREADY signal is sampled in the Synchronous mode (USEREADY = 1, READYMODE = 0), then:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
1. Lead:
AR ≥ 2 x tc(XTIM)
AW ≥ 2 x tc(XTIM)
NOTE: Restriction does not include external hardware wait states
2. Active:
These requirements result in the following XTIMING register configuration restrictions†:
XRDLEAD
XRDACTIVE
≥1
XRDTRAIL
≥1
XWRLEAD
≥0
XWRACTIVE
≥1
XWRTRAIL
≥1
≥0
X2TIMING
0, 1
† No hardware to detect illegal XTIMING configurations
Examples of valid and invalid timing when using Synchronous XREADY†:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
0
0
0
0
0
0
0, 1
Invalid
1
0
0
1
0
0
0, 1
Valid
1
1
0
1
1
0
0, 1
† No hardware to detect illegal XTIMING configurations
•
If the XREADY signal is sampled in the Asynchronous mode (USEREADY = 1, READYMODE = 1), then:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
1. Lead:
AR ≥ 2 x tc(XTIM)
AW ≥ 2 x tc(XTIM)
NOTE: Restriction does not include external hardware wait states
2. Active:
LR + AR ≥ 4 x tc(XTIM)
LW + AW ≥ 4 x tc(XTIM)
NOTE: Restriction does not include external hardware wait states
3. Lead + Active:
These requirements result in the following XTIMING register configuration restrictions†:
XRDLEAD
XRDACTIVE
≥1
XRDTRAIL
≥2
XWRLEAD
XWRACTIVE
≥1
0
XWRTRAIL
≥2
0
X2TIMING
0, 1
† No hardware to detect illegal XTIMING configurations
or†
XRDLEAD
XRDACTIVE
≥2
XRDTRAIL
≥1
XWRLEAD
XWRACTIVE
≥2
0
XWRTRAIL
≥1
0
X2TIMING
0, 1
† No hardware to detect illegal XTIMING configurations
Examples of valid and invalid timing when using Asynchronous XREADY†:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
0
0
0
0
0
0
0, 1
Invalid
1
0
0
1
0
0
0, 1
Invalid
1
1
0
1
1
0
0
Valid
1
1
0
1
1
0
1
Valid
1
2
0
1
2
0
0, 1
0
2
1
0
0, 1
Valid
2
1
† No hardware to detect illegal XTIMING configurations
116
SPRS257C
June 2004 − Revised June 2006
Electrical Specifications
Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6−28.
Table 6−28. XINTF Clock Configurations
Mode
SYSCLKOUT
XTIMCLK
XCLKOUT
1
Example:
150 MHz
SYSCLKOUT
150 MHz
SYSCLKOUT
150 MHz
2
Example:
150 MHz
SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
75 MHz
3
Example:
150 MHz
1/2 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
75 MHz
4
Example:
150 MHz
1/2 SYSCLKOUT
75 MHz
1/4 SYSCLKOUT
37.5 MHz
The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 6−26.
XTIMING0
XTIMING1
XTIMING2
LEAD/ACTIVE/TRAIL
XTIMING6
XTIMING7
XBANK
R28x
CPU
SYSCLKOUT
/2
1†
XTIMCLK
/2
1†
0
XCLKOUT
1
0
0
0
XINTCNF2
(XTIMCLK)
XINTCNF2
(CLKMODE)
XINTCNF2
(CLKOFF)
† Default Value after reset
Figure 6−26. Relationship Between XTIMCLK and SYSCLKOUT
6.22 XINTF Signal Alignment to XCLKOUT
For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock XTIMCLK.
Strobes such as XRD, XWE, and zone chip-select (XZCS) change state in relationship to the rising edge of
XTIMCLK. The external clock, XCLKOUT, can be configured to be either equal to or one-half the frequency
of XTIMCLK.
For the case where XCLKOUT = XTIMCLK, all of the XINTF strobes will change state with respect to the rising
edge of XCLKOUT. For the case where XCLKOUT = one-half XTIMCLK, some strobes will change state either
on the rising edge of XCLKOUT or the falling edge of XCLKOUT. In the XINTF timing tables, the notation
XCOHL is used to indicate that the parameter is with respect to either case; XCLKOUT rising edge (high) or
XCLKOUT falling edge (low). If the parameter is always with respect to the rising edge of XCLKOUT, the
notation XCOH is used.
June 2004 − Revised June 2006
SPRS257C
117
Electrical Specifications
For the case where XCLKOUT = one-half XTIMCLK, the XCLKOUT edge with which the change will be aligned
can be determined based on the number of XTIMCLK cycles from the start of the access to the point at which
the signal changes. If this number of XTIMCLK cycles is even, the alignment will be with respect to the rising
edge of XCLKOUT. If this number is odd, then the signal will change with respect to the falling edge of
XCLKOUT. Examples include the following:
•
Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT. This is
because all XINTF accesses begin with respect to the rising edge of XCLKOUT.
Examples:
•
XR/W active low
XRDL
XRD active low
XWEL
XWE active low
XRDH
XRD inactive high
XWEH
XWE inactive high
Strobes that change at the end of the access will align to the rising edge of XCLKOUT if the total number
of lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number of lead +
active + trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will be with
respect to the falling edge of XCLKOUT.
Examples:
118
XRNWL
Strobes that change at the beginning of the trail period will align to the rising edge of XCLKOUT if the total
number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If the
number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will
be with respect to the falling edge of XCLKOUT.
Examples:
•
Zone chip-select active low
Strobes that change at the beginning of the active period will align to the rising edge of XCLKOUT if the
total number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK cycles is odd,
then the alignment will be with respect to the falling edge of XCLKOUT.
Examples:
•
XZCSL
SPRS257C
XZCSH
Zone chip-select inactive high
XRNWH
XR/W inactive high
June 2004 − Revised June 2006
Electrical Specifications
6.23 External Interface Read Timing
Table 6−29. External Memory Interface Read Switching Characteristics
PARAMETER
MIN
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
Delay time, XCLKOUT high to zone chip-select active low
td(XCOH-XA)
td(XCOHL-XRDL)
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XRD active low
td(XCOHL-XRDH
th(XA)XZCSH
Delay time, XCLKOUT high/low to XRD inactive high
Delay time, XCLKOUT high/low to zone chip-select inactive high
MAX
−2
−2
†
Hold time, address valid after zone chip-select inactive high
UNIT
1
ns
3
ns
2
ns
1
ns
1
ns
ns
†
th(XA)XRD
Hold time, address valid after XRD inactive high
† During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
ns
Table 6−30. External Memory Interface Read Timing Requirements
MIN
ta(A)
ta(XRD)
MAX
UNIT
(LR + AR) − 14‡
AR − 12‡
Access time, read data from address valid
Access time, read data valid from XRD active low
tsu(XD)XRD
Setup time, read data valid before XRD strobe inactive high
th(XD)XRD
Hold time, read data valid after XRD inactive high
‡ LR = Lead period, read access. AR = Active period, read access. See Table 6−27.
ns
12
ns
0
ns
Trail
Active
Lead
ns
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOHL-XZCSH)
td(XCOH-XA)
XA[0:18]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
XWE
XR/W
ta(A)
th(XD)XRD
ta(XRD)
DIN
XD[0:15]
XREADY
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
Figure 6−27. Example Read Access
XTIMING register parameters used for this example:
XRDLEAD
≥1
XRDACTIVE
XRDTRAIL
≥0
≥0
USEREADY
0
X2TIMING
0
XWRLEAD
N/A†
XWRACTIVE
N/A†
XWRTRAIL
N/A†
READYMODE
N/A†
† N/A = “Don’t care” for this example
June 2004 − Revised June 2006
SPRS257C
119
Electrical Specifications
6.24 External Interface Write Timing
Table 6−31. External Memory Interface Write Switching Characteristics
PARAMETER
MIN
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
Delay time, XCLKOUT high to zone chip-select active low
td(XCOH-XA)
td(XCOHL-XWEL)
MAX
UNIT
1
ns
3
ns
Delay time, XCLKOUT high to address valid
2
ns
Delay time, XCLKOUT high/low to XWE low
2
ns
td(XCOHL-XWEH)
td(XCOH-XRNWL)
Delay time, XCLKOUT high/low to XWE high
2
ns
1
ns
td(XCOHL-XRNWH)
ten(XD)XWEL
Delay time, XCLKOUT high/low to XR/W high
1
ns
td(XWEL-XD)
Delay time, data valid after XWE active low
th(XA)XZCSH
th(XD)XWE
Hold time, address valid after zone chip-select inactive high
Delay time, XCLKOUT high or low to zone chip-select inactive high
−2
Delay time, XCLKOUT high to XR/W low
−2
Enable time, data bus driven from XWE low
0
ns
4
Hold time, write data valid after XWE inactive high
ns
†
ns
TW−2‡
ns
tdis(XD)XRNW
Data bus disabled after XR/W inactive high
4
† During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
‡ TW = Trail period, write access. See Table 6−27.
ns
Active
Lead
Trail
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOH-XA)
XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
XWE
td(XCOHL-XRNWH)
td(XCOH-XRNWL)
XR/W
tdis(XD)XRNW
th(XD)XWEH
td(XWEL-XD)
ten(XD)XWEL
DOUT
XD[0:15]
XREADY
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment
cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
Figure 6−28. Example Write Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
N/A†
XRDTRAIL
N/A†
N/A†
USEREADY
0
X2TIMING
0
XWRLEAD
≥1
XWRACTIVE
≥0
XWRTRAIL
≥0
READYMODE
N/A†
† N/A = “Don’t care” for this example
120
SPRS257C
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Electrical Specifications
6.25 External Interface Ready-on-Read Timing With One External Wait State
Table 6−32. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
Delay time, XCLKOUT high to zone chip-select active low
td(XCOH-XA)
td(XCOHL-XRDL)
Delay time, XCLKOUT high to address valid
td(XCOHL-XRDH
th(XA)XZCSH
Delay time, XCLKOUT high/low to XRD inactive high
MIN
Delay time, XCLKOUT high/low to zone chip-select inactive high
−2
Delay time, XCLKOUT high/low to XRD active low
−2
†
Hold time, address valid after zone chip-select inactive high
MAX
UNIT
1
ns
3
ns
2
ns
1
ns
1
ns
ns
†
th(XA)XRD
Hold time, address valid after XRD inactive high
† During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
ns
Table 6−33. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
ta(A)
ta(XRD)
(LR + AR) − 14‡
AR − 12‡
Access time, read data from address valid
Access time, read data valid from XRD active low
tsu(XD)XRD
Setup time, read data valid before XRD strobe inactive high
th(XD)XRD
Hold time, read data valid after XRD inactive high
‡ LR = Lead period, read access. AR = Active period, read access. See Table 6−27.
MAX
UNIT
ns
ns
12
ns
0
ns
Table 6−34. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)§
MIN
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
Setup time, XREADY (Synch) low before XCLKOUT high/low
15
Hold time, XREADY (Synch) low
12
te(XRDYsynchH)
tsu(XRDYsynchH)XCOHL
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
Setup time, XREADY (Synch) high before XCLKOUT high/low
MAX
UNIT
ns
ns
3
15
ns
ns
th(XRDYsynchH)XZCSH
Hold time, XREADY (Synch) held high after zone chip select high
0
ns
§ The first XREADY (Synch) sample occurs with respect to E in Figure 6−29:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found to be low, it will be sampled
again each tc(XTIM) until it is found to be high.
For each sample (n) the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6−35. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)¶
MIN
tsu(XRDYAsynchL)XCOHL
th(XRDYAsynchL)
Setup time, XREADY (Asynch) low before XCLKOUT high/low
te(XRDYAsynchH)
tsu(XRDYAsynchH)XCOHL
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge
Hold time, XREADY (Asynch) low
Setup time, XREADY (Asynch) high before XCLKOUT high/low
MAX
11
UNIT
ns
8
ns
3
11
ns
ns
th(XRDYasynchH)XZCSH
Hold time, XREADY (Asynch) held high after zone chip select high
0
ns
¶ The first XREADY (Asynch) sample occurs with respect to E in Figure 6−30:
E = (XRDLEAD + XRDACTIVE −2) tc(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is found to be low, it will be
sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE −3 +n) tc(XTIM) − tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
June 2004 − Revised June 2006
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121
Electrical Specifications
WS (Synch)
See Notes A and B
Active
Lead
Trail
See Note C
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOH-XA)
XA[0:18]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
XWE
ta(XRD)
XR/W
ta(A)
th(XD)XRD
XD[0:15]
DIN
tsu(XRDYsynchL)XCOHL
te(XRDYsynchH)
th(XRDYsynchL)
th(XRDYsynchH)XZCSH
tsu(XRDHsynchH)XCOHL
XREADY(Synch)
See Note D
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
D. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XRDLEAD + XRDACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL
E. Reference for the first sample is with respect to this point
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
where n is the sample number: n = 1, 2, 3, and so forth.
Figure 6−29. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
≥1
XRDTRAIL
3
≥1
USEREADY
1
X2TIMING
0
XWRLEAD
N/A†
XWRACTIVE
N/A†
XWRTRAIL
N/A†
READYMODE
0 = XREADY
(Synch)
† N/A = “Don’t care” for this example
122
SPRS257C
June 2004 − Revised June 2006
Electrical Specifications
WS (Asynch)
Active
"
#
Lead
See Note C
Trail
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOHL-XZCSH)
td(XCOH-XA)
XA[0:18]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
tsu(XD)XRD
XWE
ta(XRD)
XR/W
ta(A)
th(XD)XRD
DIN
XD[0:15]
tsu(XRDYasynchL)XCOHL
te(XRDYasynchH)
th(XRDYasynchH)XZCSH
th(XRDYasynchL)
tsu(XRDYasynchH)XCOHL
XREADY(Asynch)
See Note D
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment
cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment
cycles.
D. For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE −3 +n) tc(XTIM) − tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
E. Reference for the first sample is with respect to this point:
E = (XRDLEAD + XRDACTIVE −2) tc(XTIM)
Figure 6−30. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
≥1
XRDACTIVE
XRDTRAIL
3
≥1
USEREADY
1
X2TIMING
0
XWRLEAD
N/A†
XWRACTIVE
N/A†
XWRTRAIL
N/A†
READYMODE
1 = XREADY
(Asynch)
† N/A = “Don’t care” for this example
June 2004 − Revised June 2006
SPRS257C
123
Electrical Specifications
6.26 External Interface Ready-on-Write Timing With One External Wait State
Table 6−36. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
PARAMETER
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
Delay time, XCLKOUT high to zone chip-select active low
td(XCOH-XA)
td(XCOHL-XWEL)
Delay time, XCLKOUT high to address valid
MIN
MAX
UNIT
1
ns
3
ns
2
ns
Delay time, XCLKOUT high/low to XWE low
2
ns
td(XCOHL-XWEH)
td(XCOH-XRNWL)
Delay time, XCLKOUT high/low to XWE high
2
ns
Delay time, XCLKOUT high to XR/W low
1
ns
td(XCOHL-XRNWH)
ten(XD)XWEL
Delay time, XCLKOUT high/low to XR/W high
1
ns
td(XWEL-XD)
Delay time, data valid after XWE active low
th(XA)XZCSH
th(XD)XWE
Delay time, XCLKOUT high or low to zone chip-select inactive high
−2
−2
Enable time, data bus driven from XWE low
0
ns
4
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE inactive high
ns
†
ns
TW−2‡
ns
tdis(XD)XRNW
Data bus disabled after XR/W inactive high
4
† During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
‡ TW = trail period, write access (see Table 6−27)
ns
Table 6−37. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)§
MIN
MAX
UNIT
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
Setup time, XREADY (Synch) low before XCLKOUT high/low
15
ns
Hold time, XREADY (Synch) low
12
ns
te(XRDYsynchH)
tsu(XRDYsynchH)XCOHL
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
Setup time, XREADY (Synch) high before XCLKOUT high/low
3
15
ns
ns
th(XRDYsynchH)XZCSH
Hold time, XREADY (Synch) held high after zone chip select high
0
ns
§ The first XREADY (Synch) sample occurs with respect to E in Figure 6−31:
E =(XWRLEAD + XWRACTIVE) tc(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found to be low, it will be sampled
again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D =(XWRLEAD + XWRACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6−38. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)¶
MIN
tsu(XRDYasynchL)XCOHL
th(XRDYasynchL)
Setup time, XREADY (Asynch) low before XCLKOUT high/low
te(XRDYasynchH)
tsu(XRDYasynchH)XCOHL
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge
Hold time, XREADY (Asynch) low
Setup time, XREADY (Asynch) high before XCLKOUT high/low
MAX
11
ns
8
ns
3
11
UNIT
ns
ns
th(XRDYasynchH)XZCSH
Hold time, XREADY (Asynch) held high after zone chip select high
0
ns
¶ The first XREADY (Synch) sample occurs with respect to E in Figure 6−32:
E = (XWRLEAD + XWRACTIVE − 2) tc(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is found to be low, it will be
sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE −3 + n) tc(XTIM) − tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
124
SPRS257C
June 2004 − Revised June 2006
Electrical Specifications
WS (Synch)
See
NotesA
and B
SeeNoteC
Trail
Active
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
th(XRDYsynchH)XZCSH
td(XCOH-XA)
XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
XWE
td(XCOHL-XRNWH)
td(XCOH-XRNWL)
XR/W
tdis(XD)XRNW
td(XWEL-XD)
th(XD)XWEH
ten(XD)XWEL
XD[0:15]
DOUT
tsu(XRDYsynchL)XCOHL
te(XRDYsynchH)
th(XRDYsynchL)
tsu(XRDHsynchH)XCOHL
XREADY(Synch)
See Note D
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES:
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle before an
access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
D. For each sample, setup time from the beginning of the access can be calculated as
D = (XWRLEAD + XWRACTIVE + n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3 and so forth.
E. Reference for the first sample is with respect to this point
E = (XWRLEAD + XWRACTIVE) tc(XTIM)
Figure 6−31. Write With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
N/A†
XRDACTIVE
N/A†
June 2004 − Revised June 2006
XRDTRAIL
N/A†
USEREADY
1
X2TIMING
0
XWRLEAD
≥1
XWRACTIVE
3
XWRTRAIL
≥1
READYMODE
0 = XREADY
(Synch)
SPRS257C
125
Electrical Specifications
WS (Asynch)
"
#
"
Trail
Active
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
th(XRDYasynchH)XZCSH
td(XCOH-XA)
XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
XWE
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
XR/W
tdis(XD)XRNW
td(XWEL-XD)
th(XD)XWEH
ten(XD)XWEL
XD[0:15]
DOUT
tsu(XRDYasynchL)XCOHL
th(XRDYasynchL)
te(XRDYasynchH)
tsu(XRDYasynchH)XCOHL
XREADY(Asynch)
See Note D
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
D. For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE −3 + n) tc(XTIM) − tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3 and so forth.
E. Reference for the first sample is with respect to this point
E = (XWRLEAD + XWRACTIVE −2) tc(XTIM)
Figure 6−32. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
N/A†
XRDTRAIL
N/A†
N/A†
USEREADY
1
X2TIMING
0
XWRLEAD
≥1
XWRACTIVE
3
XWRTRAIL
≥1
READYMODE
1 = XREADY
(Asynch)
† N/A = “Don’t care” for this example
126
SPRS257C
June 2004 − Revised June 2006
Electrical Specifications
6.27 XHOLD and XHOLDA
If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of
high-impedance mode.
On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the bus
and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active low.
When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still execute
code from internal memory. If an access is made to the external interface, the CPU is stalled until the XHOLD
signal is removed.
An external DMA request, when granted, places the following signals in a high-impedance mode:
XA[18:0]
XZCS0AND1
XD[15:0]
XZCS2
XWE, XRD
XZCS6AND7
XR/W
All other signals not listed in this group remain in their default or functional operational modes during these
signal events.
June 2004 − Revised June 2006
SPRS257C
127
Electrical Specifications
6.28 XHOLD/XHOLDA Timing
Table 6−39. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)†‡
MIN
td(HL-HiZ)
td(HL-HAL)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
MAX
UNIT
4tc(XTIM)
5tc(XTIM)
Delay time, XHOLD low to XHOLDA low
ns
ns
td(HH-HAH)
Delay time, XHOLD high to XHOLDA high
3tc(XTIM)
ns
td(HH-BV)
Delay time, XHOLD high to Bus valid
4tc(XTIM)
ns
† When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance state.
‡ The state of XHOLD is latched on the rising edge of XTIMCLK.
XCLKOUT
(/1 Mode)
td(HL-Hiz)
XHOLD
td(HH-HAH)
XHOLDA
td(HL-HAL)
XR/W,
XZCS0AND1,
XZCS2,
XZCS6AND7
XA[18:0]
XD[15:0]
td(HH-BV)
High-Impedance
Á
Á
Valid
Á
Á
High-Impedance
Valid
Valid
See Note A
See Note B
NOTES: A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6−33. External Interface Hold Waveform
128
SPRS257C
June 2004 − Revised June 2006
Electrical Specifications
Table 6−40. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)†‡§
MIN
td(HL-HiZ)
td(HL-HAL)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
Delay time, XHOLD low to XHOLDA low
MAX
UNIT
4tc(XTIM)+tc(XCO)
4tc(XTIM+2tc(XCO)
ns
ns
td(HH-HAH)
Delay time, XHOLD high to XHOLDA high
4tc(XTIM)
ns
td(HH-BV)
Delay time, XHOLD high to Bus valid
6tc(XTIM)
ns
† When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance state.
‡ The state of XHOLD is latched on the rising edge of XTIMCLK.
§ After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions will occur with respect to the rising edge of XCLKOUT. Thus,
for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value specified.
XCLKOUT
(1/2 XTIMCLK)
td(HL-HAL)
XHOLD
td(HH-HAH)
XHOLDA
td(HL-HiZ)
td(HH-BV)
XR/W,
XZCS0AND1,
XZCS2,
XZCS6AND7
High-Impedance
Valid
XA[18:0]
ÁÁ
ÁÁ
Valid
XD[15:0]
See Note A
NOTES:
High-Impedance
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Valid
High-Impedance
See Note B
A All pending XINTF accesses are completed.
B Normal XINTF operation resumes.
Figure 6−34. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
June 2004 − Revised June 2006
SPRS257C
129
Electrical Specifications
6.29 On-Chip Analog-to-Digital Converter
6.29.1 ADC Absolute Maximum Ratings †
Supply voltage range,
VSSA1/VSSA2 to VDDA1/VDDA2/AVDDREFBG . . . . . . . . . . . . . . . −0.3 V to 4.6 V
VSS1 to VDD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.5 V
Analog Input (ADCIN) Clamp Current, total (max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA‡
† Unless otherwise noted, the list of absolute maximum ratings are specified over operating conditions. Stresses beyond those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
‡ The analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above VDDA or below VSS. The continuous clamp
current per pin is ± 2 mA.
130
SPRS257C
June 2004 − Revised June 2006
Electrical Specifications
6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions
Table 6−41. DC Specifications (See Note 1)
PARAMETER
MIN
Resolution
TYP
MAX
UNIT
12
Bits
1
ADC clock (See Note 2)
kHz
25
MHz
±1.5
LSB
±1
LSB
ACCURACY
INL (Integral nonlinearity)
DNL (Differential nonlinearity)
Offset error (See Note 3)
−80
80
LSB
Overall gain error with internal reference
(See Note 4)
−80
80
LSB
−50
50
LSB
Overall gain error with external reference
(See Note 5)
If ADCREFP-ADCREFM = 1 V ±0.1%
Channel-to-channel offset variation
±8
LSB
Channel-to-channel Gain variation
±8
LSB
ANALOG INPUT
Analog input voltage (ADCINx to ADCLO)
(See Note 6)
ADCLO
0
−5
Input capacitance
0
3
V
5
mV
±5
µA
10
Input leakage current
3
pF
INTERNAL VOLTAGE REFERENCE (See Note 4)
Accuracy, ADCVREFP
1.9
2
2.1
V
Accuracy, ADCVREFM
0.95
1
1.05
V
Voltage difference, ADCREFP - ADCREFM
Temperature coefficient
Reference noise
1
V
50
PPM/°C
100
µV
EXTERNAL VOLTAGE REFERENCE (See Note 5)
Accuracy, ADCVREFP
1.9
2
2.1
V
Accuracy, ADCVREFM
0.95
1
1.05
V
Input voltage difference,
ADCREFP - ADCREFM
0.99
1
1.01
V
NOTES: 1.
2.
3.
4.
Tested at 12.5-MHz ADCCLK
If SYSCLKOUT ≤ 25 MHz, ADC clock ≤ SYSCLKOUT/2
1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
A single tirmmed internal band gap reference sources both ADCREFP and ADCREFM signals, and hence, these voltages track
together. The ADC converter uses the difference between these two as its reference. The total gain error will be the combination
of the gain error shown here and the voltage reference accuracy (ADCREFP - ADCREFM). A software-based calibration
procedure is recommended for better accuracy. See F2812 ADC Calibration Application Note (literature number SPRA989) and
Section 5.2, Documentation Support, for relevant documents.
5. In this mode, the accuracy of external reference is critical for overall gain. The voltage difference (ADCREFP-ADCREFM) will
determine the overall accuracy.
6. Voltages above VDDA + 0.3 V or below VSS - 0.3 V applied to an analog input pin may temporarily affect the conversion of another
pin. To avoid this, the analog inputs should be kept within these limits.
June 2004 − Revised June 2006
SPRS257C
131
Electrical Specifications
Table 6−42. AC Specifications
PARAMETER
MIN
TYP
MAX
UNIT
SINAD
Signal-to-noise ratio + distortion
64
dB
SNR
Signal-to-noise ratio
66
dB
THD (100 kHz)
Total harmonic distortion
−68
dB
ENOB (SNR)
Effective number of bits
10.7
Bits
SFDR
Spurious free dynamic range
70
dB
6.29.3 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)‡
IDDA (TYP)§
IDDAIO (TYP)
IDD1 (TYP)
ADC OPERATING MODE/CONDITIONS
Mode A (Operational Mode):
− BG and REF enabled
− PWD disabled
40 mA
1 µA
0.5 mA
7 mA
0
5 µA
Mode B:
− ADC clock enabled
− BG and REF enabled
− PWD enabled
5 µA
Mode C:
− ADC clock enabled
− BG and REF disabled
− PWD enabled
0
Mode D:
− ADC clock disabled
− BG and REF disabled
− PWD enabled
1 µA
1 µA
0
0
‡ Test Conditions:
SYSCLKOUT = 150 MHz
ADC module clock = 25 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
§ IDDA − includes current into VDDA1 / VDDA2 and AVDDREFBG
132
SPRS257C
June 2004 − Revised June 2006
Electrical Specifications
Rs
Source
Signal
ADCIN0
Ron
1 kΩ
Switch
Cp
10 pF
ac
Ch
1.25 pF
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (Ron):
Sampling Capacitor (Ch):
Parasitic Capacitance (Cp):
Source Resistance (Rs):
1 kΩ
1.25 pF
10 pF
50 Ω
Figure 6−35. ADC Analog Input Impedance Model
6.29.4 ADC Power-Up Control Bit Timing
ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
td(BGR)
PWDNADC
td(PWD)
Request for
ADC
Conversion
Figure 6−36. ADC Power-Up Control Bit Timing
Table 6−43. ADC Power-Up Delays†
td(BGR)
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3 register
(ADCBGRFDN1/0) are to be set to 1 before the ADCPWDN bit is enabled.
td(PWD)
Delay time for power-down control to be stable. Bit 5 of the ADCTRL3 register
(ADCPWDN) is to be set to 1 before any ADC conversions are initiated.
MIN
TYP
MAX
UNIT
7
8
10
ms
20
50
1
ms
µs
† These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are initiated. If conversions
are started without these delays, the ADC results will show a higher gain. For power down, all three bits can be cleared at the same time.
June 2004 − Revised June 2006
SPRS257C
133
Electrical Specifications
6.29.5 Detailed Description
6.29.5.1
Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC. ADCVREFP
is set to 2.0 V and ADCVREFM is set to 1.0 V.
6.29.5.2
Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at a
time. These inputs are software-selectable.
6.29.5.3
Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with low
power consumption.
6.29.5.4
Conversion Modes
The conversion can be performed in two different conversion modes:
•
•
Sequential sampling mode (SMODE = 0)
Simultaneous sampling mode (SMODE = 1)
6.29.6 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax
to Bx). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software
trigger, or from an external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected
channel on every Sample/Hold pulse. The conversion time and latency of the Result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update.
The selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse
width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
134
SPRS257C
June 2004 − Revised June 2006
Electrical Specifications
Sample n+2
Sample n+1
Analog Input on
Channel Ax or Bx
Sample n
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
td(SH)
tdschx_n+1
tdschx_n
ADC Event Trigger
from EV or Other
Sources
tSH
Figure 6−37. Sequential Sampling Mode (Single-Channel) Timing
Table 6−44. Sequential Sampling Mode Timing
SAMPLE n
SAMPLE n + 1
AT 25-MHz ADC
CLOCK,
tc(ADCCLK) = 40 ns
td(SH)
Delay time from event
trigger to sampling
tSH
Sample/Hold width/
Acquisition width
(1 + Acqps) *
tc(ADCCLK)
40 ns with Acqps = 0
td(schx_n)
Delay time for first result
to appear in the Result
register
4tc(ADCCLK)
160 ns
td(schx_n+1)
Delay time for successive
results to appear in the
Result register
June 2004 − Revised June 2006
REMARKS
2.5tc(ADCCLK)
(2 + Acqps) *
tc(ADCCLK)
Acqps value = 0-15
ADCTRL1[8:11]
80 ns
SPRS257C
135
Electrical Specifications
6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels (A0/B0
to A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software
trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected
channels on every Sample/Hold pulse. The conversion time and latency of the Result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update.
The selected channels will be sampled simultaneously at the falling edge of the Sample/Hold pulse. The
Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide
(maximum).
NOTE:
In Simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ...,
A7/B7, and not in other combinations (such as A1/B3, etc.).
Sample n
Sample n+1
Analog Input on
Channel Ax
Analog Input on
Channel Bv
Sample n+2
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
td(SH)
tdschA0_n+1
tSH
ADC Event Trigger
from EV or Other
Sources
tdschA0_n
tdschB0_n+1
tdschB0_n
Figure 6−38. Simultaneous Sampling Mode Timing
Table 6−45. Simultaneous Sampling Mode Timing
SAMPLE n
SAMPLE n + 1
AT 25-MHz ADC
CLOCK,
tc(ADCCLK) = 40 ns
td(SH)
Delay time from event
trigger to sampling
tSH
Sample/Hold width/
Acquisition Width
(1 + Acqps) *
tc(ADCCLK)
40 ns with Acqps = 0
td(schA0_n)
Delay time for first result
to appear in Result
register
4tc(ADCCLK)
160 ns
td(schB0_n)
Delay time for first result
to appear in Result
register
5tc(ADCCLK)
200 ns
td(schA0_n+1)
Delay time for
successive results to
appear in Result register
(3 + Acqps) *
tc(ADCCLK)
120 ns
td(schB0_n+1)
Delay time for
successive results to
appear in Result register
(3 + Acqps) *
tc(ADCCLK)
120 ns
136
SPRS257C
REMARKS
2.5tc(ADCCLK)
Acqps value = 0-15
ADCTRL1[8:11]
June 2004 − Revised June 2006
Electrical Specifications
6.29.8 Definitions of Specifications and Terminology
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full
scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined
as level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular
code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code
transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N+
(SINAD * 1.76)
6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input
signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
June 2004 − Revised June 2006
SPRS257C
137
Electrical Specifications
6.30 Multichannel Buffered Serial Port (McBSP) Timing
6.30.1 McBSP Transmit and Receive Timing
Table 6−46. McBSP Timing Requirements†‡
NO.
MIN
MAX
UNIT
20§
MHz
1
McBSP module clock (CLKG, CLKX, CLKR) range
kHz
50
McBSP module cycle time (CLKG, CLKX, CLKR) range
M11
M12
M13
M14
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
P-7
tr(CKRX)
tf(CKRX)
Rise time, CLKR/X
CLKR/X ext
Fall time, CLKR/X
CLKR/X ext
M15
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
M16
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
M17
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
M18
th(CKRL-DRV)
Hold time, DR valid after CLKR low
M19
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
M20
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
ns
1
CLKR int
18
CLKR ext
2
CLKR int
0
CLKR ext
6
CLKR int
18
CLKR ext
2
CLKR int
0
CLKR ext
6
CLKX int
18
CLKX ext
2
CLKX int
0
CLKX ext
6
ms
ns
ns
7
ns
7
ns
ns
ns
ns
ns
ns
ns
† Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
CLKSRG
‡ 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG =
.
(1 ) CLKGDV)
CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
§ Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer speed
limit (20 MHz).
138
SPRS257C
June 2004 − Revised June 2006
Electrical Specifications
Table 6−47. McBSP Switching Characteristics†‡
NO.
M1
PARAMETER
MIN
MAX
2P
D-5§
C-5§
D+5§
C+5§
ns
CLKR int
0
4
ns
CLKR ext
3
27
ns
CLKX int
0
4
CLKX ext
3
27
tc(CKRX)
tw(CKRXH)
Cycle time, CLKR/X
CLKR/X int
M2
Pulse duration, CLKR/X high
CLKR/X int
M3
tw(CKRXL)
Pulse duration, CLKR/X low
CLKR/X int
M4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
M5
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
M6
tdis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance
following last data bit
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
M7
td(CKXH-DXV)
Delay time, CLKX high to DX valid
DXENA = 0
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY=01b or 10b) modes
DXENA = 1
Enable time, CLKX high to DX driven
M8
M9
M10
DXENA = 0
ten(CKXH-DX)
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY=01b or 10b) modes
DXENA = 1
Delay time, FSX high to DX valid
DXENA = 0
td(FXH-DXV)
ten(FXH-DX)
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY=00b) mode.
DXENA = 1
Enable time, FSX high to DX driven
DXENA = 0
ns
CLKX int
8
CLKX ext
14
CLKX int
9
CLKX ext
28
CLKX int
8
CLKX ext
14
CLKX int
P+8
CLKX ext
UNIT
ns
ns
ns
ns
P + 14
CLKX int
0
CLKX ext
6
CLKX int
P
CLKX ext
P+6
ns
FSX int
8
FSX ext
14
FSX int
P+8
FSX ext
P + 14
FSX int
0
FSX ext
6
FSX int
P
ns
ns
Only applies to first bit transmitted when in Data DXENA = 1
FSX ext
P+6
Delay 0 (XDATDLY=00b) mode
† Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
‡ 2P = 1/CLKG in ns.
§ C=CLKRX low pulse width = P
D=CLKRX high pulse width = P
June 2004 − Revised June 2006
SPRS257C
139
Electrical Specifications
M1, M11
M2, M12
M13
M3, M12
CLKR
M4
M4
M14
FSR (int)
M15
M16
FSR (ext)
M18
M17
DR
(RDATDLY=00b)
Bit (n−1)
(n−2)
(n−3)
M17
(n−4)
M18
DR
(RDATDLY=01b)
Bit (n−1)
(n−2)
M17
(n−3)
M18
DR
(RDATDLY=10b)
Bit (n−1)
(n−2)
Figure 6−39. McBSP Receive Timing
M1, M11
M2, M12
M13
M3, M12
M14
CLKX
M5
M5
FSX (int)
M19
M20
FSX (ext)
M9
M7
M10
DX
(XDATDLY=00b)
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−4)
(n−2)
(n−3)
M7
M8
DX
(XDATDLY=01b)
Bit 0
Bit (n−1)
M7
M6
DX
(XDATDLY=10b)
M8
Bit 0
Bit (n−1)
(n−2)
Figure 6−40. McBSP Transmit Timing
140
SPRS257C
June 2004 − Revised June 2006
Electrical Specifications
6.30.2 McBSP as SPI Master or Slave Timing
Table 6−48. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER
NO.
M30
MIN
SLAVE
MAX
MIN
MAX
UNIT
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
P-10
8P-10
ns
M31
Hold time, DR valid after CLKX low
P-10
8P-10
ns
M32
tsu(BFXL-CKXH)
Setup time, FSX low before CLKX high
8P+10
ns
M33
tc(CKX)
Cycle time, CLKX
16P
ns
2P
Table 6−49. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)†
MASTER
NO.
M24
M25
M28
PARAMETER
th(CKXL-FXL)
td(FXL-CKXH)
tdis(FXH-DXHZ)
MIN
SLAVE
MAX
MIN
MAX
UNIT
Hold time, FSX low after CLKX low
2P
ns
Delay time, FSX low to CLKX high
P
ns
Disable time, DX high impedance following
last data bit from FSX high
6
6P + 6
ns
M29
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
† 2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
M32
LSB
M33
MSB
CLKX
M25
M24
FSX
M28
DX
M29
Bit 0
Bit(n-1)
M30
DR
Bit 0
(n-2)
(n-3)
(n-4)
M31
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6−41. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
June 2004 − Revised June 2006
SPRS257C
141
Electrical Specifications
Table 6−50. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)†
MASTER
NO.
M39
MIN
MAX
Setup time, DR valid before CLKX high
P-10
M40
tsu(DRV-CKXH)
th(CKXH-DRV)
Hold time, DR valid after CLKX high
P-10
M41
tsu(FXL-CKXH)
Setup time, FSX low before CLKX high
M42
tc(CKX)
Cycle time, CLKX
2P
SLAVE
MIN
UNIT
MAX
8P-10
ns
8P-10
ns
16P+10
ns
16P
ns
Table 6−51. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)†
MASTER
NO.
M34
PARAMETER
M35
th(CKXL-FXL)
td(FXL-CKXH)
M37
tdis(CKXL-DXHZ)
MIN
MAX
SLAVE
MIN
UNIT
MAX
Hold time, FSX low after CLKX low
P
ns
Delay time, FSX low to CLKX high
2P
ns
Disable time, DX high impedance following last data bit
from CLKX low
P+6
7P+6
ns
M38
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
† 2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
LSB
M42
MSB
M41
CLKX
M34
M35
FSX
M37
DX
M38
Bit 0
Bit(n-1)
M39
DR
Bit 0
(n-2)
(n-3)
(n-4)
M40
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6−42. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
142
SPRS257C
June 2004 − Revised June 2006
Electrical Specifications
Table 6−52. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)†
MASTER
NO.
M49
MIN
Setup time, DR valid before CLKX high
P-10
M50
tsu(DRV-CKXH)
th(CKXH-DRV)
Hold time, DR valid after CLKX high
P-10
M51
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
M52
tc(CKX)
Cycle time, CLKX
SLAVE
MAX
MIN
MAX
UNIT
8P-10
ns
8P-10
ns
8P+10
ns
16P
ns
2P
Table 6−53. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)†
MASTER
NO.
M43
PARAMETER
M44
th(CKXH-FXL)
td(FXL-CKXL)
M47
tdis(FXH-DXHZ)
MIN
Hold time, FSX low after CLKX high
MAX
SLAVE
MIN
MAX
UNIT
2P
ns
Delay time, FSX low to CLKX low
P
ns
Disable time, DX high impedance following last data bit
from FSX high
6
6P + 6
ns
M48
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
† 2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
M52
MSB
M51
LSB
CLKX
M43
M44
FSX
M47
DX
M48
Bit 0
Bit(n-1)
M49
DR
Bit 0
(n-2)
(n-3)
(n-4)
M50
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6−43. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
June 2004 − Revised June 2006
SPRS257C
143
Electrical Specifications
Table 6−54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)†
MASTER
SLAVE
MIN
MIN
NO.
M58
tsu(DRV-CKXL)
th(CKXL-DRV)
M59
MAX
MAX
UNIT
Setup time, DR valid before CLKX low
P - 10
8P - 10
ns
Hold time, DR valid after CLKX low
P - 10
8P - 10
ns
16P +
10
ns
16P
ns
M60
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
M61
tc(CKX)
Cycle time, CLKX
2P
Table 6−55. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)†
MASTER‡
NO.
PARAMETER
M53
th(CKXH-FXL)
td(FXL-CKXL)
M54
M56
tdis(CKXH-DXHZ)
MIN
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
Disable time, DX high impedance following last data bit
from CLKX high
SLAVE
MAX
MIN
MAX
UNIT
P
ns
2P
ns
P+6
7P + 6
ns
M57
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
† 2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
‡ C = CLKX low pulse width = P
D = CLKX high pulse width = P
M60
LSB
M61
MSB
CLKX
M53
M54
FSX
M56
DX
M55
M57
Bit 0
Bit(n-1)
M58
DR
Bit 0
(n-2)
(n-3)
(n-4)
M59
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6−44. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
144
SPRS257C
June 2004 − Revised June 2006
Electrical Specifications
7
Migration From F281x Devices
Table 6−56 shows the differences between F281x and R281x features. F281x stands for TMS320F2810,
TMS320F2811, and TMS320F2812 devices. R281x stands for TMS320R2811 and TMS320R2812 devices.
Table 6−56. Feature Comparison Between F281x and R281x Devices
FEATURES
R2811
F2811
R2812
F2812
Instruction cycle (at 150 MHz)
6.67 ns
6.67 ns
6.67 ns
6.67 ns
Single−access RAM (SARAM)
(16−bit word)
20K
18K
20K
18K
Disabled
Selectable
Disabled
Selectable
On−chip non−volatile memory
No
Yes
No
Yes
F281x Flash/OTP space are reserved in
R281x devices.
Boot ROM
Yes
Yes
Yes
Yes
Same Boot ROM code as F281x devices.
Flash/OTP Boot ROM
No
Yes
No
Yes
Not available on R281x
SPI−EEPROM boot
Yes
Yes
Yes
Yes
H0 SARAM boot
Yes
Yes
Yes
Yes
SCI, Parallel I/O Boot
Yes
Yes
Yes
Yes
External memory interface
No
No
Yes
Yes
Event Managers A and B
(EVA and EVB)
EVA, EVB
EVA, EVB
EVA, EVB
EVA, EVB
General−Purpose (GP) timers
4
4
4
4
Compare (CMP)/PWM
16
16
16
16
Capture (CAP)/QEP channels
6/2
6/2
6/2
6/2
Watchdog timer
Yes
Yes
Yes
Yes
12−Bit ADC
Yes
Yes
Yes
Yes
Channels
16
16
16
16
32−Bit CPU timers
3
3
3
3
Yes
Yes
Yes
Yes
SCIA, SCIB
SCIA, SCIB
SCIA, SCIB
SCIA, SCIB
CAN
Yes
Yes
Yes
Yes
McBSP
Yes
Yes
Yes
Yes
Digital I/O pins (shared)
56
56
56
56
External interrupts
3
3
3
3
150 MHz
150 MHz
150 MHz
150 MHz
Code security feature
SPI
SCIA, SCIB
Supply voltage − 1.9 V, 3.3 V,
(5%)
June 2004 − Revised June 2006
R281X MIGRATION CONSIDERATIONS
R281x SARAM execution is single cycle,
zero−wait-state at 150 MHz.
Additional 2K words of SARAM −L2/L3
blocks −See section 3.2.7.
Code secuirty in R281x affects L0/L1
SARAM. However, CSM password
locations are preset as 0xFFFF to facilitate
easy unsecuring. See Section 3.2.9.
Internal reference trimmed for gain
accuracy. Supports external reference
mode as in F281x devices. See Section 4.3.
SPRS257C
145
Electrical Specifications
Table 6−56. Feature Comparison Between F281x and R281x Devices (Continued)
FEATURES
R2811
F2811
R2812
F2812
Not required
Required
Not required
Required
Supply voltage − 1.8 V, 3.3 V,
(5%)
135 MHz
135 MHz
135 MHz
135 MHz
Power sequencing
Optional
Required
Optional
Required
Packaging
128−pin
128−pin
179−ball/
176−pin
179−ball/
176−pin
PBK
PBK
GHH, ZHH,
PGF
GHH, ZHH,
PGF
A: −40°C to 85°C
Yes
Yes
Yes
Yes
S/Q: −40°C to 125°C
Yes
Yes
Yes
Yes
Product status
TMX
TMS
TMX
TMS
F281x
version
F281x
version
F281x
version
F281x
version
2.2x or
above
2.2x or
above
2.2x or
above
2.2x or
above
USB version
XDS510PP+
Power Sequencing
R281X MIGRATION CONSIDERATIONS
Power sequencing is optional in R281x
devices. See Section 6.7.
Lead−free options in all packages
Temperature options
Reference guides
See the F281x −CPU and peripheral
reference guides listed in Section 5.2 and in
the TMS320F28x Peripherals Reference
Guide (literature number SPRU566).
Code development
CCS
eZdsp
Emulators
C281x C/C++ Header Files
and Peripheral Examples
(literature number SPRC097)
146
SPRS257C
All versions
All versions
All versions
All versions
Rev.1.0
Rev.1.0
Rev.1.0
Rev.1.0
XDS510/XDS510PP+, XDS510USB or
other compatible emulators
Use DSP281x C/C++−header files rev 1.0
or later. Disable or remove sections that are
not applicable to R281x, such as Flash and
OTP.
June 2004 − Revised June 2006
Mechanical Data
8
Mechanical Data
Table 7−1 through Table 7−4 provide the thermal resistance characteristics for the various packages.
Table 7−1. Thermal Resistance Characteristics for 179-GHH
PARAMETER
179-GHH PACKAGE
UNIT
PsiJT
0.658
°C / W
ΘJA
42.57
°C / W
ΘJC
16.08
°C / W
Table 7−2. Thermal Resistance Characteristics for 179-ZHH
PARAMETER
179-ZHH PACKAGE
UNIT
PsiJT
0.658
°C / W
ΘJA
42.57
°C / W
ΘJC
16.08
°C / W
Table 7−3. Thermal Resistance Characteristics for 176-PGF
PARAMETER
176-PGF PACKAGE
UNIT
PsiJT
0.247
°C / W
ΘJA
41.88
°C / W
ΘJC
9.73
°C / W
Table 7−4. Thermal Resistance Characteristics for 128-PBK
PARAMETER
128-PBK PACKAGE
UNIT
PsiJT
0.271
°C / W
ΘJA
41.65
°C / W
ΘJC
10.76
°C / W
The following mechanical package diagram(s) reflect the most current released mechanical data available for
the designated device(s).
June 2004 − Revised June 2006
SPRS257C
147
PACKAGE OPTION ADDENDUM
www.ti.com
3-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
TMS320R2811PBKA
ACTIVE
LQFP
PBK
128
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
R2811PBKA
TMS320
TMS320R2812PGFA
ACTIVE
LQFP
PGF
176
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
R2812PGFA
TMS320
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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