TMS320VC5410A
Fixed-Point Digital Signal Processor
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SPRS139I
November 2000 – Revised October 2008
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data sheet revision history highlights the technical changes made to the SPRS139H device-specific
data sheet to make it an SPRS139I revision.
Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of
the specified release date with the following corrections.
ADDITIONS/CHANGES/DELETIONS
Table 2-2, Signal Descriptions:
• Updated DESCRIPTION of TRST
• Added footnote about TRST
2
Revision History
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Fixed-Point Digital Signal Processor
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Contents
Revision History ........................................................................................................................... 2
1
TMS320VC5410A Features .................................................................................................... 9
2
Introduction ....................................................................................................................... 10
2.1
2.2
2.3
3
Description ..................................................................................................................
Terminal/Pin Assignments ................................................................................................
2.2.1
Terminal Assignments for the GGU Package ...............................................................
2.2.2
Pin Assignments for the PGE Package ......................................................................
Signal Descriptions .........................................................................................................
10
10
10
12
13
Functional Overview ........................................................................................................... 17
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
Memory ......................................................................................................................
3.1.1
Data Memory .....................................................................................................
3.1.2
Program Memory ................................................................................................
3.1.3
Extended Program Memory ....................................................................................
3.1.4
On-Chip ROM With Bootloader ................................................................................
3.1.5
On-Chip RAM ....................................................................................................
3.1.6
On-Chip Memory Security ......................................................................................
3.1.7
Memory Map .....................................................................................................
3.1.7.1 Relocatable Interrupt Vector Table ...............................................................
On-Chip Peripherals .......................................................................................................
3.2.1
Software-Programmable Wait-State Generator .............................................................
3.2.2
Programmable Bank-Switching ................................................................................
3.2.3
Bus Holders ......................................................................................................
Parallel I/O Ports ...........................................................................................................
3.3.1
Enhanced 8-/16-Bit Host-Port Interface (HPI8/16) .........................................................
3.3.2
HPI Nonmultiplexed Mode......................................................................................
Multichannel Buffered Serial Ports (McBSPs) ..........................................................................
Hardware Timer ............................................................................................................
Clock Generator ............................................................................................................
Enhanced External Parallel Interface (XIO2) ...........................................................................
DMA Controller .............................................................................................................
3.8.1
Features ..........................................................................................................
3.8.2
DMA External Access ...........................................................................................
3.8.3
DMPREC Issue .................................................................................................
3.8.4
DMA Memory Map ..............................................................................................
3.8.5
DMA Priority Level...............................................................................................
3.8.6
DMA Source/Destination Address Modification .............................................................
3.8.7
DMA in Autoinitialization Mode ................................................................................
3.8.8
DMA Transfer Counting.........................................................................................
3.8.9
DMA Transfer in Doubleword Mode ..........................................................................
3.8.10 DMA Channel Index Registers.................................................................................
3.8.11 DMA Interrupts ...................................................................................................
3.8.12 DMA Controller Synchronization Events .....................................................................
General-Purpose I/O Pins .................................................................................................
3.9.1
McBSP Pins as General-Purpose I/O.........................................................................
3.9.2
HPI Data Pins as General-Purpose I/O ......................................................................
Device ID Register .........................................................................................................
Memory-Mapped Registers ...............................................................................................
McBSP Control Registers and Subaddresses ..........................................................................
DMA Subbank Addressed Registers ....................................................................................
Interrupts ....................................................................................................................
Contents
17
17
18
18
18
19
19
20
21
22
23
24
26
26
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27
29
31
32
34
37
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TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
4
Support ............................................................................................................................. 53
4.1
4.2
5
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
Absolute Maximum Ratings ...............................................................................................
Recommended Operating Conditions ...................................................................................
Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted) ........................................................................................
Test Load Circuit ...........................................................................................................
Timing Parameter Symbology ............................................................................................
Internal Oscillator With External Crystal.................................................................................
Clock Options ...............................................................................................................
5.7.1
Divide-By-Two and Divide-By-Four Clock Options ..........................................................
5.7.2
Multiply-By-N Clock Option (PLL Enabled)...................................................................
Memory and Parallel I/O Interface Timing ..............................................................................
5.8.1
Memory Read ....................................................................................................
5.8.2
Memory Write ....................................................................................................
5.8.3
I/O Read ..........................................................................................................
5.8.4
I/O Write .........................................................................................................
Ready Timing for Externally Generated Wait States ..................................................................
HOLD and HOLDA Timings ...............................................................................................
Reset, BIO, Interrupt, and MP/MC Timings .............................................................................
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings ..........................................
External Flag (XF) and TOUT Timings ..................................................................................
Multichannel Buffered Serial Port (McBSP) Timing ....................................................................
5.14.1 McBSP Transmit and Receive Timings.......................................................................
5.14.2 McBSP General-Purpose I/O Timing .........................................................................
5.14.3 McBSP as SPI Master or Slave Timing ......................................................................
Host-Port Interface Timing ................................................................................................
5.15.1 HPI8 Mode .......................................................................................................
5.15.2 HPI16 Mode ......................................................................................................
55
55
56
56
57
58
59
59
61
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62
65
67
69
70
73
74
76
77
78
78
81
82
86
86
90
Mechanical Data ................................................................................................................. 93
6.1
4
Documentation Support ................................................................................................... 53
Device and Development-Support Tool Nomenclature................................................................ 54
Electrical Specifications ...................................................................................................... 55
5.1
5.2
5.3
6
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Package Thermal Resistance Characteristics .......................................................................... 93
Contents
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Fixed-Point Digital Signal Processor
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List of Figures
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
..............................................................................
144-Pin PGE Low-Profile Quad Flatpack (Top View) ........................................................................
TMS320VC5410A Functional Block Diagram .................................................................................
Program and Data Memory Map ................................................................................................
Extended Program Memory Map ...............................................................................................
Processor Mode Status Register (PMST) .....................................................................................
Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] .........................
Software Wait-State Control Register (SWCR) [MMR Address 002Bh] ...................................................
Bank-Switching Control Register (BSCR) [MMR Address 0029h] ..........................................................
Host-Port Interface — Nonmultiplexed Mode .................................................................................
HPI Memory Map .................................................................................................................
Pin Control Register (PCR) ......................................................................................................
Multichannel Control Register 2x (MCR2x) ....................................................................................
Multichannel Control Register 1x (MCR1x) ....................................................................................
Receive Channel Enable Registers Bit Layout for Partitions A to H .......................................................
Transmit Channel Enable Registers Bit Layout for Partitions A to H.......................................................
Nonconsecutive Memory Read and I/O Read Bus Sequence ..............................................................
Consecutive Memory Read Bus Sequence (n = 3 reads) ...................................................................
Memory Write and I/O Write Bus Sequence...................................................................................
DMA Transfer Mode Control Register (DMMCRn) ...........................................................................
DMA Channel Enable Control Register (DMCECTL).........................................................................
On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0) ..........................................
On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0) ......................................
DMPREC Register ................................................................................................................
General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch] ................................................
General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh] .................................................
Device ID Register (CSIDR) [MMR Address 003Eh] .........................................................................
IFR and IMR .......................................................................................................................
Tester Pin Electronics ............................................................................................................
Internal Divide-By-Two Clock Option With External Crystal .................................................................
External Divide-By-Two Clock Timing ..........................................................................................
Multiply-By-One Clock Timing ...................................................................................................
Nonconsecutive Mode Memory Reads .........................................................................................
Consecutive Mode Memory Reads .............................................................................................
Memory Write (MSTRB = 0) .....................................................................................................
Parallel I/O Port Read (IOSTRB = 0) ...........................................................................................
Parallel I/O Port Write (IOSTRB = 0) ...........................................................................................
Memory Read With Externally Generated Wait States.......................................................................
Memory Write With Externally Generated Wait States .......................................................................
144-Ball GGU MicroStar BGA™ (Bottom View)
List of Figures
10
12
17
20
21
21
23
24
24
27
28
29
30
30
31
31
34
35
36
37
39
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42
45
45
46
52
56
58
60
61
63
64
66
68
69
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71
5
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
www.ti.com
5-12
I/O Read With Externally Generated Wait States ............................................................................. 71
5-13
I/O Write With Externally Generated Wait States ............................................................................. 72
5-14
HOLD and HOLDA Timings (HM = 1) .......................................................................................... 73
5-15
Reset and BIO Timings........................................................................................................... 74
5-16
Interrupt Timing .................................................................................................................... 75
5-17
MP/MC Timing ..................................................................................................................... 75
5-18
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings ................................................. 76
5-19
External Flag (XF) Timing ........................................................................................................ 77
5-20
TOUT Timing ...................................................................................................................... 77
5-21
McBSP Receive Timings ......................................................................................................... 79
5-22
McBSP Transmit Timings ........................................................................................................ 80
5-23
McBSP General-Purpose I/O Timings.......................................................................................... 81
5-24
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 ..................................................... 82
5-25
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 ..................................................... 83
5-26
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ..................................................... 84
5-27
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ..................................................... 85
5-28
HPI-8 Mode Timing, Using HDS to Control Accesses (HCS Always Low) ................................................ 88
5-29
HPI-8 Mode Timing, Using HCS to Control Accesses
5-30
5-31
5-32
5-33
5-34
6
.......................................................................
HPI-8 Mode, HINT Timing .......................................................................................................
GPIOx Timings ....................................................................................................................
HPI-16 Mode, Nonmultiplexed Read Timings .................................................................................
HPI-16 Mode, Nonmultiplexed Write Timings .................................................................................
HPI-16 Mode, HRDY Relative to CLKOUT ....................................................................................
List of Figures
89
89
89
91
92
92
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Fixed-Point Digital Signal Processor
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List of Tables
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
...........................................................................................................
Signal Descriptions ...............................................................................................................
Standard On-Chip ROM Layout ................................................................................................
Processor Mode Status Register (PMST) Field Descriptions ...............................................................
Software Wait-State Register (SWWSR) Field Descriptions ................................................................
Software Wait-State Control Register (SWCR) Field Descriptions .........................................................
Bank-Switching Control Register (BSCR) Field Descriptions ...............................................................
Bus Holder Control Bits ..........................................................................................................
Sample Rate Generator Clock Source Selection .............................................................................
Receive Channel Enable Registers for Partitions A to H Field Descriptions ..............................................
Transmit Channel Enable Registers for Partitions A to H Field Descriptions .............................................
Clock Mode Settings at Reset ...................................................................................................
DMD Section of the DMMCRn Register........................................................................................
DMA Channel Enable Control Register (DMCECTL) Field Descriptions ..................................................
DMA Reload Register Selection ................................................................................................
DMA Interrupts ....................................................................................................................
DMA Synchronization Events....................................................................................................
DMA Channel Interrupt Selection ...............................................................................................
CPU Memory-Mapped Registers................................................................................................
Peripheral Memory-Mapped Registers for Each DSP Subsystem .........................................................
McBSP Control Registers and Subaddresses.................................................................................
DMA Subbank Addressed Registers ...........................................................................................
Interrupt Locations and Priorities................................................................................................
Input Clock Frequency Characteristics .........................................................................................
Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options ........................................
Divide-By-2 and Divide-By-4 Clock Options Timing Requirements ........................................................
Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics ....................................................
Multiply-By-N Clock Option Timing Requirements ............................................................................
Multiply-By-N Clock Option Switching Characteristics .......................................................................
Memory Read Timing Requirements ...........................................................................................
Memory Read Switching Characteristics.......................................................................................
Memory Write Switching Characteristics .......................................................................................
I/O Read Timing Requirements .................................................................................................
I/O Read Switching Characteristics .............................................................................................
I/O Write Switching Characteristics .............................................................................................
Ready Timing Requirements for Externally Generated Wait States .......................................................
Ready Switching Characteristics for Externally Generated Wait States ...................................................
HOLD and HOLDA Timing Requirements .....................................................................................
HOLD and HOLDA Switching Characteristics .................................................................................
Terminal Assignments
List of Tables
11
13
19
22
23
24
25
26
30
31
31
33
38
39
42
43
44
44
47
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50
52
58
59
59
59
61
61
62
62
65
67
67
69
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70
73
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7
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
6-1
8
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...................................................................
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics ............................
External Flag (XF) and TOUT Switching Characteristics ....................................................................
McBSP Transmit and Receive Timing Requirements ........................................................................
McBSP Transmit and Receive Switching Characteristics ...................................................................
McBSP General-Purpose I/O Timing Requirements .........................................................................
McBSP General-Purpose I/O Switching Characteristics .....................................................................
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)...................................
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) ..............................
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)...................................
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) ..............................
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)...................................
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) ..............................
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)...................................
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ..............................
HPI8 Mode Timing Requirements...............................................................................................
HPI8 Mode Switching Characteristics ..........................................................................................
HPI16 Mode Timing Requirements .............................................................................................
HPI16 Mode Switching Characteristics.........................................................................................
Thermal Resistance Characteristics ............................................................................................
Reset, BIO, Interrupt, and MP/MC Timing Requirements
List of Tables
74
76
77
78
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81
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82
83
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91
93
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Fixed-Point Digital Signal Processor
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1
•
•
•
•
•
•
•
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SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
TMS320VC5410A Features
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and One
Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU) Including a
40-Bit Barrel Shifter and Two Independent
40-Bit Accumulators
17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
Compare, Select, and Store Unit (CSSU) for the
Add/Compare Selection of the Viterbi Operator
Exponent Encoder to Compute an Exponent
Value of a 40-Bit Accumulator Value in a
Single Cycle
Two Address Generators With Eight Auxiliary
Registers and Two Auxiliary Register
Arithmetic Units (ARAUs)
Data Bus With a Bus Holder Feature
Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space
64K × 16-Bit On-Chip RAM Composed of Eight
Blocks of 8K × 16-Bit On-Chip Dual-Access
Program/Data RAM
16K × 16-Bit On-Chip ROM Configured for
Program Memory
Enhanced External Parallel Interface (XIO2)
Single-Instruction-Repeat and Block-Repeat
Operations for Program Code
Block-Memory-Move Instructions for Better
Program and Data Management
Instructions With a 32-Bit Long Word Operand
Instructions With Two- or Three-Operand
Reads
Arithmetic Instructions With Parallel Store and
•
•
•
•
•
•
•
•
•
•
•
•
•
(1)
(2)
Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
– Software-Programmable Wait-State
Generator and Programmable
Bank-Switching
– On-Chip Programmable Phase-Locked
Loop (PLL) Clock Generator With Internal
Oscillator or External Clock Source (1)
– One 16-Bit Timer
– Six-Channel Direct Memory Access (DMA)
Controller
– Three Multichannel Buffered Serial Ports
(McBSPs)
– 8/16-Bit Enhanced Parallel Host-Port
Interface (HPI8/16)
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic, IEEE
Std 1149.1 (2) (JTAG) Boundary Scan Logic
144-Pin Ball Grid Array (BGA) (GGU Suffix)
144-Pin Low-Profile Quad Flatpack (LQFP)
(PGE Suffix)
6.25-ns Single-Cycle Fixed-Point Instruction
Execution Time (160 MIPS)
8.33-ns Single-Cycle Fixed-Point Instruction
Execution Time (120 MIPS)
3.3-V I/O Supply Voltage (160 and 120 MIPS)
1.6-V Core Supply Voltage (160 MIPS)
1.5-V Core Supply Voltage (120 MIPS)
The on-chip oscillator is not available on all 5410A devices.
For applicable devices, see the TMS320VC5410A Digital
Signal Processor Silicon Errata (literature number SPRZ187).
IEEE Standard 1149.1-1990 Standard-Test-Access Port and
Boundary Scan Architecture.
TMS320C54x, MicroStar BGA, TMS320C54x, C54x, TMS320C5000, C5000, TMS320 are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2008, Texas Instruments Incorporated
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
2
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Introduction
This section lists the pin assignments and describes the function of each pin. This data manual also
provides a detailed description section, electrical specifications, parameter measurement information, and
mechanical data about the available packaging.
NOTE
This data manual is designed to be used in conjunction with the TMS320C54x™ DSP
Functional Overview (literature number SPRU307).
2.1
Description
The TMS320VC5410A fixed-point, digital signal processor (DSP) (hereafter referred to as the 5410A
unless otherwise specified) is based on an advanced modified Harvard architecture that has one program
memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a
high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip
peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction
set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing
a high degree of parallelism. Two read operations and one write operation can be performed in a single
cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture.
In addition, data can be transferred between data and program spaces. Such parallelism supports a
powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single
machine cycle. The 5410A also includes the control mechanisms to manage interrupts, repeated
operations, and function calls.
2.2
Terminal/Pin Assignments
Figure 2-1 illustrates the ball locations for the 144-pin ball grid array (BGA) package and is used in
conjunction with Table 2-1 to locate signal names and ball grid numbers. Figure 2-2 provides the pin
assignments for the 144-pin low-profile quad flatpack (LQFP) package.
2.2.1
Terminal Assignments for the GGU Package
13 12 11 10 9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
Figure 2-1. 144-Ball GGU MicroStar BGA™ (Bottom View)
10
Introduction
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Fixed-Point Digital Signal Processor
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Table 2-1 lists each signal name and BGA ball number for the 144-pin TMS320VC5410AGGU package.
Table 2-2 lists each terminal name, terminal function, and operating modes for the TMS320VC5410A.
DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. DVSS is the
ground for the I/O pins while CVSS is the ground for the core CPU. The DVSS and CVSS pins can be
connected to a common ground plane in a system.
Table 2-1. Terminal Assignments
SIGNAL
QUADRANT 1
BGA
BALL #
SIGNAL
QUADRANT 2
CVSS
A1
BFSX1
A22
B1
BDX1
CVSS
C2
DVDD
DVDD
C1
BGA
BALL #
SIGNAL
QUADRANT 3
BGA
BALL #
SIGNAL
QUADRANT 4
BGA
BALL #
N13
CVSS
N1
A19
A13
M13
BCLKR1
N2
A20
A12
L12
HCNTL0
M3
CVSS
B11
DVSS
L13
DVSS
N3
DVDD
A11
A10
D4
CLKMD1
K10
BCLKR0
K4
D6
D10
HD7
D3
CLKMD2
K11
BCLKR2
L4
D7
C10
A11
D2
CLKMD3
K12
BFSR0
M4
D8
B10
A12
D1
HPI16
K13
BFSR2
N4
D9
A10
A13
E4
HD2
J10
BDR0
K5
D10
D9
A14
E3
TOUT
J11
HCNTL1
L5
D11
C9
B9
A15
E2
EMU0
J12
BDR2
M5
D12
CVDD
E1
EMU1/OFF
J13
BCLKX0
N5
HD4
A9
HAS
F4
TDO
H10
BCLKX2
K6
D13
D8
DVSS
F3
TDI
H11
CVSS
L6
D14
C8
CVSS
F2
TRST
H12
HINT
M6
D15
B8
CVDD
F1
TCK
H13
CVDD
N6
HD5
A8
HCS
G2
TMS
G12
BFSX0
M7
CVDD
B7
HR/W
G1
CVSS
G13
BFSX2
N7
CVSS
A7
READY
G3
CVDD
G11
HRDY
L7
HDS1
C7
PS
G4
HPIENA
G10
DVDD
K7
DVSS
D7
DS
H1
DVSS
F13
DVSS
N8
HDS2
A6
IS
H2
CLKOUT
F12
HD0
M8
DVDD
B6
R/W
H3
HD3
F11
BDX0
L8
A0
C6
MSTRB
H4
X1
F10
BDX2
K8
A1
D6
IOSTRB
J1
X2/CLKIN
E13
IACK
N9
A2
A5
MSC
J2
RS
E12
HBIL
M9
A3
B5
XF
J3
D0
E11
NMI
L9
HD6
C5
HOLDA
J4
D1
E10
INT0
K9
A4
D5
IAQ
K1
D2
D13
INT1
N10
A5
A4
HOLD
K2
D3
D12
INT2
M10
A6
B4
BIO
K3
D4
D11
INT3
L10
A7
C4
MP/MC
L1
D5
C13
CVDD
N11
A8
A3
DVDD
L2
A16
C12
HD1
M11
A9
B3
CVSS
L3
DVSS
C11
CVSS
L11
CVDD
C3
BDR1
M1
A17
B13
BCLKX1
N12
A21
A2
BFSR1
M2
A18
B12
DVSS
M12
DVSS
B2
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11
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
2.2.2
www.ti.com
Pin Assignments for the PGE Package
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
DVSS
A21
CV DD
A9
A8
A7
A6
A5
A4
HD6
A3
A2
A1
A0
DV DD
HDS2
DV SS
HDS1
CVSS
CVDD
HD5
D15
D14
D13
HD4
D12
D11
D10
D9
D8
D7
D6
DV DD
CV SS
A20
A19
The TMS320VC5410APGE 144-pin low-profile quad flatpack (LQFP) pin assignments are shown in
Figure 2-2.
108
107
106
4
5
6
7
105
104
103
102
8
9
10
11
101
100
99
98
12
13
14
15
97
96
95
94
16
17
18
19
20
93
92
91
90
89
21
22
23
24
88
87
86
85
25
26
27
28
84
83
82
81
29
30
31
32
80
79
78
77
33
34
35
36
76
75
74
73
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
A18
A17
DVSS
A16
D5
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
HD3
CLKOUT
DVSS
HPIENA
CVDD
CVSS
TMS
TCK
TRST
TDI
TDO
EMU1/OFF
EMU0
TOUT
HD2
HPI16
CLKMD3
CLKMD2
CLKMD1
DVSS
DVDD
BDX1
BFSX1
CV SS
BCLKR1
HCNTL0
DVSS
BCLKR0
BCLKR2
BFSR0
BFSR2
BDR0
HCNTL1
BDR2
BCLKX0
BCLKX2
CVSS
HINT
CVDD
BFSX0
BFSX2
HRDY
DVDD
DVSS
HD0
BDX0
BDX2
IACK
HBIL
NMI
INT0
INT1
INT2
INT3
CV DD
HD1
CVSS
BCLKX1
DVSS
CVSS
A22
CVSS
DVDD
A10
HD7
A11
A12
A13
A14
A15
CVDD
HAS
DVSS
CVSS
CVDD
HCS
HR/W
READY
PS
DS
IS
R/W
MSTRB
IOSTRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
DVDD
CVSS
BDR1
BFSR1
A.
DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. DVSS is the ground for
the I/O pins while CVSS is the ground for the core CPU. The DVSS and CVSS pins can be connected to a common
ground plane in a system.
Figure 2-2. 144-Pin PGE Low-Profile Quad Flatpack (Top View)
12
Introduction
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2.3
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
Signal Descriptions
Table 2-2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for exact
pin locations based on package type.
Table 2-2. Signal Descriptions
TERMINAL
NAME
I/O (1)
DESCRIPTION
A22 (MSB)
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 (LSB)
I/O/Z (2) (3)
Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The sixteen
LSB lines, A0 to A15, are multiplexed to address external memory (program, data) or I/O. The seven MSB
lines, A16 to A22, address external program space memory. A22-A0 is placed in the high-impedance state
in the hold mode. A22-A0 also goes into the high-impedance state when OFF is low.
A16-A0 are inputs in HPI16 mode. These pins can be used to address internal memory via the host-port
interface (HPI) when the HPI16 pin is high. These pins also have Schmitt trigger inputs.
The address bus has a bus holder feature that eliminates passive components and the power dissipation
associated with them. The bus holder keeps the address bus at the previous logic level when the bus goes
into a high-impedance state.
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
I/O/Z (2) (3)
Parallel data bus D15 (MSB) through D0 (LSB). D15-D0 is multiplexed to transfer data between the core
CPU and external data/program memory or I/O devices or HPI in HPI16 mode (when HPI16 pin is high).
D15-D0 is placed in the high-impedance state when not outputting data or when RS or HOLD is asserted.
D15-D0 also goes into the high-impedance state when OFF is low. These pins also have Schmitt trigger
inputs.
The data bus has a bus holder feature that eliminates passive components and the power dissipation
associated with them. The bus holder keeps the data bus at the previous logic level when the bus goes
into the high-impedance state. The bus holders on the data bus can be enabled/disabled under software
control.
DATA SIGNALS
INITIALIZATION, INTERRUPT AND RESET OPERATIONS
IACK
O/Z
Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is
fetching the interrupt vector location designated by A15-A0. IACK also goes into the high-impedance state
when OFF is low.
INT0 (2)
INT1 (2)
INT2 (2)
INT3 (2)
I
External user interrupt inputs. INT0-INT3 are maskable and are prioritized by the interrupt mask register
(IMR) and the interrupt mode bit. INT0 -INT3 can be polled and reset by way of the interrupt flag register
(IFR).
NMI (2)
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR.
When NMI is activated, the processor traps to the appropriate vector location.
RS (2)
I
Reset. RS causes the digital signal processor (DSP) to terminate execution and forces the program
counter to 0FF80h. When RS is brought to a high level, execution begins at location 0FF80h of program
memory. RS affects various registers and status bits.
(1)
(2)
(3)
I = Input, O = Output, Z = High-impedance, S = Supply
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register.
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Fixed-Point Digital Signal Processor
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Table 2-2. Signal Descriptions (continued)
TERMINAL
NAME
MP/MC
I/O (1)
DESCRIPTION
I
Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and
the internal program ROM is mapped into the upper 16K words of program memory space. If the pin is
driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed from program
space. This pin is only sampled at reset, and the MP/MC bit of the processor mode status (PMST) register
can override the mode that is selected at reset.
I
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes
the conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the
XC instruction, and all other instructions sample BIO during the read phase of the pipeline.
MULTIPROCESSING SIGNALS
BIO (2)
O/Z
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set
low by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF
is low, and is set high at reset.
DS
PS
IS
O/Z
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for
communicating to a particular external space. Active period corresponds to valid address information. DS,
PS, and IS are placed into the high-impedance state in the hold mode; these signals also go into the
high-impedance state when OFF is low.
MSTRB
O/Z
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access
to data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes
into the high-impedance state when OFF is low.
READY
I
Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If
the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that
the processor performs ready detection if at least two software wait states are programmed. The READY
signal is not sampled until the completion of the software wait states.
XF
MEMORY CONTROL SIGNALS
R/W
O/Z
Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is
normally in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W
is placed in the high-impedance state in the hold mode; and it also goes into the high-impedance state
when OFF is low.
IOSTRB
O/Z
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an
I/O device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the
high-impedance state when OFF is low.
HOLD
I
Hold input. HOLD is asserted to request control of the address, data, and control lines. When
acknowledged by the 5410A, these lines go into the high-impedance state.
O/Z
Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that
the address, data, and control lines are in the high-impedance state, allowing them to be available to the
external circuitry. HOLDA also goes into the high-impedance state when OFF is low. This pin is driven high
during reset.
MSC
O/Z
Microstate complete. MSC indicates completion of all software wait states. When two or more software wait
states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes
inactive high at the beginning of the last software wait state. If connected to the READY input, MSC forces
one external wait state after the last internal wait state is completed. MSC also goes into the
high-impedance state when OFF is low.
IAQ
O/Z
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the
address bus and goes into the high-impedance state when OFF is low.
HOLDA
TIMER SIGNALS
O/Z
Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as
configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the
machine-cycle rate divided by 4.
CLKMD1 (2)
CLKMD2 (2)
CLKMD3 (2)
I
Clock mode select signals. CLKMD1-CLKMD3 allow the selection and configuration of different clock
modes such as crystal, external clock, and PLL mode. The external CLKMD1-CLKMD3 pins are sampled
to determine the desired clock generation mode while RS is low. Following reset, the clock generation
mode can be reconfigured by writing to the internal clock mode register in software.
X2/CLKIN (2)
I
Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input.
(This is revision depended, see Section 3.6 for additional information.)
X1
O
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when OFF is low. (This is revision depended,
see Section 3.6 for additional information.)
CLKOUT
14
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Table 2-2. Signal Descriptions (continued)
TERMINAL
NAME
TOUT
I/O (1)
O/Z
DESCRIPTION
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one
CLKOUT cycle wide. TOUT also goes into the high-impedance state when OFF is low.
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1),
AND MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS
BCLKR0 (2)
BCLKR1 (2)
BCLKR2 (2)
I/O/Z
Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input
following reset. BCLKR serves as the serial shift clock for the buffered serial port receiver.
BDR0
BDR1
BDR2
I
BFSR0
BFSR1
BFSR2
I/O/Z
Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is
configured as an input following reset. The BFSR pulse initiates the receive data process over BDR.
BCLKX0 (2)
BCLKX1 (2)
BCLKX2 (2)
I/O/Z
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be
configured as an input or an output, and is configured as an input following reset. BCLKX enters the
high-impedance state when OFF goes low.
BDX0
BDX1
BDX2
O/Z
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
asserted, or when OFF is low.
Serial data receive input
HOST-PORT INTERFACE SIGNALS
BFSX0
BFSX1
BFSX2
HD0-HD7 (2) (3)
I/O/Z
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process
over BDX. BFSX can be configured as an input or an output, and is configured as an input following reset.
BFSX goes into the high-impedance state when OFF is low.
I/O/Z
Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with
the HPI registers. These pins can also be used as general-purpose I/O pins. HD0-HD7 is placed in the
high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus
holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is
not being driven by the 5410A, the bus holders keep the pins at the previous logic level. The HPI data bus
holders are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR. These pins also
have Schmitt trigger inputs.
HCNTL0 (4)
HCNTL1 (4)
I
Control inputs. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control
inputs have internal pullups that are only enabled when HPIENA = 0. These pins are not used when
HPI16 = 1.
HBIL (4)
I
Byte identification. HBIL identifies the first or second byte of transfer. The HPIL input has an internal pullup
resistor that is only enabled when HPIENA = 0. This pin is not used when HPI16 = 1.
HCS (2) (4)
I
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip select
input has an internal pullup resistor that is only enabled when HPIENA = 0.
I
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control the transfer. The
strobe inputs have internal pullup resistors that are only enabled when HPIENA = 0.
HAS (2) (4)
I
Address strobe. Host with multiplexed address and data pins requires HAS to latch the address in the
HPIA register. HAS input has an internal pullup resistor that is only enabled when HPIENA = 0.
HR/W (4)
I
Read/write. HR/W controls the direction of the HPI transfer. HR/W has an internal pullup resistor that is
only enabled when HPIENA = 0.
HDS1
HDS2
(2) (4)
(2) (4)
HRDY
O/Z
Ready output. HRDY goes into the high-impedance state when OFF is low. The ready output informs the
host when the HPI is ready for the next transfer.
HINT
O/Z
Interrupt output. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high.
HINT goes into the high-impedance state when OFF is low. This pin is not used when HPI16 = 1.
HPIENA (5)
I
HPI module select. HPIENA must be tied to DVDD to have HPI selected. If HPIENA is left open or
connected to ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled,
and the HPI data bus has holders set. HPIENA is provided with an internal pulldown resistor that is always
active. HPIENA is sampled when RS goes high and is ignored until RS goes low again.
HPI16 (5)
I
HPI16 mode selection. This pin must be tied to DVDD to enable HPI16 mode. The pin has an internal
pulldown resistor which is always active. If HPI16 is left open or driven low, the HPI16 mode is disabled.
CVSS
S
Ground. Dedicated ground for the core CPU
SUPPLY PINS
(4)
(5)
This pin has an internal pullup resistor.
This pin has an internal pulldown resistor.
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Fixed-Point Digital Signal Processor
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
www.ti.com
Table 2-2. Signal Descriptions (continued)
TERMINAL
NAME
I/O (1)
DESCRIPTION
CVDD
S
+VDD. Dedicated power supply for the core CPU
DVSS
S
Ground. Dedicated ground for I/O pins
DVDD
S
+VDD. Dedicated power supply for I/O pins
TEST PINS
TCK (2) (4)
I
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The
changes on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller,
instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output
signal (TDO) occur on the falling edge of TCK.
TDI (4)
I
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK.
TDO
O/Z
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are
shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the
scanning of data is in progress. TDO also goes into the high-impedance state when OFF is low.
TMS (4)
TRST
(5) (6)
EMU0 (7)
EMU1/OFF (7)
(6)
(7)
16
I
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked
into the TAP controller on the rising edge of TCK.
I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of
the operations of the device. If TRST is driven low, the device operates in its functional mode, and the
IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
I/O/Z
Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When
TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as
input/output by way of the IEEE standard 1149.1 scan system.
I/O/Z
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from
the emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When
TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all
output drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation
purposes (not for multiprocessing applications). Therefore, for the OFF condition, the following apply:
• TRST= low,
• EMU0 = high
• EMU1/OFF= low
Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple
DSPs, a buffer is recommended to ensure the VIL and VIH specifications are met.
This pin must be pulled up with a 4.7-kΩ resistor to ensure the device is operable in functional mode or emulation mode.
Introduction
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SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
Functional Overview
The following functional overview is based on the block diagram in Figure 3-1.
64K RAM
Dual Access
Program/Data
54X cLEAD
Pbus
Ebus
Cbus
Dbus
Pbus
Ebus
Cbus
Pbus
Dbus
P, C, D, E Buses and Control Signals
16K Program
ROM
MBus
GPIO
TI BUS
RHEA Bus
McBSP1
Enhanced XIO
HPI
HPI
xDMA
logic
McBSP2
MBus
RHEA bus
XIO
RHEA
Bridge
McBSP3
RHEAbus
TIMER
APLL
Clocks
JTAG
Figure 3-1. TMS320VC5410A Functional Block Diagram
3.1
Memory
The 5410A device provides both on-chip ROM and RAM memories to aid in system performance and
integration.
3.1.1
Data Memory
The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the
on-chip RAM when addressing within its bounds. When an address is generated outside the RAM bounds,
the device automatically generates an external access.
The advantages of operating from on-chip memory are as follows:
• Higher performance because no wait states are required
• Higher performance because of better flow within the pipeline of the central arithmetic logic unit
(CALU)
• Lower cost than external memory
• Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
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Fixed-Point Digital Signal Processor
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3.1.2
www.ti.com
Program Memory
Software can configure their memory cells to reside inside or outside of the program address map. When
the cells are mapped into program space, the device automatically accesses them when their addresses
are within bounds. When the program-address generation (PAGEN) logic generates an address outside its
bounds, the device automatically generates an external access. The advantages of operating from on-chip
memory are as follows:
• Higher performance because no wait states are required
• Lower cost than external memory
• Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
3.1.3
Extended Program Memory
The 5410A uses a paged extended memory scheme in program space to allow access of up to 8192K of
program memory. In order to implement this scheme, the 5410A includes several features which are also
present on C548/549/5410:
• Twenty-three address lines, instead of sixteen
• An extra memory-mapped register, the XPC
• Six extra instructions for addressing extended program space
Program memory in the 5410A is organized into 128 pages that are each 64K in length.
The value of the XPC register defines the page selection. This register is memory-mapped into data space
to address 001Eh. At a hardware reset, the XPC is initialized to 0.
3.1.4
On-Chip ROM With Bootloader
The 5410A features a 16K-word × 16-bit on-chip maskable ROM that can only be mapped into program
memory space.
Customers can arrange to have the ROM of the 5410A programmed with contents unique to any particular
application.
A bootloader is available in the standard 5410A on-chip ROM. This bootloader can be used to
automatically transfer user code from an external source to anywhere in the program memory at power
up. If MP/MC of the device is sampled low during a hardware reset, execution begins at location FF80h of
the on-chip ROM. This location contains a branch instruction to the start of the bootloader program.
The standard 5410A devices provide different ways to download the code to accommodate various
system requirements:
• Parallel from 8-bit or 16-bit-wide EPROM
• Parallel from I/O space, 8-bit or 16-bit mode
• Serial boot from serial ports, 8-bit or 16-bit mode
• Host-port interface boot
• Serial EEPROM mode
• Warm boot
18
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The standard on-chip ROM layout is shown in Table 3-1.
Table 3-1. Standard On-Chip ROM Layout
ADDRESS RANGE
DESCRIPTION
C000h-D4FFh
ROM tables for the GSM EFR speech codec
D500h-F7FFh
Reserved
F800h-FBFFh
Bootloader
FC00h-FCFFh
µ-Law expansion table
FD00h-FDFFh
A-Law expansion table
FE00h-FEFFh
Sine look-up table
FF00h-FF7Fh
Reserved (1)
FF80h-FFFFh
Interrupt vector table
(1)
In the 5410A ROM, 128 words are reserved for factory device-testing purposes. Application code to be implemented in on-chip ROM
must reserve these 128 words at addresses FF00h-FF7Fh in program space.
3.1.5
On-Chip RAM
The 5410A device contains 64K-word × 16-bit of on-chip dual-access RAM (DARAM).
The DARAM is composed of eight blocks of 8K words each. Each block in the DARAM can support two
reads in one cycle, or a read and a write in one cycle. Four blocks of DARAM are located in the address
range 0080h-7FFFh in data space, and can be mapped into program/data space by setting the OVLY bit
to one. The other four blocks of DARAM are located in the address range 18000h-1FFFFh in program
space. The DARAM located in the address range 18000h-1FFFFh in program space can be mapped into
data space by setting the DROM bit to one.
3.1.6
On-Chip Memory Security
The TMS320VC5410A device has a maskable option to protect the contents of on-chip memories.
When the RAM/ROM security option is selected, the following restrictions apply:
• Only the on-chip ROM-originating instructions can read the contents of the on-chip ROM. On-chip RAM
and external RAM-originating instructions cannot read data from ROM; instead, 0FFFFh is read. Code
can still branch to ROM from on-chip RAM or external program memory.
• The contents of on-chip RAM can be read by all instructions, even by instructions fetched from external
memory. To protect the internal RAM, the user must never branch to external memory.
• The security feature completely disables the scan-based emulation capability of the 54x to prevent the
use of a debugger utility. This only affects emulation and does not prevent the use of the JTAG
boundary scan test capability.
• The device is internally forced into microcomputer mode at reset (MP/MC bit forced to zero),
preventing the ROM from being disabled by the external MP/MC pin. The status of the MP/MC bit in
the PMST register can be changed after reset by the user application.
• HPI writes have no restriction, but HPI reads are restricted to the 4000h - 5FFFh address range.
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If the ROM-only security option is selected the following restrictions apply:
• Only the on-chip ROM-originating instructions can read the contents of the on-chip ROM. On-chip RAM
and external RAM-originating instruction cannot read data from ROM; instead, 0FFFFh is read. Code
can still branch to ROM from on-chip RAM or external program memory.
• The contents of on-chip RAM can be read by all instructions, even by instructions fetched from external
memory. To protect the internal RAM the user must never branch to external memory.
• The security feature completely disables the scan-based emulation capability of the 54x to prevent the
use of a debugger utility. This only affects emulation and does not prevent the use of the JTAG
boundary scan test capability.
• The device can be started in either microcomputer mode or microprocessor mode at reset (depends on
the MP/MC pin).
• HPI reads and writes have no restriction.
3.1.7
Memory Map
Hex Page 0 Program
0000
Reserved
(OVLY = 1)
External
(OVLY = 0)
007F
On-Chip
0080
DARAM0−3
(OVLY = 1)
External
7FFF
(OVLY = 0)
8000
External
FF7F
FF80
Interrupts
(External)
FFFF
MP/MC= 1
(Microprocessor Mode)
A.
Hex Page 0 Program
0000
Reserved
(OVLY = 1)
External
(OVLY = 0)
007F
0080
7FFF
8000
BFFF
C000
FEFF
FF00
FF7F
FF80
FFFF
On-Chip
DARAM0−3
(OVLY = 1)
External
(OVLY = 0)
External
Hex
0000
005F
0060
007F
0080
7FFF
8000
On-Chip ROM
(4K x 16-bit)
Reserved
Interrupts
(On-Chip)
MP/MC= 0
(Microcomputer Mode)
Data
Memory-Mapped
Registers
Scratch-Pad
RAM
On-Chip
DARAM0−3
(32K x 16-bit)
On-Chip
DARAM4−7
(DROM=1)
or
External
(DROM=0)
FFFF
Address ranges for on-chip DARAM in data memory are: DARAM0: 0080h-1FFFh; DARAM1: 2000h-3FFFh
DARAM2:
4000h-5FFFh;
DARAM3:
6000h-7FFFh
DARAM4:
8000h-9FFFh;
DARAM5:
A000h-BFFFh
DARAM6: C000h-DFFFh; DARAM7: E000h-FFFFh
Figure 3-2. Program and Data Memory Map
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Hex
010000
017FFF
018000
Program
On-Chip
DARAM0-3
(OVLY=1)
External
(OVLY=0)
On-Chip
DARAM4-7
(MP/MC=0)
External
(MP/MC=1)
01FFFF
Program
On-Chip
DARAM0-3
(OVLY=1)
External
7F7FFF (OVLY=0)
......
028000
7F8000
External
External
7FFFFF
02FFFF
Page 1
XPC=1
A.
Hex
7F0000
Hex Program
020000
On-Chip
DARAM0-3
(OVLY=1)
External
027FFF (OVLY=0)
Page 2
XPC=2
Page 127
XPC=7Fh
Address ranges for on-chip DARAM in program memory are: DARAM4: 018000h-019FFFh; DARAM5: 01A000h-01
BFFFh DARAM6: 01C000h-01DFFFh; DARAM7: 01E000h-01FFFFh
Figure 3-3. Extended Program Memory Map
3.1.7.1
Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning
that the processor, when taking the trap, loads the program counter (PC) with the trap address and
executes the code at the vector location. Four words, either two 1-word instructions or one 2-word
instruction, are reserved at each vector location to accommodate a delayed branch instruction which
allows branching to the appropriate interrupt service routine without the overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.
However, these vectors can be remapped to the beginning of any 128-word page in program space after
device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the
appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is
mapped to the new 128-word page.
NOTE
The hardware reset (RS) vector cannot be remapped because the hardware reset loads
the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in
program space.
15
8
IPTR
R/W-1FF
7
6
5
4
3
2
1
0
IPTR
MP/MC
OVLY
AVIS
DROM
CLKOFF
SMUL
SST
R/W-MP/MC
pin
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-4. Processor Mode Status Register (PMST)
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Table 3-2. Processor Mode Status Register (PMST) Field Descriptions
BIT
15-7
6
FIELD
VALUE
DESCRIPTION
1FFh
Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt
vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset,
these bits are all set to 1; the reset vector always resides at address FF80h in program memory space.
The RESET instruction does not affect this field.
IPTR
MP/MC
MP/MC Microprocessor/microcomputer mode. MP/MC enables/disables the on-chip ROM to be addressable in
pin
program memory space.
0
The on-chip ROM is enabled and addressable.
1
The on-chip ROM is not available.
MP/MC is set to the value corresponding to the logic level on the MP/MC pin when sampled at reset.
This pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This
bit can also be set or cleared by software.
5
4
3
3.2
RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space.
The values for the OVLY bit are:
OVLY
0
The on-chip RAM is addressable in data space but not in program space.
1
The on-chip RAM is mapped into program space and data space. Data page 0 (addresses 0h to 7Fh),
however, is not mapped into program space.
Address visibility mode. AVIS enables/disables the internal program address to be visible at the
address pins.
AVIS
0
The external address lines do not change with the internal program address. Control and data lines are
not affected and the address bus is driven with the last address on the bus.
1
This mode allows the internal program address to appear at the pins of the 5410A so that the internal
program address can be traced. Also, it allows the interrupt vector to be decoded in conjunction with
IACK when the interrupt vectors reside on on-chip memory.
Data ROM. DROM enables on-chip ROM to be mapped into data space. The values for the DROM bit
are:
DROM
0
The on-chip ROM is not mapped into data space.
1
A portion of the on-chip RAM is mapped into data space.
2
CLKOFF
0
CLOCKOUT off. When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains at a high
level.
1
SMUL
0
Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before
performing the accumulation in a MAC of MAS instruction. The SMUL bit applies only when OVM = 1
and FRCT = 1.
0
SST
0
Saturation on store. When SST = 1, saturation of the data from the accumulator is enabled before
storing in memory. The saturation is performed after the shift operation.
On-Chip Peripherals
The 5410A device has the following peripherals:
• Software-programmable wait-state generator
• Programmable bank-switching
• A host-port interface (HPI8/16)
• Three multichannel buffered serial ports (McBSPs)
• A hardware timer
• A clock generator with a multiple phase-locked loop (PLL)
• Enhanced external parallel interface (XIO2)
• A DMA controller (DMA)
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3.2.1
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Software-Programmable Wait-State Generator
The software wait-state generator of the 5410A can extend external bus cycles by up to fourteen machine
cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY
line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state
generator are automatically disabled. Disabling the wait-state generator clocks reduces the power
consumption of the 5410A.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs
of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to
five separate address ranges. This allows a different number of wait states for each of the five address
ranges. Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control
register (SWCR) defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the
wait-state generator is initialized to provide seven wait states on all external memory accesses. The
SWWSR bit fields are shown in Figure 3-5 and described in Table 3-3.
15
14
12
11
9
XPA
I/O
DATA
R/W-0
R/W-111
R/W-111
7
6
5
3
8
DATA
2
0
DATA
PROGRAM
PROGRAM
R/W-111
R/W-111
R/W-111
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address
0028h]
Table 3-3. Software Wait-State Register (SWWSR) Field Descriptions
BIT
15
FIELD
XPA
VALUE
DESCRIPTION
0
Extended program address control bit. XPA is used in conjunction with the program space fields (bits 0
through 5) to select the address range for program space wait states.
14-12
I/O
111
I/O space. The field value (0-7) corresponds to the base number of wait states for I/O space accesses
within addresses 0000-FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for
the base number of wait states.
11-9
Data
111
Upper data space. The field value (0-7) corresponds to the base number of wait states for external
data space accesses within addresses 8000-FFFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
8-6
Data
111
Lower data space. The field value (0-7) corresponds to the base number of wait states for external
data space accesses within addresses 0000-7FFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
111
Upper program space. The field value (0-7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
• XPA = 0: xx8000 - xxFFFFh
• XPA = 1: 400000h - 7FFFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
111
Program space. The field value (0-7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
• XPA = 0: xx0000 - xx7FFFh
• XPA = 1: 000000 - 3FFFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
5-3
2-0
Program
Program
The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend
the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 3-6
and described in Table 3-4.
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15
8
Reserved
R/W-0
7
1
0
Reserved
SWSM
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-6. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]
Table 3-4. Software Wait-State Control Register (SWCR) Field Descriptions
BIT
FIELD
15-1
VALUE
Reserved
0
FUNCTION
These bits are reserved and are unaffected by writes.
Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a
factor of 1 or 2.
0
SWSM
3.2.2
0
Wait-state base values are unchanged (multiplied by 1).
1
Wait-state base values are multiplied by 2 for a maximum of 14 wait states.
Programmable Bank-Switching
Programmable bank-switching logic allows the 5410A to switch between external memory banks without
requiring external wait states for memories that need additional time to turn off. The bank-switching logic
automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program
or data space.
Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped at
address 0029h. The bit fields of the BSCR are shown in Figure 3-7 and are described in Table 3-5.
15
14
13
12
11
8
CONSEC
DIVFCT
IACKOFF
Reserved
R/W-1
R/W-11
R/W-1
R
7
2
1
0
Reserved
3
HBH
BH
Reserved
R
R/W-0
R/W-0
R
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-7. Bank-Switching Control Register (BSCR) [MMR Address 0029h]
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Table 3-5. Bank-Switching Control Register (BSCR) Field Descriptions
BIT
FIELD
VALUE
DESCRIPTION
Consecutive bank-switching. Specifies the bank-switching mode.
15
CONSEC (1)
0
Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for
continuous memory reads (i.e., no starting and trailing cycles between read cycles).
1
Consecutive bank switches on external memory reads. Each read cycle consists of 3 cycles:
starting cycle, read cycle, and trailing cycle.
CLKOUT output divide factor. The CLKOUT output is driven by an on-chip source having a
frequency equal to 1/(DIVFCT+1) of the DSP clock.
14-13
DIVFCT
00
CLKOUT is not divided.
01
CLKOUT is divided by 2 from the DSP clock.
10
CLKOUT is divided by 3 from the DSP clock.
11
CLKOUT is divided by 4 from the DSP clock (default value following reset.
IACK signal output off. Controls the output of the IACK signal. IACKOFF is set to 1 at reset.
12
11-3
IACKOFF
0
The IACK signal output off function is disabled.
1
The IACK signal output off function is enabled.
Reserved
Reserved
HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset.
2
HBH
0
The bus holder is disabled except when HPI16=1.
1
The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous
logic level.
Bus holder. Controls the bus holder. BH is cleared to 0 at reset.
1
0
(1)
BH
Reserved
0
The bus holder is disabled.
1
The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous logic
level.
Reserved
For additional information, see Section 3.7 of this document.
The 5410A has an internal register that holds the MSB of the last address used for a read or write
operation in program or data space. In the non-consecutive bank switches (CONSEC = 0), if the MSB of
the address used for the current read does not match that contained in this internal register, the MSTRB
(memory strobe) signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus
switches to the new address. The contents of the internal register are replaced with the MSB for the read
of the current address. If the MSB of the address used for the current read matches the bits in the
register, a normal read cycle occurs.
In non-consecutive bank switches (CONSEC = 0), if repeated reads are performed from the same memory
bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory
conflicts are avoided by inserting an extra cycle. For more information, see Section 3.7 of this document.
The bank-switching mechanism automatically inserts one extra cycle in the following cases:
• A memory read followed by another memory read from a different memory bank.
• A program-memory read followed by a data-memory read.
• A data-memory read followed by a program-memory read.
• A program-memory read followed by another program-memory read from a different page.
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3.2.3
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Bus Holders
The 5410A has two bus holder control bits, BH (BSCR[1]) and HBH (BSCR[2]), to control the bus keepers
of the address bus (A[16-0]), data bus (D[15-0]), and the HPI data bus (HD[7-0]). Bus keeper
enabling/disabling is described in Table 3-6.
Table 3-6. Bus Holder Control Bits
HPI16 PIN
BH
HBH
D[15-0]
A[16-0]
HD[7-0]
0
0
0
OFF
OFF
OFF
0
0
1
OFF
OFF
ON
0
1
0
ON
OFF
OFF
0
1
1
ON
OFF
ON
1
0
0
OFF
OFF
ON
1
0
1
OFF
ON
ON
1
1
0
ON
OFF
ON
1
1
1
ON
ON
ON
3.3
Parallel I/O Ports
The 5410A has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the
PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The 5410A can
interface easily with external devices through the I/O ports while requiring minimal off-chip
address-decoding circuits.
3.3.1
Enhanced 8-/16-Bit Host-Port Interface (HPI8/16)
The 5410A host-port interface, also referred to as the HPI8/16, is an enhanced version of the standard
8-bit HPI found on earlier TMS320C54x™ DSPs (542, 545, 548, and 549). The 5410A HPI can be used to
interface to an 8-bit or 16-bit host. When the address and data buses for external I/O is not used (to
interface to external devices in program/data/IO spaces), the 5410A HPI can be configured as an HPI16 to
interface to a 16-bit host. This configuration can be accomplished by connecting the HPI16 pin to logic "1".
When the HPI16 pin is connected to a logic "0", the 5410A HPI is configured as an HPI8. The HPI8 is an
8-bit parallel port for interprocessor communication. The features of the HPI8 include:
Standard features:
• Sequential transfers (with autoincrement) or random-access transfers
• Host interrupt and C54x™ interrupt capability
• Multiple data strobes and control pins for interface flexibility
The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit
transfers are accomplished in two parts with the HBIL input designating high or low byte. The host
communicates with the HPI8 through three dedicated registers — the HPI address register (HPIA), the
HPI data register (HPID), and the HPI control register (HPIC). The HPIA and HPID registers are only
accessible by the host, and the HPIC register is accessible by both the host and the 5410A.
Enhanced features:
• Access to entire on-chip RAM through DMA bus
• Capability to continue transferring during emulation stop
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The HPI16 is an enhanced 16-bit version of the TMS320C54x™ DSP 8-bit host-port interface (HPI8). The
HPI16 is designed to allow a 16-bit host to access the DSP on-chip memory, with the host acting as the
master of the interface. Some of the features of the HPI16 include:
• 16-bit bidirectional data bus
• Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts
• Only nonmultiplexed address/data modes are supported
• 17-bit address bus used in nonmultiplexed mode to allow access to all internal memory (including
internal extended address pages)
• HRDY signal to hold off host accesses due to DMA latency
• The HPI16 acts as a slave to a 16-bit host processor and allows access to the on-chip memory of the
DSP.
NOTE
Only the nonmultiplexed mode is supported when the 5410A HPI is configured as a
HPI16 (see Figure 3-8).
The 5410A HPI functions as a slave and enables the host processor to access the on-chip memory. A
major enhancement to the 5410A HPI over previous versions is that it allows host access to the entire
on-chip memory range of the DSP. The host and the DSP both have access to the on-chip RAM at all
times and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for
access to the same location, the host has priority, and the DSP waits for one cycle. Note that since host
accesses are always synchronized to the 5410A clock, an active input clock (CLKIN) is required for HPI
accesses during IDLE states, and host accesses are not allowed while the 5410A reset pin is asserted.
3.3.2
HPI Nonmultiplexed Mode
In nonmultiplexed mode, a host with separate address/data buses can access the HPI16 data register
(HPID) via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 17-bit HA address
bus. The host initiates the access with the strobe signals (HDS1, HDS2, HCS) and controls the direction of
the access with the HR/W signal. The HPI16 can stall host accesses via the HRDY signal. Note that the
HPIC register is not available in nonmultiplexed mode since there are no HCNTL signals available. All
host accesses initiate a DMA read or write access. Figure 3-8 shows a block diagram of the HPI16 in
nonmultiplexed mode.
DATA[15:0]
HPI16
PPD[15:0]
HINT
HPID[15:0]
DMA
Address[16:0]
Internal
Memory
HOST
HCNTL0
VCC
HCNTL1
HBIL
HAS
HR/W
R/W
Data Strobes
READY
HRDY
HDS1, HDS2, HCS
54xx
CPU
Figure 3-8. Host-Port Interface — Nonmultiplexed Mode
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Address (Hex)
000 0000
Reserved
000 005F
000 0060
000 007F
000 0080
Scratch-Pad
RAM
DARAM0 DARAM3
000 7FFF
000 8000
Reserved
001 7FFF
001 8000
DARAM4 DARAM7
001 FFFF
002 0000
Reserved
07F FFFF
Figure 3-9. HPI Memory Map
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3.4
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Multichannel Buffered Serial Ports (McBSPs)
The 5410A device provides high-speed, full-duplex serial ports that allow direct interface to other
C54x/LC54x devices, codecs, and other devices in a system. There are three multichannel buffered serial
ports (McBSPs) on board (three per subsystem).
The McBSP provides:
• Full-duplex communication
• Double-buffer data registers, which allow a continuous data stream
• Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
• Direct interface to:
– T1/E1 framers
– MVIP switching-compatible and ST-BUS compliant devices
– IOM-2 compliant device
– AC97-compliant device
– Serial peripheral interface (SPI)
• Multichannel transmit and receive of up to 128 channels
• A wide selection of data sizes, including: 8, 12, 16, 20, 24, or 32 bits
• µ-law and A-law companding
• Programmable polarity for both frame synchronization and data clocks
• Programmable internal clock and frame generation
The 5410A McBSPs have been enhanced to provide more flexibility in the choice of the sample rate
generator input clock source. On previous TMS320C5000™ DSP platform devices, the McBSP sample
rate input clock can be driven from one of two possible choices: the internal CPU clock, or the external
CLKS pin. However, most C5000™ DSP devices have only the internal CPU clock as a possible source
because the CLKS pin is not implemented on most device packages.
To accommodate applications that require an external reference clock for the sample rate generator, the
5410A McBSPs allow either the receive clock pin (BCLKR) or the transmit clock pin (BCLKX) to be
configured as the input clock to the sample rate generator. This enhancement is enabled through two
register bits: pin control register (PCR) bit 7 - enhanced sample clock mode (SCLKME), and sample rate
generator register 2 (SRGR2) bit 13 - McBSP sample rate generator clock mode (CLKSM). SCLKME is an
addition to the PCR contained in the McBSPs on previous C5000 devices. The new bit layout of the PCR
is shown in Figure 3-10. For a description of the remaining bits, see TMS320C54x DSP Reference Set,
Volume 5: Enhanced Peripherals (literature number SPRU302).
15
13
12
11
10
9
8
Reserved
14
XIOEN
RIOEN
FSXM
FSRM
CLKXM
CLKRM
R, +0
R/W,+0
R/W,+0
R/W,+0
R/W,+0
R/W,+0
R/W,+0
7
6
5
4
3
2
1
0
SCLKME
CLKS_STAT
DX_STAT
DR_STAT
FSXP
FSRP
CLKXP
CLKRP
R/W, +0
R, +0
R, +0
R, +0
R/W,+0
R/W,+0
R/W,+0
R/W,+0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-10. Pin Control Register (PCR)
The selection of the sample rate generator (SRG) clock input source is made by the combination of the
CLKSM and SCLKME bit values as shown in Table 3-7.
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Table 3-7. Sample Rate Generator Clock Source Selection
SCLKME
CLKSM
0
0
CLKS (not available as a pin on 5410A)
SRG CLOCK SOURCE
0
1
CPU clock
1
0
BCLKR pin
1
1
BCLKX pin
When either of the bidirectional pins, BCLKR or BCLKX, is configured as the clock input, its output buffer
is automatically disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured
as the SRG input. In this case, both the transmitter and receiver circuits can be synchronized to the SRG
output by setting the PCR bits (9:8) for CLKXM = 1 and CLKRM = 1. However, the SRG output is only
driven onto the BCLKX pin because the BCLKR output is automatically disabled.
The McBSP supports independent selection of multiple channels for the transmitter and receiver. When
multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In
using time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to
save memory and bus bandwidth, multichannel selection allows independent enabling of particular
channels for transmission and reception. Up to a maximum of 128 channels in a bit stream can be
enabled or disabled.
The 5410A McBSPs have two working modes that are selected by setting the RMCME and XMCME bits
in the multichannel control registers (MCR1x and MCR2x, respectively). See Figure 3-11 and Figure 3-12.
For a description of the remaining bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced
Peripherals (literature number SPRU302).
• In the first mode, when RMCME = 0 and XMCME = 0, there are two partitions (A and B), with each
containing 16 channels as shown in Figure 3-11 and Figure 3-12. This is compatible with the McBSPs
used in earlier TMS320C54x devices, where only 32-channel selection is enabled (default).
15
10
7
6
9
8
Reserved
XMCME
XPBBLK
R, +0
R/W, +0
R/W, +0
5
4
2
1
0
XPBBLK
XPABLK
XCBLK
XMCM
R/W, +0
R/W, +0
R, +0
R, +0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-11. Multichannel Control Register 2x (MCR2x)
15
10
7
6
9
8
Reserved
RMCME
RPBBLK
R, +0
R/W, +0
R/W, +0
1
0
5
4
2
RPBBLK
RPABLK
RCBLK
RMCM
R/W, +0
R/W, +0
R, +0
R, +0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-12. Multichannel Control Register 1x (MCR1x)
•
30
In the second mode, with RMCME = 1 and XMCME = 1, the McBSPs have 128 channel selection
capability. Twelve new registers (RCERCx-RCERHx and XCERCx-XCERHx) are used to enable the
128 channel selection. The subaddresses of the new registers are shown in Table 3-19. These new
registers, functionally equivalent to the RCERA0-RCERB1 and XCERA0-XCERB1 registers in the
5420, are used to enable/disable the transmit and receive of additional channel partitions (C,D,E,F,G,
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and H) in the128 channel stream. For example, XCERH1 is the transmit enable for channel partition H
(channels 112 to 127) of MCBSP1 for each DSP subsystem. See Figure 3-13, Table 3-8, Figure 3-14,
and Table 3-9 for bit layout and function of the receive and transmit registers .
15
14
13
12
11
10
9
8
RCERyz15
RCERyz14
RCERyz13
RCERyz12
RCERyz11
RCERyz10
RCERyz9
RCERyz8
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
7
6
5
4
3
2
1
0
RCERyz7
RCERyz6
RCERyz5
RCERyz4
RCERyz3
RCERyz2
RCERyz1
RCERyz0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
LEGEND: R = Read, W = Write, n = value at reset; y = partition A, B, C, D, E, F, G, or H; z = McBSP0,1, or 2
Figure 3-13. Receive Channel Enable Registers Bit Layout for Partitions A to H
Table 3-8. Receive Channel Enable Registers for Partitions A to H Field Descriptions
BIT
FIELD
VALUE
15-0
RCERyz(15:0)
DESCRIPTION
Receive Channel Enable Register
0
Disables reception of nth channel in partition y.
1
Enables reception of nth channel in partition y.
15
14
13
12
11
10
9
8
XCERyz15
XCERyz14
XCERyz13
XCERyz12
XCERyz11
XCERyz10
XCERyz9
XCERyz8
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
7
6
5
4
3
2
1
0
XCERyz7
XCERyz6
XCERyz5
XCERyz4
XCERyz3
XCERyz2
XCERyz1
XCERyz0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
LEGEND: R = Read, W = Write, n = value at reset; y = partition A, B, C, D, E, F, G, or H; z = McBSP0,1, or 2
Figure 3-14. Transmit Channel Enable Registers Bit Layout for Partitions A to H
Table 3-9. Transmit Channel Enable Registers for Partitions A to H Field Descriptions
BIT
FIELD
VALUE
DESCRIPTION
15-0
XCERyz(15:0)
0
Disables transmit of nth channel in partition y.
1
Enables transmit of nth channel in partition y.
Transmit Channel Enable Register
The clock stop mode (CLKSTP) in the McBSP provides compatibility with the serial port interface (SPI)
protocol. Clock stop mode works with only single-phase frames and one word per frame. The word sizes
supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the
McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate together as a
master or as a slave.
The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum McBSP
multichannel operating frequency on the 5410A is 9 MBps. Nonmultichannel operation is limited to
38 MBps.
3.5
Hardware Timer
The 5410A device features a 16-bit timing circuit with a 4-bit prescaler. The timer counter is decremented
by one every CPU clock cycle. Each time the counter decrements to 0, a timer interrupt is generated. The
timer can be stopped, restarted, reset, or disabled by specific status bits.
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Clock Generator
The clock generator provides clocks to the 5410A device, and consists of a phase-locked loop (PLL)
circuit. The clock generator requires a reference clock input, which can be provided from an external clock
source. The reference clock input is then divided by two (DIV mode) to generate clocks for the 5410A
device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the
reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than
that of the CPU. The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input
clock signal.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the
input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input
signal. Then, other internal clock circuitry allows the synthesis of new clock frequencies for use as master
clock for the 5410A device.
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
• A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins
of the 5410A to enable the internal oscillator.
• An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
NOTE
The crystal oscillator function is not supported by all die revisions of the 5410A device.
See the TMS320VC5410A Digital Signal Processor Silicon Errata (literature number
SPRZ187) to verify which die revisions support this functionality.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that
provides various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock
timer that can be used to delay switching to PLL clocking mode of the device until lock is achieved.
Devices that have a built-in software-programmable PLL can be configured in one of two clock modes:
• PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios.
• DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL
can be completely disabled in order to minimize power dissipation.
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The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock
mode register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock
module. Note that upon reset, the CLKMD register is initialized with a predetermined value dependent only
upon the state of the CLKMD1 - CLKMD3 pins. For more programming information, see the TMS320C54x
DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131). The CLKMD pin
configured clock options are shown in Table 3-10.
Table 3-10. Clock Mode Settings at Reset
(1)
CLOCK MODE (1)
CLKMD1
CLKMD2
CLKMD3
CLKMD RESET VALUE
0
0
0
0000h
(PLL and Oscillator disabled)
0
0
1
9007h
PLL x 10 (Oscillator enabled)
0
1
0
4007h
PLL x 5 (Oscillator enabled)
1
0
0
1007h
PLL x 2(Oscillator enabled)
1
1
0
F007h
PLL x 1 (Oscillator enabled)
1
1
1
0000h
(PLL disabled, Oscillator enabled)
1
0
1
F000h
1/4 (PLL disabled, Oscillator enabled)
0
1
1
—
Reserved (Bypass mode)
The external CLKMD1-CLKMD3 pins are sampled to determine the desired clock generation mode while RS is low. Following reset, the
clock generation mode can be reconfigured by writing to the internal clock mode register in software. However, the oscillator
enable/disable selection is performed independently of the state of RS; therefore, if CLKMD1-CLKMD3 are changed following reset, the
oscillator enable/disable selection may change, but other aspects of the clock generation mode will not.
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3.7
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Enhanced External Parallel Interface (XIO2)
The 5410A external interface has been redesigned to include several improvements, including:
simplification of the bus sequence, more immunity to bus contention when transitioning between read and
write operations, the ability for external memory access to the DMA controller, and optimization of the
power-down modes.
The bus sequence on the 5410A still maintains all of the same interface signals as on previous 54x
devices, but the signal sequence has been simplified. Most external accesses now require 3 cycles
composed of a leading cycle, an active (read or write) cycle, and a trailing cycle. The leading and trailing
cycles provide additional immunity against bus contention when switching between read operations and
write operations. To maintain high-speed read access, a consecutive read mode that performs
single-cycle reads as on previous 54x devices is available.
Figure 3-15 shows the bus sequence for three cases: all I/O reads, memory reads in nonconsecutive
mode, or single memory reads in consecutive mode. The accesses shown in Figure 3-15 always require 3
CLKOUT cycles to complete.
CLKOUT
A[22:0]
D[15:0]
READ
R/W
MSTRB or IOSTRB
PS/DS/IS
Leading
Cycle
Read
Cycle
Trailing
Cycle
Figure 3-15. Nonconsecutive Memory Read and I/O Read Bus Sequence
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Figure 3-16 shows the bus sequence for repeated memory reads in consecutive mode. The accesses
shown in Figure 3-16 require (2+n) CLKOUT cycles to complete, where n is the number of consecutive
reads performed.
CLKOUT
A[22:0]
D[15:0]
READ
READ
READ
R/W
MSTRB
PS/DS
Leading
Cycle
Read
Cycle
Read
Cycle
Read
Cycle
Trailing
Cycle
Figure 3-16. Consecutive Memory Read Bus Sequence (n = 3 reads)
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Figure 3-17 shows the bus sequence for all memory writes and I/O writes. The accesses shown in
Figure 3-17 always require three CLKOUT cycles to complete.
CLKOUT
A[22:0]
D[15:0]
WRITE
R/W
MSTRB or IOSTRB
PS/DS/IS
Leading
Cycle
Write
Cycle
Trailing
Cycle
Figure 3-17. Memory Write and I/O Write Bus Sequence
The enhanced interface also provides the ability for DMA transfers to extend to external memory. For
more information on DMA capability, see the DMA sections that follow.
The enhanced interface improves the low-power performance already present on the TMS320C5000™
DSP platform by switching off the internal clocks to the interface when it is not being used. This
power-saving feature is automatic, requires no software setup, and causes no latency in the operation of
the interface.
Additional features integrated in the enhanced interface are the ability to automatically insert
bank-switching cycles when crossing 32K memory boundaries (see Section 3.2.2), the ability to program
up to 14 wait states through software (see Section 3.2.1), and the ability to divide down CLKOUT by a
factor of 1, 2, 3, or 4. Dividing down CLKOUT provides an alternative to wait states when interfacing to
slower external memory or peripheral devices. While inserting wait states extends the bus sequence
during read or write accesses, it does not slow down the bus signal sequences at the beginning and the
end of the access. Dividing down CLKOUT provides a method of slowing the entire bus sequence when
necessary. The CLKOUT divide-down factor is controlled through the DIVFCT field in the bank-switching
control register (BSCR) (see Table 3-5).
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3.8
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DMA Controller
The 5410A direct memory access (DMA) controller transfers data between points in the memory map
without intervention by the CPU. The DMA allows movements of data to and from internal program/data
memory, internal peripherals (such as the McBSPs), or external memory devices to occur in the
background of CPU operation. The DMA has six independent programmable channels, allowing six
different contexts for DMA operation.
3.8.1
Features
The DMA has the following features:
• The DMA operates independently of the CPU.
• The DMA has six channels. The DMA can keep track of the contexts of six independent block
transfers.
• The DMA has higher priority than the CPU for both internal and external accesses.
• Each channel has independently programmable priorities.
• Each channel's source and destination address registers can have configurable indexes through
memory on each read and write transfer, respectively. The address may remain constant, be
post-incremented, be post-decremented, or be adjusted by a programmable value.
• Each read or write internal transfer may be initialized by selected events.
• On completion of a half- or entire-block transfer, each DMA channel may send an interrupt to the CPU.
• The DMA can perform double-word internal transfers (a 32-bit transfer of two 16-bit words).
3.8.2
DMA External Access
The 5410A DMA supports external accesses to extended program, extended data, and extended I/O
memory. These overlay pages are only visible to the DMA controller. A maximum of two DMA channels
can be used for external memory accesses. The DMA external accesses require a minimum of 8 cycles
for external writes and a minimum of 11 cycles for external reads assuming the XIO02 is in consecutive
mode (CONSEC = 1), wait state is set to two, and CLKOUT is not divided (DIVFCT = 00).
The control of the bus is arbitrated between the CPU and the DMA While the DMA or CPU is in control of
the external bus, the other will be held-off via wait states until the current transfer is complete. The DMA
takes precedence over XIO requests.
• Only two channels are available for external accesses. (One for external reads and one for external
writes.)
• Single-word (16-bit) transfers are supported for external accesses.
• The DMA does not support transfers from the peripherals to external memory.
• The DMA does not support transfers from external memory to the peripherals.
• The DMA does not support external-to-external transfers.
• The DMA does not support synchronized external transfers.
To allow the DMA access to extended data pages, the SLAXS and DLAXS bits are added to the
DMMCRn register (see Figure 3-18).
15
14
13
12
11
AUTOINIT
DINM
IMOD
CTMOD
SLAXS
7
6
5
4
DMS
DLAXS
10
8
SIND
2
1
DIND
0
DMD
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-18. DMA Transfer Mode Control Register (DMMCRn)
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These new bit fields were created to allow the user to define the space-select for the DMA
(internal/external). The functions of the DLAXS and SLAXS bits are as follows:
DLAXS(DMMCRn[5]) Destination
0 = No external access (default internal)
1 = External access
SLAXS(DMMCRn[11]) Source
0 = No external access (default internal)
1 = External access
Table 3-11 lists the DMD bit values and their corresponding destination space.
Table 3-11. DMD Section of the DMMCRn Register
DMD
DESTINATION SPACE
00
PS
01
DS
10
I/O
11
Reserved
For the CPU external access, software can configure the memory cells to reside inside or outside the
program address map. When the cells are mapped into program space, the device automatically accesses
them when their addresses are within bounds. When the address generation logic generates an address
outside its bounds, the device automatically generates an external access.
3.8.3
DMPREC Issue
When updating the DE bits of the DMPREC register while one or more DMA channel transfers are in
progress, it is possible for the write to the DMPREC to cause an additional transfer on one of the active
channels.
The problem occurs when an active channel completes a transfer at the same time that the user updates
the DMPREC register. When the transfer completes, the DMA logic attempts to clear the DE bit
corresponding to the complete channel transfer, but the register is instead updated with the CPU write
(usually an ORM instruction) which can set the bit and cause an additional transfer on the channel. See
the TMS320VC5410A Digital Signal Processor Silicon Errata (literature number SPRZ187) for further
clarification.
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A hardware workaround has been implemented in revision A of the 5410A device. This solution consists of
an additional memory mapped register, DMCECTL (DMA Channel Enable Control), at DMA subbank
register address 0x003E, with the following characteristics:
15
14
8
SET/RESET
Reserved
W-0
W-0
7
5
4
3
2
1
0
Reserved
6
CH5
CH4
CH3
CH2
CH1
CH0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-19. DMA Channel Enable Control Register (DMCECTL)
Table 3-12. DMA Channel Enable Control Register (DMCECTL) Field Descriptions
BIT
FIELD
VALUE
DESCRIPTION
Sets or clears individual DE bits of the DMPREC register according to the values of CH0-CH5.
15
14-6
Set/Reset
Reserved
0
Clears the DE bits of the DMPREC register as specified by CH0-CH5.
1
Sets the DE bits of the DMPREC register as specified by CH0-CH5.
0
Reserved.
These bits are used in conjunction with the set/reset bit to write to the individual DE bits of the
DMPREC register.
5-0
CH5-CH0
0
Corresponding DE bit in the DMPREC register is unaffected by the Set/Reset bit.
1
Corresponding bit in the DMPREC register is set or cleared depending on the state of Set/Reset.
Use this register to enable or disable DMA channels instead of writing to the DMPREC register. For
example, to enable channels zero and five, write a value of 0x8021 to DMA subbank register address
0x03E. In this case only DE0 and DE5 of the DMPREC are set to 1. Or for another example, to disable
channel one, write a value of 0x02 to DMA subbank address 0x03E. In this case only DE1 is cleared. Note
that this is a write-only register.
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3.8.4
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DMA Memory Map
The DMA memory map, shown in Figure 3-20, allows the DMA transfer to be unaffected by the status of
the MP/MC, DROM, and OVLY bits.
Hex
0000
005F
0060
DLAXS = 0
SLAXS = 0
1FFF
2000
3FFF
4000
5FFF
6000
Program
Hex
010000
Program
Reserved
Hex
xx0000
Program
On-Chip
DARAM0
8K Words
On-Chip
DARAM1
8K Words
Reserved
On-Chip
DARAM2
8K Words
On-Chip
DARAM3
8K Words
7FFF
8000
017FFF
018000
019FFF
01A000
Reserved
On-Chip
DARAM 4
8K Words
On-Chip
DARAM 5
8K Words
Reserved
01BFFF
01C000
On-Chip
DARAM 6
8K Words
01DFFF
01E000
On-Chip
DARAM 7
8K Words
xxFFFF
01FFFF
FFFF
Page 0
Page 1
Page 2 − 127
Figure 3-20. On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0)
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Data Space (0000 - 005F)
Hex
0000
Reserved
001F
0020
DRR20
0021
DRR10
DXR20
0022
0023
DXR10
0024
Reserved
002F
DRR22
0030
DRR12
0031
DXR22
0032
0033
DXR12
0034
Reserved
0035
RCERA2
0036
0037
XCERA2
0038
Reserved
0039
003A
RECRA0
003B
XECRA0
003C
Reserved
003F
DRR21
0040
0041
DRR11
0042
DXR21
0043
DXR11
0044
Reserved
0049
004A
RCERA1
004B
XCERA1
004C
Reserved
005F
Data Space
I/O Space
Hex
0000
0000
Data Space
(See Breakout)
005F
0060
007F
0080
1FFF
2000
3FFF
4000
5FFF
6000
7FFF
8000
9FFF
A000
BFFF
C000
DFFF
E000
FFFF
Scratch-Pad
RAM
On-Chip
DARAM0
8K Words
On-Chip
DARAM1
8K Words
On-Chip
DARAM2
8K Words
Reserved
On-Chip
DARAM3
8K Words
On-Chip
DARAM4
8K Words
On-Chip
DARAM5
8K Words
On-Chip
DARAM6
8K Words
On-Chip
DARAM7
8K Words
FFFF
Figure 3-21. On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)
3.8.5
DMA Priority Level
Each DMA channel can be independently assigned high- or low-priority relative to each other. Multiple
DMA channels that are assigned to the same priority level are handled in a round-robin manner.
3.8.6
DMA Source/Destination Address Modification
The DMA provides flexible address-indexing modes for easy implementation of data management
schemes such as autobuffering and circular buffers. Source and destination addresses can be indexed
separately and can be post-incremented, post-decremented, or post-incremented with a specified index
offset.
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3.8.7
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DMA in Autoinitialization Mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA
registers can be preloaded for the next block transfer through the DMA reload registers (DMGSA,
DMGDA, DMGCR, and DMGFR). Autoinitialization allows:
• Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfers, but with the reload registers, it can reinitialize these values
for the next block transfer any time after the current block transfer begins.
• Repetitive operation: The CPU does not preload the reload register with new values for each block
transfer but only loads them on the first block transfer.
The 5410A DMA has been enhanced to expand the DMA reload register sets. Each DMA channel now
has its own DMA reload register set. For example, the DMA reload register set for channel 0 has
DMGSA0, DMGDA0, DMGCR0, and DMGFR0 while DMA channel 1 has DMGSA1, DMGDA1, DMGCR1,
and DMGFR1, etc.
To utilize the additional DMA reload registers, the AUTOIX bit is added to the DMPREC register as shown
in Figure 3-22.
15
14
FREE
AUTOIX
7
6
13
8
DPRC[5:0]
5
0
INTOSEL
DE[5:0]
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-22. DMPREC Register
Table 3-13. DMA Reload Register Selection
AUTOIX
0 (default)
1
3.8.8
DMA RELOAD REGISTER USAGE IN AUTO INIT MODE
All DMA channels use DMGSA0, DMGDA0, DMGCR0 and DMGFR0
Each DMA channel uses its own set of reload registers
DMA Transfer Counting
The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit
fields that represent the number of frames and the number of elements per frame to be transferred.
• Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum
number of frames per block transfer is 128 (FRAME COUNT= 0FFh). The counter is decremented
upon the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit
counter is reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1.
A frame count of 0 (default value) means the block transfer contains a single frame.
• Element count. This 16-bit value defines the number of elements per frame. This counter is
decremented after the read transfer of each element. The maximum number of elements per frame is
65536(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter
is reloaded with the DMA global count reload register (DMGCR).
3.8.9
DMA Transfer in Doubleword Mode
Doubleword mode allows the DMA to transfer 32-bit words in any index mode. In doubleword mode, two
consecutive 16-bit transfers are initiated and the source and destination addresses are automatically
updated following each transfer. In this mode, each 32-bit word is considered to be one element.
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3.8.10
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
DMA Channel Index Registers
The particular DMA channel index register is selected by way of the SIND and DIND fields in the DMA
transfer mode control register (DMMCRn). Unlike basic address adjustment, in conjunction with the frame
index DMFRI0 and DMFRI1, the DMA allows different adjustment amounts depending on whether or not
the element transfer is the last in the current frame. The normal adjustment value (element index) is
contained in the element index registers DMIDX0 and DMIDX1. The adjustment value (frame index) for
the end of the frame, is determined by the selected DMA frame index register, either DMFRI0 or DMFRI1.
The element index and the frame index affect address adjustment as follows:
• Element index: For all except the last transfer in the frame, the element index determines the amount
to be added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as
selected by the SIND/DIND bits.
• Frame index: If the transfer is the last in a frame, frame index is used for address adjustment as
selected by the SIND/DIND bits. This occurs in both single-frame and multiframe transfers.
3.8.11
DMA Interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA transfer mode control register (DMMCRn). The
available modes are shown in Table 3-14.
Table 3-14. DMA Interrupts
MODE
DINM
IMOD
ABU (non-decrement)
1
0
At full buffer only
ABU (non-decrement)
1
1
At half buffer and full buffer
Multiframe
1
0
At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
Multiframe
1
1
At end of frame and end of block (DMCTRn = 0)
Either
0
X
No interrupt generated
Either
0
X
No interrupt generated
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DMA Controller Synchronization Events
The transfers associated with each DMA channel can be synchronized to one of several events. The
DSYN bit field of the DMSEFCn register selects the synchronization event for a channel. The list of
possible events and the DSYN values are shown in Table 3-15.
Table 3-15. DMA Synchronization Events
DSYN VALUE
DMA SYNCHRONIZATION EVENT
0000b
No synchronization used
0001b
McBSP0 receive event
0010b
McBSP0 transmit event
0011b
McBSP2 receive event
0100b
McBSP2 transmit event
0101b
McBSP1 receive event
0110b
McBSP1 transmit event
0111b
McBSP0 receive event - ABIS mode
1000b
McBSP0 transmit event - ABIS mode
1001b
McBSP2 receive event - ABIS mode
1010b
McBSP2 transmit event - ABIS mode
1011b
McBSP1 receive event - ABIS mode
1100b
McBSP1 transmit event - ABIS mode
1101b
Timer interrupt event
1110b
External interrupt 3
1111b
Reserved
The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on
the number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt
sources. DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the
McBSP. When the 5410A is reset, the interrupts from these three DMA channels are deselected. The
INTOSEL bit field in the DMPREC register can be used to select these interrupts, as shown in Table 3-16.
Table 3-16. DMA Channel Interrupt Selection
INTOSEL Value
IMR/IFR[6]
IMR/IFR[7]
IMR/IFR[10]
IMR/IFR[11]
00b (reset
BRINT2
BXINT2
BRINT1
BXINT1
01b
BRINT2
BXINT2
DMAC2
DMAC3
10b
DMAC0
DMAC1
DMAC2
DMAC3
11b
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Reserved
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3.9
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
General-Purpose I/O Pins
In addition to the standard BIO and XF pins, the 5410A has pins that can be configured for
general-purpose I/O. These pins are:
• 18 McBSP pins — BCLKX0/1/2, BCLKR0/1/2, BDR0/1/2, BFSX0/1/2, BFSR0/1/2, BDX0/1/2
• 8 HPI data pins — HD0-HD7
The general-purpose I/O function of these pins is only available when the primary pin function is not
required.
3.9.1
McBSP Pins as General-Purpose I/O
When the receive or transmit portion of a McBSP is in reset, its pins can be configured as
general-purpose inputs or outputs. For more details on this feature, see Section 3.4.
3.9.2
HPI Data Pins as General-Purpose I/O
The 8-bit bidirectional data bus of the HPI can be used as general-purpose input/output (GPIO) pins when
the HPI is disabled (HPIENA = 0) or when the HPI is used in HPI16 mode (HPI16 = 1). Two
memory-mapped registers are used to control the GPIO function of the HPI data pins—the
general-purpose I/O control register (GPIOCR) and the general-purpose I/O status register (GPIOSR). The
GPIOCR is shown in Figure 3-23.
15
8
Reserved
0
7
6
5
4
3
2
1
0
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-23. General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch]
The direction bits (DIRx) are used to configure HD0-HD7 as inputs or outputs.
The status of the GPIO pins can be monitored using the bits of the GPIOSR. The GPIOSR is shown in
Figure 3-24.
15
8
Reserved
0
7
6
5
4
3
2
1
0
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-24. General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh]
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3.10 Device ID Register
A read-only memory-mapped register has been added to the 5410A to allow user application software to
identify on which device the program is being executed.
15
8
CHIP ID
R
7
4
3
0
CHIP REVISION
SUBSYSID
R
R
Bits 15:8 - Chip_ID (hex code of 10)
Bits 7:4 - Chip_Revision ID
Bits 3:0 - Subsystem ID (0000b for single core device)
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-25. Device ID Register (CSIDR) [MMR Address 003Eh]
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3.11 Memory-Mapped Registers
The 5410A has 27 memory-mapped CPU registers, which are mapped in data memory space address 0h
to 1Fh. Each 5410A device also has a set of memory-mapped registers associated with peripherals.
Table 3-17 gives a list of CPU memory-mapped registers (MMRs) available on 5410A. Table 3-18 shows
additional peripheral MMRs associated with the 5410A.
Table 3-17. CPU Memory-Mapped Registers
NAME
ADDRESS
DESCRIPTION
DEC
HEX
IMR
0
0
Interrupt mask register
IFR
1
1
Interrupt flag register
2-5
2-5
Reserved for testing
ST0
6
6
Status register 0
ST1
7
7
Status register 1
AL
8
8
Accumulator A low word (15-0)
—
AH
9
9
Accumulator A high word (31-16)
AG
10
A
Accumulator A guard bits (39-32)
BL
11
B
Accumulator B low word (15-0)
BH
12
C
Accumulator B high word (31-16)
BG
13
D
Accumulator B guard bits (39-32)
TREG
14
E
Temporary register
TRN
15
F
Transition register
AR0
16
10
Auxiliary register 0
AR1
17
11
Auxiliary register 1
AR2
18
12
Auxiliary register 2
AR3
19
13
Auxiliary register 3
AR4
20
14
Auxiliary register 4
AR5
21
15
Auxiliary register 5
AR6
22
16
Auxiliary register 6
AR7
23
17
Auxiliary register 7
SP
24
18
Stack pointer register
BK
25
19
Circular buffer size register
BRC
26
1A
Block repeat counter
RSA
27
1B
Block repeat start address
REA
28
1C
Block repeat end address
PMST
29
1D
Processor mode status (PMST) register
XPC
30
1E
Extended program page register
—
31
1F
Reserved
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Table 3-18. Peripheral Memory-Mapped Registers for Each DSP Subsystem
NAME
ADDRESS
DESCRIPTION
DEC
HEX
DRR20
32
20
McBSP 0 Data Receive Register 2
DRR10
33
21
McBSP 0 Data Receive Register 1
DXR20
34
22
McBSP 0 Data Transmit Register 2
DXR10
35
23
McBSP 0 Data Transmit Register 1
TIM
36
24
Timer Register
PRD
37
25
Timer Period Register
TCR
38
26
Timer Control Register
—
39
27
Reserved
SWWSR
40
28
Software Wait-State Register
BSCR
41
29
Bank-Switching Control Register
—
42
2A
Reserved
SWCR
43
2B
Software Wait-State Control Register
HPIC
44
2C
HPI Control Register (HMODE = 0 only)
—
45-47
2D-2F
DRR22
48
30
McBSP 2 Data Receive Register 2
DRR12
49
31
McBSP 2 Data Receive Register 1
DXR22
50
32
McBSP 2 Data Transmit Register 2
DXR12
51
33
McBSP 2 Data Transmit Register 1
SPSA2
52
34
McBSP 2 Subbank Address Register (1)
SPSD2
53
35
McBSP 2 Subbank Data Register (1)
—
Reserved
54-55
36-37
SPSA0
56
38
McBSP 0 Subbank Address Register (1)
SPSD0
57
39
McBSP 0 Subbank Data Register (1)
—
Reserved
58-59
3A-3B
GPIOCR
60
3C
General-Purpose I/O Control Register
GPIOSR
61
3D
General-Purpose I/O Status Register
CSIDR
62
3E
Device ID Register
—
63
3F
Reserved
DRR21
64
40
McBSP 1 Data Receive Register 2
DRR11
65
41
McBSP 1 Data Receive Register 1
DXR21
66
42
McBSP 1 Data Transmit Register 2
DXR11
67
43
McBSP 1 Data Transmit Register 1
68-71
44-47
SPSA1
72
48
McBSP 1 Subbank Address Register (1)
SPSD1
73
49
McBSP 1 Subbank Data Register (1)
—
—
Reserved
Reserved
74-83
4A-53
DMPREC
84
54
DMA Priority and Enable Control Register
DMSA
85
55
DMA Subbank Address Register (2)
DMSDI
86
56
DMA Subbank Data Register with Autoincrement (2)
DMSDN
87
57
DMA Subbank Data Register (2)
88
58
Clock Mode Register (CLKMD)
89-95
59-5F
CLKMD
—
(1)
(2)
48
Reserved
Reserved
See Table 3-19 for a detailed description of the McBSP control registers and their subaddresses.
See Table 3-20 for a detailed description of the DMA subbank addressed registers.
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3.12 McBSP Control Registers and Subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory
location. The McBSP subbank address register (SPSA) is used as a pointer to select a particular register
within the subbank. The McBSP data register (SPSDx) is used to access (read or write) the selected
register. Table 3-19 shows the McBSP control registers and their corresponding subaddresses.
Table 3-19. McBSP Control Registers and Subaddresses
McBSP0
McBSP1
McBSP2
NAME
ADDRESS
NAME
ADDRESS
NAME
ADDRESS
SUBADDRESS
SPCR10
39h
SPCR11
49h
SPCR12
35h
00h
Serial port control register 1
SPCR20
39h
SPCR21
49h
SPCR22
35h
01h
Serial port control register 2
RCR10
39h
RCR11
49h
RCR12
35h
02h
Receive control register 1
RCR20
39h
RCR21
49h
RCR22
35h
03h
Receive control register 2
XCR10
39h
XCR11
49h
XCR12
35h
04h
Transmit control register 1
XCR20
39h
XCR21
49h
XCR22
35h
05h
Transmit control register 2
SRGR10
39h
SRGR11
49h
SRGR12
35h
06h
Sample rate generator register 1
SRGR20
39h
SRGR21
49h
SRGR22
35h
07h
Sample rate generator register 2
MCR10
39h
MCR11
49h
MCR12
35h
08h
Multichannel control register 1
DESCRIPTION
MCR20
39h
MCR21
49h
MCR22
35h
09h
Multichannel control register 2
RCERA0
39h
RCERA1
49h
RCERA2
35h
0Ah
Receive channel enable register partition A
RCERB0
39h
RCERB1
49h
RCERA2
35h
0Bh
Receive channel enable register partition B
XCERA0
39h
XCERA1
49h
XCERA2
35h
0Ch
Transmit channel enable register partition A
XCERB0
39h
XCERB1
49h
XCERA2
35h
0Dh
Transmit channel enable register partition B
PCR0
39h
PCR1
49h
PCR2
35h
0Eh
Pin control register
RCERC0
39h
RCERC1
49h
RCERC2
35h
010h
Additional channel enable register for
128-channel selection
RCERD0
39h
RCERD1
49h
RCERD2
35h
011h
Additional channel enable register for
128-channel selection
XCERC0
39h
XCERC1
49h
XCERC2
35h
012h
Additional channel enable register for
128-channel selection
XCERD0
39h
XCERD1
49h
XCERD2
35h
013h
Additional channel enable register for
128-channel selection
RCERE0
39h
RCERE1
49h
RCERE2
35h
014h
Additional channel enable register for
128-channel selection
RCERF0
39h
RCERF1
49h
RCERF2
35h
015h
Additional channel enable register for
128-channel selection
XCERE0
39h
XCERE1
49h
XCERE2
35h
016h
Additional channel enable register for
128-channel selection
XCERF0
39h
XCERF1
49h
XCERF2
35h
017h
Additional channel enable register for
128-channel selection
RCERG0
39h
RCERG1
49h
RCERG2
35h
018h
Additional channel enable register for
128-channel selection
RCERH0
39h
RCERH1
49h
RCERH2
35h
019h
Additional channel enable register for
128-channel selection
XCERG0
39h
XCERG1
49h
XCERG2
35h
01Ah
Additional channel enable register for
128-channel selection
XCERH0
39h
XCERH1
49h
XCERH2
35h
01Bh
Additional channel enable register for
128-channel selection
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3.13 DMA Subbank Addressed Registers
The direct memory access (DMA) controller has several control registers associated with it. The main
control register (DMPREC) is a standard memory-mapped register. However, the other registers are
accessed using the subbank addressing scheme. This allows a set or subbank of registers to be accessed
through a single memory location. The DMA subbank address (DMSA) register is used as a pointer to
select a particular register within the subbank, while the DMA subbank data (DMSD) register or the DMA
subbank data register with autoincrement (DMSDI) is used to access (read or write) the selected register.
When the DMSDI register is used to access the subbank, the subbank address is automatically
postincremented so that a subsequent access affects the next register within the subbank. This
autoincrement feature is intended for efficient, successive accesses to several control registers. If the
autoincrement feature is not required, the DMSDN register should be used to access the subbank.
Table 3-20 shows the DMA controller subbank addressed registers and their corresponding subaddresses.
Table 3-20. DMA Subbank Addressed Registers
ADDRESS
SUBADDRESS
DMSRC0
56h/57h
00h
DMA channel 0 source address register
DMDST0
56h/57h
01h
DMA channel 0 destination address register
DMCTR0
56h/57h
02h
DMA channel 0 element count register
DMSFC0
56h/57h
03h
DMA channel 0 sync select and frame count register
DMMCR0
56h/57h
04h
DMA channel 0 transfer mode control register
DMSRC1
56h/57h
05h
DMA channel 1 source address register
DMDST1
56h/57h
06h
DMA channel 1 destination address register
DMCTR1
56h/57h
07h
DMA channel 1 element count register
DMSFC1
56h/57h
08h
DMA channel 1 sync select and frame count register
DMMCR1
56h/57h
09h
DMA channel 1 transfer mode control register
DMSRC2
56h/57h
0Ah
DMA channel 2 source address register
DMDST2
56h/57h
0Bh
DMA channel 2 destination address register
DMCTR2
56h/57h
0Ch
DMA channel 2 element count register
DMSFC2
56h/57h
0Dh
DMA channel 2 sync select and frame count register
DMMCR2
56h/57h
0Eh
DMA channel 2 transfer mode control register
DMSRC3
56h/57h
0Fh
DMA channel 3 source address register
DMDST3
56h/57h
10h
DMA channel 3 destination address register
DMCTR3
56h/57h
11h
DMA channel 3 element count register
DMSFC3
56h/57h
12h
DMA channel 3 sync select and frame count register
DMMCR3
56h/57h
13h
DMA channel 3 transfer mode control register
DMSRC4
56h/57h
14h
DMA channel 4 source address register
DMDST4
56h/57h
15h
DMA channel 4 destination address register
DMCTR4
56h/57h
16h
DMA channel 4 element count register
DMSFC4
56h/57h
17h
DMA channel 4 sync select and frame count register
DMMCR4
56h/57h
18h
DMA channel 4 transfer mode control register
DMSRC5
56h/57h
19h
DMA channel 5 source address register
DMDST5
56h/57h
1Ah
DMA channel 5 destination address register
DMCTR5
56h/57h
1Bh
DMA channel 5 element count register
DMSFC5
56h/57h
1Ch
DMA channel 5 sync select and frame count register
DMMCR5
56h/57h
1Dh
DMA channel 5 transfer mode control register
DMSRCP
56h/57h
1Eh
DMA source program page address (common channel)
DMDSTX
56h/57h
1Fh
DMA destination program page address (common channel)
DMIDX0
56h/57h
20h
DMA element index address register 0
DMIDX1
56h/57h
21h
DMA element index address register 1
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Table 3-20. DMA Subbank Addressed Registers (continued)
ADDRESS
SUBADDRESS
DMFRI0
56h/57h
22h
DMA frame index register 0
DMFRI1
56h/57h
23h
DMA frame index register 1
DMGSA0
56h/57h
24h
DMA global source address reload register, channel 0
DMGDA0
56h/57h
25h
DMA global destination address reload register, channel 0
DMGCR0
56h/57h
26h
DMA global count reload register, channel 0
DMGFR0
56h/57h
27h
DMA global frame count reload register, channel 0
-
56h/57h
28h
Reserved
-
56h/57h
29h
Reserved
DMGSA1
56h/57h
2Ah
DMA global source address reload register, channel 1
DMGDA1
56h/57h
2Bh
DMA global destination address reload register, channel 1
DMGCR1
56h/57h
2Ch
DMA global count reload register, channel 1
DMGFR1
56h/57h
2Dh
DMA global frame count reload register, channel 1
DMGSA2
56h/57h
2Eh
DMA global source address reload register, channel 2
DMGDA2
56h/57h
2Fh
DMA global destination address reload register, channel 2
DMGCR2
56h/57h
30h
DMA global count reload register, channel 2
DMGFR2
56h/57h
31h
DMA global frame count reload register, channel 2
DMGSA3
56h/57h
32h
DMA global source address reload register, channel 3
DMGDA3
56h/57h
33h
DMA global destination address reload register, channel 3
DMGCR3
56h/57h
34h
DMA global count reload register, channel 3
DMGFR3
56h/57h
35h
DMA global frame count reload register, channel 3
DMGSA4
56h/57h
36h
DMA global source address reload register, channel 4
DMGDA4
56h/57h
37h
DMA global destination address reload register, channel 4
DMGCR4
56h/57h
38h
DMA global count reload register, channel 4
DMGFR4
56h/57h
39h
DMA global frame count reload register, channel 4
DMGSA5
56h/57h
3Ah
DMA global source address reload register, channel 5
DMGDA5
56h/57h
3Bh
DMA global destination address reload register, channel 5
DMGCR5
56h/57h
3Ch
DMA global count reload register, channel 5
DMGFR5
56h/57h
3Dh
DMA global frame count reload register, channel 5
DMCECTL
56h/57h
3Eh
DMA channel enable control
NAME
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3.14 Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3-21.
Table 3-21. Interrupt Locations and Priorities
TRAP/INTR
NUMBER (K)
NAME
LOCATION
DECIMAL HEX
PRIORITY
FUNCTION
RS, SINTR
0
0
00
1
Reset (hardware and software reset)
NMI, SINT16
1
4
04
2
Nonmaskable interrupt
SINT17
2
8
08
—
Software interrupt #17
SINT18
3
12
0C
—
Software interrupt #18
SINT19
4
16
10
—
Software interrupt #19
SINT20
5
20
14
—
Software interrupt #20
SINT21
6
24
18
—
Software interrupt #21
SINT22
7
28
1C
—
Software interrupt #22
SINT23
8
32
20
—
Software interrupt #23
SINT24
9
36
24
—
Software interrupt #24
SINT25
10
40
28
—
Software interrupt #25
SINT26
11
44
2C
—
Software interrupt #26
SINT27
12
48
30
—
Software interrupt #27
SINT28
13
52
34
—
Software interrupt #28
SINT29
14
56
38
—
Software interrupt #29
SINT30
15
60
3C
—
Software interrupt #30
INT0, SINT0
16
64
40
3
External user interrupt #0
INT1, SINT1
17
68
44
4
External user interrupt #1
INT2, SINT2
18
72
48
5
External user interrupt #2
TINT, SINT3
19
76
4C
6
Timer interrupt
RINT0, SINT4
20
80
50
7
McBSP #0 receive interrupt (default)
XINT0, SINT5
21
84
54
8
McBSP #0 transmit interrupt (default)
RINT2, SINT6
22
88
58
9
McBSP #2 receive interrupt (default)
XINT2, SINT7
23
92
5C
10
McBSP #2 transmit interrupt (default)
INT3, SINT8
24
96
60
11
External user interrupt #3
HINT, SINT9
25
100
64
12
HPI interrupt
RINT1, SINT10
26
104
68
13
McBSP #1 receive interrupt (default)
XINT1, SINT11
27
108
6C
14
McBSP #1 transmit interrupt (default)
DMAC4,SINT12
28
112
70
15
DMA channel 4 (default)
DMAC5,SINT13
Reserved
29
116
74
16
DMA channel 5 (default)
30-31
120-127
78-7F
—
Reserved
The bit layout of the interrupt flag register (IFR) and the interrupt mask register (IMR) is shown in
Figure 3-26.
15
14
Reserved
13
12
11
10
9
8
DMAC5
DMAC4
XINT1
RINT1
HINT
INT3
7
6
5
4
3
2
1
0
XINT2
RINT2
XINT0
RINT0
TINT
INT2
INT1
INT0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-26. IFR and IMR
52
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4
Support
4.1
Documentation Support
Extensive documentation supports all TMS320™ DSP family of devices from product announcement
through applications development. The following types of documentation are available to support the
design and use of the C5000™ platform of DSPs:
SPRU307:
TMS320C54x DSP Family Functional Overview
Provides a functional overview of the devices included in the TMS320C54x™ DSP
generation of digital signal processors. Included are descriptions of the CPU architecture,
bus structure, memory structure, on-chip peripherals, and instruction set.
SPRA164:
Calculation of TMS320LC54x Power Dissipation
Describes the power-saving features of the TMS320LC54x and presents techniques for
analyzing systems and device conditions to determine operating current levels and power
dissipaton. From this information, informed decisions can be made regarding power supply
requirements and thermal management considerations.
The five-volume TMS320C54x DSP Reference Set consists of:
SPRU131:
TMS320C54x DSP Reference Set, Volume 1: CPU
Describes the TMS320C54x 16-bit fixed-point general-purpose digital signal processors.
Covered are its architecture, internal register structure, data and program addressing, and
the instruction pipeline. Also includes development support information, parts lists, and
design considerations for using the XDS510 emulator.
SPRU172:
TMS320C54x DSP Reference Set, Volume 2: Mnemonic Instruction Set
Describes the TMS320C54x digital signal processor mnemonic instructions individually. Also
includes a summary of instruction set classes and cycles.
SPRU179:
TMS320C54x DSP Reference Set, Volume 3: Algebraic Instruction Set
Describes the TMS320C54x digital signal processor algebraic instructions individually. Also
includes a summary of instruction set classes and cycles.
SPRU173:
TMS320C54x DSP Reference Set, Volume 4: Applications Guide
Describes software and hardware applications for the TMS320C54x digital signal processor.
Also includes development support information, parts lists, and design considerations for
using the XDS510 emulator.
SPRU302:
TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals
Describes the enhanced peripherals available on the TMS320C54x digital signal processors.
Includes the multichannel buffered serial ports (McBSPs), direct memory access (DMA)
controller, interprocessor communications, and the HPI-8 and HPI-16 host port interfaces.
The reference set describes in detail the TMS320C54x™ DSP products currently available and the
hardware and software applications, including algorithms, for fixed-point TMS320™ DSP family of devices.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Information regarding TI DSP porducts is also available on the web at www.ti.com.
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4.2
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Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS (e.g., TMS320C6412GDK600). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary
stages of product development from engineering prototypes (TMX/TMDX) through fully qualified
production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device's electrical
specifications
TMP
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers
describing their limitations and intended uses.
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
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SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320VC5410A DSP.
5.1
Absolute Maximum Ratings
The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond
those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated under Section 5.2 is not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability. All voltage values are with respect to DVSS. Figure 5-1 provides the
test load circuit values for a 3.3-V device.
DVDD
Supply voltage I/O range
– 0.3 V to 4.0 V
CVDD
Supply voltage core range
– 0.3 V to 2.0 V
VI
Input voltage range
– 0.3 V to 4.5 V
VO
Output voltage range
– 0.3 V to 4.5 V
TC
Operating case temperature range
– 40°C to 100°C
Tstg
Storage temperature range
– 55°C to 150°C
5.2
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
2.7
3.3
3.6
V
Device supply voltage, core (VC5410A–160)
1.55
1.6
1.65
V
Device supply voltage, core (VC5410A–120)
1.42
1.5
1.65
V
DVDD
Device supply voltage, I/O
CVDD
CVDD
DVSS,
CVSS
Supply voltage, GND
0
VIH
High-level input voltage, I/O
VIL
Low-level input voltage
RS, INTn, NMI, X2/CLKIN,
CLKMDn, BCLKRn, BCLKXn,
HCS, HDS1, HDS2, HAS,
TRST, TCK, BIO, Dn, An,
HDn(DVDD = 2.7 V to 3.6 V)
All other inputs
DVDD + 0.3
2
DVDD + 0.3
(1) (2)
High-level output current
IOL
Low-level output current (1) (2)
TC
Operating case temperature
(1)
(2)
2.4
– 0.3
IOH
V
– 40
V
0.8
V
–8
mA
8
mA
100
°C
These output current limits are used for the test conditions on VOL and VOH, except where noted otherwise.
The maximum output currents are DC values only. Transient currents may exceed these values.
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Fixed-Point Digital Signal Processor
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5.3
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Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted)
PARAMETER
MIN TYP (1)
TEST CONDITIONS
(DVDD = 2.7 V to 3.0 V), IOH = –2 mA
2.2
(DVDD = 3.0 V to 3.6 V), IOH = MAX
2.4
VOH
High-level output voltage (2)
VOL
Low-level output voltage (2)
IOL = MAX
IIZ
Input current in high
impedance
DVDD = MAX, VO = DVSS to DVDD
A[16:0]
Input current
(VI = DVSS to DVDD)
II
0.4
V
275
µA
– 40
40
µA
– 10
800
– 10
400
TRST, HPI16
With internal pulldown
HPIENA
With internal pulldown, RS = 0
TMS, TCK, TDI, HPI (3)
With internal pullups
– 400
10
D[15:0], HD[7:0]
Bus holders enabled, DVDD = MAX (4)
– 275
275
All other input-only pins
UNIT
V
– 275
X2/CLKIN
MAX
–5
µA
5
IDDC
Supply current, core CPU
CVDD = 1.6 V, fx = 160 MHz, (5)TC = 25°C
60 (6)
mA
IDDP
Supply current, pins
DVDD = 3.0 V, fx = 160 MHz, (5)TC = 25°C
40
(7)
mA
2
mA
IDD
Supply current,
standby
Ci
Co
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
5.4
IDLE2
PLL × 1 mode, 20 MHz input
IDLE3, divide-by-two
mode, CLKIN stopped
TC = 25°C
1 (8)
TC = 100°C
30
mA
Input capacitance
5
pF
Output capacitance
5
pF
All values are typical unless otherwise specified.
All input and output voltage levels except RS, INT0–INT3, NMI, X2/CLKIN, CLKMD1–CLKMD3, BCLKR0 – BCLKR2, BCLKX0 –
BCLKX2, HCS, HAS, HDS1, HDS2, BIO, TCK, TRST, D0 – D15, HD0 – HD7, A0 – A16 are LVTTL-compatible.
HPI input signals except for HPIENA and HPI16, when HPIENA = 0.
VIL(MIN) ≤ VI ≤ VIL(MAX) or VIH(MIN) ≤ VI ≤ VIH(MAX)
Clock mode: PLL × 1 with external source
This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program
being executed.
This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is
performed, refer to the Calculation of TMS320LC54x Power Dissipation application report (literature number SPRA164).
Material with high IDD has been observed with a typical IDD value of 5 to 10 mA during high temperature testing.
Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this data manual.
Tester Pin Electronics
42 W
3.5 nH
Transmission Line
Z0 = 50 W
(see note)
4.0 pF
1.85 pF
Data Sheet Timing Reference Point
Output
Under
Test
Device Pin
(see note)
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must
taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The
transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data
sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 5-1. Tester Pin Electronics
56
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5.5
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are
created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and
other related terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
dis
disable time
Z
High impedance
en
enable time
f
fall time
h
hold time
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
X
Unknown, changing, or don't care level
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TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
5.6
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Internal Oscillator With External Crystal
The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is
device-dependent; see Section 3.6) and connecting a crystal or ceramic resonator across X1 and
X2/CLKIN. The CPU clock frequency is one-half, one-fourth, or a multiple of the oscillator frequency. The
multiply ratio is determined by the bit settings in the CLKMD register.
The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series
resistance of 30Ω maximum and power dissipation of 1 mW. The connection of the required circuit,
consisting of the crystal and two load capacitors, is shown in Figure 5-2. The load capacitors, C1 and C2,
should be chosen such that the equation below is satisfied. CL (recommended value of 10 pF)in the
equation is the load specified for the crystal.
CL +
C 1C 2
(C1 ) C2)
Table 5-1. Input Clock Frequency Characteristics
fx
(1)
(2)
Input clock frequency
MIN
MAX
UNIT
10 (1)
20 (2)
MHz
This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz
It is recommended that the PLL multiply by N clocking option be used for maximum frequency operation.
X1
X2/CLKIN
Crystal
C1
C2
Figure 5-2. Internal Divide-By-Two Clock Option With External Crystal
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5.7
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
Clock Options
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four or
multiplied by one of several values to generate the internal machine cycle.
5.7.1
Divide-By-Two and Divide-By-Four Clock Options
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or
four to generate the internal machine cycle. The selection of the clock mode is described in Section 3.6.
When an external clock source is used, the frequency injected must conform to specifications listed in
Table 5-3.
An external frequency source can be used by applying an input clock to X2/CLKIN with X1 left
unconnected.
Table 5-2 shows the configuration options for the CLKMD pins that generate the external divide-by-2 or
divide-by-4 clock option.
Table 5-2. Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options
CLKMD1
CLKMD2
CLKMD3
Clock Mode
0
0
0
1/2, PLL disabled
1
0
1
1/4, PLL disabled
1
1
1
1/2, PLL disabled
Table 5-3 and Table 5-4 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5-3).
Table 5-3. Divide-By-2 and Divide-By-4 Clock Options Timing Requirements
5410A-120
5410A-160
MIN
UNIT
MAX
tc(CI)
Cycle time, X2/CLKIN
20
ns
tf(CI)
Fall time, X2/CLKIN
4
ns
tr(CI)
Rise time, X2/CLKIN
4
ns
tw(CIL)
Pulse duration, X2/CLKIN low
4
ns
tw(CIH)
Pulse duration, X2/CLKIN high
4
ns
Table 5-4. Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics
Parameter
5410A-120
MIN
TYP
8.33 (1)
5410A-160
MAX
MIN
(2)
6.25 (1)
11
4
TYP
MAX
UNIT
(2)
ns
11
ns
tc(CO)
Cycle time, CLKOUT
td(CIH-CO)
Delay time, X2/CLKIN high to CLKOUT high/low
tf(CO)
Fall time, CLKOUT
1
1
tr(CO)
Rise time, CLKOUT
1
1
tw(COL)
Pulse duration, CLKOUT low
H –3
H
H+3
H –3
H
H+3
ns
tw(COH)
Pulse duration, CLKOUT high
H–3
H
H+3
H–3
H
H+3
ns
(1)
(2)
4
7
7
ns
ns
It is recommended that the PLL clocking option be used for maximum frequency operation.
This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
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tr(CI)
tw(CIH)
tf(CI)
tw(CIL)
tc(CI)
X2/CLKIN
tc(CO)
td(CIH-CO)
tw(COH)
tf(CO)
tr(CO)
tw(COL)
CLKOUT(A)
A.
The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as
00 (CLKOUT not divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5-3. External Divide-By-Two Clock Timing
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5.7.2
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
Multiply-By-N Clock Option (PLL Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to
generate the internal machine cycle. The selection of the clock mode and the value of N is described in
Section 3.6. Following reset, the software PLL can be programmed for the desired multiplication factor.
Refer to the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number
SPRU131) for detailed information on programming the PLL.
When an external clock source is used, the external frequency injected must conform to specifications
listed in Table 5-5.
Table 5-5 and Table 5-6 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5-4).
Table 5-5. Multiply-By-N Clock Option Timing Requirements
5410A-120
5410A-160
MAX
20
200
20
100
20
50
Integer PLL multiplier N
(N = 1–15) (1)
tc(CI)
Cycle time, X2/CLKIN
PLL multiplier N = x.5 (1)
PLL multiplier N = x.25, x.75
UNIT
MIN
(1)
ns
tf(CI)
Fall time, X2/CLKIN
tr(CI)
Rise time, X2/CLKIN
tw(CIL)
Pulse duration, X2/CLKIN low
4
ns
tw(CIH)
Pulse duration, X2/CLKIN high
4
ns
(1)
4
ns
4
ns
N is the multiplication factor.
Table 5-6. Multiply-By-N Clock Option Switching Characteristics
5410A-120
PARAMETER
MIN
TYP
5410A-160
MAX
8.33
MIN
TYP
MAX
tc(CO)
Cycle time, CLKOUT
td(CI-CO)
Delay time, X2/CLKIN high/low to CLKOUT high/low
tf(CO)
Fall time, CLKOUT
2
2
ns
tr(CO)
Rise time, CLKOUT
2
2
ns
tw(COL)
Pulse duration, CLKOUT low
H
H
ns
tw(COH)
Pulse duration, CLKOUT high
H
H
tp
Transitory phase, PLL lock-up time
4
6.25
UNIT
7
11
4
ns
7
30
tw(CIH)
tc(CI)
tw(CIL)
11
ns
ns
30
ms
tf(CI)
tr(CI)
X2/CLKIN
td(CI-CO)
tw(COH)
tc(CO)
tp
CLKOUT(A)
A.
tf(CO)
tw(COL)
tr(CO)
Unstable
The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as
00 (CLKOUT not divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5-4. Multiply-By-One Clock Timing
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Memory and Parallel I/O Interface Timing
Address delay times are longer for cycles immediatly following a HOLD operation. All timings related to
the address bus have been seperated in to two cases; one showing normal operation and the other
showing the delays related to the HOLD operation.
5.8.1
Memory Read
External memory reads can be performed in consecutive or nonconsecutive mode under control of the
CONSEC bit in the BSCR. Table 5-7 and Table 5-8 assume testing over recommended operating
conditions with MSTRB = 0 and H = 0.5tc(CO) (see Figure 5-5 and Figure 5-6).
Table 5-7. Memory Read Timing Requirements
5410A-120
5410A-160
MIN
Access time, read data access from address
valid, first read access (1)
ta(A)M1
UNIT
MAX
For accesses not immediately following a
HOLD operation
4H–9
ns
For a read accesses immediately following a
HOLD operation
4H–11
ns
2H–9
ns
ta(A)M2
Access time, read data access from address valid, consecutive read accesses (1)
tsu(D)R
Setup time, read data valid before CLKOUT low
7
ns
th(D)R
Hold time, read data valid after CLKOUT low
0
ns
(1)
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Table 5-8. Memory Read Switching Characteristics
5410A-120
5410A-160
PARAMETER
td(CLKL-A)
Delay time, CLKOUT low to address valid
(1)
UNIT
MIN
MAX
For accesses not immediately following a
HOLD operation
–1
4
ns
For a read accesses immediately following a
HOLD operation
–1
6
ns
td(CLKL-MSL)
Delay time, CLKOUT low to MSTRB low
–1
4
ns
td(CLKL-MSH)
Delay time, CLKOUT low to MSTRB high
–1
4
ns
(1)
62
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
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CLKOUT
td(CLKL-A)
A[22:0] (A)
td(CLKL-MSL)
td(CLKL-MSH)
ta(A)M1
D[15:0]
tsu(D)R
th(D)R
MSTRB
R/W(A)
PS/DS(A)
A.
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-5. Nonconsecutive Mode Memory Reads
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CLKOUT
td(CLKL-A)
td(CLKL-MSL)
td(CLKL-MSH)
A[22:0] (A)
ta(A)M1
ta(A)M2
D[15:0]
tsu(D)R
tsu(D)R
th(D)R
th(D)R
MSTRB
R/W(A)
(A)
DSPS/
A.
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-6. Consecutive Mode Memory Reads
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5.8.2
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
Memory Write
Table 5-9 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5tc(CO)
(see Figure 5-7).
Table 5-9. Memory Write Switching Characteristics
5410A-120
5410A-160
PARAMETER
td(CLKL-A)
tsu(A)MSL
Delay time, CLKOUT low to address
valid (1)
Setup time, address valid before MSTRB
low (1)
td(CLKL-D)W
Delay time, CLKOUT low to data valid
tsu(D)MSH
th(D)MSH
UNIT
MIN
MAX
For accesses not immediately following a
HOLD operation
–1
4
ns
For a read accesses immediately following a
HOLD operation
–1
6
ns
For accesses not immediately following a
HOLD operation
2H – 3
ns
For a read accesses immediately following a
HOLD operation
2H – 5
ns
–1
4
ns
Setup time, data valid before MSTRB high
2H – 5
2H + 6
ns
Hold time, data valid after MSTRB high
2H – 5
2H + 6
ns
td(CLKL-MSL)
Delay time, CLKOUT low to MSTRB low
–1
4
ns
tw(SL)MS
Pulse duration, MSTRB low
td(CLKL-MSH)
Delay time, CLKOUT low to MSTRB high
(1)
2H – 2
–1
ns
4
ns
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
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CLKOUT
td(CLKL-A)
td(CLKL-D)W
tsu(A)MSL
A[22:0] (A)
tsu(D)MSH
th(D)MSH
D[15:0]
td(CLKL-MSL)
td(CLKL-MSH)
tw(SL)MS
MSTRB
R/W(A)
PS/DS(A)
A.
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-7. Memory Write (MSTRB = 0)
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5.8.3
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
I/O Read
Table 5-10 and Table 5-11 assume testing over recommended operating conditions, IOSTRB = 0, and
H = 0.5tc(CO) (see Figure 5-8).
Table 5-10. I/O Read Timing Requirements
5410A-120
5410A-160
MIN
ta(A)M1
Access time, read data access from
address valid, first read access (1)
UNIT
MAX
For accesses not immediately following a
HOLD operation
4H – 9
ns
For a read accesses immediately following a
HOLD operation
4H – 11
ns
tsu(D)R
Setup time, read data valid before CLKOUT low
7
ns
th(D)R
Hold time, read data valid after CLKOUT low
0
ns
(1)
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
Table 5-11. I/O Read Switching Characteristics
5410A-120
5410A-160
PARAMETER
td(CLKL-A)
Delay time, CLKOUT low to address valid
(1)
UNIT
MIN
MAX
For accesses not immediately following a
HOLD operation
–1
4
ns
For a read accesses immediately following a
HOLD operation
–1
6
ns
td(CLKL-IOSL)
Delay time, CLKOUT low to IOSTRB low
–1
4
ns
td(CLKL-IOSH)
Delay time, CLKOUT low to IOSTRB high
–1
4
ns
(1)
Address R/W,PS, DS, and IS timings are included in timings referenced as address.
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CLKOUT
td(CLKL-A)
td(CLKL-IOSL)
td(CLKL-IOSH)
A[22:0] (A)
ta(A)M1
tsu(D)R
th(D)R
D[15:0]
IOSTRB
R/W(A)
IS(A)
A.
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-8. Parallel I/O Port Read (IOSTRB = 0)
68
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5.8.4
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
I/O Write
Table 5-12 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5tc(CO) (see
Figure 5-9).
Table 5-12. I/O Write Switching Characteristics
5410A-120
5410A-160
PARAMETER
Delay time, CLKOUT low to address
valid (1)
td(CLKL-A)
Setup time, address valid before IOSTRB
low (1)
tsu(A)IOSL
UNIT
MIN
MAX
For accesses not immediately following a
HOLD operation
–1
4
ns
For a read accesses immediately following a
HOLD operation
–1
6
ns
For accesses not immediately following a
HOLD operation
2H – 3
ns
For a read accesses immediately following a
HOLD operation
2H – 5
ns
td(CLKL-D)W
Delay time, CLKOUT low to write data valid
–1
4
ns
tsu(D)IOSH
Setup time, data valid before IOSTRB high
2H – 5
2H + 6
ns
th(D)IOSH
Hold time, data valid after IOSTRB high
2H – 5
2H + 6
ns
td(CLKL-IOSL)
Delay time, CLKOUT low to IOSTRB low
–1
4
ns
tw(SL)IOS
Pulse duration, IOSTRB low
td(CLKL-IOSH)
Delay time, CLKOUT low to IOSTRB high
(1)
2H – 2
–1
ns
4
ns
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
CLKOUT
td(CLKL-A)
A[22:0] (A)
td(CLKL-D)W
td(CLKL-D)W
tsu(A)IOS
L
D[15:0]
tsu(D)IOSH
td(CLKL-IOSH)
th(D)IOSH
td(CLKL-IOSL
IOSTRB
R/W(A)
)
tw(SL)IOS
IS(A)
A.
NOTE: Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-9. Parallel I/O Port Write (IOSTRB = 0)
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5.9
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Ready Timing for Externally Generated Wait States
Table 5-13 and Table 5-14 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5-10, Figure 5-11, Figure 5-12, and Figure 5-13).
Table 5-13. Ready Timing Requirements for Externally Generated Wait States (1)
5410A-120
5410A-160
MIN
UNIT
MAX
tsu(RDY)
Setup time, READY before CLKOUT low
7
ns
th(RDY)
Hold time, READY after CLKOUT low
0
ns
(2)
tv(RDY)MSTRB
Valid time, READY after MSTRB low
th(RDY)MSTRB
Hold time, READY after MSTRB low (2)
tv(RDY)IOSTRB
Valid time, READY after IOSTRB low (2)
th(RDY)IOSTRB
(2)
(1)
(2)
Hold time, READY after IOSTRB low
4H – 4
4H
ns
ns
4H – 4
4H
ns
ns
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states
by READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software
wait states.
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
Table 5-14. Ready Switching Characteristics for Externally Generated Wait States (1)
5410A-120
5410A-160
PARAMETER
UNIT
MIN
MAX
td(MSCL)
Delay time, CLKOUT low to MSC low
–1
4
ns
td(MSCH)
Delay time, CLKOUT low to MSC high
–1
4
ns
(1)
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states
by READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software
wait states.
CLKOUT
A[22:0]
tsu(RDY)
th(RDY)
READY
tv(RDY)MSTRB
th(RDY)MSTRB
MSTRB
td(MCSL)
td(MCSH)
MSC
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 5-10. Memory Read With Externally Generated Wait States
70
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CLKOUT
A[22:0]
D[15:0]
tsu(RDY)
th(RDY)
READY
tv(RDY)MSTRB
th(RDY)MSTRB
MSTRB
td(MSCL)
td(MSCH)
MSC
Leading
Cycle
Wait
States
Generated
by READY
Wait
States
Generated
Internally
Trailing
Cycle
Figure 5-11. Memory Write With Externally Generated Wait States
CLKOUT
A[22:0]
tsu(RDY)
th(RDY)
READY
tv(RDY)IOSTRB
th(RDY)IOSTRB
IOSTRB
td(MSCL)
td(MSCH)
MSC
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 5-12. I/O Read With Externally Generated Wait States
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CLKOUT
A[22:0]
D[15:0]
tsu(RDY)
th(RDY)
READY
tv(RDY)IOSTRB
th(RDY)IOSTRB
IOSTRB
td(MSCL)
td(MSCH)
MSC
Leading
Cycle
Wait
States
Generated
Internally
Trailing
Cycle
Wait
States
Generated
by READY
Figure 5-13. I/O Write With Externally Generated Wait States
72
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5.10 HOLD and HOLDA Timings
Table 5-15 and Table 5-16 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5-14).
Table 5-15. HOLD and HOLDA Timing Requirements
5410A-120
5410A-160
MIN
tw(HOLD)
Pulse duration, HOLD low duration
tsu(HOLD)
Setup time, HOLD before CLKOUT low
UNIT
MAX
4H+8
ns
7
ns
Table 5-16. HOLD and HOLDA Switching Characteristics
5410A-120
5410A-160
PARAMETER
MIN
UNIT
MAX
tdis(CLKL-A)
Disable time, Address, PS, DS, IS high impedance from CLKOUT low
3
ns
tdis(CLKL-RW)
Disable time, R/W high impedance from CLKOUT low
3
ns
tdis(CLKL-S)
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
3
ns
ten(CLKL-A)
Enable time, Address, PS, DS, IS valid from CLKOUT low
2H+6
ns
ten(CLKL-RW)
Enable time, R/W enabled from CLKOUT low
2H+3
ns
ten(CLKL-S)
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
tv(HOLDA)
tw(HOLDA)
2
2H+3
ns
Valid time, HOLDA low after CLKOUT low
–1
4
ns
Valid time, HOLDA high after CLKOUT low
–1
4
ns
Pulse duration, HOLDA low duration
2H–3
ns
CLKOUT
tsu(HOLD)
tw(HOLD)
tsu(HOLD)
HOLD
tv(HOLDA)
tv(HOLDA)
tw(HOLDA)
HOLDA
tdis(CLKL-A)
ten(CLKL-A)
tdis(CLKL-RW)
ten(CLKL-RW)
tdis(CLKL-S)
ten(CLKL-S)
tdis(CLKL-S)
ten(CLKL-S)
A[22:0]
PS, DS, IS
D[15:0]
R/W
MSTRB
IOSTRB
Figure 5-14. HOLD and HOLDA Timings (HM = 1)
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5.11 Reset, BIO, Interrupt, and MP/MC Timings
Table 5-17 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 5-15,
Figure 5-16, and Figure 5-17).
Table 5-17. Reset, BIO, Interrupt, and MP/MC Timing Requirements
5410A-120
5410A-160
MIN
UNIT
MAX
th(RS)
Hold time, RS after CLKOUT low
2
ns
th(BIO)
Hold time, BIO after CLKOUT low
4
ns
1
ns
4
ns
(1)
th(INT)
Hold time, INTn, NMI, after CLKOUT low
th(MPMC)
Hold time, MP/MC after CLKOUT low
tw(RSL)
Pulse duration, RS low (2) (3)
4H+3
ns
tw(BIO)S
Pulse duration, BIO low, synchronous
2H+3
ns
tw(BIO)A
Pulse duration, BIO low, asynchronous
4H
ns
tw(INTH)S
Pulse duration, INTn, NMI high (synchronous)
2H+2
ns
tw(INTH)A
Pulse duration, INTn, NMI high (asynchronous)
4H
ns
tw(INTL)S
Pulse duration, INTn, NMI low (synchronous)
2H+2
ns
tw(INTL)A
Pulse duration, INTn, NMI low (asynchronous)
4H
ns
tw(INTL)WKP
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
7
ns
(4)
tsu(RS)
Setup time, RS before X2/CLKIN low
3
ns
tsu(BIO)
Setup time, BIO before CLKOUT low
7
ns
tsu(INT)
Setup time, INTn, NMI, RS before CLKOUT low
7
ns
tsu(MPMC)
Setup time, MP/MC before CLKOUT low
5
ns
(1)
(2)
(3)
(4)
The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples these
inputs with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing
that is corresponding to three CLKOUTs sampling sequence.
If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure
synchronization and lock-in of the PLL.
Note that RS may cause a change in clock frequency, therefore changing the value of H.
The diagram assumes clock mode is divide-by-2 and the CLKOUT divide factor is set to no-divide mode (DIVFCT=00 field in the BSCR).
X2/CLKIN
tsu(RS)
tw(RSL)
RS, INTn, NMI
tsu(INT)
th(RS)
CLKOUT
tsu(BIO)
th(BIO)
BIO
tw(BIO)S
Figure 5-15. Reset and BIO Timings
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CLKOUT
tsu(INT)
tsu(INT)
th(INT)
INTn, NMI
tw(INTH)A
tw(INTL)A
Figure 5-16. Interrupt Timing
CLKOUT
RS
th(MPMC)
tsu(MPMC)
MP/MC
Figure 5-17. MP/MC Timing
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5.12 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
Table 5-18 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 5-18).
Table 5-18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics
5410A-120
5410A-160
PARAMETER
UNIT
MIN
MAX
td(CLKL-IAQL)
Delay time, CLKOUT low to IAQ low
–1
4
ns
td(CLKL-IAQH)
Delay time, CLKOUT low to IAQ high
–1
4
ns
td(A)IAQ
Delay time, IAQ low to address valid
2
ns
td(CLKL-IACKL)
Delay time, CLKOUT low to IACK low
–1
4
ns
td(CLKL-IACKH)
Delay time, CLKOUT low to IACK high
–1
4
ns
td(A)IACK
Delay time, IACK low to address valid
2
ns
th(A)IAQ
Hold time, address valid after IAQ high
–2
ns
th(A)IACK
Hold time, address valid after IACK high
–2
ns
tw(IAQL)
Pulse duration, IAQ low
2H – 2
ns
tw(IACKL)
Pulse duration, IACK low
2H – 2
ns
CLKOUT
A[22:0]
td(CLKL - IAQH)
td(CLKL - IAQL)
th(A)IAQ
td(A)IAQ
tw(IAQL)
IAQ
td(CLKL - IACKL)
td(CLKL - IACKH)
th(A)IACK
td(A)IACK
tw(IACKL)
IACK
Figure 5-18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
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5.13 External Flag (XF) and TOUT Timings
Table 5-19 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 5-19
and Figure 5-20).
Table 5-19. External Flag (XF) and TOUT Switching Characteristics
5410A-120
5410A-160
PARAMETER
UNIT
MIN
MAX
Delay time, CLKOUT low to XF high
–1
4
Delay time, CLKOUT low to XF low
–1
4
td(TOUTH)
Delay time, CLKOUT low to TOUT high
–1
4
ns
td(TOUTL)
Delay time, CLKOUT low to TOUT low
–1
4
ns
tw(TOUT)
Pulse duration, TOUT
td(XF)
2H – 4
ns
ns
CLKOUT
td(XF)
XF
Figure 5-19. External Flag (XF) Timing
CLKOUT
td(TOUTH)
td(TOUTL)
TOUT
tw(TOUT)
Figure 5-20. TOUT Timing
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5.14 Multichannel Buffered Serial Port (McBSP) Timing
5.14.1 McBSP Transmit and Receive Timings
Table 5-20 and Table 5-21 assume testing over recommended operating conditions (see Figure 5-21 and
Figure 5-22).
Table 5-20. McBSP Transmit and Receive Timing Requirements (1)
5410A-120
5410A-160
MIN
UNIT
MAX
tc(BCKRX)
Cycle time, BCLKR/X
BCLKR/X ext
4P (2)
ns
tw(BCKRX)
Pulse duration, BCLKR/X high or BCLKR/X low
BCLKR/X ext
2P–1 (2)
ns
tsu(BFRH-BCKRL)
Setup time, external BFSR high before BCLKR low
th(BCKRL-BFRH)
Hold time, external BFSR high after BCLKR low
tsu(BDRV-BCKRL)
Setup time, BDR valid before BCLKR low
th(BCKRL-BDRV)
Hold time, BDR valid after BCLKR low
tsu(BFXH-BCKXL)
Setup time, external BFSX high before BCLKX low
th(BCKXL-BFXH)
Hold time, external BFSX high after BCLKX low
tr(BCKRX)
Rise time, BCKR/X
BCLKR/X ext
6
ns
tf(BCKRX)
Fall time, BCKR/X
BCLKR/X ext
6
ns
(1)
(2)
78
BCLKR int
8
BCLKR ext
1
BCLKR int
1
BCLKR ext
2
BCLKR int
7
BCLKR ext
1
BCLKR int
2
BCLKR ext
3
BCLKX int
8
BCLKX ext
1
BCLKX int
0
BCLKX ext
2
ns
ns
ns
ns
ns
ns
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
P = 0.5 * processor clock
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Table 5-21. McBSP Transmit and Receive Switching Characteristics (1)
5410A-120
5410A-160
PARAMETER
MIN
UNIT
MAX
4P (2)
tc(BCKRX)
Cycle time, BCLKR/X
BCLKR/X int
tw(BCKRXH)
Pulse duration, BCLKR/X high
BCLKR/X int
D – 1 (3) D + 1 (3)
ns
tw(BCKRXL)
Pulse duration, BCLKR/X low
BCLKR/X int
C – 1 (3) C + 1 (3)
ns
td(BCKRH-BFRV)
Delay time, BCLKR high to internal BFSR valid
td(BCKXH-BFXV)
Delay time, BCLKX high to internal BFSX valid
tdis(BCKXH-BDXHZ)
Disable time, BCLKX high to BDX high impedance following last data
bit of transfer
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
td(BFXH-BDXV)
Delay time, BFSX high to BDX valid
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
(1)
(2)
(3)
(4)
(5)
DXENA = 0 (4)
ns
BCLKR int
–3
3
ns
BCLKR ext
0
11
ns
BCLKX int
–1
5
BCLKX ext
2
10
BCLKX int
6
BCLKX ext
10
BCLKX int
– 1 (5)
10
BCLKX ext
2
20
BFSX int
–1 (5)
7
BFSX ext
2
11
ns
ns
ns
ns
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
P = 0.5 * processor clock
T = BCLKRX period = (1 + CLKGDV) * 2P
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
The transmit delay enable (DXENA) feature of the McBSP is not implemented on the TMS320VC5410A.
Minimum delay times also represent minimum output hold times.
tc(BCKRX)
tw(BCKRXH)
tr(BCKRX)
tw(BCKRXL)
BCLKR
td(BCKRH-BFRV)
td(BCKRH-BFRV)
tr(BCKRX)
BFSR (int)
tsu(BFRH-BCKRL)
th(BCKRL-BFRH)
BFSR (ext)
th(BCKRL-BDRV)
tsu(BDRV-BCKRL)
BDR
(RDATDLY=00b)
Bit (n-1)
(n-2)
tsu(BDRV-BCKRL)
BDR
(RDATDLY=01b)
(n-3)
(n-4)
th(BCKRL-BDRV)
Bit (n-1)
(n-2)
tsu(BDRV-BCKRL)
BDR
(RDATDLY=10b)
(n-3)
th(BCKRL-BDRV)
Bit (n-1)
(n-2)
Figure 5-21. McBSP Receive Timings
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tc(BCKRX)
tw(BCKRXH)
tr(BCKRX)
tw(BCKRXL)
tf(BCKRX)
BCLKX
td(BCKXH-BFXV)
td(BCKXH-BFXV)
BFSX (int)
tsu(BFXH-BCKXL)
th(BCKXL-BFXH)
BFSX (ext)
td(BDFXH-BDXV)
BDX
(XDATDLY=00b)
Bit 0
Bit (n-1)
td(BCKXH-BDXV)
(n-2)
(n-3)
(n-4)
td(BCKXH-BDXV)
BDX
(XDATDLY=01b)
Bit 0
Bit (n-1)
(n-3)
td(BCKXH-BDXV)
tdis(BCKXH-BDXHZ)
BDX
(XDATDLY=10b)
(n-2)
Bit 0
Bit (n-1)
(n-2)
Figure 5-22. McBSP Transmit Timings
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5.14.2 McBSP General-Purpose I/O Timing
Table 5-22 and Table 5-23 assume testing over recommended operating conditions (see Figure 5-23).
Table 5-22. McBSP General-Purpose I/O Timing Requirements
5410A-120
5410A-160
MIN
UNIT
MAX
tsu(BGPIO-COH)
Setup time, BGPIOx input mode before CLKOUT high (1)
7
ns
th(COH-BGPIO)
Hold time, BGPIOx input mode after CLKOUT high (1)
0
ns
(1)
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
Table 5-23. McBSP General-Purpose I/O Switching Characteristics
5410A-120
5410A-160
PARAMETER
td(COH-BGPIO)
(1)
Delay time, CLKOUT high to BGPIOx output mode (1)
MIN
MAX
–2
4
UNIT
ns
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
tsu(BGPIO-COH)
td(COH-BGPIO)
CLKOUT
th(COH-BGPIO)
BGPIOx
Input Mode(A)
BGPIOx
Output Mode(B)
A.
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
B.
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
Figure 5-23. McBSP General-Purpose I/O Timings
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5.14.3 McBSP as SPI Master or Slave Timing
Table 5-24 to Table 5-31 assume testing over recommended operating conditions (see Figure 5-24,
Figure 5-25, Figure 5-26, and Figure 5-27).
Table 5-24. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1)
5410A-120
5410A-160
MASTER
MIN
tsu(BDRV-BCKXL)
Setup time, BDR valid before BCLKX low
th(BCKXL-BDRV)
(1)
(2)
MAX
MIN
MAX
2 – 6P (2)
12
Hold time, BDR valid after BCLKX low
UNIT
SLAVE
4
5 + 12P
ns
(2)
ns
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
Table 5-25. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) (1)
5410A-120
5410A-160
PARAMETER
MASTER (2)
MIN
(3)
MAX
Hold time, BFSX low after BCLKX low
Delay time, BFSX low to BCLKX high (4)
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
tdis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit
from BCLKX low
tdis(BFXH-BDXHZ)
Disable time, BDX high impedance following last data bit
from BFSX high
2P– 4 (5)
6P + 17 (5)
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
4P+ 2 (5)
8P + 17 (5)
ns
(4)
(5)
–4
5
C–2
C+3
MAX
td(BFXL-BCKXH)
(3)
T+4
C+3
MIN
th(BCKXL-BFXL)
(1)
(2)
T–3
C–4
UNIT
SLAVE
ns
ns
6P + 2 (5)
10P + 17 (5)
ns
ns
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input
on BFSX and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the
master clock (BCLKX).
P = 0.5 * processor clock
MSB
LSB
BCLKX
th(BCKXL-BFXL)
td(BFXL-BCKXH)
BFSX
tdis(BFXH-BDXHZ)
td(BFXL-BDXV)
td(BCKXH-BDXV)
tdis(BCKXL-BDXHZ)
BDX
Bit 0
Bit(n-1)
tsu(BDRV-BCLXL)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
th(BCKXL-BDRV)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 5-24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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Table 5-26. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) (1)
5410A-120
5410A-160
MASTER
MIN
UNIT
SLAVE
MAX
MIN
MAX
tsu(BDRV-BCKXL)
Setup time, BDR valid before BCLKX low
12
2 – 6P (2)
ns
th(BCKXH-BDRV)
Hold time, BDR valid after BCLKX high
4
5 + 12P (2)
ns
(1)
(2)
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
Table 5-27. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) (1)
5410A-120
5410A-160
PARAMETER
MASTER (2)
Hold time, BFSX low after BCLKX low (3)
th(BCKXL-BFXL)
(4)
MIN
MAX
C –3
C+4
UNIT
SLAVE
MIN
MAX
ns
td(BFXL-BCKXH)
Delay time, BFSX low to BCLKX high
T–4
T+3
td(BCKXL-BDXV)
Delay time, BCLKX low to BDX valid
–4
5
6P + 2 (5)
10P + 17 (5)
ns
tdis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit
from BCLKX low
–2
4
6P – 4 (5)
10P + 17 (5)
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
D–2
D+4
4P + 2 (5)
8P + 17 (5)
ns
(1)
(2)
(3)
(4)
(5)
ns
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input
on BFSX and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the
master clock (BCLKX).
P = 0.5 * processor clock
MSB
LSB
BCLKX
th(BCKXL-BFXL)
td(BFXL-BCKXH)
BFSX
tdis(BCKXL-BDXHZ)
BDX
td(BCKXL-BDXV)
td(BFXL-BDXV)
Bit 0
Bit(n-1)
tsu(BDRV-BCKXL)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
th(BCKXH-BDRV)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 5-25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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Table 5-28. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) (1)
5410A-120
5410A-160
MASTER
MIN
UNIT
SLAVE
MAX
MIN
MAX
tsu(BDRV-BCKXH)
Setup time, BDR valid before BCLKX high
12
2 – 6P (2)
ns
th(BCKXH-BDRV)
Hold time, BDR valid after BCLKX high
4
5 + 12P (2)
ns
(1)
(2)
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
Table 5-29. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) (1)
5410A-120
5410A-160
PARAMETER
MASTER (2)
Hold time, BFSX low after BCLKX high (3)
th(BCKXH-BFXL)
(4)
MIN
MAX
T–3
T+4
D–4
D+3
–4
5
D–2
D+3
UNIT
SLAVE
MIN
MAX
ns
td(BFXL-BCKXL)
Delay time, BFSX low to BCLKX low
td(BCKXL-BDXV)
Delay time, BCLKX low to BDX valid
tdis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data
bit from BCLKX high
tdis(BFXH-BDXHZ)
Disable time, BDX high impedance following last data
bit from BFSX high
2P – 4 (5)
6P + 17 (5)
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
4P + 2 (5)
8P + 17 (5)
ns
(1)
(2)
(3)
(4)
(5)
ns
6P + 2 (5)
10P + 17 (5)
ns
ns
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2P
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input
on BFSX and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the
master clock (BCLKX).
P = 0.5 * processor clock
LSB
MSB
BCLKX
th(BCKXH-BFXL)
td(BFXL-BCKXL)
BFSX
td(BFXL-BDXV)
tdis(BFXH-BDXHZ)
td(BCKXL-BDXV)
tdis(BCKXH-BDXHZ)
BDX
Bit 0
Bit(n-1)
tsu(BDRV-BCKXH)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
th(BCKXH-BDRV)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 5-26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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Table 5-30. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) (1)
5410A-120
5410A-160
MASTER
MIN
UNIT
SLAVE
MAX
MIN
MAX
tsu(BDRV-BCKXL)
Setup time, BDR valid before BCLKX low
12
2 – 6P (2)
ns
th(BCKXL-BDRV)
Hold time, BDR valid after BCLKX low
4
5 + 12P (2)
ns
(1)
(2)
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
Table 5-31. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) (1)
5410A-120
5410A-160
PARAMETER
MASTER (2)
Hold time, BFSX low after BCLKX high (3)
th(BCKXH-BFXL)
(4)
MIN
MAX
D–3
D+4
UNIT
SLAVE
MIN
MAX
ns
td(BFXL-BCKXL)
Delay time, BFSX low to BCLKX low
T–4
T+3
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
–4
5
6P + 2 (5)
10P + 17 (5)
ns
tdis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data
bit from BCLKX high
–2
4
6P – 4 (5)
10P + 17 (5)
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
C–2
C+4
4P + 2 (5)
8P + 17 (5)
ns
(1)
(2)
(3)
(4)
(5)
ns
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input
on BFSX and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the
master clock (BCLKX).
P = 0.5 * processor clock
MSB
LSB
BCLKX
th(BCKXH-BFXL)
td(BFXL-BCKXL)
BFSX
tdis(BCKXH-BDXHZ)
BDX
td(BCKXH-BDXV)
td(BFXL-BDXV)
Bit 0
Bit(n-1)
tsu(BDRV-BCKXL)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
th(BCKXL-BDRV)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 5-27. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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5.15 Host-Port Interface Timing
5.15.1
HPI8 Mode
Table 5-32 and Table 5-33 assume testing over recommended operating conditions and P = 0.5 *
processor clock (see Figure 5-28 through Figure 5-31). In the following tables, DS refers to the logical OR
of HCS, HDS1, and HDS2. HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). HAD stands
for HCNTL0, HCNTL1, and HR/W.
Table 5-32. HPI8 Mode Timing Requirements
5410A-120
5410A-160
MIN
UNIT
MAX
tsu(HBV-DSL)
Setup time, HBIL and HAD valid before DS low (when HAS is not used), or HBIL valid before
HAS low
6
ns
th(DSL-HBV)
Hold time, HBIL and HAD valid after DS low (when HAS is not used), or HBIL valid after
HAS low
3
ns
tsu(HSL-DSL)
Setup time, HAS low before DS low
8
ns
tw(DSL)
Pulse duration, DS low
13
ns
tw(DSH)
Pulse duration, DS high
7
ns
tsu(HDV-DSH)
Setup time, HD valid before DS high, HPI write
3
ns
th(DSH-HDV)W
Hold time, HD valid after DS high, HPI write
2
ns
tsu(GPIO-COH)
Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
3
ns
th(GPIO-COH)
Hold time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
0
ns
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Table 5-33. HPI8 Mode Switching Characteristics
5410A-120
5410A-160
PARAMETER
MIN
ten(DSL-HD)
td(DSL-HDV1)
Enable time, HD driven from DS low
Delay time, DS low to HD
valid for first byte of an
HPI read
18P+10–tw(DSH)
Case 1b: Memory accesses when DMAC is active in
32-bit mode and tw(DSH) ≥ I8H (1)
36P+10–tw(DSH)
Case 1c: Memory accesses when DMAC is active in
16-bit mode and tw(DSH) ≥ I8H (1)
10
Case 1d: Memory accesses when DMAC is active in
32-bit mode and tw(DSH) ≥ I8H (1)
10
Case 2a: Memory accesses when DMAC is inactive
and tw(DSH) < 10H (1)
10P+10–tw(DSH)
Case 2b: Memory accesses when DMAC is inactive
and tw(DSH) ≥ 10H (1)
10
Case 3: Register accesses
10
Delay time, DS low to HD valid for second byte of an HPI read
th(DSH-HDV)R
Hold time, HD valid after DS high, for a HPI read
tv(HYH-HDV)
Valid time, HD valid after HRDY high
td(DSH-HYH)
Delay time, DS high to HRDY low
Delay time, DS high to
HRDY high (2)
10
Case 1a: Memory accesses when DMAC is active in
16-bit mode and tw(DSH) < I8H (1)
td(DSL-HDV2)
td(DSH-HYL)
0
10
0
(2)
ns
ns
ns
ns
8
ns
18P+6
Case 1b: Memory accesses when DMAC is active in
32-bit mode (1)
36P+6
(1)
10P+6
Case 3: Write accesses to HPIC register (3)
ns
2
Case 1a: Memory accesses when DMAC is active in
16-bit mode (1)
Case 2: Memory accesses when DMAC is inactive
UNIT
MAX
ns
6P+6
td(HCS-HRDY)
Delay time, HCS low/high to HRDY low/high
6
ns
td(COH-HYH)
Delay time, CLKOUT high to HRDY high
9
ns
td(COH-HTX)
Delay time, CLKOUT high to HINT change
6
ns
td(COH-GPIO)
Delay time, CLKOUT high to HDx output change. HDx is configured as a
general-purpose output
5
ns
(1)
(2)
(3)
DMAC stands for direct memory access controller (DMAC). The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access
times are affected by DMAC activity.
The HRDY output is always high when the HCS input is high, regardless of DS timings.
This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur
asynchronously, and do not cause HRDY to be deasserted.
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Second Byte
First Byte
Second Byte
HAS
tsu(HBV-DSL)
tsu(HSL-DSL)
th(DSL-HBV)
HAD(A)
Valid
Valid
tsu(HBV-DSL)(B)
th(DSL-HBV) (see Note B)
HBIL
HCS
tw(DSH)
tw(DSL)
HDS
td(DSH-HYH)
td(DSH-HYL)
HRDY
ten(DSL-HD)
td(DSL-HDV2)
th(DSH-HDV)R
HD READ
td(DSL-HDV1)
Valid
Valid
tsu(HDV-DSH)
Valid
tv(HYH-HDV)
th(DSH-HDV)W
HD WRITE
Valid
Valid
Valid
td(COH-HYH)
Processor
CLK
A.
HAD refers to HCNTL0, HCNTL1, and HR/W.
B.
When HAS is not used (HAS always high)
Figure 5-28. HPI-8 Mode Timing, Using HDS to Control Accesses (HCS Always Low)
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HCS
HDS
td(HCS-HRDY)
HRDY
Figure 5-29. HPI-8 Mode Timing, Using HCS to Control Accesses
CLKOUT
td(COH-HTX)
HINT
Figure 5-30. HPI-8 Mode, HINT Timing
CLKOUT
tsu(GPIO-COH)
th(GPIO-COH)
GPIOx Input Mode(A)
td(COH-GPIO)
GPIOx Output Mode(A)
A.
GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O).
Figure 5-31. GPIOx Timings
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5.15.2 HPI16 Mode
Table 5-34 and Table 5-35 assume testing over recommended operating conditions and P = 0.5 *
processor clock (see Figure 5-32 through Figure 5-34). In the following tables, DS refers to the logical OR
of HCS, HDS1, and HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These
timings are shown assuming that HDS is the signal controlling the transfer. See the TMS320C54x DSP
Reference Set,Volume 5: Enhanced Peripherals (literature number SPRU302) for addition information.
Table 5-34. HPI16 Mode Timing Requirements
5410A-120
5410A-160
MIN
UNIT
MAX
tsu(HBV-DSL)
Setup time, HR/W valid before DS falling edge
6
ns
th(DSL-HBV)
Hold time, HR/W valid after DS falling edge
5
ns
tsu(HAV-DSH)
Setup time, address valid before DS rising edge (write)
5
ns
tsu(HAV-DSL)
Setup time, address valid before DS falling edge (read)
–(4P – 6)
ns
th(DSH-HAV)
Hold time, address valid after DS rising edge
1
ns
tw(DSL)
Pulse duration, DS low
30
ns
tw(DSH)
Pulse duration, DS high
10
ns
Memory accesses with no DMA
activity.
tc(DSH-DSH)
Cycle time, DS rising edge to next
DS rising edge
Reads
10P + 30
Writes
10P + 10
Memory accesses with 16-bit DMA Reads
activity.
Writes
16P + 30
Memory accesses with 32-bit DMA Reads
activity.
Writes
24P + 30
16P + 10
ns
24P + 10
tsu(HDV-DSH)W
Setup time, HD valid before DS rising edge
8
ns
th(DSH-HDV)W
Hold time, HD valid after DS rising edge, write
2
ns
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Table 5-35. HPI16 Mode Switching Characteristics
5410A-120
5410A-160
PARAMETER
MIN
td(DSL-HDD)
td(DSL-HDV1)
Delay time, DS low to HD driven
Delay time, DS
low to HD valid
for first word of
an HPI read
0
10
Case 1a: Memory accesses initiated immediately following a
write when DMAC is active in 16-bit mode and
tw(DSH) was < 18H
32P + 20 – tw(DSH)
Case 1b: Memory accesses not immediately following a write
when DMAC is active in 16-bit mode
16P + 20
Case 1c: Memory accesses initiated immediately following a
write when DMAC is active in 32-bit mode and
tw(DSH) was < 26H
48P + 20 – tw(DSH)
Case 1d: Memory access not immediately following a write
when DMAC is active in 32-bit mode
20P + 20 – tw(DSH)
Case 2b: Memory accesses not immediately following a write
when DMAC is inactive
10P + 20
Memory writes when no DMA is active
Delay time, DS
high to HRDY Memory writes with one or more 16-bit DMA channels active
high
Memory writes with one or more 32-bit DMA channels active
tv(HYH-HDV)
Valid time, HD valid after HRDY high
th(DSH-HDV)R
Hold time, HD valid after DS rising edge, read
td(COH-HYH)
ns
ns
24P + 20
Case 2a: Memory accesses initiated immediately following a
write when DMAC is inactive and tw(DSH) was < 10H
td(DSH-HYH)
UNIT
MAX
10P + 5
16P + 5
ns
24P + 5
7
ns
6
ns
Delay time, CLKOUT rising edge to HRDY high
5
ns
td(DSL-HYL)
Delay time, DS low to HRDY low
12
ns
td(DSH-HYL)
Delay time, DS high to HRDY low
12
ns
1
HCS
tw(DSH)
tc(DSH-DSH)
HDS
tsu(HBV-DSL)
tw(DSL)
tsu(HBV-DSL)
th(DSL-HBV)
th(DSL-HBV)
HR/W
tsu(HAV-DSL)
th(DSH-HAV)
HA[16:0]
Valid Address
Valid Address
th(DSH-HDV)R
td(DSL-HDV1)
td(DSL-HDV1)
Data
HD[15:0]
td(DSL-HDD)
th(DSH-HDV)R
Data
td(DSL-HDD)
tv(HYH-HDV)
tv(HYH-HDV)
HRDY
td(DSL-HYL)
td(DSL-HYL)
Figure 5-32. HPI-16 Mode, Nonmultiplexed Read Timings
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HCS
tw(DSH)
tc(DSH-DSH)
HDS
tsu(HBV-DSL)
tsu(HBV-DSL)
th(DSL-HBV)
th(DSL-HBV)
HR/W
tsu(HAV-DSH)
tw(DSL)
th(DSH-HAV)
HA[16:0]
Valid Address
Valid Address
tsu(HDV-DSH)W
tsu(HDV-DSH)W
th(DSH-HDV)W
th(DSH-HDV)W
HD[15:0]
Data Valid
Data Valid
td(DSH-HYH)
HRDY
td(DSH-HYL)
Figure 5-33. HPI-16 Mode, Nonmultiplexed Write Timings
HRDY
td(COH-HYH)
CLKOUT
Figure 5-34. HPI-16 Mode, HRDY Relative to CLKOUT
92
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6
SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008
Mechanical Data
The following mechanical package diagram(s) reflect the most current released mechanical data available
for the designated device(s).
6.1
Package Thermal Resistance Characteristics
Table 6-1 provides the estimated thermal resistance characteristics for the recommended package types
used on the device.
Table 6-1. Thermal Resistance Characteristics
PARAMETER
GGU PACKAGE
PGE PACKAGE
UNIT
RθJA
38
56
°C/W
RθJC
5
5
°C/W
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93
PACKAGE OPTION ADDENDUM
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11-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TMS320VC5410AGWS12
ACTIVE
NFBGA
GWS
144
160
Non-RoHS
& Green
SNPB
Level-3-220C-168 HR
-40 to 100
DVC5410AGWS
120
Samples
TMS320VC5410AGWS16
ACTIVE
NFBGA
GWS
144
160
Non-RoHS
& Green
SNPB
Level-3-220C-168 HR
-40 to 100
DVC5410AGWS
160
Samples
TMS320VC5410APGE12
ACTIVE
LQFP
PGE
144
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 0
320VC5410
APGE
120
TMS
TMS320VC5410APGE16
ACTIVE
LQFP
PGE
144
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 0
320VC5410A
PGE
160
TMS
TMS320VC5410AZWS12
ACTIVE
NFBGA
ZWS
144
160
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 100
DVC5410AZWS
120
Samples
TMS320VC5410AZWS16
ACTIVE
NFBGA
ZWS
144
160
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 100
DVC5410AZWS
160
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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