TMS370C156AFNT

TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 D D D D D D D D D FN / FZ PACKAGE ( TOP VIEW ) VSS1 C2 C1 MC C0 B7 B6 B5 B4 B3 B2 B1 B0 D0 / CSE2 / OCF VCC2 VSS2 VCC1 CMOS/EEPROM/EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume Production – One-Time-Programmable (OTP) EPROM Devices for Low-Volume Production – Reprogrammable EPROM Devices for Prototyping Purposes Internal System Memory Configurations – On-Chip Program Memory Versions – ROM: 4K to 48K Bytes – EPROM: 16K to 48K Bytes – ROM-less – Data EEPROM: 256 or 512 Bytes – Static RAM: 256 to 3.5K Bytes – External Memory / Peripheral Wait States – Precoded External Chip-Select Outputs in Microcomputer Mode Flexible Operating Features – Low-Power Modes: STANDBY and HALT – Commercial, Industrial, and Automotive Temperature Ranges – Clock Options – Divide-by-4 (0.5 MHz – 5 MHz SYSCLK) – Divide-by-1 (2 MHz – 5 MHz SYSCLK) Phase-Locked Loop (PLL) – Supply Voltage (VCC): 5 V ± 10% Eight-Channel 8-Bit Analog-to-Digital Converter 1 (ADC1) Two 16-Bit General-Purpose Timers On-Chip 24-Bit Watchdog Timer Two Communication Modules – Serial Communications Interface 1 (SCI1) – Serial Peripheral Interface (SPI) Flexible Interrupt Handling TMS370 Series Compatibility CMOS/Package /TTL-Compatible I / O Pins – 64-Pin Plastic and Ceramic Shrink Dual-In-Line Packages / 44 Bidirectional, 9 Input Pins – 68-Pin Plastic and Ceramic Leaded Chip Carrier Packages / 46 Bidirectional, 9 Input Pins – All Peripheral Function Pins Are Software Configurable for Digital I / O C3 C4 C5 C6 C7 VCC2 VSS2 A0 A1 A2 A3 A4 A5 A6 A7 T2AEVT T2AIC2/PWM 10 11 12 13 14 15 16 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 D1 / CSH3 D2 / CSH2 D3 / SYSCLK D4 / R / W D5 / CSPF D6/CSH1/EDS D7/CSE1/WAIT RESET INT1 INT2 INT3 SPISOMI SPISIMO SPICLK T1IC/CR T1PWM T1EVT T2AIC1/CR SCICLK SCIRXD SCITXD XTAL2/CLKIN XTAL1 V CC1 V CC3 V SS3 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 D JN / NM PACKAGE ( TOP VIEW ) B5 B6 B7 C0 MC C1 C2 VSS1 C3 C4 C5 C6 C7 AN0 A0 A1 A2 A3 A4 A5 A6 A7 T2AEVT T2AIC2 / PWM T2AIC1 / CR SCICLK SCIRXD SCITXD XTAL2 / CLKIN XTAL1 VCC1 VCC3 D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 B4 B3 B2 B1 B0 D0 / CSE2 / OCF VSS1 VCC1 D1 / CSH3 D3 / SYSCLK D4 / R / W D6 / CSH1 / EDS D7 / CSE1 / WAIT RESET INT1 INT2 INT3 SPISOMI SPISIMO SPICLK T1IC / CR T1PWM AN7 T1EVT VSS1 AN6 AN5 AN4 AN3 AN2 AN1 VSS3 Workstation/PC-Based Development System – C Compiler and C Source Debugger – Real-Time In-Circuit Emulation – Extensive Breakpoint / Trace Capability – Software Performance Analysis – Multi-Window User Interface – Microcontroller Programmer Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Pin Descriptions PIN I/O† DESCRIPTION‡ 17 18 19 20 21 22 23 24 I/O Single-chip mode: Port A is a general-purpose bidirectional I/O port. Expansion mode: Port A can be individually programmed as the external bidirectional data bus (DATA0 – DATA7). 60 61 62 63 64 1 2 3 65 66 67 68 1 2 3 4 I/O Single-chip mode: Port B is a general-purpose bidirectional I/O port. Expansion mode: Port B can be individually programmed as the low-order address output bus (ADDR0 – ADDR7). ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 4 6 7 9 10 11 12 13 5 7 8 10 11 12 13 14 I/O Single-chip mode: Port C is a general-purpose bidirectional I/O port. Expansion mode: Port C can be individually programmed as the high-order address output bus (ADDR8 – ADDR15). INT1 INT2 INT3 NMI — — 50 49 48 52 51 50 I I/O I/O External (nonmaskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 E0 E1 E2 E3 E4 E5 E6 E7 14 34 35 36 37 38 39 42 36 37 38 39 40 41 42 43 I VCC3 VSS3 32 33 34 35 RESET 51 53 I/O MC 5 6 I Mode control (MC) pin. MC enables EEPROM write-protection override (WPO) mode, also EPROM VPP. XTAL2/CLKIN XTAL1 29 30 31 32 I O Internal oscillator crystal input / external clock source input Internal oscillator output for crystal 31, 57 33, 61 ALTERNATE FUNCTION SDIP (64) LCC (68) A0 A1 A2 A3 A4 A5 A6 A7 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 15 16 17 18 19 20 21 22 B0 B1 B2 B3 B4 B5 B6 B7 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 C0 C1 C2 C3 C4 C5 C6 C7 NAME VCC1 ADC1 analog input (AN0 – AN7) or positive reference pins (AN1 – AN7) Port E can be individually programmed as general-purpose input pins if not used as ADC1 analog input or positive reference input. ADC1 positive-supply voltage and optional positive-reference input pin ADC1 ground reference pin System reset bidirectional pin. RESET, as an input, initializes the microcontroller; as open-drain output, RESET indicates an internal failure was detected by the watchdog or oscillator fault circuit. Positive supply voltage VCC2 — 15,63 Positive supply voltage † I = input, O = output ‡ Ports A, B, C, and D can be configured only as general-purpose I/O pins. Also, port D3 can be configured as SYSCLK. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Pin Descriptions (Continued) PIN ALTERNATE FUNCTION SDIP (64) LCC (68) VSS1 8, 58,40 9 VSS2 — 16,62 NAME I/O† DESCRIPTION‡ Ground reference for digital logic Ground reference for digital I / O logic Single-chip mode: Port D is a general-purpose bidirectional I / O port. Each of the port D pins can be individually configured as a general-purpose I / O pin, primary memory control signal (function A), A) or secondary memory control signal (function B). All chip selects are independent and can be used for memory bank switching. Refer to Table 1 for function A memory accesses. FUNCTION A B D0 CSE2 OCF 59 64 I / O pin A: Chip select eighth output 2 goes low during memory accesses I / O pin B: Opcode fetch goes low during the opcode fetch memory cycle. D1 CSH3 — 56 60 I / O pin A: Chip select half output 3 goes low during memory accesses. I / O pin B: Reserved D2 CSH2 — — 59 I / O pin A: Chip select half output 2 goes low during memory accesses. I / O pin B: Reserved D3 SYSCLK SYSCLK 55 58 I / O pin A, B: Internal clock signal is 1 / 1 (PLL) or 1 / 4 XTAL2 / CLKIN frequency. D4 R/W R/W 54 57 D5 CSPF — — 56 I / O pin A: Chip select peripheral output for peripheral file goes low during memory accesses. I / O pin B: Reserved D6 CSH1 EDS 53 55 I / O pin A: Chip select half output 1 goes low during memory accesses. I / O pin B: External data strobe output goes low during memory accesses from external memory and has the same timings as the five chip selects. D7 CSE1 WAIT 52 54 I / O pin A: Chip select eighth output goes low during memory accesses. I / O pin B: Wait input pin extends bus signals. SCITXD SCIRXD SCICLK SCIIO1 SCIIO2 SCIIO3 28 27 26 30 29 28 T1IC / CR T1PWM T1EVT T1IO1 T1IO2 T1IO3 44 43 41 46 45 44 T2AIO1 T2AIO2 T2AIO3 25 24 23 27 26 25 T2AIC1 / CR T2AIC2 / PWM T2AEVT I/O I / O pin A, B: Read / write output pin I/O SCI transmit data output pin / general-purpose bidirectional pin (see Note 1) SCI receive data input pin / general-purpose bidirectional pin SCI bidirectional serial clock pin / general-purpose bidirectional pin I/O Timer1 input capture / counter reset input pin / general-purpose bidirectional pin Timer1 pulse-width-modulation (PWM) output pin / general-purpose bidirectional pin Timer1 external event input pin / general-purpose bidirectional pin I/O Timer2A input capture 1 / counter reset input pin / general-purpose bidirectional pin Timer2A input capture 2 / PWM output pin / general-purpose bidirectional pin Timer2A external event input pin / general-purpose bidirectional pin SPISOMI SPIIO1 47 49 SPI slave output pin, master input pin / general-purpose bidirectional pin SPISIMO SPIIO2 46 48 I / O SPI slave input pin, master output pin / general-purpose bidirectional pin SPICLK SPIIO3 45 47 SPI bidirectional serial clock pin / general-purpose bidirectional pin † I = input, O = output ‡ Ports A, B, C, and D can be configured only as general-purpose I/O pins. Port D3 also can be configured as SYSCLK. NOTE 1: The three-pin configuration SCI is referred to as SCI1. ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Table 1. Function A: Memory Accesses Locations for ‘x5x Devices FUNCTION A ‘X50, ‘X52, ‘X53, AND ‘X56 ‘X58 ‘X59 CSEx 2000h – 3FFFh (8K bytes) A000h – BFFFh (8K bytes) E000h – EFFFh (4K bytes) CSHx 8000h – FFFFh (32K bytes) C000h – FFFFh (16K bytes) F000h – FFFFh (4K bytes) CSPF 10C0h – 10FFh (64 bytes) 10C0h – 10FFh (64 bytes) 10C0h – 10FFh (64 bytes) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 functional block diagram INT1 INT2 INT3 XTAL1 XTAL2/ CLKIN Interrupts MC E0 – E7 or AN0 – AN7 RESET Clock Options: System Control Divide-by-4 or Divide-by-1(PLL) Analog-to-Digital Converter 1 VSS3 RAM 256, 512, 1K, 1.5K, or 3.5K Bytes CPU Program Memory ROM: 4K, 8K, 12K, 16K, 32K, or 48K Bytes EPROM: 16K, 32K, or 48K Bytes Data EEPROM 0, 256, or 512 Bytes Serial Peripheral Interface SPISOMI SPISIMO SPICLK Serial Communications Interface 1 SCIRXD SCITXD SCICLK Timer 2A T2AIC1 / CR T2AEVT T2AIC2 / PWM Timer 1 T1IC / CR T1EVT T1PWM Watchdog Control Address MSbyte Address LSbyte Memory Expansion Data VCC3 Port A Port B Port C Port D† 8 8 8 8/6 VCC1 VSS1 VSS2 VCC2 † For the 64-pin devices, there are only six pins for port D. description The TMS370Cx5x family of single-chip 8-bit microcontrollers provides cost-effective real-time system control through integration of advanced peripheral function modules and various on-chip memory configurations. The TMS370Cx5x family presently consists of twenty-one devices which are grouped into seven main sub-families: the TMS370Cx50, TMS370Cx52, TMS370Cx53, TMS370Cx56, TMS370Cx58, TMS370Cx59, and SE370C75x. The TMS370Cx5x family of devices is implemented using high-performance silicon-gate CMOS EPROM and EEPROM technologies. The low-operating power, wide-operating temperature range, and noise immunity of CMOS technology, coupled with the high performance and extensive on-chip peripheral functions, make the TMS370Cx5x devices attractive in system designs for automotive electronics, industrial motor control, computer peripheral control, telecommunications, and consumer application. Table 2 provides a memory configuration overview of the TMS370Cx5x devices. 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 description (continued) Table 2. Memory Configurations DEVICE PROGRAM MEMORY (BYTES) OFF-CHIP MEMORY EXP (BYTES) EXP. DATA MEMORY (BYTES) OPERATING MODES PACKAGES 68 PIN PLCC/CLCC, OR 64 PIN PSDIP/CSDIP ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ROM EPROM RAM EEPROM µC† µP† TMS370Cx50: TMS370C050, TMS370C150, TMS370C250, AND TMS370C350 256 √ √ FN – PLCC / NM –PSDIP 256 — — √ FN – PLCC 256 256 — √ FN – PLCC 256 — √ √ FN – PLCC / NM –PSDIP TMS370C050A 4K — 112K 256 TMS370C150A — — 56K TMS370C250A — — 56K TMS370C350A 4K — 112K TMS370C052A 8K — 112K 256 TMS370C352A TMS370C452A‡ 8K — 112K 8K — 112K TMS370Cx52: TMS370C052, TMS370C352, AND TMS370C452 256 √ √ FN – PLCC / NM –PSDIP 256 — √ √ FN – PLCC / NM –PSDIP 256 256 √ √ FN – PLCC √ √ FN – PLCC TMS370Cx53: TMS370C353 TMS370C353A 12K — 112K 1.5K — TMS370Cx56: TMS370C056, TMS370C156, TMS370C256, TMS370C356, TMS370C456, AND TMS370C756 512 √ √ FN – PLCC / NM –PSDIP 512 — — √ FN – PLCC 512 512 — √ FN – PLCC 512 — √ √ FN – PLCC / NM –PSDIP 512 512 √ √ FN – PLCC 512 512 √ √ FN – PLCC / NM –PSDIP TMS370C056A 16K — 112K 512 TMS370C156A — — 56K TMS370C256A — — 56K TMS370C356A TMS370C456A‡ 16K — 112K 16K — 112K TMS370C756A — 16K 112K TMS370C058A 32K — 64K 1K 256 √ √ FN – PLCC / NM –PSDIP TMS370C358A 32K — 64K 1K — √ √ FN – PLCC / NM –PSDIP TMS370C758A, TMS370C758B — 32K 64K 1K 256 √ √ FN – PLCC / NM –PSDIP 48K — 20K 3.5K 256 √ √ FN – PLCC 48K 20K 3.5K 256 √ √ FN – PLCC TMS370Cx58: TMS370C058, TMS370C358, AND TMS370C758 TMS370Cx59: TMS370C059 AND TMS370C759 TMS370C059A§ TMS370C759A§ — EPROM DEVICE: SE370C756, SE370C758, and SE370C759 SE370C756A¶ SE370C758A¶, SE370C758B¶ — 16K 112K 512 512 √ √ FZ – CLCC / JN –CSDIP — 32K 64K 1K 256 √ √ FZ – CLCC / JN –CSDIP SE370C759A§¶ — 48K 20K 3.5K 256 √ √ FZ – CLCC † µC – Microcomputer mode µP – Microprocessor mode ‡ TMS370C45x support ROM memory security. Refer to the program ROM section. § Only operate up to 3 MHz SYSCLK ¶ System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 description (continued) The suffix letter (A or B) appended to the device names shown in the device column of Table 2 indicates the configuration of the device. ROM or an EPROM devices have different configurations as indicated in Table 3. ROM devices with the suffix letter A are configured through a programmable contact during manufacture. Table 3. Suffix Letter Configuration DEVICE† WATCHDOG TIMER CLOCK LOW-POWER MODE EPROM A Standard Divide-by-4 (Standard oscillator) Enabled EPROM B Hard Divide-by-1 (PLL) Enabled Divide-by-4 or Divide-by-1 (PLL) Enabled or disabled Divide-by-4 Enabled Standard ROM A Hard Simple ROM-less A Standard † Refer to the “device numbering conventions” section for device nomenclature and the “device part numbers” section for ordering. Unless otherwise noted, the terms TMS370Cx50, TMS370Cx52, TMS370Cx53, TMS370Cx56, TMS370Cx58, TMS370Cx59, and SE370C75x refer to the individual devices listed in Table 2 and described in this data sheet. All TMS370Cx5x devices contain the following on-chip peripheral modules: D D D D D Eight-channel, 8-bit analog-to-digital converter 1 (ADC1) Serial communications interface 1 (SCI1) Serial peripheral interface (SPI) One 24-bit general-purpose watchdog timer Two 16-bit general-purpose timers (one with an 8-bit prescaler) TMS370C756, TMS370C758, and TMS370C759 are one-time programmable (OTP) devices that are available in plastic packages. This microcomputer is effective to use for immediate production updates for other members of the TMS370Cx5x family or for low-volume production runs when the mask charge or cycle time for low-cost mask ROM devices is not practical. The SE370C756, SE370C758, and SE370C759 have windowed ceramic packages to allow reprogramming of the program EPROM memory during the development / prototyping phase of design. The SE370C75x devices allow quick updates to breadboards and prototype systems while iterating initial designs. The TMS370Cx5x family provides two low-power modes (STANDBY and HALT) for applications where low-power consumption is critical. Both modes stop all central processing unit (CPU) activity (that is, no instructions are executed). In the STANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HALT mode, all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both low-power modes. The TMS370Cx5x features advanced register-to-register architecture that allows direct arithmetic and logical operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to the contents of register 47 and store the result in register 47). The TMS370Cx5x family is fully instruction-set-compatible, allowing easy transition between members of the TMS370 8-bit microcontroller family. The SPI and the two operational modes of the SCI1 give three methods of serial communications. The SCI1 allows standard RS-232-C communications interface between other common data transmission equipment, while the SPI gives high-speed communications between simpler shift-register type devices, such as display drivers, ADC1 converter, phase-locked loop (PLL), I/O expansion, or other microcontrollers in the system. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 description (continued) For large memory applications, the TMS370Cx5x family provides an external bus with non-multiplexed address and data. Precoded memory chip-select outputs can be enabled, which allows minimum-chip-count system implementations. Wait-state support facilitates performance matching among the CPU, external memory, and the peripherals. All pins associated with memory expansion interface are individually software configurable for general purpose digital input/output (I / O) pins when operating in the microcomputer mode. The TMS370Cx5x family provides the system designer with very economical, efficient solution to real-time control applications. The TMS370 family extended development system (XDS) and compact development tool (CDT) solve the challenge of efficiently developing the software and hardware required to design the TMS370Cx5x into an ever-increasing number of complex applications. The application source code can be written in assembly and C-language, and the output code can be generated by the linker. The TMS370 family XDS development tools communicate through a standard RS-232-C interface with an existing personal computer. This allows the use of the personal computer editors and software utilities already familiar to the designer. The TMS370 family XDS emphasizes ease-of-use through extensive use of menus and screen windowing so that a system designer with minimal training can begin developing software. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as reduced time-to-market cycle. The TMS370Cx5x family together with the TMS370 family XDS/22, CDT370, design kit, starter kit, software tools, the SE370C75x reprogrammable devices, comprehensive product documentation, and customer support provide a complete solution to the needs of the system designer. modes The TMS370Cx5x has four operating modes, two basic modes with each mode having two memory configurations. The basic operating modes are the microcomputer and microprocessor modes, which are selected by the voltage level applied to the dedicated MC pin two cycles before RESET goes inactive. The two memory configurations then are selected through software programming of the internal system configuration registers. The four operating modes are the microcomputer single chip, microcomputer with external expansion, microprocessor without internal program memory, and microprocessor with internal program memory. These modes are described in the following list. D D Microcomputer single chip mode: – Operates as a self-contained microcomputer with all memory and peripherals on-chip. – Maximizes the general-purpose I/O capability for real-time control applications. Microcomputer with external expansion mode: – Supports bus expansion to external memory or peripherals, while all on-chip memory (RAM, ROM, EPROM, and data EEPROM) remains active. – Configures digital I/O ports (ports A, B, C, and D) through software, under control of the associated port control, to become external memory as follows: – Port A: 8-bit data memory – Port B and C: 16-bit address memory – Port D: 8-bit control memory (pin not used as function A or B can be configured as I/O) – Utilizes the pins available (not used for address, data, or control memory) as general-purpose input/output by programming them individually. – Lowers the system cost by not requiring an external address/data latch (address memory and data memory are nonmultiplexed). XDS and CDT are trademarks of Texas Instruments Incorporated. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 modes (continued) D D – Reduces external interface decode logic by using the precoded chip select outputs that provide direct memory/peripheral chip select or chip enable functions. – Function A maps up to 112K bytes of external memory into the address space by using CSE1, CSE2, CSH1, CSH2, and CSH3 as memory-bank selects under software control. – Function B maps up to 40K bytes of external memory into the address space by using EDS under software control. Microprocessor without internal program memory mode: – Ports A, B, C, and D (these ports are not programmable) become the address, data, and control buses for interface to external memory and peripherals. – On-chip RAM and data EEPROM remain active, while the on-chip ROM or EPROM is disabled. – Program area and the reset, interrupt, and trap vectors are located in off-chip memory locations. Microprocessor with internal program memory mode: – Configured as the microprocessor without internal program memory mode with respect to the external bus interface. – Application program in external memory enables the internal program ROM or EPROM to be active in the system. (Writing a zero to the MEMORY DISABLED control bit (SCCR1.2) of the SCCR1 control register accomplishes this.) memory/peripheral wait operation The TMS370Cx5x enhances interface flexibility by providing WAIT-state support, decoupling the cycle time of the CPU from the read/write access of the external memory or peripherals. External devices can extend the read/write accesses indefinitely by placing an active low on the WAIT-input pin. The CPU continues to wait as long as WAIT remains active. Programmable automatic wait-state generation also is provided by the TMS370Cx5x on-chip bus controller. Following a hardware reset, the TMS370Cx5x is configured to add one wait state to all external bus transactions and memory and peripheral accesses automatically, thus making every external access a minimum of three system-clock cycles. The designer can disable the automatic wait-state generation if the AUTOWAIT DISABLE bit in SCCR1 is set to 1. Also, all accesses to the upper four frames of the peripheral file can be extended independently to four system clock cycles if the PF AUTO WAIT bit in SCCR0 is set to one. Programmable wait states can be used in conjunction with the external WAIT pin. In applications where the external device read/write access can interface with the TMS370Cx5x CPU using one wait state, the automatic wait-state generation can eliminate external WAIT interface logic, lowering system cost. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 CPU The CPU used on TMS370Cx5x devices is the high-performance 8-bit TMS370 CPU module. The ’x5x implements an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete ’x5x instruction set is summarized in Table 23. Figure 1 illustrates the CPU registers and memory blocks. Program Counter 15 Stack Pointer (SP) 7 0 Legend: C=Carry N=Negative Z=Zero 0 Status Register (ST) C N Z V 7 6 5 4 IE2 IE1 3 2 1 V=Overflow IE2=Level2 interrupts Enable IE1=Level1 interrupts Enable 0 256-Byte RAM (0000h – 00FFh) 512-Byte RAM (0000h – 01FFh) 1K-Byte RAM (0000h – 03FFh) 1.5K-Byte RAM (0000h – 05FFh) 3.5K-Byte RAM (0000h – 0DFFh) Reserved† Peripheral File Peripheral Exp Reserved† RAM (Includes 256-Byte Registers File) 0000h R0(A) 0001h R1(B) 0002h R2 0003h R3 512-Byte (1E00h – 1FFFh) Data EEPROM 0100h 0200h 0400h 0600h 0E00h 1000h 10C0h 1100h 1E00h 1F00h 256-Byte (1F00h – 1FFFh) 2000h 16K-Byte ROM / EPROM (4000h – 7FFFh) 12K-Byte ROM (5000h – 7FFFh) 8K-Byte ROM (6000h – 7FFFh) 007Fh 0000h R127 4K-Byte ROM (7000h – 7FFFh) Interrupts and Reset Vectors; Trap Vectors 32K-Byte ROM / EPROM (2000h – 9FFFh) 48K-Byte ROM / EPROM (2000h – DFFFh) R255 Memory Expansion 00FFh 4000h 5000h 6000h 7000h 7FC0h 8000h A000h E000h FFFFh † Reserved means the address space is reserved for future expansion. Figure 1. Programmer’s Model POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 CPU (continued) The ’x5x CPU architecture provides the following components: D D CPU registers: – A stack pointer that points to the last entry in the memory stack – A status register that monitors the operation of the instructions and contains the global-interrupt-enable bits – A program counter (PC) that points to the memory location of the next instruction to be executed A memory map that includes : – 256-, 512-, 1K-, 1.5K-, or 3.5K-byte general-purpose RAM that can be used for data-memory storage, program instructions, general-purpose register, or the stack (can be located only in the first 256 bytes) – A peripheral file that provides access to all internal peripheral modules, system-wide control functions, and EEPROM/EPROM programming control – 256- or 512-byte EEPROM module that provides in-circuit programmability and data retention in power-off conditions – 4K-, 8K-, 12K-, 16K-, 32K-, or 48K-byte ROM or 16K-, 32K-, or 48K-byte EPROM program memory stack pointer (SP) The SP is an 8-bit CPU register. The stack operates as a last-in, first-out, read/write memory. Typically the stack is used to store the return address on subroutine calls as well as the status-register contents during interrupt sequences. The SP points to the last entry or to the top of the stack. The SP increments automatically before data is pushed onto the stack and decrements after data is popped from the stack. The stack can be located only in the first 256 bytes of the on-chip RAM memory. status register (ST) The ST monitors the operation of the instructions and contains the global-interrupt-enable bits. The ST includes four status bits (condition flags) and two interrupt-enable bits: D D The four status bits indicate the outcome of the previous instruction; conditional instructions (for example, the conditional-jump instructions) use these status bits to determine program flow. The two interrupt-enable bits control the two interrupt levels. The ST register, status bit notation, and status bit definitions are shown in Table 4. ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ Table 4. Status Registers 7 6 5 4 3 2 1 0 C N Z V IE2 IE1 Reserved Reserved RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R = read, W = write, 0 = value after reset 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 CPU (continued) program counter (PC) The contents of the PC point to the memory location of the next instruction to be executed. The PC consists of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These registers contain the most-significant byte (MSbyte) and least-significant byte (LSbyte) of a 16-bit address. The contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter during reset. The PCH (MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 6000h as the contents of memory locations 7FFEh and 7FFFh (reset vector). Program Counter (PC) Memory 0000h 7FFEh 60 7FFFh 00 PCH PCL 60 00 Figure 2. Program Counter After Reset memory map The TMS370Cx5x architecture is based on the Von Neuman architecture, where the program memory and data memory share a common address space. All peripheral input/output is memory mapped in this same common address space. In the expansion mode, external memory peripherals are also memory-mapped into this common address. As shown in Figure 3, the TMS370Cx5x provides a 16 bit-address range to access internal or external RAM, ROM, data EEPROM, EPROM input/output pins, peripheral functions, and system-interrupt vectors. The peripheral file contains all input/output port control, on- and off-chip peripheral status and control, EPROM, EEPROM programming, and system-wide control functions. The peripheral file consists of 256 contiguous addresses located from 1000h to 10FFh. The 256 contiguous addresses are divided logically into 16 peripheral file frames of 16 bytes each. Each on-chip peripheral is assigned to a separate frame through which peripheral control and data information is passed. The TMS370Cx5x has its on-chip peripherals and system control assigned to peripheral file frames 1 through 7, addresses 1010h through 107Fh. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 memory map (continued) ÜÚÚ ÛÛ ÙŠŠ ÒÒ ÜÜ ÛÙÙ ÚÚ ŠÜÜ ÒÒ ÛÛ ÚÙÙ ŠÒÒÜÛÛ ÚÙÙ ŠŠ Ò ÛÛ Ü ÚÚ ÙŠŠ ÒÒ ÜÜ ÛÙÙ ÚÚ ŠÜÜ ÒÒ ÛÛ ÚÙÙ ŠÒÒÜÛÛ ÚÙÙ ŠŠ Ò ÛÛ Ü ÚÚ Ù ÜÜ ÛÙÙÜÜ ÚÚ ÛÛ ÚÙÙ ÜÛÛ ÚÙÙ ÛÛÙ ÜÜ Ü ÛÙÙÜÜ ÛÛ ÙÙ ÜÛÛ ÙÙ Ü Ù ÜÜÙÙÜÜÙÙ ÜÙÙ Ü Ù ÜÜÙÙÜÜÙÙ ÜÙÙ Ü ÜÜ ÜÜ Ü ÜÚÚ ÛÛ ÙÒÒ ŠŠ ÜÜ ÛÙÙ ÚÚ ŠÒÒ ÜÜ ÛÛ ÚŠÒÒÛÛ ÙÙ ÜÙÙ ÚŠŠ Ò ÜÚÚ ÛÛ ÙÒÒ ŠŠ ÜÜ ÛÙÙ ÚÚ ŠÒÒ ÜÜ ÛÛ ÚŠÒÒÛÛ ÙÙ ÜÙÙ ÚŠŠ Ò ’X59 ’X56 ’X52 ’X50 ’X58 ’X53 ’X59 ’X56 ’X52 ’X50 ’X58 ’X53 ’X59 ’X56 ’X52 ’X50 ’X58 ’X53 0000h 0100h 0100h 0200h 0200h 0400h 0400h 0600h 0600h 0E00h Reserved† Reserved† Reserved† Peripheral File Control Registers ’X59 ’X56 ’X52 ’X50 ’X58 ’X53 0000h Reserved† 1000h 0E00h 256-Byte RAM (0000h–00FFh) (Register File/Stack) 512-Byte RAM (0000h–01FFh) 1K-Byte RAM (0000h–03FFh) Reserved† 1000h–100Fh System Control 1010h–101Fh Digital Port Control 1020h–102Fh 1.5K-Byte RAM (0000h–05FFh) SPI Peripheral Control 1030h–103Fh 3.5K-Byte RAM (0000h–0DFFh) Timer 1 Peripheral Control 1040h–104Fh Reserved† SCI1 Peripheral Control 1050h–105Fh 1000h Timer 2A Peripheral 1060h–106Fh Control Peripheral File 10C0h Not Available‡ (N / A) External§ External External 1100h ÚÚ ÚÚ Ú Ú ÚÚ ÚÚ Ú Ú ÛÛ Ü ŠŠ ÒÒ ÜÜ Û ŠÒÒ ÜÜ ÛÛ ŠÒÒÜÛÛ ŠŠ Ò ÚÚ ÚÚ Ú Ú ÛÛ Ü ŠŠ ÒÒ ÜÜ Û ŠÒÒ ÜÜ ÛÛ ŠÒÒÜÛÛ ŠŠ Ò ÚÚ ÚÚ Ú Ú ÛÛ Ü ŠŠ ÒÒ ÜÜ ÛÚÚŠÒÒ ÜÜ ÛÛ Ò ÚÚ ÚÚ ÚÚŠÒÒÜÛÛ ÚŠŠ ÚÚ ÛÛ Ü ÜÜ Û ÜÜ ÛÛ Ù ÜÜ ÙÙÜÜ ÙÙ ÚÚ ÚÚ Ú ÛÛ Ü Û ÛÛ ÙŠŠÜÜ ÙÙ ÙÙ ÚÚ ÚÚ Ú ÛÛ Ü Û ÜÜ ÛÛ Š Š ÙŠŠ ÙÙ ÙÙ ÚÚ ÚÚ Ú ÛÛ Ü ÜÜ Û ÜÜ ÛÛ ÒÒ ÒÒ ÒÒ Š Š ÙŠŠ ÙÙ ÙÙ ÚÚ ÚÚ Ú ÛÛ Ü ÜÜ Û ÜÜ ÛÛ ÒÒ ÒÒ ŠÒÒ ŠÒÒ ÙŠŠ ÙÙ ÙÙ ÚÚ ÚÚ Ú ÛÛ Ü ÜÜ Û ÜÜ ÛÛ ÒÒ ÒÒ Š ŠÒÒ ÙŠŠ ÙÙ ÙÙ ÚÚ ÚÚ Ú ÛÛ Ü ÜÜ Û ÜÜ ÛÛ ÒÒ ÒÒ Š Š ÙŠŠ ÙÙ ÙÙ ÚÚ ÚÚ Ú ÛÛ Ü ÜÜ Û ÜÜ ÛÛ ÒÒ ŠÜÜ ŠÒÒ ÙÒÒ ÚÚ ÚÚ ÚÙÙ ÛÛ Ü ÜÜ ÛÙÙ ÛÛ ÛÛ ÜÜ Ü Û ÜÜ ÛÛ Ü ÜÜ ÜÜ Ü ÜÜ ÜÜ Ü ÜÜ ÜÜ Reserved† Reserved† Reserved† 10C0h 1100h Reserved† Reserved† 1E00h 1E00h 1F00h 1F00h 2000h External§ 4000h N / A‡ N / A‡ Peripheral Expansion 256-Byte Data EEPROM (1F00h–1FFFh) 4000h 5000h 5000h 6000h 6000h 7000h 7000h External§ Vectors Trap 15–0 7FC0h–7FDFh 16K-Byte ROM (4000h–7FFFh) Reserved† 7FE0h–7FFBh 12K-Byte ROM (5000h–7FFFh) FFFFh ADC1 7FECh–7FEDh 8K-Byte ROM (6000h–7FFFh) Timer 2A 7FEEh–7FEFh 4K-Byte ROM (7000h–7FFFh) Serial Comm I/F TX 7FF0h–7FF1h Interrupts and Reset Vectors; Trap Vectors Timer 1 32K-Byte ROM (2000h–9FFFh) ÜÜ ÛÛ Microcomputer Mode With External Expansion On-Chip For TMS370Cx59 Devices On-Chip For TMS370Cx58 Devices Microprocessor With Internal Program Memory 7FF4h–7FF5h Serial Peripheral I/F 7FF6h–7FF7h A000h 48K-Byte ROM (2000h–DFFFh) E000h Interrupt 3 7FF8h–7FF9h Interrupt 2 7FFAh–7FFBh Interrupt 1 7FFCh–7FFDh Reset 7FFEh–7FFFh Memory Expansion FFFFh Microcomputer Single Chip Mode Serial Comm I/F RX 7FF2h–7FF3h 8000h External E000h 1080h–108Fh 7FC0h External Not Available‡ Reserved† 2000h N / A‡ A000h 1070h–107Fh 512K-Byte Data EEPROM (1E00h–1FFFh) External 8000h ADC1 Peripheral Control Microprocessor Mode¶ ÚÚ ÙÙ On-Chip For TMS370Cx56 Devices On-Chip For TMS370Cx53 Devices ŠŠ ÒÒ On-Chip For TMS370Cx52 Devices On-Chip For TMS370Cx50 Devices † Reserved = the address space is reserved for future expansion. ‡ Not available (N /A) = address space unavailable in the mode illustrated. § Precoded chip select outputs available on external expansion bus. ¶ Microprocessor mode is designed for ROM-less devices (’x50 and ’x56). ROM and EPROM devices can also be used in this mode but all on-chip memory is ignored. Figure 3. TMS370Cx5x Memory Map 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 RAM/register file (RF) Locations within RAM address space can serve as either register file or general-purpose read/write memory, program memory, or stack instructions. The TMS370Cx50 and TMS370Cx52 devices contain 256 bytes of internal RAM, mapped beginning at location 0000h and continuing through location 00FFh which is shown in Table 5 along with other ’x5x devices. ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Table 5. RAM Memory Map ‘x50 and ‘x52 ‘x56 ‘x58 ‘x53 ‘x59 RAM Size 256 Bytes 512 Bytes 1K Bytes 1.5K Bytes 3.5K Bytes Memory Mapped 0000h – 00FFh 0000h – 01FFh 0000h – 03FFh 0000h – 05FFh 0000h – 0DFFh The first 256 bytes of RAM (0000h – 00FFh) are register files, R0 through R255 (see Figure 1). The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the stack pointer is contained in register B. Registers A and B are the only registers cleared on reset. peripheral file (PF) The TMS370Cx5x control registers contain all the registers necessary to operate the system and peripheral modules on the device. The instruction set includes some instructions that access the PF directly. These instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal designator or by P for a decimal designator. For example, the system control register 0 (SCCR0) is located at address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 6 shows the TMS370Cx5x peripheral files. ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 6. TMS370Cx5x Peripheral File Address map ADDRESS RANGE PERIPHERAL FILE DESIGNATOR 1000h – 100Fh P000 – P00F Reserved for factory test 1010h – 101Fh P010 – P01F System and EEPROM/EPROM control registers 1020h – 102Fh P020 – P02F Digital I/O port control registers 1030h – 103Fh P030 – P03F Serial peripheral interface registers 1040h – 104Fh P040 – P04F Timer 1 registers 1050h – 105Fh P050 – P05F Serial communication interface 1 registers 1060h – 106Fh P060 – P06F Timer 2A registers DESCRIPTION 1070h – 107Fh P070 – P07F Analog-to-digital converter 1 registers 1080h – 10BFh P080 – P0BF Reserved 10C0h – 10FFh P0C0 – P0FF External peripheral control data EEPROM The TMS370Cx56 devices contain 512 bytes of data EEPROM, which are memory mapped beginning at location 1E00h and continuing through location 1FFFh as shown in Table 7 along with other ‘x5x devices. Table 7. Data-EEPROM Memory Map ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ‘x50, ‘x52, ‘x58, and ‘x59 ‘x56 ‘X53 Data-EEPROM Size 256 Bytes 512 Bytes None Memory Mapped 1F00h – 1FFFh 1E00h – 1FFFh None POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 data EEPROM (continued) Writing to the data EEPROM module is controlled by the data EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm examples are available in the TMS370 Family User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B). The data EEPROM features include the following: D D D Programming: – Bit, byte, and block write/erase modes – Internal charge pump circuitry. No external EEPROM programming voltage supply is needed. – Control register: Data EEPROM programming is controlled by the data EEPROM control register (DEECTL) located in the PF frame beginning at location P01A. – In-circuit programming capability: There is no need to remove the device to program it. Write-protection: Writes to the data EEPROM are disabled during the following conditions: – Reset: All programming of the data EEPROM module is halted. – Write protection active: There is one write-protect bit per 32-byte EEPROM block. – Low-power mode operation Write protection can be overridden by applying 12 V to MC. Table 8 shows the memory map of the control registers. ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 8. Data EEPROM and Program EPROM Control Registers Memory Map ADDRESS SYMBOL P014 EPCTLH P015 – P016 NAME Program EPROM control register – high array Reserved P017 INT1 External interrupt 1 control register P018 INT2 External interrupt 2 control register P019 INT3 External interrupt 3 control register P01A DEECTL P01B P01C Reserved EPCTLM P01D P01E Data EEPROM control register Program EPROM control register – middle array Reserved EPCTLL Program EPROM control register – low array For the 16K-byte EPROM device, program memory is controlled by P01C; for the 32K-byte EPROM device, the program memory is controlled by P01C and P01E; for the 48K-byte EPROM device, the program memory is controlled by P014, P01C, and P01E. program EPROM The ‘370C756 consists of a 16K-byte array of EPROM at address locations 4000h through 7FFFh. The ‘370C758 consists of 32K bytes made up of two 16K-byte arrays of EPROM; the first 16K-bytes array is located at address locations 2000h through 5FFFh, and the second 16K byte array is located at address locations 6000h through 9FFFh. The ’370C759 consists of 48K bytes that is made up of three 16K byte arrays of EPROM; the first 16K bytes array is located at address locations 2000h through 5FFFh, the second 16K-byte array is located at address locations 6000h through 9FFFh, the third 16K-byte array is located at address locations A000h through DFFFh (see Figure 3). 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 program EPROM (continued) The EPROM memory map in Table 9 expresses the following: D D D The programming control register for program EPROM (EPCTLM) for 16K-byte EPROM is located at address 101Ch (P01C). For the 32K-byte EPROM, the first 16K-byte array is controlled by EPCTLL, located at 101Eh (P01E); the second 16K-byte array is controlled by EPCTLM, located at 101Ch (P01C). For the 48K-byte EPROM, the first 16K-byte array is controlled by EPCTLL, located at 101Eh (P01E); the second 16K-byte array is controlled by EPCTLM, located at 101Ch (P01C); the third 16K-byte array is controlled by EPCTLH, located at 1014h (P014). ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ Table 9. EPROM Memory Map EPROM size ’756 ’758 ’759 16K Bytes 32K Bytes 48K Bytes Memory Mapped 16K 4000h – 7FFFh First 16K 2000h – 5FFFh Second 16K 6000h – 9FFFh First 16K 2000h – 5FFFh Second 16K 6000h – 9FFFh Third 16K A000h – DFFFh Contol Registers EPCTLM P01C EPCTLL P01E EPCTLM P01C EPCTLL P01E EPCTLM P01C EPCTLH P014 Reading the program-EPROM modules is identical to reading other internal memory. During programming, the EPROM is controlled by the EPCTL. The program EPROM modules’ features include: D D Programming – In-circuit programming capability if VPP is applied to MC – Control register: Program EPROM programming is controlled by the program EPROM control registers (EPCTLL, EPCTLM, and EPCTLH) located in the PF frame as shown in Table 8. – Programming one EPROM module while executing the other Write protection: Writes to the program EPROM are disabled under the following conditions: – Reset: All programming to the EPROM module is halted. – Low-power modes – 13 V not applied to MC program ROM The program ROM consists of 4K to 48K bytes of mask-programmable ROM. The program ROM is used for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device fabrication. ROM security is a feature of the ‘45x devices, which inhibits reading of the data using the programmer. ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ Table 10. ROM Memory Map† ‘x50 ‘x52 ‘x53 ‘x56 ‘x58 ‘x59 ROM Size 4K Bytes 8K Bytes 12K Bytes 16K Bytes 32K Bytes 48K Bytes Memory Mapped 7000h – 7FFFh 6000h – 7FFFh 5000h – 7FFFh 4000h – 7FFFh 3000h – 9FFFh 2000h – DFFFh † Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments (TI), and addresses 7FECh through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions are located between addresses 7FC0h and 7FDFh. TI is a trademark of Texas Instruments Incorporated. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 system reset The system-reset operation ensures an orderly start-up sequence for the TMS370Cx5x CPU-based device. There are up to three different actions that can cause a system reset to the device. Two of these actions are internally generated, while one (RESET) is controlled externally. These actions are as follows: D D D Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key register, or if the re-initialization does not occur before the watchdog timer timeout . See the TMS370 User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B) for more information. Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See the TMS370 User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B) for more information. External RESET Pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the TMS370 User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B) for more information. Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK cycles. This allows the ’x5x device to reset external system components. Additionally, if a cold-start condition (VCC is off for several hundred milliseconds) occurs, oscillator failure occurs, or RESET pin is held low, then the reset logic holds the device in a reset state for as long as these actions are active. After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag (COLD START, SCCR0.7), and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source of the reset. A reset does not clear these flags. Table 11 lists the reset sources. ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Table 11. Reset Sources REGISTER ADDRESS PF BIT NO. CONTROL BIT SOURCE OF RESET SCCR0 1010h P010 7 COLD START Cold (power-up) SCCR0 1010h P010 4 OSC FLT FLAG Oscillator out of range T1CTL2 104Ah P04A 5 WD OVRFL INT FLAG Watchdog timer timeout Once a reset is activated, the following sequence of events occurs: 1. The CPU registers initialize: ST = 00h, SP = 01h (reset state). 2. Registers A and B initialize to 00h (no other RAM is changed). 3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL. 4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH. 5. Program execution begins with an opcode fetch from the address pointed to by the PC. The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control register bits are initialized to their reset state. During RESET, the two basic operating modes which are the microcomputer and microprocessor modes can be selected by applying the desired voltage level to the dedicated MC pin two cycles before RESET goes inactive (refer to page 7 for operating modes description). 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 interrupts The TMS370 family software-programmable interrupt structure permits flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt level 2. The two priority levels can be masked independently by the global interrupt mask bits (IE1 and IE2) of the status register. Each system interrupt is configured independently to either the high- or low-priority chain by the application program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of the system interrupt. However, since each system interrupt is configured selectively on either the high- or low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority. Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions. The TMS370Cx5x has nine hardware system interrupts (plus RESET) as shown in Table 12. Each system interrupt has a dedicated vector located in program memory through which control is passed to the interrupt service routines. A system interrupt can have multiple interrupt sources (e.g., SCI RXINT has two interrupt sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in the associated PF. Each interrupt source FLAG bit is individually readable for software polling or determining which interrupt source generated the associated system interrupt. Interrupt control block diagram is illustrated in Figure 4. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 interrupts (continued) EXT INT 3 INT 3 EXT INT 2 TIMER 2A INT 2 TIMER 1 INT3 PRI Overflow Overflow Compare1 Compare1 Ext Edge Ext Edge Compare2 Compare2 INT2 PRI EXT INT1 CPU INT1 Input Capture 1 Input Capture 1 Input Capture 2 Watchdog T2A PRI NMI T1 PRI INT1 PRI Priority Logic STATUS REG IE1 Level 1 INT IE2 Level 2 INT AD INT AD PRI SCI INT TX TXPRI TXRDY A/D SPI INT RX Enable SPI PRI RXPRI BRKDT RXRDY SPI Figure 4. Interrupt Control On-chip peripheral functions generate six of the system interrupts. Three external interrupts also are supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3 control registers in PF frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or non-maskable interrupt. When INT1 is configured as nonmaskable, it cannot be masked by the individual- or global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupts INT2 and INT3 can be software configured as general purpose input/output pins if the interrupt function is not required (INT1 can be similarly configured as an input pin). Table 12 shows the interrupt vector sources, corresponding addresses, and hardware priorities. 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 interrupts (continued) ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ Table 12. Hardware System Interrupts INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT VECTOR ADDRESS PRIORITY† RESET‡ 7FFEh, 7FFFh 1 7FFCh, 7FFDh 2 External RESET Watchdog overflow Oscillator fault detect COLD START WD OVRFL INT FLAG OSC FLT FLAG External INT1 INT1 FLAG External INT2 INT2 FLAG INT1‡ INT2‡ 7FFAh, 7FFBh 3 External INT3 INT3 FLAG INT3‡ 7FF8h, 7FF9h 4 SPI RX/TX complete SPI INT FLAG SPIINT 7FF6h, 7FF7h 5 Timer 1 overflow Timer 1 compare 1 Timer 1 compare 2 Timer 1 external edge Timer 1 input capture 1 Watchdog overflow T1 OVRFL INT FLAG T1C1 INT FLAG T1C2 INT FLAG T1EDGE INT FLAG T1IC1 INT FLAG WD OVRFL INT FLAG T1INT§ 7FF4h, 7FF5h 6 SCI RX data register full SCI RX break detect RXRDY FLAG BRKDT FLAG RXINT‡ 7FF2h,7FF3h 7 SCI TX data register empty TXRDY FLAG TXINT 7FF0h, 7FF1h 8 Timer 2A overflow Timer 2A compare 1 Timer 2A compare 2 Timer 2A external edge Timer 2A input capture 1 Timer 2A input capture 2 T2A OVRFL INT FLAG T2AC1 INT FLAG T2AC2 INT FLAG T2AEDGE INT FLAG T2AIC1 INT FLAG T2AIC2 INT FLAG T2AINT 7FEEh, 7FEFh 9 ADINT 7FECh, 7FEDh 10 A/D conversion complete AD INT FLAG † Relative priority within an interrupt level ‡ Releases microcontroller from STANDBY and HALT low-power modes. § Releases microcontroller from STANDBY low-power mode. privileged operation and EEPROM write-protection override The TMS370Cx5x family has significant flexibility to enable the designer to software-configure the system and peripherals to meet the requirements of a broad variety of applications. The nonprivileged mode of operation ensures the integrity of the system configuration, once it is defined for an application. Following a hardware reset, the TMS370Cx5x operates in the privileged mode, where all peripheral file registers have unrestricted read/write access, and the application program configures the system during the initialization sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) should be set to 1 to enter the nonprivileged mode; disabling write operations to specific configuration control bits within the peripheral file. Table 13 displays the system configuration bits that are write-protected during the nonprivileged mode and must be configured by software prior to exiting the privileged mode. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 privileged operation and EEPROM write-protection override (continued) ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Table 13. Privileged Bits REGISTER† CONTROL BIT NAME LOCATION SCCRO P010.5 P010.6 PF AUTOWAIT OSC POWER SCCR1 P011.2 P011.4 MEMORY DISABLE AUTOWAIT DISABLE SCCR2 P012.0 P012.1 P012.3 P012.4 P012.6 P012.7 PRIVILEGE DISABLE INT1 NMI CPU STEST BUS STEST PWRDWN/IDLE HALT/STANDBY SPIPRI P03F.5 P03F.6 P03F.7 SPI ESPEN SPI PRIORITY SPI STEST SCIPRI P05F.4 P05F.5 P05F.6 P05F.7 SCI ESPEN SCIRX PRIORITY SCITX PRIORITY SCI STEST T1PRI P04F.6 P04F.7 T1 PRIORITY T1 STEST T2APRI P06F.6 P06F.7 T2A PRIORITY T2A STEST ADPRI P07F.5 P07F.6 P07F.7 AD ESPEN AD PRIORITY AD STEST † The privileged bits are shown in a bold typeface in Table 15. The write-protect override (WPO) mode provides an external hardware method for overriding the write-protection registers of data EEPROM on the TMS370Cx5x. The WPO mode is entered by applying a 12-V input to MC after RESET input goes high (logic 1). The high voltage on MC during the WPO mode is not the programming voltage for the data EEPROM or Program EPROM. All EEPROM programming voltages are generated on-chip. The WPO mode provides hardware system-level capability to modify the content of the data EEPROM while the device remains in the application, but only while requiring a 12-V external input on the MC pin (normally not available in the end application except in a service or diagnostic environment). low-power and IDLE modes The TMS370Cx5x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the time when the mask is manufactured. The STANDBY and HALT low power modes significantly reduce power consumption by reducing or stopping the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The HALT / STANDBY bit in SCCR2 controls which low-power mode is entered. In the STANDBY mode (HALT/STANDBY = 0), all CPU activity and most peripheral module activity is stopped; however, the oscillator, internal clocks, timer 1, and the receive start-bit detection circuit of the serial communications interface remain active. System processing is suspended until a qualified interrupt (hardware RESET, external interrupt on INT1, INT2, INT3, timer 1 interrupt, or low level on the receive pin of the serial communications interface 1) is detected. 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 low-power and IDLE modes (continued) In the HALT mode (HALT/STANDBY = 1), the TMS370Cx5x is placed in its lowest power consumption mode. The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is suspended until a qualified interrupt (hardware RESET, external interrupt on the INT1, INT2, INT3, or low level on the receive pin of the serial communications interface 1) is detected. The low-power mode selection bits are summarized in Table 14. ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Table 14. Low-Power/Idle Control Bits POWER-DOWN CONTROL BITS PWRDWN/IDLE (SCCR2.6) HALT/STANDBY (SCCR2.7) MODE SELECTED 1 0 STANDBY 1 1 HALT 0 X IDLE X = don’t care When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the SCCR2.6–7 bits is ignored. In addition, if an idle instruction is executed when low-power modes are disabled through a programmable contact, the device always enters the IDLE mode. To provide a method of always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This means that the NMI is generated always, regardless of the interrupt enable flags. The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file), CPU registers (stack pointer, program counter, and status register), I/O pin direction and output data, and status registers of all on-chip peripheral functions. Since all CPU instruction processing is stopped during the STANDBY and HALT modes, the clocking of the watchdog timer is inhibited. clock modules The ‘x5x family provides two clock options which are referred to as divide-by-1 (PLL) and divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of a TMS370 microcontroller. The ‘x5x ROM-masked devices offer both options to meet system engineering requirements. Only one of the two clock options is allowed on each ROM device. The ‘75xA EPROM has only the standard divide-by-4, while the ‘75xB EPROM has the divide-by-1. The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with no added cost. The divide-by-1 provides a 1-to-1 match of the external resonator frequency to the internal system clock (SYSCLK) frequency. The divide-by-4 produces a SYSCLK which is one-fourth the frequency of the external resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by four. The clock module then divides the resulting signal by four to provide the four-phased internal system clock signals. The resulting SYSCLK is equal to the resonator frequency. The frequencies are formulated as follows frequency + external resonator + CLKIN 4 4 external resonator frequency 4 Divide-by-1 option : SYSCLK + + CLKIN 4 Divide-by-4 option : SYSCLK The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators. The divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a steeper decay of emissions produced by the oscillator. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 system configuration registers Table 15 contains system configuration and control functions and registers for controlling EEPROM programming. The privileged bits are shown in a bold typeface and shaded. ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ Table 15. Peripheral File Frame 1: System Configuration Registers PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG P010 COLD START OSC POWER PF AUTO WAIT OSC FLT FLAG MC PIN WPO MC PIN DATA — µP/µC MODE SCCR0 P011 — — — AUTOWAIT DISABLE — MEMORY DISABLE — — SCCR1 P012 HALT/ STANDBY PWRDWN/ IDLE — BUS STEST CPU STEST — INT1 NMI PRIVILEGE DISABLE SCCR2 BUSY VPPS — — — — W0 EXE EPCTLH P013 P014 Reserved P015 to P016 Reserved P017 INT1 FLAG INT1 PIN DATA — — — INT1 POLARITY INT1 PRIORITY INT1 ENABLE INT1 P018 INT2 FLAG INT2 PIN DATA — INT2 DATA DIR INT2 DATA OUT INT2 POLARITY INT2 PRIORITY INT2 ENABLE INT2 P019 INT3 FLAG INT3 PIN DATA — INT3 DATA DIR INT3 DATA OUT INT3 POLARITY INT3 PRIORITY INT3 ENABLE INT3 P01A BUSY — — — — AP W1W0 EXE DEECTL BUSY VPPS — — — — W0 EXE EPCTLM — — W0 EXE EPCTLL P01B P01C Reserved P01D P01E P01F 22 Reserved BUSY VPPS — — Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 digital port control registers Peripheral file frame 2 contains the digital I/O pin configuration and control registers. Table 16 lists the specific addresses, registers, and control bits within this peripheral file frame. ÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ Table 16. Peripheral File Frame 2: Digital Port Control Registers PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG P020 Reserved APORT1 P021 Port A Control Register 2 APORT2 P022 Port A Data P023 Port A Direction P024 Reserved BPORT1 P025 Port B Control Register 2 BPORT2 P026 Port B Data P027 Port B Direction P028 Reserved CPORT1 P029 Port C Control Register 2 CPORT2 P02A Port C Data P02B Port C Direction P02C P02D Port D Control Register 1 Port D Control Register 2† P02E Port D Data P02F Port D Direction ADATA ADIR BDATA BDIR CDATA CDIR DPORT1 DPORT2 DDATA DDIR † To configure pin D3 as SYSCLK, set port D control register 2 = 08h. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 digital port control registers (continued) Table 17. Port Configuration Register Setup INPUT OUTPUT FUNCTION A FUNCTION B (µP MODE) XPORT1 = 0† XPORT2 = 0 XDATA = y XDIR = 0 XPORT1 = 0† XPORT2 = 0 XDATA = q XDIR = 1 XPORT1 = 0† XPORT2 = 1 XDATA = x XDIR = x XPORT1 = 1† XPORT2 = 1 XDATA = x XDIR = x PORT PIN A 0–7 Data In y Data Out q Data Bus Reserved B 0–7 Data In y Data Out q Low ADDR Reserved C 0–7 Data In y Data Out q Hi ADDR Reserved D 0 1 2 3 4 5 6 7 Data Out q CSE2 CSH3 CSH2 SYSCLK R/W CSPF CSH1 CSE1 OCF — — SYSCLK R/W — EDS WAIT Data In y XPORT1 = 1 XPORT2 =0 Not defined XDATA = x XDIR = x † DPORT only timer 1 module The programmable timer 1 (T1) module of the TMS370Cx5x provides the designer with the enhanced timer resources required to perform realtime system control. The T1 module contains the general-purpose timer and the watchdog (WD) timer. The two independent 16-bit timers (T1 and WD) allow program selection of input clock sources (real-time, external event, or pulse-accumulate) with multiple 16-bit registers (input capture and compare) for special timer function control. The T1 module includes three external device pins that can be used for multiple counter functions (operation mode dependent) or used as general-purpose I/O pins. T1 module is shown in Figure 5. 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 timer 1 module (continued) T1IC/CR MUX T1EVT Edge Select 16-Bit Capt/Comp Register 16-Bit Counter 16 16-Bit Compare Register 8-Bit Prescaler 16-Bit WatchdogCounter (Aux. Timer) MUX PWM Toggle T1PWM Interrupt Logic Interrupt Logic Figure 5. Timer 1 Block Diagram D D D D D D D D Three T1 I/O pins: – T1IC/CR: T1 input capture / counter reset input pin, or general-purpose bidirectional I/O pin – T1PWM: T1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin – T1EVT: T1 event input pin, or general-purpose bidirectional I/O pin Two operation modes: – Dual-compare mode: Provides PWM signal – Capture/compare mode: Provides input capture pin One 16-bit general-purpose resettable counter One 16-bit compare register with associated compare logic One 16-bit capture / compare register, which, depending on the mode of operation, operates as either a capture or compare register One 16-bit WD counter can be used as an event counter, a pulse accumulator, or an interval timer if watchdog feature is not needed. Prescaler/ clock sources that determine one of eight clock sources for general-purpose timer Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on the input capture pins (T1IC/CR) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 25 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 timer 1 module (continued) D D Interrupts that can be generated on the occurrence of: – A capture – A compare equal – A counter overflow – An external edge detection Sixteen T1 module control registers located in the PF frame, beginning at address P040 Table 18 shows the T1 module control register. ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ Table 18. T1 Module Register Memory Map PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG Modes: Dual-Compare and Capture/Compare P040 Bit 15 T1 Counter MSbyte Bit 8 T1CNTR P041 Bit 7 T1 Counter LSbyte Bit 0 P042 Bit 15 Compare Register MSbyte Bit 8 T1C P043 Bit 7 Compare Register LSbyte Bit 0 P044 Bit 15 Capture/Compare Register MSbyte Bit 8 T1CC P045 Bit 7 Capture/Compare Register LSbyte Bit 0 P046 Bit 15 Watchdog Counter MSbyte Bit 8 WDCNTR P047 Bit 7 Watchdog Counter LSbyte Bit 0 P048 Bit 15 Watchdog Reset Key P049 WD OVRFL TAP SEL† WD INPUT SELECT2† P04A WD OVRFL RST ENA† WD OVRFL INT ENA WD INPUT SELECT1† WD INPUT SELECT0† WD OVRFL INT FLAG Bit 0 WDRST — T1 INPUT SELECT2 T1 INPUT SELECT1 T1 INPUT SELECT0 T1CTL1 T1 OVRFL INT ENA T1 OVRFL INT FLAG — — T1 SW RESET T1CTL2 Mode: Dual-Compare P04B T1EDGE INT FLAG T1C2 INT FLAG T1C1 INT FLAG — — T1EDGE INT ENA T1C2 INT ENA T1C1 INT ENA T1CTL3 P04C T1 MODE = 0 T1C1 OUT ENA T1C2 OUT ENA T1C1 RST ENA T1CR OUT ENA T1EDGE POLARITY T1CR RST ENA T1EDGE DET ENA T1CTL4 Mode: Capture/Compare P04B T1EDGE INT FLAG — T1C1 INT FLAG — — T1EDGE INT ENA — T1C1 INT ENA T1CTL3 P04C T1 MODE = 1 T1C1 OUT ENA — T1C1 RST ENA — T1EDGE POLARITY — T1EDGE DET ENA T1CTL4 Modes: Dual-Compare and Capture/Compare P04D — — — — T1EVT DATA IN T1EVT DATA OUT T1EVT FUNCTION T1EVT DATA DIR T1PC1 P04E T1PWM DATA IN T1PWM DATA OUT T1PWM FUNCTION T1PWM DATA DIR T1IC/CR DATA IN T1IC/CR DATA OUT T1IC/CR FUNCTION T1IC/CR DATA DIR T1PC2 P04F T1 STEST T1 PRIORITY — — — — — — T1PRI † Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard watchdog and to the simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2 bits are ignored. 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 timer 1 module (continued) The T1 capture/compare mode block diagram is illustrated in Figure 6. The annotations on the diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2 register. 16-Bit LSB Capt/Comp MSB Register Prescale Clock Source T1C1 OUT ENA T1CTL4.6 Toggle T1CC.15-0 T1PC2.7-4 T1PWM T1CNTR.15-0 LSB 16-Bit MSB Counter 16 Compare= T1CTL3.5 Reset T1CTL3.0 T1C.15-0 T1 SW RESET T1PRI.6 0 1 Level 1 Int Level 2 Int T1C1 INT ENA 16-Bit LSB Compare Register MSB T1C1 RST ENA T1CTL2.0 ÏÏÏÏ T1 PRIORITY T1C1 INT FLAG T1 OVRFL INT FLAG T1CTL2.3 T1CTL4.4 T1CTL2.4 T1 OVRFL INT ENA T1PC2.3-0 T1EDGE DET ENA T1IC/CR Edge Select T1EDGE INT FLAG T1CTL3.7 T1CTL4.0 T1CTL3.2 T1EDGE INT ENA T1CTL4.2 T1EDGE POLARITY Figure 6. Capture/Compare Mode POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 27 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 timer 1 module (continued) The T1 dual-compare mode block diagram is illustrated in Figure 7. The annotations on the diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2 register. T1CC.15-0 16-Bit LSB Capt/Comp Register MSB MSB T1CTL2.0 Compare= T1CTL4.4 T1CTL4.5 T1PC2.7-4 16 T1C1 INT FLAG T1CTL3.5 Compare= T1C1 RST ENA Output Enable T1C2 OUT ENA 16-Bit Counter Reset T1 SW RESET T1CTL3.6 T1CTL3.1 T1C2 INT ENA T1CNTR.15-0 LSB T1C2 INT FLAG T1CTL3.0 T1C.15-0 T1CTL4.6 Toggle Prescaler Clock Source T1PWM T1C1 OUT ENA T1CTL4.3 T1C1 INT ENA 16-Bit LSB Compare Register MSB T1CR OUT ENA T1 OVRFL INT FLAG T1PC2.3-0 T1IC/CR T1CTL4.1 T1CR RST ENA T1CTL2.3 T1CTL2.4 T1 OVRFL INT ENA Edge Select T1 PRIORITY T1CTL4.0 T1EDGE DET ENA T1EDGE INT FLAG T1CTL4.2 T1EDGE POLARITY T1CTL3.7 T1CTL3.2 T1EDGE INT ENA Figure 7. Dual-Compare Mode 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 T1PRI.6 0 1 Level 1 Int Level 2 Int TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 timer 1 module (continued) The TMS370Cx5x device includes a 24-bit watchdog (WD) timer, contained in the T1 module, which can be software-programmed as an event counter, pulse accumulator, or interval timer if the watchdog function is not desired. The WD function is to monitor software and hardware operation and to implement a system reset when the WD counter is not serviced properly (WD counter overflow or WD counter is reinitialized by an incorrect value). The WD can be configured as one of the three mask options: standard watchdog, hard watchdog, or simple counter. D Standard watchdog configuration (see Figure 8) – for ’C75xA EPROM and mask-ROM devices – – Watchdog mode – Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK – A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct value is written. – Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter overflows – A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a system reset Non-watchdog mode – Watchdog timer can be configured as an event counter, pulse accumulator, or an interval timer WDCNTR.15-0 WD OVRFL INT FLAG 16-Bit Watchdog Counter T1CTL2.6 T1CTL2.5 Reset Clock Prescaler Interrupt WD OVRFL INT ENA T1CTL1.7 T1CTL2.7 WD OVRFL TAP SEL System Reset WD OVRFL RST ENA Watchdog Reset Key WDRST.7-0 Figure 8. Standard Watchdog POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 29 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 timer 1 module (continued) D Hard watchdog configuration (see Figure 9) – for ‘C75xB EPROM and mask-ROM devices – Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK. – A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct value is written. – Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter overflows – Automatic activation of the WD timer upon power-up reset – INT1 is enabled as nonmaskable interrupt during low-power modes – A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a system reset WDCNTR.15-0 WD OVRFL INT FLAG 16-Bit Watchdog Counter T1CTL2.5 Reset Clock Prescaler T1CTL1.7 WD OVRFL TAP SEL Watchdog Reset Key WDRST.7-0 Figure 9. Hard Watchdog 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 System Reset TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 timer 1 module (continued) D Simple-counter configuration (see Figure 10) – for mask-ROM devices only – The simple counter can be configured as an event counter, pulse accumulator, or an interval timer WDCNTR.15-0 WD OVFL INT FLAG 16-Bit Watchdog Counter T1CTL2.6 Interrupt T1CTL2.5 WD OVRFL INT ENA Reset Clock Prescaler T1CTL1.7 WD OVRFL TAP SEL Watchdog Reset Key WDRST.7-0 Figure 10. Simple Counter timer 2A module The 16-bit general-purpose timer 2A (T2A) module is composed of a 16-bit resettable counter, 16-bit compare register with associated compare logic, 16-bit capture register, and a 16-bit register that functions as a capture register in one mode and as a compare register in the other mode. The T2A module adds an additional timer that provides an event count, input capture, and compare functions. The T2A module includes three external device pins that can be dedicated as timer functions or used as general-purpose I/O pins. The T2A module is shown in Figure 11. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 31 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 timer 2A module (continued) Edge Detect T2AIC1/CR 16–Bit Capt/Comp Register Edge Detect T2AIC2/PWM (Dual-Capture Mode) 16–Bit Capture Register INT Logic PWM Toggle T2AIC2/PWM (Dual-Compare Mode) 16 T2AEVT Clock Select 16–Bit Compare Register 16–Bit Counter Figure 11. Timer 2A Block Diagram The T2A module features include the following: D D D D D D D 32 Three T2A I/O pins: – T2AIC1/CR: T2A input-capture 1 / counter-reset input pin, or general-purpose bidirectional I/O pin – T2AIC2/PWM: T2A input-capture 2 / pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin – T2AEVT: Timer 2A event-input pin, or general-purpose bidirectional I/O pin Two operational modes: – Dual-compare mode: Provides PWM signal – Dual-capture mode: Provides input-capture pin One 16-bit general-purpose resettable counter One 16-bit compare register with associated compare logic One 16-bit capture register with associated capture logic One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a capture or compare register T2A clock sources can be any of the following: – System clock – No clock (the counter is stopped) – External clock synchronized to the system clock (event counter) – System clock while external input is high (pulse accumulation) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 timer 2A module (continued) D D D Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on the input capture pins (T2AIC1/CR) Interrupts that can be generated on the occurrence of: – A compare equal to dedicated compare register – A compare equal to capture-compare register – A counter overflow – An external edge 1 detection – An external edge 2 detection Fourteen T2A module-control registers: Located in the PF frame beginning at address P060 The T2A module-control registers are illustrated in Table 19. ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ Table 19. Timer 2A Module Register Memory Map PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG Modes: Dual-Compare and Dual-Capture P060 Bit 15 T2A Counter MSbyte Bit 8 P061 Bit 7 T2A Counter LSbyte Bit 0 P062 Bit 15 Compare Register MSbyte Bit 8 P063 Bit 7 Compare Register LSbyte Bit 0 P064 Bit 15 Capture/Compare Register MSbyte Bit 8 P065 Bit 7 Capture/Compare Register LSbyte Bit 0 P066 Bit 15 Capture Register 2 MSbyte Bit 8 P067 Bit 7 Capture Register 2 LSbyte Bit 0 P06A — — T2ACNTR T2AC T2ACC T2AIC — T2A OVRFL INT ENA T2A OVRFL INT FLAG T2A INPUT SELECT1 T2A INPUT SELECT0 T2A SW RESET T2ACTL1 Mode: Dual-Compare P06B T2AEDGE1 INT FLAG T2AC2 INT FLAG T2AC1 INT FLAG — — T2AEDGE1 INT ENA T2AC2 INT ENA T2AC1 INT ENA T2ACTL2 P06C T2A MODE = 0 T2AC1 OUT ENA T2AC2 OUT ENA T2AC1 RST ENA T2AEDGE1 OUT ENA T2AEDGE1 POLARITY T2AEDGE1 RST ENA T2AEDGE1 DET ENA T2ACTL3 Mode: Dual-Capture P06B T2AEDGE1 INT FLAG T2AEDGE2 INT FLAG T2AC1 INT FLAG — — T2AEDGE1 INT ENA T2AEDGE2 INT ENA T2AC1 INT ENA T2ACTL2 P06C T2A MODE = 1 — — T2AC1 RST ENA T2AEDGE2 POLARITY T2AEDGE1 POLARITY T2AEDGE2 DET ENA T2AEDGE1 DET ENA T2ACTL3 Modes: Dual-Compare and Dual-Capture P06D — — — — T2AEVT DATA IN T2AEVT DATA OUT T2AEVT FUNCTION T2AEVT DATA DIR T2APC1 P06E T2AIC2 / PWM DATA IN T2AIC2 / PWM DATA OUT T2AIC2 / PWM FUNCTION T2AIC2 / PWM DATA DIR T2AIC1/CR DATA IN T2AIC1/CR DATA OUT T2AIC1/CR FUNCTION T2AIC1/CR DATA DIR T2APC2 P06F T2A STEST T2A PRIORITY — — — — — — T2APRI POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 33 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 timer 2A module (continued) The T2A dual-compare mode block diagram is illustrated in Figure 12. The annotations on the diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is 106Bh, bit 0, in the T2ACTL2 register. T2ACC.15-0 16-Bit Capt/Comp LSB Register MSB T2ACNTR.15-0 LSB MSB 16-Bit Counter Reset T2A SW RESET T2ACTL1.0 T2APC2.3-0 T2AIC1/CR T2AC2 INT FLAG T2ACTL2.6 T2ACTL2.1 Compare= T2ACTL3.5 T2AC2 INT ENA 16 T2AC1 INT FLAG T2ACTL2.5 Compare= T2ACTL2.0 T2AC.15-0 T2AC1 RST ENA 16-Bit LSB T2ACTL3.4 Compare Register MSB T2AC1 INT ENA T2AC2 OUT ENA T2ACTL3.6 T2APC2.7-4 T2AIC2/PWM T2AC1 OUT ENA T2ACTL3.3 T2AEDGE1 OUT ENA T2A OVRFL INT FLAG T2ACTL1.3 T2ACTL3.1 T2AEDGE1 RST ENA T2ACTL1.4 T2A OVRFL INT ENA Edge 1 Select T2A PRIORITY T2ACTL3.0 T2AEDGE1 DET ENA T2AEDGE1 INT FLAG T2ACTL2.7 T2ACTL3.2 T2AEDGE1 POLARITY T2ACTL2.2 T2AEDGE1 INT ENA Figure 12. Dual-Compare Mode 34 Output Enable Toggle Clock Source POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 T2APRI.6 0 Level 1 Int 1 Level 2 Int TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 timer 2A module (continued) The T2A dual-capture mode block diagram is illustrated in Figure 13. The annotations on the diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is 106Bh, bit 0, in the T2ACTL2 register. T2AIC.15–0 T2ACC.15–0 16-Bit Capt/Comp Register 1 Clock Source LSB MSB 16-Bit Capture Register 2 LSB MSB T2ACNTR.15–0 LSB MSB 16-Bit Counter 16 T2A PRIORITY T2AC1 INT FLAG T2ACTL2.5 Compare = Reset T2ACTL2.0 T2AC1 INT ENA T2AC.15–0 T2A SW RESET T2ACTL1.0 16-Bit Compare Register T2AC1 RST ENA T2APRI.6 0 Level 1 Int 1 Level 2 Int T2A OVRFL INT FLAG LSB MSB T2ACTL1.3 T2ACTL1.4 T2A OVRFL INT ENA T2ACTL3.4 T2ACTL3.0 T2AEDGE1 DET ENA T2APC2.3–0 T2AIC1/CR Edge1 Select T2AEDGE1 INT FLAG T2ACTL2.7 T2ACTL2.2 T2AEDGE1 INT ENA T2ACTL3.2 T2AEDGE1 POLARITY T2ACTL3.1 T2ACTL3.3 T2AEDGE2 DET ENA T2APC2.7–4 T2AIC2/PWM Edge 2 Select T2AEDGE2 INT FLAG T2ACTL2.6 T2AEDGE2 POLARITY T2ACTL2.1 T2AEDGE2 INT ENA Figure 13. Dual-Capture Mode POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 35 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 serial peripheral interface (SPI) module The SPI is a high-speed, synchronous, serial I/O port that allows a serial bit stream of programmed length (1 to 8 bits) to be shifted into, and out of, the device at a programmable bit-transfer rate.The SPI is used normally for communications between the microcontroller and external peripherals or another microcontroller. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and analog-to-digital converters. The master/slave operation of the SPI supports multi-device communications. The SPI module features include the following: D D D Three external pins: – SPISOMI: SPI slave output/master input pin or general purpose bidirectional I/O pin – SPISIMO: SPI slave input/master output pin or general purpose bidirectional I/O pin – SPICLK: SPI serial clock pin or general purpose bidirectional I/O pin Two operational modes: master and slave Baud rate: Eight different programmable rates – Maximum baud rate in master mode: 2.5M bps at 5-MHz SYSCLK SPI BAUD RATE – + SYSCLK 2 2 b Maximum baud rate in slave mode: 625K bps at 5-MHz SYSCLK. For maximum slave SPI BAUD RATE < SYSCLK/8 where b = bit rate in SPICCR.5-3 (range 0–7) D D D D 36 Data word format: one to eight data bits Simultaneous receive and transmit operation (transmit function can be disabled in software) Transmitter and receiver operations are accomplished through either interrupt driven or polled algorithms. Seven SPI module control registers located in control register frame beginning at address P030h POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 serial peripheral interface (SPI) module (continued) The SPI module control registers are illustrated in Table 20. Table 20. SPI Module Control Register Memory Map ÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 P030 SPI SW RESET CLOCK POLARITY SPI BIT RATE2 SPI BIT RATE1 SPI BIT RATE0 SPI CHAR2 SPI CHAR1 SPI CHAR0 SPICCR P031 RECEIVER OVERRUN SPI INT FLAG — — — MASTER/ SLAVE TALK SPI INT ENA SPICTL RCVD3 RCVD2 RCVD1 RCVD0 SPIBUF SDAT2 SDAT1 SDAT0 SPIDAT P032 to P036 P037 Reserved RCVD7 RCVD6 RCVD5 RCVD4 P038 P039 REG Reserved SDAT7 SDAT6 SDAT5 SDAT4 P03A to P03C SDAT3 Reserved P03D — — — — SPICLK DATA IN SPICLK DATA OUT SPICLK FUNCTION SPICLK DATA DIR SPIPC1 P03E SPISIMO DATA IN SPISIMO DATA OUT SPISIMO FUNCTION SPISIMO DATA DIR SPISOMI DATA IN SPISOMI DATA OUT SPISOMI FUNCTION SPISOMI DATA DIR SPIPC2 P03F SPI STEST SPI PRIORITY SPI ESPEN — — — — — SPIPRI POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 37 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 serial peripheral interface (SPI) module (continued) The SPI block diagram is illustrated in Figure 14. SPIBUF.7-0 RECEIVER OVERRUN SPIBUF Buffer Register SPICTL.7 SPIPRI.6 8 SPI INT FLAG SPICTL.0 0 SPICTL.6 1 SPIINT ENA Level 1 INT Level 2 INT SPIPC2.7-4 SPIDAT Data Register SPIDAT.7-0 SPISIMO SPICTL.1 SPIPC2.3-0 SPISOMI TALK State Control MASTER/SLAVE† SPI CHAR SPICCR.2-0 2 System Clock 1 SPICTL.2 0 SPIPC1.3-0 SPICCR.6 SPICCR.5-3 5 4 SPICLK CLOCK POLARITY 3 SPI BIT RATE † The diagram is shown in slave mode. Figure 14. SPI Block Diagram serial communications interface 1 (SCI1) module The TMS370x5x devices include a serial communications interface (SCI1) module. The SCI1 module supports digital communications between the TMS370 devices and other asynchronous peripherals and uses the standard non-return-zero format (NRZ) format. The SCI1’s receiver and transmitter are double buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full duplex mode. To ensure data integrity, the SCI1 checks received data for break detection, parity, overrun, and framing errors. The speed of bit rate (baud) is programmable to over 65,000 different speeds through a 16-bit baud-select register. 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 serial communications interface 1 (SCI1) module (continued) Features of the SCI1 module include: D D D Three external pins: – SCITXD: SCI transmit output pin or general-purpose bidirectional I/O pin – SCIRXD: SCI receive input pin or general-purpose bidirectional I/O pin – SCICLK: SCI bidirectional serial clock pin, or general-purpose bidirectional I/O pin Two communications modes: asynchronous and isosynchronous† Baud rate: 64K different programmable rates – Asynchronous mode: 3 bps to 156K bps at 5-MHz SYSCLK ASYNCHRONOUS BAUD – + (BAUD SYSCLK REG ) 1) Isosynchronous mode: 39 bps to 2.5M bps at 5-MHz SYSCLK ISOSYNCHRONOUS BAUD D D D D D D D 32 + (BAUDSYSCLK REG ) 1) 2 Data-word format – One start bit – Data-word length programmable from 1 to 8 bits – Optional even/odd/no parity bit – One or two stop bits Four error-detection flags: parity, overrun, framing, and break detection Two wake-up multiprocessor modes: Idle-line and address bit Half or full-duplex operation Double-buffered receive and transmit functions Interrupt driven or polled algorithms with status flags accomplish transmitter (TX) and receiver (RX) operations. – Transmitter: TXRDY flag (transmitter buffer register is ready to receive another character) and TX EMPTY flag (transmitter shift register is empty) – Receiver: RXRDY flag (receive buffer register ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR monitoring four interrupt conditions – Separate enable bits for transmitter and receiver interrupts – NRZ (non return-to-zero) format Eleven SCI1 module control registers are located in control register frame beginning at address P050h. † Isosynchronous = Isochronous POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 39 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 serial communications interface 1 (SCI1) module (continued) The SCI1 module control registers are illustrated in Table 21. ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ Table 21. SCI1 Module Control Register Memory Map PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 P050 STOP BITS EVEN/ODD PARITY PARITY ENABLE ASYNC/ ISOSYNC ADDRESS/ IDLE WUP SCI CHAR2 SCI CHAR1 SCI CHAR0 SCICCR P051 — — SCI SW RESET CLOCK TXWAKE SLEEP TXENA RXENA SCICTL P052 BAUDF (MSB) BAUDE BAUDD BAUDC BAUDB BAUDA BAUD9 BAUD8 BAUD MSB P053 BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1 BAUD0 (LSB) BAUD LSB P054 TXRDY TX EMPTY — — — — — SCI TX INT ENA TXCTL P055 RX ERROR RXRDY BRKDT FE OE PE RXWAKE SCI RX INT ENA RXCTL RXDT3 RXDT2 RXDT1 RXDT0 RXBUF TXDT2 TXDT1 TXDT0 TXBUF P056 P057 Reserved RXDT7 RXDT6 RXDT5 RXDT4 P058 P059 REG Reserved TXDT7 TXDT6 TXDT5 TXDT4 P05A P05B P05C TXDT3 Reserved P05D — — — — SCICLK DATA IN SCICLK DATA OUT SCICLK FUNCTION SCICLK DATA DIR SCIPC1 P05E SCITXD DATA IN SCITXD DATA OUT SCITXD FUNCTION SCITXD DATA DIR SCIRXD DATA IN SCIRXD DATA OUT SCIRXD FUNCTION SCIRXD DATA DIR SCIPC2 P05F SCI STEST SCITX PRIORITY SCIRX PRIORITY SCI ESPEN — — — — SCIPRI The SCI1 module block diagram is illustrated in Figure 15. 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 serial communications interface 1 (SCI1) module (continued) Frame Format and Mode TXWAKE SCICTL.3 PARITY EVEN / ODD ENABLE TXBUF.7 – 0 SCI TX Interrupt Transmit Data Buffer Reg. 1 TXRDY TXCTL.7 SCICCR.6 SCICCR.5 WUT ÏÏÏ ÏÏÏ SCITX PRIORITY SCI TX INT ENA SCIPRI.6 0 1 TXCTL.0 8 Level 1 INT Level 2 INT TX EMPTY TXCTL.6 TXENA BAUD MSB. 7 – 0 Baud Rate MSbyte Reg. TXSHF Reg. SCIPC2.7 – 4 SCITXD SCITXD SCICTL.1 CLOCK SCIPC1.3 – 0 SYSCLK BAUD LSB. 7 – 0 SCICLK SCICTL.4 Baud Rate LSbyte Reg. SCIPC2.3 – 0 SCIRXD RXSHF Reg. SCIRXD RXWAKE RXCTL.1 SCI RX Interrupt RXENA RX ERROR RXCTL.7 RXCTL.4 – 2 ERR FE OE PE SCICTL.0 RXRDY RXCTL.6 8 SCI RX INT ENA RXCTL.0 Receive Data Buffer Reg. ÏÏÏÏ ÏÏÏÏ SCIRX PRIORITY SCIPRI.5 0 1 Level 1 INT Level 2 INT BRKDT RXCTL.5 RXBUF.7 – 0 Figure 15. SCI1 Block Diagram analog-to-digital converter 1 (ADC1) module The analog-to-digital converter 1 (ADC1) module is an 8-bit, successive approximation converter with internal sample-and-hold circuitry. The module has eight multiplexed analog input channels that allow the processor to convert the voltage levels from up to eight different sources. The ADC1 module features include the following: D D Minimum conversion time: 32.8 µs at 5-MHz SYSCLK Ten external pins: – Eight analog input channels (AN0 – AN7), any of which can be software configured as digital inputs (E0– E7) if not needed as analog channels – AN1– AN7 can also be configured as positive-input voltage reference. – VCC3: A/D module high-voltage reference input – VSS3: A/D module low-voltage reference input POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 41 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 analog-to-digital converter 1 (ADC1) module (continued) D D D The ADDATA register, which contains the digital result of the last ADC1 conversion ADC1 operations can be accomplished through either interrupt driven or polled algorithms. Six ADC1 module control registers are located in the control-register frame beginning at address 1070h. The ADC1 module control registers are illustrated in Table 22. ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ Table 22. ADC1 Module Control Register Memory Map PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 P070 CONVERT START SAMPLE START REF VOLT SELECT2 REF VOLT SELECT1 REF VOLT SELECT0 AD INPUT SELECT2 AD INPUT SELECT1 AD INPUT SELECT0 ADCTL P071 — — — — — AD READY AD INT FLAG AD INT ENA ADSTAT P072 A-to-D Conversion Data Register P073 to P07C Reserved P07D Port E Data Input Register P07E P07F 42 ADDATA ADIN Port E Input Enable Register AD STEST AD PRIORITY AD ESPEN — POST OFFICE BOX 1443 — REG ADENA — • HOUSTON, TEXAS 77251–1443 — — ADPRI TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 analog-to-digital converter 1 (ADC1) module (continued) The ADC1 module block diagram is illustrated in Figure 16. Port E Input ENA 0 ADENA.0 Port E Data AN 0 ADIN.0 0 SAMPLE START CONVERT START ADCTL.2 – 0 ADCTL.6 ADCTL.7 2 1 AN0 Port E Input ENA 1 ADENA.1 Port E Data AN 1 AD INPUT SELECT ADIN.1 AN1 Port E Input ENA 2 ADENA.2 Port E Data AN 2 ADIN.2 AN2 Port E Input ENA 3 ADENA.3 Port E Data AN 3 ADIN.3 AN3 Port E Input ENA 4 ADENA.4 ADC1 Port E Data AN 4 ADIN.4 AN4 ADDATA.7 – 0 Port E Input ENA 5 ADENA.5 Port E Data AN 5 A-to-D Conversion Data Register ADIN.5 AN5 Port E Input ENA 6 ADENA.6 ADIN.6 AN6 Port E Input ENA 7 ADENA.7 AD READY Port E Data AN 6 ADSTAT.2 5 4 3 ADCTL.5 – 3 Port E Data AN 7 REF VOLTS SELECT AD PRIORITY ADPRI.6 0 Level 1 INT 1 Level 2 INT ADIN.7 AN7 VCC3 AD INT FLAG VSS3 ADSTAT.1 ADSTAT.0 AD INT ENA Figure 16. ADC1 Block Diagram POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 43 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 instruction set overview Table 23 provides an opcode-to-instruction cross-reference of all 73 instructions and 274 opcodes of the ‘370Cx5x instruction set. The numbers at the top of this table represent the most significant nibble of the opcode while the numbers at the left side of the table represent the least significant nibble. The instruction of these two opcode nibbles contains the mnemonic, operands, and byte / cycle particular to that opcode. For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes in eight SYSCLK cycles. 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Table 23. TMS370 Family Opcode/Instruction Map† MSN 0 2 3 4 5 6 7 8 INCW #ra,Rd 3/11 MOV Ps,A 2/8 0 JMP #ra 2/7 1 JN ra 2/5 2 JZ ra 2/5 MOV Rs,A 2/7 MOV #n,A 2/6 MOV Rs,B 2/7 MOV Rs,Rd 3/9 MOV #n,B 2/6 MOV B,A 1/8 MOV #n,Rd 3/8 3 JC ra 2/5 AND Rs,A 2/7 AND #n,A 2/6 AND Rs,B 2/7 AND Rs,Rd 3/9 AND #n,B 2/6 AND B,A 1/8 AND #n,Rd 3/8 AND A,Pd 2/9 4 JP ra 2/5 OR Rs,A 2/7 OR #n,A 2/6 OR Rs,B 2/7 OR Rs,Rd 3/9 OR #n,B 2/6 OR B,A 1/8 OR #n,Rd 3/8 5 JPZ ra 2/5 XOR Rs,A 2/7 XOR #n,A 2/6 XOR Rs,B 2/7 XOR Rs,Rd 3/9 XOR #n,B 2/6 XOR B,A 1/8 6 JNZ ra 2/5 BTJO Rs,A,ra 3/9 BTJO #n,A,ra 3/8 BTJO Rs,B,ra 3/9 BTJO Rs,Rd,ra 4/11 BTJO #n,B,ra 3/8 7 JNC ra 2/5 BTJZ Rs.,A,ra 3/9 BTJZ #n,A,ra 3/8 BTJZ Rs,B,ra 3/9 BTJZ Rs,Rd,ra 4/11 8 JV ra 2/5 ADD Rs,A 2/7 ADD #n,A 2/6 ADD Rs,B 2/7 9 JL ra 2/5 ADC Rs,A 2/7 ADC #n,A 2/6 A JLE ra 2/5 SUB Rs,A 2/7 B JHS ra 2/5 SBB Rs,A 2/7 MOV A,Pd 2/8 MOV B,Pd 2/8 MOV Rs,Pd 3/10 9 A B C D E F CLRC / TST A 1/9 MOV A,B 1/9 MOV A,Rd 2/7 TRAP 15 1/14 LDST n 2/6 MOV B,Rd 2/7 TRAP 14 1/14 MOV #ra[SP],A 2/7 MOV Ps,B 2/7 MOV Ps,Rd 3/10 DEC A 1/8 DEC B 1/8 DEC Rd 2/6 TRAP 13 1/14 MOV A,*ra[SP] 2/7 AND B,Pd 2/9 AND #n,Pd 3/10 INC A 1/8 INC B 1/8 INC Rd 2/6 TRAP 12 1/14 CMP *n[SP],A 2/8 OR A,Pd 2/9 OR B,Pd 2/9 OR #n,Pd 3/10 INV A 1/8 INV B 1/8 INV Rd 2/6 TRAP 11 1/14 extend inst,2 opcodes XOR #n,Rd 3/8 XOR A,Pd 2/9 XOR B,Pd 2/9 XOR #n,Pd 3/10 CLR A 1/8 CLR B 1/8 CLR Rn 2/6 TRAP 10 1/14 BTJO B,A,ra 2/10 BTJO #n,Rd,ra 4/10 BTJO A,Pd,ra 3/11 BTJO B,Pd,ra 3/10 BTJO #n,Pd,ra 4/11 XCHB A 1/10 XCHB A / TST B 1/10 XCHB Rn 2/8 TRAP 9 1/14 IDLE BTJZ #n,B,ra 3/8 BTJZ B,A,ra 2/10 BTJZ #n,Rd,ra 4/10 BTJZ A,Pd,ra 3/10 BTJZ B,Pd,ra 3/10 BTJZ #n,Pd,ra 4/11 SWAP A 1/11 SWAP B 1/11 SWAP Rn 2/9 TRAP 8 1/14 MOV #n,Pd 3/10 ADD Rs,Rd 3/9 ADD #n,B 2/6 ADD B,A 1/8 ADD #n,Rd 3/8 MOVW #16,Rd 4/13 MOVW Rs,Rd 3/12 MOVW #16[B],Rpd 4/15 PUSH A 1/9 PUSH B 1/9 PUSH Rd 2/7 TRAP 7 1/14 SETC ADC Rs,B 2/7 ADC Rs,Rd 3/9 ADC #n,B 2/6 ADC B,A 1/8 ADC #n,Rd 3/8 JMPL lab 3/9 JMPL *Rp 2/8 JMPL *lab[B] 3/11 POP A 1/9 POP B 1/9 POP Rd 2/7 TRAP 6 1/14 RTS SUB #n,A 2/6 SUB Rs,B 2/7 SUB Rs,Rd 3/9 SUB #n,B 2/6 SUB B,A 1/8 SUB #n,Rd 3/8 MOV & lab,A 3/10 MOV *Rp,A 2/9 MOV *lab[B],A 3/12 DJNZ A,#ra 2/10 DJNZ B,#ra 2/10 DJNZ Rd,#ra 3/8 TRAP 5 1/14 RTI 1/12 SBB #n,A 2/6 SBB Rs,B 2/7 SBB Rs,Rd 3/9 SBB #n,B 2/6 SBB B,A 1/8 SBB #n,Rd 3/8 MOV A, & lab 3/10 MOV A, *Rp 2/9 MOV A,*lab[B] 3/12 COMPL A 1/8 COMPL B 1/8 COMPL Rd 2/6 TRAP 4 1/14 PUSH ST 1/8 1/6 1/7 1/9 45 TMS370Cx5x 8-BIT MICROCONTROLLER † All conditional jumps (opcodes 01 – 0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions have a relative address as the last operand. SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 L S N 1 2 3 4 5 6 7 8 9 A B C D E F C JNV ra 2/5 MPY Rs,A 2/46 MPY #n,A 2/45 MPY Rs,B 2/46 MPY Rs,Rd 3/48 MPY #n,B 2/45 MPY B,A 1/47 MPY #n,Rs 3/47 BR lab 3/9 BR *Rp 2/8 BR *lab[B] 3/11 RR A 1/8 RR B 1/8 RR Rd 2/6 TRAP 3 1/14 POP ST 1/8 JGE ra 2/5 CMP Rs,A 2/7 CMP #n,A 2/6 CMP Rs,B 2/7 CMP Rs,Rd 3/9 CMP #n,B 2/6 CMP B,A 1/8 CMP #n,Rd 3/8 CMP & lab,A 3/11 CMP *Rp,A 2/10 CMP *lab[B],A 3/13 RRC A 1/8 RRC B 1/8 RRC Rd 2/6 TRAP 2 1/14 LDSP D DAC Rs,A 2/9 DAC #n,A 2/8 DAC Rs,B 2/9 DAC Rs,Rd 3/11 DAC #n,B 2/8 DAC B,A 1/10 DAC #n,Rd 3/10 CALL lab 3/13 CALL *Rp 2/12 CALL *lab[B] 3/15 RL A 1/8 RL B 1/8 RL Rd 2/6 TRAP 1 1/14 STSP E JG ra 2/5 DSB Rs,A 2/9 DSB #n,A 2/8 DSB Rs,B 2/9 DSB Rs,Rd 3/11 DSB #n,B 2/8 DSB B,A 1/10 DSB #n,Rd 3/10 CALLR lab 3/15 CALLR *Rp 2/14 CALLR *lab[B] 3/17 RLC A 1/8 RLC B 1/8 RLC Rd 2/6 TRAP 0 1/14 NOP F JLO ra 2/5 F4 8 MOVW *n[Rn] 4/15 DIV Rn.A 3/14-63 F4 9 JMPL *n[Rn] 4/16 F4 A MOV *n[Rn],A 4/17 F4 B MOV A,*n[Rn] 4/16 F4 C BR *n[Rn] 4/16 F4 D CMP *n[Rn],A 4/18 F4 E CALL *n[Rn] 4/20 F4 F CALLR *n[Rn] 4/22 L S N Second byte of two-byte instructions (F4xx): POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Legend: * = Indirect addressing operand prefix & = Direct addressing operand prefix # = immediate operand #16 = immediate 16-bit number lab = 16-label n = immediate i di t 8-bit 8 bit number b Pd = Peripheral register containing destination type Pn = Peripheral register Ps = Peripheral Peri heral register containing source byte ra = Relative address Rd = Register containing destination type Rn = Register file Rp = Register pair Rpd = Destination register pair Rps = Source Register pair Rs = Register containing source byte 1/7 1/8 1/7 † All conditional jumps (opcodes 01 – 0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions have a relative address as the last operand. Template Release Date: 7–11–94 1 TMS370Cx5x 8-BIT MICROCONTROLLER MSN 0 SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 46 Table 23. TMS370 Family Opcode/Instruction Map† (Continued) TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 development system support The TMS370 family development support tools include an assembler, a C compiler, a linker, an in-circuit emulator (XDS/22), CDT, and an EEPROM / UVEPROM programmer. D D D Assembler/ linker (Part No. TMDS3740850–02 for PC) – Includes extensive macro capability – Features high-speed operation – Includes format conversion utilities for popular formats ANSI C-Compiler (Part No. TMDS3740855–02 for PC, Part No. TMDS3740555–09 for HP700, Sun-3 or Sun-4) – Generates assembly code for the TMS370 that can be inspected easily – Improves code execution speed and reduces code size with optional optimizer pass – Enables direct reference of the TMS370’s port registers by using a naming convention – Provides flexibility in specifying the storage for data objects – Interfaces C functions and assembly functions easily – Includes assembler and linker CDT370 (compact development tool) real-time in-circuit emulation – D Base (Part Number EDSCDT370 – for PC, requires cable) – Cable for 68-pin PLCC (Part No. EDSTRG68PLCC) – Cable for 64-pin SDIP (Part No. EDSTRG64SDIL) – Provides EEPROM and EPROM programming support – Allows inspection and modification of memory locations – Allows uploading / downloading of program and data memory – Provides capability to execute programs and software routines – Includes 1 024 samples trace buffer – Includes single-step executable instructions – Allows use of software breakpoints to halt program execution at selected address XDS/ 22 (extended development support) in-circuit emulator – Base (Part Number TMDS3762210 for PC, requires cable) – Cable for 68-pin PLCC / 64-Pin SDIP (Part No. TMDS3788868) – Contains all of the features of the CDT370 described above but does not have the capability to program the data EEPROM and program EPROM – Contains sophisticated breakpoint trace and timing hardware that provides up to 2 047 qualified trace samples with symbolic disassembly – Allows breakpoints to be qualified by address and / or data on any type of memory acquisition. Up to four levels of events can be combined to cause a breakpoint – Provides timers for analyzing total and average time in routines HP700 is a trademark of Hewlett-Packard Company. Sun-3 and Sun-4 are trademarks of Sun Microsystems, Inc. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 47 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 development system support (continued) – D Microcontroller programmer – – D D 48 Contains an eight-line logic probe for adding visibility of external signals to the breakpoint qualifier and for tracing display Base (Part No. TMDS3760500A – for PC, requires programmer head) – Single unit head for 68-pin PLCC (Part No. TMDS3780510A) – Single unit head for 64-pin SDIP (Part No. TMDS3780511A) Personal computer-based, window / function-key oriented user interface for ease of use and rapid learning environment Design kit (Part No. TMDS3770110 – for PC) – Includes TMS370 Application Board and TMS370 Assembler diskette and documentation. – Supports quick evaluation of TMS370 functionality – Provides capability to upload and download code – Provides capability to execute programs and software routines, and to single-step executable instructions – Allows software breakpoints to halt program execution at selected addresses – Includes wire-wrap prototype area – Includes reverse assembler Starter Kit (Part No. TMDS37000 – For PC) – Includes TMS370 Assembler diskette and documentation – Includes TMS370 Simulator – Includes programming adapter board and programming software – Does not include – (to be supplied by the user): – + 5 V power supply – ZIF sockets – 9-pin RS232 cable POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 device numbering conventions Figure 17 illustrates the numbering and symbol nomenclature for the TMS370Cx5x family. TMS 370 C 7 5 2 A FN T Prefix: TMS = Standard prefix for fully qualified devices SE = System evaluator (window EPROM) that is used for prototyping purpose. Family: Technology: Program Memory Types: Device Type: Memory Size: Temperature Ranges: Packages: ROM and EPROM Option: 370 = TMS370 8-Bit Microcontroller Family C = CMOS 0 1 2 3 4 7 = = = = = = Mask ROM ROM-less, No Data EEPROM ROM-less Mask ROM, No Data EEPROM ROM memory with security EPROM 5 = ’x5x device containing the following modules: – Timer 1 – Timer 2A – Serial Peripheral Interface – Serial Communications Interface 1 – Analog-to-Digital Converter 1 0 2 3 6 8 9 = = = = = = 4K bytes 8K bytes 12K bytes 16K bytes 32K Bytes 48K Bytes A = – 40°C to 85°C L = 0°C to 70°C T = – 40°C to 105°C FN FZ NM JN = = = = Plastic Leaded Chip Carrier Ceramic Leaded Chip Carrier Plastic Shrink Dual-In-Line Ceramic Shrink Dual-in-Line A = For ROM device, the watchdog timer can be configured as one of the three different mask options: – A standard watchdog – A hard watchdog – A simple watchdog The clock can be either: – Divide-by-4 clock – Divide-by-1 (PLL) clock The low-power modes can be either: – Enabled – Disabled A = For ROM-less device, a standard watchdog, a divide-by-4 clock, and low-power modes are enabled. A = For EPROM device, a standard watchdog, a divide-by-4 clock, and low-power modes are enabled. B = For EPROM device, a hard watchdog, a divide-by-1 (PLL) clock, and low-power modes are enabled. Figure 17. TMS370Cx5x Family Nomenclature POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 49 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 device part numbers Table 24 provides a list of all the ‘x5x devices available. The device part number nomenclature is designed to assist ordering. Upon ordering, the customer must specify not only the device part number but also the clock and watchdog timer options desired. Remember that each device can have only one of the three possible watchdog timer options and one of the two clock options. The options to be specified pertain solely to orders involving ROM devices. ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Table 24. Device Part Numbers DEVICE PART NUMBERS FOR 68 PINS DEVICE PART NUMBERS FOR 64 PINS DEVICE PART NUMBERS FOR 68 PINS DEVICE PART NUMBERS FOR 64 PINS TMS370C050AFNA TMS370C050AFNL TMS370C050AFNT TMS370C050ANMA TMS370C050ANML TMS370C050ANMT TMS370C356AFNA TMS370C356AFNL TMS370C356AFNT TMS370C356ANMA TMS370C356ANML TMS370C356ANMT TMS370C150AFNT — TMS370C456AFNA TMS370C456AFNL TMS370C456AFNT — TMS370C250AFNT — TMS370C756AFNT TMS370C756ANMT TMS370C350AFNA TMS370C350AFNL TMS370C350AFNT TMS370C350ANMA TMS370C350ANML TMS370C350ANMT TMS370C058AFNA TMS370C058AFNL TMS370C058AFNT TMS370C058ANMA TMS370C058ANML TMS370C058ANMT TMS370C052AFNA TMS370C052AFNL TMS370C052AFNT TMS370C052ANMA TMS370C052ANML TMS370C052ANMT TMS370C358AFNA TMS370C358AFNL TMS370C358AFNT TMS370C358ANMA TMS370C358ANML TMS370C358ANMT TMS370C352AFNA TMS370C352AFNL TMS370C352AFNT TMS370C352ANMA TMS370C352ANML TMS370C352ANMT TMS370C758AFNT TMS370C758ANMT TMS370C452AFNA TMS370C452AFNL TMS370C452AFNT — TMS370C758BFNT TMS370C758BNMT TMS370C353AFNA TMS370C353AFNL TMS370C353AFNT — TMS370C059AFNA† TMS370C059AFNL† TMS370C059AFNT† — TMS370C056AFNA TMS370C056AFNL TMS370C056AFNT TMS370C056ANMA TMS370C056ANML TMS370C056ANMT TMS370C759AFNT† — TMS370C156AFNT — TMS370C256AFNT — SE370C756AFZT‡ SE370C758AFZT‡ SE370C758BFZT‡ SE370C759AFZT †‡ SE370C756AJNT‡ SE370C758AJNT‡ SE370C758BJNT‡ † Only operate up to 3 MHz SYSCLK ‡ System evaluators are for use only in prototype environment, and their reliability has not been characterized. 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 new code release form Figure 18 shows a sample of the new code release form. NEW CODE RELEASE FORM TEXAS INSTRUMENTS TMS370 MICROCONTROLLER PRODUCTS DATE: To release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information: 1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media) 2. An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book. Company Name: Street Address: Street Address: City: Contact Mr./Ms.: Phone: ( State Zip ) Ext.: Customer Purchase Order Number: Customer Print Number *Yes: # No: (Std. spec to be followed) *If Yes: Customer must provide ”print” to TI w/NCRF for approval before ROM code processing starts. Customer Part Number: Customer Application: TMS370 Device: TI Customer ROM Number: (provided by Texas Instruments) CONTACT OPTIONS FOR THE ’A’ VERSION TMS370 MICROCONTROLLERS OSCILLATOR FREQUENCY MIN TYP MAX [] External Drive (CLKIN) [] Crystal [] Ceramic Resonator [] Supply Voltage MIN: (std range: 4.5V to 5.5V) Low Power Modes [] Enabled [] Disabled Watchdog counter [] Standard [] Hard Enabled [] Simple Counter Clock Type [] Standard (/4) [] PLL (/1) NOTE: Non ’A’ version ROM devices of the TMS370 microcontrollers will have the “Low-power modes Enabled”, “Divide-by-4” Clock, and “Standard” Watchdog options. See the TMS370 Family User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B). MAX: TEMPERATURE RANGE [] ’L’: 0° to 70°C (standard) [] ’A’: –40° to 85°C [] ’T’: –40° to 105°C PACKAGE TYPE [] ’N’ 28-pin PDIP [] “FN” 44-pin PLCC [] “FN” 28-pin PLCC [] “FN” 68-pin PLCC [] “N” 40-pin PDIP [] “NM” 64-pin PSDIP [] “NJ” 40-pin PSDIP (formerly known as N2) SYMBOLIZATION BUS EXPANSION [] TI standard symbolization [] TI standard w/customer part number [] Customer symbolization (per attached spec, subject to approval) [] YES [] NO NON-STANDARD SPECIFICATIONS: ALL NON-STANDARDS SPECIFICATIONS MUST BE APPROVED BY THE TI ENGINEERING STAFF: If the customer requires expedited production material (i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a ’P’ in the symbolization preceding the TI part number. RELEASE AUTHORIZATION: This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification code is approved by the customer. 1. Customer: Date: 2. TI: Field Sales: Marketing: Prod. Eng.: Proto. Release: Figure 18. Sample New Code Release Form POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 51 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 Table 25 is a listing of all the peripheral file frames using the ’Cx5x (provided for a quick reference). ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ Á ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 25. Peripheral File Frame Compilation PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG SYSTEM CONFIGURATION REGISTERS P010 OSC POWER PF AUTO WAIT OSC FLT FLAG MC PIN WPO MC PIN DATA — µP/µC MODE SCCR0 — — AUTOWAIT DISABLE — MEMORY DISABLE — — SCCR1 HALT/ STANDBY PWRDWN/ IDLE — BUS STEST CPU STEST — INT1 NMI PRIVILEGE DISABLE SCCR2 BUSY VPPS — — — — W0 EXE EPCTLH COLD START P011 P012 P013 P014 Reserved P015 to P016 Reserved P017 INT1 FLAG INT1 PIN DATA — — — INT1 POLARITY INT1 PRIORITY INT1 ENABLE INT1 P018 INT2 FLAG INT2 PIN DATA — INT2 DATA DIR INT2 DATA OUT INT2 POLARITY INT2 PRIORITY INT2 ENABLE INT2 P019 INT3 FLAG INT3 PIN DATA — INT3 DATA DIR INT3 DATA OUT INT3 POLARITY INT3 PRIORITY INT3 ENABLE INT3 P01A BUSY — — — — AP W1W0 EXE DEECTL BUSY VPPS — — — — W0 EXE EPCTLM BUSY VPPS — — — — W0 EXE EPCTLL P01B P01C Reserved P01D P01E Reserved DIGITAL PORT CONTROL REGISTERS P01F Reserved P020 Reserved APORT1 P021 Port A Control Register 2 APORT2 P022 Port A Data P023 Port A Direction ADATA ADIR P024 Reserved BPORT1 P025 Port B Control Register 2 BPORT2 P026 Port B Data P027 Port B Direction P028 Reserved CPORT1 CPORT2 P029 Port C Control Register 2 P02A Port C Data P02B Port C Direction BDATA BDIR CDATA CDIR P02C Port D Control Register 1 DPORT1 P02D Port D Control Register 2† DPORT2 P02E Port D Data P02F Port D Direction † To configure pin D3 as SYSCLK, set port D control register 2 = 08h. 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DDATA DDIR TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 Table 25. Peripheral File Frame Compilation (Continued) ÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG SPI MODULE CONTROL REGISTER P030 SPI SW RESET CLOCK POLARITY SPI BIT RATE2 SPI BIT RATE1 SPI BIT RATE0 SPI CHAR2 SPI CHAR1 SPI CHAR0 SPICCR P031 RECEIVER OVERRUN SPI INT FLAG — — — MASTER/ SLAVE TALK SPI INT ENA SPICTL RCVD3 RCVD2 RCVD1 RCVD0 SPIBUF SDAT2 SDAT1 SDAT0 SPIDAT P032 to P036 P037 Reserved RCVD7 RCVD6 RCVD5 RCVD4 SDAT7 SDAT6 SDAT5 SDAT4 P038 P039 Reserved P03A to P03C SDAT3 Reserved P03D — — — — SPICLK DATA IN SPICLK DATA OUT SPICLK FUNCTION SPICLK DATA DIR SPIPC1 P03E SPISIMO DATA IN SPISIMO DATA OUT SPISIMO FUNCTION SPISIMO DATA DIR SPISOMI DATA IN SPISOMI DATA OUT SPISOMI FUNCTION SPISOMI DATA DIR SPIPC2 P03F SPI STEST SPI PRIORITY SPI ESPEN — — — — — SPIPRI TIMER 1 MODULE REGISTER Modes: Dual-Compare and Capture / Compare P040 Bit 15 T1 Counter MSbyte Bit 8 P041 Bit 7 T1 Counter LSbyte Bit 0 P042 Bit 15 Compare Register MSbyte Bit 8 P043 Bit 7 Compare Register LSbyte Bit 0 P044 Bit 15 Capture/Compare Register MSbyte Bit 8 P045 Bit 7 Capture/Compare Register LSbyte Bit 0 P046 Bit 15 Watchdog Counter MSbyte Bit 8 P047 Bit 7 Watchdog Counter LSbyte Bit 0 P048 Bit 15 Watchdog Reset Key P049 WD OVRFL TAP SEL† WD INPUT SELECT2† P04A WD OVRFL RST ENA† WD OVRFL INT ENA WD INPUT SELECT1† WD INPUT SELECT0† WD OVRFL INT FLAG Bit 0 T1CNTR T1C T1CC WDCNTR WDRST — T1 INPUT SELECT2 T1 INPUT SELECT1 T1 INPUT SELECT0 T1CTL1 T1 OVRFL INT ENA T1 OVRFL INT FLAG — — T1 SW RESET T1CTL2 Mode: Dual-Compare P04B T1EDGE INT FLAG T1C2 INT FLAG T1C1 INT FLAG — — T1EDGE INT ENA T1C2 INT ENA T1C1 INT ENA T1CTL3 P04C T1 MODE = 0 T1C1 OUT ENA T1C2 OUT ENA T1C1 RST ENA T1CR OUT ENA T1EDGE POLARITY T1CR RST ENA T1EDGE DET ENA T1CTL4 T1C1 INT FLAG — — T1EDGE INT ENA — T1C1 INT ENA T1CTL3 Mode: Capture/Compare P04B T1EDGE INT FLAG — † Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard watchdog and to the simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2 bits are ignored. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 53 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 Table 25. Peripheral File Frame Compilation (Continued) ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ Á ÁÁÁÁ Á ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG T1C1 RST ENA — T1EDGE POLARITY — T1EDGE DET ENA T1CTL4 Mode: Capture/Compare (Continued) P04C T1 MODE = 1 T1C1 OUT ENA — Modes: Dual-Compare and Capture / Compare P04D — — — — T1EVT DATA IN T1EVT DATA OUT T1EVT FUNCTION T1EVT DATA DIR T1PC1 P04E T1PWM DATA IN T1PWM DATA OUT T1PWM FUNCTION T1PWM DATA DIR T1IC/CR DATA IN T1IC/CR DATA OUT T1IC/CR FUNCTION T1IC/CR DATA DIR T1PC2 P04F T1 STEST T1 PRIORITY — — — — — — T1PRI SCI1 MODULE CONTROL REGISTER P050 STOP BITS EVEN/ODD PARITY PARITY ENABLE ASYNC/ ISOSYNC ADDRESS/ IDLE WUP SCI CHAR2 SCI CHAR1 SCI CHAR0 SCICCR P051 — — SCI SW RESET CLOCK TXWAKE SLEEP TXENA RXENA SCICTL P052 BAUDF (MSB) BAUDE BAUDD BAUDC BAUDB BAUDA BAUD9 BAUD8 BAUD MSB P053 BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1 BAUD0 (LSB) BAUD LSB P054 TXRDY TX EMPTY — — — — — SCI TX INT ENA TXCTL P055 RX ERROR RXRDY BRKDT FE OE PE RXWAKE SCI RX INT ENA RXCTL RXDT3 RXDT2 RXDT1 RXDT0 RXBUF TXDT2 TXDT1 TXDT0 TXBUF P056 P057 Reserved RXDT7 RXDT6 RXDT5 RXDT4 P058 P059 Reserved TXDT7 TXDT6 TXDT5 TXDT4 P05A P05B P05C TXDT3 Reserved P05D — — — — SCICLK DATA IN SCICLK DATA OUT SCICLK FUNCTION SCICLK DATA DIR SCIPC1 P05E SCITXD DATA IN SCITXD DATA OUT SCITXD FUNCTION SCITXD DATA DIR SCIRXD DATA IN SCIRXD DATA OUT SCIRXD FUNCTION SCIRXD DATA DIR SCIPC2 P05F SCI STEST SCITX PRIORITY SCIRX PRIORITY SCI ESPEN — — — — SCIPRI T2A MODULE REGISTER Modes: Dual-Compare and Dual-Capture P060 Bit 15 T2A Counter MSbyte Bit 8 P061 Bit 7 T2A Counter LSbyte Bit 0 P062 Bit 15 Compare Register MSbyte Bit 8 P063 Bit 7 Compare Register LSbyte Bit 0 P064 Bit 15 Capture/Compare Register MSbyte Bit 8 P065 Bit 7 Capture/Compare Register LSbyte Bit 0 P066 Bit 15 Capture Register 2 MSbyte Bit 8 P067 Bit 7 Capture Register 2 LSbyte Bit 0 54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 T2ACNTR T2AC T2ACC T2AIC TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 Table 25. Peripheral File Frame Compilation (Continued) ÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG Modes: Dual-Compare and Dual-Capture (Continued) P06A — — — T2A OVRFLINT ENA T2A OVRFL INT FLAG T2A INPUT SELECT1 T2A INPUT SELECT0 T2A SW RESET T2ACTL1 Mode: Dual-Compare P06B T2AEDGE1 INT FLAG T2AC2 INT FLAG T2AC1 INT FLAG — — T2AEDGE1 INT ENA T2AC2 INT ENA T2AC1 INT ENA T2ACTL2 P06C T2A MODE = 0 T2AC1 OUT ENA T2AC2 OUT ENA T2AC1 RST ENA T2AEDGE1 OUT ENA T2AEDGE1 POLARITY T2AEDGE1 RST ENA T2AEDGE1 DET ENA T2ACTL3 Mode: Dual-Capture P06B T2AEDGE1 INT FLAG T2AEDGE2 INT FLAG T2AC1 INT FLAG — — T2AEDGE1 INT ENA T2AEDGE2 INT ENA T2AC1 INT ENA T2ACTL2 P06C T2A MODE = 1 — — T2AC1 RST ENA T2AEDGE2 POLARITY T2AEDGE1 POLARITY T2AEDGE2 DET ENA T2AEDGE1 DET ENA T2ACTL3 Modes: Dual-Compare and Dual-Capture P06D — — — — T2AEVT DATA IN T2AEVT DATA OUT T2AEVT FUNCTION T2AEVT DATA DIR T2APC1 P06E T2AIC2 / PWM DATA IN T2AIC2 / PWM DATA OUT T2AIC2 / PWM FUNCTION T2AIC2 / PWM DATA DIR T2AIC1/CR DATA IN T2AIC1/CR DATA OUT T2AIC1/CR FUNCTION T2AIC1/CR DATA DIR T2APC2 P06F T2A STEST T2A PRIORITY — — — — — — T2APRI P070 CONVERT START SAMPLE START REF VOLT SELECT2 REF VOLT SELECT1 REF VOLT SELECT0 AD INPUT SELECT2 AD INPUT SELECT1 AD INPUT SELECT0 ADCTL P071 — — — — — AD READY AD INT FLAG AD INT ENA ADSTAT ADC1 MODULE CONTROL REGISTER P072 A-to-D Conversion Data Register P073 to P07C Reserved P07D Port E Data Input Register P07E P07F ADDATA ADIN Port E Input Enable Register AD STEST AD PRIORITY AD ESPEN — POST OFFICE BOX 1443 — ADENA — • HOUSTON, TEXAS 77251–1443 — — ADPRI 55 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range,VCC1‡, VCC2, VCC3 (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V Input voltage range, All pins except MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V Input clamp current, IIK (VI < 0 or VI > VCC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Continuous output current per buffer, IO (VO = 0 to VCC1)§ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 mA Maximum ICC current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 mA Maximum ISS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 170 mA Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W Operating free-air temperature range, TA: L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 105°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ VCC1 = VCC § Electrical characteristics are specified with all output buffers loaded with specified IO current. Exceeding the specified IO current in any buffer can affect the levels on other buffers. NOTE 2: Unless otherwise noted, all voltage values are with respect to VSS1. recommended operating conditions VCC1 Supply voltage (see Note 2) RAM data-retention supply voltage (see Note 3) MIN NOM MAX 4.5 5 5.5 3 5.5 UNIT V VCC2 VCC3 Digital I/O supply voltage (see Note 2) 4.5 5 5.5 Analog supply voltage (see Note 2) 4.5 5 5.5 VSS2 VSS3 Digital I/O supply ground – 0.3 0 0.3 V – 0.3 0 VIL Analog supply ground Low level input voltage Low-level All pins except MC MC, normal operation All pins except MC, XTAL2 / CLKIN, and RESET VIH High-level g input voltage g MC (non-WPO mode) XTAL2 / CLKIN RESET VMC MC ((mode control)) voltage g (see Note 4) EPROM programming voltage (VPP) Operating free-air temperature V 0.8 V 0.3 V 2 VCC1 VCC1 – 0.3 0.8 VCC1 VCC1 + 0.3 VCC1 11.7 12 VCC1 13 13 13.2 13.5 VCC1 – 0.3 VSS1 Microprocessor Microcomputer TA 0.3 VSS1 VSS1 0.7 VCC1 EEPROM write protect override (WPO) V VCC1 + 0.3 0.3 L version 0 A version – 40 85 T version – 40 105 V V 70 °C NOTES: 2. Unless otherwise noted, all voltage values are with respect to VSS1. 3. RESET must be externally activated when VCC1 or SYSCLK is not within the recommended operating range. 4. The basic microcomputer and microprocessor operating modes are selected by the voltage level applied to the dedicated MC pin two system-clock cycles (tc) before RESET goes inactive (high). The WPO mode can be selected anytime a sufficient voltage is present on MC. electrical characteristics over recommended operating free-air temperature range (unless 56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 otherwise noted) PARAMETER TEST CONDITIONS VOL Low-level output voltage (see Note 5) VOH High level output voltage High-level II Input current IOL = 1.4 mA IOH = – 50 µA IOH 0.9 VCC1 Low-level output current (see Note 5) High level output current High-level 50 VCC1–0.3 V ≤ VI ≤ VCC 1+ 0.3 V VCC1 + 0.3 V < VI ≤ 13 V 10 Supply current (operating ( i mode) d ) OSC POWER bit = 0 (see Note 9) ICC SYSCLK = 3 MHz See Notes 7 and 8 TMS370Cx50A TMS370Cx52A S l currentt Supply (operating mode) OSC POWER bit = 0 (see Note 9) TMS370Cx53A TMS370Cx56A TMS370Cx58A TMS370Cx58B TMS370Cx59A† Supply S l currentt (STANDBY mode) d ) OSC POWER bit = 0 (see Note 10) Supply y current (STANDBY ( mode)) OSC POWER bit = 1 (see Note 11) mA µA mA – 50 µA –2 mA 30 45 35 56 20 30 25 36 46 55 5 11 13 18 See Notes 7 and 8 TMS370Cx50A TMS370Cx52A TMS370Cx53A TMS370Cx56A TMS370Cx58A TMS370Cx58B TMS370Cx59A† 50 ± 10 1.4 TMS370Cx50A TMS370Cx52A µA 650 See Note 6 VOL = 0.4 V VOH = 0.9 VCC1 SYSCLK = 5 MHz V 10 VOH = 2.4 V TMS370Cx53A TMS370Cx56A TMS370Cx58A TMS370Cx58B UNIT V 2.4 0 V ≤ VI ≤ VCC1 I / O pins MAX 0.3 V < VI < VCC1–0.3 V 12 V ≤ VI ≤ 13 V IOL TYP 0.4 IOH = – 2 mA 0 V < VI ≤ 0.3 V MC MIN SYSCLK = 0.5 MHz See Notes 7 and 8 22 28 SYSCLK = 5 MHz, See Notes 7 and 8 12 17 SYSCLK = 3 MHz, See Notes 7 and 8 8 11 SYSCLK = 0.5 MHz, See Notes 7 and 8 2.5 3.5 SYSCLK = 3 MHz, See Notes 7 and 8 6 8.6 SYSCLK = 0.5 MHz, See Notes 7 and 8 2 3 mA mA mA mA Supply current (HALT mode) XTAL2 / CLKIN < 0.2 V, See Note 7 2 30 µA † TMS370Cx59 only operate up to 3 MHz SYSCLK NOTES: 5. In prior versions of the TMS370 family, the IOL current was equal to 2 mA for ports A, B, C, and D and the RESET pin. 6. Input current IPP is a maximum of 50 mA only when the EPROM is being programmed. 7. Single chip mode, ports configured as inputs or outputs with no load. All inputs ≤ 0.2 V or ≥ VCC – 0.2V. 8. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 9. Maximum operating current for TMS370Cx50A and TMS370Cx52A = 7.6 (SYSCLK) + 7 mA. Maximum operating current for TMS370Cx53A, TMS370Cx56A, TMS370Cx58A, and TMS370Cx58B = 10 (SYSCLK) + 5.8 mA. 10. Maximum standby current for TMS370Cx5xA = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0). 11. Maximum standby current for TMS370Cx5xA and TMS370Cx5xB = 2.24 (SYSCLK) + 1.9 mA. (OSC POWER bit = 1, valid only up to 3 MHz of SYSCLK.) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 57 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 PARAMETER MEASUREMENT INFORMATION XTAL2/CLKIN C1 (see Note B) XTAL1 Crystal/Ceramic Resonator (see Note A) XTAL2/CLKIN XTAL1 C3 (see Note B) C2 (see Note B) External Clock Signal NOTES: A. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period. B. The values of C1 and C2 are typically 15 pF and C3 is typically 50 pF. See the manufacturer’s recommendations for ceramic resonators. Figure 19. Recommended Crystal/Clock Connections Load Voltage 1.2 kΩ VO 20 pF Case 1: VO = VOH = 2.4 V; Load Voltage = 0 V Case 2: VO = VOL = 0.4 V; Load Voltage = 2.1 V NOTE A: All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated. Figure 20. Typical Output Load Circuit (see Note A) VCC VCC 300 Ω Pin Data 30 Ω Output Enable I/O 6 kΩ INT1 20 Ω 20 Ω GND GND Figure 21. Typlcal Buffer Circuitry 58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 PARAMETER MEASUREMENT INFORMATION timing parameter symbology Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: A Address RXD SCIRXD AR Array S Slave mode B Byte SC SYSCLK CI XTAL2/CLKIN SCC SCICLK D Data SIMO SPISIMO E EDS SOMI SPISOMI FE Final SPC SPICLK IE Initial TXD SCITXD M Master mode W Write PGM Program WT WAIT R Read Lowercase subscripts and their meanings are: c cycle time (period) r rise time d delay time su setup time f fall time v valid time h hold time w pulse duration (width) The following additional letters are defined as follows: H High L Low V Valid Z High impedance All timings are measured between high and low measurement points as indicated in Figure 22 and Figure 23. 0.8 VCC V (High) 2 V (High) 0.8 V (Low) 0.8 V (Low) Figure 22. XTAL2/CLKIN Measurement Points POST OFFICE BOX 1443 Figure 23. General Measurement Points • HOUSTON, TEXAS 77251–1443 59 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 external clocking requirements for clock divided by 4† NO. 1 2 3 4 PARAMETER MIN MAX 20 UNIT tw(Cl) tr(Cl) Pulse duration, XTAL2/CLKIN (see Note 12) Rise time, XTAL2/CLKIN 30 ns tf(CI) td(CIH-SCL) CLKIN‡ Fall time, XTAL2/CLKIN 30 ns Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency System clock¶ 2 ns 100 ns 20 MHz SYSCLK§ 0.5 5 MHz † For VIL and VIH, refer to recommended operating conditions. ‡ ’x59A operates up to 12 MHz CLKIN § ’x59A operates up to 3 MHz SYSCLK ¶ SYSCLK = CLKIN/4 NOTE 12: This pulse can be either a high pulse which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 1 XTAL2/CLKIN 2 3 4 SYSCLK Figure 24. External Clock Timing for Divide-by-4 external clocking requirements for clock divided by 1 (PLL)† NO. 1 2 3 4 PARAMETER MIN MAX Pulse duration, XTAL2/CLKIN (see Note 12) Rise time, XTAL2/CLKIN 30 ns tf(CI) td(CIH-SCH) CLKIN# Fall time, XTAL2/CLKIN 30 ns 100 ns SYSCLK§ 20 UNIT tw(Cl) tr(Cl) Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency System clock|| ns 2 5 2 5 MHz MHz † For VIL and VIH, refer to recommended operating conditions. § ’x59A operates up to 3 MHz SYSCLK # ’x59A operates up to 3 MHz CLKIN (for divide-by-1 clock option) || SYSCLK = CLKIN/1 NOTE 12: This pulse can be either a high pulse which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 1 XTAL2/CLKIN 2 3 4 SYSCLK Figure 25. External Clock Timing for Divide-by-1 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 general purpose output signal-switching time requirements MIN tr tf NOM MAX UNIT Rise time 30 ns Fall time 30 ns tr tf Figure 26. Signal-Switching Timing recommended EEPROM timing requirements for programming MIN tw(PGM)B tw(PGM)AR MAX UNIT Pulse duration, programming signal to ensure valid data is stored (byte mode) 10 ms Pulse duration, programming signal to ensure valid data is stored (array mode) 20 ms recommended EPROM operating conditions for programming VCC1 VPP Supply voltage IPP Supply current at MC pin during programming (VPP = 13 V) SYSCLK System clock Supply voltage at MC pin MIN NOM MAX 4.75 5.5 6 13 13.2 13.5 30 50 Divide-by-4 0.5 5 Divide-by-1 2 5 UNIT V V mA MHz recommended EPROM timing requirements for programming tw(EPGM) Pulse duration, programming signal (see Note 13) NOTE 13: Programming pulse is active when both EXE (EPCTL.0) and VPPS (EPCTL.6) are set. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MIN NOM MAX 0.40 0.50 3 UNIT ms 61 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 switching characteristics and timing requirements for external read and write (see Figure 27 and Figure 28)† NO. PARAMETER 5 tc Cycle time, time SYSCLK (system clock) 6 tw(SCL) tw(SCH) Pulse duration, SYSCLK low 7 8 td(SCL-A) Delay time, SYSCLK low to address R / W and OCF valid 9 tv(A) Valid time, address to EDS, CSE1, CSE2, CSH1, CSH2, CSH3, and CSPF low 10 tsu(D) Setup time, write data time to EDS high 11 th(EH-A) Hold time, address, R / W and OCF from EDS, CSE1, CSE2, CSH1, CSH2, CSH3, and CSPF high 12 th(EH-D)W 13 td(DZ-EL) 14 15 16 17 18 19 MAX 200 2 000 Divide-by-1 PLL 200 500 0.5tc–25 0.5tc 0.5tc 0.5tc+20 ns 0.25tc+75 ns Pulse duration, SYSCLK high UNIT ns ns 0.5tc–90 ns 0.75tc–80‡ ns 0.5tc–60 ns Hold time, write data time from EDS high 0.75tc+15 ns Delay time, data bus high impedance to EDS low (read cycle) 0.25tc–35 ns td(EH-D) td(EL-DV)R Delay time, EDS high to data bus enable (read cycle) 1.25tc–40 th(EH-D)R tsu(WT-SCH) Hold time, read time from EDS high th(SCH-WT) td(EL-WTV) Hold time, WAIT time from SYSCLK high 20 tw 21 td(AV-DV)R td(AV-WTV) 22 MIN Divide-by-4 clock ns tc–95‡ Delay time, EDS low to read data valid 0 ns 0.25tc+70§ Setup time, WAIT time to SYSCLK high ns 0 Delay time, EDS low to WAIT valid ns 0.5tc–60 Pulse duration, EDS, CSE1, CSE2, CSH1, CSH2, CSH3, and CSPF low tc–80‡ Delay time, address valid to read data valid Delay time, address valid to WAIT valid 1.5tc–85‡ ns ns tc+40‡ ns 1.5tc–115‡ tc–115 ns ns 23 td(AV-EH) Delay time, address valid to EDS high (end of write) ns † tc = system-clock cycle time = 1 / SYSCLK ‡ If wait states, PFWait, or the autowait feature is used, add tc to this value for each wait state invoked. § If the autowait feature is enabled, the WAIT input can assume a “don’t care” condition until the third cycle of the access. The WAIT signal must be synchronized with the high pulse of the SYSCLK signal while still conforming to the minimum setup time. 62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 7 5 6 SYSCLK 8 ADDRESS 11 20 EDS, CSE1, CSE2, CSH1, CSH2, CSH3, CSPF 14 9 21 13 16 15 DATA 370 Drives Data Read Data Drive Read Data Valid Read Data Disable 370 Drives Data 19 22 17 18 WAIT R/W OCF Figure 27. Switching Characteristics and Timing Requirements for External-Read POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 63 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 7 5 6 SYSCLK 8 ADDRESS 11 20 EDS, CSE1, CSE2, CSH1, CSH2, CSH3, CSPF 9 10 23 12 DATA 19 22 17 18 WAIT R/W Figure 28. Switching Characteristics and Timing Requirements for External-Write 64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 SCI1 isosynchronous† mode timing characteristics and requirements for internal clock (see Note 14 and Figure 29) NO. 24 25 26 27 28 29 MIN tc(SCC) tw(SCCL) Cycle time, SCICLK 2tc tc – 45 tw(SCCH) td(SCCL-TXDV) Pulse duration, SCICLK high tv(SCCH-TXD) tsu(RXD-SCCH) Valid time, SCITXD data valid after SCICLK high Pulse duration, SCICLK low tc – 45 – 50 Delay time, SCITXD valid after SCICLK low Setup time, SCIRXD to SCICLK high 30 tv(SCCH-RXD) Valid time, SCIRXD data valid after SCICLK high NOTE 14: tc = system-clock cycle time = 1 / SYSCLK tw(SCCH) – 50 0.25 tc + 145 0 MAX UNIT 131 072tc ns 0.5tc(SCC)+45 0.5tc(SCC)+45 ns 60 ns ns ns ns ns 24 26 25 SCICLK 28 27 Data Valid SCITXD 29 30 Data Valid SCIRXD Figure 29. SCI1 Isosynchronous† Mode Timing for Internal Clock † Isosynchronous = Isochronous POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 65 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 SCI1 isosynchronous† mode timing characteristics and requirements for external clock (see Note 14 and Figure 30) NO. 31 32 33 34 35 36 MIN tc(SCC) tw(SCCL) Cycle time, SCICLK tw(SCCH) td(SCCL-TXDV) Pulse duration, SCICLK high tv(SCCH-TXD) tsu(RXD-SCCH) Valid time, SCITXD data valid after SCICLK high Pulse duration, SCICLK low 37 tv(SCCH-RXD) Valid time, SCIRXD data after SCICLK high NOTE 14: tc = system-clock cycle time = 1 / SYSCLK tw(SCCH) 40 2tc 31 33 32 SCICLK 35 34 Data Valid 36 37 Data Valid SCIRXD Figure 30. SCI1 Isosynchronous† Timing for External Clock † Isosynchronous = Isochronous 66 POST OFFICE BOX 1443 ns ns 4.25tc + 145 Setup time, SCIRXD to SCICLK high • HOUSTON, TEXAS 77251–1443 UNIT ns tc + 120 Delay time, SCITXD valid after SCICLK low SCITXD MAX 10tc 4.25tc + 120 ns ns ns ns TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 SPI master mode external timing characteristics and requirements (see Note 14 and Figure 31) NO. 38 tc(SPC)M tw(SPCL)M Cycle time, SPICLK tw(SPCH)M td(SPCL-SIMOV)M Pulse duration, SPICLK high Valid time, SPISIMO data valid after SPICLK high (polarity =1) 43 tv(SPCH-SIMO)M tsu(SOMI-SPCH)M 44 tv(SPCH-SOMI)M 39 40 41 42 Pulse duration, SPICLK low Delay time, SPISIMO valid after SPICLK low (polarity = 1) Setup time, SPISOMI to SPICLK high (polarity = 1) MIN MAX UNIT 2tc tc – 45 256tc ns 0.5tc(SPC)+45 0.5tc(SPC)+45 ns tc – 55 – 65 tw(SPCH) – 50 0.25 tc + 150 Valid time, SPISOMI data valid after SPICLK high (polarity = 1) 0 50 ns ns ns ns ns NOTE 14: tc = system-clock cycle time = 1 / SYSCLK 38 40 39 SPICLK 41 42 Data Valid SPISIMO 43 44 SPISOMI Data Valid NOTE A: The diagram shows polarity = 1. SPICLK is inverted when polarity = 0. Figure 31. SPI Master External Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 67 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 SPI slave mode external timing characteristics and requirements (see Note 14 and Figure 32) NO. 45 46 47 48 49 50 MIN tc(SPC)S tw(SPCL)S Cycle time, SPICLK Pulse duration, SPICLK low 8tc 4tc – 45 tw(SPCH)S td(SPCL-SOMIV)S Pulse duration, SPICLK high 4tc – 45 tv(SPCH-SOMI)S tsu(SIMO-SPCH)S Valid time, SPISOMI data valid after SPICLK high (polarity =1) Delay time, SPISOMI valid after SPICLK low (polarity = 1) Setup time, SPISIMO to SPICLK high (polarity = 1) SPICLK 49 Data Valid 50 51 Data Valid NOTE A: The diagram shows polarity = 1. SPICLK is inverted when polarity = 0. 68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ns 3.25tc + 130 ns ns ns 47 Figure 32. SPI-Slave External Timing 0.5tc(SPC)S+45 0.5tc(SPC)S+45 3tc + 100 46 SPISOMI ns ns 45 SPISIMO UNIT tw(SPCH)S 0 51 tv(SPCH-SIMO)S Valid time, SPISIMO data after SPICLK high (polarity = 1) NOTE 14: tc = system-clock cycle time = 1 / SYSCLK 48 MAX ns TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 The ADC1 has a separate power bus for its analog circuitry. These pins are referred to as VCC3 and VSS3 . The purpose is to enhance ADC1 performance by preventing digital switching noise of the logic circuitry that can be present on VSS1 and VCC1 from coupling into the ADC1 analog stage. All ADC1 specifications are given with respect to VSS3 unless otherwise noted. Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-bits (256 values) Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Yes Output conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00h to FFh (00 for VI ≤ VSS3 ≤; FF for VI ≤ Vref) Conversion time (excluding sample time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 tc recommended operating conditions VCC3 Analog supply voltage VSS3 Vref Analog ground MIN NOM 4.5 5 VCC1–0.3 VSS1–0.3 Non-VCC3 reference† Analog input for conversion 2.5 MAX UNIT 5.5 VCC1 + 0.3 VSS1+0.3 VCC3 VSS3 † Vref must be stable, within ± 1/2 LSB of the required resolution, during the entire conversion time. VCC3 + 0.1 Vref V V V V operating characteristics over recommended ranges operating conditions PARAMETER MIN Absolute accuracy‡ VCC3 = 5.5 V VCC3 = 5.5 V Differential/integral linearity error‡§ ICC3 II Zreff Analog supply current Input current, AN0 – AN7 Vref = 5.1 V Vref = 5.1 V UNIT ± 1.5 LSB ± 0.9 LSB Converting 2 mA Nonconverting 5 µA 0 V ≤ VI ≤ 5.5 V 2 µA 1 mA SYSCLK ≤ 3 MHz 24 kΩ 3 MHz < SYSCLK ≤ 5 MHz 10 Iref input charge current Source impedance of Vreff MAX kΩ ‡ Absolute resolution = 20 mV. At Vref = 5 V, this is one LSB. As Vref decreases, LSB size decreases; therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase. § Excluding quantization error of 1/2 LSB POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 69 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 The ADC1 module allows complete freedom in design of the sources for the analog inputs. The period of the sample time is user-defined so that the high-impedance can be accommodated without penalty to the low-impedance sources. The sample period begins when the SAMPLE START bit of the ADC1 control register (ADCTL.6) is set to 1. The end of the signal sample period occurs when the conversion bit (CONVERT START, ADCTL.7) is set to 1. After a hold time, the converter will reset the SAMPLE START and CONVERT START bits, signaling that a conversion has started and that the analog signal can be removed. analog timing requirements MIN tsu(S) th(AN) Setup time, analog to sample command 0 MAX UNIT ns Hold time, analog input from start of conversion 18tc ns tw(S) Pulse duration, sample time per kilohm of source impedance† 1 µs/kΩ † The value given is valid for a signal with a source impedance > 1 kΩ. If the source impedance is < 1 kΩ, use a minimum sampling time of 1µs. Analog Stable Analog In tsu(S) Sample Start th(AN) tw(S) Convert Start Figure 33. Analog Timing 70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 Table 26 is designed to aid the user in referencing a device part number to a mechanical drawing. The table shows a cross-reference of the device part number to the TMS370 generic package name and the associated mechanical drawing by drawing number and name. ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Table 26. TMS370Cx5x Family Package Type and Mechanical Cross-Reference PKG TYPE (mil pin spacing) PKG TYPE NO. AND MECHANICAL NAME TMS370 GENERIC NAME DEVICE PART NUMBERS PLASTIC LEADED CHIP CARRIER (PLCC) FN(S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER TMS370C050AFNA TMS370C050AFNL TMS370C050AFNT TMS370C150AFNT TMS370C250AFNT TMS370C350AFNA TMS370C350AFNL TMS370C350AFNT TMS370C052AFNA TMS370C052AFNL TMS370C052AFNT TMS370C352AFNA TMS370C352AFNL TMS370C352AFNT TMS370C452AFNA TMS370C452AFNL TMS370C452AFNT TMS370C353AFNA TMS370C353AFNL TMS370C353AFNT TMS370C056AFNA TMS370C056AFNL TMS370C056AFNT TMS370C156AFNT TMS370C256AFNT TMS370C356AFNA TMS370C356AFNL TMS370C356AFNT TMS370C456AFNA TMS370C456AFNL TMS370C456AFNT TMS370C756AFNT TMS370C058AFNA TMS370C058AFNL TMS370C058AFNT TMS370C358AFNA TMS370C358AFNL TMS370C358AFNT TMS370C758AFNT TMS370C758BFNT TMS370C059AFNA TMS370C059AFNL TMS370C059AFNT TMS370C759AFNT FZ – 68 pin (50-mil pin spacing) CERAMIC LEADED CHIP CARRIER (CLCC) FZ(S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER SE370C756AFZT SE370C758AFZT SE370C758BFZT SE370C759AFZT JN – 64 pin (70-mil pin spacing) CERAMIC SHRINK DUAL-IN-LINE PACKAGE (CSDIP) JN(R-CDIP-T64) CERAMIC DUAL-IN-LINE PACKAGE SE370C756AJNT SE370C758AJNT SE370C758BJNT FN – 68 pin (50-mil pin spacing) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 71 TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 Table 26. TMS370Cx5x Family Package Type and Mechanical Cross-Reference (Continued) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ PKG TYPE (mil pin spacing) NM – 64 pin (70-mil pin spacing) 72 TMS370 GENERIC NAME PLASTIC SHRINK DUAL-IN-LINE PACKAGE (PSDIP) POST OFFICE BOX 1443 PKG TYPE NO. AND MECHANICAL NAME NM(R-PDIP-T64) PLASTIC SHRINK DUAL-IN-LINE PACKAGE • HOUSTON, TEXAS 77251–1443 DEVICE PART NUMBERS TMS370C050ANMA TMS370C050ANML TMS370C050ANMT TMS370C350ANMA TMS370C350ANML TMS370C350ANMT TMS370C052ANMA TMS370C052ANML TMS370C052ANMT TMS370C352ANMA TMS370C352ANML TMS370C352ANMT TMS370C056ANMA TMS370C056ANML TMS370C056ANMT TMS370C356ANMA TMS370C356ANML TMS370C356ANMT TMS370C756ANMT TMS370C058ANMA TMS370C058ANML TMS370C058ANMT TMS370C358ANMA TMS370C358ANML TMS370C358ANMT TMS370C758ANMT TMS370C758BNMT PACKAGE OPTION ADDENDUM www.ti.com 5-May-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) SE370C756AFZT OBSOLETE JLCC FZ 68 TBD Call TI Call TI SE370C756AJNT OBSOLETE CDIP JN 64 TBD Call TI Call TI SE370C758AFZT OBSOLETE JLCC FZ 68 TBD Call TI Call TI SE370C758AJNT OBSOLETE CDIP JN 64 TBD Call TI Call TI SE370C758BFZT OBSOLETE JLCC FZ 68 TBD Call TI Call TI SE370C758BJNT OBSOLETE CDIP JN 64 TBD Call TI Call TI SE370C759AFZT OBSOLETE JLCC FZ 68 TBD Call TI Call TI TMS370C156AFNT OBSOLETE PLCC FN 68 TBD Call TI Call TI TMS370C256AFNT OBSOLETE PLCC FN 68 TBD Call TI Call TI Op Temp (°C) Device Marking (4/5) TMS370C256AFNT @ 1986 TI TMS370C356AFNT OBSOLETE PLCC FN 68 TBD Call TI Call TI TMS370C356ANMT OBSOLETE SDIP NM 64 TBD Call TI Call TI TMS370C756AFNT OBSOLETE PLCC FN 68 TBD Call TI Call TI @1986 TI TMS370C756AFNT TMS370C758AFNTG4 OBSOLETE PLCC FN 68 TBD Call TI Call TI TMS370C758AFNT @1986 TI TMS370C758ANMT OBSOLETE SDIP NM 64 TBD Call TI Call TI TMS370C758BFNT OBSOLETE PLCC FN 68 TBD Call TI Call TI TMS370C758BNMT OBSOLETE SDIP NM 64 TBD Call TI Call TI @1986 TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 5-May-2015 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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