TMS370C712ANT

TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 D CMOS/EEPROM/EPROM Technologies on D D D D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D3 RESET D4 SPISOMI SPICLK SPISIMO T1IC/CR T1PWM T1EVT MC INT3 INT2 INT1 D5 FZ AND FN PACKAGES (TOP VIEW) V CC A7 D7 D6 D3 RESET D4 D D6 D7 A7 VCC XTAL2/CLKIN XTAL1 A6 A5 A4 A3 A2 VSS A1 A0 4 3 2 1 28 27 26 XTAL2/CLKIN XTAL1 A6 A5 A4 A3 A2 5 6 7 8 9 10 11 25 24 23 22 21 20 19 12 13 14 15 16 1718 SPISOMI SPICLK SPISIMO T1IC/CR T1PWM T1EVT MC VSS A1 A0 D5 INT1 INT2 INT3 D a Single Device -- Mask-ROM Devices for High-Volume Production -- One-Time-Programmable (OTP) EPROM Devices for Low-Volume Production -- Reprogrammable-EPROM Devices for Prototyping Purposes Internal System Memory Configurations -- On-Chip Program Memory Versions -- ROM: 2K, 4K, or 8K Bytes -- EPROM: 8K Bytes -- Data EEPROM: 256 Bytes -- Static RAM: 128 or 256 Bytes Usable as Registers Flexible Operating Features -- Low-Power Modes: STANDBY and HALT -- Commercial, Industrial, and Automotive Temperature Ranges -- Clock Options -- Divide-by-1 (2 MHz--5 MHz SYSCLK) Phase-Locked Loop (PLL) -- Divide-by-4 (0.5 MHz--5 MHz SYSCLK) -- Supply Voltage (VCC) 5 V 10% 16-Bit General Purpose Timer -- Software Configurable as a 16-Bit Event Counter, or a 16-Bit Pulse Accumulator, or a 16-Bit Input Capture Functions, or Two Compare Registers, or a Self-Contained PWM Function -- Software Programmable Input Polarity -- 8-Bit Prescaler, Providing a 24-Bit Real-Time Timer On-Chip 24-Bit Watchdog Timer -- EPROM/OTP Devices: -- EPROM ’712A Standard Watchdog -- EPROM ’712B Hard Watchdog -- Mask-ROM Devices: Hard Watchdog, Simple Counter, or Standard Watchdog Flexible Interrupt Handling -- Two Software Programmable Interrupt Levels -- Global-and Individual-Interrupt Masking -- Programmable Rising- or Falling-Edge Detect -- Individual Interrupt Vectors Serial Peripheral Interface (SPI) -- Variable-Length High-Speed Shift Register JD AND N PACKAGES (TOP VIEW) -- Synchronous Master/Slave Operation D TMS370 Series Compatibility ----- D D Register-to-Register Architecture 128 or 256 General-Purpose Registers 14 Powerful Addressing Modes Instructions Upwardly Compatible With All TMS370 Devices CMOS/TTL Compatible I/O Pins/Packages -- All Peripheral Function Pins Software Configurable for Digital I/O -- 21 Bidirectional Pins, 1 Input Pin -- 28-Pin Plastic and Ceramic DIP, or Leaded Chip Carrier (LCC) Packages Workstation/PC-Based Development System -- C Compiler and C Source Debugger -- Real-Time In-Circuit Emulation -- Extensive Breakpoint/Trace Capability -- Multi-Window User Interface -- Microcontroller Programmer Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 1 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 Pin Descriptions 28 PINS DIP and LCC NAME I/O† DESCRIPTION NO. A0 A1 A2 A3 A4 A5 A6 A7 14 13 11 10 9 8 7 3 I/O Port A is a general-purpose bidirectional I/O port. D3 D4 D5 D6 D7 28 26 15 1 2 I/O Port D is a general-purpose bidirectional I/O port. D3 is also configurable as SYSCLK. INT1 INT2 INT3 16 17 18 I I/O I/O External interrupt (non-maskable or maskable)/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin T1IC/CR T1PWM T1EVT 22 21 20 I/O Timer1 input capture/counter reset input pin/general-purpose bidirectional pin Timer1 PWM output pin/general-purpose bidirectional pin Timer1 external event input pin/general-purpose bidirectional pin SPISOMI SPISIMO SPICLK 25 23 24 I/O SPI slave output pin, master input pin/general-purpose bidirectional pin SPI slave input pin, master output pin/general-purpose bidirectional pin SPI bidirectional serial clock pin/general-purpose bidirectional pin RESET 27 I/O System reset bidirectional pin; as input pin, RESET initializes the microcontroller; as open-drain output, RESET indicates that an internal failure was detected by watchdog or oscillator fault circuit. MC 19 I Mode control input pin; enables EEPROM write protection override (WPO) mode, also EPROM VPP XTAL2/CLKIN XTAL1 5 6 I O Internal oscillator crystal input/External clock source input Internal oscillator output for crystal VCC 4 Positive supply voltage VSS 12 Ground reference † I = input, O = output All trademarks are the property of their respective owners. 2 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 functional block diagram INT1 INT2 INT3 Interrupts XTAL1 XTAL2/ CLKIN Clock Options: Divide-By-4 or Divide-By-1 (PLL) CPU Program Memory ROM: 2K, 4K, or 8K Bytes EPROM: 8K Bytes MC RESET System Control Serial Peripheral Interface RAM 128 or 256 Bytes SPISOMI SPISIMO SPICLK Data EEPROM 0 or 256 Bytes Timer 1 T1IC/CR T1EVT T1PWM Watchdog VCC Port A Port D 8 VSS 5 description The TMS370C010, TMS370C012, TMS370C311, TMS370C310, TMS370C312, TMS370C712, and SE370C712 devices are members of the TMS370 family of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx1x refers to these devices. The TMS370 family provides cost-effective real-time system control through integration of advanced peripheral-function modules and various on-chip memory configurations. The TMS370Cx1x family of devices is implemented using high-performance silicon-gate CMOS EPROM and EEPROM technologies. Low-operating power, wide-operating temperature range, and noise immunity of CMOS technology coupled with the high performance and extensive on-chip peripheral functions make the TMS370Cx1x devices attractive for system designs for automotive electronics, industrial motors, computer peripheral controls, telecommunications, and consumer applications. All TMS370Cx1x devices contain the following on-chip peripheral modules: D Serial peripheral interface (SPI) D One 24-bit general-purpose watchdog timer D One 16-bit general-purpose timer with an 8-bit prescaler POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 3 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 description (continued) Table 1 provides a memory configuration overview of the TMS370Cx1x devices. Table 1. Memory Configurations DEVICE PROGRAM MEMORY (BYTES) ROM EPROM DATA MEMORY (BYTES) RAM EEPROM 28 PIN PACKAGES TMS370C010A 4K — 128 256 FN -- PLCC N -- PDIP TMS370C012A 8K — 256 256 FN -- PLCC N -- PDIP TMS370C311A 2K — 128 -- FN -- PLCC N -- PDIP TMS370C310A 4K — 128 -- FN -- PLCC N -- PDIP TMS370C312A 8K — 128 -- FN -- PLCC N -- PDIP TMS370C712A, TMS370C712B — 8K 256 256 FN -- PLCC N --PDIP SE370C712A†, SE370C712B† — 8K 256 256 FZ -- CLCC JD -- CDIP † System evaluators and development are for use only in prototype environment and their reliability has not been characterized. The suffix letter (A or B) appended to the device names shown in the device column of Tables 1 and 2 indicates the configuration of the device. ROM or EPROM devices have different configurations as indicated in Table 2. ROM devices with the suffix letter A are configured through a programmable contact during manufacture. Table 2. Suffix Letter Configuration DEVICE‡ WATCHDOG TIMER CLOCK LOW-POWER MODE EPROM A Standard Divide-by-4 (Standard oscillator) Enabled EPROM B Hard Divide-by-1 (PLL) Enabled Divide-by-4 Divide by 4 or Divide-by-1 Divide by 1 (PLL) Enabled or disabled Standard ROM A Hard Simple ‡ Refer to the “device numbering conventions” section for device nomenclature and to the “device part numbers” section for ordering. The 2K bytes, 4K bytes, and 8K bytes of mask-programmable ROM in the associated TMS370Cx1x devices are replaced in the TMS370C712 with 8K bytes of EPROM. All other available memory and on-chip peripherals are identical, with the exception of no data EEPROM on the TMS370C311, TMS370C310, and TMS370C312 devices. The OTP (TMS370C712) device and reprogrammable (SE370C712) device are available. TMS370C712 OTP devices are available in plastic packages. This microcontroller is effective to use for immediate production updates for other members of the TMS370Cx1x family or for low volume production runs when the mask charge or cycle time for the low-cost mask ROM devices is not practical. The SE370C712 has a windowed ceramic package to allow reprogramming of the program EPROM memory during the development/prototyping phase of design. The SE370C712 devices allow quick updates to breadboards and prototype systems while iterating initial designs. 4 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 description (continued) The TMS370Cx1x family provides two low-power modes (STANDBY and HALT) for applications where low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In the STANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HALT mode, all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both low-power modes. The TMS370Cx1x features advanced register-to-register architecture that allows direct arithmetic and logical operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to the contents of register 47 and store the result in register 47). The TMS370Cx1x family is fully instruction-set-compatible, providing easy transition between members of the TMS370 8-bit microcontroller family. The SPI provides a convenient method of serial interaction for high-speed communications between simpler shift register-type devices, such as display drivers, analog-to-digital (A/D) converters, PLL, input/output (I/O) expansion, or other microcontrollers in the system. The TMS370Cx1x family provides the system designer with economical, efficient solution to real-time control applications. The TMS370 family extended development system (XDS) and compact development tool (CDT) solve the challenge of efficiently developing the software and hardware required to design the TMS370Cx1x into an ever-increasing number of complex applications. The application source code can be written in assembly and C language, and the output code can be generated by the linker. The TMS370 family XDS development tool communicates through a standard RS-232-C interface with an existing personal computer. This allows the use of the PC’s editors and software utilities already familiar to the designer. The TMS370 family XDS emphasizes ease-of-use through extensive menus and screen windowing so that a system designer can begin developing software with minimal training. Precise real-time, in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as reducing the time-to-market cycle. The TMS370Cx1x family together with the TMS370 family XDS22, CDT370, design kit, starter kit, software tools, the SE370C712 reprogrammable devices, comprehensive product documentation, and customer support provide a complete solution to the needs of the system designer. central processing unit (CPU) The CPU on the TMS370Cx1x device is the high-performance 8-bit TMS370 CPU module. The ’x1x implements an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete ’x1x instruction map is shown in Table 17 in the TMS370Cx1x instruction set overview section. The ’370Cx1x CPU architecture provides the following components: CPU registers: D A stack pointer that points to the last entry in the memory stack D A status register that monitors the operation of the instructions and contains the global interrupt-enable bits D A program counter (PC) that points to the memory location of the next instruction to be executed XDS and CDT are trademarks of Texas Instruments Incorporated. POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 5 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 central processing unit (CPU) (continued) Figure 1 illustrates the CPU registers and memory blocks. Program Counter 15 Stack Pointer (SP) 7 Legend: C=Carry N=Negative Z=Zero 0 Status Register (ST) C N Z V 7 6 5 4 IE2 IE1 3 2 1 0 V=Overflow IE2=Level 2 interrupts Enable IE1=Level 1 interrupts Enable 0 RAM (Includes up to 256-Byte Registers File) 0000h R0(A) 128-Byte RAM (0000h--007Fh) 0001h R1(B) 256-Byte RAM (0000h--00FFh) 0002h R2 Reserved† 0003h R3 Peripheral File Reserved† 256-Byte Data EEPROM Not Available‡ 007Fh R127 8K-Byte ROM/EPROM (6000h--7FFFh) 4K-Byte ROM (7000h--7FFFh) 0000h 007Fh 0080h 00FFh 0100h 100Fh 1010h 104Fh 1050h 1EFFh 1F00h 1FFFh 2000h 5FFFh 6000h 6FFFh 7000h 77FFh 7800h 2K-Byte ROM (7800h--7FFFh) 00FFh Interrupts and Reset Vectors; Trap Vectors R255 7FBFh 7FC0h 7FFFh † Reserved means the address space is reserved for future expansion. ‡ Not available means the address space is not accessible. Figure 1. Programmer’s Model A memory map includes: D 128- or 256-byte general-purpose RAM that can be used for data memory storage, program instructions, general purpose register, or the stack D A peripheral file that provides access to all internal peripheral modules, system-wide control functions, and EEPROM/EPROM programming control D 256-byte EEPROM module, that provides in-circuit programmability and data retention in power-off conditions D 2K-, 4K-, or 8K-byte ROM or 8K-byte EPROM stack pointer (SP) The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read/write memory. Typically, the stack is used to store the return address on subroutine calls as well as the status register (ST) contents during interrupt sequences. The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the on-chip RAM. 6 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 central processing unit (CPU) (continued) status register (ST) The ST monitors the operation of the instructions and contains the global interrupt-enable bits. The ST includes four status bits (condition flags) and two interrupt-enable bits. D The four status bits indicate the outcome of the previous instruction; conditional instructions (for example, the conditional-jump instructions) use the status bits to determine program flow. D The two interrupt-enable bits control the two interrupt levels. The ST, status-bit notation, and status-bit definitions are shown in Table 3. Table 3. Status Registers 7 6 5 4 3 2 1 0 C N Z V IE2 IE1 Reserved Reserved RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R = read, W = write, 0 = value after reset program counter (PC) The contents of the PC point to the memory location of the next instruction to be executed. The PC consists of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These registers contains the most significant byte (MSbyte) and least significant byte (LSbyte) of a 16-bit address. During reset, the contents of the reset vector (7FFEh, 7FFFh) are loaded into the PC. The PCH (MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 6000h as the contents of the reset vector. Program Counter (PC) Memory 0000h 7FFEh 60 7FFFh 00 PCH PCL 60 00 Figure 2. Program Counter After Reset memory map The TMS370Cx1x architecture is based on the Von Neuman architecture, where the program memory and data memory share a common address space. All peripheral input/output is memory mapped in this same common address space. As shown in Figure 3, the TMS370Cx1x provides memory-mapped RAM, ROM, data EEPROM, I/O pins, peripheral functions, and system-interrupt vectors. The peripheral file contains all I/O port control, peripheral status and control, EEPROM, EPROM, and system-wide control functions. The peripheral file is located between 1010h to 104Fh and is divided logically into four peripheral file frames of 16 bytes each. Each on-chip peripheral is assigned to a separate frame through which peripheral control and data information is passed. POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 7 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 TMS370Cx1x CPU (continued) Peripheral File Control Registers 0000h 007Fh 0080h 00FFh 0100h 100Fh 1010h System Control 1010h -- 101Fh 128-Byte RAM (Register File/Stack) Digital Port Control 1020h -- 102Fh SPI Control 1030h -- 103Fh 256-Byte RAM (Register File/Stack) Reserved† Timer 1 Peripheral Control 1040h -- 104Fh Peripheral File 104Fh 1050h 1EFFh 1F00h Reserved† 256-Byte Data EEPROM 1FFFh 2000h Vectors Not Available‡ 5FFFh 6000h 6FFFh 7000h 77FFh 7800h 7FBFh 7FC0h 7FFFh 8000h Trap 15--0 7FC0h -- 7FDFh Reserved 7FE0h -- 7FF3h Timer 1 7FF4h -- 7FF5h Serial Peripheral Interface 7FF6h -- 7FF7h Interrupt 3 7FF8h -- 7FF9h Interrupt 2 7FFAh -- 7FFBh Interrupt 1 7FFCh -- 7FFDh Reset 7FFEh -- 7FFFh 8K Bytes Start at 6000h 4K Bytes Start at 7000h 2K Bytes Start at 7800h Interrupts and Reset Vectors; Trap Vectors Not Available‡ FFFFh † Reserved means that the address space is reserved for future expansion. ‡ Not available means that the address space is not accessible. Figure 3. TMS370Cx1x Memory Map RAM/register file (RF) Locations within the RAM address space can serve as the RF, general-purpose read/write memory, program memory, or the stack instructions. The TMS370Cx10, TMS370Cx11, and TMS370C312 contain 128 bytes of internal RAM mapped beginning at location 0000h (R0) and continuing through location 007Fh (R127) which is shown in Table 4 along with ’712 devices. Table 4. RAM Memory Map ’x10, ’x11 AND ’312 RAM size Memory mapped ’712 128 bytes 256 bytes 0000h--007Fh 0000h--00FFh The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the stack pointer is contained in register B. Registers A and B are the only registers cleared on reset. 8 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 peripheral file (PF) The TMS370Cx1x control registers contain all the registers necessary to operate the system and peripheral modules on the device. The instruction set includes some instructions that access the PF directly. These instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal designator or P for a decimal designator. For example, the system-control register 0 (SCCR0) is located at address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 5 shows the TMS370Cx1x PF address map. Table 5. TMS370Cx1x Peripheral File Address Map ADDRESS RANGE PERIPHERAL FILE DESIGNATOR 1000h--100Fh P000--P00F Reserved 1010h--101Fh P010--P01F System and EPROM/EEPROM control registers 1020h--102Fh P020--P02F Digital I/O port control registers 1030h--103Fh P030--P03F SPI registers 1040h--104Fh P040--P04F Timer 1 registers 1050h--10FFh P050--P0FF Reserved DESCRIPTION data EEPROM The TMS370Cx1x devices, containing 256 bytes of data EEPROM, have memory mapped beginning at location 1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by the data EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm examples are available in the TMS370 Family User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B). The data EEPROM features include the following: D Programming: -- Bit-, byte-, and block-write/erase modes -- Internal charge pump circuitry. No external EEPROM programming voltage supply is needed. -- Control register: Data EEPROM programming is controlled by the DEECTL located in the PF frame beginning at location P01A. See Table 6. -- In-circuit programming capability. There is no need to remove the device to program. D Write protection. Writes to the data EEPROM are disabled during the following conditions. -- Reset. All programming of the data EEPROM module is halted. -- Write protection active. There is one write-protect bit per 32-byte EEPROM block. -- Low-power mode operation D Write protection can be overridden by applying 12 V to MC. Table 6. Data EEPROM and PROGRAM EPROM Control Registers Memory Map ADDRESS SYMBOL P01A DEECTL P01B — P01C EPCTL POST OFFICE BOX 1443 NAME Data EEPROM Control Register Reserved Program EPROM Control Register  HOUSTON, TEXAS 77251--1443 9 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 program EPROM† The TMS370C712 device contains 8K bytes of EPROM mapped, beginning at location 6000h and continuing through location 7FFFh as shown in Figure 3. Reading the program EPROM modules is identical to reading other internal memory. During programming, the EPROM is controlled by the EPROM control register (EPCTL). The program EPROM module features include: D Programming -- In-circuit programming capability if VPP is applied to MC -- Control register: EPROM programming is controlled by the EPROM control register (EPCTL) located in the peripheral file (PF) frame at location P01Ch as shown in Table 6. D Write protection: Writes to the program EPROM are disabled under the following conditions: -- Reset: All programming to the EPROM module is halted -- Low-power modes -- 13 V not applied to MC program ROM† The program ROM consists of 2K to 8K bytes of mask programmable read-only memory (see Table 7). The program ROM is used for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device fabrication. Table 7. Program ROM Memory Map ’x11 ROM size Memory mapped ’x10 ’x12 2K bytes 4K bytes 8K bytes 7800h--7FFFh 7000h--7FFFh 6000h--7FFFh system reset The system-reset operation ensures an orderly start-up sequence for the TMS370Cx1x CPU-based device. There are up to three different actions that can cause a system reset to the device. Two of these actions are generated internally, while one (RESET pin) is controlled externally. These actions are as follows: D Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key register, or if the re-initialization does not occur before the watchdog timer timeout . See the TMS370 Family User’s Guide (literature number SPNU127) for more information. D Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range. See the TMS370 Family User’s Guide (literature number SPNU127) for more information. D External RESET pin. A low level signal can trigger an external reset. To ensure a reset, the external signal should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the TMS370 Family User’s Guide (literature number SPNU127) for more information. Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK cycles. This allows the ’x1x device to reset external system components. Additionally, if a cold start (VCC is off for several hundred milliseconds) condition or oscillator failure occurs or the RESET pin is held low, then the reset logic holds the device in a reset state for as long as these actions are active. † 10 Memory addresses 7FF8h through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions are located between addresses 7FC0h and 7FDFh. POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 system reset (continued) After a reset, the program can check the oscillator-fault flag (OSC FLT FLAG, SCCR0.4), the cold-start flag (COLD START, SCCR0.7) and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source of the reset. A reset does not clear these flags. Table 8 depicts the reset sources. Table 8. Reset Sources ADDRESS PF BIT NO. SCCR0 REGISTER 1010h P010 7 COLD START CONTROL BIT Cold (power-up) SOURCE OF RESET SCCR0 1010h P010 4 OSC FLT FLAG Oscillator out of range T1CTL2 104Ah P04A 5 WD OVRFL INT FLAG Watchdog timer timeout Once a reset is activated, the following sequence of events occurs: 1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state). 2. Register A and B are initialized to 00h (no other RAM is changed). 3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL. 4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH. 5. Program execution begins with an opcode fetch from the address pointed to the PC. The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control register bits are initialized to their reset state. POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 11 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 interrupts The TMS370 family software-programmable interrupt structure permits flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt level 2. The two priority levels can be masked independently by the global interrupt mask bits (IE1 and IE2) of the ST. EXT INT 3 INT 3 EXT INT 2 TIMER1 INT 2 Overflow INT3 PRI Compare1 Ext Edge INT2 PRI Compare2 EXT INT1 Input Capture CPU INT1 Watchdog NMI Priority INT1 PRI T1 PRI Logic STATUS REG IE1 IE2 Enable SPI INT Level 1 INT Level 2 INT SPI PRI SPI Figure 4. Interrupt Control Each system interrupt is configured independently to either the high- or low-priority chain by the application program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of the system interrupt. However, since each system interrupt is selectively configured on either the high- or low-priority-interrupt chain, the application program can elevate any system interrupt to the highest priority. Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority 12 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 interrupts (continued) chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending-interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions. The TMS370Cx1x has five hardware system interrupts (plus RESET) as shown in Table 9. Each system interrupt has a dedicated vector located in program memory through which control is passed to the interrupt service routines. A system interrupt may have multiple interrupt sources. All of the interrupt sources are individually maskable by local interrupt enable control bits in the associated peripheral file. Each interrupt source FLAG bit is individually readable for software polling or to determine which interrupt source generated the associated system interrupt. Two of the system interrupts are generated by on-chip peripheral functions, and three external interrupts are supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3 control registers in peripheral file frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked by the individual or global enable mask bits. The INT1 NMI bit is protected during non-privileged operation and, therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupts INT2 and INT3 can be software configured as general purpose input/output pins if the interrupt function is not required (INT1 can be similarly configured as an input pin). Table 9. Hardware System Interrupts INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT VECTOR ADDRESS PRIORITY† RESET‡ 7FFEh, 7FFFh 1 External RESET Watchdog Overflow Oscillator Fault Detect COLD START WD OVRFL INT FLAG OSC FLT FLAG External INT1 INT1 FLAG INT1‡ 7FFCh, 7FFDh 2 External INT2 INT2 FLAG INT2‡ 7FFAh, 7FFBh 3 External INT3 INT3 FLAG INT3‡ 7FF8h, 7FF9h 4 SPI Receiver (Rx)/Transmitter (Tx) Data Complete SPI INT FLAG SPIINT 7FF6h, 7FF7h 5 Timer 1 Overflow Timer 1 Compare 1 Timer 1 Compare 2 Timer 1 External Edge Timer 1 Input Capture 1 Watchdog Overflow T1 OVRFL INT FLAG T1C1 INT FLAG T1C2 INT FLAG T1EDGE INT FLAG T1IC1 INT FLAG WD OVRFL INT FLAG T1INT§ 7FF4h, 7FF5h 6 † Relative priority within an interrupt level Release microcontroller from STANDBY and HALT low-power modes § Release microcontroller from STANDBY low-power mode ‡ privileged operation and EEPROM write protection override The TMS370Cx1x family is designed with significant flexibility to enable the designer to software-configure the system and peripherals to meet the requirements of a variety of applications. The nonprivileged mode of operation ensures the integrity of the system configuration, once it is defined for an application. Following a hardware reset, the TMS370Cx1x operates in the privileged mode, where all peripheral file registers have unrestricted read/write access, and the application program configures the system during the initialization sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 13 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 privileged operation and EEPROM write protection override (continued) set to 1 to enter the nonprivileged mode, disabling write operations to specific configuration-control bits within the PF. Table 10 displays the system-configuration bits which are write-protected during the nonprivileged mode and must be configured by software prior to exiting the privileged mode. Table 10. Privilege Bits REGISTER† NAME LOCATION CONTROL BIT SCCRO P010.6 OSC POWER SCCR1 P011.2 P011.4 MEMORY DISABLE AUTOWAIT DISABLE SCCR2 P012.0 P012.1 P012.3 P012.4 P012.6 P012.7 PRIVILEGE DISABLE INT1 NMI CPU STEST BUS STEST PWRDWN/IDLE HALT/STANDBY SPIPRI P03F.5 P03F.6 P03F.7 SPI ESPEN SPI PRIORITY SPI STEST T1PRI P04F.6 P04F.7 T1 PRIORITY T1 STEST † The privilege bits are shown in a bold typeface in the peripheral file frame 1 section. The write protect override (WPO) mode provides an external hardware method of overriding the write protection registers (WPRs) of data EEPROM on the TMS370Cx1x. WPO mode is entered by applying a 12-V input to the MC pin after the RESET pin input goes high (logic 1). The high voltage on the MC pin during the WPO mode is not the programming voltage for the data EEPROM or Program EPROM. All EEPROM programming voltages are generated on-chip. The WPO mode provides hardware system level capability to modify the content of data EEPROM while the device remains in the application but only while requiring a 12 V external input on the MC pin (normally not available in the end application except in a service or diagnostic environment). low-power and IDLE modes The TMS370Cx1x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the time when the mask is manufactured. The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The HALT/STANDBY bit in SCCR2 controls the low-power mode selection. In the STANDBY mode (HALT/STANDBY = 0), all CPU activity and most peripheral module activity is stopped; however, the oscillator, internal clocks, and Timer 1 remain active. System processing is suspended until a qualified interrupt (hardware RESET, external interrupt on INT1, INT2, INT3, or timer 1 interrupt) is detected. In the HALT mode (HALT/STANDBY = 1), the TMS370Cx1x is placed in its lowest power consumption mode. The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is suspended until a qualified interrupt (hardware RESET, external interrupt on the INT1, INT2, or INT3) is detected. The power-down mode-selection bits are summarized in Table 11. 14 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 low-power and IDLE modes (continued) Table 11. Low-Power/Idle Control Bits POWER-DOWN CONTROL BITS † MODE SELECTED PWRDWN/IDLE (SCCR2.6) HALT/STANDBY (SCCR2.7) 1 0 STANDBY 1 1 HALT 0 X† IDLE Don’t care When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the SCCR2.6-7 bits is ignored. In addition, if an IDLE instruction is executed when low-power modes are disabled through a programmable contact, the device always enters the IDLE mode. To provide a method for always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This means that the NMI is generated always, regardless of the interrupt enable flags. The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file), CPU registers (SP, PC, and ST), I/O pin direction and output data, and status registers of all on-chip peripheral functions. Since all CPU instruction processing is stopped during the STANDBY and HALT modes, the clocking of the WD timer is inhibited. clock modules The ’x1x family provides two clock options that are referred to as divide-by-1 (phase-locked loop) and divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of a TMS370 MCU. The ’x1x masked ROM devices offer both options to meet system engineering requirements. Only one of the two clock options is allowed on each ROM device. The ’712A EPROM has only the divide-by-4, while the ’712B has divide-by-1. The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with no added cost. The divide-by-1 provides a one-to-one match of the external resonator frequency (CLKIN) to the internal system clock (SYSCLK) frequency, whereas the divide-by-4 produces a SYSCLK which is one-fourth the frequency of the external resonator. Inside of the divide-by-1 module, the frequency of the external resonator is multiplied by four, and the clock module then divides the resulting signal by four to provide the four-phased internal system clock signals. The resulting SYSCLK is equal to the resonator frequency. These are formulated as follows: Divide-by-4 option : SYSCLK = external resonator frequency = CLKIN 4 4 Divide-by-1 option : SYSCLK = external resonator frequency × 4 = CLKIN 4 The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of low-speed resonators extend through fewer of the emissions spectrum than the harmonics of faster resonators. The divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a steeper decay of emissions produced by the oscillator. POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 15 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 system configuration registers Table 12 contains system-configuration and control functions and registers for controlling EEPROM programming. The privileged bits are shown in a bold typeface and shaded areas. Table 12. Peripheral File Frame 1: System-Configuration Registers PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG P010 COLD START OSC POWER PF AUTO WAIT OSC FLT FLAG MC PIN WPO MC PIN DATA — P/C MODE SCCR0 P011 — — — AUTO WAIT DISABLE — MEMORY DISABLE — — SCCR1 P012 HALT/ STANDBY PWRDWN/ IDLE — BUS STEST CPU STEST — INT1 NMI PRIVILEGE DISABLE SCCR2 P013 to P016 Reserved P017 INT1 FLAG INT1 PIN DATA — — — INT1 POLARITY INT1 PRIORITY INT1 ENABLE INT1 P018 INT2 FLAG INT2 PIN DATA — INT2 DATA DIR INT2 DATA OUT INT2 POLARITY INT2 PRIORITY INT2 ENABLE INT2 P019 INT3 FLAG INT3 PIN DATA — INT3 DATA DIR INT3 DATA OUT INT3 POLARITY INT3 PRIORITY INT3 ENABLE INT3 P01A BUSY — — — — AP W1W0 EXE DEECTL — — W0 EXE EPCTL P01B P01C P01D P01E P01F 16 Reserved BUSY VPPS — — Reserved POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 digital port control registers Peripheral file frame 2 contains the digital I/O pin configuration and control registers. Table 13 shows the specific addresses, registers, and control bits within this peripheral file frame. Table 14 shows the port configuration register setup. Table 13. Peripheral File Frame 2: Digital Port-Control Registers PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG P020 Reserved APORT1 P021 Port A Control Register 2 (must be 0) APORT2 P022 Port A Data P023 Port A Direction P024 to P02B Reserved ADATA ADIR P02C Port D Control Register 1 (must be 0) — — — DPORT1 P02D 0)† — — — DPORT2 P02E Port D Control Register 2 (must be Port D Data — — — DDATA P02F Port D Direction — — — DDIR † D3 as SYSCLK, set port D control register 2 = 08h. Table 14. Port Configuration Register Setup PORT PIN abcd 00q1 abcd 00y0 A 0 -- 7 Data Out q Data In y D 3 -- 7 Data Out q Data In y a = Port x Control Register 1 b = Port x Control Register 2 c = Data d = Direction POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 17 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 programmable timer 1 The programmable Timer 1 (T1) module of the TMS370Cx1x provides the designer with the enhanced timer resources required to perform real-time system control. The T1 module contains the general-purpose timer and the watchdog (WD) timer. The two independent 16-bit timers, T1 and WD, allow program selection of input clock sources (real-time, external event, or pulse accumulate) with multiple 16-bit registers (input capture and compare) for special timer function control. The Timer 1 module includes three external device pins that can be used for multiple counter functions (operation-mode dependent), or used as general-purpose I/O pins. The T1 module block diagram is shown in Figure 5. Edge Select T1IC/CR 16-Bit Counter MUX T1EVT 16-Bit Capt/Comp Register 16 16-Bit Compare Register 8-Bit Prescaler 16-Bit WatchdogCounter (Aux. Timer) MUX PWM Toggle T1PWM Interrupt Logic Interrupt Logic Figure 5. Timer 1 Block Diagram D Three T1 I/O pins -- T1IC/CR: T1 input capture / counter-reset input pin, or general-purpose bidirectional I/O pin -- T1PWM: T1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin -- T1EVT: T1 event input pin, or general-purpose bidirectional I/O pin D Two operational modes: -- Dual-compare mode: Provides PWM signal -- Capture/compare mode: Provides input capture pin D One 16-bit general-purpose resettable counter D One 16-bit compare register with associated compare logic D One 16-bit capture/compare register, which, depending on the mode of operation, operates as either capture or compare registers. D One 16-bit WD counter can be used as an event counter, a pulse accumulator, or an interval timer if WD feature is not needed. D Prescaler/clock sources that determine one of eight clock sources for general-purpose timer 18 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 programmable timer 1 (continued) D Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on the input capture pins (T1IC/CR) D Interrupts that can be generated on the occurrence of: -- A capture -- A compare equal -- A counter overflow -- An external edge detection D Sixteen T1 module control registers located in the PF frame beginning at address P040 The T1 module control registers are illustrated in Table 15. POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 19 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 programmable timer 1 (continued) Table 15. Timer 1 Module Register Memory Map PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG Modes: Dual-Compare and Capture/Compare P040 Bit 15 T1Counter MSbyte Bit 8 P041 Bit 7 T1 Counter LSbyte Bit 0 P042 Bit 15 Compare Register MSbyte Bit 8 P043 Bit 7 Compare Register LSbyte Bit 0 P044 Bit 15 Capture/Compare Register MSbyte Bit 8 P045 Bit 7 Capture/Compare Register LSbyte Bit 0 P046 Bit 15 Watchdog Counter MSbyte Bit 8 P047 Bit 7 Watchdog Counter LSbyte Bit 0 P048 Bit 7 Watchdog Reset Key P049 WD OVRFL TAP SEL† WD INPUT SELECT2† WD INPUT SELECT1† WD INPUT SELECT0† P04A WD OVRFL RST ENA† WD OVRFL INT ENA WD OVRFL INT FLAG Bit 0 T1CNTR T1C T1CC WDCNTR WDRST — T1 INPUT SELECT2 T1 INPUT SELECT1 T1 INPUT SELECT0 T1CTL1 T1 OVRFL INT ENA T1 OVRFL INT FLAG — — T1 SW RESET T1CTL2 Mode: Dual-Compare P04B T1EDGE INT FLAG T1C2 INT FLAG T1C1 INT FLAG — — T1EDGE INT ENA T1C2 INT ENA T1C1 INT ENA T1CTL3 P04C T1 MODE=0 T1C1 OUT ENA T1C2 OUT ENA T1C1 RST ENA T1CR OUT ENA T1EDGE POLARITY T1CR RST ENA T1EDGE DET ENA T1CTL4 Mode: Capture/Compare P04B T1EDGE INT FLAG — T1C1 INT FLAG — — T1EDGE INT ENA — T1C1 INT ENA T1CTL3 P04C T1 MODE = 1 T1C1 OUT ENA — T1C1 RST ENA — T1EDGE POLARITY — T1EDGE DET ENA T1CTL4 Modes: Dual-Compare and Capture/Compare P04D — — — — T1EVT DATA IN T1EVT DATA OUT T1EVT FUNCTION T1EVT DATA DIR T1PC1 P04E T1PWM DATA IN T1PWM DATA OUT T1PWM FUNCTION T1PWM DATA DIR T1IC/CR DATA IN T1IC/CR DATA OUT T1IC/CR FUNCTION T1IC/CR DATA DIR T1PC2 P04F T1 STEST T1 PRIORITY — — — — — — T1PRI † 20 Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2 bits are ignored. POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 programmable timer 1 (continued) Figure 6 shows the Timer 1 capture/compare mode block diagram. The annotations on the diagram identify the register and the bit(s) in the PF. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2 register. 16-Bit LSB Capt/Comp MSB Register Prescale Clock Source T1C1 OUT ENA T1CTL4.6 Toggle T1CC.15-0 T1PC2.7-4 T1PWM T1CNTR.15 - 0 LSB 16-Bit MSB Counter 16 T1 PRIORITY T1C1 INT FLAG Compare= Reset T1CTL3.0 T1C.15-0 T1 SW RESET 0 1 Level 1 Int Level 2 Int T1C1 INT ENA 16-Bit LSB Compare Register MSB T1C1 RST ENA T1CTL2.0 T1CTL3.5 T1PRI.6 T1 OVRFL INT FLAG T1CTL2.3 T1CTL4.4 T1CTL2.4 T1 OVRFL INT ENA T1PC2.3-0 T1IC/CR T1EDGE DET ENA Edge Select T1EDGE INT FLAG T1CTL3.7 T1CTL4.0 T1CTL3.2 T1EDGE INT ENA T1CTL4.2 T1EDGE POLARITY Figure 6. Capture/Compare Mode POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 21 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 programmable timer 1 (continued) Figure 7 shows the Timer 1 dual-compare mode block diagram. The annotations on the diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2 register. T1CC.15-0 MSB T1CTL2.0 T1C2 INT ENA Compare= T1CTL4.4 T1CTL4.5 T1PC2.7-4 16 T1C1 INT FLAG T1CTL3.5 Compare= T1C1 RST ENA Output Enable T1C2 OUT ENA 16-Bit Counter Reset T1 SW RESET T1CTL3.6 T1CTL3.1 T1CNTR.15-0 LSB T1C2 INT FLAG T1CTL3.0 T1C.15-0 T1C1 INT ENA 16-Bit LSB Compare Register MSB T1CTL4.6 Toggle 16-Bit LSB Capt/Comp Register MSB Prescaler Clock Source T1PWM T1C1 OUT ENA T1CTL4.3 T1CR OUT ENA T1 OVRFL INT FLAG T1PC2.3-0 T1IC/CR T1CTL4.1 T1CR RST ENA Edge Select T1CTL2.3 T1CTL2.4 T1 OVRFL INT ENA T1 PRIORITY T1CTL4.0 T1EDGE DET ENA T1EDGE INT FLAG T1CTL4.2 T1EDGE POLARITY T1CTL3.7 T1CTL3.2 T1EDGE INT ENA Figure 7. Dual-Compare Mode 22 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 T1PRI.6 0 1 Level 1 Int Level 2 Int TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 programmable timer 1 (continued) The TMS370Cx1x device includes a 24-bit WD timer, contained in the T1 module, which can be programmed as an event counter, pulse accumulator, or interval timer if the WD function is not used. The WD function is to monitor software and hardware operation and to implement a system reset when the WD counter is not properly serviced (WD counter overflow or WD counter is re-initialized by an incorrect value). The WD can be configured as one of three mask options as follows: standard watchdog, hard WD, or simple counter. D Standard watchdog configuration (see Figure 8) for ’C712A EPROM and mask-ROM devices: -- -- Watchdog mode -- Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK -- A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct value is written. -- Generates a system reset if an incorrect value is written to the WD reset key or if the counter overflows -- A WD overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a system reset Non-watchdog mode -- Watchdog timer can be configured as an event counter, pulse accumulator or an interval timer WDCNTR.15-0 WD OVRFL INT FLAG 16-Bit Watchdog Counter T1CTL2.6 T1CTL2.5 Reset Clock Prescaler Interrupt WD OVRFL INT ENA T1CTL1.7 T1CTL2.7 WD OVRFL TAP SEL System Reset WD OVRFL RST ENA Watchdog Reset Key WDRST.7-0 Figure 8. Standard Watchdog POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 23 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 programmable timer 1 (continued) D Hard watchdog configuration (see Figure 9) for ’C712B EPROM and mask-ROM devices: -- Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK -- A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct value is written. -- Generates a system reset if an incorrect value is written to the WDRST or if the counter overflows -- A WD overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a system reset -- Automatic activation of the WD timer upon power-up reset -- INT1 is enabled as a nonmaskable interrupt during low power modes. WDCNTR.15-0 WD OVRFL INT FLAG 16-Bit Watchdog Counter T1CTL2.5 Reset Clock Prescaler T1CTL1.7 WD OVRFL TAP SEL Watchdog Reset Key WDRST.7-0 Figure 9. Hard Watchdog 24 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 System Reset TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 programmable timer 1 (continued) D Simple counter configuration (see Figure 10) for mask-ROM devices only -- Simple counter can be configured as an event counter, pulse accumulator, or an internal timer. WDCNTR.15-0 WD OVFL INT FLAG 16-Bit Watchdog Counter T1CTL2.6 Interrupt T1CTL2.5 WD OVRFL INT ENA Reset Clock Prescaler T1CTL1.7 WD OVRFL TAP SEL Watchdog Reset Key WDRST.7-0 Figure 10. Simple Counter serial peripheral interface The SPI is a high-speed synchronous serial I/O port that allows a serial bit stream of programmed length (one to eight bits) to be shifted into and out of the device at a programmable bit transfer rate. The SPI normally is used for communications between the microcontroller and external peripherals or another microcontroller. Typical applications include external I/O or peripheral expansion by way of devices such as shift registers, display drivers, and A/D converters. Multi-device communications are supported by the master/slave operation of the SPI. The SPI module features include the following: D Three external pins -- SPISOMI: SPI slave output/master input pin or general-purpose bidirectional I/O pin -- SPISIMO: SPI slave input/master output pin or general-purpose bidirectional I/O pin -- SPICLK: SPI serial clock pin or general-purpose bidirectional I/O pin D Two operational modes: Master and slave D Baud rate: Eight different programmable rates -- Maximum baud rate in master mode: 2.5M bps at 5-MHz SYSCLK SPI BAUD RATE = SYSCLK 2 × 2b where b=bit rate in SPICCR.5-3 (range 0--7) -- Maximum baud rate in slave mode: 625K bps at 5-MHz SYSCLK for maximum slave SPI BAUD RATE < SYSCLK/8 D Data word format: one to eight data bits D Simultaneous receiver and transmitter operations (transmit function can be disabled in software) POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 25 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 serial peripheral interface (continued) D Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. D Seven SPI module control registers located in control register frame beginning at address P030h The SPI module-control registers are illustrated in Table 16. Table 16. SPI Module-Control Register Memory Map PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 P030 SPI SW RESET CLOCK POLARITY SPI BIT RATE2 SPI BIT RATE1 SPI BIT RATE0 SPI CHAR2 SPI CHAR1 SPI CHAR0 SPICCR P031 RECEIVER OVERRUN SPI INT FLAG — — — MASTER/ SLAVE TALK SPI INT ENA SPICTL RCVD3 RCVD2 RCVD1 RCVD0 SPIBUF SDAT2 SDAT1 SDAT0 SPIDAT P032 to P036 P037 Reserved RCVD7 RCVD6 RCVD5 RCVD4 SDAT7 SDAT6 SDAT5 SDAT4 P038 P039 Reserved P03A to P03C 26 REG SDAT3 Reserved P03D — — — — SPICLK DATA IN SPICLK DATA OUT SPICLK FUNCTION SPICLK DATA DIR SPIPC1 P03E SPISIMO DATA IN SPISIMO DATA OUT SPISIMO FUNCTION SPISIMO DATA DIR SPISOMI DATA IN SPISOMI DATA OUT SPISOMI FUNCTION SPISOMI DATA DIR SPIPC2 P03F SPI STEST SPI PRIORITY SPI ESPEN — — — — — SPIPRI POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 serial peripheral interface (continued) The SPI block diagram is illustrated in Figure 11. RECEIVER OVERRUN SPIBUF.7-0 SPIBUF Buffer Register SPICTL.7 SPIPRI.6 8 SPI INT FLAG SPICTL.0 0 SPICTL.6 1 SPIINT ENA Level 1 INT Level 2 INT SPIPC2.7-4 SPIDAT Data Register SPIDAT.7-0 SPISIMO SPICTL.1 SPIPC2.3-0 SPISOMI TALK State Control MASTER/SLAVE† SPI CHAR SPICCR.2-0 2 System Clock 1 SPICTL.2 0 SPIPC1.3-0 SPICCR.6 SPICCR.5-3 5 4 SPICLK CLOCK POLARITY 3 SPI BIT RATE † The diagram is shown in the slave mode. Figure 11. SPI Block Diagram instruction set overview Table 17 provides an opcode to instruction cross reference of all 73 instructions and 274 opcodes of the ‘370Cx1x instruction set. The numbers at the top of this table represent the most significant nibble of the opcode while the numbers at the left side of the table represent the least significant nibble (LBN). The instruction of these two opcode nibbles contains the mnemonic, operands, and byte/cycle particular to that opcode. For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes in eight SYSCLK cycles. POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 27 28 L S N BTJO Rs,A,ra 3/9 BTJZ Rs.,A,ra 3/9 ADD Rs,A 2/7 ADC Rs,A 2/7 SUB Rs,A 2/7 SBB Rs,A 2/7 JNZ ra 2/5 JNC ra 2/5 JV ra 2/5 JL ra 2/5 JLE ra 2/5 JHS ra 2/5 6 7 8 9 A B † XOR Rs,A 2/7 JPZ ra 2/5 5 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 SBB Rs,B 2/7 SUB Rs,B 2/7 ADC Rs,B 2/7 ADD Rs,B 2/7 BTJZ Rs,B,ra 3/9 BTJO Rs,B,ra 3/9 XOR Rs,B 2/7 OR Rs,B 2/7 SBB Rs,Rd 3/9 SUB Rs,Rd 3/9 ADC Rs,Rd 3/9 ADD Rs,Rd 3/9 BTJZ Rs,Rd,ra 4/11 BTJO Rs,Rd,ra 4/11 XOR Rs,Rd 3/9 OR Rs,Rd 3/9 SBB #n,B 2/6 SUB #n,B 2/6 ADC #n,B 2/6 ADD #n,B 2/6 BTJZ #n,B,ra 3/8 BTJO #n,B,ra 3/8 XOR #n,B 2/6 OR #n,B 2/6 SBB B,A 1/8 SUB B,A 1/8 ADC B,A 1/8 ADD B,A 1/8 BTJZ B,A,ra 2/10 BTJO B,A,ra 2/10 XOR B,A 1/8 OR B,A 1/8 SBB #n,Rd 3/8 SUB #n,Rd 3/8 ADC #n,Rd 3/8 ADD #n,Rd 3/8 BTJZ #n,Rd,ra 4/10 BTJO #n,Rd,ra 4/10 XOR #n,Rd 3/8 OR #n,Rd 3/8 AND #n,Rd 3/8 MOV A, & lab 3/10 MOV & lab,A 3/10 JMPL lab 3/9 MOVW #16,Rd 4/13 BTJZ A,Pd,ra 3/10 BTJO A,Pd,ra 3/11 XOR A,Pd 2/9 OR A,Pd 2/9 AND A,Pd 2/9 MOV Ps,A 2/8 8 MSN MOV A, *Rd 2/9 MOV *Rs,A 2/9 JMPL *Rd 2/8 MOVW Rs,Rd 3/12 BTJZ B,Pd,ra 3/10 BTJO B,Pd,ra 3/10 XOR B,Pd 2/9 OR B,Pd 2/9 AND B,Pd 2/9 MOV Ps,B 2/7 9 MOV A,*lab[B] 3/12 MOV *lab[B],A 3/12 JMPL *lab[B] 3/11 MOVW #16[B],Rd 4/15 BTJZ #n,Pd,ra 4/11 BTJO #n,Pd,ra 4/11 XOR #n,Pd 3/10 OR #n,Pd 3/10 AND #n,Pd 3/10 MOV Ps,Rd 3/10 A B COMPL A 1/8 DJNZ A,ra 2/10 POP A 1/9 PUSH A 1/9 SWAP A 1/11 XCHB A 1/10 CLR A 1/8 INV A 1/8 INC A 1/8 DEC A 1/8 CLRC / TST A 1/9 C COMPL B 1/8 DJNZ B,ra 2/10 POP B 1/9 PUSH B 1/9 SWAP B 1/11 XCHB A / TST B 1/10 CLR B 1/8 INV B 1/8 INC B 1/8 DEC B 1/8 MOV A,B 1/9 D COMPL Rn 2/6 DJNZ Rn,ra 3/8 POP Rd 2/7 PUSH Rs 2/7 SWAP Rn 2/9 XCHB Rn 2/8 CLR Rn 2/6 INV Rn 2/6 INC Rn 2/6 DEC Rn 2/6 MOV B,Rd 2/7 MOV A,Rd 2/7 E TRAP 4 1/14 TRAP 5 1/14 TRAP 6 1/14 TRAP 7 1/14 TRAP 8 1/14 TRAP 9 1/14 TRAP 10 1/14 TRAP 11 1/14 TRAP 12 1/14 TRAP 13 1/14 TRAP 14 1/14 TRAP 15 1/14 F PUSH ST 1/8 1/12 RTI 1/9 RTS 1/7 SETC MOV #n,Pd 3/10 1/6 IDLE extend inst,2 opcodes CMP *n[SP],A 2/8 MOV A,*n[SP] 2/7 MOV *n[SP],A 2/7 LDST n 2/6 All conditional jumps (opcodes 01--0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions have a relative address as the last operand. SBB #n,A 2/6 SUB #n,A 2/6 ADC #n,A 2/6 ADD #n,A 2/6 BTJZ #n,A,ra 3/8 BTJO #n,A,ra 3/8 XOR #n,A 2/6 OR #n,A 2/6 OR Rs,A 2/7 AND #n,B 2/6 AND B,A 1/8 JP ra 2/5 AND Rs,Rd 3/9 4 AND Rs,B 2/7 MOV #n,Rd 3/8 AND #n,A 2/6 MOV B,A 1/8 AND Rs,A 2/7 MOV #n,B 2/6 JC ra 2/5 MOV Rs,Rd 3/9 3 MOV Rs,B 2/7 MOV #n,A 2/6 MOV Rs,A 2/7 JZ ra 2/5 2 7 MOV Rs,Pd 3/10 MOV B,Pd 2/8 6 MOV A,Pd 2/8 5 JN ra 2/5 4 1 3 0 2 INCW #n,Rd 3/11 1 JMP ra 2/7 0 Table 17. TMS370 Family Opcode/Instruction Map† Template Release Date: 7--11--94 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 L S N CMP Rs,A 2/7 DAC Rs,A 2/9 DSB Rs,A 2/9 JGE ra 2/5 JG ra 2/5 JLO ra 2/5 C D E F † MPY Rs,A 2/46 JNV ra 2/5 DSB #n,A 2/8 DAC #n,A 2/8 CMP #n,A 2/6 MPY #n,A 2/45 2 DSB Rs,B 2/9 DAC Rs,B 2/9 CMP Rs,B 2/7 MPY Rs,B 2/46 3 DSB Rs,Rd 3/11 DAC Rs,Rd 3/11 CMP Rs,Rd 3/9 MPY Rs,Rd 3/48 4 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 DSB #n,B 2/8 DAC #n,B 2/8 CMP #n,B 2/6 MPY #n,B 2/45 5 DSB B,A 1/10 DAC B,A 1/10 CMP B,A 1/8 MPY B,A 1/47 6 DSB #n,Rd 3/10 DAC #n,Rd 3/10 CMP #n,Rd 3/8 MPY #n,Rs 3/47 7 CALLR lab 3/15 CALL lab 3/13 CMP & lab,A 3/11 BR lab 3/9 8 MSN 9 A CALLR *lab[B] 3/17 CALL *lab[B] 3/15 CMP *lab[B],A 3/13 BR *lab[B] 3/11 B RLC A 1/8 RL A 1/8 RRC A 1/8 RR A 1/8 Second byte of two-byte instructions (F4xx): CALLR *Rd 2/14 CALL *Rd 2/12 CMP *Rs,A 2/10 BR *Rd 2/8 C D A B C D E F F4 F4 F4 F4 F4 9 F4 F4 8 RLC Rn 2/6 RL Rn 2/6 RRC Rn 2/6 RR Rn 2/6 F4 RLC B 1/8 RL B 1/8 RRC B 1/8 RR B 1/8 E CALLR *n[Rn] 4/22 CALL *n[Rn] 4/20 CMP *n[Rn],A 4/18 BR *n[Rn] 4/16 MOV A,*n[Rn] 4/16 MOV *n[Rn],A 4/17 JMPL *n[Rn] 4/16 MOVW *n[Rn] 4/15 TRAP 0 1/14 TRAP 1 1/14 TRAP 2 1/14 TRAP 3 1/14 F DIV Rn.A 3/14-63 1/7 NOP 1/8 STSP 1/7 LDSP POP ST 1/8 All conditional jumps (opcodes 01--0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions have a relative address as the last operand. Legend: * = Indirect addressing operand prefix & = Direct addressing operand prefix # = immediate operand #16 = immediate 16-bit number lab = 16-label n = immediate 8-bit number Pd = Peripheral register containing destination type Pn = Peripheral register Ps = Peripheral register containing source byte ra = Relative address Rd = Register containing g g destination type yp R = Register Rn R i file fil Rp = Register pair Rpd = Destination register pair Rps = Source So rce Register pair Rs = Register containing source byte 1 0 Table 17. TMS370 Family Opcode/Instruction Map †(Continued) TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 29 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 development system support The TMS370 family development support tools include an assembler, a C-compiler, a linker, an in-circuit emulator XDS/22, CDT and an EEPROM/UVEPROM programmer. D Assembler/linker (Part No. TMDS3740850--02 for PC) -- Includes extensive macro capability -- Provides high-speed operation -- Includes format conversion utilities for popular formats D ANSI C Compiler (Part No. TMDS3740855--02 for PC, Part No. TMDS3740555--09 for HP700, Sun-3 or Sun-4) -- Generate assembly code for the TMS370 that can be inspected easily -- Improves code execution speed and reduces code size with optional optimizer pass -- Enables direct reference the TMS370’s port registers by using a naming convention -- Provides flexibility in specifying the storage for data objects -- Interfaces C functions and assembly functions easily -- Includes assembler and linker D CDT370 (Compact Development Tool) real-time in-circuit emulation -- Base (Part Number EDSCDT370 -- for PC, requires cable) -- Cable for 28-pin DIP (Part No. EDSTRG28DIL) -- Cable for 28-pin PLCC (Part No. EDSTRG28PLCC) -- EEPROM and EPROM programming support -- Allows inspection and modification of memory locations -- Includes compatibility to upload/download program and data memory -- Execute programs and software routines -- Includes 1024 samples trace buffer -- Includes single-step executable instructions -- Uses software breakpoints to halt program execution at selected address D XDS/22 in-circuit emulator -- Base (Part Number TMDS3762210 for PC, requires cable) -- Cable for 28-pin DIP/PLCC (Part No. TMDS3788828) -- Contains all the features of the CDT370 described previously but does not have the capability to program the data EEPROM and program EPROM -- Contains sophisticated breakpoint trace and timing hardware that provides up to 2047 qualified trace samples with symbolic disassembly -- Allows qualification of breakpoints by address and/or data on any type of memory acquisition. Up to four levels of events can be combined to cause a breakpoint HP700 is a trademark of Hewlett-Packard Company. Sun-3 and Sun-4 are trademarks of Sun Microsystems, Incorporated. 30 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 development system support (continued) -- Provides timers for analyzing total and average time in routines -- Contains an eight-line logic probe for adding visibility of external signals to the breakpoint qualifier and to trace display D Microcontroller programmer -- -- Base (Part No. TMDS3760500A -- for PC, requires programmer head) -- Single unit head for 28-pin PLCC (Part No. TMDS3780510A) -- Single unit head for 28-pin DIP (Part No. TMDS3780511A) PC-based, window/function-key-oriented user interface for ease of use and rapid learning environment D Design kit (Part No. TMDS3770110 -- for PC) -- Includes TMS370 Application Board and TMS370 Assembler diskette and documentation -- Supports quick evaluation of TMS370 functionality -- Capability to upload and download code -- Capability to execute programs and software routines, and to single-step executable instructions -- Software breakpoints to halt program execution at selected addresses -- Wire-wrap prototype area -- Reverse assembler D Starter Kit (Part No. TMDS37000 -- for PC) -- Includes TMS370 Assembler diskette and documentation -- Includes TMS370 Simulator -- Includes programming adapter board and programming software -- Does not include (to be supplied by the user) -- + 5 V power supply -- ZIF sockets -- Nine-pin RS232 cable POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 31 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 device numbering conventions Figure 12 illustrates the numbering and symbol nomenclature for the TMS370Cx1x family. TMS 370 C 7 1 2 A FN L Prefix: TMS = Standard prefix for fully qualified devices SE = System evaluator (window EPROM) that is used for prototyping purpose. Family: Technology: Program Memory Types: Device Type: Memory Size: Temperature Ranges: Packages: ROM and EPROM Option: 370 = TMS370 8-Bit Microcontroller Family C = CMOS 0 = Mask ROM 3 = Mask ROM, No Data EEPROM 7 = EPROM 1 = ’x1x device containing the following modules: -- Timer 1 -- Serial Peripheral Interface 0 = 4K bytes 1 = 2K bytes 2 = 8K bytes A = --40C to 85C L = 0C to 70C T = --40C to 105C FN FZ N JD = = = = Plastic Leaded Chip Carrier Ceramic Leaded Chip Carrier Plastic Dual-In-Line Ceramic Dual-in-Line A = For ROM device, the watchdog timer can be configured as one of the three different mask options: -- A standard watchdog -- A hard watchdog -- A simple watchdog The clock can be either: -- Divide-by-4 clock -- Divide-by-1 (PLL) clock The low-power modes can be either: -- Enabled -- Disabled A = For EPROM device, a standard watchdog, a divide-by4 clock, and low-power modes are enabled B = For EPROM device, a hard watchdog, a divide-by-1 (PLL) clock, and low-power modes are enabled. Figure 12. TMS370Cx1x Family Nomenclature 32 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 device part numbers Table 18 provides all of the ’x1x devices available. The device part number nomenclature is designed to assist ordering. Upon ordering, the customer must specify not only the device part number, but also the clock and watchdog timer options desired. Each device can have only one of the three possible watchdog timer options and one of the two clock options. The options to be specified pertain solely to orders involving ROM devices. Table 18. Device Part Numbers † DEVICES PART NUMBERS FOR 28 PINS (LCC) DEVICES PART NUMBERS FOR 28 PINS (DIP) TMS370C010AFNA TMS370C010AFNL TMS370C010AFNT TMS370C010ANA TMS370C010ANL TMS370C010ANT TMS370C012AFNA TMS370C012AFNL TMS370C012AFNT TMS370C012ANA TMS370C012ANL TMS370C012ANT TMS370C310AFNA TMS370C310AFNL TMS370C310AFNT TMS370C310ANA TMS370C310ANL TMS370C310ANT TMS370C311AFNA TMS370C311AFNL TMS370C311AFNT TMS370C311ANA TMS370C311ANL TMS370C311ANT TMS370C312AFNA TMS370C312AFNL TMS370C312AFNT TMS370C312ANA TMS370C312ANL TMS370C312ANT TMS370C712AFNT TMS370C712BFNT TMS370C712ANT TMS370C712BNT SE370C712AFZT† SE370C712BFZT† SE370C712AJDT† SE370C712BJDT† System evaluators are for use in prototype environment and their reliability has not been characterized. POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 33 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 new code release form Figure 13 shows a sample of the new code release form. NEW CODE RELEASE FORM TEXAS INSTRUMENTS TMS370 MICROCONTROLLER PRODUCTS DATE: To release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information: 1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media) 2. An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book. Company Name: Street Address: Street Address: City: Contact Mr./Ms.: Phone: ( State Zip ) Ext.: Customer Purchase Order Number: Customer Print Number *Yes: # No: (Std. spec to be followed) *If Yes: Customer must provide ”print” to TI w/NCRF for approval before ROM code processing starts. Customer Part Number: Customer Application: TMS370 Device: TI Customer ROM Number: (provided by Texas Instruments) OSCILLATOR FREQUENCY [] External Drive (CLKIN) [] Crystal [] Ceramic Resonator CONTACT OPTIONS FOR THE ’A’ VERSION TMS370 MICROCONTROLLERS MIN [] Supply Voltage MIN: (std range: 4.5V to 5.5V) TYP MAX Low Power Modes [] Enabled [] Disabled Watchdog counter [] Standard [] Hard Enabled [] Simple Counter Clock Type [] Standard (/4) [] PLL (/1) NOTE: Non ’A’ version ROM devices of the TMS370 microcontrollers will have the “Low-power modes Enabled”, “Divide-by-4” Clock, and “Standard” Watchdog options. See the TMS370 Family User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B). MAX: TEMPERATURE RANGE [] ’L’: 0 to 70C (standard) [] ’A’: --40 to 85C [] ’T’: --40 to 105C PACKAGE TYPE [] ’N’ 28-pin PDIP [] “FN” 44-pin PLCC [] “FN” 28-pin PLCC [] “FN” 68-pin PLCC [] “N” 40-pin PDIP [] “NM” 64-pin PSDIP [] “NJ” 40-pin PSDIP (formerly known as N2) SYMBOLIZATION BUS EXPANSION [] TI standard symbolization [] TI standard w/customer part number [] Customer symbolization (per attached spec, subject to approval) [] YES [] NO NON-STANDARD SPECIFICATIONS: ALL NON-STANDARDS SPECIFICATIONS MUST BE APPROVED BY THE TI ENGINEERING STAFF: If the customer requires expedited production material (i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a ’P’ in the symbolization preceding the TI part number. RELEASE AUTHORIZATION: This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification code is approved by the customer. 1. Customer: Date: 2. TI: Field Sales: Marketing: Prod. Eng.: Proto. Release: Figure 13. Sample New Code Release Form 34 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 Table 19 is a collection of all the peripheral file frames used in the ’Cx1x (provided for a quick reference). Table 19. Peripheral File Frame Compilation PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG System Configuration Registers P010 COLD START OSC POWER PF AUTO WAIT OSC FLT FLAG MC PIN WPO MC PIN DATA — P/C MODE SCCR0 P011 — — — AUTO WAIT DISABLE — MEMORY DISABLE — — SCCR1 P012 HALT/ STANDBY PWRDWN/ IDLE — BUS STEST CPU STEST — INT1 NMI PRIVILEGE DISABLE SCCR2 P013 to P016 Reserved P017 INT1 FLAG INT1 PIN DATA — — — INT1 POLARITY INT1 PRIORITY INT1 ENABLE INT1 P018 INT2 FLAG INT2 PIN DATA — INT2 DATA DIR INT2 DATA OUT INT2 POLARITY INT2 PRIORITY INT2 ENABLE INT2 P019 INT3 FLAG INT3 PIN DATA — INT3 DATA DIR INT3 DATA OUT INT3 POLARITY INT3 PRIORITY INT3 ENABLE INT3 P01A BUSY — — — — AP W1W0 EXE DEECTL — — W0 EXE EPCTL P01B Reserved P01C BUSY VPPS — — P01D P01E P01F Reserved Digital Port Control Registers P020 Reserved APORT1 P021 Port A Control Register 2 (must be 0) APORT2 P022 Port A Data P023 Port A Direction P024 to P02B Reserved ADATA ADIR P02C Port D Control Register 1 (must be 0) — — — DPORT1 P02D 0)† — — — DPORT2 P02E Port D Control Register 2 (must be Port D Data — — — DDATA P02F Port D Direction — — — DDIR SPI Module Control Register Memory Map P030 SPI SW RESET CLOCK POLARITY SPI BIT RATE2 SPI BIT RATE1 SPI BIT RATE0 SPI CHAR2 SPI CHAR1 SPI CHAR0 SPICCR P031 RECEIVER OVERRUN SPI INT FLAG — — — MASTER/ SLAVE TALK SPI INT ENA SPICTL RCVD3 RCVD2 RCVD1 RCVD0 SPIBUF P032 to P036 Reserved P037 RCVD7 RCVD6 RCVD5 RCVD4 P038 Reserved † D3 as SYSCLK, set port D control register 2 = 08h. POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 35 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 Table 19. Peripheral File Frame Compilation (Continued) PF P039 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SDAT7 SDAT6 SDAT5 SDAT4 SDAT3 SDAT2 SDAT1 SDAT0 SPIDAT P03A to P03C REG Reserved P03D — — — — SPICLK DATA IN SPICLK DATA OUT SPICLK FUNCTION SPICLK DATA DIR SPIPC1 P03E SPISIMO DATA IN SPISIMO DATA OUT SPISIMO FUNCTION SPISIMO DATA DIR SPISOMI DATA IN SPISOMI DATA OUT SPISOMI FUNCTION SPISOMI DATA DIR SPIPC2 P03F SPI STEST SPI RIORITY SPI ESPEN — — — — — SPIPRI Timer1 Module Register Memory Map Modes: Dual-Compare and Capture/Compare P040 Bit 15 T1Counter MSbyte Bit 8 P041 Bit 7 T1 Counter LSbyte Bit 0 T1CNTR P042 Bit 15 Compare Register MSbyte Bit 8 P043 Bit 7 Compare Register LSbyte Bit 0 P044 Bit 15 Capture/Compare Register MSbyte Bit 8 P045 Bit 7 Capture/Compare Register LSbyte Bit 0 P046 Bit 15 Watchdog Counter MSbyte Bit 8 P047 Bit 7 Watchdog Counter LSbyte Bit 0 P048 Bit 7 Watchdog Reset Key Bit 0 P049 WD OVRFL TAP SEL† WD INPUT SELECT2† WD INPUT SELECT1† WD INPUT SELECT0† — T1 INPUT SELECT2 T1 INPUT SELECT1 T1 INPUT SELECT0 T1CTL1 P04A WD OVRFL RST ENA† WD OVRFL INT ENA WD OVRFL INT FLAG T1 OVRFL INT ENA T1 OVRFL INT FLAG — — T1 SW RESET T1CTL2 T1C T1CC WDCNTR WDRST Mode: Dual-Compare P04B T1EDGE INT FLAG T1C2 INT FLAG T1C1 INT FLAG — — T1EDGE INT ENA T1C2 INT ENA T1C1 INT ENA T1CTL3 P04C T1 MODE=0 T1C1 OUT ENA T1C2 OUT ENA T1C1 RST ENA T1CR OUT ENA T1EDGE POLARITY T1CR RST ENA T1EDGE DET ENA T1CTL4 Mode: Capture/Compare P04B T1EDGE INT FLAG — T1C1 INT FLAG — — T1EDGE INT ENA — T1C1 INT ENA T1CTL3 P04C T1 MODE = 1 T1C1 OUT ENA — T1C1 RST ENA — T1EDGE POLARITY — T1EDGE DET ENA T1CTL4 Modes: Dual-Compare and Capture/Compare P04D — — — — T1EVT DATA IN T1EVT DATA OUT T1EVT FUNCTION T1EVT DATA DIR T1PC1 P04E T1PWM DATA IN T1PWM DATA OUT T1PWM FUNCTION T1PWM DATA DIR T1IC/CR DATA IN T1IC/CR DATA OUT T1IC/CR FUNCTION T1IC/CR DATA DIR T1PC2 P04F T1 STEST T1 PRIORITY — — — — — — T1PRI † 36 Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2 bits are ignored. POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range,VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.6 V to 7 V Input voltage range, All pins except MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.6 V to 7 V MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.6 V to 14 V Input clamp current, IIK (VI  0 or VI  VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO  0 or VO  VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current per buffer, IO (VO = 0 to VCC)) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Maximum ICC current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 mA Maximum ISS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -- 170 mA Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW Operating free-air temperature range, TA: L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --40C to 85C T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --40C to 105C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --65C to 150C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Unless otherwise noted, all voltage values are with respect to VSS. 2. Electrical characteristics are specified with all output buffers loaded with specified IO current. Exceeding the specified IO current in any buffer can affect the levels on other buffers. recommended operating conditions VCC VIL VIH Supply voltage (see Note 1) Hi h l High-level l input i t voltage lt TA MC (mode control) voltage Operating free free-air air temperature MAX 4.5 5 UNIT 5.5 V 5.5 V All pins except MC VSS 0.8 MC, normal operation VSS 0.3 All pins except MC, XTAL2/CLKIN, and RESET 2 V VCC XTAL2/CLKIN 0.8 VCC VCC RESET 0.7 VCC VCC EEPROM write protect override (WPO) VMC NOM 3 RAM data-retention supply voltage (see Note 3) Low level input voltage Low-level MIN 11.7 12 13 EPROM programming voltage (VPP) 13 13.2 13.5 Microcomputer VSS 0.3 70 L version 0 A version -- 40 85 T version -- 40 105 V V C C NOTES: 1. Unless otherwise noted, all voltage values are with respect to VSS. 3. RESET must be externally activated when VCC or SYSCLK is not within the recommended operating range. POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 37 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOL Low-level output voltage VOH High level output voltage High-level II Input current IOL Low-level output current IOH High le el output High-level o tp t current c rrent TEST CONDITIONS IOH = --50 A IOH = --2 mA MC I/O pins TYP See Note 4 12 V  VI  13 V 50 0 V  VI  VCC  10 1.4 V A A mA A mA -- 50 A -- 2 mA See Notes 5 and 6 SYSCLK = 5 MHz 20 36 See Notes 5 and 6 SYSCLK = 3 MHz 13 25 See Notes 5 and 6 SYSCLK = 0.5 MHz 5 11 See Notes 5 and 6 SYSCLK = 5 MHz 10 17 See Notes 5 and 6 SYSCLK = 3 MHz 6.5 11 2 3.5 See Notes 5 and 6 SYSCLK = 3 MHz 4.5 8.6 See Notes 5 and 6 SYSCLK = 0.5 MHz 1.5 3.0 1 30 See Note 5 XTAL2/CLKIN < 0.2 V UNIT V 2.4 650 See Notes 5 and 6 SYSCLK = 0.5 MHz Supply current (HALT mode) 0.9 VCC 0.3 V < VI  13 V VOH = 0.9 VCC Supply current (STANDBY mode) OSC POWER bit = 1 (see Note 9) 0.4 10 VOH = 2.4 V Supply current (STANDBY mode) OSC POWER bit = 0 (see Note 8) MAX 0 V  VI  0.3 V VOL = 0.4 V Supply current (operating mode) OSC POWER bit = 0 (see Note 7) ICC MIN IOL = 1.4 mA mA mA mA A NOTES: 4. Input current IPP is a maximum of 50 mA only when you are programming EPROM. 5. Single chip mode, ports configured as inputs or outputs with no load. All inputs  0.2 V or  VCC -- 0.2V. 6. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 7. Maximum operating current = 5.6 (SYSCLK) + 8 mA. 8. Maximum standby current = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0). 9. Maximum standby current = 2.24 (SYSCLK) + 1.9 mA. (OSC POWER bit = 1, only valid up to 3 MHz SYSCLK). 38 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 XTAL2/CLKIN C1 (see Note B) XTAL1 Crystal/Ceramic Resonator (see Note A) XTAL2/CLKIN C2 (see Note B) XTAL1 C3 (see Note B) External Clock Signal NOTES: A. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period. B. The values of C1 and C2 are typically 15 pF and the value of C3 is typically 50 pF. See the manufacturer’s recommendations for ceramic resonators. Figure 14. Recommended Crystal/Clock Connections Load Voltage 1.2 k VO 20 pF Case 1: VO = VOH = 2.4 V; Load Voltage = 0 V Case 2: VO = VOL = 0.4 V; Load Voltage = 2.1 V NOTE A: All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated. Figure 15. Typical Output Load Circuit (See Note A) VCC VCC Pin Data 300  30  Output Enable I/O 6 k INT1 20  20  GND GND Figure 16. Typical Buffer Circuitry POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 39 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 PARAMETER MEASUREMENT INFORMATION timing parameter symbology Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: AR Array SC SYSCLK B Byte SIMO SPISIMO CI XTAL2/CLKIN SOMI SPISOMI M Master mode SPC SPICLK S Slave mode Lowercase subscripts and their meanings are: c cycle time (period) su setup time d delay time v valid time f fall time w pulse duration (width) r rise time The following additional letters are used with these meanings: H High L Low V Valid All timings are measured between high and low measurement points as indicated in Figure 17 and Figure 18. 0.8 VCC V (High) 2 V (High) 0.8 V (Low) 0.8 V (Low) Figure 17. XTAL2/CLKIN Measurement Points 40 POST OFFICE BOX 1443 Figure 18. General Measurement Points  HOUSTON, TEXAS 77251--1443 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 external clocking requirements for clock divided by 4 (see Note 10 and Figure 19) NO. PARAMETER MIN MAX 20 UNIT 1 tw(Cl) Pulse duration, XTAL2/CLKIN (see Note 11) 2 tr(Cl) Rise time, XTAL2/CLKIN 30 ns ns 3 tf(CI) Fall time, XTAL2/CLKIN 30 ns 4 td(CIH-SCL) Delay time, XTAL2/CLKIN rise to SYSCLK fall CLKIN Crystal operating frequency SYSCLK Internal system clock operating frequency† 100 ns 2 20 MHz 0.5 5 MHz † SYSCLK = CLKIN/4 NOTES: 10. For VIL and VIH, refer to recommended operating conditions. 11. This pulse may be either a high pulse which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 1 XTAL2/CLKIN 2 3 4 SYSCLK Figure 19. External Clock Timing for Divide-by-4 external clocking requirements for clock divided by 1 (PLL) (see Note 10 and Figure 20) NO. PARAMETER MIN MAX 20 UNIT 1 tw(Cl) Pulse duration, XTAL2/CLKIN (see Note 11) ns 2 tr(Cl) Rise time, XTAL2/CLKIN 30 ns 3 tf(CI) Fall time, XTAL2/CLKIN 30 ns 4 td(CIH-SCH) Delay time, XTAL2/CLKIN rise to SYSCLK rise 100 ns CLKIN Crystal operating frequency 2 5 MHz SYSCLK Internal system clock operating frequency‡ 2 5 MHz ‡ SYSCLK = CLKIN/1 NOTES: 10. For VIL and VIH, refer to recommended operating conditions. 11. This pulse can be either a high pulse which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 1 XTAL2/CLKIN 2 3 4 SYSCLK Figure 20. External Clock Timing for Divide-by-1 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 41 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 switching characteristics and timing requirements (see Note 12 and Figure 21) NO. PARAMETER MIN MAX Divide by 4 200 2000 Divide by 1 200 500 5 tc Cycle time, time SYSCLK 6 tw(SCL) Pulse duration, SYSCLK low 0.5 tc --20 7 tw(SCH) Pulse duration, SYSCLK high 0.5 tc UNIT ns 0.5 tc ns 0.5 tc + 20 ns NOTE 12: tc = system-clock cycle time = 1/SYSCLK 5 7 6 SYSCLK Figure 21. SYSCLK Timing general purpose output signal switching time requirements (see Figure 22) MIN NOM MAX UNIT tr Rise time 30 ns tf Fall time 30 ns tr tf Figure 22. Signal Switching Timing recommended EEPROM timing requirements for programming MIN MAX UNIT tw(PGM)B Pulse duration, programming signal to ensure valid data is stored (byte mode) 10 ms tw(PGM)AR Pulse duration, programming signal to ensure valid data is stored (array mode) 20 ms recommended EPROM operating conditions for programming VCC Supply voltage VPP Supply voltage at MC pin IPP Supply current at MC pin during programming (VPP = 13 V) SYSCLK S stem clock System MIN NOM MAX 4.75 5.5 6 13 13.2 13.5 30 50 Divide by 4 0.5 5 Divide by 1 2 5 UNIT V V mA MH MHz recommended EPROM timing requirements for programming tw(EPGM) Pulse duration, programming signal (see Note 13) NOTE 13: Programming pulse is active when both EXE (EPCTL.0) and VPPS (EPCTL.6) are set. 42 POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 MIN NOM MAX 0.40 0.50 3 UNIT ms TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 SPI master mode external timing characteristics and requirements (see Note 12 and Figure 23) NO. MIN 2tc MAX UNIT 256tc ns 38 tc(SPC)M Cycle time, SPICLK 39 tw(SPCL)M Pulse duration, SPICLK low tc -- 45 0.5tc(SPC)+45 ns 40 tw(SPCH)M Pulse duration, SPICLK high tc -- 55 0.5tc(SPC)+45 ns 41 td(SPCL-SIMOV)M Delay time, SPISIMO valid after SPICLK low (polarity = 1) 50 ns 42 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (polarity =1) tw(SPCH) -- 50 ns 43 tsu(SOMI-SPCH)M Setup time, SPISOMI to SPICLK high (polarity = 1) 0.25 tc + 150 ns 44 tv(SPCH-SOMI)M Valid time, SPISOMI data valid after SPICLK high (polarity = 1) -- 65 0 ns NOTE 12: tc = system-clock cycle time = 1/SYSCLK 38 40 39 SPICLK 41 42 Data Valid SPISIMO 43 44 SPISOMI Data Valid NOTE A: The diagram is for polarity = 1. SPICLK is inverted when polarity = 0. Figure 23. SPI Master External Timing POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 43 TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 SPI slave mode external timing characteristics and requirements (see Note 12 and Figure 24) NO. MIN UNIT 45 tc(SPC)S Cycle time, SPICLK 8tc 46 tw(SPCL)S Pulse duration, SPICLK low 4tc -- 45 0.5tc(SPC)S+45 ns 47 tw(SPCH)S Pulse duration, SPICLK high 4tc -- 45 0.5tc(SPC)S+45 ns 48 td(SPCL-SOMIV)S Delay time, SPISOMI valid after SPICLK low (polarity = 1) 3.25tc + 130 ns 49 tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (polarity =1) 50 tsu(SIMO-SPCH)S Setup time, SPISIMO to SPICLK high (polarity = 1) 51 tv(SPCH-SIMO)S Valid time, SPISIMO data after SPICLK high (polarity = 1) NOTE 12: tc = system-clock cycle time = 1/SYSCLK 45 47 46 SPICLK 48 49 Data Valid SPISIMO 50 51 SPISOMI Data Valid NOTE A: The diagram is for polarity = 1. SPICLK is inverted when polarity = 0. Figure 24. SPI Slave External Timing 44 MAX POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 tw(SPCH)S 0 3tC + 100 ns ns ns ns TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 Table 20 is designed to aid the user in referencing a device part number to a mechanical drawing. The table shows a cross-reference of the device part number to the TMS370 generic package name and the associated mechanical drawing by drawing number and name. Table 20. TMS370Cx1x Family Package Type and Mechanical Cross-Reference PKG TYPE (mil pin spacing) PKG TYPE NO. AND MECHANICAL NAME TMS370 GENERIC NAME DEVICE PART NUMBERS FN -- 28 pin (50-mil pin spacing) PLASTIC LEADED CHIP CARRIER (PLCC) FN(S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER TMS370C010AFNA TMS370C010AFNL TMS370C010AFNT TMS370C012AFNA TMS370C012AFNL TMS370C012AFNT TMS370C310AFNA TMS370C310AFNL TMS370C310AFNT TMS370C311AFNA TMS370C311AFNL TMS370C311AFNT TMS370C312AFNA TMS370C312AFNL TMS370C312AFNT TMS370C712AFNT TMS370C712BFNT FZ -- 28 pin (50-mil pin spacing) CERAMIC LEADED CHIP CARRIER (CLCC) FZ(S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER SE370C712AFZT SE370C712BFZT JD -- 28 pin (100-mil pin spacing) CERAMIC DUAL-IN-LINE PACKAGE (CDIP) JD(R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE SE370C712AJDT SE370C712BJDT N(R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE TMS370C010ANA TMS370C010ANL TMS370C010ANT TMS370C012ANA TMS370C012ANL TMS370C012ANT TMS370C310ANA TMS370C310ANL TMS370C310ANT TMS370C311ANA TMS370C311ANL TMS370C311ANT TMS370C312ANA TMS370C312ANL TMS370C312ANT TMS370C712ANT TMS370C712BNT N -- 28 pin (100-mil pin spacing) PLASTIC DUAL-IN-LINE PACKAGE (PDIP) POST OFFICE BOX 1443  HOUSTON, TEXAS 77251--1443 45 MECHANICAL DATA MCDI005 – JANUARY 1998 JD (R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE 24 PINS SHOWN A 24 13 0.590 (15,00) TYP 1 12 0.065 (1,65) 0.045 (1,14) 0.620 (15,75) 0.590 (14,99) 0.175 (4,45) 0.140 (3,56) 0.075 (1,91) MAX (4 Places) Seating Plane 0.020 (0,51) MIN 0.021 (0,53) 0.015 (0,38) 0.100 (2,54) PINS ** DIM A MAX 0°– 15° 0.125 (3,18) MIN 0.012 (0,30) 0.008 (0,20) 24 28 40 48 52 1.250 (31,75) 1.450 (36,83) 2.050 (52,07) 2.435 (61,85) 2.650 (67,31) 4040087/B 04/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package is hermetically sealed with a metal lid. The terminals are gold-plated. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDI008 – OCTOBER 1994 N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 24 PIN SHOWN A 24 13 0.560 (14,22) 0.520 (13,21) 1 12 0.060 (1,52) TYP 0.200 (5,08) MAX 0.610 (15,49) 0.590 (14,99) 0.020 (0,51) MIN Seating Plane 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.125 (3,18) MIN 0.010 (0,25) M PINS ** 0°– 15° 0.010 (0,25) NOM 24 28 32 40 48 52 A MAX 1.270 (32,26) 1.450 (36,83) 1.650 (41,91) 2.090 (53,09) 2.450 (62,23) 2.650 (67,31) A MIN 1.230 (31,24) 1.410 (35,81) 1.610 (40,89) 2.040 (51,82) 2.390 (60,71) 2.590 (65,79) DIM 4040053 / B 04/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MS-011 Falls within JEDEC MS-015 (32 pin only) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MJLC003A – FEBRUARY 1995 FZ (S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER 28 LEAD SHOWN 0.040 (1,02)  45° Seating Plane 0.180 (4,57) A 0.155 (3,94) 0.140 (3,55) B 4 1 0.120 (3,05) 26 25 5 A B 0.050 (1,27) C (at Seating Plane) 0.032 (0,81) 0.026 (0,66) 0.020 (0,51) 0.014 (0,36) 19 11 18 12 0.025 (0,64) R TYP 0.040 (1,02) MIN 0.120 (3,05) 0.090 (2,29) B A C JEDEC NO. OF OUTLINE PINS** MIN MAX MIN MAX MIN MAX MO-087AA 28 0.485 (12,32) 0.495 (12,57) 0.430 (10,92) 0.455 (11,56) 0.410 (10,41) 0.430 (10,92) MO-087AB 44 0.685 (17,40) 0.695 (17,65) 0.630 (16,00) 0.655 (16,64) 0.610 (15,49) 0.630 (16,00) MO-087AC 52 0.785 (19,94) 0.795 (20,19) 0.730 (18,54) 0.765 (19,43) 0.680 (17,28) 0.740 (18,79) MO-087AD 68 0.985 (25,02) 0.995 (25,27) 0.930 (23,62) 0.955 (24,26) 0.910 (23,11) 0.930 (23,62) 4040219 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) SE370C712AFZT OBSOLETE JLCC FZ 28 TBD Call TI Call TI SE370C712AJDT OBSOLETE CDIP SB JD 28 TBD Call TI Call TI SE370C712BFZT OBSOLETE JLCC FZ 28 TBD Call TI Call TI SE370C712BJDT OBSOLETE CDIP SB JD 28 TBD Call TI Call TI TMS370C012AFNA NRND PLCC FN 28 TBD Call TI Call TI TMS370C012AFNL NRND PLCC FN 28 TBD Call TI Call TI TMS370C310AFNA NRND PLCC FN 28 TBD Call TI Call TI TMS370C310AFNL NRND PLCC FN 28 TBD Call TI Call TI TMS370C712AFNT OBSOLETE PLCC FN 28 TBD Call TI Call TI TMS370C712BFNT OBSOLETE PLCC FN 28 TBD Call TI Call TI TMS370C712BNT OBSOLETE PDIP N 28 TBD Call TI Call TI Op Temp (°C) Device Marking (4/5) TMS @1986 TI 370C712AFNT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2014 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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