TMS5701114BPGEQQ1

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 TMS570LS1114 16- and 32-Bit RISC Flash Microcontroller 1 Device Overview 1.1 Features 1 • High-Performance Automotive-Grade Microcontroller for Safety-Critical Applications – Dual CPUs Running in Lockstep – ECC on Flash and RAM Interfaces – Built-In Self-Test (BIST) for CPU and On-chip RAMs – Error Signaling Module With Error Pin – Voltage and Clock Monitoring • ARM® Cortex®-R4F 32-Bit RISC CPU – 1.66 DMIPS/MHz With 8-Stage Pipeline – FPU With Single- and Double-Precision – 12-Region Memory Protection Unit (MPU) – Open Architecture With Third-Party Support • Operating Conditions – Up to 180-MHz System Clock – Core Supply Voltage (VCC): 1.14 to 1.32 V – I/O Supply Voltage (VCCIO): 3.0 to 3.6 V • Integrated Memory – 1MB of Program Flash With ECC – 128KB of RAM With ECC – 64KB of Flash for Emulated EEPROM With ECC • 16-Bit External Memory Interface (EMIF) • Common Platform Architecture – Consistent Memory Map Across Family – Real-Time Interrupt (RTI) Timer (OS Timer) – 128-Channel Vectored Interrupt Module (VIM) – 2-Channel Cyclic Redundancy Checker (CRC) • Direct Memory Access (DMA) Controller – 16 Channels and 32 Control Packets – Parity Protection for Control Packet RAM – DMA Accesses Protected by Dedicated MPU • Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In Slip Detector • Separate Nonmodulating PLL • IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight™ Components • Advanced JTAG Security Module (AJSM) • Calibration Capabilities – Parameter Overlay Module (POM) • 16 General-Purpose Input/Output (GPIO) Pins Capable of Generating Interrupts • Enhanced Timing Peripherals for Motor Control – 7 Enhanced Pulse Width Modulator (ePWM) Modules – 6 Enhanced Capture (eCAP) Modules – 2 Enhanced Quadrature Encoder Pulse (eQEP) Modules • Two Next Generation High-End Timer (N2HET) Modules – N2HET1: 32 Programmable Channels – N2HET2: 18 Programmable Channels – 160-Word Instruction RAM Each With Parity Protection – Each N2HET Includes Hardware Angle Generator – Dedicated High-End Timer Transfer Unit (HTU) for Each N2HET • Two 12-Bit Multibuffered Analog-to-Digital Converter (MibADC) Modules – ADC1: 24 Channels – ADC2: 16 Channels Shared With ADC1 – 64 Result Buffers Each With Parity Protection • Multiple Communication Interfaces – Three CAN Controllers (DCANs) • 64 Mailboxes Each With Parity Protection • Compliant to CAN Protocol Version 2.0A and 2.0B – Inter-Integrated Circuit (I2C) – Three Multibuffered Serial Peripheral Interface (MibSPI) Modules • 128 Words Each With Parity Protection • 8 Transfer Groups – Up to Two Standard Serial Peripheral Interface (SPI) Modules – Two UART (SCI) Interfaces, One With Local Interconnect Network (LIN 2.1) Interface Support • Packages – 144-Pin Quad Flatpack (PGE) [Green] – 337-Ball Grid Array (ZWT) [Green] 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 1.2 • • • • Applications Braking Systems (ABS and ESC) Electric Power Steering (EPS) HEV and EV Inverter Systems Battery Management Systems 1.3 www.ti.com • • • • Active Driver Assistance Systems Aerospace and Avionics Railway Communications Off-road Vehicles Description The TMS570LS1114 device is a high-performance automotive-grade microcontroller family for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os. The TMS570LS1114 device integrates the ARM Cortex-R4F floating-point CPU which offers an efficient 1.66 DMIPS/MHz, and has configurations which can run up to 180 MHz providing up to 298 DMIPS. The device supports the word-invariant big-endian [BE32] format. The TMS570LS1114 device has 1MB of integrated flash and 128KB of data RAM with single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable and programmable memory, implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-word modes throughout the supported frequency range. The TMS570LS1114 device features peripherals for real-time control-based applications, including two Next Generation High-End Timer (N2HET) timing coprocessors with up to 44 I/O terminals, seven Enhanced Pulse Width Modulator (ePWM) modules with up to 14 outputs, six Enhanced Capture (eCAP) modules, two Enhanced Quadrature Encoder Pulse (eQEP) modules, and two 12-bit Analog-to-Digital Converters (ADCs) supporting up to 24 inputs. The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or general-purpose I/O (GIO). The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU. The ePWM module can generate complex pulse width waveforms with minimal CPU overhead or intervention. The ePWM is easy to use and it supports both high-side and low-side PWM and deadband generation. With integrated trip zone protection and synchronization with the on-chip MibADC, the ePWM module is ideal for digital motor control applications. The eCAP module is essential in systems where the accurately timed capture of external events is important. The eCAP can also be used to monitor the ePWM outputs or for simple PWM generation when the eCAP is not needed for capture applications. The eQEP module is used for direct interface with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine as used in high-performance motion and position-control systems. 2 Device Overview Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 The device has two 12-bit-resolution MibADCs with 24 total inputs and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen inputs are shared between the two MibADCs. Each MibADC supports three separate groupings of channels. Each group can be converted once when triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster conversion time is desired. MibADC1 also supports the use of external analog multiplexers. The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three DCANs, and one I2C. The SPI provides a convenient method of serial high-speed communications between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for example, automotive and industrial fields) that require reliable serial communication or multiplexed wiring. The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports speeds of 100 and 400 Kbps. A Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. The Global Clock Module (GCM) manages the mapping between the available clock sources and the device clock domains. The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous external clock on the ECLK terminal. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency. The Direct Memory Access (DMA) controller has 16 channels, 32 control packets, and parity protection on its memory. An MPU is built into the DMA to protect memory against erroneous transfers. The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt or external error pin (ball) is triggered when a fault is detected. The nERROR terminal can be monitored externally as an indicator of a fault condition in the microcontroller. The External Memory Interface (EMIF) provides a memory extension to asynchronous and synchronous memories or other slave devices. A Parameter Overlay Module (POM) enhances the calibration capabilities of application code. The POM can reroute flash accesses to internal memory or to the EMIF, thus avoiding the reprogramming steps necessary for parameter updates in flash. With integrated safety features and a wide choice of communication and control peripherals, the TMS570LS1114 device is an ideal solution for high-performance real-time control applications with safetycritical requirements. Table 1-1. Device Information (1) PACKAGE BODY SIZE TMS570LS1114ZWT PART NUMBER NFBGA (337) 16.0 mm × 16.0 mm TMS570LS1114PGE LQFP (144) 20.0 mm × 20.0 mm (1) For more information, see Section 9, Mechanical Packaging and Orderable Information. Device Overview Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 3 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 1.4 www.ti.com Functional Block Diagram NOTE The block diagram reflects the 337BGA package. Some pins are multiplexed or not available in the 144QFP. For details, see the respective terminal functions tables in Section 4.3. 128kB RAM with ECC 32K 32K 1MB Flash with ECC 32K 32K DMA Dual Cortex-R4F CPUs in Lockstep HTU1 POM HTU2 Switched Central Resource Switched Central Resource Main Cross Bar: Arbitration and Prioritization Control CRC Switched Central Resource 64 KB Flash for EEPROM Emulation with ECC EMIF EMIF_nWAIT EMIF_CLK EMIF_CKE EMIF_nCS[4:2] EMIF_nCS[0] EMIF_ADDR[12:0] EMIF_BA[1:0] EMIF_DATA[15:0] EMIF_nDQM[1:0] EMIF_nOE EMIF_nWE EMIF_nRAS EMIF_nCAS eQEPxA eQEPxB eQEPxS eQEPxI eQEP 1,2 eCAP 1..6 always on SYS nPORRST nRST ECLK ESM nERROR IOMM PMM DCAN1 eCAP[6:1] VIM nTZ[3:1] SYNCO SYNCI ePWMxA ePWMxB ePWM 1..7 DCAN2 DCAN3 RTI Color Legend for Power Domains Core/RAM Peripheral Central Resource Bridge Switched Central Resource MibSPI1 MIBSPI1_nCS[5:0] MIBSPI1_nENA DCC1 SPI2 DCC2 MibSPI3 RAM Core #1 #2 #1 #3 #5 SPI4 I2C_SCL I2C I2C_SDA GIOB[7:0] GIO GIOA[7:0] N2HET2_PIN_nDIS N2HET2[15:0] N2HET2[18,16] N2HET1[31:0] AD2EVT N2HET1_PIN_nDIS AD1IN[23:16] \ AD2IN[7:0] VCCAD VSSAD ADREFHI ADREFLO MibADC2 N2HET1 N2HET2 AD1IN[15:8] \ AD2IN[15:8] AD1EVT AD1IN[7:0] MibADC1 CAN1_RX CAN1_TX CAN2_RX CAN2_TX CAN3_RX CAN3_TX MIBSPI1_CLK MIBSPI1_SIMO[1:0] MIBSPI1_SOMI[1:0] MibSPI5 SPI2_CLK SPI2_SIMO SPI2_SOMI SPI2_nCS[1:0] SPI2_nENA MIBSPI3_CLK MIBSPI3_SIMO MIBSPI3_SOMI MIBSPI3_nCS[5:0] MIBSPI3_nENA SPI4_CLK SPI4_SIMO SPI4_SOMI SPI4_nCS0 SPI4_nENA MIBSPI5_CLK MIBSPI5_SIMO[3:0] MIBSPI5_SOMI[3:0] MIBSPI5_nCS[3:0] MIBSPI5_nENA LIN LIN_RX LIN_TX SCI SCI_RX SCI_TX Figure 1-1. Functional Block Diagram 4 Device Overview Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table of Contents 1 2 3 4 5 Device Overview ......................................... 1 Device Memory Map Features .............................................. 1 6.10 Flash Memory ....................................... 75 1.2 Applications ........................................... 2 6.11 Tightly Coupled RAM Interface Module ............. 78 1.3 Description ............................................ 2 6.12 Parity Protection for Accesses to Peripheral RAMs 1.4 Functional Block Diagram ............................ 4 6.13 On-Chip SRAM Initialization and Testing Revision History ......................................... 6 Device Comparison ..................................... 8 Terminal Configuration and Functions ............. 9 6.14 4.1 PGE QFP Package Pinout (144-Pin) ................. 9 6.17 4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array) 10 6.18 4.3 Terminal Functions 11 6.19 41 6.20 Specifications 5.1 ................................. .......................................... Absolute Maximum Ratings Over Operating FreeAir Temperature Range ............................ 41 ........................................ 6.15 6.16 6.21 7 78 ........... 80 External Memory Interface (EMIF) .................. 82 Vectored Interrupt Manager ......................... 90 DMA Controller ...................................... 94 Real Time Interrupt Module ......................... 96 Error Signaling Module .............................. 98 Reset / Abort / Error Sources ...................... 102 Digital Windowed Watchdog ....................... 105 Debug Subsystem ................................. 106 Peripheral Information and Electrical Specifications ......................................... 111 ESD Ratings 5.3 Power-On Hours (POH) ............................. 41 7.1 Enhanced Translator PWM Modules (ePWM) ..... 111 5.4 5.5 Device Recommended Operating Conditions....... 42 Switching Characteristics Over Recommended Operating Conditions for Clock Domains ........... 43 7.2 Enhanced Capture Modules (eCAP) ............... 116 7.3 Enhanced Quadrature Encoder (eQEP) ........... 118 7.4 Multibuffered 12bit Analog-to-Digital Converter.... 119 7.5 General-Purpose Input/Output ..................... 131 7.6 Enhanced High-End Timer (N2HET) 7.7 Controller Area Network (DCAN) .................. 136 7.8 Local Interconnect Network Interface (LIN) ........ 137 5.8 5.9 41 69 5.2 5.6 5.7 6 ................................ 6.9 1.1 Wait States Required ............................... 43 Power Consumption Over Recommended Operating Conditions ................................ 44 Input/Output Electrical Characteristics Over Recommended Operating Conditions ............... 45 Thermal Resistance Characteristics ................ 45 ...................... 5.10 Output Buffer Drive Strengths 5.11 Input Timings ........................................ 47 5.12 Output Timings ...................................... 47 5.13 Low-EMI Output Buffers ............................ 46 49 8 System Information and Electrical Specifications ........................................... 50 6.1 Device Power Domains ............................. 50 6.2 Voltage Monitor Characteristics ..................... 50 6.3 Power Sequencing and Power On Reset ........... 52 6.4 Warm Reset (nRST)................................. 54 6.5 ARM Cortex-R4F CPU Information 6.6 6.7 6.8 ................. Clocks ............................................... Clock Monitoring .................................... Glitch Filters ......................................... 58 66 68 Serial Communication Interface (SCI) ............. 138 7.10 7.11 Inter-Integrated Circuit (I2C) ....................... 139 Multibuffered / Standard Serial Peripheral Interface ............................................ 142 Device and Documentation Support .............. 154 8.1 Device and Development-Support Tool Nomenclature ...................................... 154 8.2 Documentation Support ............................ 156 8.3 Trademarks ........................................ 156 8.4 Electrostatic Discharge Caution 8.6 8.7 9 132 7.9 8.5 55 .............. ................... Glossary............................................ Device Identification................................ Module Certifications............................... 156 156 157 159 Mechanical Packaging and Orderable Information ............................................. 164 9.1 Packaging Information ............................. 164 Table of Contents Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 5 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 2 Revision History This data manual revision history highlights the technical changes made to the SPNS188A device-specific data manual addendum to make it an SPNS188B revision. Scope: Applicable updates to the Hercules™ TMS570 MCU device family, specifically relating to the TMS570LS1114 devices, which are now in the production data (PD) stage of development have been incorporated. Changes from September 1, 2013 to February 28, 2015 (from A Revision (September 2013) to B Revision) • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 6 Page Updated/Changed section title to "Device Overview" ........................................................................... 1 Updated/changed the N2HET feature ............................................................................................. 1 Added Table 1-1, Device Information .............................................................................................. 3 Added Section 3, Device Comparison ............................................................................................. 8 Updated/Changed section title to "Terminal Configuration and Functions" ................................................... 9 Table 4-2 (PGE Enhanced High-End Timer Modules (N2HET)) Updated/Changed N2HET1 time input capture or output compare pin description .................................................................................................... 13 Table 4-2 Updated/Changed N2HET2 time input capture or output compare pin description ............................ 14 Table 4-5Updated/Changed the EPWM1SYNCI Signal Type from "Output" to "Input" .................................... 15 Table 4-5Updated/Changed the EPWM1SYNCI pin description from "Output" to "Input" ................................. 15 Table 4-15 (PGE Test and Debug Modules Interface): Updated/Changed TEST pin description ........................ 20 Table 4-21 (ZWT Enhanced High-End Timer Modules (N2HET)) Updated/Changed N2HET1 time input capture or output compare pin description ................................................................................................ 24 Table 4-21 Updated/Changed N2HET2 time input capture or output compare pin description .......................... 25 Updated/Changed the EPWM1SYNCI pin description from "Output" to "Input" ............................................ 27 Table 4-32 (External Memory Interface (EMIF)): Global: Deleted EMIF_RNW pin function............................... 32 Table 4-35 (ZWT Test and Debug Modules Interface): Updated/Changed TEST pin description ....................... 35 Table 4-37 Changed six BGA balls from NC to Reserved ..................................................................... 35 Updated/Changed section title to "Specifications" ............................................................................. 41 Moved Storage temperature range, Tstg back to Section 5.1, Absolute Maximum Ratings Over Operating FreeAir Temperature Range ............................................................................................................ 41 Added Section 5.2, Handling Ratings (Automotive) ............................................................................ 41 Added Section 5.3, Power-On-Hours (POH) .................................................................................... 41 Moved Thermal Data section here. ............................................................................................... 45 Section 5.9 (Thermal Resistance Characteristics): Updated/Changed title from "Thermal Data" to "Thermal Resistance Characteristics" ........................................................................................................ 45 Added ΘJA test conditions and added ΨJT for PGE package .................................................................. 45 Added ΘJA test conditions and added ΨJT for ZWT package.................................................................. 45 Clarified impact of SPI2PC9 register on drive strength of SPI2SOMI pin .................................................. 47 Changed the number of cycles of tv(RST) from 2252 to 2256 ................................................................... 54 Section 6.9.1 (Memory Map Diagram): Updated/Changed memory map (Figure 6-10 .................................... 69 Table 6-22 (Flash Memory Banks and Sectors): Updated/Changed the BANK 0 Sector No. to support 1MB Flash .. 75 Table 6-22: Added associated footnotes ........................................................................................ 75 Figure 6-11 (TCRAM Block Diagram): Updated/Changed figure ............................................................. 78 Added table notes identifying address ranges of ESRAM PBIST groups ................................................... 80 Updated/Changed N2HET2 RAM ending address from "0xFF57FFFF" to "0xFF45FFFF" in Table 6-26, Memory Initialization .......................................................................................................................... 81 Updated EMIF Timings ............................................................................................................ 82 Changed maximum addressable size of asynchronous memories from 16MB to 32KB .................................. 82 Updated/Changed the EMIF address bus signals from "EMIF_ADDR[21:0]" to "EMIF_ADDR[12:0]" for all figures in Section 6.14.2, Electrical and Timing Specifications ........................................................................ 82 Updated/Changed EMIF address from "EMIF_ADDR[21:0]" to "EMIF_ADDR[12:0]" ...................................... 82 Added "E = EMIF_CLK period in ns." footnote .................................................................................. 84 Added MIN value to EMIF clock period in Table 6-27, EMIF Asynchronous Memory Timing Requirements ........... 84 Changed EMIF tsu(EMDV-EMOEH) from 30nS to 9nS ................................................................................ 84 Changed EMIF th(EMOEH-EMDIV) from 0.5nS to 0nS ............................................................................... 84 Changed EMIF tsu(EMOEL-EMWAIT) from 4E+30nS to 4E+9nS .................................................................... 84 Changed EMIF tsu(EMWEL-EMWAIT) from 4E+30nS to 4E+14nS................................................................... 84 Changed EMIF tsu(EMCEL-EMOEL) from (RS)*E-5 to (RS)*E-6 ..................................................................... 85 Revision History Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Changed EMIF tsu(EMCEL-EMOEL) from -5 to -6 ..................................................................................... 85 Changed EMIF th(EMOEH-EMCEH) from (RH)*E -4 to (RH)*E -3 ................................................................... 85 Changed EMIF th(EMOEH-EMCEH) from (RH)*E +4 to (RH)*E +5 .................................................................. 85 Changed EMIF th(EMOEH-EMCEH) from -4 to -3 ...................................................................................... 85 Changed EMIF th(EMOEH-EMCEH) from +4 to +5 .................................................................................... 85 Changed EMIF tsu(EMBAV-EMOEL) from (RS)*E-5 to (RS)*E-6..................................................................... 85 Changed EMIF th(EMOEH-EMBAIV) from (RS)*E-4 to (RS)*E-3 ..................................................................... 85 Changed EMIF tsu(EMAV-EMOEL) from (RS)*E-5 to (RS)*E-6 ...................................................................... 85 Changed EMIF th(EMOEH-EMAIV) from (RS)*E-4 to (RS)*E-3 ...................................................................... 85 Changed EMIF td(EMWAITH-EMOEH) from 3E-3 to 3E+9 ............................................................................ 85 Changed EMIF td(EMWAITH-EMOEH) from 4E+30 to 4E+20 ......................................................................... 85 Changed EMIF tsu(EMDQMV-EMOEL) from (RS)*E-5 to (RS)*E-6 ................................................................... 85 Changed EMIF th(EMOEH-EMDQMIV) from (RS)*E-4 to (RS)*E-3 ................................................................... 85 Changed EMIF tsu(EMCEL-EMWEL) from (WS)*E -4 to (WS)*E -3 ................................................................. 86 Changed EMIF tsu(EMCEL-EMWEL) from -4 to -3 ..................................................................................... 86 Changed EMIF th(EMWEH-EMCEH) from (WS)*E -4 to (WS)*E -3 .................................................................. 86 Changed EMIF th(EMWEH-EMCEH) from -4 to -3 ..................................................................................... 86 Changed EMIF tsu(EMDQMV-EMWEL) from (WS)*E -4 to (WS)*E -3 ................................................................ 86 Changed EMIF th(EMWEH-EMDQMIV) from (WS)*E -4 to (WS)*E -3 ................................................................ 86 Changed EMIF tsu(EMBAV-EMWEL) from (WS)*E -4 to (WS)*E -3 ................................................................. 86 Changed EMIF th(EMWEH-EMBAIV) from (WS)*E -4 to (WS)*E -3 ................................................................. 86 Changed EMIF tsu(EMAV-EMWEL) from (WS)*E -4 to (WS)*E -3 ................................................................... 86 Changed EMIF th(EMWEH-EMAIV) from (WS)*E -4 to (WS)*E -3 ................................................................... 86 Changed EMIF td(EMWAITH-EMWEH) from 3E-4 to 3E+11 ........................................................................... 86 Changed EMIF td(EMWAITH-EMWEH) from 4E+30 to 4E+24 ........................................................................ 86 Changed EMIF tsu(EMDV-EMWEL) from (WS)*E -4 to (WS)*E -3 .................................................................. 86 Changed EMIF th(EMWEH-EMDIV) from (WS)*E -4 to (WS)*E -3 ................................................................... 86 Changed EMIF tsu(EMDQMV-EMWEL) from (WS)*E -4 to (WS)*E -3 ................................................................ 86 Changed EMIF th(EMWEH-EMDQMIV) from (WS)*E -4 to (WS)*E -3 ................................................................ 86 Added JTAG ID for revision C silicon .......................................................................................... 106 Revised description of ePWM Trip Zone Timing Requirement tw(TZ) ........................................................ 115 Corrected SPI table note describing Master mode, phase = 0 condition .................................................. 146 Added Device Identification code for revision C silicon ...................................................................... 157 Changed address of die identification registers ............................................................................... 157 Updated/Changed the section title to "Mechanical Packaging and Orderable Information" ............................. 164 Section 9.1 (Packaging Information): Updated/Changed paragraph ........................................................ 164 Revision History Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 7 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 3 Device Comparison Table 3-1 lists the features of the TMS570LS1114 devices. Table 3-1. TMS570LS1114 Device Comparison (1) (2) FEATURES Generic Part Number Package CPU DEVICES TMS570LS3137ZWT (3) TMS570LS1227ZWT (3) TMS570LS1114ZWT TMS570LS1114PGE TMS570LS0714PGE TMS570LS0714PZ 337 BGA 337 BGA 337 BGA 144 QFP 144 QFP 100 QFP TMS570LS0432PZ 100 QFP ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4 Frequency (MHz) 180 180 180 160 160 100 80 Flash (KB) 3072 1280 1024 1024 768 768 384 RAM (KB) 256 192 128 128 128 128 32 Data Flash [EEPROM] (KB) 64 64 64 64 64 64 16 10/100 10/100 – – – – – 2-ch 2-ch – – – – – 3 3 3 3 3 2 2 2 (24ch) 2 (24ch) 2 (24ch) 2 (24ch) 2 (24ch) 2 (16ch) 1 (16ch) EMAC FlexRay CAN MibADC 12-bit (Ch) N2HET (Ch) 2 (44) 2 (44) 2 (44) 2 (40) 2 (40) 2 (21) 1 (19) ePWM Channels – 14 14 14 14 8 – eCAP Channels – 6 6 6 6 4 0 eQEP Channels – 2 2 2 2 1 1 3 (6 + 6 + 4) 3 (6 + 6 + 4) 3 (6 + 6 + 4) 3 (5 + 6 + 1) 3 (5 + 6 + 4) 2 (5 + 1) 1 (4) MibSPI (CS) SPI (CS) 2 (2 + 1) 2 (2 + 1) 2 (2 + 1) 1 (1) 1 (1) 1 (1) 2 SCI (LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 1 (with LIN) 1 (with LIN) I2C GPIO (INT) (4) EMIF 1 1 1 1 1 – – 144 (with 16 interrupt capable) 101 (with 16 interrupt capable) 101 (with 16 interrupt capable) 64 (with 10 interrupt capable) 64 (with 10 interrupt capable) 45 (with 9 interrupt capable) 45 (with 8 interrupt capable) 16-bit data 16-bit data 16-bit data – – – – ETM (Trace) 32-bit – – – – – – RTP/DMM YES – – – – – – Operating Temperature -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC Core Supply (V) 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V I/O Supply (V) (1) (2) (3) (4) 8 For additional device variants, see www.ti.com/tms570 This table reflects the maximum configuration for each peripheral. Some functions are multiplexed and not all pins are available at the same time. Superset device. Total number of pins that can be used as general purpose input or output when not used as part of a peripheral. Device Comparison Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 4 Terminal Configuration and Functions PGE QFP Package Pinout (144-Pin) 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 TMS N2HET1[28] N2HET1[8] MIBSPI1NCS[0] VCCIO VSS VSS VCC MIBSPI5CLK MIBSPI5SIMO[0] MIBSPI5SOMI[0] MIBSPI5NENA MIBSPI1NENA MIBSPI1CLK MIBSPI1SOMI MIBSPI1SIMO N2HET1[26] N2HET1[24] CAN1RX CAN1TX VSS VCC AD1EVT AD1IN[15] / AD2IN[15] AD1IN[23] / AD2IN[7] AD1IN[8] / AD2IN[8] AD1IN[14] / AD2IN[14] AD1IN[22] / AD2IN[6] AD1IN[6] AD1IN[13] / AD2IN[13] AD1IN[5] AD1IN[12] / AD2IN[12] AD1IN[4] AD1IN[11] / AD2IN[11] AD1IN[3] AD1IN[2] 4.1 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 AD1IN[10] / AD2IN[10] AD1IN[1] AD1IN[9] / AD2IN[9] VCCAD VSSAD ADREFLO ADREFHI AD1IN[21] / AD2IN[5] AD1IN[20] / AD2IN[4] AD1IN[19] / AD2IN[3] AD1IN[18] / AD2IN[2] AD1IN[7] AD1IN[0] AD1IN[17] / AD2IN[1] AD1IN[16] / AD2IN[0] VCC VSS MIBSPI3NCS[0] MIBSPI3NENA MIBSPI3CLK MIBSPI3SIMO MIBSPI3SOMI VSS VCC VCC VSS nPORRST VCC VSS VSS VCCIO N2HET1[15] MIBSPI1NCS[2] N2HET1[13] N2HET1[6] MIBSPI3NCS[1] GIOB[3] GIOA[0] MIBSPI3NCS[3] MIBSPI3NCS[2] GIOA[1] N2HET1[11] FLTP1 FLTP2 GIOA[2] VCCIO VSS CAN3RX CAN3TX GIOA[5] N2HET1[22] GIOA[6] VCC OSCIN Kelvin_GND OSCOUT VSS GIOA[7] N2HET1[1] N2HET1[3] N2HET1[0] VCCIO VSS VSS VCC N2HET1[2] N2HET1[5] MIBSPI5NCS[0] N2HET1[7] TEST N2HET1[9] N2HET1[4] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 nTRST TDI TDO TCK RTCK VCC VSS nRST nERROR N2HET1[10] ECLK VCCIO VSS VSS VCC N2HET1[12] N2HET1[14] GIOB[0] N2HET1[30] CAN2TX CAN2RX MIBSPI1NCS[1] LINRX LINTX GIOB[1] VCCP VSS VCCIO VCC VSS N2HET1[16] N2HET1[18] N2HET1[20] GIOB[2] VCC VSS Figure 4-1. PGE QFP Package Pinout (144-Pin) Note: Pins can have multiplexed functions. Only the default function is depicted in above diagram. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 9 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.2 www.ti.com ZWT BGA Package Ball-Map (337 Ball Grid Array) A B C D E F G H J K MIBSPI5 NCS[0] MIBSPI1 SIMO MIBSPI1 NENA MIBSPI5 CLK MIBSPI5 SIMO[0] N2HET1 [28] L M NC CAN3RX N P R AD1IN[15] AD1IN[22] / / AD1EVT AD2IN[15] AD2IN[6] 19 VSS VSS TMS N2HET1 [10] 18 VSS TCK TDO nTRST N2HET1 [8] MIBSPI1 CLK MIBSPI1 SOMI MIBSPI5 NENA MIBSPI5 SOMI[0] N2HET1 [0] NC CAN3TX NC 17 TDI nRST NC EMIF_ nWE MIBSPI5 SOMI[1] NC MIBSPI5 SIMO[3] MIBSPI5 SIMO[2] N2HET1 [31] EMIF_ nCS[3] EMIF_ nCS[2] EMIF_ nCS[4] EMIF_ nCS[0] NC 16 RTCK NC NC EMIF_ BA[1] MIBSPI5 SIMO[1] NC MIBSPI5 SOMI[3] MIBSPI5 SOMI[2] NC NC NC NC NC NC 15 NC NC NC NC NC NC NC NC NC EMIF_ DATA[0] EMIF_ DATA[1] EMIF_ DATA[2] EMIF_ DATA[3] NC NC 14 N2HET1 [26] nERROR NC NC NC VCCIO VCCIO VCCIO VCC VCC VCCIO VCCIO VCCIO VCCIO NC 13 N2HET1 [17] N2HET1 [19] NC NC EMIF_BA[0] VCCIO VCCIO 12 ECLK N2HET1 [4] NC NC EMIF_nOE VCCIO VSS VSS VCC VSS VSS 11 N2HET1 [14] N2HET1 [30] NC NC EMIF_ nDQM[1] VCCIO VSS VSS VSS VSS 10 CAN1TX CAN1RX EMIF_ ADDR[12] NC EMIF_ nDQM[0] VCC VCC VSS VSS T U V W AD1IN [6] AD1IN[11] / AD2IN[11] VSSAD VSSAD 19 AD1IN [4] AD1IN [2] VSSAD 18 AD1IN[10] / AD2IN[10] AD1IN [1] AD1IN[8] AD1IN[14] AD1IN[13] / / / AD2IN[8] AD2IN[14] AD2IN[13] AD1IN [5] AD1IN [3] AD1IN[9] / 17 AD2IN[9] AD1IN[23] AD1IN[12] AD1IN[19] / / / ADREFLO AD2IN[7] AD2IN[12] AD2IN[3] VSSAD 16 AD1IN[21] AD1IN[20] / / ADREFHI AD2IN[5] AD2IN[4] VCCAD 15 NC AD1IN[18] / AD2IN[2] AD1IN [0] 14 NC NC AD1IN[17] AD1IN[16] / / AD2IN[1] AD2IN[0] NC 13 VCCIO NC MIBSPI5 NCS[3] NC NC NC 12 VSS VCCPLL NC NC NC NC NC 11 VSS VCC VCC NC NC NC MIBSPI3 NCS[0] GIOB[3] 10 AD1IN [7] 9 N2HET1 [27] NC EMIF_ ADDR[11] NC EMIF_ ADDR[5] VCC VSS VSS VSS VSS VSS VCCIO EXTCLKI N2 NC NC MIBSPI3 CLK MIBSPI3 9 NENA 8 NC NC EMIF_ ADDR[10] NC EMIF_ ADDR[4] VCCP VSS VSS VCC VSS VSS VCCIO EMIF_ DATA[15] NC NC MIBSPI3 SOMI MIBSPI3 8 SIMO 7 LINRX LINTX EMIF_ ADDR[9] NC EMIF_ ADDR[3] VCCIO VCCIO EMIF_ DATA[14] NC NC N2HET1 [9] nPORRST 7 6 GIOA[4] MIBSPI5 NCS[1] EMIF_ ADDR[8] NC EMIF_ ADDR[2] VCCIO VCCIO VCCIO VCCIO VCC VCC VCCIO VCCIO VCCIO EMIF_ DATA[13] NC NC N2HET1 [5] MIBSPI5 6 NCS[2] 5 GIOA[0] GIOA[5] EMIF_ ADDR[7] EMIF_ ADDR[1] EMIF_ DATA[4] EMIF_ DATA[5] EMIF_ DATA[6] FLTP2 FLTP1 EMIF_ DATA[7] EMIF_ DATA[8] EMIF_ DATA[9] EMIF_ DATA[10] EMIF_ DATA[11] EMIF_ DATA[12] NC NC MIBSPI3 NCS[1] N2HET1 [2] 5 4 N2HET1 [16] N2HET1 [12] EMIF_ ADDR[6] EMIF_ ADDR[0] NC NC NC N2HET1 [21] N2HET1 [23] NC NC NC NC NC EMIF_ nCAS NC NC NC NC 4 3 N2HET1 [29] N2HET1 [22] MIBSPI3 NCS[3] SPI2 NENA N2HET1 [11] MIBSPI1 NCS[1] MIBSPI1 NCS[2] GIOA[6] MIBSPI1 NCS[3] EMIF_ CLK EMIF_ CKE N2HET1 [25] SPI2 NCS[0] EMIF_ nWAIT EMIF_ nRAS NC NC NC N2HET1 [6] 3 2 VSS MIBSPI3 NCS[2] GIOA[1] SPI2 SOMI SPI2 CLK GIOB[2] GIOB[5] CAN2TX GIOB[6] GIOB[1] KELVIN_ GND GIOB[0] N2HET1 [13] N2HET1 [20] MIBSPI1 NCS[0] NC TEST N2HET1 [1] VSS 2 1 VSS VSS GIOA[2] SPI2 SIMO GIOA[3] GIOB[7] GIOB[4] CAN2RX N2HET1 [18] OSCIN OSCOUT GIOA[7] N2HET1 [15] N2HET1 [24] NC N2HET1 [7] N2HET1 [3] VSS VSS 1 A B C D E F G H J K L M N P R T U V W Figure 4-2. ZWT Package Pinout. Top View Note: Balls can have multiplexed functions. Only the default function is depicted in above diagram. 10 Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 4.3 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Terminal Functions Section 4.3.1 and Section 4.3.2 identify the external signal names, the associated pin/ball numbers along with the mechanical package designator, the pin/ball type (Input, Output, IO, Power or Ground), whether the pin/ball has any internal pullup/pulldown, whether the pin/ball can be configured as a GPIO, and a functional pin/ball description. The first signal name listed is the primary function for that terminal. The signal name in Bold is the function being described. Refer to the I/O Multiplexing Module (IOMM) chapter of the TMS570LS12x/11x Technical Reference Manual (SPNU515). NOTE In the Terminal Functions table below, the "Reset Pull State" is the state of the pull applied to the terminal while nPORRST is low and immediately after nPORRST goes High. The default pull direction may change when software configures the pin for an alternate function. The "Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given terminal by the IOMM control registers. All I/O signals except nRST are configured as inputs while nPORRST is low and immediately after nPORRST goes High. While nPORRST is low, the input buffers are disabled, and the output buffers are disabled with the default pulls enabled. All output-only signals have the output buffer disabled and the default pull enabled while nPORRST is low, and are configured as outputs with the pulls disabled immediately after nPORRST goes High. 4.3.1 PGE Package 4.3.1.1 Multibuffered Analog-to-Digital Converters (MibADC) Table 4-1. PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2) Terminal Signal Name 144 PGE Signal Type Reset Pull State Pull Type N/A None Description ADREFHI (1) 66 Power ADREFLO (1) 67 Power ADC low reference supply VCCAD (1) 69 Power Operating supply for ADC (1) VSSAD ADC high reference supply 68 Ground AD1EVT 86 I/O Pull Down Programmable, 20 µA ADC1 event trigger input, or GPIO MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS 55 I/O Pull Up Programmable, 20 µA ADC2 event trigger input, or GPIO AD1IN[0] 60 Input N/A None AD1IN[1] 71 AD1IN[2] 73 AD1IN[3] 74 AD1IN[4] 76 AD1IN[5] 78 AD1IN[6] 80 AD1IN[7] 61 (1) ADC1 analog input The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 11 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 4-1. PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2) (continued) Terminal Signal Name 144 PGE Signal Type Reset Pull State Pull Type Description Input N/A None ADC1/ADC2 shared analog inputs AD1IN[8] / AD2IN[8] 83 AD1IN[9] / AD2IN[9] 70 AD1IN[10] / AD2IN[10] 72 AD1IN[11] / AD2IN[11] 75 AD1IN[12] / AD2IN[12] 77 AD1IN[13] / AD2IN[13] 79 AD1IN[14] / AD2IN[14] 82 AD1IN[15] / AD2IN[15] 85 AD1IN[16] / AD2IN[0] 58 AD1IN[17] / AD2IN[1] 59 AD1IN[18] / AD2IN[2] 62 AD1IN[19] / AD2IN[3] 63 AD1IN[20] / AD2IN[4] 64 AD1IN[21] / AD2IN[5] 65 AD1IN[22] / AD2IN[6] 81 AD1IN[23] / AD2IN[7] 84 MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 51 Output Pull Up None AWM1 external analog mux enable MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 52 Output Pull Up None AWM1 external analog mux select line0 MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A 53 Output Pull Up None AWM1 external analog mux select line0 12 Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 4.3.1.2 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Enhanced High-End Timer Modules (N2HET) Table 4-2. PGE Enhanced High-End Timer Modules (N2HET) Terminal Signal Name 144 PGE N2HET1[0]/SPI4CLK/EPWM2B 25 N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A 23 N2HET1[2]/SPI4SIMO[0]/EPWM3A 30 N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B 24 N2HET1[4]/EPWM4B 36 N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B 31 N2HET1[6]/SCIRX/EPWM5A 38 N2HET1[7]/N2HET2[14]/EPWM7B 33 N2HET1[8]/MIBSPI1SIMO[1] 106 N2HET1[9]/N2HET2[16]/EPWM7A 35 N2HET1[10]/nTZ3 118 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ EPWM1SYNCO N2HET1[12] Signal Type Reset Pull State Pull Type I/O Pull Down Programmable, 20 µA Description N2HET1 time input capture or output compare, or GIO. Each terminal has a suppression filter with a programmable duration. 6 124 N2HET1[13]/SCITX/EPWM5B 39 N2HET1[14] 125 N2HET1[15]/MIBSPI1NCS[4]/ECAP1 41 N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO 139 MIBSPI1NCS[1]/N2HET1[17]/EQEP1S 130 Pull Up N2HET1[18]/EPWM6A 140 Pull Down MIBSPI1NCS[2]/N2HET1[19] 40 Pull Up N2HET1[20]/EPWM6B 141 Pull Down N2HET1[22] 15 MIBSPI1NENA/N2HET1[23]/ECAP4 96 Pull Up N2HET1[24]/MIBSPI1NCS[5] 91 Pull Down MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 Pull Up N2HET1[26] 92 Pull Down MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 4 Pull Up 107 Pull Down 3 Pull Up N2HET1[30]/EQEP2S 127 Pull Down MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 Pull Up N2HET1[28] MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 13 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 4-2. PGE Enhanced High-End Timer Modules (N2HET) (continued) Terminal Signal Type Reset Pull State Pull Type 14 I/O Pull Down Programmable, 20 µA (1) GIOA[2]/N2HET2[0]/ EQEP2I 9 I/O Pull Down GIOA[6]/N2HET2[4]/EPWM1B 16 Programmable, 20 µA GIOA[7]/N2HET2[6]/EPWM2A 22 N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A 23 N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B 24 N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B 31 N2HET1[7]/N2HET2[14]/EPWM7B 33 N2HET1[9]/N2HET2[16]/EPWM7A 35 Signal Name 144 PGE GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ EPWM1SYNCO 6 MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS 55 (1) Description Disable selected PWM outputs N2HET2 time input capture or output compare, or GPIO Each terminal has a suppression filter with a programmable duration. I/O Pull Up Programmable, 20 µA (1) Disable selected PWM outputs The N2HETx_PIN_nDIS function is always available on this terminal. There is no mux control to select this function. The pull direction is controlled by the function which is selected by the output mux control for this terminal. 4.3.1.3 Enhanced Capture Modules (eCAP) Table 4-3. PGE Enhanced Capture Modules (eCAP) (1) Terminal Signal Name 144 PGE Signal Type Reset Pull State Pull Type I/O Pull Down Fixed 20 µA Pull Up Description N2HET1[15]/MIBSPI1NCS[4]/ECAP1 41 MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 51 MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 52 Enhanced Capture Module 3 I/O MIBSPI1NENA/N2HET1[23]/ECAP4 96 Enhanced Capture Module 4 I/O MIBSPI5NENA/MIBSPI5SOMI[1]/ ECAP5 97 Enhanced Capture Module 5 I/O MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 105 Enhanced Capture Module 6 I/O (1) 14 Pull Up Enhanced Capture Module 1 I/O Enhanced Capture Module 2 I/O These signals, when used as inputs, are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 4.3.1.4 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Enhanced Quadrature Encoder Pulse Modules (eQEP) Table 4-4. PGE Enhanced Quadrature Encoder Pulse Modules (eQEP) (1) Terminal Signal Name 144 PGE Signal Type Reset Pull State Pull Type Pull Up Fixed 20 µA Pull Up Description MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A 53 Input MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 Input MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS 55 I/O MIBSPI1NCS[1]/N2HET1[17]/EQEP1S 130 I/O N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A 23 Input N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B 24 Input GIOA[2]/N2HET2[0]/ EQEP2I 9 I/O Enhanced QEP2 Index 127 I/O Enhanced QEP2 Strobe N2HET1[30]/EQEP2S (1) Enhanced QEP1 Input A Enhanced QEP1 Input B Enhanced QEP1 Index Enhanced QEP1 Strobe Pull Down Enhanced QEP2 Input A Enhanced QEP2 Input B These signals are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter. 4.3.1.5 Enhanced Pulse-Width Modulator Modules (ePWM) Table 4-5. PGE Enhanced Pulse-Width Modulator Modules (ePWM) Terminal Signal Name 144 PGE Signal Type Reset Pull State Pull Type Output Pull Down None Description GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS 14 Enhanced PWM1 Output A GIOA[6]/N2HET2[4]/EPWM1B 16 Enhanced PWM1 Output B N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO 6 External ePWM Sync Pulse Output N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO 139 Input Fixed 20 µA Pull Up External ePWM Sync Pulse Input GIOA[7]/N2HET2[6]/EPWM2A 22 Output None N2HET1[0]/SPI4CLK/EPWM2B 25 Enhanced PWM2 Output B N2HET1[2]/SPI4SIMO[0]/EPWM3A 30 Enhanced PWM3 Output A N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B 31 Enhanced PWM3 Output B MIBSPI5NCS[0]/EPWM4A 32 Pull Up Enhanced PWM4 Output A N2HET1[4]/EPWM4B 36 Pull Down Enhanced PWM4 Output B N2HET1[6]/SCIRX/EPWM5A 38 Enhanced PWM5 Output A N2HET1[13]/SCITX/EPWM5B 39 Enhanced PWM5 Output B N2HET1[18]/EPWM6A 140 Enhanced PWM6 Output A N2HET1[20]/EPWM6B 141 Enhanced PWM6 Output B N2HET1[9]/N2HET2[16]/EPWM7A 35 Enhanced PWM7 Output A N2HET1[7]/N2HET2[14]/EPWM7B 33 Enhanced PWM7 Output B Enhanced PWM2 Output A Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 15 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 4-5. PGE Enhanced Pulse-Width Modulator Modules (ePWM) (continued) Terminal Signal Name 144 PGE MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 3 MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 4 N2HET1[10]/nTZ3 4.3.1.6 Signal Type Reset Pull State Pull Type Description Input Pull Up Fixed 20 µA Pull Up Trip Zone Inputs 1, 2 and 3. These signals are either connected asynchronously to the ePWMx trip zone inputs, or double-synchronized with VCLK4, or doublesynchronized and then filtered with a 6-cycle VCLK4-based counter before connecting to the ePWMx trip zone inputs. 118 Pull Down General-Purpose Input / Output (GPIO) Table 4-6. PGE General-Purpose Input / Output (GPIO) Terminal Signal Name 144 PGE GIOA[0] 2 GIOA[1] 5 Signal Type Reset Pull State Pull Type I/O Pull Down Programmable, 20 µA GIOA[2]/N2HET2[0] /EQEP2I 9 GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS 14 GIOA[6]/N2HET2[4]/EPWM1B 16 GIOA[7]/N2HET2[6]/EPWM2A 22 GIOB[0] 126 GIOB[1] 133 GIOB[2] 142 MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS 55 (1) Pull Up 1 Pull Down GIOB[3] (1) Description General-purpose I/O. All GPIO terminals are capable of generating interrupts to the CPU on rising / falling / both edges. GIOB[2] cannot output a level on to pin 55. Only the input functionality is supported so that the application can generate an interrupt whenever the N2HET2_PIN_nDIS is asserted (driven low). Also, a pull up is enabled on the input. This is not programmable using the GIO module control registers. 4.3.1.7 Controller Area Network Controllers (DCAN) Table 4-7. PGE Controller Area Network Controllers (DCAN) Terminal Signal Name 144 PGE Signal Type Reset Pull State Pull Type I/O Pull Up Programmable, 20 µA Description CAN1RX 90 CAN1TX 89 CAN2RX 129 CAN2 receive, or GPIO CAN2TX 128 CAN2 transmit, or GPIO CAN3RX 12 CAN3 receive, or GPIO CAN3TX 13 CAN3 transmit, or GPIO 16 Terminal Configuration and Functions CAN1 receive, or GPIO CAN1 transmit, or GPIO Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 4.3.1.8 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Local Interconnect Network Interface Module (LIN) Table 4-8. PGE Local Interconnect Network Interface Module (LIN) Terminal Signal Name 144 PGE LINRX 131 LINTX 132 4.3.1.9 Signal Type Reset Pull State Pull Type I/O Pull Up Programmable, 20 µA Description LIN receive, or GPIO LIN transmit, or GPIO Standard Serial Communication Interface (SCI) Table 4-9. PGE Standard Serial Communication Interface (SCI) Terminal Signal Name 144 PGE N2HET1[6]/SCIRX/EPWM5A 38 N2HET1[13]/SCITX/EPWM5B 39 Signal Type Reset Pull State Pull Type I/O Pull Down Programmable, 20 µA Description SCI receive, or GPIO SCI transmit, or GPIO 4.3.1.10 Inter-Integrated Circuit Interface Module (I2C) Table 4-10. PGE Inter-Integrated Circuit Interface Module (I2C) Terminal Signal Name 144 PGE MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 4 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 3 Signal Type Reset Pull State Pull Type I/O Pull Up Programmable, 20 µA Description I2C serial data, or GPIO I2C serial clock, or GPIO 4.3.1.11 Standard Serial Peripheral Interface (SPI) Table 4-11. PGE Standard Serial Peripheral Interface (SPI) Terminal Signal Name 144 PGE Signal Type Reset Pull State Pull Type I/O Pull Down Programmable, 20 µA Description N2HET1[0]/SPI4CLK/EPWM2B 25 N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B 24 SPI4 clock, or GPIO N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A 23 SPI4 enable, or GPIO N2HET1[2]/SPI4SIMO[0]/EPWM3A 30 SPI4 slave-input masteroutput, or GPIO N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B 31 SPI4 slave-output masterinput, or GPIO SPI4 chip select, or GPIO Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 17 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI) Table 4-12. PGE Multibuffered Serial Peripheral Interface Modules (MibSPI) Terminal Signal Name 144 PGE Signal Type Reset Pull State Pull Type Description I/O Pull Up Programmable, 20 µA MibSPI1 clock, or GPIO Pull Down Programmable, 20 µA MibSPI1 chip select, or GPIO Pull Up Programmable, 20 µA MibSPI1 enable, or GPIO MIBSPI1CLK 95 MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 105 MIBSPI1NCS[1]/N2HET1[17]/EQEP1S 130 MIBSPI1NCS[2]/N2HET1[19] 40 N2HET1[15]/MIBSPI1NCS[4]/ECAP1 41 N2HET1[24]/MIBSPI1NCS[5] 91 MIBSPI1NENA/N2HET1[23]/ECAP4 96 MIBSPI1SIMO[0] 93 N2HET1[8]/MIBSPI1SIMO[1] 106 Pull Down Programmable, 20 µA MibSPI1 slave-in masterout, or GPIO MIBSPI1SOMI[0] 94 Pull Up MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 105 Programmable, 20 µA MibSPI1 slave-out masterin, or GPIO MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A 53 Pull Up 55 Programmable, 20 µA MibSPI3 clock, or GPIO MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 4 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 3 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO 6 Pull Down Programmable, 20 µA MibSPI3 chip select, or GPIO MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 Pull Up Programmable, 20 µA MibSPI3 chip select, or GPIO MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 MibSPI3 enable, or GPIO MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 52 MibSPI3 slave-in masterout, or GPIO MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 51 MibSPI3 slave-out masterin, or GPIO MIBSPI5CLK 100 MIBSPI5NCS[0]/EPWM4A 32 MIBSPI5NENA/MIBSPI5SOMI[1]/ ECAP5 97 MibSPI5 enable, or GPIO MIBSPI5SIMO[0]/MIBSPI5SOMI[2] 99 MibSPI5 slave-in masterout, or GPIO MIBSPI5SOMI[0] 98 MibSPI5 slave-out masterin, or GPIO MIBSPI5NENA/MIBSPI5SOMI[1]/ ECAP5 97 MibSPI5 slave-out masterin, or GPIO MIBSPI5SIMO[0]/MIBSPI5SOMI[2] 99 MibSPI5 slave-out masterin, or GPIO 18 I/O I/O Pull Up Terminal Configuration and Functions Programmable, 20 µA MibSPI1 chip select, or GPIO MibSPI1 slave-in masterout, or GPIO MibSPI3 chip select, or GPIO MibSPI5 clock, or GPIO MibSPI5 chip select, or GPIO Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.3.1.13 System Module Interface Table 4-13. PGE System Module Interface Terminal Signal Name 144 PGE Signal Type Reset Pull State Pull Type Description nPORRST 46 Input Pull Down Fixed 100 µA Pull Down Power-on reset, cold reset External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter. See Section 6.8. nRST 116 I/O Pull Up Fixed 100 µA Pull Up System reset, warm reset, bidirectional. The internal circuitry indicates any reset condition by driving nRST low. The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pull-up resistor is connected to this terminal. This terminal has a glitch filter. See Section 6.8. nERROR 117 I/O Pull Down Fixed 20 µA Pull Down ESM Error Signal Indicates error of high severity. See Section 6.18. 4.3.1.14 Clock Inputs and Outputs Table 4-14. PGE Clock Inputs and Outputs Terminal Signal Name 144 PGE Signal Type Reset Pull State Pull Type N/A None OSCIN 18 Input KELVIN_GND 19 Input OSCOUT 20 Output ECLK 119 I/O Pull Down Programmable, 20 µA GIOA[5]/EXTCLKIN/EPWM1A /N2HET1_PIN_nDIS 14 Input Pull Down Fixed 20 µA Pull Down Description From external crystal/resonator, or external clock input Kelvin ground for oscillator To external crystal/resonator External prescaled clock output, or GPIO. External clock input #1 Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 19 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.1.15 Test and Debug Modules Interface Table 4-15. PGE Test and Debug Modules Interface Terminal Signal Name 144 PGE Signal Type Reset Pull State Pull Type Description Input Pull Down Fixed 100 µA Pull Down Test enable. This terminal must be connected to ground directly or via a pull-down resistor. TEST 34 nTRST 109 Input RTCK 113 Output N/A None TCK 112 Input Pull Down Fixed 100 µA Pull Down JTAG test clock TDI 110 Input Pull Up Fixed 100 µA Pull Up JTAG test data in TDO 111 Output 100 µA Pull Down None TMS 108 Input Pull Up Fixed 100 µA Pull Up JTAG test hardware reset JTAG return test clock JTAG test data out JTAG test select 4.3.1.16 Flash Supply and Test Pads Table 4-16. PGE Flash Supply and Test Pads Terminal Signal Name 144 PGE Signal Type Reset Pull State Pull Type Description VCCP 134 3.3V Power N/A None Flash pump supply FLTP1 7 - N/A- None FLTP2 8 Flash test pads. These terminals are reserved for TI use only. For proper operation these terminals must connect only to a test pad or not be connected at all [no connect (NC)]. 20 Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.3.1.17 Supply for Core Logic: 1.2V nominal Table 4-17. PGE Supply for Core Logic: 1.2V nominal Terminal Signal Name 144 PGE VCC 17 VCC 29 VCC 45 VCC 48 VCC 49 VCC 57 VCC 87 VCC 101 VCC 114 VCC 123 VCC 137 VCC 143 Signal Type Reset Pull State Pull Type 1.2V Power N/A None Description Core supply 4.3.1.18 Supply for I/O Cells: 3.3V nominal Table 4-18. PGE Supply for I/O Cells: 3.3V nominal Terminal Signal Name 144 PGE VCCIO 10 VCCIO 26 VCCIO 42 VCCIO 104 VCCIO 120 VCCIO 136 Signal Type Reset Pull State Pull Type 3.3V Power N/A None Description Operating supply for I/Os Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 21 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.1.19 Ground Reference for All Supplies Except VCCAD Table 4-19. PGE Ground Reference for All Supplies Except VCCAD Terminal Signal Name 144 PGE VSS 11 VSS 21 VSS 27 VSS 28 VSS 43 VSS 44 VSS 47 VSS 50 VSS 56 VSS 88 VSS 102 VSS 103 VSS 115 VSS 121 VSS 122 VSS 135 VSS 138 VSS 144 22 Signal Type Reset Pull State Pull Type Ground N/A None Terminal Configuration and Functions Description Ground reference Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 4.3.2 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 ZWT Package 4.3.2.1 Multibuffered Analog-to-Digital Converters (MibADC) Table 4-20. ZWT Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2) Terminal Signal Type Reset Pull State Pull Type V15 Power N/A None ADREFLO (1) V16 Power ADC low reference supply VCCAD (1) W15 Power Operating supply for ADC VSSAD V19 Ground N/A None VSSAD W16 VSSAD W18 VSSAD W19 AD1EVT N19 I/O Pull Down Programmable, 20 µA ADC1 event trigger input, or GPIO MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS V10 I/O Pull Up Programmable, 20 µA ADC2 event trigger input, or GPIO AD1IN[0] W14 Input N/A None ADC1 analog input AD1IN[1] V17 AD1IN[2] V18 Input N/A None ADC1/ADC2 shared analog inputs Output Pull Up None AWM1 external analog mux enable Signal Name ADREFHI (1) 337 ZWT AD1IN[3] T17 AD1IN[4] U18 AD1IN[5] R17 AD1IN[6] T19 AD1IN[7] V14 AD1IN[8] / AD2IN[8] P18 AD1IN[9] / AD2IN[9] W17 AD1IN[10] / AD2IN[10] U17 AD1IN[11] / AD2IN[11] U19 AD1IN[12] / AD2IN[12] T16 AD1IN[13] / AD2IN[13] T18 AD1IN[14] / AD2IN[14] R18 AD1IN[15] / AD2IN[15] P19 AD1IN[16] / AD2IN[0] V13 AD1IN[17] / AD2IN[1] U13 AD1IN[18] / AD2IN[2] U14 AD1IN[19] / AD2IN[3] U16 AD1IN[20] / AD2IN[4] U15 AD1IN[21] / AD2IN[5] T15 AD1IN[22] / AD2IN[6] R19 AD1IN[23] / AD2IN[7] R16 Description ADC high reference supply ADC supply power MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 V8 MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 W8 AWM1 external analog mux select line0 MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A V9 AWM1 external analog mux select line0 (1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 23 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.3.2.2 www.ti.com Enhanced High-End Timer Modules (N2HET) Table 4-21. ZWT Enhanced High-End Timer Modules (N2HET) Terminal Signal Name 337 ZWT N2HET1[0]/SPI4CLK/EPWM2B K18 N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A V2 N2HET1[2]/SPI4SIMO[0]/EPWM3A W5 N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B U1 N2HET1[4]/EPWM4B B12 N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B V6 N2HET1[6]/SCIRX/EPWM5A W3 N2HET1[7]/N2HET2[14]/EPWM7B T1 N2HET1[8]/MIBSPI1SIMO[1] E18 N2HET1[9]/N2HET2[16]/EPWM7A E3 N2HET1[12] B4 N2HET1[13]/SCITX/EPWM5B N2 N2HET1[14] A11 N2HET1[15]/MIBSPI1NCS[4]/ECAP1 N1 N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO A4 N2HET1[17] A13 MIBSPI1NCS[1]/N2HET1[17]/ EQEP1S F3 I/O Pull Down Programmable, 20 µA B13 MIBSPI1NCS[2]/N2HET1[19] G3 N2HET1[20]/EPWM6B P2 N2HET1[21] H4 MIBSPI1NCS[3]/N2HET1[21] J3 N2HET1[22] B3 N2HET1 time capture or compare, or GIO. input output Each terminal has a suppression filter with a programmable duration. J4 G19 Pull Up N2HET1[24]/MIBSPI1NCS[5] P1 Pull Down N2HET1[25] M3 MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5 N2HET1[26] A14 N2HET1[27] A9 MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 B2 Pull Up N2HET1[28] K19 Pull Down N2HET1[29] A3 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 C3 24 Description J1 N2HET1[19] MIBSPI1NENA/N2HET1[23]/ECAP4 Pull Type D19 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO N2HET1[23] Reset Pull State V7 N2HET1[10]/nTZ3 N2HET1[18]/EPWM6A Signal Type Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 4-21. ZWT Enhanced High-End Timer Modules (N2HET) (continued) Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type I/O Pull Down Programmable, 20 µA N2HET1[30]/EQEP2S B11 N2HET1[31] J17 MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS B5 input Pull Down Programmable, 20 µA (1) GIOA[2]/N2HET2[0] /EQEP2I C1 I/O Pull Down EMIF_ADDR[0]/N2HET2[1] D4 Programmable, 20 µA GIOA[3]/N2HET2[2] E1 EMIF_ADDR[1]/N2HET2[3] D5 GIOA[6]/N2HET2[4]/EPWM1B H3 EMIF_BA[1]/N2HET2[5] D16 GIOA[7]/N2HET2[6]/EPWM2A M1 EMIF_nCS[0]/N2HET2[7] N17 N2HET1[1]/SPI4NENA/ N2HET2[8]/EQEP2A V2 EMIF_nCS[3]/N2HET2[9] K17 N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B U1 EMIF_ADDR[6]/N2HET2[11] C4 N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B V6 EMIF_ADDR[7]/N2HET2[13] C5 N2HET1[7]/N2HET2[14]/EPWM7B T1 EMIF_ADDR[8]/N2HET2[15] C6 N2HET1[9]/N2HET2[16]/EPWM7A V7 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO E3 MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS V10 (1) Description Pull Up Disable selected PWM outputs N2HET2 time capture or compare, or GIO. input output Each terminal has a suppression filter with a programmable duration. I/O Pull Up Programmable, 20 µA (1) Disable selected PWM outputs The N2HETx_PIN_nDIS function is always available on this terminal. There is no mux control to select this function. The pull direction is controlled by the function which is selected by the output mux control for this terminal. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 25 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.3.2.3 www.ti.com Enhanced Capture Modules (eCAP) Table 4-22. ZWT Enhanced Capture Modules (eCAP) (1) Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type Fixed 20 µA Pull Up Description N2HET1[15]/MIBSPI1NCS[4]/ECAP1 N1 I/O Pull Down MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 V8 I/O Pull Up MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 W8 I/O Enhanced Capture Module 3 I/O MIBSPI1NENA/N2HET1[23]/ECAP4 G19 I/O Enhanced Capture Module 4 I/O MIBSPI5NENA/MIBSPI5SOMI[1]/ ECAP5 H18 I/O Enhanced Capture Module 5 I/O MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ ECAP6 R2 I/O Enhanced Capture Module 6 I/O (1) Enhanced Capture Module 1 I/O Enhanced Capture Module 2 I/O These signals, when used as inputs, are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter. 4.3.2.4 Enhanced Quadrature Encoder Pulse Modules (eQEP) Table 4-23. ZWT Enhanced Quadrature Encoder Pulse Modules (eQEP) (1) Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type Pull Up Fixed 20 µA Pull Up MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A V9 Input MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 Input MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS V10 I/O Description Enhanced QEP1 Input A Enhanced QEP1 Input B Enhanced QEP1 Index MIBSPI1NCS[1]/N2HET1[17]/ EQEP1S F3 I/O N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A V2 Input Pull Down Enhanced QEP2 Input A N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B U1 Input Pull Down Enhanced QEP2 Input B GIOA[2]/N2HET2[0]/ EQEP2I C1 I/O Pull Down Enhanced QEP2 Index N2HET1[30]/EQEP2S B11 I/O Pull Down Enhanced QEP2 Strobe (1) 26 Enhanced QEP1 Strobe These signals are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 4.3.2.5 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Enhanced Pulse-Width Modulator Modules (ePWM) Table 4-24. ZWT Enhanced Pulse-Width Modulator Modules (ePWM) TERMINAL 337 ZWT SIGNAL NAME SIGNA Reset Pull L TYPE State B5 GIOA[6]/N2HET2[4]/EPWM1B H3 Enhanced PWM1 Output B N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO E3 External ePWM Sync Pulse Output N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO A4 Input Fixed 20 µA Pull Up External ePWM Sync Pulse Input GIOA[7]/N2HET2[6]/EPWM2A M1 Output None Enhanced PWM2 Output A N2HET1[0]/SPI4CLK/EPWM2B K18 Enhanced PWM2 Output B N2HET1[2]/SPI4SIMO[0]/EPWM3A W5 Enhanced PWM3 Output A N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B V6 Enhanced PWM3 Output B MIBSPI5NCS[0]/EPWM4A E19 Pull Up Enhanced PWM4 Output A N2HET1[4]/EPWM4B B12 Pull Down Enhanced PWM4 Output B N2HET1[6]/SCIRX/EPWM5A W3 Enhanced PWM5 Output A N2HET1[13]/SCITX/EPWM5B N2 Enhanced PWM5 Output B N2HET1[18]/EPWM6A J1 Enhanced PWM6 Output A N2HET1[20]/EPWM6B P2 Enhanced PWM6 Output B N2HET1[9]/N2HET2[16]/EPWM7A V7 Enhanced PWM7 Output A N2HET1[7]/N2HET2[14]/EPWM7B T1 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 C3 MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 B2 D19 Pull Down None DESCRIPTION GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS N2HET1[10]/nTZ3 Output PULL TYPE Enhanced PWM1 Output A Enhanced PWM7 Output B Input Pull Up Pull Down Fixed 20 µA Pull Up Trip Zone Inputs 1, 2 and 3. These signals are either connected asynchronously to the ePWMx trip zone inputs, or double-synchronized with VCLK4, or doublesynchronized and then filtered with a 6-cycle VCLK4-based counter before connecting to the ePWMx trip zone inputs. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 27 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.3.2.6 www.ti.com General-Purpose Input / Output (GPIO) Table 4-25. ZWT General-Purpose Input / Output (GPIO) Terminal Signal Name 337 ZWT GIOA[0] A5 GIOA[1] C2 GIOA[2]/N2HET2[0] /EQEP2I C1 GIOA[3]/N2HET2[2] E1 GIOA[4] A6 GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS B5 GIOA[6]/N2HET2[4]/EPWM1B H3 GIOA[7]/N2HET2[6]/EPWM2A M1 GIOB[0] M2 GIOB[1] K2 GIOB[2] MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS Pull Type I/O Pull Down Programmable, 20 µA Description General-purpose I/O. All GPIO terminals are capable of generating interrupts to the CPU on rising / falling / both edges. F2 W10 GIOB[4] G1 GIOB[5] G2 GIOB[6] J2 GIOB[7] F1 28 Reset Pull State V10 (1) GIOB[3] (1) Signal Type GIOB[2] cannot output a level on to terminal V10. Only the input functionality is supported so that the application can generate an interrupt whenever the N2HET2_PIN_nDIS is asserted (driven low). Also, a pull up is enabled on the input. This is not programmable using the GIO module control registers. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 4.3.2.7 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Controller Area Network Controllers (DCAN) Table 4-26. ZWT Controller Area Network Controllers (DCAN) Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type I/O Pull Up Programmable, 20 µA Description CAN1RX B10 CAN1TX A10 CAN2RX H1 CAN2 receive, or GPIO CAN2TX H2 CAN2 transmit, or GPIO CAN3RX M19 CAN3 receive, or GPIO CAN3TX M18 CAN3 transmit, or GPIO 4.3.2.8 CAN1 receive, or GPIO CAN1 transmit, or GPIO Local Interconnect Network Interface Module (LIN) Table 4-27. ZWT Local Interconnect Network Interface Module (LIN) Terminal Signal Name 337 ZWT LINRX A7 LINTX B7 4.3.2.9 Signal Type Reset Pull State Pull Type I/O Pull Up Programmable, 20 µA Description LIN receive, or GPIO LIN transmit, or GPIO Standard Serial Communication Interface (SCI) Table 4-28. ZWT Standard Serial Communication Interface (SCI) Terminal Signal Name 337 ZWT N2HET1[6]/SCIRX/EPWM5A W3 N2HET1[13]/SCITX/EPWM5B N2 Signal Type Reset Pull State Pull Type I/O Pull Down Programmable, 20 µA Description SCI receive, or GPIO SCI transmit, or GPIO Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 29 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.2.10 Inter-Integrated Circuit Interface Module (I2C) Table 4-29. ZWT Inter-Integrated Circuit Interface Module (I2C) Terminal Signal Name 337 ZWT MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 B2 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 C3 Signal Type Reset Pull State Pull Type I/O Pull Up Programmable, 20 µA Description I2C serial data, or GPIO I2C serial clock, or GPIO 4.3.2.11 Standard Serial Peripheral Interface (SPI) Table 4-30. ZWT Standard Serial Peripheral Interface (SPI) Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type I/O Pull Up Programmable, 20 µA Description SPI2CLK E2 SPI2NCS[0] N3 SPI2NENA/SPI2NCS[1] D3 SPI2 chip select, or GPIO SPI2NENA/SPI2NCS[1] D3 SPI2 enable, or GPIO SPI2SIMO[0] D1 SPI2 slave-input masteroutput, or GPIO SPI2SOMI[0] D2 SPI2 slave-output masterinput, or GPIO N2HET1[0]/SPI4CLK/EPWM2B K18 N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B U1 N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A V2 SPI4 enable, or GPIO N2HET1[2]/SPI4SIMO[0]/EPWM3A W5 SPI4 slave-input masteroutput, or GPIO N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B V6 SPI4 slave-output masterinput, or GPIO 30 I/O Pull Down Terminal Configuration and Functions Programmable, 20 µA SPI2 clock, or GPIO SPI2 chip select, or GPIO SPI4 clock, or GPIO SPI4 chip select, or GPIO Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.3.2.12 Multibuffered Serial Peripheral Interface Modules (MibSPI) Table 4-31. ZWT Multibuffered Serial Peripheral Interface Modules (MibSPI) Terminal Signal Name 337 ZWT MIBSPI1CLK F18 MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 R2 MIBSPI1NCS[1]/N2HET1[17]/EQEP1S F3 MIBSPI1NCS[2]/N2HET1[19] G3 MIBSPI1NCS[3]/N2HET1[21] J3 N2HET1[15]/MIBSPI1NCS[4]/ECAP1 N1 N2HET1[24]/MIBSPI1NCS[5] Signal Type Reset Pull State Pull Type I/O Pull Up Programmable, 20 µA MibSPI1 clock, or GPIO Pull Down Programmable, 20 µA MibSPI1 chip select, or GPIO Pull Up Programmable, 20 µA MibSPI1 enable, or GPIO P1 Description MibSPI1 chip select, or GPIO MIBSPI1NENA/N2HET1[23]/ECAP4 G19 MIBSPI1SIMO[0] F19 N2HET1[8]/MIBSPI1SIMO[1] E18 Pull Down Programmable, 20 µA MibSPI1 slave-in masterout, or GPIO MIBSPI1SOMI[0] G18 Pull Up Programmable, 20 µA MibSPI1 slave-out masterin, or GPIO Pull Up Programmable, 20 µA MibSPI3 clock, or GPIO MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6 R2 MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A V9 MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ EQEP1I/N2HET2_PIN_nDIS V10 MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5 I/O MibSPI1 slave-in masterout, or GPIO MibSPI3 chip select, or GPIO MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 B2 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 C3 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO E3 Pull Down Programmable, 20 µA MibSPI3 chip select, or GPIO MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 Pull Up Programmable, 20 µA MibSPI3 chip select, or GPIO MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 MibSPI3 enable, or GPIO MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 W8 MibSPI3 slave-in masterout, or GPIO MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 V8 MibSPI3 slave-out masterin, or GPIO MIBSPI5CLK H19 MIBSPI5NCS[0]/EPWM4A E19 MIBSPI5NCS[1] B6 MIBSPI5NCS[2] W6 I/O Pull Up Programmable, 20 µA MibSPI5 clock, or GPIO MibSPI5 chip select, or GPIO MIBSPI5NCS[3] T12 MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5 H18 MibSPI5 enable, or GPIO MIBSPI5SIMO[0]/MIBSPI5SOMI[2] J19 MIBSPI5SIMO[1] E16 MibSPI5 slave-in masterout, or GPIO MIBSPI5SIMO[2] H17 MIBSPI5SIMO[3] G17 MIBSPI5SOMI[0] J18 MIBSPI5SOMI[1] E17 MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5 H18 MIBSPI5SOMI[2] H16 MIBSPI5SIMO[0]/MIBSPI5SOMI[2] J19 MIBSPI5SOMI[3] G16 MibSPI5 slave-out masterin, or GPIO Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 31 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.2.13 External Memory Interface (EMIF) Table 4-32. External Memory Interface (EMIF) Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type Description Pull Up None EMIF Clock Enable None EMIF clock. This is an output signal in functional mode. It is gated off by default, so that the signal is pulled up. PINMUX29[8] must be cleared to enable this output. EMIF Read Enable EMIF_CKE L3 Output EMIF_CLK K3 I/O EMIF_nOE E12 Output Pull Up None EMIF_nWAIT P3 I/O Pull Up Fixed 20 µA Pull Up EMIF_nWE D17 Output Pull Up None EMIF_nCAS R4 Output EMIF column address strobe EMIF_nRAS R3 Output EMIF row address strobe EMIF_nCS[0]/N2HET2[7] (1) N17 Output EMIF chip select, synchronous EMIF_nCS[2] L17 Output EMIF_nCS[3]/N2HET2[9] (1) K17 Output EMIF_nCS[4] M17 Output EMIF chip selects, asynchronous This applies to chip selects 2, 3 and 4 EMIF_nDQM[0] E10 Output EMIF_nDQM[1] E11 Output EMIF_BA[0] E13 Output EMIF bank address or address line EMIF_BA[1]/N2HET2[5] (1) D16 Output EMIF bank address or address line EMIF_ADDR[0]/N2HET2[1] (1) D4 Output EMIF address (1) EMIF_ADDR[1]/N2HET2[3] D5 Output EMIF_ADDR[2] E6 Output EMIF_ADDR[3] E7 Output EMIF_ADDR[4] E8 Output EMIF_ADDR[5] E9 Output EMIF_ADDR[6]/N2HET2[11] (1) C4 Output EMIF_ADDR[7]/N2HET2[13] (1) C5 Output (1) EMIF_ADDR[8]/N2HET2[15] C6 Output EMIF_ADDR[9] C7 Output EMIF_ADDR[10] C8 Output EMIF_ADDR[11] C9 Output EMIF_ADDR[12] C10 Output (1) 32 EMIF Extended Wait Signal EMIF Write Enable EMIF Data Mask or Write Strobe. Data mask for SDRAM devices, write strobe for connected asynchronous devices. These signals are tri-stated and pulled up by default after power-up. Any application that requires the EMIF must set the bit 31 of the system module general-purpose register GPREG1. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 4-32. External Memory Interface (EMIF) (continued) Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type Pull Up Fixed 20 µA Pull Up EMIF_DATA[0] K15 I/O EMIF_DATA[1] L15 I/O EMIF_DATA[2] M15 I/O EMIF_DATA[3] N15 I/O EMIF_DATA[4] E5 I/O EMIF_DATA[5] F5 I/O EMIF_DATA[6] G5 I/O EMIF_DATA[7] K5 I/O EMIF_DATA[8] L5 I/O EMIF_DATA[9] M5 I/O EMIF_DATA[10] N5 I/O EMIF_DATA[11] P5 I/O EMIF_DATA[12] R5 I/O EMIF_DATA[13] R6 I/O EMIF_DATA[14] R7 I/O EMIF_DATA[15] R8 I/O Description EMIF Data Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 33 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.2.14 System Module Interface Table 4-33. ZWT System Module Interface Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type Description nPORRST W7 Input Pull Down Fixed 100 µA Pull Down Power-on reset, cold reset External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter. See Section 6.8. nRST B17 I/O Pull Up Fixed 100 µA Pull Up System reset, warm reset, bidirectional. The internal circuitry indicates any reset condition by driving nRST low. The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pull-up resistor is connected to this terminal. This terminal has a glitch filter. See Section 6.8. nERROR B14 I/O Pull Down Fixed 20 µA Pull Down ESM Error Signal Indicates error of high severity. See Section 6.18. 4.3.2.15 Clock Inputs and Outputs Table 4-34. ZWT Clock Inputs and Outputs Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type N/A None OSCIN K1 Input KELVIN_GND L2 Input OSCOUT L1 Output A12 I/O Pull Down Programmable, 20 µA GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS B5 Input Pull Down 20 µA EXTCLKIN2 R9 Input VCCPLL P11 1.2V Power N/A None ECLK 34 Description From external crystal/resonator, or external clock input Kelvin ground for oscillator To external crystal/resonator External prescaled clock output, or GIO. External clock input #1 External clock input #2 Terminal Configuration and Functions Dedicated core supply for PLL's Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.3.2.16 Test and Debug Modules Interface Table 4-35. ZWT Test and Debug Modules Interface Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type Description Input Pull Down Fixed 100 µA Pull Down Test enable. This terminal must be connected to ground directly or via a pull-down resistor. TEST U2 nTRST D18 Input RTCK A16 Output N/A None TCK B18 Input Pull Down Fixed 100 µA Pull Down JTAG test clock TDI A17 Input Pull Up Fixed 100 µA Pull Up JTAG test data in TDO C18 Output 100 µA Pull Down None TMS C19 Input Pull Up Fixed 100 µA Pull Up JTAG test hardware reset JTAG return test clock JTAG test data out JTAG test select 4.3.2.17 Flash Supply and Test Pads Table 4-36. ZWT Flash Supply and Test Pads Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type Description VCCP F8 3.3V Power N/A None Flash pump supply FLTP1 J5 - N/A None FLTP2 H5 Flash test pads. These terminals are reserved for TI use only. For proper operation these terminals must connect only to a test pad or not be connected at all [no connect (NC)]. Signal Type Reset Pull State Pull Type Description Reserved. These balls are connected to internal logic but are not outputs nor do they have internal pulls. They are subject to ±1 µA leakage current. 4.3.2.18 Reserved Table 4-37. Reserved Terminal Signal Name 337 ZWT Reserved A15 - N/A None Reserved B15 - N/A None Reserved B16 - N/A None Reserved A8 - N/A- None Reserved B8 - N/A None Reserved B9 - N/A None Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 35 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.2.19 No Connects Table 4-38. No Connects Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type Description No Connects. These balls are not connected to any internal logic and can be connected to the PCB ground without affecting the functionality of the device. NC C11 - N/A None NC C12 - N/A None NC C13 - N/A None NC C14 - N/A None NC C15 - N/A None NC C16 - N/A None NC C17 - N/A None NC D6 - N/A None NC D7 - N/A None NC D8 - N/A None NC D9 - N/A None NC D10 - N/A None NC D11 - N/A None NC D12 - N/A None NC D13 - N/A None NC D14 - N/A None NC D15 - N/A None NC E4 - N/A None NC E14 - N/A None NC E15 - N/A None NC F4 - N/A None NC F15 - N/A None NC F16 - N/A None NC F17 - N/A None NC G4 - N/A None NC G15 - N/A None NC H15 - N/A None NC J15 - N/A None NC J16 - N/A None NC K4 - N/A None NC K16 - N/A None NC L4 - N/A None NC L16 - N/A None NC L18 - N/A None NC L19 - N/A None NC M4 - N/A None NC M16 - N/A None NC N4 - N/A None NC N16 - N/A None NC N18 - N/A None NC P4 - N/A None 36 Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 4-38. No Connects (continued) Terminal Signal Name 337 ZWT Signal Type Reset Pull State Pull Type Description No Connects. These balls are not connected to any internal logic and can be connected to the PCB ground without affecting the functionality of the device. NC P15 - N/A None NC P16 - N/A None NC P17 - N/A None NC R1 - N/A None NC R10 - N/A None NC R11 - N/A None NC R12 - N/A None NC R13 - N/A None NC R14 - N/A None NC R15 - N/A None NC T2 - N/A None NC T3 - N/A None NC T4 - N/A None NC T5 - N/A None NC T6 - N/A None NC T7 - N/A None NC T8 - N/A None NC T9 - N/A None NC T10 - N/A None NC T11 - N/A None NC T13 - N/A None NC T14 - N/A None NC U3 - N/A- None NC U4 - N/A None NC U5 - N/A None NC U6 - N/A None NC U7 - N/A None NC U8 - N/A None NC U9 - N/A None NC U10 - N/A None NC U11 - N/A None NC U12 - N/A None NC V3 - N/A None NC V4 - N/A None NC V11 - N/A None NC V12 - N/A None NC W4 - N/A None NC W11 - N/A None NC W12 - N/A None NC W13 - N/A None Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 37 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.2.20 Supply for Core Logic: 1.2V nominal Table 4-39. ZWT Supply for Core Logic: 1.2V nominal Terminal Signal Name 337 ZWT VCC F9 VCC F10 VCC H10 VCC J14 VCC K6 VCC K8 VCC K12 VCC K14 VCC L6 VCC M10 VCC P10 38 Signal Type Reset Pull State Pull Type 1.2V Power N/A None Terminal Configuration and Functions Description Core supply Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 4.3.2.21 Supply for I/O Cells: 3.3V nominal Table 4-40. ZWT Supply for I/O Cells: 3.3V nominal Terminal Signal Name 337 ZWT VCCIO F6 VCCIO F7 VCCIO F11 VCCIO F12 VCCIO F13 VCCIO F14 VCCIO G6 VCCIO G14 VCCIO H6 VCCIO H14 VCCIO J6 VCCIO L14 VCCIO M6 VCCIO M14 VCCIO N6 VCCIO N14 VCCIO P6 VCCIO P7 VCCIO P8 VCCIO P9 VCCIO P12 VCCIO P13 VCCIO P14 Signal Type Reset Pull State Pull Type 3.3V Power N/A None Description Operating supply for I/Os Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 39 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 4.3.2.22 Ground Reference for All Supplies Except VCCAD Table 4-41. ZWT Ground Reference for All Supplies Except VCCAD Terminal Signal Name 337 ZWT VSS A1 VSS A2 VSS A18 VSS A19 VSS B1 VSS B19 VSS H8 VSS H9 VSS H11 VSS H12 VSS J8 VSS J9 VSS J10 VSS J11 VSS J12 VSS K9 VSS K10 VSS K11 VSS L8 VSS L9 VSS L10 VSS L11 VSS L12 VSS M8 VSS M9 VSS M11 VSS M12 VSS V1 VSS W1 VSS W2 40 Signal Type Reset Pull State Pull Type Ground N/A None Terminal Configuration and Functions Description Ground reference Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 5 Specifications 5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range VCC (2) Supply voltage range: VCCIO, VCCP Input voltage range: Input clamp current: (2) (1) MIN MAX UNIT -0.3 1.43 V -0.3 4.6 V VCCAD -0.3 6.25 V All input pins, with exception of ADC pins -0.3 4.6 V ADC input pins -0.3 6.25 V IIK (VI < 0 or VI > VCCIO) All pins, except AD1IN[23:0] or AD2IN[15:0] -20 +20 mA IIK (VI < 0 or VI > VCCAD) AD1IN[23:0] or AD2IN[15:0] -10 +10 mA Total -40 +40 mA Operating free-air temperature range, TA: -40 125 °C Operating junction temperature range, TJ: -40 150 °C Storage temperature range, Tstg -65 150 °C (1) (2) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated grounds. 5.2 ESD Ratings VALUE UNIT ±2 kV All pins ±500 V Corner pins on 144-pin PGE (1, 36, 37, 72, 73, 108, 109, 144) ±750 V Corner balls on 337-ball ZWT (A1, A19, W1, W19) ±750 V Human body model (HBM), per AEC Q100-002 (1) VESD (1) 5.3 (1) (2) Electrostatic discharge (ESD) performance: Charged device model (CDM), per AEC Q100-011 AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS‑001 specification. Power-On Hours (POH) (1) (2) NOMINAL CORE VOLTAGE (VCC) JUNCTION TEMPERATURE (Tj) LIFETIME POH 1.2 105ºC 100K This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products. To avoid significant degradation, the device power-on hours (POH) must be limited to those specified in this table. To convert to equivalent POH for a specific temperature profile, see the Calculating Equivalent Power-on-Hours for Hercules Safety MCUs Application Report (SPNA207). Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 41 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Device Recommended Operating Conditions (1) 5.4 MIN NOM MAX UNIT VCC Digital logic supply voltage (Core) 1.14 1.2 1.32 V VCCPLL PLL Supply Voltage 1.14 1.2 1.32 V VCCIO Digital logic supply voltage (I/O) 3 3.3 3.6 V VCCAD MibADC supply voltage 3 5.25 V VCCP Flash pump supply voltage 3 3.6 V VSS Digital logic supply ground VSSAD MibADC supply ground VADREFHI VADREFLO VSLEW Maximum positive slew rate for VCCIO, VCCAD and VCCP supplies TA Operating free-air temperature TJ (1) (2) 42 3.3 0 V -0.1 0.1 V A-to-D high-voltage reference source VSSAD VCCAD V A-to-D low-voltage reference source VSSAD VCCAD Operating junction temperature (2) 1 V V/µs -40 125 °C -40 150 °C All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD Reliability data is based upon a temperature profile that is equivalent to 100,000 power-on hours at 105°C junction temperature. Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 5.5 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Switching Characteristics Over Recommended Operating Conditions for Clock Domains Table 5-1. Clock Domain Timing Specifications PARAMETER DESCRIPTION CONDITIONS PGE fHCLK HCLK - System clock frequency ZWT MAX UNIT Pipeline mode enabled 160 MHz Pipeline mode disabled 50 MHz Pipeline mode enabled 180 MHz Pipeline mode disabled 50 MHz fGCLK GCLK - CPU clock frequency fHCLK MHz fVCLK VCLK - Primary peripheral clock frequency 100 MHz fVCLK2 VCLK2 - Secondary peripheral clock frequency 100 MHz fVCLK3 VCLK3 - Secondary peripheral clock frequency 100 MHz fVCLK4 VCLK4 - Secondary peripheral clock frequency 150 MHz fVCLKA1 VCLKA1 - Primary asynchronous peripheral clock frequency 100 MHz fVCLKA2 VCLKA2 - Secondary asynchronous peripheral clock frequency 100 MHz fVCLKA3 VCLKA3 - Primary asynchronous peripheral clock frequency 100 MHz fVCLKA4 VCLKA4 - Secondary asynchronous peripheral clock frequency 100 MHz fRTICLK RTICLK - clock frequency fVCLK MHz 5.6 Wait States Required RAM 0 Address Wait States fHCLK(max) 0MHz Data Wait States 0 0MHz fHCLK(max) Flash (Main Memory) Address Wait States 1 0 Data Wait States 0 1 0MHz Flash (Data Memory) Data Wait States fHCLK(max) 150MHz 0MHz 0 2 100MHz 50MHz 1 50MHz 0MHz 3 150MHz 3 2 100MHz fHCLK(max) 150MHz fHCLK(max) Figure 5-1. Wait States Scheme As shown in the figure above, the TCM RAM can support program and data fetches at full CPU speed without any address or data wait states required. The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in nonpipelined mode. The flash supports a maximum CPU clock speed of 160 MHz in pipelined mode for the PGE Package and 180 MHz for the ZWT package, with one address wait state and three data wait states. The flash wrapper defaults to non-pipelined mode with zero address wait state and one random-read data wait state. Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 43 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 5.7 www.ti.com Power Consumption Over Recommended Operating Conditions PARAMETER TEST CONDITIONS VCC digital supply current (operating mode) fVCLK = fHCLK/2; Flash in pipelined mode; VCCmax ICC VCC Digital supply current (LBIST/PBIST mode) fHCLK = 160MHz MIN TYP 170 (1) MAX UNIT 340 (2) mA fHCLK = 180MHz 190 (1) 360 (2) LBIST/PBIST clock frequency = 80MHz 215 (1) 460 (3) (4) mA (3) (4) mA LBIST/PBIST clock frequency = 90MHz 240 (1) 460 ICCPLL VCCPLL digital supply current (operating mode) VCCPLL = VCCPLLmax 10 mA ICCIO VCCIO Digital supply current (operating mode. No DC load, VCCmax 10 mA Single ADC operational, VCCADmax 15 Both ADCs operational, VCCADmax 30 Single ADC operational, ADREFHImax 3 Both ADCs operational, ADREFHImax 6 ICCAD VCCAD supply current (operating mode) IADREFHI ICCP (1) (2) (3) (4) 44 ADREFHI supply current (operating mode) VCCP supply current read from 1 bank and program another bank, VCCPmax mA mA 55 mA The typical value is the average current for the nominal process corner and junction temperature of 25C. The maximum ICC, value can be derated • linearly with voltage • by 1 ma/MHz for lower operating frequency when fHCLK= 2 * fVCLK • for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes. 160 - 0.073 e0.0181 TJK The maximum ICC, value can be derated • linearly with voltage • by 1.5 ma/MHz for lower operating frequency • for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes. 160 - 0.073 e0.0181 TJK LBIST and PBIST currents are for a short duration, typically less than 10ms. They are usually ignored for thermal calculations for the device and the voltage regulator Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 5.8 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Input/Output Electrical Characteristics Over Recommended Operating Conditions (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vhys Input hysteresis All inputs 180 mV VIL Low-level input voltage All inputs -0.3 0.8 V VIH High-level input voltage All inputs 2 VCCIO + 0.3 V IOL = IOLmax VOL Low-level output voltage IOL = 50 µA, standard output mode 0.2 IOL = 50 µA, low-EMI output mode (see Section 5.13) 0.2 VCCIO IOH = IOHmax VOH IIK II High-level output voltage Input clamp current (I/O pins) (2) Input current (I/O pins) 0.2 VCCIO V 0.8 VCCIO IOH = 50 µA, standard output mode VCCIO -0.3 IOH = 50 µA, low-EMI output mode (see Section 5.13) 0.8 VCCIO VI < VSSIO - 0.3 or VI > VCCIO + 0.3 -3.5 3.5 5 40 40 195 V IIH Pulldown 20µA VI = VCCIO IIH Pulldown 100µA VI = VCCIO IIL Pullup 20µA VI = VSS -40 -5 IIL Pullup 100µA VI = VSS -195 -40 All other pins No pullup or pulldown -1 1 mA µA CI Input capacitance 2 pF CO Output capacitance 3 pF (1) (2) 5.9 Source currents (out of the device) are negative while sink currents (into the device) are positive. If the input voltage extends outside of the range VIL to VIH then the input current must be limited to IIK to maintain proper operation. See the application note SPNA201 for more information on limiting input clamp currents. Thermal Resistance Characteristics Table 5-2 shows the thermal resistance characteristics for the QFP - PGE mechanical package. Table 5-3 shows the thermal resistance characteristics for the BGA - ZWT mechanical package. Table 5-2. Thermal Resistance Characteristics (PGE Package) °C/W RΘJA Junction-to-free air thermal resistance, Still air using JEDEC 2S2P test board RΘJB Junction-to-board thermal resistance RΘJC Junction-to-case thermal resistance 7.3 ΨJT Junction-to-package top, Still air 0.10 40 27.2 Table 5-3. Thermal Resistance Characteristics (ZWT Package) °C/W RΘJA Junction-to-free air thermal resistance, Still air (includes 5x5 thermal via cluster in 2s2p PCB connected to 1st ground plane) 18.8 RΘJB Junction-to-board thermal resistance 14.1 RΘJC Junction-to-case thermal resistance 7.1 Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 45 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 5-3. Thermal Resistance Characteristics (ZWT Package) (continued) °C/W Junction-to-package top, Still air (includes 5x5 thermal via cluster in 2s2p PCB connected to 1st ground plane) ΨJT 0.33 5.10 Output Buffer Drive Strengths Table 5-4. Output Buffer Drive Strengths LOW-LEVEL OUTPUT CURRENT, IOL for VI=VOLmax or HIGH-LEVEL OUTPUT CURRENT, IOH for VI=VOHmin SIGNALS MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3], MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3], TMS, TDI, TDO, RTCK, SPI4CLK, SPI4SIMO, SPI4SOMI, nERROR, N2HET2[1], N2HET2[3], N2HET2[5], N2HET2[7], N2HET2[9], N2HET2[11], N2HET2[13], N2HET2[15] 8 mA ECAP1, ECAP4, ECAP5, ECAP6 EQEP1I, EQEP1S, EQEP2I, EQEP2S EPWM1A, EPWM1B, EPWM1SYNCO, ETPW2A, EPWM2B, EPWM3A, EPWM3B, EPWM4A, EPWM4B, EPWM5A, EPWM5B, EPWM6A, EPWM6B, EPWM7A, EPWM7B EMIF_ADDR[0:12], EMIF_BA[0:1], EMIF_CKE, EMIF_CLK, EMIF_DATA[0:15], EMIF_nCAS, EMIF_nCS[0:4], EMIF_nDQM[0:1], EMIF_nOE, EMIF_nRAS, EMIF_nWAIT, EMIF_nWE, EMIF_RNW TEST, 4 mA MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK, ECAP2, ECAP3 nRST AD1EVT, CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX, GIOA[0-7], GIOB[0-7], LINRX, LINTX, 2 mA zero-dominant MIBSPI1nCS[0], MIBSPI1nCS[1-3], MIBSPI5nCS[0-3], MIBSPI5nENA, MIBSPI1nENA, MIBSPI3nCS[0-3], MIBSPI3nENA, N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[5], N2HET2[6], N2HET2[7], N2HET2[8], N2HET2[9], N2HET2[10], N2HET2[11], N2HET2[12], N2HET2[13], N2HET2[14], N2HET2[15], N2HET2[16], N2HET2[18], SPI2nCS[0], SPI2nENA, SPI4nCS[0], SPI4nENA ECLK, selectable 8 mA / 2 mA SPI2CLK, SPI2SIMO, SPI2SOMI The default output buffer drive strength is 8 mA for these signals. Table 5-5. Selectable 8 mA/2 mA Control 46 Signal Control Bit Address 8 mA 2 mA ECLK SYSPC10[0] 0xFFFF FF78 0 1 SPI2CLK SPI2PC9[9] 0xFFF7 F668 0 1 SPI2SIMO SPI2PC9[10] 0xFFF7 F668 0 1 Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 5-5. Selectable 8 mA/2 mA Control (continued) (1) Signal Control Bit Address 8 mA 2 mA SPI2SOMI SPI2PC9[11] (1) 0xFFF7 F668 0 1 Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these two bits differ, SPI2PC9[11] determines the drive strength. 5.11 Input Timings t pw Input V IH VCCIO VIH VIL V IL 0 Figure 5-2. TTL-Level Inputs Table 5-6. Timing Requirements for Inputs (1) Parameter MIN Input minimum pulse width tin_slew Time for input signal to go from VIL to VIH or from VIH to VIL (1) (2) MAX Unit tc(VCLK) + 10 (2) tpw ns 1 ns tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK) The timing shown above is only valid for pin used in general-purpose input mode. 5.12 Output Timings Table 5-7. Switching Characteristics for Output Timings versus Load Capacitance ©L) Parameter Rise time, tr 8 mA low EMI pins (see Table 5-4) Fall time, tf Rise time, tr 4 mA low EMI pins (see Table 5-4) Fall time, tf MIN CL = 15 pF MAX Unit 2.5 ns CL = 50 pF 4 CL = 100 pF 7.2 CL = 150 pF 12.5 CL = 15 pF 2.5 CL = 50 pF 4 CL = 100 pF 7.2 CL = 150 pF 12.5 CL = 15 pF 5.6 CL = 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2 CL = 15 pF 5.6 CL= 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2 Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 ns ns ns 47 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 5-7. Switching Characteristics for Output Timings versus Load Capacitance ©L) (continued) Parameter Rise time, tr MIN 2 mA-z low EMI pins (see Table 5-4) Fall time, tf Rise time, tr Selectable 8 mA / 2 mA-z pins (see Table 5-4) 8 mA mode Fall time, tf Rise time, tr 2 mA-z mode Fall time, tf MAX Unit CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 CL = 15 pF 8 CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 CL = 15 pF 2.5 CL = 50 pF 4 CL = 100 pF 7.2 CL = 150 pF 12.5 CL = 15 pF 2.5 CL = 50 pF 4 ns ns CL = 100 pF 7.2 CL = 150 pF 12.5 CL = 15 pF 8 CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 CL = 15 pF 8 CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 tr ns ns tf V OH Output ns VCCIO VOH VOL VOL 0 Figure 5-3. CMOS-Level Outputs Table 5-8. Timing Requirements for Outputs (1) Parameter td(parallel_out) (1) 48 MIN Delay between low to high, or high to low transition of general-purpose output signals that can be configured by an application in parallel, e.g. all signals in a GIOA port, or all N2HET1 signals, etc. MAX UNIT 6 ns This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check Table 5-4 for output buffer drive strength information on each signal. Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 5.13 Low-EMI Output Buffers The low-EMI output buffer has been designed explicitly to address the issue of decoupling sources of emissions from the pins which they drive. This is accomplished by adaptively controlling the impedance of the output buffer, and is particularly effective with capacitive loads. This is not the default mode of operation of the low-EMI output buffers and must be enabled by setting the system module GPCR1 register for the desired module or signal, as shown in . The adaptive impedance control circuit monitors the DC bias point of the output signal. The buffer internally generates two reference levels, VREFLOW and VREFHIGH, which are set to approximately 10% and 90% of VCCIO, respectively. Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then the output buffer’s impedance will increase to hi-Z. A high degree of decoupling between the internal ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing, e.g. the buffer is driving low on a resistive path to ground. Current loads on the buffer which attempt to pull the output voltage above VREFLOW will be opposed by the buffer’s output impedance so as to maintain the output voltage at or below VREFLOW. Conversely, once the output buffer has driven the output to a high level, if the output voltage is above VREFHIGH then the output buffer’s impedance will again increase to hi-Z. A high degree of decoupling between internal power bus ad output pin will occur with capacitive loads or any loads in which no current is flowing, e.g. buffer is driving high on a resistive path to VCCIO. Current loads on the buffer which attempt to pull the output voltage below VREFHIGH will be opposed by the buffer’s output impedance so as to maintain the output voltage at or above VREFHIGH. The bandwidth of the control circuitry is relatively low, so that the output buffer in adaptive impedance control mode cannot respond to high-frequency noise coupling into the buffer’s power buses. In this manner, internal bus noise approaching 20% peak-to-peak of VCCIO can be rejected. Unlike standard output buffers which clamp to the rails, an output buffer in impedance control mode will allow a positive current load to pull the output voltage up to VCCIO + 0.6V without opposition. Also, a negative current load will pull the output voltage down to VSSIO – 0.6V without opposition. This is not an issue since the actual clamp current capability is always greater than the IOH / IOL specifications. The low-EMI output buffers are automatically configured to be in the standard buffer mode when the device enters a low-power mode. Table 5-9. Low-EMI Output Buffer Hookup Module or Signal Name Control Register to Enable Low-EMI Mode Module: MibSPI1 GPREG1.0 Module: SPI2 GPREG1.1 Module: MibSPI3 GPREG1.2 Reserved GPREG1.3 Module: MibSPI5 GPREG1.4 Reserved GPREG1.5 Module: EMIF GPREG1.6 Reserved GPREG1.7 Signal: TMS GPREG1.8 Signal: TDI GPREG1.9 Signal: TDO GPREG1.10 Signal: RTCK GPREG1.11 Signal: TEST GPREG1.12 Signal: nERROR GPREG1.13 Signal: AD1EVT GPREG1.14 Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 49 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6 System Information and Electrical Specifications 6.1 Device Power Domains The device core logic is split up into multiple power domains to optimize the Self-Test Clock Configuration power for a given application use case. There are 7 power domains in total: PD1, PD2, PD3, PD5, and RAM_PD1. Refer to Section 1.4 for more information. PD1 is an "always-ON" power domain, which cannot be turned off. Each of the other power domains can be turned OFF one time during device initialization as per the application requirement. Refer to the Power Management Module (PMM) chapter of TMS570LS12x/11x Technical Reference Manual (SPNU515) for more details. NOTE The clocks to a module must be turned off before powering down the core domain that contains the module. NOTE The logic in the modules that are powered down loses its power completely. Any access to modules that are powered down results in an abort being generated. When power is restored, the modules power-up to their default states (after normal power-up). No register or memory contents are preserved in the core domains that are turned off. 6.2 Voltage Monitor Characteristics A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the requirement for a specific sequence when powering up the core and I/O voltage supplies. 6.2.1 Important Considerations • • 6.2.2 The voltage monitor does not eliminate the need of a voltage supervisor circuit to ensure that the device is held in reset when the voltage supplies are out of range. The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and VCCP supplies. Voltage Monitor Operation The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO signal (PGIO) on the device. During power-up or power-down, the PGMCU and PGIO are driven low when the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and PGMCU being low isolates the core logic as well as the I/O controls during the power-up or power-down of the supplies. This allows the core and I/O supplies to be powered up or down in any order. When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device enters a low power mode. The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.3.3.1 for the timing information on this glitch filter. 50 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-1. Voltage Monitoring Specifications PARAMETER VMON 6.2.3 Voltage monitoring thresholds MIN TYP MAX UNIT VCC low - VCC level below this threshold is detected as too low. 0.75 0.9 1.13 V VCC high - VCC level above this threshold is detected as too high. 1.40 1.7 2.1 VCCIO low - VCCIO level below this threshold is detected as too low. 1.85 2.4 2.9 Supply Filtering The VMON has the capability to filter glitches on the VCC and VCCIO supplies. The following table shows the characteristics of the supply filtering. Glitches in the supply larger than the maximum specification cannot be filtered. Table 6-2. VMON Supply Glitch Filtering Capability Parameter MIN MAX Width of glitch on VCC that can be filtered 250 ns 1 µs Width of glitch on VCCIO that can be filtered 250 ns 1 µs Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 51 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.3 www.ti.com Power Sequencing and Power On Reset 6.3.1 Power-Up Sequence There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The powerup sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 6-4 for more details), core voltage rising above the minimum core supply threshold and the release of power-on reset. The high frequency oscillator will start up first and its amplitude will grow to an acceptable level. The oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. The different supplies to the device can be powered up in any order. The device goes through the following sequential phases during power up. Table 6-3. Power-Up Phases Oscillator start-up and validity check 1032 oscillator cycles eFuse autoload 1160 oscillator cycles Flash pump power-up 688 oscillator cycles Flash bank power-up 617 oscillator cycles Total 3497 oscillator cycles The CPU reset is released at the end of the above sequence and fetches the first instruction from address 0x00000000. 6.3.2 Power-Down Sequence The different supplies to the device can be powered down in any order. 6.3.3 Power-On Reset: nPORRST This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an internal pulldown. 6.3.3.1 nPORRST Electrical and Timing Requirements Table 6-4. Electrical Requirements for nPORRST NO Parameter MIN MAX Unit 0.5 V VCCPORL VCC low supply level when nPORRST must be active during powerup VCCPORH VCC high supply level when nPORRST must remain active during power-up and become active during power down VCCIOPORL VCCIO / VCCP low supply level when nPORRST must be active during power-up VCCIOPORH VCCIO / VCCP high supply level when nPORRST must remain active during power-up and become active during power down VIL(PORRST) Low-level input voltage of nPORRST VCCIO > 2.5V 0.2 * VCCIO V Low-level input voltage of nPORRST VCCIO < 2.5V 0.5 V 1.14 V 1.1 3.0 V V 3 tsu(PORRST) Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL during power-up 0 ms 6 th(PORRST) Hold time, nPORRST active after VCC > VCCPORH 1 ms 7 tsu(PORRST) Setup time, nPORRST active before VCC < VCCPORH during power down 2 µs 8 th(PORRST) Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH 1 ms 9 th(PORRST) Hold time, nPORRST active after VCC < VCCPORL 0 ms 52 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-4. Electrical Requirements for nPORRST (continued) NO Parameter tf(nPORRST) Filter time nPORRST pin; MIN MAX Unit 475 2000 ns pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset. 3.3 V 1.2 V VCCIOPORH VCCPORH 6 VCCIOPORL VCC (1.2 V) VCCIO / VCCP(3.3 V) nPORRST VCCIOPORH VCCIO / VCCP 8 VCCPORH VCC 7 6 7 VCCPORL VCCPORL 3 VIL(PORRST) VCCIOPORL 9 VIL VIL VIL VIL(PORRST) NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing. Figure 6-1. nPORRST Timing Diagram Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 53 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.4 www.ti.com Warm Reset (nRST) This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the output buffer is implemented as an open drain (drives low only). To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal. This terminal has a glitch filter. It also has an internal pullup. 6.4.1 Causes of Warm Reset Table 6-5. Causes of Warm Reset DEVICE EVENT SYSTEM STATUS FLAG Power-Up Reset Exception Status Register, bit 15 Oscillator fail Global Status Register, bit 0 PLL slip Global Status Register, bits 8 and 9 Watchdog exception / Debugger reset Exception Status Register, bit 13 Software Reset Exception Status Register, bit 4 External Reset Exception Status Register, bit 3 6.4.2 nRST Timing Requirements Table 6-6. nRST Timing Requirements PARAMETER tv(RST) Valid time, nRST active after nPORRST inactive Valid time, nRST active (all other System reset conditions) tf(nRST) Filter time nRST pin; MIN 2256 tc(OSC) MAX (1) UNIT ns 32 tc(VCLK) 475 2000 ns pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset (1) 54 Assumes the oscillator has started up and stabilized before nPORRST is released .. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 6.5 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 ARM Cortex-R4F CPU Information 6.5.1 Summary of ARM Cortex-R4F CPU Features The features of the ARM Cortex-R4F CPU include: • An integer unit with integral Embedded ICE-RT logic. • High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI) for Level two (L2) master and slave interfaces. • Floating Point Coprocessor • Dynamic branch prediction with a global history buffer, and a 4-entry return stack • Low interrupt latency. • Non-maskable interrupt. • A Harvard Level one (L1) memory system with: – Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking memories – ARMv7-R architecture Memory Protection Unit (MPU) with 12 regions • Dual core logic for fault detection in safety-critical applications. • An L2 memory interface: – Single 64-bit master AXI interface – 64-bit slave AXI interface to TCM RAM blocks • A debug interface to a CoreSight Debug Access Port (DAP). • A Performance Monitoring Unit (PMU). • A Vectored Interrupt Controller (VIC) port. For more information on the ARM Cortex-R4F CPU, see www.arm.com. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software The following CPU features are disabled on reset and must be enabled by the application if required. • ECC On Tightly-Coupled Memory (TCM) Accesses • Hardware Vectored Interrupt (VIC) Port • Floating Point Coprocessor • Memory Protection Unit (MPU) 6.5.3 Dual Core Implementation The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the CCMR4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by 2 clock cycles as shown in Figure 6-3. The CPUs have a diverse CPU placement given by following requirements: different orientation; for example, CPU1 = "north" orientation, CPU2 = "flip west" orientation dedicated guard ring for each CPU North F Flip West F • • Figure 6-2. Dual - CPU Orientation Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 55 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.5.4 www.ti.com Duplicate clock tree after GCLK The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the 2nd CPU running at the same frequency and in phase to the clock of CPU1. See Figure 6-3. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety This device has two ARM Cortex-R4F CPU cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in a different way as shown in the figure below. Output + Control CCM-R4 2 cycle delay CCM-R4 compare CPU1CLK CPU 1 compare error CPU 2 2 cycle delay CPU2CLK Input + Control Figure 6-3. Dual Core Implementation To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of both CPUs before the registers are used, including function calls where the register values are pushed onto the stack. 6.5.6 CPU Self-Test The CPU STC (Self-Test Controller) is used to test the two Cortex-R4F CPU Cores using the Deterministic Logic BIST Controller as the test engine. The main features of the self-test controller are: • Ability to divide the complete test run into independent test intervals • Capable of running the complete test as well as running few intervals at a time • Ability to continue from the last executed interval (test set) as well as ability to restart from the beginning (First test set) • Complete isolation of the self-tested CPU core from rest of the system during the self-test run • Ability to capture the Failure interval number • Timeout counter for the CPU self-test run as a fail-safe feature 56 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 6.5.6.1 1. 2. 3. 4. 5. 6. 7. SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Application Sequence for CPU Self-Test Configure clock domain frequencies. Select number of test intervals to be run. Configure the timeout period for the self-test run. Enable self-test. Wait for CPU reset. In the reset handler, read CPU self-test status to identify any failures. Retrieve CPU state if required. For more information see TMS570LS12x/11x Technical Reference Manual (SPNU515). 6.5.6.2 CPU Self-Test Clock Configuration The maximum clock rate for the self-test is 90MHz. The STCCLK is divided down from the CPU clock. This divider is configured by the STCCLKDIV register at address 0xFFFFE108. For more information see TMS570LS12x/11x Technical Reference Manual (SPNU515). 6.5.6.3 CPU Self-Test Coverage Table 6-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period. Table 6-7. CPU Self-Test Coverage INTERVALS TEST COVERAGE, % TEST CYCLES 0 0 0 1 62.13 1365 2 70.09 2730 3 74.49 4095 4 77.28 5460 5 79.28 6825 6 80.90 8190 7 82.02 9555 8 83.10 10920 9 84.08 12285 10 84.87 13650 11 85.59 15015 12 86.11 16380 13 86.67 17745 14 87.16 19110 15 87.61 20475 16 87.98 21840 17 88.38 23205 18 88.69 24570 19 88.98 25935 20 89.28 27300 21 89.50 28665 22 89.76 30030 23 90.01 31395 24 90.21 32760 Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 57 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.6 www.ti.com Clocks 6.6.1 Clock Sources The table below lists the available clock sources on the device. Each of the clock sources can be enabled or disabled using the CSDISx registers in the system module. The clock source number in the table corresponds to the control bit in the CSDISx register for that clock source. The table also shows the default state of each clock source. Table 6-8. Available Clock Sources Clock Source # Name 0 OSCIN Main Oscillator Enabled 1 PLL1 Output From PLL1 Disabled Description Default State 2 Reserved Reserved Disabled 3 EXTCLKIN1 External Clock Input #1 Disabled 4 LFLPO Low Frequency Output of Internal Reference Oscillator Enabled HFLPO High Frequency Output of Internal Reference Oscillator Enabled 5 6 PLL2 Output From PLL2 Disabled 7 EXTCLKIN2 External Clock Input #2 Disabled 6.6.1.1 Main Oscillator The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in Figure 6-4. The oscillator is a single stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and low power modes. TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes. An external oscillator source can be used by connecting a 3.3 V clock signal to the OSCIN pin and leaving the OSCOUT pin unconnected (open) as shown in the figure below. OSCIN (see Note B) Kelvin_GND C1 OSCIN OSCOUT OSCOUT C2 (see Note A) External Clock Signal (toggling 0 V to 3.3 V) Crystal (a) (b) Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor. Note B: Kelvin_GND should not be connected to any other GND. Figure 6-4. Recommended Crystal/Clock Connection 58 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.6.1.1.1 Timing Requirements for Main Oscillator Table 6-9. Timing Requirements for Main Oscillator MAX Unit tc(OSC) Cycle time, OSCIN (when using a sine-wave input) Parameter 50 200 ns tc(OSC_SQR) Cycle time, OSCIN, (when input to the OSCIN is a square wave ) 50 200 ns tw(OSCIL) Pulse duration, OSCIN low (when input to the OSCIN is a square wave) 15 ns tw(OSCIH) Pulse duration, OSCIN high (when input to the OSCIN is a square wave) 15 ns Copyright © 2012–2015, Texas Instruments Incorporated MIN Type System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 59 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.6.1.2 www.ti.com Low Power Oscillator The Low Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single macro. 6.6.1.2.1 Features The main features of the LPO are: • Supplies a clock at extremely low power for power-saving modes. This is connected as clock source # 4 of the Global Clock Module. • Supplies a high-frequency clock for non-timing-critical systems. This is connected as clock source # 5 of the Global Clock Module. • Provides a comparison clock for the crystal oscillator failure detection circuit. BIAS_EN LFLPO LFEN LF_TRIM Low Power Oscillator HFEN HFLPO HF_TRIM HFLPO_VALID nPORRST Figure 6-5. LPO Block Diagram Figure 6-5 shows a block diagram of the internal reference oscillator. This is a low power oscillator (LPO) and provides two clock sources: one nominally 80KHz and one nominally 10MHz. Table 6-10. LPO Specifications Parameter Clock Detection LPO - HF oscillator (fHFLPO) LPO - LF oscillator 60 MIN Typical MAX Unit oscillator fail frequency - lower threshold, using untrimmed LPO output 1.375 2.4 4.875 MHz oscillator fail frequency - higher threshold, using untrimmed LPO output 22 38.4 78 MHz untrimmed frequency 5.5 9 19.5 MHz 8 9.6 11 MHz startup time from STANDBY (LPO BIAS_EN High for at least 900µs) 10 µs cold startup time 900 µs trimmed frequency untrimmed frequency 180 kHz startup time from STANDBY (LPO BIAS_EN High for at least 900µs) 36 85 100 µs cold startup time 2000 µs System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 6.6.1.3 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Phase Locked Loop (PLL) Clock Modules The PLL is used to multiply the input frequency to some higher frequency. The main features of the PLL are: • Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The frequency modulation capability of PLL2 is permanently disabled. • Configurable frequency multipliers and dividers. • Built-in PLL Slip monitoring circuit. • Option to reset the device on a PLL slip detection. 6.6.1.3.1 Block Diagram Figure 6-6 shows a high-level block diagram of the two PLL macros on this microcontroller. PLLCTL1 and PLLCTL2 are used to configure the multiplier and dividers for the PLL1. PLLCTL3 is used to configure the multiplier and dividers for PLL2. OSCIN /NR INTCLK VCOCLK PLL /1 to /64 /OD post_ODCLK /1 to /8 /R PLLCLK /1 to /32 fPLLCLK = (fOSCIN / NR) * NF / (OD * R) /NF /1 to /256 OSCIN /NR2 VCOCLK2 INTCLK2 /1 to /64 PLL#2 /NF2 /OD2 post_ODCLK2 /1 to /8 /R2 PLL2CLK /1 to /32 f PLL2CLK = (fOSCIN / NR2) * NF2 / (OD2 * R2) /1 to /256 Figure 6-6. PLLx Block Diagram 6.6.1.3.2 PLL Timing Specifications Table 6-11. PLL Timing Specifications PARAMETER fINTCLK fpost_ODCLK PLL1 Reference Clock frequency VCOCLK – PLL1 Output Divider (OD) input clock frequency fINTCLK2 PLL2 Reference Clock frequency fVCOCLK2 MAX 1 f(OSC_SQR) MHz 400 MHz 150 550 MHz 1 f(OSC_SQR) MHz 400 MHz 550 MHz Post-ODCLK – PLL1 Post-divider input clock frequency fVCOCLK fpost_ODCLK2 MIN Post-ODCLK – PLL2 Post-divider input clock frequency VCOCLK – PLL2 Output Divider (OD) input clock frequency Copyright © 2012–2015, Texas Instruments Incorporated 150 UNIT System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 61 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.6.1.4 www.ti.com External Clock Inputs The device supports up to two external clock inputs. This clock input must be a square wave input. The electrical and timing requirements for these clock inputs are specified below. The external clock sources are not checked for validity. They are assumed valid when enabled. Table 6-12. External Clock Timing and Electrical Specifications Parameter Description Min Max Unit 80 MHz fEXTCLKx External clock input frequency tw(EXTCLKIN)H EXTCLK high-pulse duration 6 ns tw(EXTCLKIN)L EXTCLK low-pulse duration 6 ns viL(EXTCLKIN) Low-level input voltage -0.3 0.8 V viH(EXTCLKIN) High-level input voltage 2 VCCIO + 0.3 V 6.6.2 Clock Domains 6.6.2.1 Clock Domain Descriptions The table below lists the device clock domains and their default clock sources. The table also shows the system module control register that is used to select an available clock source for each clock domain. Table 6-13. Clock Domain Descriptions Clock Domain Name Default Clock Source Clock Source Selection Register Description HCLK OSCIN GHVSRC • • Is disabled through the CDDISx registers bit 1 Used for all system modules including DMA, ESM GCLK OSCIN GHVSRC • • • Always the same frequency as HCLK In phase with HCLK Is disabled separately from HCLK through the CDDISx registers bit 0 Can be divided by 1up to 8 when running CPU self-test (LBIST) using the CLKDIV field of the STCCLKDIV register at address 0xFFFFE108 • 62 GCLK2 OSCIN GHVSRC • • • • Always the same frequency as GCLK 2 cycles delayed from GCLK Is disabled along with GCLK Gets divided by the same divider setting as that for GCLK when running CPU self-test (LBIST) VCLK OSCIN GHVSRC • • • Divided down from HCLK Can be HCLK/1, HCLK/2, ... or HCLK/16 Is disabled separately from HCLK through the CDDISx registers bit 2 VCLK2 OSCIN GHVSRC • • • • Divided down from HCLK Can be HCLK/1, HCLK/2, ... or HCLK/16 Frequency must be an integer multiple of VCLK frequency Is disabled separately from HCLK through the CDDISx registers bit 3 VCLK3 OSCIN GHVSRC • • • Divided down from HCLK Can be HCLK/1, HCLK/2, ... or HCLK/16 Is disabled separately from HCLK through the CDDISx registers bit 8 VCLK4 OSCIN GHVSRC • • • Divided down from HCLK Can be HCLK/1, HCLK/2, ... or HCLK/16 Is disabled separately from HCLK through the CDDISx registers bit 9 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-13. Clock Domain Descriptions (continued) Clock Domain Name Default Clock Source Clock Source Selection Register Description VCLKA1 VCLK VCLKASRC • • Defaults to VCLK as the source Is disabled through the CDDISx registers bit 4 VCLKA2 VCLK VCLKASRC • • Defaults to VCLK as the source Is disabled through the CDDISx registers bit 5 VCLKA4_S VCLK VCLKACON1 • • • Defaults to VCLK as the source Frequency can be as fast as HCLK frequency Is disabled through the CDDISx registers bit 11 VCLKA4_DIVR VCLK VCLKACON1 • Divided down from the VCLKA4_S using the VCLKA4R field of the VCLKACON1 register at address 0xFFFFE140 Frequency can be VCLKA4_S/1, VCLKA4_S/2, ..., or VCLKA4_S/8 Default frequency is VCLKA4_S/2 Is disabled separately through the VCLKACON1 register VCLKA4_DIV_CDDIS bit only if the VCLKA4_S clock is not disabled • • • RTICLK VCLK RCLKSRC • • • Copyright © 2012–2015, Texas Instruments Incorporated Defaults to VCLK as the source If a clock source other than VCLK is selected for RTICLK, then the RTICLK frequency must be less than or equal to VCLK/3 – Application can ensure this by programming the RTI1DIV field of the RCLKSRC register, if necessary Is disabled through the CDDISx registers bit 6 System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 63 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.6.2.2 www.ti.com Mapping of Clock Domains to Device Modules Each clock domain has a dedicated functionality as shown in the figures below. GCM 0 OSCIN PLL #1 /1..64 X1..256 Low Power Oscillator PLL #2 /1..64 X1..256 * the frequency at this node must not exceed the maximum HCLK specifiation. GCLK, GCLK2 (to CPU) (FMzPLL) /1..32 /1..8 1 * 80kHz 4 10MHz /1..16 HCLK (to SYSTEM) VCLK _peri (VCLK to peripherals on PCR1) VCLK_sys (VCLK to system modules) /1..16 VCLK2 (to N2HETx and HTUx) 5 /1..16 VCLK3 (to EMIF) 6 /1..16 VCLK4 (to ePWM, eQEP, eCAP) (FMzPLL) /1..8 /1..32 * 3 EXTCLKIN 1 0 1 3 4 5 6 7 VCLK 7 EXTCLKIN2 0 1 3 4 5 6 7 VCLKA1 (to DCANx) /1, 2, 4, or 8 RTICLK (to RTI, DWWD) VCLK VCLKA1 VCLK VCLK2 VCLK2 /1,2,..1024 /1,2,..256 /2,3..224 /1,2..32 /1,2..65536 HRP /1..64 /1,2..256 N2HETx TU Prop_seg Phase_seg2 SPI Baud Rate LIN / SCI Baud Rate ADCLK ECLK I2C baud rate LIN, SCI MibADCx External Clock I2C Phase_seg1 SPIx,MibSPIx EXTCLKIN1 CAN Baud Rate DCANx PLL#2 output Reserved Reserved NTU[3] NTU[2] NTU[1] RTI LRP /20 ..2 5 Loop High Resolution Clock N2HETx NTU[0] Figure 6-7. Device Clock Domains 64 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 6.6.3 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Clock Test Mode The RM4x platform architecture defines a special mode that allows various clock signals to be brought out on to the ECLK pin and N2HET1[12] device outputs. This mode is called the Clock Test mode. It is very useful for debugging purposes and can be configured through the CLKTEST register in the system module. Table 6-14. Clock Test Mode Options SEL_ECP_PIN = CLKTEST[3-0] SIGNAL ON ECLK SEL_GIO_PIN = CLKTEST[11-8] SIGNAL ON N2HET1[12] 0000 Oscillator 0000 Oscillator Valid Status 0001 Main PLL free-running clock output 0001 Main PLL Valid status 0010 Reserved 0010 Reserved 0011 EXTCLKIN1 0011 Reserved 0100 LFLPO 0100 Reserved 0101 HFLPO 0101 HFLPO Valid status 0110 Secondary PLL free-running clock output 0110 Secondary PLL Valid Status 0111 EXTCLKIN2 0111 Reserved 1000 GCLK 1000 LFLPO 1001 RTI Base 1001 Oscillator Valid status 1010 Reserved 1010 Oscillator Valid status 1011 VCLKA1 1011 Oscillator Valid status 1100 VCLKA2 1100 Oscillator Valid status 1101 Reserved 1101 Reserved 1110 VCLKA4_DIVR 1110 VCLKA4_S 1111 Reserved 1111 Oscillator Valid status Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 65 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.7 www.ti.com Clock Monitoring The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal low power oscillator (LPO). The LPO provides two different clock sources – a low frequency (LFLPO) and a high frequency (HFLPO). The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN frequency falls out of a frequency window, the CLKDET flags this condition in the global status register (GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the HFLPO clock (limp mode clock). The valid OSCIN frequency range is defined as: fHFLPO / 4 < fOSCIN < fHFLPO * 4. 6.7.1 Clock Monitor Timings For more information on LPO and Clock detection, refer to Table 6-10. lower threshold fail 1.375 upper threshold pass 4.875 22 fail f[MHz] 78 Figure 6-8. LPO and Clock Detection, Untrimmed HFLPO 6.7.2 External Clock (ECLK) Output Functionality The ECLK pin can be configured to output a pre-scaled clock signal indicative of an internal device clock. This output can be externally monitored as a safety diagnostic. 6.7.3 Dual Clock Comparators The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of spec, an error signal is generated. For example, the DCC1 can be configured to use HFLPO as the reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source. An additional use of this module is to measure the frequency of a selectable clock source, using the input clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width pulse (1 cycle) after a pre-programmed number of pulses. This pulse sets as an error signal if counter 1 does not reach 0 within the counting window generated by counter 0. 6.7.3.1 • • • • 6.7.3.2 Features Takes two different clock sources as input to two independent counter blocks. One of the clock sources is the known-good, or reference clock; the second clock source is the "clock under test." Each counter block is programmable with initial, or seed values. The counter blocks start counting down from their seed values at the same time; a mismatch from the expected frequency for the clock under test generates an error signal which is used to interrupt the CPU. Mapping of DCC Clock Source Inputs Table 6-15. DCC1 Counter 0 Clock Sources CLOCK SOURCE [3:0] 66 CLOCK NAME others oscillator (OSCIN) 0x5 high frequency LPO System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-15. DCC1 Counter 0 Clock Sources (continued) CLOCK SOURCE [3:0] CLOCK NAME 0xA test clock (TCK) Table 6-16. DCC1 Counter 1 Clock Sources KEY [3:0] CLOCK SOURCE [3:0] others 0xA CLOCK NAME - N2HET1[31] 0x0 Main PLL free-running clock output 0x1 PLL #2 free-running clock output 0x2 low frequency LPO 0x3 high frequency LPO 0x4 reserved 0x5 EXTCLKIN1 0x6 EXTCLKIN2 0x7 reserved 0x8 - 0xF VCLK Table 6-17. DCC2 Counter 0 Clock Sources CLOCK SOURCE [3:0] CLOCK NAME others oscillator (OSCIN) 0xA test clock (TCK) Table 6-18. DCC2 Counter 1 Clock Sources KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME others - N2HET2[0] 0xA 00x0 - 0x7 Reserved 0x8 - 0xF VCLK Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 67 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.8 www.ti.com Glitch Filters A glitch filter is present on the following signals. Table 6-19. Glitch Filter Timing Specifications Pin nPORRST Parameter tf(nPORRST) Filter time nPORRST pin; MIN MAX Unit 475 2000 ns 475 2000 ns 475 2000 ns pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset (1) nRST tf(nRST) Filter time nRST pin; pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset TEST tf(TEST) Filter time TEST pin; pulses less than MIN will be filtered out, pulses greater than MAX will pass through (1) 68 The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump, I/O pins, etc.) without also generating a valid reset signal to the CPU. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 6.9 6.9.1 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Device Memory Map Memory Map Diagram The figure below shows the device memory map. Figure 6-9. Memory Map 0xFFFFFFFF SYSTEM Modules 0xFFF80000 Peripherals - Frame 1 0xFF000000 0xFE000000 CRC RESERVED 0xFCFFFFFF 0xFC000000 Peripherals - Frame 2 RESERVED 0xF07FFFFF Flash Module Bus2 Interface (Flash ECC, OTP and EEPROM Emulation accesses) 0xF0000000 RESERVED 0x87FFFFFF 0x80000000 0x6FFFFFFF 0x60000000 EMIF (128MB) SDRAM RESERVED CS0 reserved 0x6C000000 CS4 0x68000000 CS3 0x64000000 CS2 EMIF (32KB * 3) Async RAM RESERVED 0x200FFFFF 0x20000000 Flash (1MB) (Mirrored Image) RESERVED 0x0841FFFF 0x08400000 RAM - ECC RESERVED 0x0801FFFF 0x08000000 0x000FFFFF 0x00000000 RAM (128KB) RESERVED Flash (1MB) Figure 6-10. Memory Map The Flash memory is mirrored to support ECC logic testing. The base address of the mirrored Flash image is 0x2000 0000. Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 69 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.9.2 www.ti.com Memory Map Table Table 6-20. Device Memory Map FRAME ADDRESS RANGE MODULE NAME FRAME CHIP SELECT TCM Flash CS0 0x0000_0000 0x00FF_FFFF 16MB 1MB TCM RAM + RAM ECC CSRAM0 0x0800_0000 0x0BFF_FFFF 64MB 128KB Mirrored Flash Flash mirror frame 0x2000_0000 0x20FF_FFFF 16MB 1MB START END FRAME ACTUAL SIZE SIZE RESPNSE FOR ACCESS TO UNIMPLEMENTED LOCATIONS IN FRAME Memories tightly coupled to the ARM Cortex-R4F CPU Abort External Memory Accesses EMIF Chip Select 2 (asynchronous) EMIF select 2 0x6000_0000 0x63FF_FFFF 64MB 32KB EMIF Chip Select 3 (asynchronous) EMIF select 3 0x6400_0000 0x67FF_FFFF 64MB 32KB EMIF Chip Select 4 (asynchronous) EMIF select 4 0x6800_0000 0x6BFF_FFFF 64MB 32KB EMIF Chip Select 0 (synchronous) EMIF select 0 0x8000_0000 0x87FF_FFFF 128MB 128MB Access to "Reserved" space will generate Abort Flash Module Bus2 Interface Customer OTP, TCM Flash Banks 0xF000_0000 0xF000_1FFF 8KB 4KB Customer OTP, Bank 7 0xF000_E000 0xF000_FFFF 8KB 2KB Customer OTP–ECC, TCM Flash Banks 0xF004_0000 0xF004_03FF 1KB 512B Customer OTP–ECC, Bank 7 0xF004_1C00 0xF004_1FFF 1KB 256B TI OTP, TCM Flash Banks 0xF008_0000 0xF008_1FFF 8KB 4KB TI OTP, Bank 7 0xF008_E000 0xF008_FFFF 8KB 2KB TI OTP–ECC, TCM Flash Banks 0xF00C_0000 0xF00C_03FF 1KB 512B TI OTP–ECC, Bank 7 0xF00C_1C00 0xF00C_1FFF 1KB 256B Bank 7 – ECC 0xF010_0000 0xF013_FFFF 256KB 8KB Abort Bank 7 0xF020_0000 0xF03F_FFFF 2MB 64KB Flash Data Space ECC 0xF040_0000 0xF04F_FFFF 1MB 128KB EMIF Registers 0xFCFF_E800 256B 256B Abort EMIF slave interfaces 0xFCFF_E8FF SCR5: Enhanced Timer Peripherals 70 ePWM1 0xFCF7_8C00 0xFCF7_8CFF 256B 256B Abort ePWM2 0xFCF7_8D00 0xFCF7_8DFF 256B 256B Abort ePWM3 0xFCF7_8E00 0xFCF7_8EFF 256B 256B Abort ePWM4 0xFCF7_8F00 0xFCF7_8FFF 256B 256B Abort ePWM5 0xFCF7_9000 0xFCF7_90FF 256B 256B Abort ePWM6 0xFCF7_9100 0xFCF7_91FF 256B 256B Abort ePWM7 0xFCF7_9200 0xFCF7_92FF 256B 256B Abort eCAP1 0xFCF7_9300 0xFCF7_93FF 256B 256B Abort System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-20. Device Memory Map (continued) MODULE NAME FRAME CHIP SELECT FRAME ADDRESS RANGE FRAME ACTUAL SIZE SIZE RESPNSE FOR ACCESS TO UNIMPLEMENTED LOCATIONS IN FRAME START END eCAP2 0xFCF7_9400 0xFCF7_94FF 256B 256B Abort eCAP3 0xFCF7_9500 0xFCF7_95FF 256B 256B Abort eCAP4 0xFCF7_9600 0xFCF7_96FF 256B 256B Abort eCAP5 0xFCF7_9700 0xFCF7_97FF 256B 256B Abort eCAP6 0xFCF7_9800 0xFCF7_98FF 256B 256B Abort eQEP1 0xFCF7_9900 0xFCF7_99FF 256B 256B Abort 0xFCF7_9A00 0xFCF7_9AFF 256B 256B Abort eQEP2 Cyclic Redundancy Checker (CRC) Module Registers 16MB 512B Accesses above 0x200 generate abort. 0xFF0B_FFFF 128KB 2KB Abort for accesses above 2KB 0xFF0D_FFFF 128KB 2KB Abort for accesses above 2KB 0xFF0F_FFFF 128KB 2KB Abort for accesses above 2KB 0xFF1B_FFFF 128KB 2KB Wrap around for accesses to unimplemented address offsets lower than 0x7FF. Abort generated for accesses beyond offset 0x800. 2KB Wrap around for accesses to unimplemented address offsets lower than 0x7FF. Abort generated for accesses beyond offset 0x800. 2KB Wrap around for accesses to unimplemented address offsets lower than 0x7FF. Abort generated for accesses beyond offset 0x800. 8KB Wrap around for accesses to unimplemented address offsets lower than 0x1FFF. Abort generated for accesses beyond 0x1FFF. MIBADC2 LookUp Table 384B Look-Up Table for ADC2 wrapper. Starts at address offset 0x2000 and ends at address offset 0x217F. Wrap around for accesses between offsets 0x0180 and 0x3FFF. Abort generated for accesses beyond offset 0x4000. MIBADC1 RAM 8KB Wrap around for accesses to unimplemented address offsets lower than 0x1FFF. Abort generated for accesses beyond 0x1FFF. 384B Look-Up Table for ADC1 wrapper. Starts at address offset 0x2000 and ends at address offset 0x217F. Wrap around for accesses between offsets 0x0180 and 0x3FFF. Abort generated for accesses beyond offset 0x4000. 16KB Wrap around for accesses to unimplemented address offsets lower than 0x3FFF. Abort generated for accesses beyond 0x3FFF. CRC CRC frame 0xFE00_0000 MIBSPI5 RAM PCS[5] 0xFF0A_0000 MIBSPI3 RAM PCS[6] 0xFF0C_0000 MIBSPI1 RAM PCS[7] 0xFF0E_0000 DCAN3 RAM PCS[13] 0xFF1A_0000 0xFEFF_FFFF Peripheral Memories DCAN2 RAM DCAN1 RAM PCS[14] PCS[15] 0xFF1C_0000 0xFF1E_0000 0xFF1D_FFFF 0xFF1F_FFFF 128KB 128KB MIBADC2 RAM PCS[29] PCS[31] 0xFF3A_0000 0xFF3E_0000 0xFF3B_FFFF 0xFF3F_FFFF 128KB 128KB MibADC1 LookUp Table N2HET2 RAM PCS[34] 0xFF44_0000 0xFF45_FFFF 128KB N2HET1 RAM PCS[35] 0xFF46_0000 0xFF47_FFFF 128KB 16KB Wrap around for accesses to unimplemented address offsets lower than 0x3FFF. Abort generated for accesses beyond 0x3FFF. HTU2 RAM PCS[38] 0xFF4C_0000 0xFF4D_FFFF 128KB 1KB Abort HTU1 RAM PCS[39] 0xFF4E_0000 0xFF4F_FFFF 128KB 1KB Abort Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 71 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 6-20. Device Memory Map (continued) MODULE NAME FRAME CHIP SELECT FRAME ADDRESS RANGE START END FRAME ACTUAL SIZE SIZE RESPNSE FOR ACCESS TO UNIMPLEMENTED LOCATIONS IN FRAME Debug Components CoreSight Debug ROM CSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KB Reads return zeros, writes have no effect Cortex-R4F Debug CSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB Reads return zeros, writes have no effect POM CSCS4 0xFFA0_4000 0xFFA0_4FFF 4KB 4KB Abort Peripheral Control Registers HTU1 PS[22] 0xFFF7_A400 0xFFF7_A4FF 256B 256B Reads return zeros, writes have no effect HTU2 PS[22] 0xFFF7_A500 0xFFF7_A5FF 256B 256B Reads return zeros, writes have no effect N2HET1 PS[17] 0xFFF7_B800 0xFFF7_B8FF 256B 256B Reads return zeros, writes have no effect N2HET2 PS[17] 0xFFF7_B900 0xFFF7_B9FF 256B 256B Reads return zeros, writes have no effect GIO PS[16] 0xFFF7_BC00 0xFFF7_BDFF 512B 256B Reads return zeros, writes have no effect MIBADC1 PS[15] 0xFFF7_C000 0xFFF7_C1FF 512B 512B Reads return zeros, writes have no effect MIBADC2 PS[15] 0xFFF7_C200 0xFFF7_C3FF 512B 512B Reads return zeros, writes have no effect I2C PS[10] 0xFFF7_D400 0xFFF7_D4FF 256B 256B Reads return zeros, writes have no effect DCAN1 PS[8] 0xFFF7_DC00 0xFFF7_DDFF 512B 512B Reads return zeros, writes have no effect DCAN2 PS[8] 0xFFF7_DE00 0xFFF7_DFFF 512B 512B Reads return zeros, writes have no effect DCAN3 PS[7] 0xFFF7_E000 0xFFF7_E1FF 512B 512B Reads return zeros, writes have no effect LIN PS[6] 0xFFF7_E400 0xFFF7_E4FF 256B 256B Reads return zeros, writes have no effect SCI PS[6] 0xFFF7_E500 0xFFF7_E5FF 256B 256B Reads return zeros, writes have no effect MibSPI1 PS[2] 0xFFF7_F400 0xFFF7_F5FF 512B 512B Reads return zeros, writes have no effect SPI2 PS[2] 0xFFF7_F600 0xFFF7_F7FF 512B 512B Reads return zeros, writes have no effect MibSPI3 PS[1] 0xFFF7_F800 0xFFF7_F9FF 512B 512B Reads return zeros, writes have no effect SPI4 PS[1] 0xFFF7_FA00 0xFFF7_FBFF 512B 512B Reads return zeros, writes have no effect MibSPI5 PS[0] 0xFFF7_FC00 0xFFF7_FDFF 512B 512B Reads return zeros, writes have no effect DMA RAM PPCS0 0xFFF8_0000 System Modules Control Registers and Memories 0xFFF8_0FFF 4KB 4KB Abort VIM RAM PPCS2 0xFFF8_2000 0xFFF8_2FFF 4KB 1KB Wrap around for accesses to unimplemented address offsets between 1KB and 4KB. Flash Module PPCS7 0xFFF8_7000 0xFFF8_7FFF 4KB 4KB Abort eFuse Controller PPCS12 0xFFF8_C000 0xFFF8_CFFF 4KB 4KB Abort Power Management Module (PMM) PPSE0 0xFFFF_0000 0xFFFF_01FF 512B 512B Abort 72 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-20. Device Memory Map (continued) MODULE NAME FRAME CHIP SELECT PCR registers FRAME ADDRESS RANGE FRAME ACTUAL SIZE SIZE RESPNSE FOR ACCESS TO UNIMPLEMENTED LOCATIONS IN FRAME START END PPS0 0xFFFF_E000 0xFFFF_E0FF 256B 256B Reads return zeros, writes have no effect System Module Frame 2 (see SPNU515) PPS0 0xFFFF_E100 0xFFFF_E1FF 256B 256B Reads return zeros, writes have no effect PBIST PPS1 0xFFFF_E400 0xFFFF_E5FF 512B 512B Reads return zeros, writes have no effect STC PPS1 0xFFFF_E600 0xFFFF_E6FF 256B 256B Generates address error interrupt, if enabled IOMM Multiplexing Control Module PPS2 0xFFFF_EA00 0xFFFF_EBFF 512B 512B Reads return zeros, writes have no effect DCC1 PPS3 0xFFFF_EC00 0xFFFF_ECFF 256B 256B Reads return zeros, writes have no effect DMA PPS4 0xFFFF_F000 0xFFFF_F3FF 1KB 1KB Reads return zeros, writes have no effect DCC2 PPS5 0xFFFF_F400 0xFFFF_F4FF 256B 256B Reads return zeros, writes have no effect ESM PPS5 0xFFFF_F500 0xFFFF_F5FF 256B 256B Reads return zeros, writes have no effect CCMR4 PPS5 0xFFFF_F600 0xFFFF_F6FF 256B 256B Reads return zeros, writes have no effect RAM ECC even PPS6 0xFFFF_F800 0xFFFF_F8FF 256B 256B Reads return zeros, writes have no effect RAM ECC odd PPS6 0xFFFF_F900 0xFFFF_F9FF 256B 256B Reads return zeros, writes have no effect RTI + DWWD PPS7 0xFFFF_FC00 0xFFFF_FCFF 256B 256B Reads return zeros, writes have no effect VIM Parity PPS7 0xFFFF_FD00 0xFFFF_FDFF 256B 256B Reads return zeros, writes have no effect VIM PPS7 0xFFFF_FE00 0xFFFF_FEFF 256B 256B Reads return zeros, writes have no effect System Module Frame 1 (see SPNU515) PPS7 0xFFFF_FF00 0xFFFF_FFFF 256B 256B Reads return zeros, writes have no effect 6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts Any CPU write access to a Normal or Device type memory, which generates a fault, will generate an imprecise abort. The imprecise abort exception is disabled by default and must be enabled for the CPU to handle this exception. The imprecise abort handling is enabled by clearing the "A" bit in the CPU’s program status register (CPSR). 6.9.4 Master/Slave Access Privileges The table below lists the access permissions for each bus master on the device. A bus master is a module that can initiate a read or a write transaction on the device. Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed in the "MASTERS" column can access that slave module. Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 73 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 6-21. Master / Slave Access Matrix MASTERS ACCESS MODE SLAVES ON MAIN SCR Flash Module Bus2 Interface: OTP, ECC, Bank 7 Non-CPU Accesses to Program Flash and CPU Data RAM CRC EMIF Slave Interface Peripheral Control Registers, All Peripheral Memories, And All System Module Control Registers And Memories CPU READ User/Privilege Yes Yes Yes Yes Yes CPU WRITE User/Privilege No Yes Yes Yes Yes DMA User Yes Yes Yes Yes Yes POM User Yes Yes Yes Yes Yes DAP Privilege Yes Yes Yes Yes Yes HTU1 Privilege No Yes Yes Yes Yes HTU2 Privilege No Yes Yes Yes Yes 6.9.5 Special Notes on Accesses to Certain Slaves Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU (master id = 1). The other masters can only read from these registers. A debugger can also write to the PMM registers. The master-id check is disabled in debug mode. The device contains dedicated logic to generate a bus error response on any access to a module that is in a power domain that has been turned OFF. 6.9.6 Parameter Overlay Module (POM) Considerations • • • • 74 The POM can map onto up to 8MB of the internal or external memory space. The starting address and the size of the memory overlay are configurable through the POM control registers. Care must be taken to ensure that the overlay is mapped on to available memory. ECC must be disabled by software through CP15 in case POM overlay is enabled; otherwise ECC errors will be generated. POM overlay must not be enabled when the flash and internal RAM memories are swapped through the MEM SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1). When POM is used to overlay the flash on to internal or external RAM, there is a bus contention possibility when another master accesses the TCM flash. This results in a system hang. – The POM implements a timeout feature to detect this exact scenario. The timeout needs to be enabled whenever POM overlay is enabled. – The timeout can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global Control register (POMGLBCTRL, address = 0xFFA04000). – In case a read request by the POM cannot be completed within 32 HCLK cycles, the timeout (TO) flag is set in the POM Flag register (POMFLG, address = 0xFFA0400C). Also, an abort is generated to the CPU. This can be a prefetch abort for an instruction fetch or a data abort for a data fetch. – The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM is set. If so, then the application can assume that the timeout is caused by a bus contention between the POM transaction and another master accessing the same memory region. The abort handlers need to clear the TO flag, so that any further aborts are not misinterpreted as having been caused due to a timeout from the POM. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.10 Flash Memory 6.10.1 Flash Memory Configuration Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense amplifiers, and control logic. Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical construction constraints. Flash Pump: A charge pump which generates all the voltages required for reading, programming, or erasing the flash banks. Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module. Table 6-22. Flash Memory Banks and Sectors Memory Arrays (or Banks) Sector No. Segment Low Address High Address BANK0 (1MByte) (1) 0 16K Bytes 0x0000_0000 0x0000_3FFF 1 16K Bytes 0x0000_4000 0x0000_7FFF 2 16K Bytes 0x0000_8000 0x0000_BFFF 3 16K Bytes 0x0000_C000 0x0000_FFFF 4 16K Bytes 0x0001_0000 0x0001_3FFF 5 16K Bytes 0x0001_4000 0x0001_7FFF 6 32K Bytes 0x0001_8000 0x0001_FFFF 7 128K Bytes 0x0002_0000 0x0003_FFFF 8 128K Bytes 0x0004_0000 0x0005_FFFF 9 128K Bytes 0x0006_0000 0x0007_FFFF 10 128K Bytes 0x0008_0000 0x0009_FFFF 11 128K Bytes 0x000A_0000 0x000B_FFFF 12 128K Bytes 0x000C_0000 0x000D_FFFF 13 128K Bytes 0x000E_0000 0x000F_FFFF 0 16K Bytes 0xF020_0000 0xF020_3FFF 1 16K Bytes 0xF020_4000 0xF020_7FFF 2 16K Bytes 0xF020_8000 0xF020_BFFF 3 16K Bytes 0xF020_C000 0xF020_FFFF BANK7 (64KBytes) for EEPROM emulation (1) (2) (3) (2) (3) The Flash banks are 144-bit wide bank with ECC support. The flash bank7 can be programmed while executing code from flash bank0. Code execution is not allowed from flash bank7. 6.10.2 Main Features of Flash Module • • • • • • Support for multiple flash banks for program and/or data storage Simultaneous read access on a bank while performing program or erase operation on any other bank Integrated state machines to automate flash erase and program operations Pipelined mode operation to improve instruction access interface bandwidth Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4F CPU – Error address is captured for host system debugging Support for a rich set of diagnostic features Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 75 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.10.3 ECC Protection for Flash Accesses All accesses to the program flash memory are protected by Single Error Correction Double Error Detection (SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on the 64 bits received and compares it with the ECC code returned by the flash module. A single-bit error is corrected and flagged by the CPU, while a multibit error is only flagged. The CPU signals an ECC error through its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the "X" bit of the Performance Monitor Control Register, c9. MRC ORR MCR MRC p15,#0,r1,c9,c12,#0 r1, r1, #0x00000010 p15,#0,r1,c9,c12,#0 p15,#0,r1,c9,c12,#0 ;Enabling Event monitor states ;Set 4th bit (‘X’) of PMNC register The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN bits of the System Control coprocessor's Auxiliary Control Register, c1. MRC p15, #0, r1, c1, c0, #1 ORR r1, r1, #0x0e000000 DMB MCR p15, #0, r1, c1, c0, #1 ;Enable ECC checking for ATCM and BTCMs 6.10.4 Flash Access Speeds For information on flash memory access speeds and the relevant wait states required, refer to Section 5.6. 76 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.10.5 Program Flash Table 6-23. Timing Requirements for Program Flash Parameter MIN tprog(144bit) Wide Word (144bit) programming time tprog(Total) 1MByte programming time (1) terase(bank0) (1) (2) MAX Unit 40 300 µs 11 s 5.5 s -40°C to 125°C Sector/Bank erase time (2) 0°C to 60°C, for first 25 cycles 2.8 -40°C to 125°C 0.03 4 s 16 100 ms 1000 cycles 0°C to 60°C, for first 25 cycles twec NOM Write/erase cycles with 15 year Data Retention -40°C to 125°C requirement This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes programming 144 bits at a time at the maximum specified operating frequency. During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase a sector. 6.10.6 Data Flash Table 6-24. Timing Requirements for Data Flash Parameter MIN NOM MAX Unit 40 300 µs 660 ms 330 ms 0.2 8 s 14 100 ms 100000 cycles tprog(144bit) Wide Word (144bit) programming time tprog(Total) EEPROM Emulation (bank 7) 64KByte programming time (1) -40°C to 125°C 0°C to 60°C, for first 25 cycles 165 EEPROM Emulation (bank 7) Sector/Bank erase time (2) -40°C to 125°C 0°C to 60°C, for first 25 cycles terase(bank7) twec (1) (2) Write/erase cycles with 15 year Data Retention -40°C to 125°C requirement This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes programming 144 bits at a time at the maximum specified operating frequency. During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase a sector. Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 77 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.11 Tightly Coupled RAM Interface Module Figure 6-11 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F CPU. Upper 32 bits data & 4 ECC bits Cortex-R4F B0 TCM TCM BUS TCRAM Interface 1 72 Bit data + ECC Lower 32 bits data & 4 ECC bits B1 TCM Upper 32 bits data & 4 ECC bits TCM BUS 72 Bit data + ECC TCRAM Interface 2 Lower 32 bits data & 4 ECC bits 36 Bit Bit 3636 Bit wide wide wideRAM RAM RAM 36 Bit Bit 3636 Bit wide wide wideRAM RAM RAM 36 Bit Bit 3636 Bit wide wide wideRAM RAM RAM 36 Bit Bit 3636 Bit wide wide wide RAM RAM RAM Figure 6-11. TCRAM Block Diagram 6.11.1 Features The features of the Tightly Coupled RAM (TCRAM) Module are: • • • • • • • • • Acts as slave to the BTCM interface of the Cortex-R4F CPU Supports the internal ECC scheme of the CPU by providing 64-bit data and 8-bit ECC code Monitors CPU Event Bus and generates single or multibit error interrupts Stores addresses for single and multibit errors Supports RAM trace module Provides CPU address bus integrity checking by supporting parity checking on the address bus Performs redundant address decoding for the RAM bank chip select and ECC select generation logic Provides enhanced safety for the RAM addressing by implementing two 36-bit-wide byte-interleaved RAM banks and generating independent RAM access control signals to the two banks Supports auto-initialization of the RAM banks along with the ECC bits 6.11.2 TCRAM ECC Support The TCRAM interface passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM. It also stores the contents of the CPU ECC port in the ECC RAM when the CPU does a write to the RAM. The TCRAM interface monitors the CPU event bus and provides registers for indicating single/multibit errors and also for identifying the address that caused the single or multibit error. The event signaling and the ECC checking for the RAM accesses must be enabled inside the CPU. For more information see TMS570LS12x/11x Technical Reference Manual (SPNU515). 6.12 Parity Protection for Accesses to Peripheral RAMs Accesses to some peripheral RAMs are protected by odd/even parity checking. During a read access the parity is calculated based on the data read from the peripheral RAM and compared with the good parity value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates a parity error signal that is mapped to the Error Signaling Module. The module also captures the peripheral RAM address that caused the parity error. The parity protection for peripheral RAMs is not enabled by default and must be enabled by the application. Each individual peripheral contains control registers to enable the parity protection for accesses to its RAM. 78 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 NOTE The CPU read access gets the actual data from the peripheral. The application can choose to generate an interrupt whenever a peripheral RAM parity error is detected. Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 79 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.13 On-Chip SRAM Initialization and Testing 6.13.1 On-Chip SRAM Self-Test Using PBIST 6.13.1.1 Features • • • Extensive instruction set to support various memory test algorithms ROM-based algorithms allow application to run TI production-level memory tests Independent testing of all on-chip SRAM 6.13.1.2 PBIST RAM Groups Table 6-25. PBIST RAM Grouping Test Pattern (Algorithm) Memory RAM Group Test Clock triple read slow read triple read fast read March 13N (1) two port (cycles) March 13N (1) single port (cycles) ALGO MASK 0x1 ALGO MASK 0x2 ALGO MASK 0x4 ALGO MASK 0x8 ROM 24578 8194 19586 6530 MEM Type PBIST_ROM 1 ROM CLK STC_ROM 2 ROM CLK ROM DCAN1 3 VCLK Dual Port 25200 DCAN2 4 VCLK Dual Port 25200 DCAN3 5 VCLK Dual Port 25200 ESRAM1 (1) (2) (3) (2) 6 HCLK Single Port MIBSPI1 7 VCLK Dual Port 33440 266280 MIBSPI3 8 VCLK Dual Port 33440 MIBSPI5 9 VCLK Dual Port 33440 VIM 10 VCLK Dual Port 12560 MIBADC1 11 VCLK Dual Port 4200 DMA 12 HCLK Dual Port 18960 N2HET1 13 VCLK Dual Port 31680 HTU1 14 VCLK Dual Port 6480 MIBADC2 18 VCLK Dual Port 4200 N2HET2 19 VCLK Dual Port 31680 HTU2 20 VCLK Dual Port 6480 ESRAM5 (3) 21 HCLK Single Port 266280 There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for application testing. ESRAM1: Address 0x08000000 - 0x0800FFFF ESRAM5: Address 0x08010000 - 0x0801FFFF The PBIST ROM clock frequency is limited to 100MHz, if 100MHz < HCLK NMI => nERROR 2.6 B0 TCM (even) address bus parity error User/Privilege ESM => NMI => nERROR 2.10 B1 TCM (odd) ECC single error (correctable) User/Privilege ESM 1.28 B1 TCM (odd) ECC double error (non-correctable) User/Privilege Abort (CPU), ESM => nERROR 3.5 B1 TCM (odd) uncorrectable error (for example, redundant address decode) User/Privilege ESM => NMI => nERROR 2.8 B1 TCM (odd) address bus parity error User/Privilege ESM => NMI => nERROR 2.12 Illegal instruction MPU access violation SRAM B0 TCM (even) ECC single error (correctable) FLASH WITH CPU BASED ECC FMC correctable error - Bus1 and Bus2 interfaces (does not include accesses to Bank 7) User/Privilege ESM 1.6 FMC uncorrectable error - Bus1 and Bus2 accesses (does not include address parity error) User/Privilege Abort (CPU), ESM => nERROR 3.7 FMC uncorrectable error - address parity error on Bus1 accesses User/Privilege ESM => NMI => nERROR 2.4 FMC correctable error - Accesses to Bank 7 User/Privilege ESM 1.35 FMC uncorrectable error - Accesses to Bank 7 User/Privilege ESM 1.36 DMA TRANSACTIONS External imprecise error on read (Illegal transaction with ok response) User/Privilege ESM 1.5 External imprecise error on write (Illegal transaction with ok response) User/Privilege ESM 1.13 Memory access permission violation User/Privilege ESM 1.2 Memory parity error User/Privilege ESM 1.3 High-End Timer Transfer Unit 1 (HTU1) NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt => VIM n/a External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt => VIM n/a Memory access permission violation User/Privilege ESM 1.9 Memory parity error User/Privilege ESM 1.8 High-End Timer Transfer Unit 2 (HTU2) NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt => VIM n/a External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt => VIM n/a Memory access permission violation User/Privilege ESM 1.9 Memory parity error User/Privilege ESM 1.8 (1) 102 The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage of the CPU. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 6-36. Reset/Abort/Error Sources (continued) ERROR SOURCE SYSTEM MODE ERROR RESPONSE ESM HOOKUP group.channel ESM 1.7 ESM 1.34 N2HET1 Memory parity error User/Privilege N2HET2 Memory parity error User/Privilege MIBSPI MibSPI1 memory parity error User/Privilege ESM 1.17 MibSPI3 memory parity error User/Privilege ESM 1.18 User/Privilege ESM 1.24 User/Privilege ESM 1.19 User/Privilege ESM 1.1 MibSPI5 memory parity error MIBADC MibADC1 Memory parity error MibADC2 Memory parity error DCAN DCAN1 memory parity error User/Privilege ESM 1.21 DCAN2 memory parity error User/Privilege ESM 1.23 DCAN3 memory parity error User/Privilege ESM 1.22 User/Privilege ESM 1.10 User/Privilege ESM 1.42 ESM 1.11 PLL PLL slip error PLL #2 slip error CLOCK MONITOR Clock monitor interrupt User/Privilege DCC DCC1 error User/Privilege ESM 1.30 DCC2 error User/Privilege ESM 1.62 CCM-R4 Self test failure User/Privilege ESM 1.31 Compare failure User/Privilege ESM => NMI => nERROR 2.2 ESM 1.15 Reset n/a ESM 1.27 ESM 1.37 VIM Memory parity error User/Privilege VOLTAGE MONITOR VMON out of voltage range n/a CPU SELFTEST (LBIST) CPU Selftest (LBIST) error User/Privilege PIN MULTIPLEXING CONTROL Mux configuration error User/Privilege POWER DOMAIN CONTROL PSCON compare error User/Privilege ESM 1.38 PSCON self-test error User/Privilege ESM 1.39 eFuse CONTROLLER eFuse Controller Autoload error User/Privilege ESM => nERROR 3.1 eFuse Controller - Any bit set in the error status register User/Privilege ESM 1.40 User/Privilege ESM 1.41 ESM => NMI => nERROR 2.24 eFuse Controller self-test error WINDOWED WATCHDOG WWD Non-Maskable Interrupt exception n/a ERRORS REFLECTED IN THE SYSESR REGISTER Power-Up Reset n/a Reset n/a Oscillator fail / PLL slip (2) n/a Reset n/a (2) Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset. Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 103 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 6-36. Reset/Abort/Error Sources (continued) SYSTEM MODE ERROR RESPONSE ESM HOOKUP group.channel Watchdog exception n/a Reset n/a CPU Reset (driven by the CPU STC) n/a Reset n/a Software Reset n/a Reset n/a External Reset n/a Reset n/a ERROR SOURCE 104 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.20 Digital Windowed Watchdog This device includes a digital windowed watchdog (DWWD) module that protects against runaway code execution. The DWWD module allows the application to configure the time window within which the DWWD module expects the application to service the watchdog. A watchdog violation occurs if the application services the watchdog outside of this window, or fails to service the watchdog at all. The application can choose to generate a system reset or an ESM group2 error signal in case of a watchdog violation. The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog can only be disabled upon a system reset. Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 105 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.21 Debug Subsystem 6.21.1 Block Diagram The device contains an ICEPICK module to allow JTAG access to the scan chains. Boundary Scan BSR/BSDL Boundary Scan I/F TRST TMS TCK RTCK TDI TDO Debug ROM1 Debug APB DAP Secondary Tap 0 APB Mux AHB-AP POM ICEPICK_C to SCR1 via A2A from PCR1/Bridge APB slave Cortex R4F Secondary Tap 2 AJSM Test Tap 0 eFuse Farm Test Tap 1 PSCON Figure 6-20. Debug Subsystem Block Diagram 6.21.2 Debug Components Memory Map Table 6-37. Debug Components Memory Map MODULE NAME FRAME CHIP SELECT CoreSight Debug ROM Cortex-R4F Debug FRAME ADDRESS RANGE FRAME ACTUA SIZE L SIZE RESPNSE FOR ACCESS TO UNIMPLEMENTED LOCATIONS IN FRAME START END CSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KB Reads return zeros, writes have no effect CSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB Reads return zeros, writes have no effect 6.21.3 JTAG Identification Code The JTAG ID code for this device is the same as the device ICEPick Identification Code. Table 6-38. JTAG ID Code 106 Silicon Revision ID Rev A 0x0B95502F Rev B 0x2B95502F Rev C 0x3B95502F System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.21.4 Debug ROM The Debug ROM stores the location of the components on the Debug APB bus: Table 6-39. Debug ROM table ADDRESS DESCRIPTION VALUE 0x000 pointer to Cortex-R4F 0x0000 1003 0x001 Reserved 0x0000 2002 0x002 Reserved 0x0000 3002 0x003 POM 0x0000 4003 0x004 end of table 0x0000 0000 Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 107 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.21.5 JTAG Scan Interface Timings Table 6-40. JTAG Scan Interface Timing (1) No. Parameter fTCK fRTCK 1 td(TCK -RTCK) 2 tsu(TDI/TMS - RTCKr) 3 th(RTCKr -TDI/TMS) 4 th(RTCKr -TDO) 5 td(TCKf -TDO) (1) Min TCK frequency (at HCLKmax) RTCK frequency (at TCKmax and HCLKmax) MAX Unit 12 MHz 10 Delay time, TCK to RTCK MHz 24 ns Setup time, TDI, TMS before RTCK rise (RTCKr) 26 ns Hold time, TDI, TMS after RTCKr 0 ns Hold time, TDO after RTCKf 0 Delay time, TDO valid after RTCK fall (RTCKf) ns 12 ns Timings for TDO are specified for a maximum of 50pF load on TDO TCK RTCK 1 1 TMS TDI 2 3 TDO 4 5 Figure 6-21. JTAG Timing 108 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 6.21.6 Advanced JTAG Security Module This device includes a an Advanced JTAG Security Module (AJSM). which provides maximum security to the device’s memory content by allowing users to secure the device after programming. Flash Module Output OTP Contents (example) H L H ... ... L Unlock By Scan Register Internal Tie-Offs (example only) L L H H L H H L H H L L UNLOCK 128-bit comparator Internal Tie-Offs (example only) H L L H H L L H Figure 6-22. AJSM Unlock The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP address 0xF0000000.The OTP contents are XOR-ed with the "Unlock By Scan" register contents. The outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of this combinational logic is compared against a secret hard-wired 128-bit value. A match results in the UNLOCK signal being asserted, so that the device is now unsecure. A user can secure the device by changing at least one bit in the visible unlock code from 1 to 0. Changing a 0 to 1 is not possible since the visible unlock code is stored in the One Time Programmable (OTP) flash region. Also, changing all the 128 bits to zeros is not a valid condition and will permanently secure the device. Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By Scan" register of the AJSM module. This register is accessible by configuring an IR value of 0b1011 on the AJSM TAP. The value to be scanned is such that the XOR of the OTP contents and the Unlock-ByScan register contents results in the original visible unlock code. The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST). A secure device only permits JTAG accesses to the AJSM scan chain through the Secondary Tap # 2 of the ICEPick module. All other secondary taps, test taps and the boundary scan interface are not accessible in this state. Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 109 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 6.21.7 Boundary Scan Chain The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary scan chain is connected to the Boundary Scan Interface of the ICEPICK module. Device Pins (conceptual) RTCK TDI TDO IC E P ICK TRST TMS TCK Boundary Scan Interface Boundary Scan TDI TDO BSDL Figure 6-23. Boundary Scan Implementation (Conceptual Diagram) Data is serially shifted into all boundary-scan buffers through TDI, and out through TDO. 110 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 7 Peripheral Information and Electrical Specifications 7.1 Enhanced Translator PWM Modules (ePWM) Figure 7-1 illustrates the connections between the seven ePWM modules (ePWM1,2,3,4,5,6,7) on the device. PINMMR36[25] NHET1_LOOP_SYNC EPWMSYNCI VIM EPWM1TZINTn VIM EPWM1INTn ADC Wrapper EPWM1A EPWM1B TZ1/2/3n Mux Selector SOCA1, SOCB1 EPWM1 VBus32 EQEP1 + EQEP2 EQEP1ERR / EQEP2ERR / EQEP1ERR or EQEP2ERR System Module OSC FAIL or PLL Slip Debug Mode Entry CPU TZ4n VCLK4, SYS_nRST EPWM1ENCLK TBCLKSYNC TZ5n TZ6n VIM EPWM2/3/4/5/6TZINTn VIM EPWM2/3/4/5/6INTn EPWM2/3/4/5/6A TZ1/2/3n ADC Wrapper Mux Selector SOCA2/3/4/5/6 SOCB2/3/4/5/6 EQEP1 + EQEP2 EQEP1ERR / EQEP2ERR / EQEP1ERR or EQEP2ERR System Module OSC FAIL or PLL Slip VBus32 TZ4n VCLK4, SYS_nRST EPWM2/3/4/5/6ENCLK TZ5n Debug Mode Entry CPU EPWM 2/3/4/5/6 IOMUX EPWM2/3/4/5/6B TBCLKSYNC TZ6n VIM EPWM7TZINTn VIM EPWM7INTn EPWM7A EPWM7B ADC Wrapper EQEP1 + EQEP2 System Module Mux Selector EPWM 7 EQEP1ERR / EQEP2ERR / EQEP1ERR or EQEP2ERR OSC FAIL or PLL SLip VBus32 TZ4n VCLK4, SYS_nRST EPWM7ENCLK TBCLKSYNC TZ5n Debug Mode Entry CPU TZ1/2/3n SOCA7, SOCB7 TZ6n Pulse Stretch, EPWMSYNCO 8 VCLK4 cycles VBus32 / VBus32DP VIM ECAP1INTn ECAP 1 ECAP1 Figure 7-1. ePWMx Module Interconnections Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 111 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.1.1 www.ti.com ePWM Clocking and Reset Each ePWM module has a clock enable (EPWMxENCLK). When SYS_nRST is active low, the clock enables are ignored and the ePWM logic is clocked so that it can reset to a proper state. When SYS_nRST goes in-active high, the state of clock enable is respected. Table 7-1. ePWMx Clock Enable Control ePWM Module Instance Control Register to Enable Clock Default Value ePWM1 PINMMR37[8] 1 ePWM2 PINMMR37[16] 1 ePWM3 PINMMR37[24] 1 ePWM4 PINMMR38[0] 1 ePWM5 PINMMR38[8] 1 ePWM6 PINMMR38[16] 1 ePWM7 PINMMR38[24] 1 The default value of the control registers to enable the clocks to the ePWMx modules is 1. This means that the VCLK4 clock connections to the ePWMx modules are enabled by default. The application can choose to gate off the VCLK4 clock to any ePWMx module individually by clearing the respective control register bit. 7.1.2 Synchronization of ePWMx Time Base Counters A time-base synchronization scheme connects all of the ePWM modules on a device. Each ePWM module has a synchronization input (EPWMxSYNCI) and a synchronization output (EPWMxSYNCO). The input synchronization for the first instance (ePWM1) comes from an external pin. Figure 7-1 shows the synchronization connections for all the ePWMx modules. Each ePWM module can be configured to use or ignore the synchronization input. Refer to the ePWM chapter in the TMS570LS12x/11x Technical Reference Manual (SPNU515) for more information. 7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base The connection between the N2HET1_LOOP_SYNC and SYNCI input of ePWM1 module is implemented as shown in Figure 7-2. N2HET1 N2HET1_LOOP_SYNC EXT_LOOP_SYNC 2 VCLK4 cycles Pulse Strength SYNCI N2HET2 ePWM1 ePWM1_SYNCI ePWM1_SYNCI_SYNCED ePWM1_SYNCI_FILTERED PINMMR36[25] PINMMR47[8,9,10] Figure 7-2. Synchronizing Time Bases Between N2HET1, N2HET2 and ePWMx Modules 112 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 7.1.4 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM modules on a device. This bit is implemented as PINMMR37 register bit 1. When TBCLKSYNC = 0, the time-base clock of all ePWM modules is stopped. This is the default condition. When TBCLKSYNC = 1, all ePWM time-base clocks are started with the rising edge of TBCLK aligned. For perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each ePWM module must be set identically. The proper procedure for enabling the ePWM clocks is as follows: 1. Enable the individual ePWM module clocks (if disable) using the control registers shown in Table 7-1. 2. Configure TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module. 3. Configure the prescaler values and desired ePWM modes. 4. Configure TBCLKSYNC = 1. 7.1.5 ePWM Synchronization with External Devices The output sync from EPWM1 Module is also exported to a device output terminal so that multiple devices can be synchronized together. The signal pulse is stretched by eight VCLK4 cycles before being exported on the terminal as the EPWM1SYNCO signal. 7.1.6 ePWM Trip Zones The ePWMx modules have six trip zone inputs each. These are active-low signals. The application can control the ePWMx module response to each of the trip zone input separately. The timing requirements from the assertion of the trip zone inputs to the actual response are specified in Section 7.1.8. 7.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n These three trip zone inputs are driven by external circuits and are connected to device-level inputs. These signals are either connected asynchronously to the ePWMx trip zone inputs, or doublesynchronized with VCLK4, or double-synchronized and then filtered with a 6-cycle VCLK4-based counter before connecting to the ePWMx. By default, the trip zone inputs are asynchronously connected to the ePWMx modules. Table 7-2. Connection to ePWMx Modules for Device-Level Trip Zone Inputs Trip Zone Input Control for Asynchronous Connection to ePWMx Control for Double-Synchronized Connection to ePWMx Control for Double-Synchronized and Filtered Connection to ePWMx TZ1n PINMMR46[16] = 1 PINMMR46[16] = 0 AND PINMMR46[17] = 1 PINMMR46[16] = 0 AND PINMMR46[17] = 0 AND PINMMR46[18] = 1 TZ2n PINMMR46[24] = 1 PINMMR46[24] = 0 AND PINMMR46[25] = 1 PINMMR46[24] = 0 AND PINMMR46[25] = 0 AND PINMMR46[26] = 1 TZ3n PINMMR47[0] = 1 PINMMR47[0] = 0 AND PINMMR47[1] =1 PINMMR47[0] = 0 AND PINMMR47[1] = 0 AND PINMMR47[2] = 1 7.1.6.2 Trip Zone TZ4n This trip zone input is dedicated to eQEPx error indications. There are two eQEP modules on this device. Each eQEP module indicates a phase error by driving its EQEPxERR output High. The following control registers allow the application to configure the trip zone input (TZ4n) to each ePWMx module based on the application’s requirements. Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 113 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 7-3. TZ4n Connections for ePWMx Modules ePWMx Control for TZ4n = not(EQEP1ERR OR EQEP2ERR) Control for TZ4n = not(EQEP1ERR) Control for TZ4n = not(EQEP2ERR) ePWM1 PINMMR41[0] = 1 PINMMR41[0] = 0 AND PINMMR41[1] =1 PINMMR41[0] = 1 AND PINMMR41[1] = 0 AND PINMMR41[2] = 1 ePWM2 PINMMR41[8] PINMMR41[8] = 0 AND PINMMR41[9] =1 PINMMR41[8] = 1 AND PINMMR41[9] = 0 AND PINMMR41[10] = 1 ePWM3 PINMMR41[16] PINMMR41[16] = 0 AND PINMMR41[17] = 1 PINMMR41[16] = 1 AND PINMMR41[17] = 0 AND PINMMR41[18] = 1 ePWM4 PINMMR41[24] PINMMR41[24] = 0 AND PINMMR41[25] = 1 PINMMR41[24] = 1 AND PINMMR41[25] = 0 AND PINMMR41[26] = 1 ePWM5 PINMMR42[0] PINMMR42[0] = 0 AND PINMMR42[1] =1 PINMMR42[0] = 1 AND PINMMR42[1] = 0 AND PINMMR42[2] = 1 ePWM6 PINMMR42[8] PINMMR42[8] = 0 AND PINMMR42[9] =1 PINMMR42[8] = 1 AND PINMMR42[9] = 0 AND PINMMR42[10] = 1 ePWM7 PINMMR42[16] PINMMR42[16] = 0 AND PINMMR42[17] = 1 PINMMR42[16] = 1 AND PINMMR42[17] = 0 AND PINMMR42[18] = 1 7.1.6.3 Trip Zone TZ5n This trip zone input is dedicated to a clock failure on the device. That is, this trip zone input is asserted whenever an oscillator failure or a PLL slip is detected on the device. The application can use this trip zone input for each ePWMx module in order to prevent the external system from going out of control when the device clocks are not within expected range (system running at limp clock). The oscillator failure and PLL slip signals used for this trip zone input are taken from the status flags in the system module. These are level signals are set until cleared by the application. 7.1.6.4 Trip Zone TZ6n This trip zone input to the ePWMx modules is dedicated to a debug mode entry of the CPU. If enabled, the user can force the PWM outputs to a known state when the emulator stops the CPU. This prevents the external system from going out of control when the CPU is stopped. 7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs A special scheme is implemented in order to select the actual signal used for triggering the start of conversion on the two ADCs on this device. This scheme is defined in Section 7.4.2.3. 7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings Table 7-4. ePWMx Timing Requirements PARAMETER tw(SYNCIN) Synchronization input pulse width TEST CONDITIONS MIN Asynchronous 2 tc(VCLK4) MAX cycles UNIT Synchronous 2 tc(VCLK4) cycles Synchronous, with input filter 2 tc(VCLK4) + filter width cycles Table 7-5. ePWMx Switching Characteristics PARAMETER tw(PWM) TEST CONDITIONS Pulse duration, ePWMx output high or low tw(SYNCOUT Synchronization Output Pulse Width MIN MAX UNIT 33.33 ns 8 tc(VCLK4) cycles ) td(PWM)tza 114 Delay time, trip input active to PWM forced high, OR Delay time, trip input active to PWM forced low no pin load 25 ns Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 7-5. ePWMx Switching Characteristics (continued) PARAMETER td(TZ- TEST CONDITIONS MIN Delay time, trip input active to PWM Hi-Z MAX UNIT 20 ns MAX UNIT PWM)HZ Table 7-6. ePWMx Trip-Zone Timing Requirements PARAMETER tw(TZ) (1) Pulse duration, TZn input low TEST CONDITIONS MIN Asynchronous 2 * HSPCLKDIV * CLKDIV * tc(VCLK4) (1) ns Synchronous 2 tc(VCLK4) ns Synchronous, with input filter 8 tc(VCLK4) ns Refer to the ePWM chapter of the TMS570LS12x/11x Technical Reference Manual (SPNU515) for more information on the clock divider fields HSPCLKDIV and CLKDIV. Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 115 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.2 www.ti.com Enhanced Capture Modules (eCAP) Figure 7-3 shows how the eCAP modules are interconnected on this microcontroller. EPWM1SYNCO ECAP1SYNCI ECAP1 VIM ECAP1INTn ECAP1 VBus32 VCLK4, SYS_nRST ECAP1ENCLK ECAP1SYNCO ECAP2SYNCI VIM ECAP2INTn ECAP 2/3/4/5 IOMUX ECAP2 VBus32 VCLK4, SYS_nRST ECAP2SYNCO ECAP2ENCLK ECAP6 VIM ECAP6INTn ECAP 6 VBus32 VCLK4, SYS_nRST ECAP6ENCLK Figure 7-3. eCAP Module Connections 7.2.1 Clock Enable Control for eCAPx Modules Each of the ECAPx modules have a clock enable (ECAPxENCLK). These signals need to be generated from a device-level control register. When SYS_nRST is active low, the clock enables are ignored and the ECAPx logic is clocked so that it can reset to a proper state. When SYS_nRST goes in-active high, the state of clock enable is respected. 116 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 7-7. eCAPx Clock Enable Control ePWM Module Instance Control Register to Enable Clock Default Value eCAP1 PINMMR39[0] 1 eCAP2 PINMMR39[8] 1 eCAP3 PINMMR39[16] 1 eCAP4 PINMMR39[24] 1 eCAP5 PINMMR40[0] 1 eCAP6 PINMMR40[8] 1 The default value of the control registers to enable the clocks to the eCAPx modules is 1. This means that the VCLK4 clock connections to the eCAPx modules are enabled by default. The application can choose to gate off the VCLK4 clock to any eCAPx module individually by clearing the respective control register bit. 7.2.2 PWM Output Capability of eCAPx When not used in capture mode, each of the eCAPx modules can be used as a single-channel PWM output. This is called the auxiliary PWM (APWM) mode of operation of the eCAP modules. Refer to the eCAP chapter of the TMS570LS12x/11x Technical Reference Manual (SPNU515) for more information. 7.2.3 Input Connection to eCAPx Modules The input connection to each of the eCAP modules can be selected between a double-VCLK4synchronized input or a double-VCLK4-synchronized and filtered input, as shown in Table 7-8. Table 7-8. Device-Level Input Connection to eCAPx Modules Input Signal Control for Double-Synchronized Connection to eCAPx Control for Double-Synchronized and Filtered Connection to eCAPx eCAP1 PINMMR43[0] = 1 PINMMR43[0] = 0 AND PINMMR43[1] = 1 eCAP2 PINMMR43[8] = 1 PINMMR43[8] = 0 AND PINMMR43[9] = 1 eCAP3 PINMMR43[16] = 1 PINMMR43[16] = 0 AND PINMMR43[17] = 1 eCAP4 PINMMR43[24] = 1 PINMMR43[24] = 0 AND PINMMR43[25] = 1 eCAP5 PINMMR44[0] = 1 PINMMR44[0] = 0 AND PINMMR44[1] = 1 eCAP6 PINMMR44[8] = 1 PINMMR44[8] = 0 AND PINMMR44[9] = 1 7.2.4 Enhanced Capture Module (eCAP) Timings Table 7-9. eCAPx Timing Requirements PARAMETER tw(CAP) Capture input pulse width TEST CONDITIONS MIN Synchronous 2 tc(VCLK4) MAX cycles UNIT Synchronous, with input filter 2 tc(VCLK4) + filter width cycles Table 7-10. eCAPx Switching Characteristics PARAMETER tw(APWM) TEST CONDITIONS Pulse duration, APWMx output high or low Copyright © 2012–2015, Texas Instruments Incorporated MIN MAX UNIT 20 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 ns 117 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.3 www.ti.com Enhanced Quadrature Encoder (eQEP) Figure 7-4 shows the eQEP module interconnections on the device. VBus32 EQEP1A EQEP1B EQEP1ENCLK VCLK4 SYS_nRST EPWM1/../7 VIM EQEP1INTn EQEP1 Module EQEP1ERR EQEP1I EQEP1IO EQEP1IOE TZ4n EQEP1S EQEP1SO EQEP1SOE IO Mux VBus32 EQEP2A EQEP2B EQEP2ENCLK VCLK4 SYS_nRST VIM Connection Selection Mux EQEP2INTn EQEP2 Module EQEP2ERR EQEP2I EQEP2IO EQEP2IOE EQEP2S EQEP2SO EQEP2SOE Figure 7-4. eQEP Module Interconnections 7.3.1 Clock Enable Control for eQEPx Modules Device-level control registers are implemented to generate the EQEPxENCLK signals. When SYS_nRST is active low, the clock enables are ignored and the eQEPx logic is clocked so that it can reset to a proper state. When SYS_nRST goes in-active high, the state of clock enable is respected. Table 7-11. eQEPx Clock Enable Control ePWM Module Instance Control Register to Enable Clock Default Value eQEP1 PINMMR40[16] 1 eQEP2 PINMMR40[24] 1 The default value of the control registers to enable the clocks to the eQEPx modules is 1. This means that the VCLK4 clock connections to the eQEPx modules are enabled by default. The application can choose to gate off the VCLK4 clock to any eQEPx module individually by clearing the respective control register bit. 7.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs The eQEP module sets the EQEPERR signal output whenever a phase error is detected in its inputs EQEPxA and EQEPxB. This error signal from both the eQEP modules is input to the connection selection multiplexor. This multiplexor is defined in Table 7-3. As shown in Figure 7-1, the output of this selection multiplexor is inverted and connected to the TZ4n trip-zone input of all EPWMx modules. This connection allows the application to define the response of each ePWMx module on a phase error indicated by the eQEP modules. 7.3.3 Input Connections to eQEPx Modules The input connections to each of the eQEP modules can be selected between a double-VCLK4synchronized input or a double-VCLK4-synchronized and filtered input, as shown in Table 7-12. 118 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 7-12. Device-Level Input Connection to eCAPx Modules Input Signal Control for Double-Synchronized Connection to eQEPx Control for Double-Synchronized and Filtered Connection to eQEPx eQEP1A PINMMR44[16] = 1 PINMMR44[16] = 0 and PINMMR44[17] = 1 eQEP1B PINMMR44[24] = 1 PINMMR44[24] = 0 and PINMMR44[25] = 1 PINMMR45[0] = 0 and PINMMR45[1] = 1 eQEP1I PINMMR45[0] = 1 eQEP1S PINMMR45[8] = 1 PINMMR45[8] = 0 and PINMMR45[9] = 1 eQEP2A PINMMR45[16] = 1 PINMMR45[16] = 0 and PINMMR45[17] = 1 eQEP2B PINMMR45[24] = 1 PINMMR45[24] = 0 and PINMMR45[25] = 1 eQEP2I PINMMR46[0] = 1 PINMMR46[0] = 0 and PINMMR46[1] = 1 eQEP2S PINMMR46[8] = 1 PINMMR46[8] = 0 and PINMMR46[9] = 1 7.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing Table 7-13. eQEPx Timing Requirements PARAMETER tw(QEPP) tw(INDEXH) tw(INDEXL) tw(STROBH) tw(STROBL) TEST CONDITIONS MIN Synchronous 2 tc(VCLK4) cycles Synchronous, with input filter 2 tc(VCLK4) + filter width cycles Synchronous 2 tc(VCLK4) cycles Synchronous, with input filter 2 tc(VCLK4) + filter width cycles Synchronous 2 tc(VCLK4) cycles Synchronous, with input filter 2 tc(VCLK4) + filter width cycles QEP input period QEP Index Input High Time QEP Index Input Low Time QEP Strobe Input High Time MAX UNIT Synchronous 2 tc(VCLK4) cycles Synchronous, with input filter 2 tc(VCLK4) + filter width cycles Synchronous 2 tc(VCLK4) cycles Synchronous, with input filter 2 tc(VCLK4) + filter width cycles QEP Strobe Input Low Time Table 7-14. eQEPx Switching Characteristics MAX UNIT td(CNTR)xin Delay time, external clock to counter increment PARAMETER 4 tc(VCLK4) cycles td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 6 tc(VCLK4) cycles 7.4 MIN Multibuffered 12bit Analog-to-Digital Converter The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to ADREFLO unless otherwise noted. Table 7-15. MibADC Overview Description Value Resolution 12 bits Monotonic Assured Output conversion code 00h to 3FFh [00 for VAI ≤ ADREFLO; 3FFh for VAI ≥ ADREFHI] Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 119 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.4.1 www.ti.com Features • • • • • • • • • • • • • • 12-bit resolution ADREFHI and ADREFLO pins (high and low reference voltages) Total Sample/Hold/Convert time: 600ns Minimum at 30MHz ADCLK One memory region per conversion group is available (event, group 1, group 2) Allocation of channels to conversion groups is completely programmable Supports flexible channel conversion order Memory regions are serviced either by interrupt or by DMA Programmable interrupt threshold counter is available for each group Programmable magnitude threshold interrupt for each group for any one channel Option to read either 8-bit, 10-bit or 12-bit values from memory regions Single or continuous conversion modes Embedded self-test Embedded calibration logic Enhanced power-down mode – Optional feature to automatically power down ADC core when no conversion is in progress External event pin (ADxEVT) programmable as general-purpose I/O • 7.4.2 Event Trigger Options The ADC module supports 3 conversion groups: Event Group, Group1 and Group2. Each of these 3 groups can be configured to be hardware event-triggered. In that case, the application can select from among 8 event sources to be the trigger for a group's conversions. 7.4.2.1 MIBADC1 Event Trigger Hookup Table 7-16. MIBADC1 Event Trigger Hookup Trigger Event Signal Group Source Select, G1SRC, G2SRC or EVSRC Event # 000 1 120 PINMMR30[0] = 0 and PINMMR30[1] = 1 PINMMR30[0] = 1 (default) Option A Control for Option A Option B AD1EVT AD1EVT — AD1EVT — PINMMR30[8] = 0 and PINMMR30[9] = 1 Control for Option B 001 2 N2HET1[8] N2HET2[5] PINMMR30[8] = 1 ePWM_B 010 3 N2HET1[10] N2HET1[27] — N2HET1[27] — 011 4 RTI Compare 0 Interrupt RTI Compare 0 Interrupt PINMMR30[16] = 1 ePWM_A1 PINMMR30[16] = 0 and PINMMR30[17] = 1 100 5 N2HET1[12] N2HET1[17] — N2HET1[17] — 101 6 N2HET1[14] N2HET1[19] PINMMR30[24] = 1 N2HET2[1] PINMMR30[24] = 0 and PINMMR30[25] = 1 110 7 GIOB[0] N2HET1[11] PINMMR31[0] = 1 ePWM_A2 PINMMR31[0] = 0 and PINMMR31[1] = 1 111 8 GIOB[1] N2HET2[13] PINMMR32[16] = 1 ePWM_AB PINMMR31[8] = 0 and PINMMR31[9] = 1 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 NOTE If ADEVT, N2HET1 or GIOB is used as a trigger source, the connection to the MibADC1 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring the function as output onto the pad (through the mux control), or by driving the function from an external trigger source as input. If the mux control module is used to select different functionality instead of the ADEVT, N2HET1[x] or GIOB[x] signals, then care must be taken to disable these signals from triggering conversions; there is no multiplexing on the input connections. If ePWM_B, ePWM_S2, ePWM_AB, N2HET2[1], N2HET2[5], N2HET2[13], N2HET1[11], N2HET1[17] or N2HET1[19] is used to trigger the ADC the connection to the ADC is made directly from the N2HET or ePWM module outputs. As a result, the ADC can be triggered without having to enable the signal from being output on a device terminal. NOTE For the RTI compare 0 interrupt source, the connection is made directly from the output of the RTI module. That is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the CPU. 7.4.2.2 MIBADC2 Event Trigger Hookup Table 7-17. MIBADC2 Event Trigger Hookup Trigger Event Signal Group Source Select, G1SRC, G2SRC or EVSRC Event # 000 1 PINMMR30[0] = 0 and PINMMR30[1] = 1 PINMMR30[0] = 1 (default) Option A Control for Option A Option B AD2EVT AD2EVT — AD2EVT — Control for Option B 001 2 N2HET1[8] N2HET2[5] PINMMR31[16] = 1 ePWM_B PINMMR31[16] = 0 and PINMMR31[17] = 1 010 3 N2HET1[10] N2HET1[27] — N2HET1[27] — 011 4 RTI Compare 0 Interrupt RTI Compare 0 Interrupt PINMMR31[24] = 1 ePWM_A1 PINMMR31[24] = 0 and PINMMR31[25] = 1 100 5 N2HET1[12] N2HET1[17] — N2HET1[17] — 101 6 N2HET1[14] N2HET1[19] PINMMR32[0] = 1 N2HET2[1] PINMMR32[0] = 0 and PINMMR32[1] = 1 110 7 GIOB[0] N2HET1[11] PINMMR32[8] = 1 ePWM_A2 PINMMR32[8] = 0 and PINMMR32[9] = 1 111 8 GIOB[1] N2HET2[13] PINMMR32[16] = 1 ePWM_AB PINMMR32[16] = 0 and PINMMR32[17] = 1 Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 121 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com NOTE If AD2EVT, N2HET1 or GIOB is used as a trigger source, the connection to the MibADC2 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring the function as output onto the pad (through the mux control), or by driving the function from an external trigger source as input. If the mux control module is used to select different functionality instead of the AD2EVT, N2HET1[x] or GIOB[x] signals, then care must be taken to disable these signals from triggering conversions; there is no multiplexing on the input connections. If ePWM_B, ePWM_S2, ePWM_AB, N2HET2[5], N2HET2[1], N2HET2[13], N2HET1[11], N2HET1[17] or N2HET1[19] is used to trigger the ADC the connection to the ADC is made directly from the N2HET or ePWM module outputs. As a result, the ADC can be triggered without having to enable the signal from being output on a device terminal. NOTE For the RTI compare 0 interrupt source, the connection is made directly from the output of the RTI module. That is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the CPU. 7.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules As shown in Figure 7-5, the ePWMxSOCA and ePWMxSOCB outputs from each ePWM module are used to generate 4 signals – ePWM_B, ePWM_A1, ePWM_A2 and ePWM_AB, that are available to trigger the ADC based on the application requirement. 122 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 SOCAEN, SOCBEN bits inside ePWMx modules Controlled by PINMMR EPWM1SOCA EPWM1 module EPWM1SOCB EPWM2SOCA EPWM2 module EPWM2SOCB EPWM3SOCA EPWM3 module EPWM3SOCB EPWM4SOCA EPWM4 module EPWM4SOCB EPWM5SOCA EPWM5 module EPWM5SOCB EPWM6SOCA EPWM6 module EPWM6SOCB EPWM7SOCA EPWM7 module EPWM7SOCB ePWM_B ePWM_A1 ePWM_A2 ePWM_AB Figure 7-5. ADC Trigger Source Generation from ePWMx Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 123 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 7-18. Control Bit to SOC Output Control Bit SOC Output PINMMR35[0] SOC1A_SEL PINMMR35[8] SOC2A_SEL PINMMR35[16] SOC3A_SEL PINMMR35[24] SOC4A_SEL PINMMR36[0] SOC5A_SEL PINMMR36[8] SOC6A_SEL PINMMR36[16] SOC7A_SEL The SOCA output from each ePWM module is connected to a "switch" shown in Figure 7-5. The logic equations for the 4 outputs from the combinational logic shown in Figure 7-5 are: ePWM_ SOC1B or SOC2B or SOC3B or SOC4B or SOC5B or SOC6B or SOC7B B= ePWM_ [ SOC1A and not(SOC1A_SEL) ] or [ SOC2A and not(SOC2A_SEL) ] or [ SOC3A and not(SOC3A_SEL) ] or A1 = [ SOC4A and not(SOC4A_SEL) ] or [ SOC5A and not(SOC5A_SEL) ] or [ SOC6A and not(SOC6A_SEL) ] or [ SOC7A and not(SOC7A_SEL) ] ePWM_ [ SOC1A and SOC1A_SEL ] or [ SOC2A and SOC2A_SEL ] or [ SOC3A and SOC3A_SEL ] or A2 = [ SOC4A and SOC4A_SEL ] or [ SOC5A and SOC5A_SEL ] or [ SOC6A and SOC6A_SEL ] or [ SOC7A and SOC7A_SEL ] ePWM_ ePWM_B or ePWM_A2 AB = 124 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 7.4.3 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 ADC Electrical and Timing Specifications Table 7-19. MibADC Recommended Operating Conditions Parameter MIN MAX Unit (1) V V ADREFHI A-to-D high-voltage reference source ADREFLO VCCAD ADREFLO A-to-D low-voltage reference source VSSAD (1) ADREFHI VAI Analog input voltage ADREFLO ADREFHI V IAIK Analog input clamp current (2) (VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3) -2 2 mA (1) (2) For VCCAD and VSSAD recommended operating conditions, see Section 5.4. Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels. Table 7-20. MibADC Electrical Characteristics Over Full Ranges of Recommended Operating Conditions Parameter MAX Unit Rmux Analog input mux onresistance See Figure 7-6 250 Ω Rsamp ADC sample switch onresistance See Figure 7-6 250 Ω Cmux Input mux capacitance See Figure 7-6 16 pF Csamp ADC sample capacitance See Figure 7-6 13 pF IAIL Analog off-state input leakage current VCCAD = 3.6V maximum IAIL Description/Conditions Analog off-state input leakage current IAOSB1 (1) IAOSB2 (1) IAOSB1 (1) IAOSB2 (1) ADC1 Analog on-state input bias current ADC2 Analog on-state input bias current ADC1 Analog on-state input bias current VCCAD = 5.5V maximum VCCAD = 3.6V maximum VCCAD = 3.6V maximum VCCAD = 5.5V maximum MIN Nom VSSAD ≤ VIN < VSSAD + 100mV -300 200 nA VSSAD + 100mV ≤ VIN ≤ VCCAD - 200mV -200 200 nA VCCAD - 200mV < VIN ≤ VCCAD -200 500 nA VSSAD ≤ VIN < VSSAD + 300mV -1000 250 nA VSSAD + 300mV ≤ VIN ≤ VCCAD - 300mV -250 250 nA VCCAD - 300mV < VIN ≤ VCCAD -250 1000 nA VSSAD ≤ VIN < VSSAD + 100mV -8 2 µA VSSAD + 100mV < VIN < VCCAD - 200mV -4 2 µA VCCAD - 200mV < VIN < VCCAD -4 12 µA VSSAD ≤ VIN < VSSAD + 100mV -7 2 µA VSSAD + 100mV ≤ VIN ≤ VCCAD - 200mV -4 2 µA VCCAD - 200mV < VIN ≤ VCCAD -4 10 µA VSSAD ≤ VIN < VSSAD + 300mV -10 3 µA VSSAD + 300mV ≤ VIN ≤ VCCAD - 300mV -5 3 µA VCCAD - 300mV < VIN ≤ VCCAD -5 14 µA VSSAD ≤ VIN < VSSAD + 300mV -8 3 µA VSSAD + 300mV ≤ VIN ≤ VCCAD - 300mV -5 3 µA VCCAD - 300mV < VIN ≤ VCCAD -5 ADC2 Analog on-state input bias current VCCAD = 5.5V maximum 12 µA IADREFHI ADREFHI input current ADREFHI = VCCAD, ADREFLO = VSSAD 3 mA ICCAD Static supply current Normal operating mode 15 mA ADC core in power down mode 5 µA (1) If a shared channel is being converted by both ADC converters at the same time, the on-state leakage is equal to IAOSB1 + IAOSB2 Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 125 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Rext Pin VS1 www.ti.com Smux Rmux Smux Rmux IAOSB Cext On-State Bias Current Rext Pin VS2 IAIL Cext IAIL IAIL Off-State Leakages Rext Pin Smux Rmux Ssamp Rsamp VS24 IAIL Csamp Cmux Cext IAIL IAIL Figure 7-6. MibADC Input Equivalent Circuit Table 7-21. MibADC Timing Specifications Parameter tc(ADCLK) (1) td(SH) (2) MIN Cycle time, MibADC clock Delay time, sample and hold time NOM MAX Unit 0.033 µs 0.2 µs 1 µs td(PU-ADV) Delay time from ADC power on until first input can be sampled td©) Delay time, conversion time 0.4 µs td(SHC) (3) Delay time, total sample/hold and conversion time 0.6 µs td©) Delay time, conversion time 0.33 µs td(SHC) (3) Delay time, total sample/hold and conversion time 0.53 µs 12-bit mode 10-bit mode (1) (2) (3) 126 The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits 4:0. The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the ADSAMP register for each conversion group. The sample time needs to be determined by accounting for the external impedance connected to the input channel as well as the ADC’s internal impedance. This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, for example, the prescale settings. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Table 7-22. MibADC Operating Characteristics Over Full Ranges of Recommended Operating Conditions (1) (2) Parameter Description/Conditions CR Conversion range over ADREFHI - ADREFLO which specified accuracy is maintained ZSET Zero Scale Offset FSET EDNL EINL Differential nonlinearity error Integral nonlinearity error ETOT (1) (2) Full Scale Offset Total unadjusted error MIN 3 Type MAX Unit 5.5 V Difference between the first ideal transition (from code 000h to 001h) and the actual transition 10-bit mode 1 LSB 12-bit mode 2 LSB Difference between the range of the measured code transitions (from first to last) and the range of the ideal code transitions 10-bit mode 2 LSB 12-bit mode 3 LSB Difference between the actual step width and the ideal value. (See Figure 7-7) 10-bit mode ± 1.5 LSB 12-bit mode ±2 LSB Maximum deviation from the best straight line 10-bit through the MibADC. MibADC transfer mode characteristics, excluding the quantization 12-bit error. mode ±2 LSB ±2 LSB Maximum value of the difference between an analog value and the ideal midstep value. 10-bit mode ±2 LSB 12-bit mode ±4 LSB 1 LSB = (ADREFHI – ADREFLO)/ 212 for 12-bit mode 1 LSB = (ADREFHI – ADREFLO)/ 210 for 10-bit mode Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 127 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.4.4 www.ti.com Performance (Accuracy) Specifications 7.4.4.1 MibADC Nonlinearity Errors The differential nonlinearity error shown in Figure 7-7 (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of 1 LSB. 0 ... 110 Digital Output Code 0 ... 101 0 ... 100 0 ... 011 Differential Linearity Error (–½ LSB) 1 LSB 0 ... 010 Differential Linearity Error (–½ LSB) 0 ... 001 1 LSB 0 ... 000 0 1 3 4 2 Analog Input Value (LSB) 5 12 NOTE A: 1 LSB = (ADREFHI – ADREFLO)/2 Figure 7-7. Differential Nonlinearity (DNL) Error 128 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 The integral nonlinearity error shown in Figure 7-8 (sometimes referred to as linearity error) is the deviation of the values on the actual transfer function from a straight line. 0 ... 111 0 ... 110 Ideal Transition Digital Output Code 0 ... 101 Actual Transition 0 ... 100 At Transition 011/100 (–½ LSB) 0 ... 011 0 ... 010 End-Point Lin. Error 0 ... 001 At Transition 001/010 (–1/4 LSB) 0 ... 000 0 1 2 3 4 5 6 7 Analog Input Value (LSB) 12 NOTE A: 1 LSB = (ADREFHI – ADREFLO)/2 Figure 7-8. Integral Nonlinearity (INL) Error Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 129 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.4.4.2 www.ti.com MibADC Total Error The absolute accuracy or total error of an MibADC as shown in Figure 7-9 is the maximum value of the difference between an analog value and the ideal midstep value. 0 ... 111 0 ... 110 Digital Output Code 0 ... 101 0 ... 100 Total Error At Step 0 ... 101 (–1 1/4 LSB) 0 ... 011 0 ... 010 Total Error At Step 0 ... 001 (1/2 LSB) 0 ... 001 0 ... 000 0 1 2 3 4 5 6 7 Analog Input Value (LSB) 12 NOTE A: 1 LSB = (ADREFHI – ADREFLO)/2 Figure 7-9. Absolute Accuracy (Total) Error 130 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 7.5 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 General-Purpose Input/Output The GPIO module on this device supports two ports, GIOA and GIOB. The I/O pins are bidirectional and bit-programmable. Both GIOA and GIOB support external interrupt capability. 7.5.1 Features The GPIO module has the following features: • Each IO pin can be configured as: – Input – Output – Open Drain • The interrupts have the following characteristics: – Programmable interrupt detection either on both edges or on a single edge (set in GIOINTDET) – Programmable edge-detection polarity, either rising or falling edge (set in GIOPOL register) – Individual interrupt flags (set in GIOFLG register) – Individual interrupt enables, set and cleared through GIOENASET and GIOENACLR registers respectively – Programmable interrupt priority, set through GIOLVLSET and GIOLVLCLR registers • Internal pullup/pulldown allows unused I/O pins to be left unconnected For information on input and output timings see Section 5.11 and Section 5.12 Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 131 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.6 www.ti.com Enhanced High-End Timer (N2HET) The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs, capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. 7.6.1 Features The N2HET module has the following features: • Programmable timer for input and output timing functions • Reduced instruction set (30 instructions) for dedicated time and angle functions • 160 words of instruction RAM protected by parity • User defined number of 25-bit virtual counters for timer, event counters and angle counters • 7-bit hardware counters for each pin allow up to 32-bit resolution in conjunction with the 25-bit virtual counters • Up to 32 pins usable for input signal measurements or output signal generation • Programmable suppression filter for each input pin with adjustable limiting frequency • Low CPU overhead and interrupt load • Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU) or DMA • Diagnostic capabilities with different loopback mechanisms and pin status read back functionality 7.6.2 N2HET RAM Organization The timer RAM uses 4 RAM banks, where each bank has two port access capability. This means that one RAM address may be written while another address is read. The RAM words are 96-bits wide, which are split into three 32-bit fields (program, control, and data). 132 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 7.6.3 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Input Timing Specifications All of the N2HET channels have an enhanced pulse capture circuit. The N2HET instructions PCNT and WCAP use this circuit to achieve the input timing requirements shown in Figure 7-10 and Table 7-23 below. 1 N2HETx 3 4 2 Figure 7-10. N2HET Input Capture Timings Table 7-23. Input Timing Requirements for N2HET Channels with Enhanced Pulse Capture PARAMETER 1, 2 MIN 25 MAX UNIT Input signal period, PCNT or WCAP (HRP) (LRP) tc(VCLK2) + 2 2 (HRP) (LRP) tc(VCLK2) - 2 ns 3 Input signal high phase, PCNT or WCAP 2 (HRP) tc(VCLK2) + 2 225 (HRP) (LRP) tc(VCLK2) - 2 ns 4 Input signal low phase, PCNT or WCAP 2 (HRP) tc(VCLK2) + 2 225 (HRP) (LRP) tc(VCLK2) - 2 ns 7.6.4 N2HET1-N2HET2 Synchronization In some applications the N2HET resolutions must be synchronized. Some other applications require a single time base to be used for all PWM outputs and input timing captures. The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures the N2HET in master or slave mode (default is slave mode). A N2HET in master mode provides a signal to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to the loop resolution signal sent by the master. The slave does not require this signal after it receives the first synchronization signal. However, anytime the slave receives the re-synchronization signal from the master, the slave must synchronize itself again.. N2HET1 N2HET2 EXT_LOOP_SYNC NHET_LOOP_SYNC NHET_LOOP_SYNC EXT_LOOP_SYNC Figure 7-11. N2HET1 – N2HET2 Synchronization Hookup 7.6.5 N2HET Checking 7.6.5.1 Internal Monitoring To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be used to monitor each other’s signals as shown in Figure 7-12. The direction of the monitoring is controlled by the I/O multiplexing control module. Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 133 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 N2HET1[1,3,5,7,9,11] www.ti.com IOMM mux control signal x N2HET1[1,3,5,7,9,11] / N2HET2[8,10,12,14,16,18] N2HET1 N2HET2[8,10,12,14,16,18] N2HET2 Figure 7-12. N2HET Monitoring 7.6.5.2 Output Monitoring using Dual Clock Comparator (DCC) N2HET1[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure the frequency of the pulse-width modulated (PWM) signal on N2HET1[31]. Similarly, N2HET2[0] is connected as a clock source for counter 1 in DCC2. This allows the application to measure the frequency of the pulse-width modulated (PWM) signal on N2HET2[0]. Both N2HET1[31] and N2HET2[0] can be configured to be internal-only channels. That is, the connection to the DCC module is made directly from the output of the N2HETx module (from the input of the output buffer). For more information on DCC see Section 6.7.3. 7.6.6 Disabling N2HET Outputs Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET module provides this capability through the "Pin Disable" input signal. This signal, when driven low, causes the N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated. For more details on the "N2HET Pin Disable" feature, see the device-specific Terminal Reference Manual. GIOA[5] is connected to the "Pin Disable" input for N2HET1, and GIOB[2] is connected to the "Pin Disable" input for N2HET2. 134 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 7.6.7 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 High-End Timer Transfer Unit (HTU) A High End Timer Transfer Unit (HTU) can perform DMA type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU. 7.6.7.1 • • • • • • • • • 7.6.7.2 Features CPU and DMA independent Master Port to access system memory 8 control packets supporting dual buffer configuration Control packet information is stored in RAM protected by parity Event synchronization (HET transfer requests) Supports 32 or 64 bit transactions Addressing modes for HET address (8 byte or 16 byte) and system memory address (fixed, 32 bit or 64bit) One shot, circular and auto switch buffer transfer modes Request lost detection Trigger Connections Table 7-24. HTU1 Request Line Connection Modules Request Source HTU1 Request N2HET1 HTUREQ[0] HTU1 DCP[0] N2HET1 HTUREQ[1] HTU1 DCP[1] N2HET1 HTUREQ[2] HTU1 DCP[2] N2HET1 HTUREQ[3] HTU1 DCP[3] N2HET1 HTUREQ[4] HTU1 DCP[4] N2HET1 HTUREQ[5] HTU1 DCP[5] N2HET1 HTUREQ[6] HTU1 DCP[6] N2HET1 HTUREQ[7] HTU1 DCP[7] Table 7-25. HET TU2 Request Line Connection Modules Request Source HET TU2 Request N2HET2 HTUREQ[0] HTU2 DCP[0] N2HET2 HTUREQ[1] HTU2 DCP[1] N2HET2 HTUREQ[2] HTU2 DCP[2] N2HET2 HTUREQ[3] HTU2 DCP[3] N2HET2 HTUREQ[4] HTU2 DCP[4] N2HET2 HTUREQ[5] HTU2 DCP[5] N2HET2 HTUREQ[6] HTU2 DCP[6] N2HET2 HTUREQ[7] HTU2 DCP[7] Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 135 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.7 www.ti.com Controller Area Network (DCAN) The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and harsh environments (for example, automotive and industrial fields) that require reliable serial communication or multiplexed wiring. 7.7.1 Features Features of the DCAN module include: • Supports CAN protocol version 2.0 part A, B • Bit rates up to 1 MBit/s • The CAN kernel can be clocked by the oscillator for baud-rate generation. • 64 mailboxes on each DCAN • Individual identifier mask for each message object • Programmable FIFO mode for message objects • Programmable loop-back modes for self-test operation • Automatic bus on after Bus-Off state by a programmable 32-bit timer • Message RAM protected by parity • Direct access to Message RAM during test mode • CAN Rx / Tx pins configurable as general purpose IO pins • Message RAM Auto Initialization • DMA support For more information on the DCAN see the TMS570LS12x/11x Technical Reference Manual (SPNU515). 7.7.2 Electrical and Timing Specifications Table 7-26. Dynamic Characteristics for the DCANx TX and RX pins MAX Unit td(CANnTX) Delay time, transmit shift register to CANnTX pin (1) Parameter 15 ns td(CANnRX) Delay time, CANnRX pin to receive shift register 5 ns (1) 136 MIN These values do not include rise/fall times of the output buffer. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 7.8 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Local Interconnect Network Interface (LIN) The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is an SCI. The SCI’s hardware features are augmented to achieve LIN compatibility. The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a Kline. The LIN standard is based on the SCI (UART) serial data link format. The communication concept is single-master/multiple-slave with a message identification for multi-cast transmission between any network nodes. 7.8.1 LIN Features The following are features of the LIN module: • Compatible to LIN 1.3, 2.0 and 2.1 protocols • Multibuffered receive and transmit units DMA capability for minimal CPU intervention • Identification masks for message filtering • Automatic Master Header Generation – Programmable Synch Break Field – Synch Field – Identifier Field • Slave Automatic Synchronization – Synch break detection – Optional baudrate update – Synchronization Validation • 231 programmable transmission rates with 7 fractional bits • Error detection • 2 Interrupt lines with priority encoding Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 137 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.9 Serial Communication Interface (SCI) 7.9.1 Features • • • • • • • • • • • 138 www.ti.com Standard universal asynchronous receiver-transmitter (UART) communication Supports full- or half-duplex operation Standard nonreturn to zero (NRZ) format Double-buffered receive and transmit functions Configurable frame format of 3 to 13 bits per character based on the following: – Data word length programmable from one to eight bits – Additional address bit in address-bit mode – Parity programmable for zero or one parity bit, odd or even parity – Stop programmable for one or two stop bits Asynchronous or isosynchronous communication modes Two multiprocessor communication formats allow communication between more than two devices. Sleep mode is available to free CPU resources during multiprocessor communication. The 24-bit programmable baud rate supports 224 different baud rates provide high accuracy baud rate selection. Four error flags and Five status flags provide detailed information regarding SCI events. Capability to use DMA for transmit and receive data. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.10 Inter-Integrated Circuit (I2C) The inter-integrated circuit (I2C) module is a multi-master communication module providing an interface between the RM4x microcontroller and devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an I2C-bus. This module will support any slave or master I2C compatible device. 7.10.1 Features The I2C has the following features: • Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number 9398 393 40011) – Bit/Byte format transfer – 7-bit and 10-bit device addressing modes – General call – START byte – Multi-master transmitter/ slave receiver mode – Multi-master receiver/ slave transmitter mode – Combined master transmit/receive and receive/transmit mode – Transfer rates of 10 kbps up to 400 kbps (Phillips fast-mode rate) • Free data format • Two DMA events (transmit and receive) • DMA event enable/disable capability • Seven interrupts that can be used by the CPU • Module enable/disable capability • The SDA and SCL are optionally configurable as general purpose I/O • Slew rate control of the outputs • Open drain control of the outputs • Programmable pullup/pulldown capability on the inputs • Supports Ignore NACK mode NOTE This I2C module does not support: • High-speed (HS) mode • C-bus compatibility mode • The combined format in 10-bit address mode (the I2C sends the slave address second byte every time it sends the slave address first byte) Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 139 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 7.10.2 I2C I/O Timing Specifications Table 7-27. I2C Signals (SDA and SCL) Switching Characteristics (1) Parameter Standard Mode Fast Mode Unit MIN MAX MIN MAX 75.2 149 75.2 149 ns 0 100 0 400 kHz tc(I2CCLK) Cycle time, Internal Module clock for I2C, prescaled from VCLK f(SCL) SCL Clock frequency tc(SCL) Cycle time, SCL 10 2.5 µs tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 µs th(SCLL-SDAL) Hold time, SCL low after SDA low (for a repeated START condition) 4 0.6 µs tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs tw(SCLH) Pulse duration, SCL high 4 0.6 µs tsu(SDA-SCLH) Setup time, SDA valid before SCL high th(SDA-SCLL) Hold time, SDA valid after SCL low (for I2C bus devices) tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4.0 0.6 µs tw(SP) Pulse duration, spike (must be suppressed) Cb (3) Capacitive load for each bus line (1) (2) (3) 250 100 3.45 (2) 0 ns 0 0.9 0 400 µs 50 ns 400 pF The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL signal. Cb = The total capacitance of one bus line in pF. SDA tw(SDAH) tsu(SDA-SCLH) tw(SCLL) tw(SP) tsu(SCLH-SDAH) tw(SCLH) tr(SCL) SCL tc(SCL) tf(SCL) th(SCLL-SDAL) th(SDA-SCLL) tsu(SCLH-SDAL) th(SCLL-SDAL) Stop Start Repeated Start Stop Figure 7-13. I2C Timings 140 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 NOTE • • • • A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL signal. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH). Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster falltimes are allowed. Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 141 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 7.11 Multibuffered / Standard Serial Peripheral Interface The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate. Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display drivers, and analog-to-digital converters. 7.11.1 Features Both Standard and MibSPI modules have the following features: • 16-bit shift register • Receive buffer register • 8-bit baud clock generator • SPICLK can be internally-generated (master mode) or received from an external clock source (slave mode) • Each word transferred can have a unique format • SPI I/Os not used in the communication can be used as digital input/output signals Table 7-28. MibSPI/SPI Configurations PGE Package MibSPIx/SPIx I/Os MibSPI1 MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:4,2:0], MIBSPI1nENA MibSPI3 MIBSPI3SIMO[0], MIBSPI3SOMI[0], MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA MibSPI5 MIBSPI5SIMO[0], MIBSPI5SOMI[2:0], MIBSPI5CLK, MIBSPI5nCS[0], MIBSPI5nENA SPI4 SPI4SIMO[0], SPI4SOMI[0], SPI4CLK, SPI4nCS[0], SPI4nENA Table 7-29. MibSPI/SPI Configurations ZWT Package MibSPIx/SPIx I/Os MibSPI1 MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:0], MIBSPI1nENA MibSPI3 MIBSPI3SIMO[0], MIBSPI3SOMI[0], MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA MibSPI5 MIBSPI5SIMO[3:0], MIBSPI5SOMI[3:0], MIBSPI5CLK, MIBSPI5nCS[3:0], MIBSPI5nENA SPI2 SPI2SIMO[0], SPI2SOMI[0], SPI2CLK, SPI2nCS[1:0], SPI2nENA SPI4 SPI4SIMO[0], SPI4SOMI[0], SPI4CLK, SPI4nCS[0], SPI4nENA 7.11.2 MibSPI Transmit and Receive RAM Organization The Multibuffer RAM is comprised of 128 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a 16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer RAM can be partitioned into multiple transfer group with variable number of buffers each. Each MibSPIx module supports 8 transfer groups. 7.11.3 MibSPI Transmit Trigger Events Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event and a trigger source can be chosen. A trigger event can be for example a rising edge or a permanent low level at a selectable trigger source. For example, up to 15 trigger sources are available for use by each transfer group. These trigger options are listed in Table 7-30 and Section 7.11.3.2 for MibSPI1 and MibSPi3 respectively. 142 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 7.11.3.1 MIBSPI1 Event Trigger Hookup Table 7-30. MIBSPI1 Event Trigger Hookup Event # TGxCTRL TRIGSRC[3:0] Trigger Disabled 0000 No trigger source EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 N2HET1[8] EVENT9 1010 N2HET1[10] EVENT10 1011 N2HET1[12] EVENT11 1100 N2HET1[14] EVENT12 1101 N2HET1[16] EVENT13 1110 N2HET1[18] EVENT14 1111 Internal Tick counter NOTE For N2HET1 trigger sources, the connection to the MibSPI1 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary). This way, a trigger condition can be generated even if the N2HET1 signal is not selected to be output on the pad. NOTE For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving the GIOx pin from an external trigger source. If the mux control module is used to select different functionality instead of the GIOx signal, then care must be taken to disable GIOx from triggering MibSPI1 transfers; there is no multiplexing on the input connections. 7.11.3.2 MIBSPI3 Event Trigger Hookup Table 7-31. MIBSPI3 Event Trigger Hookup Event # TGxCTRL TRIGSRC[3:0] Trigger Disabled 0000 No trigger source EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 N2HET1[8] Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 143 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 7-31. MIBSPI3 Event Trigger Hookup (continued) Event # TGxCTRL TRIGSRC[3:0] Trigger EVENT9 1010 N2HET1[10] EVENT10 1011 N2HET1[12] EVENT11 1100 N2HET1[14] EVENT12 1101 N2HET1[16] EVENT13 1110 N2HET1[18] EVENT14 1111 Internal Tick counter NOTE For N2HET1 trigger sources, the connection to the MibSPI3 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary). This way, a trigger condition can be generated even if the N2HET1 signal is not selected to be output on the pad. NOTE For GIOx trigger sources, the connection to the MibSPI3 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving the GIOx pin from an external trigger source. If the mux control module is used to select different functionality instead of the GIOx signal, then care must be taken to disable GIOx from triggering MibSPI3 transfers; there is no multiplexing on the input connections. 7.11.3.3 MIBSPI5 Event Trigger Hookup Table 7-32. MIBSPI5 Event Trigger Hookup Event # TGxCTRL TRIGSRC[3:0] Trigger Disabled 0000 No trigger source EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 N2HET1[8] EVENT9 1010 N2HET1[10] EVENT10 1011 N2HET1[12] EVENT11 1100 N2HET1[14] EVENT12 1101 N2HET1[16] EVENT13 1110 N2HET1[18] EVENT14 1111 Internal Tick counter NOTE For N2HET1 trigger sources, the connection to the MibSPI5 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary). This way, a trigger condition can be generated even if the N2HET1 signal is not selected to be output on the pad. 144 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 NOTE For GIOx trigger sources, the connection to the MibSPI5 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving the GIOx pin from an external trigger source. If the mux control module is used to select different functionality instead of the GIOx signal, then care must be taken to disable GIOx from triggering MibSPI5 transfers; there is no multiplexing on the input connections. Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 145 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 7.11.4 MibSPI/SPI Master Mode I/O Timing Specifications Table 7-33. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (2) (3) NO. 1 2 (5) 3 (5) 4 (5) 5 (5) 6 (5) 7 (5) 8 (6) 9 (6) Parameter MIN MAX Unit 40 256tc(VCLK) ns Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 td(SPCH-SIMO)M Delay time, SPISIMO valid before SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 6 td(SPCL-SIMO)M Delay time, SPISIMO valid before SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 6 tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)M – tf(SPC) – 4 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)M – tr(SPC) – 4 tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 0) tf(SPC) + 2.2 tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 1) tr(SPC) + 2.2 tc(SPC)M Cycle time, SPICLK (4) tw(SPCH)M ns 10 th(SPCH-SOMI)M Hold time, SPISOMI data valid after SPICLK high (clock polarity = 1) 10 tC2TDELAY Setup time CS active until SPICLK high (clock polarity = 0) CSHOLD = 0 C2TDELAY*tc(VCLK) + 2*tc(VCLK) - tf(SPICS) + tr(SPC) – 7 (C2TDELAY+2) * tc(VCLK) tf(SPICS) + tr(SPC) + 5.5 CSHOLD = 1 C2TDELAY*tc(VCLK) + 3*tc(VCLK) - tf(SPICS) + tr(SPC) – 7 (C2TDELAY+3) * tc(VCLK) tf(SPICS) + tr(SPC) + 5.5 Setup time CS active until SPICLK low (clock polarity = 1) CSHOLD = 0 C2TDELAY*tc(VCLK) + 2*tc(VCLK) - tf(SPICS) + tf(SPC) – 7 (C2TDELAY+2) * tc(VCLK) tf(SPICS) + tf(SPC) + 5.5 CSHOLD = 1 C2TDELAY*tc(VCLK) + 3*tc(VCLK) - tf(SPICS) + tf(SPC) – 7 (C2TDELAY+3) * tc(VCLK) tf(SPICS) + tf(SPC) + 5.5 Hold time SPICLK low until CS inactive (clock polarity = 0) 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) tf(SPC) + tr(SPICS) - 7 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) tf(SPC) + tr(SPICS) + 11 ns Hold time SPICLK high until CS inactive (clock polarity = 1) 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) tr(SPC) + tr(SPICS) - 7 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) tr(SPC) + tr(SPICS) + 11 ns (C2TDELAY+1) * tc(VCLK) tf(SPICS) – 29 (C2TDELAY+1)*tc(VCLK) ns (C2TDELAY+2)*tc(VCLK) ns tT2CDELAY SPIENAn Sample point 11 tSPIENAW SPIENAn Sample point from write to buffer 146 ns Hold time, SPISOMI data valid after SPICLK low (clock polarity = 0) tSPIENA (5) (6) ns th(SPCL-SOMI)M 10 (1) (2) (3) (4) ns ns ns ns The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared. tc(VCLK) = interface clock cycle time = 1 / f(VCLK) For rise and fall timings, see Table 5-7. When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40ns. The external load on the SPICLK pin must be less than 60pF. The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). C2TDELAY and T2CDELAY is programmed in the SPIDELAY register Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 SPISIMO 5 Master Out Data Is Valid 6 7 Master In Data Must Be Valid SPISOMI Figure 7-14. SPI Master Mode External Timing (CLOCK PHASE = 0) Write to buffer SPICLK (clock polarity=0) SPICLK (clock polarity=1) SPISIMO Master Out Data Is Valid 8 9 SPICSn 10 11 SPIENAn Figure 7-15. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0) Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 147 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 7-34. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (2) (3) NO. Parameter MIN MAX Unit 40 256tc(VCLK) ns Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 tv(SIMO-SPCH)M Valid time, SPICLK high after SPISIMO data valid (clock polarity = 0) 0.5tc(SPC)M – 6 tv(SIMO-SPCL)M Valid time, SPICLK low after SPISIMO data valid (clock polarity = 1) 0.5tc(SPC)M – 6 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC) – 4 tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)M – tf(SPC) – 4 tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 0) tr(SPC) + 2.2 tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 1) tf(SPC) + 2.2 tv(SPCH-SOMI)M Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0) 10 tv(SPCL-SOMI)M Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) 10 tC2TDELAY Setup time CS CSHOLD = 0 active until SPICLK high (clock polarity = 0) CSHOLD = 1 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) tf(SPICS) + tr(SPC) – 7 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) tf(SPICS) + tr(SPC) + 5.5 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) tf(SPICS) + tr(SPC) – 7 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) tf(SPICS) + tr(SPC) + 5.5 Setup time CS active until SPICLK low (clock polarity = 1) CSHOLD = 0 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) tf(SPICS) + tf(SPC) – 7 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) tf(SPICS) + tf(SPC) + 5.5 CSHOLD = 1 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) tf(SPICS) + tf(SPC) – 7 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) tf(SPICS) + tf(SPC) + 5.5 Hold time SPICLK low until CS inactive (clock polarity = 0) T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) 7 T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) + 11 ns Hold time SPICLK high until CS inactive (clock polarity = 1) T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) 7 T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) + 11 ns (C2TDELAY+1)* tc(VCLK) tf(SPICS) – 29 (C2TDELAY+1)*tc(VCLK) ns (C2TDELAY+2)*tc(VCLK) ns 1 tc(SPC)M Cycle time, SPICLK (5) tw(SPCH)M 2 3 (5) 4 (5) 5 (5) 6 (5) 7 (5) 8 (6) 9 (6) tT2CDELAY (4) 10 tSPIENA SPIENAn Sample Point 11 tSPIENAW SPIENAn Sample point from write to buffer (1) (2) (3) (4) (5) (6) 148 ns ns ns ns ns ns ns The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set. tc(VCLK) = interface clock cycle time = 1 / f(VCLK) For rise and fall timings, see the Table 5-7. When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40ns. The external load on the SPICLK pin must be less than 60pF. The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). C2TDELAY and T2CDELAY is programmed in the SPIDELAY register Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 5 4 Master Out Data Is Valid SPISIMO 6 Data Valid 7 Master In Data Must Be Valid SPISOMI Figure 7-16. SPI Master Mode External Timing (CLOCK PHASE = 1) Write to buffer SPICLK (clock polarity=0) SPICLK (clock polarity=1) SPISIMO Master Out Data Is Valid 8 9 SPICSn 10 11 SPIENAn Figure 7-17. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1) Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 149 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 7.11.5 SPI Slave Mode I/O Timings Table 7-35. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (2) (3) (4) NO. 1 2 (6) 3 (6) 4 (6) 5 (6) 6 (6) 7 (6) 8 9 (1) (2) (3) (4) (5) (6) 150 Parameter MIN MAX Unit tc(SPC)S Cycle time, SPICLK (5) 40 ns tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 14 ns tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 14 tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 14 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 14 td(SPCH-SOMI)S Delay time, SPISOMI valid after SPICLK high (clock polarity = 0) trf(SOMI) + 20 td(SPCL-SOMI)S Delay time, SPISOMI valid after SPICLK low (clock polarity = 1) trf(SOMI) + 20 th(SPCH-SOMI)S Hold time, SPISOMI data valid after SPICLK high (clock polarity =0) 2 th(SPCL-SOMI)S Hold time, SPISOMI data valid after SPICLK low (clock polarity =1) 2 tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 4 tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 4 th(SPCL-SIMO)S Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0) 2 th(SPCH-SIMO)S Hold time, SPISIMO data valid after S PICLK high (clock polarity = 1) 2 td(SPCL-SENAH)S Delay time, SPIENAn high after last SPICLK low (clock polarity = 0) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn)+ 22 td(SPCH-SENAH)S Delay time, SPIENAn high after last SPICLK high (clock polarity = 1) 1.5tc(VCLK) 2.5tc(VCLK)+ tr(ENAn) + 22 td(SCSL-SENAL)S Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer) tf(ENAn) tc(VCLK)+tf(ENAn)+27 ns ns ns ns ns ns ns The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is cleared. If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8]. For rise and fall timings, see Table 5-7. tc(VCLK) = interface clock cycle time = 1 /f(VCLK) When the SPI is in Slave mode, the following must be true: For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40ns. The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 5 4 SPISOMI Data Is Valid SPISOMI 6 7 SPISIMO Data Must Be Valid SPISIMO Figure 7-18. SPI Slave Mode External Timing (CLOCK PHASE = 0) SPICLK (clock polarity=0) SPICLK (clock polarity=1) 8 SPIENAn 9 SPICSn Figure 7-19. SPI Slave Mode Enable Timing (CLOCK PHASE = 0) Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 151 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 7-36. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (2) (3) (4) NO. Parameter MIN MAX Unit 1 tc(SPC)S Cycle time, SPICLK (5) 40 ns (6) tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 14 ns tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 14 tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 14 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 14 td(SOMI-SPCL)S Delay time, SPISOMI data valid after SPICLK low (clock polarity = 0) trf(SOMI) + 20 td(SOMI-SPCH)S Delay time, SPISOMI data valid after SPICLK high (clock polarity = 1) trf(SOMI) + 20 th(SPCL-SOMI)S Hold time, SPISOMI data valid after SPICLK high (clock polarity =0) 2 th(SPCH-SOMI)S Hold time, SPISOMI data valid after SPICLK low (clock polarity =1) 2 tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 4 tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 4 tv(SPCH-SIMO)S High time, SPISIMO data valid after SPICLK high (clock polarity = 0) 2 tv(SPCL-SIMO)S High time, SPISIMO data valid after SPICLK low (clock polarity = 1) 2 2 3 (6) 4 (6) 5 (6) 6 (6) 7 (6) 8 ns ns ns ns ns td(SPCH-SENAH)S Delay time, SPIENAn high after last SPICLK high (clock polarity = 0) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) + 22 td(SPCL-SENAH)S Delay time, SPIENAn high after last SPICLK low (clock polarity = 1) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) + 22 9 td(SCSL-SENAL)S Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer) tf(ENAn) tc(VCLK)+tf(ENAn)+ 27 ns 10 td(SCSL-SOMI)S Delay time, SOMI valid after SPICSn low (if new data has been written to the SPI buffer) tc(VCLK) 2tc(VCLK)+trf(SOMI)+ 28 ns (1) (2) (3) (4) (5) (6) 152 ns The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is set. If the SPI is in slave mode, the following must be true: tc(SPC)S ≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8]. For rise and fall timings, see Table 5-7. tc(VCLK) = interface clock cycle time = 1 /f(VCLK) When the SPI is in Slave mode, the following must be true: For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40ns. The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 5 4 SPISOMI SPISOMI Data Is Valid 6 7 SPISIMO Data Must Be Valid SPISIMO Figure 7-20. SPI Slave Mode External Timing (CLOCK PHASE = 1) SPICLK (clock polarity=0) SPICLK (clock polarity=1) 8 SPIENAn 9 SPICSn 10 SPISOMI Slave Out Data Is Valid Figure 7-21. SPI Slave Mode Enable Timing (CLOCK PHASE = 1) Copyright © 2012–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS1114 153 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 8 Device and Documentation Support 8.1 Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all devices and support tools. Each commercial family member has one of three prefixes: TMX, TMP, or TMS (for example,TMS570LS1114). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications. TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. TMS Fully-qualified production device. TMX and TMP devices are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. The figure below illustrates the numbering and symbol nomenclature for the TMS570LS1114 . 154 Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Full Part # TMS 570 Orderable Part # TMX 570 LS 11 1 4 B ZWT Q Q1 R 11 1 4 B ZWT Q Q1 R Prefix: TM TMS = Fully Qualified TMP = Prototype TMX = Samples Core Technology: 570 = Cortex R4F Architecture: LS = Dual CPUs in Lockstep (not included in orderable part #) Flash Memory Size: 11 = 1MB RAM MemorySize: 1 = 128kB Peripheral Set: 4 = no FlexRay, no Ethernet Die Revision: A = Die Revision A B = Die Revision B Package Type: ZWT = 337-Pin Plastic BGA with pb-free solder ball PGE = 144 Pin Plastic Quad Flatpack Temperature Range: Q = -40...+125oC Quality Designator: Q1 = Automotive Shipping Options: R = Tape and Reel Figure 8-1. TMS570LS1114 Device Numbering Conventions Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 155 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 8.2 8.2.1 www.ti.com Documentation Support Related Documentation from Texas Instruments The following documents describe the TMS570LS11x/12x microcontroller.. 8.2.2 SPNU515 TMS570LS12x/11x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the device. SPNZ199 TMS570LS12x/11x Microcontroller, Silicon Revision B, Silicon Errata describes the usage notes and known exceptions to the functional specifications for the device silicon revision B. SPNZ218 TMS570LS12x/11x Microcontroller, Silicon Revision C, Silicon Errata describes the usage notes and known exceptions to the functional specifications for the device silicon revision C. Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 8.3 Trademarks E2E is a trademark of Texas Instruments. CoreSight is a trademark of ARM Limited. ARM, Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All other trademarks are the property of their respective owners. 8.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 156 Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 8.6 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Device Identification 8.6.1 Device Identification Code Register The device identification code register identifies several aspects of the device including the silicon version. The details of the device identification code register are shown in Table 8-1. The device identification code register value for this device is: • Rev A = 0x8046AD05 • Rev B = 0x8046AD15 • Rev C = 0x8046AD1D Figure 8-2. Device ID Bit Allocation Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CP-15 UNIQUE ID TECH R-1 R-00000000100011 R-0 15 12 11 2 1 0 TECH 14 13 I/O VOLT AGE PERIPH PARITY FLASH ECC 10 9 RAM ECC 8 7 6 VERSION 5 4 3 1 0 1 R-101 R-0 R-1 R-10 R-1 R-00011 R-1 R-0 R-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-1. Device ID Bit Allocation Register Field Descriptions Bit Field 31 CP15 Value Indicates the presence of coprocessor 15 1 30-17 UNIQUE ID 16-13 TECH 100011 11 10-9 I/O VOLTAGE Unique device identification number This bitfield holds a unique number for a dedicated device configuration (die). PERIPHERAL PARITY F021 I/O voltage of the device. 0 I/O are 3.3v 1 Peripheral Parity Parity on peripheral memories FLASH ECC Flash ECC 10 8 CP15 present Process technology on which the device is manufactured. 0101 12 Description RAM ECC Program memory with ECC Indicates if RAM memory ECC is present. 1 ECC implemented 7-3 REVISION Revision of the Device. 2-0 101 The platform family ID is always 0b101 8.6.2 Die Identification Registers The two die ID registers at addresses 0xFFFFFF7C and 0xFFFFFF80 form a 64-bit dieid with the information as shown in Table 8-2. Table 8-2. Die-ID Registers Item # of Bits Bit Location X Coordinate on Wafer 12 0xFFFFFF7C[11:0] Y Coordinate on Wafer 12 0xFFFFFF7C[23:12] Wafer # 8 0xFFFFFF7C[31:24] Lot # 24 0xFFFFFF80[23:0] Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 157 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Table 8-2. Die-ID Registers (continued) 158 Item # of Bits Bit Location Reserved 8 0xFFFFFF80[31:24] Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 8.7 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 Module Certifications The following communications modules have received certification of adherence to a standard. Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 159 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 8.7.1 www.ti.com DCAN Certification Figure 8-3. DCAN Certification 160 Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 8.7.2 8.7.2.1 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 LIN Certification LIN Master Mode Figure 8-4. LIN Certification - Master Mode Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 161 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 8.7.2.2 www.ti.com LIN Slave Mode - Fixed Baud Rate Figure 8-5. LIN Certification - Slave Mode - Fixed Baud Rate 162 Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 TMS570LS1114 www.ti.com 8.7.2.3 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 LIN Slave Mode - Adaptive Baud Rate Figure 8-6. LIN Certification - Slave Mode - Adaptive Baud Rate Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 163 TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 9 Mechanical Packaging and Orderable Information 9.1 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 164 Mechanical Packaging and Orderable Information Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) TMS5701114CPGEQQ1 ACTIVE LQFP PGE 144 60 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS570LS 1114CPGEQQ1 TMS5701114CZWTQQ1 ACTIVE NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 125 TMS570LS 1114CZWTQQ1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of