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TMUX1121, TMUX1122, TMUX1123
SCDS413A – AUGUST 2019 – REVISED SEPTEMBER 2019
TMUX112x 5-V, Low-Leakage-Current, 1:1 (SPST), 2-Channel Precision Switches
1 Features
3 Description
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The TMUX1121, TMUX1122, and TMUX1123 are
precision complementary metal-oxide semiconductor
(CMOS) devices that have two independently
selectable 1:1, single-pole, single-throw (SPST)
switches. Wide operating supply of 1.08 V to 5.5 V
allows for use in a broad array of applications from
medical equipment to industrial systems. The device
supports bidirectional analog and digital signals on
the source (Sx) and drain (Dx) pins ranging from
GND to VDD.
1
Wide supply range: 1.08 V to 5.5 V
Low leakage current: 3 pA
Low charge injection: –1.5 pC
Low on-resistance: 1.9 Ω
–40°C to +125°C operating temperature
1.8 V Logic compatible
Fail-safe logic
Rail to rail operation
Bidirectional signal path
Break-before-make switching
ESD protection HBM: 2000 V
The switches of the TMUX1121 are turned on with
Logic 1 on the appropriate logic control inputs, while
Logic 0 is required to turn on switches in the
TMUX1122. The two channels of the TMUX1123 are
split with channel one supporting Logic 1, while
channel two supports Logic 0. The TMUX1123
exhibits break-before-make switching, allowing the
device to be used in cross-point switching
applications.
2 Applications
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Sample-and-hold circuits
Feedback gain switching
Signal isolation
Field transmitters
Programmable logic controllers (PLC)
Factory automation and control
Ultrasound scanners
Patient monitoring & diagnostics
Electrocardiogram (ECG)
Data acquisition systems (DAQ)
Semiconductor test equipment
Battery test equipment
Instrumentation: lab, analytical, portable
Ultrasonic smart meters: Water and Gas
Optical networking
Optical test equipment
The TMUX112x devices are part of the precision
switches and multiplexers family. These devices have
very low on and off leakage currents and low charge
injection, allowing them to be used in high precision
measurement applications. A low supply current of
7 nA and small package options enable use in
portable applications.
Device Information(1)
PART NUMBER
TMUX1121
TMUX1122
TMUX1123
PACKAGE
VSSOP (8) (DGK)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
SPACER
SPACER
SPACER
TMUX112x Block Diagrams
CHANNEL 1
S1
CHANNEL 1
D1
S1
CHANNEL 2
S2
CHANNEL 1
D1
S1
CHANNEL 2
D2
S2
D2
S2
SEL1
SEL1
SEL1
SEL2
SEL2
SEL2
TMUX1121
TMUX1122
D1
CHANNEL 2
D2
TMUX1123
ALL SWITCHES SHOWN FOR A LO GIC 0 INPUT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX1121, TMUX1122, TMUX1123
SCDS413A – AUGUST 2019 – REVISED SEPTEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
1
1
1
2
3
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics (VDD = 5 V ±10 %) ............ 5
Electrical Characteristics (VDD = 3.3 V ±10 %) ......... 7
Electrical Characteristics (VDD = 1.8 V ±10 %) ......... 9
Electrical Characteristics (VDD = 1.2 V ±10 %) ....... 11
Typical Characteristics ............................................ 13
Parameter Measurement Information ................ 16
8.1
8.2
8.3
8.4
8.5
8.6
8.7
On-resistance..........................................................
Off-leakage current .................................................
On-leakage current .................................................
Transition time.........................................................
Break-before-make .................................................
Charge injection ......................................................
Off isolation .............................................................
16
16
17
17
18
18
19
8.8 Channel-to-Channel Crosstalk ................................ 19
8.9 Bandwidth ............................................................... 20
9
Detailed Description ............................................ 21
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
21
21
21
23
10 Application and Implementation........................ 24
10.1 Application Information.......................................... 24
10.2 Typical Application - Sample-and-Hold Circuit .... 24
10.3 Typical Application - Switched Gain Amplifier ..... 26
11 Power Supply Recommendations ..................... 28
12 Layout................................................................... 28
12.1 Layout Guidelines ................................................. 28
12.2 Layout Example .................................................... 29
13 Device and Documentation Support ................. 30
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
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14 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2019) to Revision A
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Changed the document From: Advanced Information To: Production data .......................................................................... 1
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Product Folder Links: TMUX1121 TMUX1122 TMUX1123
TMUX1121, TMUX1122, TMUX1123
www.ti.com
SCDS413A – AUGUST 2019 – REVISED SEPTEMBER 2019
5 Device Comparison Table
PRODUCT
DESCRIPTION
TMUX1121
Low-Leakage-Current, 1:1 (SPST), 2-Channel Precision Switches (Active High)
TMUX1122
Low-Leakage-Current, 1:1 (SPST), 2-Channel Precision Switches (Active Low)
TMUX1123
Low-Leakage-Current, 1:1 (SPST), 2-Channel Precision Switches (Active High + Active Low)
6 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
S1
1
8
V
D1
2
7
SEL1
SEL2
3
6
D2
GND
4
5
S2
DD
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION (2)
S1
1
I/O
Source pin 1. Can be an input or output.
D1
2
I/O
Drain pin 1. Can be an input or output.
SEL2
3
I
Logic control select pin 2. Controls channel 2 state as shown in Truth Tables.
GND
4
P
Ground (0 V) reference
S2
5
I/O
Source pin 2. Can be an input or output.
D2
6
I/O
Drain pin 2. Can be an input or output.
SEL1
7
I
Logic control select pin 1. Controls channel 1 state as shown in Truth Tables.
VDD
8
P
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
(1)
(2)
I = input, O = output, I/O = input and output, P = power
Refer to Device Functional Modes for what to do with unused pins
Copyright © 2019, Texas Instruments Incorporated
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TMUX1121, TMUX1122, TMUX1123
SCDS413A – AUGUST 2019 – REVISED SEPTEMBER 2019
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
MIN
MAX
VDD
Supply voltage
–0.5
6
V
VSEL
Logic control input pin voltage (SELx)
–0.5
6
V
ISEL
Logic control input pin current (SELx)
–30
30
mA
VS or VD
Source or drain voltage (Sx, Dx)
–0.5
VDD+0.5
IS or ID (CONT)
Source or drain continuous current (Sx, Dx)
–30
30
mA
Tstg
Storage temperature
–65
150
°C
TJ
Junction temperature
150
°C
(1)
(2)
(3)
UNIT
V
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
All voltages are with respect to ground, unless otherwise specified.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
Positive power supply voltage
VS or VD
VSEL
IS or ID
TA
NOM
MAX
UNIT
1.08
5.5
V
Signal path input/output voltage (source or drain pins: Sx, Dx)
0
VDD
V
Logic control input pin voltage (SELx)
0
5.5
V
Signal path continuous current (source or drain pins: Sx, Dx)
–30
30
mA
Ambient temperature
–40
125
°C
7.4 Thermal Information
THERMAL METRIC
(1)
TMUX1121 / TMUX1122 /
TMUX1123
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
205.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
91.7
°C/W
RθJB
Junction-to-board thermal resistance
127.0
°C/W
ΨJT
Junction-to-top characterization parameter
25.9
°C/W
ΨJB
Junction-to-board characterization parameter
125.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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Product Folder Links: TMUX1121 TMUX1122 TMUX1123
TMUX1121, TMUX1122, TMUX1123
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SCDS413A – AUGUST 2019 – REVISED SEPTEMBER 2019
7.5 Electrical Characteristics (VDD = 5 V ±10 %)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
RON
On-resistance matching between
channels
On-resistance flatness
FLAT
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
Source off leakage current (1)
Drain off leakage current (1)
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
25°C
4
Ω
–40°C to +85°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
25°C
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
Refer to Off-leakage current
25°C
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
Refer to Off-leakage current
25°C
VDD = 5 V
Switch On
VD = VS = 4.5 V / 1.5 V
Refer to On-leakage current
1.9
4.5
Ω
–40°C to +125°C
4.9
Ω
0.13
Ω
–40°C to +85°C
0.4
Ω
–40°C to +125°C
0.5
Ω
0.85
Ω
–40°C to +85°C
1.6
Ω
–40°C to +125°C
1.6
Ω
0.08
nA
–40°C to +85°C
–0.08
–0.3
0.3
nA
–40°C to +125°C
–0.9
0.9
nA
–0.08
±0.003
0.08
nA
–40°C to +85°C
–0.3
0.3
nA
–40°C to +125°C
–0.9
0.9
nA
25°C
–0.1
0.1
nA
–40°C to +85°C
±0.003
±0.003
–0.35
0.35
nA
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (SELx)
VIH
Input logic high
–40°C to +125°C
1.49
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.87
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
0.007
–40°C to +125°C
µA
1
µA
When VS is 4.5 V, VD is 1.5 V or when VS is 1.5 V, VD is 4.5 V.
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Electrical Characteristics (VDD = 5 V ±10 %) (continued)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
(BBM)
QC
OISO
XTALK
Transition time between channels
Break before make time
(TMUX1123 Only)
Charge Injection
Off Isolation
Crosstalk
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to Transition time
25°C
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to Break-before-make
25°C
12
–40°C to +85°C
–40°C to +125°C
8
ns
17
ns
18
ns
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
VS = 1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge injection
25°C
–1.5
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off isolation
25°C
–62
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off isolation
25°C
–40
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Channel-to-Channel
Crosstalk
25°C
–100
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Channel-to-Channel
Crosstalk
25°C
–90
dB
300
MHz
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
CSOFF
Source off capacitance
f = 1 MHz
25°C
6
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
10
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
18
pF
6
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SCDS413A – AUGUST 2019 – REVISED SEPTEMBER 2019
7.6 Electrical Characteristics (VDD = 3.3 V ±10 %)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
3.7
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
RON
On-resistance matching between
channels
On-resistance flatness
FLAT
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
Source off leakage current (1)
Drain off leakage current (1)
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
25°C
8.8
Ω
–40°C to +85°C
9.5
Ω
–40°C to +125°C
9.8
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
25°C
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
VS = 1 V / 3 V
Refer to Off-leakage current
25°C
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
VS = 1 V / 3 V
Refer to Off-leakage current
25°C
VDD = 3.3 V
Switch On
VD = VS = 3 V / 1 V
Refer to On-leakage current
0.13
Ω
–40°C to +85°C
0.4
Ω
–40°C to +125°C
0.5
Ω
–40°C to +85°C
–40°C to +125°C
–0.05
1.9
Ω
2
Ω
2.2
Ω
0.05
nA
–40°C to +85°C
–0.2
0.2
nA
–40°C to +125°C
–0.9
0.9
nA
–0.05
±0.001
0.05
nA
–40°C to +85°C
–0.2
0.2
nA
–40°C to +125°C
–0.9
0.9
nA
25°C
–0.1
0.1
nA
–40°C to +85°C
±0.001
±0.003
–0.35
0.35
nA
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (SELx)
VIH
Input logic high
–40°C to +125°C
1.35
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.8
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
0.004
–40°C to +125°C
µA
1
µA
When VS is 3 V, VD is 1 V or when VS is 1 V, VD is 3 V.
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Electrical Characteristics (VDD = 3.3 V ±10 %) (continued)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
(BBM)
QC
OISO
XTALK
Transition time between channels
Break before make time
(TMUX1123 Only)
Charge Injection
Off Isolation
Crosstalk
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to Transition time
25°C
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to Break-before-make
25°C
14
–40°C to +85°C
–40°C to +125°C
9
ns
20
ns
22
ns
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
VS = 1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge injection
25°C
–1.5
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off isolation
25°C
–62
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off isolation
25°C
–40
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Channel-to-Channel
Crosstalk
25°C
–100
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Channel-to-Channel
Crosstalk
25°C
–90
dB
300
MHz
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
CSOFF
Source off capacitance
f = 1 MHz
25°C
6
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
10
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
18
pF
8
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SCDS413A – AUGUST 2019 – REVISED SEPTEMBER 2019
7.7 Electrical Characteristics (VDD = 1.8 V ±10 %)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
On-resistance matching between
channels
Source off leakage current (1)
Drain off leakage current (1)
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
25°C
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
Refer to Off-leakage current
25°C
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
Refer to Off-leakage current
25°C
VDD = 1.98 V
Switch On
VD = VS = 1.62 V / 1 V
Refer to On-leakage current
40
Ω
–40°C to +85°C
80
Ω
–40°C to +125°C
80
Ω
0.4
Ω
–40°C to +85°C
1.5
Ω
–40°C to +125°C
1.5
Ω
0.05
nA
–40°C to +85°C
–0.05
–0.2
0.2
nA
–40°C to +125°C
–0.9
0.9
nA
–0.05
±0.001
0.05
nA
–40°C to +85°C
–0.2
0.2
nA
–40°C to +125°C
–0.9
0.9
nA
25°C
–0.1
0.1
nA
–40°C to +85°C
±0.001
±0.003
–0.35
0.35
nA
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (SELx)
VIH
Input logic high
–40°C to +125°C
1.07
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.68
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
0.001
–40°C to +125°C
µA
0.85
µA
When VS is 1.62 V, VD is 1 V or when VS is 1 V, VD is 1.62 V.
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Electrical Characteristics (VDD = 1.8 V ±10 %) (continued)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
(BBM)
QC
OISO
XTALK
Transition time between channels
Break before make time
(TMUX1123 Only)
Charge Injection
Off Isolation
Crosstalk
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Transition time
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Break-before-make
25°C
25
–40°C to +85°C
–40°C to +125°C
17
ns
44
ns
44
ns
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
VS = 1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge injection
25°C
–0.5
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off isolation
25°C
–62
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off isolation
25°C
–40
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Channel-to-Channel
Crosstalk
25°C
–100
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Channel-to-Channel
Crosstalk
25°C
–90
dB
300
MHz
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
CSOFF
Source off capacitance
f = 1 MHz
25°C
6
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
10
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
18
pF
10
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7.8 Electrical Characteristics (VDD = 1.2 V ±10 %)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
25°C
On-resistance matching between
channels
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
25°C
25°C
Source off leakage current (1)
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
Refer to Off-leakage current
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
Refer to Off-leakage current
25°C
VDD = 1.32 V
Switch On
VD = VS = 1 V / 0.8 V
Refer to On-leakage current
25°C
On-resistance
ΔRON
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
Drain off leakage current (1)
Channel on leakage current
70
–40°C to +85°C
–40°C to +125°C
Ω
105
Ω
105
Ω
0.4
–40°C to +85°C
Ω
1.5
–40°C to +125°C
–0.05
±0.001
Ω
1.5
Ω
0.05
nA
–40°C to +85°C
–0.2
0.2
nA
–40°C to +125°C
–0.9
0.9
nA
0.05
nA
–0.05
±0.001
–40°C to +85°C
–0.2
0.2
nA
–40°C to +125°C
–0.9
0.9
nA
0.1
nA
–0.35
–0.1
0.35
nA
–40°C to +125°C
–2
2
nA
–40°C to +85°C
±0.003
LOGIC INPUTS (SELx)
VIH
Input logic high
–40°C to +125°C
0.96
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.36
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
0.001
–40°C to +125°C
µA
0.7
µA
When VS is 1 V, VD is 0.8 V or when VS is 0.8 V, VD is 1 V.
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Electrical Characteristics (VDD = 1.2 V ±10 %) (continued)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
(BBM)
QC
OISO
XTALK
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Transition time
25°C
Break before make time
(TMUX1123 Only)
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Break-before-make
25°C
Charge Injection
VS = 1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge injection
25°C
–0.5
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off isolation
25°C
–62
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off isolation
25°C
–40
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Channel-to-Channel
Crosstalk
25°C
–100
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Channel-to-Channel
Crosstalk
25°C
–90
dB
300
MHz
Transition time between channels
Off Isolation
Crosstalk
55
ns
–40°C to +85°C
190
ns
–40°C to +125°C
190
ns
28
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
CSOFF
Source off capacitance
f = 1 MHz
25°C
6
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
10
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
18
pF
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7.9 Typical Characteristics
at TA = 25°C, VDD = 5 V (unless otherwise noted)
6
5
VDD = 3 V
VDD = 3.63 V
VDD = 4.5 V
VDD = 5.5 V
TA = 125°C
TA = 85°C
TA = 25°C
TA = 40°C
4
On Resistance (:)
On Resistance (:)
5
4.5
4
3
2
3.5
3
2.5
2
1.5
1
1
0.5
0
0
0
1
2
3
4
VS or VD - Source or Drain Voltage (V)
5
5.5
0
1
2
3
4
VS or VD - Source or Drain Voltage (V)
D001
TA = 25°C
Figure 2. On-Resistance vs Temperature
8
80
TA = 125°C
TA = 85°C
TA = 25°C
TA = 40°C
7
VDD = 1.08 V
VDD = 1.32 V
VDD = 1.62 V
VDD = 1.98 V
70
60
On Resistance (:)
6
On Resistance (:)
D002
VDD = 5 V
Figure 1. On-Resistance vs Source or Drain Voltage
5
4
3
50
40
30
2
20
1
10
0
0
0
0.5
1
1.5
2
2.5
3
VS or VD - Source or Drain Voltage (V)
3.5
0
D003
0.2
0.4 0.6 0.8
1
1.2 1.4 1.6
VS or VD - Source or Drain Voltage (V)
VDD = 3.3 V
1.8
2
D004
TA = 25°C
Figure 3. On-Resistance vs Temperature
Figure 4. On-Resistance vs Source or Drain Voltage
20
80
VDD = 3.63 V
VDD = 1.98V
VDD = 1.32V
15
VDD = 5 V
60
40
On-Leakage (pA)
10
On-Leakage (pA)
5
5
0
-5
20
0
-20
-10
-40
-15
-60
-20
-80
0
0.5
1
1.5
2
2.5
3
3.5
VS or VD - Source or Drain Voltage (V)
4
D005
0
1
2
3
4
VS or VD - Source or Drain Voltage (V)
TA = 25°C
5
D006
TA = 25°C
Figure 5. On-Leakage vs Source or Drain Voltage
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Figure 6. On-Leakage vs Source or Drain Voltage
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Typical Characteristics (continued)
1
2
IOFF
ION
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-40
IOFF
ION
1.5
Leakage Current (nA)
Leakage Current (nA)
0.75
1
0.5
0
-0.5
-1
-1.5
-20
0
20
40
60
Temperature (qC)
80
100
-2
-40
120
-20
0
20
40
60
Temperature (qC)
D007
VDD = 3.3 V
Figure 7. Leakage Current vs Temperature
VDD = 5 V
VDD = 3.3 V
VDD = 1.8 V
VDD = 1.2 V
400
Supply Current (PA)
Supply Current (PA)
D008
Figure 8. Leakage Current vs Temperature
VDD = 5 V
VDD = 3.3 V
VDD = 1.8 V
VDD = 1.2 V
0.2
0.1
300
200
100
-0.1
-40
0
-20
0
20
40
60
80
Temperature (qC)
100
120
140
0
0.5
1
1.5
D009
VSEL = 5.5 V
2
2.5
3
3.5
Logic Voltage (V)
4
4.5
5
D010
TA = 25°C
Figure 9. Supply Current vs Temperature
Figure 10. Supply Current vs Logic Voltage
20
8
VDD = 3.3 V
VDD = 5 V
15
VDD = 1.2 V
VDD = 1.8 V
6
10
Charge Injection (pC)
Charge Injection (pC)
120
500
0
5
0
-5
-10
-15
4
2
0
-2
-4
-6
-20
-8
0
1
2
3
VS - Source Voltage (V)
4
TA = -40°C to 125°C
Figure 11. Charge Injection vs Source Voltage
14
100
VDD = 5 V
0.4
0.3
80
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D011
0
0.25
0.5
0.75
1
1.25
Source Voltage (V)
1.5
1.75
2
D012
TA = –40°C to 125°C
Figure 12. Charge Injection vs Source Voltage
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Typical Characteristics (continued)
55
Transition OFF
Transition ON
50
45
Magnitude (dB)
Time (ns)
40
35
30
25
20
15
10
5
1
1.5
2
2.5
3
3.5
4
VDD - Supply Voltage (V)
4.5
5
5.5
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
100k
Off-Isolation
Crosstalk
1M
10M
Frequency (Hz)
D013
TA = -40°C to +125°C
100M
D014
TA = -40°C to +125°C
Figure 13. Output TTRANSITION vs Supply Voltage
Figure 14. Off-Isolation vs Frequency
0
-1
Gain (dB)
-2
-3
-4
-5
-6
1M
10M
Frequency (Hz)
100M
D015
TA = -40°C to +125°C
Figure 15. On Response vs Frequency
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8 Parameter Measurement Information
8.1 On-resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (Dx) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.
The measurement setup used to measure RON is shown in Figure 16. Voltage (V) and current (ISD) are measured
using this setup, and RON is computed with RON = V / ISD:
V
ISD
Sx
Dx
VS
Figure 16. On-Resistance measurement setup
8.2 Off-leakage current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF).
The setup used to measure both off-leakage currents is shown in Figure 17.
VDD
VDD
VDD
D1
S1
A
A
VD
VS
D1
VD
IS (OFF)
A
A
VD
VS
S1
VS
ID (OFF)
D2
S2
VDD
IS (OFF)
ID (OFF)
S2
D2
VS
VD
GND
GND
Figure 17. Off-leakage measurement setup
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8.3 On-leakage current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON).
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON).
Either the source pin or drain pin is left floating during the measurement. Figure 18 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON).
VDD
VDD
VDD
N.C.
A
A
VD
N.C.
S1
D1
S2
D2
N.C.
VS
IS (ON)
ID (ON)
D2
S2
VDD
IS (ON)
ID (ON)
D1
S1
A
A
VD
N.C.
VS
GND
GND
Figure 18. On-leakage measurement setup
8.4 Transition time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device. System level timing can then account for the time constant added from the load resistance and load
capacitance. Figure 19 shows the setup used to measure transition time, denoted by the symbol tTRANSITION.
VDD
0.1 F
VDD
VDD
VSEL
tf < 5ns
tr < 5ns
VIH
VIL
S1
0V
D1
OUTPUT
VS
RL
tTRAN SITION
CL
tTRAN SITION
S2
D2
OUTPUT
VS
90%
RL
CL
SEL1 ± SEL2
OUTPUT
10%
VSEL
GND
0V
Figure 19. Transition-time measurement setup
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8.5 Break-before-make
The TMUX1123 has break-before-make delay which allows the device to be used in cross-point switching
application. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. Figure 20 shows
the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM).
VDD
0.1 F
VDD
VDD
VIH
VSEL
VIL
0V
90%
OUTPUT 1
D1
S1
VS
90%
CL
RL
Output 2
0V
S2
VS
90%
90%
OUTPUT 2
D2
tBBM2
Output 1
RL
tBBM1
CL
SEL1 ± SEL2
0V
VSEL
tBBM= min (tBBM1, tBBM2)
GND
Figure 20. Break-before-make delay measurement setup
8.6 Charge injection
The TMUX112x devices have a transmission-gate topology. Any mismatch in capacitance between the NMOS
and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the
gate signal. The amount of charge injected into the source or drain of the device is known as charge injection,
and is denoted by the symbol QC. Figure 21 shows the setup used to measure charge injection from source (Sx)
to drain (Dx).
VDD
0.1 F
VDD
VDD
VSEL
VS
S1
D1
OUTPUT
VOUT
0V
CL
Output
VOUT
VS
QC = CL ×
VOUT
VS
S2
D2
SEL1 ± SEL2
VSEL
OUTPUT
VOUT
CL
GND
Figure 21. Charge-injection measurement setup
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8.7 Off isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the
source pin (Sx) of an off-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. Figure 22
shows the setup used to measure off isolation. Use off isolation equation to compute off isolation.
0.1µF
NETWORK
VDD
ANALYZER
VS
50Ÿ
S
VSIG
D
VOUT
RL
50Ÿ
SX/DX
GND
RL
50Ÿ
Figure 22. Off isolation measurement setup
Off Isolation
§V
·
20 ˜ Log ¨ OUT ¸
V
© S ¹
(1)
8.8 Channel-to-Channel Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (Dx) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. The characteristic impedance, Z0, for the measurement is 50 Ω.
Figure 23 shows the setup used to measure, and the equation used to compute crosstalk.
VDD
0.1µF
NETWO RK
VDD
ANALYZER
VOUT
S1
D1
S2
D2
RL
RL
50Ÿ
50Ÿ
VS
RL
50Ÿ
50Ÿ
VSIG = 200 mVpp
VBIAS = VDD / 2
GND
Figure 23. Channel-to-Channel Crosstalk Measurement Setup
Channel-to-Channel Crosstalk
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
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8.9 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. The
characteristic impedance, Z0, for the measurement is 50 Ω. Figure 24 shows the setup used to measure
bandwidth.
VDD
0.1µF
NETWORK
VDD
VS
S
ANALYZER
50Ÿ
VSIG
D
VOUT
RL
50Ÿ
GND
Figure 24. Bandwidth measurement setup
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9 Detailed Description
9.1 Overview
The TMUX1121, TMUX1122, and TMUX1123 are 1:1 (SPST), 2-Channel switches. The devices have two
independently selectable single-pole, single-throw switches that are turned-on or turned-off based on the state of
the corresponding select pin.
9.2 Functional Block Diagram
CHANNEL 1
CHANNEL 1
S1
D1
S1
CHANNEL 2
CHANNEL 1
D1
S1
D1
CHANNEL 2
S2
D2
S2
CHANNEL 2
D2
S2
D2
SEL1
SEL1
SEL1
SEL2
SEL2
SEL2
TMUX1121
TMUX1122
TMUX1123
ALL SWITCHES SHOWN FOR A LO GIC 0 INPUT
Figure 25. TMUX112x Functional Block Diagram
9.3 Feature Description
9.3.1 Bidirectional operation
The TMUX112x conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each
channel has very similar characteristics in both directions and supports both analog and digital signals.
9.3.2 Rail to rail operation
The valid signal path input/output voltage for TMUX112x ranges from GND to VDD.
9.3.3 1.8 V Logic compatible inputs
The TMUX112x devices have 1.8-V logic compatible control for all logic control inputs. The logic input thresholds
scale with supply but still provide 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V logic level
inputs allows the TMUX112x devices to interface with processors that have lower logic I/O rails and eliminates
the need for an external translator, which saves both space and BOM cost. The current consumption of the
TMUX112x devices increase when using 1.8V logic with higher supply voltage as shown in Figure 10. For more
information on 1.8 V logic implementations refer to Simplifying Design with 1.8 V logic Muxes and Switches
9.3.4 Fail-safe logic
The TMUX112x supports Fail-Safe Logic on the control input pins (EN, A0, A1) allowing for operation up to 5.5
V, regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied before
the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by
removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic
feature allows the select pins of the TMUX112x to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature
enables operation of the TMUX112x with VDD = 1.2 V while allowing the select pins to interface with a logic level
of another device up to 5.5 V.
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Feature Description (continued)
9.3.5 Ultra-low Leakage Current
The TMUX112x devices provide extremely low on-leakage and off-leakage currents. The TMUX112x devices are
capable of switching signals from high source-impedance inputs into a high input-impedance op amp with
minimal offset error because of the ultra-low leakage currents. Figure 26 shows typical leakage currents of the
TMUX112x devices versus temperature at VDD = 5V.
2
IOFF
ION
1.5
Leakage Current (nA)
1
0.5
0
-0.5
-1
-1.5
-2
-40
-20
0
20
40
60
Temperature (qC)
80
100
120
D008
Figure 26. Leakage Current vs Temperature
9.3.6 Ultra-low Charge Injection
The TMUX112x devices have a transmission gate topology, as shown in Figure 27. Any mismatch in the stray
capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is
opened or closed.
The TMUX112x devices have special charge-injection cancellation circuitry that reduces the source-to-drain
charge injection to -1.5 pC at VS = 1 V as shown in Figure 28.
SPACER
SPACER
20
OFF ON
VDD = 3.3 V
VDD = 5 V
CGDN
CGSN
D
S
CGDP
CGSP
Charge Injection (pC)
15
10
5
0
-5
-10
-15
-20
0
1
2
3
VS - Source Voltage (V)
OFF ON
Figure 27. Transmission Gate Topology
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4
5
D011
Figure 28. Charge Injection vs Source Voltage
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9.4 Device Functional Modes
The TMUX112x devices have two independently selectable single-pole, single-throw switches that are turned-on
or turned-off based on the state of the corresponding select pin. The control pins can be as high as 5.5 V.
The TMUX112x devices can be operated without any external components except for the supply decoupling
capacitors. Unused logic control pins should be tied to GND or VDD in order to ensure the device does not
consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path
inputs (Sx or Dx) should be connected to GND.
9.4.1 Truth Tables
Table 1, Table 2, and Table 3 show the truth tables for the TMUX1121, TMUX1122, and TMUX1123,
respectively.
Table 1. TMUX1121 Truth table (1)
(1)
SEL1
SEL2
CHANNEL STATE
0
X
Channel 1 OFF
1
X
Channel 1 ON
X
0
Channel 2 OFF
X
1
Channel 2 ON
X denotes don't care.
Table 2. TMUX1122 Truth table (1)
(1)
SEL1
SEL2
CHANNEL STATE
0
X
Channel 1 ON
1
X
Channel 1 OFF
X
0
Channel 2 ON
X
1
Channel 2 OFF
X denotes don't care.
Table 3. TMUX1123 Truth table (1)
(1)
SEL1
SEL2
CHANNEL STATE
0
X
Channel 1 OFF
Channel 1 ON
1
X
X
0
Channel 2 ON
X
1
Channel 2 OFF
X denotes don't care.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TMUX11xx family offers ulta-low input/output leakage currents and low charge injection. These devices
operate up to 5.5 V, and offer true rail-to-rail input and output of both analog and digital signals. The TMUX112x
have a low on-capacitance which allows faster settling time when multiplexing inputs in the time domain. These
features make the TMUX11xx devices a family of precision, high-performance switches and multiplexers for lowvoltage applications.
10.2 Typical Application - Sample-and-Hold Circuit
One useful application to take advantage of the TMUX1121, TMUX1122, and TMUX1123 performance is the
sample-and-hold circuit. A sample-and-hold circuit can be useful for an analog to digital converter (ADC) to
sample a varying input voltage with improved reliability and stability. It can also be used to store the output
samples from a single digital-to-analog converter (DAC) in a multi-output application. A simple sample-and-hold
circuit can be realized using an analog switch such as the TMUX1121, TMUX1122, and TMUX1123 analog
switches. Figure 29 shows a single channel sample-and hold circuit using only 1 of 2 channels in the TMUX112x
devices.
TMUX112x
DAC
+
OP AMP
±
+
RL
CH
SEL1
2 Channels
OP AMP
VOUT
CL
±
(1.8V Capable Control Logic)
SEL2
Figure 29. Single Channel Sample-and-Hold Circuit Example
An optional operational amplifier is used before the switch since buffered DACs typically have limitations in
driving capacitive loads. The additional buffer stage is included following the DAC to prevent potential stability
problems from driving a large capacitive load.
Ideally, the switch delivers only the input signals to the holding capacitors. However, when the switch gets
toggled, some amount of charge also gets transferred to the switch output in the form of charge injection,
resulting in a pedestal sampling error. The TMUX1121, TMUX1122, and TMUX1123 switches have excellent
charge injection performance of only -1.5 pC, making them ideal choices for this implementation to minimize
sampling error. The pedestal error voltage is indirectly related to the size of the capacitance on the output, for
better precision a larger capacitor is required due to charge injection. Larger capacitance limits the system
settling time which may not be acceptable in some applications. Figure 30 shows a TMUX112x device configured
for a 2-channel sample-and-hold circuit with pedestal error compensation.
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Typical Application - Sample-and-Hold Circuit (continued)
5V
CH
VDD
5V
DAC988 1
VIN1
SW1
5V
+
SW2
5V
±
CC
RC
0V
VOUT1
CL
+
OPA2192
±
RL
OPA2192
0V
SEL1/
SEL2
CH
TMUX112x
Figure 30. 2-Channel Sample-and-Hold Circuit with Pedestal Error Compensation
10.2.1 Design Requirements
The purpose of this precision design is to implement an optimized 2-output sample-and-hold circuit using a 2channel 1:1 (SPST) switch. The sample and hold circuit needs to be capable of supporting high accuracy with
minimized pedestal error and fast settling time..
10.2.2 Detailed Design Procedure
The TMUX1121, TMUX1122, or TMUX1123 switch is used in conjunction with the voltage holding capacitors
(CH) to implement the sample-and-hold circuit. The basic operation is:
1. When the switch (SW2) is closed, it samples the input voltage and charges the holding capacitors (CH) to the
input voltages values.
2. When the switch (SW2) is open, the holding capacitors (CH) holds its previous value, maintaining stable
voltage at the amplifier output (VOUT).
Due to switch and capacitor leakage current, as well as amplifier bias current, the voltage on the hold capacitors
droops with time. The TMUX1121, TMUX1122, or TMUX1123 minimize the droops due to its ultra-low leakage
performance. At 25°C, the TMUX1121, TMUX1122, andTMUX1123 have extremely low leakage current at 3 pA
typical.
A second switch SW1 is also included to operate in parallel with SW2 to reduce pedestal error during switch
toggling. Because both switches are driven at the same potential, they act as common-mode signal to the opamp, thereby minimizing the charge injection effects caused by the switch toggling action. Compensation network
consisting of RC and CC is also added to further reduce the pedestal error, whiling reducing the hold-time glitch
and improving the settling time of the circuit. Refer to Sample & Hold Glitch Reduction for Precision Outputs
Reference Design for more information on sample-and-hold circuits.
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Typical Application - Sample-and-Hold Circuit (continued)
10.2.3 Application Curve
TMUX1121, TMUX1122, andTMUX1123 have excellent charge injection performance and ultra-low leakage
current, making them ideal choices to minimize sampling error for the sample and hold application.
20
80
VDD = 3.3 V
VDD = 5 V
VDD = 5 V
60
10
40
On-Leakage (pA)
Charge Injection (pC)
15
5
0
-5
20
0
-20
-10
-40
-15
-60
-80
-20
0
1
2
3
VS - Source Voltage (V)
4
0
5
1
2
3
4
VS or VD - Source or Drain Voltage (V)
D011
5
D006
TA = -40°C to +125°C
VDD= 5 V
Figure 31. Charge Injection vs Source Voltage
Figure 32. On-Leakage vs Source or Drain Voltage
10.3 Typical Application - Switched Gain Amplifier
Switches and multiplexers are commonly used in the feedback path of amplifier circuits to provide configurable
gain control. By using various resistor values on each switch path the TMUX112x allows the system to have
multiple gain settings. An external resistor, or utilizing 1 channel always being closed, ensures the amplifier isn't
operating in an open loop configuration. A transimpedance amplifier (TIA) for photodiode inputs is a common
circuit that requires gain control using a multi-channel switch to convert the output current of the photodiode into
a voltage for the MCU or processor. The leakage current, capacitance, and charge injection performance of the
TMUX112x are key specifications to evaluate when selecting a device for gain control.
VI/O
VDD
VDD
0.1µF
Processor
SEL1
SEL2
1.8V Logic I/O
RF_1
RF_2
Digital Processin g
VDD
VDD
IPD
+
OP
AMP
Gai n / Fil ter
Network
ADC
Figure 33. Switching Gain Settings of a TIA circuit
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Typical Application - Switched Gain Amplifier (continued)
10.3.1 Design Requirements
For this design example, use the parameters listed in Table 4.
Table 4. Design parameters
PARAMETERS
VALUES
Supply (VDD)
3.3 V
Input / Output signal range
0 µA to 10 µA
Control logic thresholds
1.8 V compatible
10.3.2 Detailed Design Procedure
The TMUX112x devices can be operated without any external components except for the supply decoupling
capacitors. All inputs signals passing through the switch must fall within the recommend operating conditions of
the TMUX112x including signal range and continuous current. For this design example, with a supply of 3.3 V,
the signals can range from 0 V to 3.3 V when the device is powered. The max continuous current can be 30 mA.
Photodiodes commonly have a current output that ranges from a few hundred picoamps to tens of microamps
based on the amount of light being absorbed. The TMUX112x have a typical On-leakage current of less than 10
pA which would lead to an accuracy well within 1% of a full scale 10 µA signal. The low ON and OFF
capacitance of the TMUX112x improves system stability by minimizing the total capacitance on the output of the
amplifier. Lower capacitance leads to less overshoot and ringing in the system which can cause the amplifier
circuit to go unstable if the phase margin is not at least 45°. Refer to Improve Stability Issues with Low CON
Multiplexers for more information on calculating the phase margin vs. percent overshoot.
10.3.3 Application Curve
The TMUX1121 is capable of switching signals from high source-impedance inputs into a high input-impedance
op amp with minimal offset error because of the ultra-low leakage currents.
20
VDD = 3.63 V
VDD = 1.98V
VDD = 1.32V
15
On-Leakage (pA)
10
5
0
-5
-10
-15
-20
0
0.5
1
1.5
2
2.5
3
3.5
VS or VD - Source or Drain Voltage (V)
4
D005
TA = 25°C
Figure 34. On-Leakage vs Source or Drain Voltage
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11 Power Supply Recommendations
The TMUX112x operate across a wide supply range of 1.08 V to 5.5 V. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply to
other components. Good power-supply decoupling is important to achieve optimum performance. For improved
supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground.
Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance
connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series
resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive
systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to
the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall
inductance and is beneficial for connections to ground planes.
12 Layout
12.1 Layout Guidelines
12.1.1 Layout Information
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight, and therefore; some traces must
turn corners.Figure 35 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
BETTER
BEST
2W
WORST
1W min.
W
Figure 35. Trace example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, throughhole pins are not recommended at high frequencies.
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Layout Guidelines (continued)
Figure 36 illustrates an example of a PCB layout with the TMUX112x. Some key considerations are:
•
•
•
•
Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
12.2 Layout Example
C
S1
1
D1
2
8 VDD
TMUX112x
Wide (low inductance)
trace for power
7 SEL1
SEL2 3
6
D2
GND 4
5
S2
Via to
GND p lane
No t to scale
Figure 36. TMUX112x Layout example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
Texas Instruments, Sample & Hold Glitch Reduction for Precision Outputs Reference Design.
Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit.
Texas Instruments, Improve Stability Issues with Low CON Multiplexers.
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.
Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches.
Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers.
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 5. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TMUX1121
Click here
Click here
Click here
Click here
Click here
TMUX1122
Click here
Click here
Click here
Click here
Click here
TMUX1123
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMUX1121DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
121
TMUX1122DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
122
TMUX1123DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
123
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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