Product
Folder
Order
Now
Technical
Documents
Support &
Community
Tools &
Software
TMUX1136
SCDS402A – JUNE 2019 – REVISED JULY 2019
TMUX1136 5-V Low-Leakage-Current, 2:1, 2-Channel Precision Analog Switch
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
The TMUX1136 is a complementary metal-oxide
semiconductor (CMOS) single-pole double-throw
(2:1) switch with two independently controlled
channels. Wide operating supply of 1.08 V to 5.5 V
allows for use in a broad array of applications from
medical equipment to industrial systems. The device
supports bidirectional analog and digital signals on
the source (Sx) and drain (Dx) pins ranging from
GND to VDD. All logic inputs have 1.8 V logic
compatible thresholds, ensuring both TTL and CMOS
logic compatibility when operating in the valid supply
voltage range. Fail-Safe Logic circuitry allows
voltages on the control pins to be applied before the
supply pin, protecting the device from potential
damage.
1
Wide supply range: 1.08 V to 5.5 V
Low leakage current: 3 pA
Low on-resistance: 2 Ω
Low charge injection: –6 pC
-40°C to +125°C operating temperature
1.8 V Logic compatible
Fail-safe logic
Rail-to-rail operation
Bidirectional signal path
Break-before-make switching
ESD protection HBM: 2000 V
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Ultrasound scanners
Patient monitoring & diagnostics
Blood glucose monitors
Optical networking
Optical test equipment
Remote radio units
Power amplifier switching
Data acquisition systems
ATE test equipment
Factory automation and industrial controls
Flow transmitters
Programmable logic controllers (PLC)
Analog input modules
SONAR receivers
Battery monitoring systems
The TMUX1136 is part of the precision switches and
multiplexers family of devices. These devices have
very low on and off leakage currents and low charge
injection, allowing them to be used in high precision
measurement applications. A low supply current of
3 nA and small package options enable use in
portable applications.
Device Information(1)
PART NUMBER
TMUX1136
USON (10) (DQA)
2.50 mm x 1.00 mm
SPACER
Block Diagram
RF_1
TMUX1136
FEEDBACK 1
S1A
RF_2
CF_2
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Application Example
CF_1
PACKAGE
VSSOP (10) (DGS)
FEEDBACK 2
D1
S1B
IPD
SEL1
VO = IPD*RF
S2A
1.8 V
Con trol
TMUX1136
D2
S2B
SEL2
*Switches Shown for Logic 1 Input
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX1136
SCDS402A – JUNE 2019 – REVISED JULY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics (VDD = 5 V ±10 %) ............ 5
Electrical Characteristics (VDD = 3.3 V ±10 %) ......... 7
Electrical Characteristics (VDD = 1.8 V ±10 %) ......... 9
Electrical Characteristics (VDD = 1.2 V ±10 %) ....... 11
Typical Characteristics ............................................ 13
Parameter Measurement Information ................ 16
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
On-Resistance ........................................................
Off-Leakage Current ...............................................
On-Leakage Current ...............................................
Transition Time .......................................................
Break-Before-Make .................................................
Charge Injection ......................................................
Off Isolation .............................................................
Crosstalk .................................................................
16
16
17
17
18
18
19
19
7.9 Bandwidth ............................................................... 20
8
Detailed Description ............................................ 21
8.1 Functional Block Diagram ....................................... 21
8.2 Feature Description................................................. 21
8.3 Device Functional Modes........................................ 23
9
Application and Implementation ........................ 24
9.1
9.2
9.3
9.4
9.5
Application Information............................................
Typical Application .................................................
Design Requirements..............................................
Detailed Design Procedure .....................................
Application Curve ....................................................
24
24
24
25
25
10 Power Supply Recommendations ..................... 26
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 27
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
28
28
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2019) to Revision A
Page
•
Deleted the Product Preview note from the DQA package in the Device Information table ................................................. 1
•
Deleted the Product Preview note from the DQA package in the Pin Configuration and Functions section ......................... 3
2
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
TMUX1136
www.ti.com
SCDS402A – JUNE 2019 – REVISED JULY 2019
5 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
DQA Package
10-Pin USON
Top View
SEL1
1
10
D1
S1A
2
9
S1B
GND
3
8
VDD
S2A
4
7
S2B
SEL2
5
6
D2
SEL1
1
10
D1
S1A
2
9
S1B
GND
3
8
VDD
S2A
4
7
S2B
SEL2
5
6
D2
Not to scale
Not to scale
Pin Functions
PIN
NAME
VSSOP,
USON
TYPE (1)
SEL1
1
I
S1A
2
I/O
GND
3
P
S2A
4
I/O
SEL2
5
I
D2
6
I/O
Drain pin 2. Can be an input or output.
S2B
7
I/O
Source pin 2B. Can be an input or output.
VDD
8
P
S1B
9
I/O
Source pin 1B. Can be an input or output.
D1
10
I/O
Drain pin 1. Can be an input or output.
(1)
DESCRIPTION
Select pin 1: controls state of switch #1 according to Table 1. (Logic Low = S1B to D1, Logic High =
S1A to D1)
Source pin 1A. Can be an input or output.
Ground (0 V) reference
Source pin 2A. Can be an input or output.
Select pin 2: controls state of switch #2 according to Table 1. (Logic Low = S2B to D2, Logic High =
S2A to D2)
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
I = input, O = output, I/O = input and output, P = power
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
3
TMUX1136
SCDS402A – JUNE 2019 – REVISED JULY 2019
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
VDD
Supply voltage
–0.5
6
V
VSEL or VEN
Logic control input pin voltage (SELx)
–0.5
6
V
ISEL or IEN
Logic control input pin current (SELx)
–30
30
mA
VS or VD
Source or drain voltage (SxA, SxB, Dx)
–0.5
VDD+0.5
IS or ID (CONT)
Source or drain continuous current (SxA, SxB, Dx)
–30
30
mA
Tstg
Storage temperature
–65
150
°C
TJ
Junction temperature
150
°C
(1)
(2)
UNIT
V
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101
or ANSI/ESDA/JEDEC JS-002, all pins (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
Supply voltage
VS or VD
Signal path input/output voltage (source or drain pin) (SxA, SxB, Dx)
VSEL
Logic control input pin voltage (SELx)
TA
Ambient temperature
NOM
MAX
UNIT
1.08
5.5
V
0
VDD
V
0
5.5
V
–40
125
°C
6.4 Thermal Information
TMUX1136
THERMAL METRIC (1)
DGS (VSSOP)
DQA (USON)
10 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
193.9
172.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
83.1
79.3
°C/W
RθJB
Junction-to-board thermal resistance
116.5
72.0
°C/W
ΨJT
Junction-to-top characterization parameter
22.0
9.0
°C/W
ΨJB
Junction-to-board characterization parameter
114.6
71.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
TMUX1136
www.ti.com
SCDS402A – JUNE 2019 – REVISED JULY 2019
6.5 Electrical Characteristics (VDD = 5 V ±10 %)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
RON
On-resistance matching between
channels
On-resistance flatness
FLAT
IS(OFF)
ID(ON)
IS(ON)
ID(ON)
IS(ON)
Source off leakage current (1)
Channel on leakage current
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
4
Ω
–40°C to +85°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
Refer to Off-Leakage Current
25°C
VDD = 5 V
Switch On
VD = VS = 2.5 V
Refer to On-Leakage Current
25°C
VDD = 5 V
Switch On
VD = VS = 4.5 V / 1.5 V
Refer to On-Leakage Current
25°C
2
4.5
Ω
–40°C to +125°C
4.9
Ω
0.13
Ω
–40°C to +85°C
0.4
Ω
–40°C to +125°C
0.5
Ω
0.85
Ω
–40°C to +85°C
1.6
Ω
–40°C to +125°C
1.6
Ω
0.08
nA
–40°C to +85°C
–0.08
–0.3
0.3
nA
–40°C to +125°C
–0.9
0.9
nA
–0.025
±0.005
0.025
nA
–40°C to +85°C
–0.3
0.3
nA
–40°C to +125°C
–0.95
0.95
nA
0.1
nA
–0.35
0.35
nA
–40°C to +125°C
–2
2
nA
–40°C to +85°C
–0.1
±0.003
±0.01
LOGIC INPUTS (SELx)
VIH
Input logic high
–40°C to +125°C
1.49
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.87
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
–40°C to +125°C
0.003
µA
1
µA
When VS is 4.5 V, VD is 1.5 V or when VS is 1.5 V, VD is 4.5 V.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
5
TMUX1136
SCDS402A – JUNE 2019 – REVISED JULY 2019
www.ti.com
Electrical Characteristics (VDD = 5 V ±10 %) (continued)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
Switching time between channels
Break before make time
(BBM)
QC
OISO
XTALK
Charge Injection
Off Isolation
Crosstalk
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
25°C
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
12
–40°C to +85°C
–40°C to +125°C
8
ns
18
ns
19
ns
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
VD = 1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
–6
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
–100
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
–80
dB
MHz
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
220
CSOFF
Source off capacitance
f = 1 MHz
25°C
6
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
20
pF
6
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
TMUX1136
www.ti.com
SCDS402A – JUNE 2019 – REVISED JULY 2019
6.6 Electrical Characteristics (VDD = 3.3 V ±10 %)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
3.7
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
RON
On-resistance matching between
channels
On-resistance flatness
FLAT
IS(OFF)
ID(ON)
IS(ON)
Source off leakage current (1)
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
8.8
Ω
–40°C to +85°C
9.5
Ω
–40°C to +125°C
9.8
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
VS = 1 V / 3 V
Refer to Off-Leakage Current
25°C
VDD = 3.3 V
Switch On
VD = VS = 3 V / 1 V
Refer to On-Leakage Current
25°C
0.13
Ω
–40°C to +85°C
0.4
Ω
–40°C to +125°C
0.5
Ω
–40°C to +85°C
–40°C to +125°C
–0.05
1.9
Ω
2
Ω
2.2
Ω
0.05
nA
–40°C to +85°C
–0.1
0.1
nA
–40°C to +125°C
–0.5
0.5
nA
0.1
nA
–0.35
0.35
nA
–40°C to +125°C
–2
2
nA
–40°C to +85°C
–0.1
±0.001
±0.005
LOGIC INPUTS (SELx)
VIH
Input logic high
–40°C to +125°C
1.35
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.8
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
-40°C to 125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
–40°C to +125°C
0.003
µA
0.8
µA
When VS is 3 V, VD is 1 V or when VS is 1 V, VD is 3 V.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
7
TMUX1136
SCDS402A – JUNE 2019 – REVISED JULY 2019
www.ti.com
Electrical Characteristics (VDD = 3.3 V ±10 %) (continued)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
Switching time between channels
Break before make time
(BBM)
QC
OISO
XTALK
Charge Injection
Off Isolation
Crosstalk
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
25°C
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
14
–40°C to +85°C
–40°C to +125°C
9
ns
20
ns
21
ns
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
VD = 1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
–6
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
–100
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
–80
dB
MHz
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
220
CSOFF
Source off capacitance
f = 1 MHz
25°C
6
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
20
pF
8
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
TMUX1136
www.ti.com
SCDS402A – JUNE 2019 – REVISED JULY 2019
6.7 Electrical Characteristics (VDD = 1.8 V ±10 %)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
IS(OFF)
ID(ON)
IS(ON)
On-resistance matching between
channels
Source off leakage current (1)
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
Refer to Off-Leakage Current
25°C
VDD = 1.98 V
Switch On
VD = VS = 1.62 V / 1 V
Refer to On-Leakage Current
40
Ω
–40°C to +85°C
80
Ω
–40°C to +125°C
80
Ω
0.4
Ω
–40°C to +85°C
1.5
Ω
–40°C to +125°C
1.5
Ω
0.05
nA
–40°C to +85°C
–0.05
–0.1
±0.003
0.1
nA
–40°C to +125°C
–0.5
0.5
nA
25°C
–0.1
0.1
nA
–40°C to +85°C
–0.5
0.5
nA
–40°C to +125°C
–2
2
nA
±0.005
LOGIC INPUTS (SELx)
VIH
Input logic high
–40°C to +125°C
1.07
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.68
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
–40°C to +125°C
0.001
µA
0.85
µA
When VS is 1.62 V, VD is 1 V or when VS is 1 V, VD is 1.62 V.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
9
TMUX1136
SCDS402A – JUNE 2019 – REVISED JULY 2019
www.ti.com
Electrical Characteristics (VDD = 1.8 V ±10 %) (continued)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
Transition time between channels
Break before make time
(BBM)
QC
OISO
XTALK
Charge Injection
Off Isolation
Crosstalk
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
28
–40°C to +85°C
–40°C to +125°C
16
ns
44
ns
44
ns
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
VD = 1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
–3
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
–100
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
–80
dB
MHz
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
25°C
220
CSOFF
Source off capacitance
f = 1 MHz
25°C
6
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
20
pF
10
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
TMUX1136
www.ti.com
SCDS402A – JUNE 2019 – REVISED JULY 2019
6.8 Electrical Characteristics (VDD = 1.2 V ±10 %)
at TA = 25°C, VDD = 1.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
IS(OFF)
ID(ON)
IS(ON)
On-resistance matching between
channels
Source off leakage current (1)
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
Refer to Off-Leakage Current
25°C
VDD = 1.32 V
Switch On
VD = VS = 1 V / 0.8 V
Refer to On-Leakage Current
70
Ω
–40°C to +85°C
105
Ω
–40°C to +125°C
105
Ω
0.4
Ω
–40°C to +85°C
1.5
Ω
–40°C to +125°C
1.5
Ω
0.05
nA
–40°C to +85°C
–0.05
–0.1
±0.003
0.1
nA
–40°C to +125°C
–0.5
0.5
nA
25°C
–0.1
0.1
nA
–40°C to +85°C
–0.5
0.5
nA
–40°C to +125°C
–2
2
nA
±0.005
LOGIC INPUTS (SELx)
VIH
Input logic high
–40°C to +125°C
0.96
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.36
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
–40°C to +125°C
0.003
µA
0.7
µA
When VS is 1 V, VD is 0.8 V or when VS is 0.8 V, VD is 1 V.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
11
TMUX1136
SCDS402A – JUNE 2019 – REVISED JULY 2019
www.ti.com
Electrical Characteristics (VDD = 1.2 V ±10 %) (continued)
at TA = 25°C, VDD = 1.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
Transition time between channels
Break before make time
(BBM)
QC
OISO
XTALK
Charge Injection
Off Isolation
Crosstalk
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
55
–40°C to +85°C
–40°C to +125°C
28
ns
190
ns
190
ns
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
VD = 1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
–2
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
–100
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
–80
dB
MHz
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
25°C
220
CSOFF
Source off capacitance
f = 1 MHz
25°C
6
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
20
pF
12
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
TMUX1136
www.ti.com
SCDS402A – JUNE 2019 – REVISED JULY 2019
6.9 Typical Characteristics
at TA = 25°C, VDD = 5 V (unless otherwise noted)
6
5
VDD = 3 V
4.5
5
4
4
VDD = 4.5 V
3
VDD = 5.5 V
2
On Resistance (:)
On Resistance (:)
VDD = 3.63 V
TA = 85qC
3
2.5
2
1.5
1
1
TA = -40qC
0.5
0
TA = 25qC
0
0
1
2
3
4
VS or VD - Source or Drain Voltage (V)
5
5.5
0
1
2
3
4
VS or VD - Source or Drain Voltage (V)
D001
TA = 25°C
80
7
70
TA = 85qC
VDD = 1.08 V
TA = 125qC
On Resistance (:)
60
5
4
3
2
VDD = 1.32 V
50
VDD = 1.62 V
40
30
VDD = 1.98 V
20
1
TA = -40qC
D002
Figure 2. On-Resistance vs Temperature
8
6
5
VDD = 5 V
Figure 1. On-Resistance vs Source or Drain Voltage
On Resistance (:)
TA = 125qC
3.5
10
TA = 25qC
0
0
0
0.5
1
1.5
2
2.5
VS or VD - Source or Drain Voltage (V)
3
3.5
0
0.2
D003
VDD = 3.3 V
0.4 0.6 0.8
1
1.2 1.4 1.6
VS or VD - Source or Drain Voltage (V)
1.8
2
D004
TA = 25°C
Figure 3. On-Resistance vs Temperature
Figure 4. On-Resistance vs Source or Drain Voltage
40
100
30
80
60
VDD = 1.32 V
VDD = 1.98 V
VDD = 3.63 V
On-Leakage (pA)
On-Leakage (pA)
20
10
0
-10
40
20
0
-20
-40
-20
-60
-30
-80
-40
-100
0
0.5
1
1.5
2
2.5
3
VS or VD - Source or Drain Voltage (V)
3.5
4
0
D005
TA = 25°C
1
2
3
4
VS or VD - Source or Drain Voltage (V)
5
D006
VDD = 5 V
Figure 5. On-Leakage vs Source or Drain Voltage
Figure 6. On-Leakage vs Source or Drain Voltage
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
13
TMUX1136
SCDS402A – JUNE 2019 – REVISED JULY 2019
www.ti.com
Typical Characteristics (continued)
3
1
2
0.5
Leakage Current (nA)
Leakage Current (nA)
0.75
IS(OFF)
0.25
0
-0.25
I(ON)
-0.5
0
-1
I(ON)
-2
-0.75
-1
-40
IS(OFF)
1
-20
0
20
40
60
Temperature (qC)
80
100
-3
-40
120
-20
0
20
40
60
Temperature (qC)
D007
VDD = 3.3 V
80
100
120
D008
VDD = 5 V
Figure 7. Leakage Current vs Temperature
Figure 8. Leakage Current vs Temperature
0.5
800
VDD = 5 V
Supply Current (PA)
Supply Current (PA)
0.4
0.3
VDD = 3.3 V
0.2
VDD = 1.8 V
0.1
600
400
VDD = 5 V
VDD = 3.3 V
200
0
VDD = 1.2 V
-0.1
-40
VDD = 1.8 V
0
-20
0
20
40
60
80
Temperature (qC)
100
120
140
0
0.5
1
D009
VSEL = VDD V
Figure 9. Supply Current vs Temperature
4
4.5
5
D010
Figure 10. Supply Current vs Logic Voltage
6
15
4
10
5
Charge Injection (pC)
Charge Injection (pC)
2
2.5
3
3.5
Logic Voltage (V)
TA = 25°C
20
VDD = 3.3 V
0
VDD = 5 V
-5
-10
2
VDD = 1.2 V
0
VDD = 1.8 V
-2
-4
-15
-20
-6
0
1
2
3
VD - Drain Voltage (V)
4
5
0
0.5
D011
TA = -40°C to 125°C
1
VD - Drain Voltage (V)
1.5
2
D012
TA = -40°C to 125°C
Figure 11. Charge Injection vs Drain Voltage
14
1.5
Figure 12. Charge Injection vs Drain Voltage
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
TMUX1136
www.ti.com
SCDS402A – JUNE 2019 – REVISED JULY 2019
Typical Characteristics (continued)
30
25
Falling
Magnitude (dB)
Time (ns)
20
15
Rising
10
5
0
0.5
1.5
2.5
3.5
VDD - Supply Voltage (V)
4.5
5.5
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
100k
Off-Isolation
Crosstalk
1M
D013
TA = 25°C
10M
Frequency (Hz)
100M
D014
TA = -40°C to 125°C
Figure 13. Output TTRANSITION vs Supply Voltage
Figure 14. Xtalk and Off-Isolation vs Frequency
0
-1
Gain (dB)
-2
-3
-4
-5
-6
1M
10M
Frequency (Hz)
100M
D015
TA = -40°C to 125°C
Figure 15. On Response vs Frequency
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
15
TMUX1136
SCDS402A – JUNE 2019 – REVISED JULY 2019
www.ti.com
7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (Dx) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.
The measurement setup used to measure RON is shown in Figure 16. Voltage (V) and current (ISD) are measured
using this setup, and RON is computed with RON = V / ISD:
V
ISD
Sx
D
VS
Figure 16. On-Resistance Measurement Setup
7.2 Off-Leakage Current
Source off-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is off. This current is denoted by the symbol IS(OFF).
The setup used to measure off-leakage current is shown in Figure 17.
VDD
Is (OFF)
S1A
A
D1
S1B
VS
VD
VD
Is (OFF)
S2A
A
D2
S2B
VS
VD
VD
GND
Figure 17. Off-Leakage Measurement Setup
16
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
TMUX1136
www.ti.com
SCDS402A – JUNE 2019 – REVISED JULY 2019
7.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON).
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON).
Either the source pin or drain pin is left floating during the measurement. Figure 18 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON).
VDD
VDD
IS (ON)
VDD
N.C.
VDD
ID (ON)
S1A
S1A
A
D1
D1
A
S1B
N.C.
S1B
VD
Vs
VS
VS
IS (ON)
ID (ON)
S2A
N.C.
S2A
A
D2
D2
A
S2B
N.C.
S2B
VD
Vs
GND
VS
GND
VS
Figure 18. On-Leakage Measurement Setup
7.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the control signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device. System level timing can then account for the time constant added from the load resistance and load
capacitance. Figure 19 shows the setup used to measure transition time, denoted by the symbol tTRANSITION.
VDD
0.1…F
VDD
VDD
ADDRESS
DRIVE
(VSEL)
tf < 5ns
tr < 5ns
VIH
VS
VIL
S1B
D1
OUTPUT
S1A
0V
RL
tTRANSITION
tTRANSITION
VS
CL
S2B
D2
OUTPUT
S2A
RL
90%
CL
SELx
OUTPUT
10%
VSEL
GND
0V
Figure 19. Transition-Time Measurement Setup
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
17
TMUX1136
SCDS402A – JUNE 2019 – REVISED JULY 2019
www.ti.com
7.5 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. Figure 20 shows
the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM).
VDD
0.1…F
VDD
VDD
VS
ADDRESS
DRIVE
(VSEL)
tr < 5ns
tf < 5ns
S1B
D1
OUTPUT
S1A
RL
0V
VS
90%
Output
CL
S2B
D2
OUTPUT
S2A
tBBM 1
tBBM 2
RL
CL
0V
SELx
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
VSEL
GND
Figure 20. Break-Before-Make Delay Measurement Setup
7.6 Charge Injection
The TMUX1136 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS
transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.
The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted
by the symbol QC. Figure 21 shows the setup used to measure charge injection from Drain (D) to Source (Sx).
0.1…F
VDD
VDD
S1A
VDD
VD
VSEL
D1
S1B
0V
N.C.
OUTPUT
VOUT
CL
S2A
Output
D2
S2B
VOUT
VS
QC = CL ×
VOUT
SELx
N.C.
OUTPUT
VOUT
CL
VSEL
GND
Figure 21. Charge-Injection Measurement Setup
18
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
TMUX1136
www.ti.com
SCDS402A – JUNE 2019 – REVISED JULY 2019
7.7 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. Figure 22 shows the setup used to measure, and the equation used to
calculate off isolation.
0.1µF
NETWORK
VDD
ANALYZER
VS
50Q
S
VSIG
D
VOUT
RL
50Q
SxA / SxB
GND
RL
50Q
Figure 22. Off Isolation Measurement Setup
Off Isolation
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
(1)
7.8 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. Figure 23 shows the setup used to measure, and the equation used to
calculate crosstalk.
VDD
0.1µF
NETWORK
VDD
ANALYZER
S1A
D1
VOUT
RL
50Ÿ
RL
S1B
50Ÿ
VS
S2A
D2
S2B
RL
50Ÿ
50Ÿ
VSIG = 200 mVpp
VBIAS = VDD / 2
S1B / S2B
RL
GND
50Ÿ
Figure 23. Crosstalk Measurement Setup
Channel-to-Channel Crosstalk
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
(2)
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
19
TMUX1136
SCDS402A – JUNE 2019 – REVISED JULY 2019
www.ti.com
7.9 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure 24
shows the setup used to measure bandwidth.
0.1µF
NETWORK
VDD
VS
ANALYZER
50Q
S
VSIG
D
VOUT
SxA / SxB
RL
50Q
GND
RL
50Q
Figure 24. Bandwidth Measurement Setup
20
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
TMUX1136
www.ti.com
SCDS402A – JUNE 2019 – REVISED JULY 2019
8 Detailed Description
8.1 Functional Block Diagram
The TMUX1136 is a 2:1 (SPDT), 2-channel analog switch with two independently controlled channels. Each
channel is controlled with a single select (SELx) control pin to toggle between source inputs.
TMUX1136
S1A
D1
S1B
SEL1
S2A
D2
S2B
SEL2
*Switches Shown for Logic 1 Input
Figure 25. TMUX1136 Functional Block Diagram
8.2 Feature Description
8.2.1 Bidirectional Operation
The TMUX1136 conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). The
device has very similar characteristics in both directions and supports both analog and digital signals.
8.2.2 Rail to Rail Operation
The valid signal path input/output voltage for TMUX1136 ranges from GND to VDD.
8.2.3 1.8 V Logic Compatible Inputs
The TMUX1136 has 1.8-V logic compatible control for the logic control inputs (SELx). The logic input threshold
scales with supply but still provides 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V logic level
inputs allow the TMUX1136 to interface with processors that have lower logic I/O rails and eliminates the need
for an external translator, which saves both space and BOM cost. The current consumption of the TMUX1136
increases when using 1.8V logic with higher supply voltage as shown in Figure 10. For more information on 1.8 V
logic implementations refer to Simplifying Design with 1.8 V logic Muxes and Switches.
8.2.4 Fail-Safe Logic
The TMUX1136 supports Fail-Safe Logic on the control input pins (SELx) allowing for operation up to 5.5 V,
regardless of the state of the supply pin. This feature allows voltages on the control pin to be applied before the
supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by
removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic
feature allows the select pin of the TMUX1136 to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature
enables operation of the TMUX1136 with VDD = 1.2 V while allowing the select pin to interface with a logic level
of another device up to 5.5 V.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
21
TMUX1136
SCDS402A – JUNE 2019 – REVISED JULY 2019
www.ti.com
Feature Description (continued)
8.2.5 Ultra-low Leakage Current
The TMUX1136 provides extremely low on-leakage and off-leakage currents. The TMUX1136 is capable of
switching signals from high source-impedance inputs into a high input-impedance op amp with minimal offset
error because of the ultra-low leakage currents. Figure 26 shows typical leakage currents of the TMUX1136
versus temperature.
3
Leakage Current (nA)
2
IS(OFF)
1
0
-1
I(ON)
-2
-3
-40
-20
0
20
40
60
Temperature (qC)
80
100
120
D008
Figure 26. Leakage Current vs Temperature
8.2.6 Ultra-low Charge Injection
The TMUX1136 has a transmission gate topology, as shown in Figure 27. Any mismatch in the stray capacitance
associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.
OFF ON
CGSN
CGDN
S
D
CGSP
CGDP
OFF ON
Figure 27. Transmission Gate Topology
22
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
TMUX1136
www.ti.com
SCDS402A – JUNE 2019 – REVISED JULY 2019
Feature Description (continued)
The TMUX1136 has special charge-injection cancellation circuitry that reduces the drain-to-source charge
injection to -6 pC at VD = 1 V as shown in Figure 28.
20
Charge Injection (pC)
15
10
5
VDD = 3.3 V
0
VDD = 5 V
-5
-10
-15
-20
0
1
2
3
VD - Drain Voltage (V)
4
5
D011
Figure 28. Charge Injection vs Drain Voltage
8.3 Device Functional Modes
The select (SELx) pins of the TMUX1136 controls which source is connected to the drain pins of the device.
When a signal path is not selected, that source pin is in high impedance mode (HI-Z). The control pins can be as
high as 5.5 V.
8.3.1 Truth Tables
Table 1. TMUX1136 Truth Table
CONTROL LOGIC (SELx)
Selected Source (SxA or SxB) Connected To Drain (Dx) Pin
0
S1B to D1
S2B to D2
1
S1A to D1
S2A to D2
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
23
TMUX1136
SCDS402A – JUNE 2019 – REVISED JULY 2019
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TMUX11xx family offers ultra-low input/output leakage currents and low charge injection. These devices
operate up to 5.5 V, and offer true rail-to-rail input and output of both analog and digital signals. The TMUX1136
has a low on-capacitance which allows faster settling time when multiplexing inputs in the time domain. These
features make the TMUX11xx devices a family of precision, high-performance switches and multiplexers for lowvoltage applications.
9.2 Typical Application
Figure 29 shows an example circuit where the TMUX1136 is used to switch different feedback networks of a
transimpedance amplifier (TIA). The application uses a 2-channel SPDT switch in order to optimize the tradeoffs
of low leakage current and on resistance of the switch.
RF_1
CF_1
(Different feed back networks based
on gain setting requirements)
RF_2
CF_2
IPD
FEEDBACK 1
FEEDBACK 2
IBIAS
VO = IPD*RF
1.8 V
Con trol
TMUX1136
VA = IPD*(RF + RON) (Error introduced from R
ON
)
Figure 29. Transimpedance Amplifier Feedback Switching
9.3 Design Requirements
For this design example, use the parameters listed in Table 2.
Table 2. Design Parameters
PARAMETERS
24
VALUES
Supply (VDD)
5V
Input / Output signal range
1nA to 10 µA
Control logic thresholds
1.8 V compatible
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
TMUX1136
www.ti.com
SCDS402A – JUNE 2019 – REVISED JULY 2019
9.4 Detailed Design Procedure
The TMUX1136 can be operated without any external components except for the supply decoupling capacitors.
All inputs passing through the switch must fall within the recommend operating conditions of the TMUX1136,
including signal range and continuous current. For this design with a supply of 5 V the signal range can be 0 V to
5 V, and the max continuous current can be 30 mA.
Photodiodes commonly have a current output that ranges from a few hundred picoamps to tens of microamps
based on the amount of light being absorbed. Difference feedback networks can be switched into a
transimpedance amplifier in order to scale the output voltage to maximize system dynamic range. Typical
feedback resistance is in the 10s-100s of kilo-ohms range where the on resistance of a switch would have
minimal impact on system accuracy. However, some applications will have larger photodiode currents due to
light exposure and can require a feedback resistor as low as 100Ω. Analog switches and multiplexers commonly
have a tradeoff between on-resistance and leakage current which will both lead to overall system error. Figure 29
shows how to configure a multi-channel analog switch to eliminate the impact from on-resistance and select a
device optimized for low leakage currents. The drawback of this architecture is that the output impedance of the
TIA stage is now the on-resistance of the multiplexer since the second channel is outside the feedback loop. This
is commonly an acceptable tradeoff as the on-resistance of the TMUX1136 is very low, 2Ω typical.
The TMUX1136 has a typical On-leakage current of less than 10 pA which would lead to an accuracy well within
1% of a full scale 10 µA signal. The low ON and OFF capacitance of the TMUX1136 improves system stability by
minimizing the total capacitance on the output of the amplifier. Lower capacitance leads to less overshoot and
ringing in the system which can cause the amplifier circuit to go unstable if the phase margin is not at least 45°.
Refer to Improve Stability Issues with Low CON Multiplexers for more information on calculating the phase margin
vs. percent overshoot..
9.5 Application Curve
The TMUX1136 is capable of switching signals with minimal distortion because of the ultra-low leakage currents
and low On-resistance. Figure 30 shows how the leakage current of the TMUX1136 varies with different input
voltages.
100
80
On-Leakage (pA)
60
40
20
0
-20
-40
-60
-80
-100
0
1
2
3
4
VS or VD - Source or Drain Voltage (V)
5
D006
TA = 25°C
Figure 30. On-Leakage vs Source or Drain Voltage
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
25
TMUX1136
SCDS402A – JUNE 2019 – REVISED JULY 2019
www.ti.com
10 Power Supply Recommendations
The TMUX1136 operates across a wide supply range of 1.08 V to 5.5 V. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply to
other components. Good power-supply decoupling is important to achieve optimum performance. For improved
supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground.
Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance
connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series
resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive
systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to
the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall
inductance and is beneficial for connections to ground planes.
11 Layout
11.1 Layout Guidelines
11.1.1 Layout Information
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. Figure 31 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
BETTER
BEST
2W
WORST
1W min.
W
Figure 31. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, throughhole pins are not recommended at high frequencies.
26
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
TMUX1136
www.ti.com
SCDS402A – JUNE 2019 – REVISED JULY 2019
Layout Guidelines (continued)
Figure 32 illustrates an example of a PCB layout with the TMUX1136. Some key considerations are:
•
•
•
•
Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
Via to
GND plane
C
Wide (low inductance)
trace for power
Figure 32. TMUX1136 Layout Example
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
27
TMUX1136
SCDS402A – JUNE 2019 – REVISED JULY 2019
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
Texas Instruments, Ultrasonic Gas Meter Front-End With MSP430™ Reference Design.
Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit.
Texas Instruments, Improve Stability Issues with Low CON Multiplexers.
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.
Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches.
Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers.
Texas Instruments, QFN/SON PCB Attachment.
Texas Instruments, Quad Flatpack No-Lead Logic Packages.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
28
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
TMUX1136
www.ti.com
SCDS402A – JUNE 2019 – REVISED JULY 2019
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TMUX1136
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMUX1136DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1136
TMUX1136DQAR
ACTIVE
USON
DQA
10
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
136
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
