TMUX1308-Q1, TMUX1309-Q1
TMUX1308-Q1,
SCDS414D – DECEMBER
2019 – REVISEDTMUX1309-Q1
NOVEMBER 2020
SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
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TMUX13xx-Q1 5-V, Bidirectional 8:1, 1-Channel and 4:1, 2-Channel
Multiplexers with Injection Current Control
1 Features
3 Description
•
The TMUX1308-Q1 and TMUX1309-Q1 are general
purpose complementary metal-oxide semiconductor
(CMOS) multiplexers (MUX). The TMUX1308-Q1 is
an 8:1, 1-channel (single-ended) mux, while the
TMUX1309-Q1 is a 4:1, 2-channel (differential) mux.
The devices support bidirectional analog and digital
signals on the source (Sx) and drain (Dx) pins ranging
from GND to VDD.
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature
Injection Current Control
Back-Powering Protection
– No ESD Diode Path to VDD
Wide Supply Range: 1.62 V to 5.5 V
Low Capacitance
Bidirectional Signal Path
Rail-to-Rail Operation
1.8 V Logic Compatible
Fail-Safe Logic
Break-Before-Make Switching
Functional Safety-Capable
– Documentation Available to Aid Functional
Safety System Design
TMUX1308-Q1 - Pin Compatible with:
– Industry Standard 4051 and 4851 Multiplexers
TMUX1309-Q1 - Pin Compatible with:
– Industry Standard 4052 and 4852 Multiplexers
2 Applications
•
•
•
•
•
•
•
•
Analog and Digital Multiplexing and Demultiplexing
Diagnostics and Monitoring
Body Control Modules
Battery Management Systems (BMS)
HVAC Control Module
Automotive Head Unit
Telematics
On-board (OBC) and Wireless Charging
The TMUX13xx-Q1 devices have an internal injection
current control feature which eliminates the need for
external diode and resistor networks typically used to
protect the switch and keep the input signals within
the supply voltage. The internal injection current
control circuitry allows signals on disabled signal
paths to exceed the supply voltage without affecting
the signal of the enabled signal path. Additionally, the
TMUX13xx-Q1 devices do not have any internal diode
path to the supply pin, which eliminates the risk of
damaging components connected to the supply pin, or
providing unintended power to the supply rail.
All logic inputs have 1.8 V logic compatible
thresholds, ensuring both TTL and CMOS logic
compatibility when operating with a valid supply
voltage. Fail-Safe Logic circuitry allows voltages on
the control pins to be applied before the supply pin,
protecting the device from potential damage.
Device Information
PART NUMBER(1)
TMUX1308-Q1
TMUX1309-Q1
(1)
PACKAGE
BODY SIZE (NOM)
TSSOP (16)
5.00 mm × 4.40 mm
SOT-23-THIN (16)
4.20 mm x 2.00 mm
WQFN (16)
3.50 mm x 2.50 mm
For all available packages, see the package option
addendum at the end of the data sheet.
TMUX130 8-Q1
S0
S1
S2
S3
S4
S5
S6
S7
TMUX130 9-Q1
D
S0A
S1A
S2A
S3A
DA
S0B
S1B
S2B
S3B
DB
1-OF-8
DECODER
A0
A1
A2
1-OF-4
DECODER
EN
A0
A1
EN
TMUX1308-Q1 and TMUX1309-Q1 Block Diagram
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2020 Texas Instruments
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings ....................................... 7
7.2 ESD Ratings .............................................................. 7
7.3 Recommended Operating Conditions ........................7
7.4 Thermal Information: TMUX1308-Q1 .........................8
7.5 Thermal Information: TMUX1309-Q1 .........................8
7.6 Electrical Characteristics ............................................9
7.7 Logic and Dynamic Characteristics ..........................10
7.8 Timing Characteristics ..............................................11
7.9 Injection Current Coupling ....................................... 12
7.10 Typical Characteristics............................................ 13
8 Detailed Description......................................................16
8.1 Overview................................................................... 16
8.2 Functional Block Diagram......................................... 22
8.3 Feature Description...................................................22
9 Application and Implementation.................................. 27
9.1 Application Information............................................. 27
9.2 Typical Application.................................................... 27
9.3 Design Requirements............................................... 28
9.4 Detailed Design Procedure....................................... 28
10 Power Supply Recommendations..............................29
11 Layout........................................................................... 29
11.1 Layout Guidelines................................................... 29
11.2 Layout Example...................................................... 30
12 Device and Documentation Support..........................31
12.1 Documentation Support.......................................... 31
12.2 Related Links.......................................................... 31
12.3 Receiving Notification of Documentation Updates..31
12.4 Support Resources................................................. 31
12.5 Trademarks............................................................. 31
12.6 Electrostatic Discharge Caution..............................31
12.7 Glossary..................................................................31
13 Mechanical, Packaging, and Orderable
Information.................................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2020) to Revision D (November 2020)
Page
• Changed the status of the TMUX1309 device from preview to production.........................................................1
• Changed ΔRON test condition to VDD / 2 ............................................................................................................9
• Changed max ΔRON spec limit for 1.8 V and 2.5 V supply................................................................................. 9
Changes from Revision B (July 2020) to Revision C (August 2020)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added the Typical Characteristics.................................................................................................................... 13
Changes from Revision A (June 2020) to Revision B (July 2020)
Page
• Added thermal information for TMUX1309-Q1................................................................................................... 8
Changes from Revision * (December 2019) to Revision A (June 2020)
Page
• Changed status From: Advanced Information To: Production Data ...................................................................1
2
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
5 Device Comparison Table
PRODUCT
DESCRIPTION
TMUX1308-Q1
8:1, 1-Channel, single-ended multiplexer
TMUX1309-Q1
4:1, 2-Channel, differential multiplexer
6 Pin Configuration and Functions
S4
1
16
VDD
S2
S6
2
15
S2
14
S1
D
3
14
S1
4
13
S0
S7
4
13
S0
5
12
S3
S5
5
12
S3
6
11
A0
6
11
A0
N.C.
7
10
A1
N.C.
7
10
A1
GND
8
9
A2
GND
8
9
A2
S4
1
16
VDD
S6
2
15
D
3
S7
S5
Not to scale
Not to scale
Figure 6-2. TMUX1308-Q1: DYY Package 16-Pin
SOT-23-THIN Top View
S6
2
D
3
S7
S4
VDD
1
16
Figure 6-1. TMUX1308-Q1: PW Package 16-Pin
TSSOP Top View
15
S2
14
S1
13
S0
5
12
S3
6
11
A0
7
10
A1
Thermal
4
GND
8
N.C.
A2
S5
9
Pad
Not to scale
Figure 6-3. TMUX1308-Q1: BQB Package 16-Pin WQFN Top View
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
Pin Functions TMUX1308-Q1
PIN
NAME
TYPE(1)
DESCRIPTION(2)
S4
1
I/O
Source pin 4. Signal path can be an input or output.
S6
2
I/O
Source pin 6. Signal path can be an input or output.
D
3
I/O
Drain pin (common). Signal path can be an input or output.
S7
4
I/O
Source pin 7. Signal path can be an input or output.
S5
5
I/O
Source pin 5. Signal path can be an input or output.
Active low logic input. When this pin is high, all switches are turned off. When this pin is low, the A[2:0]
address inputs determine which switch is turned on as shown in Table 8-1.
EN
6
I
N.C.
7
Not Connected
GND
8
P
Ground (0 V) reference
A2
9
I
Address line 2. Controls the switch configuration as shown in Table 8-1.
A1
10
I
Address line 1. Controls the switch configuration as shown in Table 8-1.
A0
11
I
Address line 0. Controls the switch configuration as shown in Table 8-1.
S3
12
I/O
Source pin 3. Signal path can be an input or output.
S0
13
I/O
Source pin 0. Signal path can be an input or output.
S1
14
I/O
Source pin 1. Signal path can be an input or output.
S2
15
I/O
Source pin 2. Signal path can be an input or output.
VDD
16
P
Thermal pad
—
Not Connected
(1)
(2)
4
NO.
Not Connected.
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
Exposed thermal pad. No requirement to solder this pad, if connected it should be left floating or tied to
GND.
I = input, O = output, I/O = input and output, P = power.
Refer to Section 8.3.6 for what to do with unused pins.
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
S0B
1
16
VDD
S2A
S2B
2
15
S2A
14
S1A
DB
3
14
S1A
4
13
DA
S3B
4
13
DA
5
12
S0A
S1B
5
12
S0A
6
11
S3A
6
11
S3A
N.C.
7
10
A0
N.C.
7
10
A0
GND
8
9
A1
GND
8
9
A1
S0B
1
16
VDD
S2B
2
15
DB
3
S3B
S1B
Not to scale
Not to scale
Figure 6-5. TMUX1309-Q1: DYY Package 16-Pin
SOT-23-THIN Top View
S0B
VDD
1
16
Figure 6-4. TMUX1309-Q1: PW Package 16-Pin
TSSOP Top View
S2B
2
15
S2A
DB
3
14
S1A
S3B
4
13
DA
5
12
S0A
6
11
S3A
7
10
A0
Thermal
GND
8
N.C.
A1
S1B
9
Pad
Not to scale
Figure 6-6. TMUX1309-Q1: BQB Package 16-Pin WQFN Top View
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
Pin Functions TMUX1309-Q1
PIN
NAME
TYPE(1)
DESCRIPTION(1)
S0B
1
I/O
Source pin 0 of mux B. Can be an input or output.
S2B
2
I/O
Source pin 2 of mux B. Can be an input or output.
DB
3
I/O
Drain pin (Common) of mux B. Can be an input or output.
S3B
4
I/O
Source pin 3 of mux B. Can be an input or output.
S1B
5
I/O
Source pin 1 of mux B. Can be an input or output.
Active low logic input. When this pin is high, all switches are turned off. When this pin is low, the A[1:0]
address inputs determine which switch is turned on.
EN
6
I
N.C.
7
Not Connected
GND
8
P
Ground (0 V) reference
A1
9
I
Address line 1. Controls the switch configuration as shown in Table 8-2.
A0
10
I
Address line 0. Controls the switch configuration as shown in Table 8-2.
S3A
11
I/O
Source pin 3 of mux A. Can be an input or output.
S0A
12
I/O
Source pin 0 of mux A. Can be an input or output.
DA
13
I/O
Drain pin (Common) of mux A. Can be an input or output.
S1A
14
I/O
Source pin 1 of mux A. Can be an input or output.
S2A
15
I/O
Source pin 3 of mux A. Can be an input or output.
VDD
16
P
Thermal pad
—
Not Connected
(1)
6
NO.
Not Connected.
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
Exposed thermal pad. No requirement to solder this pad, if connected it should be left floating or tied to
GND.
Refer to Section 8.3.6 for what to do with unused pins.
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
MAX
VDD
Supply voltage
–0.5
6
VSEL or VEN
Logic control input pin voltage (EN, A0, A1, A2)
–0.5
6
VS or VD
Source or drain voltage (Sx, D)
–0.5
VDD+0.5
ISEL or IEN
Logic control input pin current (EN, A0, A1, A2)
–30
30
IS or ID (CONT)
Continuous current through switch (Sx, D pins) –40°C to +85°C
–50
50
IS or ID (CONT)
Continuous current through switch (Sx, D pins) –40°C to +125°C
–25
25
IGND
Continuous current through GND
–100
100
Ptot
Total power dissipation(4)
Tstg
Storage temperature
TJ
Junction temperature
(1)
(2)
(3)
(4)
UNIT
V
mA
500
–65
mW
150
°C
150
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
All voltages are with respect to ground, unless otherwise specified.
For TSSOP package: Ptot derates linearily above TA = 80°C by 7.2mW/°C.
For SOT-23-THIN package: Ptot derates linearily above TA = 66°C by 6mW/°C.
For BQB package: Ptot derates linearily above TA = 102°C by 10.6mW/°C.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per
AEC Q100-002(1)
All pins
±2000
Charged device model (CDM), per
AEC Q100-011
All pins
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
Supply voltage
NOM
MAX
1.62
5.5
UNIT
V
VS or VD
Signal path input/output voltage (source or drain pin) (Sx, D)
0
VDD
V
VSEL or VEN
Logic control input pin voltage (EN, A0, A1, A2)
0
5.5
V
IS or ID (CONT)
Continuous current through switch (Sx, D pins) –40°C to +85°C
–50
50
mA
IS or ID (CONT)
Continuous current through switch (Sx, D pins) –40°C to +125°C
–25
25
mA
IOK
Current per input into source or drain pins when singal voltage exceeds
recommended operating voltage (1)
–50
50
mA
IINJ
Injected current into single off switch input
IINJ_ALL
Total injected current into all off switch inputs combined
TA
Ambient temperature
(1)
–50
50
mA
–100
100
mA
–40
125
°C
If source or drain voltage exceeds VDD, or goes below GND, the pin will be shunted to GND through an internal FET, the current must
be limited within the specified value. If Vsignal > VDD or if Vsignal < GND.
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
7.4 Thermal Information: TMUX1308-Q1
TMUX1308-Q1
THERMAL METRIC(1)
PW (TSSOP)
DYY (SOT)
BQB (WQFN)
UNIT
PINS
PINS
PINS
RθJA
Junction-to-ambient thermal resistance
139.6
167.1
94.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
77.2
106.3
92.6
°C/W
RθJB
Junction-to-board thermal resistance
84.2
90.0
64.5
°C/W
ΨJT
Junction-to-top characterization parameter
26.5
17.2
13.3
°C/W
ΨJB
Junction-to-board characterization parameter
83.8
90.0
64.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
42.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: TMUX1309-Q1
TMUX1309-Q1
THERMAL
PW (TSSOP)
DYY (SOT)
BQB (WQFN)
PINS
PINS
PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
139.6
172.4
94.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
77.2
107.0
92.6
°C/W
RθJB
Junction-to-board thermal resistance
84.2
96.1
64.5
°C/W
ΨJT
Junction-to-top characterization parameter
26.5
19.7
13.3
°C/W
ΨJB
Junction-to-board characterization parameter
83.8
95.9
64.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
42.7
°C/W
(1)
8
METRIC(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
7.6 Electrical Characteristics
At specified VDD ±10%
Typical values measured at nominal VDD
Operating free-air temperature (TA)
PARAMETER
TEST CONDITIONS
VDD
25°C
MIN
–40°C to 85°C
MIN
TYP
UNIT
–40°C to 125°C
TYP
MAX
MAX
MIN
TYP
MAX
1.8 V
650
1500
1700
1700
2.5 V
230
600
670
670
3.3 V
120
330
350
370
5V
75
195
220
270
1.8 V
10
38
45
45
2.5 V
3
20
22
22
3.3 V
2
8
11
15
5V
1
7
10
14
ANALOG SWITCH
RON
On-state
switch
resistance
ΔRON
On-state
switch
resistance
matching
between
inputs
VS = VDD / 2
ISD = 0.5 mA
Source offstate leakage
current
1.8 V
Switch Off
2.5 V
VD = 0.8 x VDD/ 0.2 x VDD
VS = 0.2 x VDD/ 0.8 x VDD 3.3 V
5V
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
CSOFF
CDOFF
CSON
CDON
VS = 0 V to VDD
ISD = 0.5 mA
Drain off-state
leakage
Switch Off
VD = 0.8 x VDD/ 0.2 x VDD
current
(common
VS = 0.2 x VDD/ 0.8 x VDD
drain pin)
Channel onstate leakage
current
Source off
capacitance
Drain off
capacitance
On
capacitance
Switch On
VD = VS = 0.8 x VDD or
VD = VS = 0.2 x VDD
VS = VDD / 2
f = 1 MHz
VS = VDD / 2
f = 1 MHz
VS = VDD / 2
f = 1 MHz
±1
–25
25
–800
800
±1
–25
25
–800
800
±1
–25
25
–800
800
±1
–25
25
–800
800
1.8 V
±1
–45
45
–800
800
2.5 V
±1
–45
45
–800
800
3.3 V
±1
–45
45
–800
800
5V
±1
–45
45
–800
800
1.8 V
±1
–45
45
–800
800
2.5 V
±1
–45
45
–800
800
3.3 V
±1
–45
45
–800
800
5V
±1
–45
45
–800
800
1.8 V
2
14
14
14
2.5 V
2
14
14
14
3.3 V
2
14
14
14
5V
2
14
14
14
1.8 V
7
37
37
37
2.5 V
7
37
37
37
3.3 V
7
37
37
37
5V
7
37
37
37
1.8 V
11
40
40
40
2.5 V
11
40
40
40
3.3 V
11
40
40
40
5V
11
40
40
40
1.8 V
1
1
1.2
2.5 V
1
1
1.5
3.3 V
1
1
2
5V
1
1.5
3
Ω
Ω
nA
nA
nA
pF
pF
pF
POWER SUPPLY
IDD
VDD supply
current
Logic inputs = 0 V or VDD
µA
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7.7 Logic and Dynamic Characteristics
At specified VDD ±10%
Typical values measured at nominal VDD and TA = 25°C.
PARAMETER
TEST CONDITIONS
VDD
Operating free-air
temperature (TA)
UNIT
–40°C to 125°C
MIN
TYP
MAX
LOGIC INPUTS (EN, A0, A1, A2)
VIH
VIL
Input logic high
Input logic low
1.8 V
0.95
5.5
2.5 V
1.1
5.5
3.3 V
1.15
5.5
5V
1.25
5.5
1.8 V
0
0.6
2.5 V
0
0.7
3.3 V
0
0.8
5V
0
0.95
IIH
Logic high input leakage current
VLOGIC = 1.8 V or VDD
All
IIL
Logic low input leakage current
VLOGIC = 0 V
All
CIN
Logic input capacitance
VLOGIC = 0 V, 1.8 V, VDD
f = 1 MHz
All
1
–1
V
V
uA
uA
1
2
pF
DYNAMIC CHARACTERISTICS
QINJ
OISO
OISO
XTALK
XTALK
BW
10
Charge Injection
Off Isolation
Off Isolation
Crosstalk
Crosstalk
Bandwidth
VS = VDD / 2
RS = 0 Ω, CL = 100 pF
VBIAS = VDD / 2
VS = 200 mVpp
RL = 50 Ω, CL = 5 pF
f = 100 kHz
VBIAS = VDD / 2
VS = 200 mVpp
RL = 50 Ω, CL = 5 pF
f = 1 MHz
VBIAS = VDD / 2
VS = 200 mVpp
RL = 50 Ω, CL = 5 pF
f = 100 kHz
VBIAS = VDD / 2
VS = 200 mVpp
RL = 50 Ω, CL = 5 pF
f = 1 MHz
VBIAS = VDD / 2
VS = 200 mVpp
RL = 50 Ω, CL = 5 pF
1.8 V
–0.5
2.5 V
–0.5
3.3 V
–1
5V
–6.5
1.8 V
–110
2.5 V
–110
3.3 V
–110
5V
–110
1.8 V
–90
2.5 V
–90
3.3 V
–90
5V
dB
dB
–90
1.8 V
–110
2.5 V
–110
3.3 V
–110
5V
–110
1.8 V
–90
2.5 V
–90
3.3 V
–90
5V
–90
1.8 V
350
2.5 V
450
3.3 V
500
5V
500
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dB
dB
MHz
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
7.8 Timing Characteristics
At specified VDD ±10%
Typical values measured at nominal VDD.
Operating free-air temperature (TA)
PARAMETER
TEST CONDITIONS
VDD
25°C
MIN
–40°C to 85°C
MIN
TYP
–40°C to 125°C
MAX
MIN
TYP
UNIT
TYP
MAX
MAX
1.8 V
15
30
30
30
2.5 V
8
15
20
20
3.3 V
5
11
15
15
5V
4
9
10
10
5V
1.5
4
5
5
1.8 V
44
94
103
103
RL = 10 kΩ, CL = 50 pF 2.5 V
Ax to D, Ax to Sx
3.3 V
30
63
67
67
SWITCHING CHARACTERISTICS
tPD
Propagation delay
CL = 50 pF
Sx to D, D to Sx
CL = 15 pF
tTRAN
Transition-time
between inputs
5V
RL = 10 kΩ, CL = 15 pF 5 V
tON(EN)
tOFF(EN)
Turnon-time from
enable
Turnoff time from
enable
54
54
43
46
46
15
39
43
43
39
64
75
75
RL = 10 kΩ, CL = 50 pF 2.5 V
EN to D, EN to Sx
3.3 V
30
45
50
50
26
38
42
42
5V
24
32
37
37
RL = 10 kΩ, CL = 15 pF 5 V
22
31
35
35
1.8 V
58
80
85
85
RL = 10 kΩ, CL = 50 pF 2.5 V
EN to D, EN to Sx
3.3 V
21
70
72
72
15
65
70
70
11
40
45
45
8
15
RL = 10 kΩ, CL = 15 pF 5 V
Break before make
time
51
18
1.8 V
5V
tBBM
23
20
ns
ns
ns
20
1.8 V
1
16
1
1
RL = 10 kΩ, CL = 15 pF 2.5 V
Sx to D, D to Sx
3.3 V
1
22
1
1
1
24
1
1
1
33
1
1
5V
ns
ns
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
7.9 Injection Current Coupling
At specified VDD ±10%
Typical values measured at nominal VDD and TA = 25°C.
PARAMETER
VDD
TEST CONDITIONS
-40°C to 125°C
MIN
TYP
MAX
0.01
1
0.05
1
0.1
1
0.01
2
UNIT
INJECTION CURRENT COUPLING
1.8 V
3.3 V
RS ≤ 3.9 kΩ IINJ ≤ 1 mA
5V
1.8 V
3.3 V
ΔVOUT
Maximum shift of output voltage
of enabled analog input
I ≤ 10
RS ≤ 3.9 kΩ INJ
mA
0.3
3
5V
0.06
4
1.8 V
0.05
2
0.05
2
3.3 V
RS ≤ 20 kΩ IINJ ≤ 1 mA
5V
1.8 V
3.3 V
RS ≤ 20 kΩ
IINJ ≤ 10
mA
5V
12
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0.1
2
0.05
15
0.05
15
0.02
15
mV
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
7.10 Typical Characteristics
at TA = 25°C, VDD = 5 V (unless otherwise noted)
270
370
TA
TA
TA
TA
TA = 125qC
TA = 85qC
TA = 25qC
TA = 40qC
320
On Resistance (:)
On Resistance (:)
220
= 125qC
= 85qC
= 25qC
= 40qC
170
120
270
220
170
120
70
70
20
20
0
1
2
3
4
VS or VD - Source or Drain Voltage (V)
0
5
0.5
D001
1
1.5
2
2.5
3
VS or VD - Source or Drain Voltage (V)
VDD = 5 V
Figure 7-1. On-Resistance vs Temperature
Figure 7-2. On-Resistance vs Temperature
530
700
650
600
550
500
450
400
350
300
250
200
150
100
50
TA = 125qC
TA = 85qC
TA = 25qC
TA = 40qC
430
380
On Resistance (:)
On Resistance (:)
D002
VDD = 3.3 V
480
330
280
230
180
130
80
30
0
0.5
1
1.5
2
VS or VD - Source or Drain Voltage (V)
VDD =
VDD =
VDD =
VDD =
0
2.5
0.5
D003
1
1.5
2
2.5
3
3.5
4
VS or VD - Source or Drain Voltage (V)
VDD = 2.5 V
Figure 7-3. On-Resistance vs Temperature
900
Capacitance (pF)
800
700
600
500
400
300
200
100
0
0.5
1
1.5
4.5
5
D005
Figure 7-4. On-Resistance vs Source or Drain Voltage
VDD = 5.5 V
VDD = 5 V
VDD = 3.3 V
VDD = 1.8 V
1000
0
5V
3.3 V
2.5 V
1.8 V
TA = 25°C
1100
Supply Current (PA)
3.5
2 2.5 3
3.5
Logic Voltage (V)
4
4.5
5
5.5
D006
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0.3
CON
CSOFF
CDOFF
0.6
0.9
1.2
1.5
1.8
2.1
2.4
VS or VD - Source or Drain Voltage (V)
.
2.7
3
D013
VDD = 3.3 V
Figure 7-5. Supply Current vs Logic Voltage
Figure 7-6. Capacitance vs Source Voltage
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
10m
TON(EN)
TOFF(EN)
70
60
1m
Time (ns)
Supply Current (A)
80
VDD = 5.5 V
VDD = 5 V
VDD = 3.3 V
VDD = 1.8 V
100m
100P
10P
50
40
30
1P
20
100n
100
1k
100k
10k
Frequency (Hz)
1M
10
-40
10M
-20
0
20
D012
TA = 25°C
40
60
80
Temperature (qC)
100
120
140
D007
VDD = 3.3 V
Figure 7-7. Supply Current vs Input Switching Frequency
Figure 7-8. TON(EN) and TOFF(EN) vs Temperature
40
50
Transiton_Falling
Transiton_Rising
45
Transiton_Falling
Transiton_Rising
Transition Time (ns)
Transition Time (ns)
35
40
35
30
25
20
30
25
20
15
10
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
15
-40
5.5
-20
0
D008
TA = 25°C
20
40
60
80
Temperature (qC)
100
120
140
D009
TA = 25°C
Figure 7-9. TTRANSITION vs Supply Voltage
Figure 7-10. TTRANSITION vs Temperature
-20
-4
-30
-40
Magnitude (dB)
Gain (dB)
-5
-6
-7
-50
-60
-70
-80
-90
-100
-8
-110
-9
100k
1M
10M
Frequency (Hz)
100k
D010
TA = 25°C
1M
10M
Frequency (Hz)
100M
1G
D014
D001
TA = 25°C , VDD = 3.3 V
Figure 7-11. On Response vs Frequency
14
-120
10k
100M
Figure 7-12. Xtalk and Off-Isolation vs Frequency
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
16
VDD = 5 V
VDD = 3.3 V
VDD = 1.8 V
14
12
'VOUT (PV)
10
8
6
4
2
0
-2
0
5
10
15
20
25
30
Current (mA)
35
40
45
50
D011
VS = (VDD/2), TA = 25°C
Figure 7-13. Injection Current vs Maximum Output Voltage shift
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
8 Detailed Description
8.1 Overview
8.1.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol R ON is used to denote onresistance. The measurement setup used to measure R ON is shown below. Voltage (V) and current (I SD) are
measured using this setup, and RON is computed as shown in Figure 8-1 with RON = V / ISD:
V
ISD
Sx
D
VS
Figure 8-1. On-Resistance Measurement Setup
8.1.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current.
2. Drain off-leakage current.
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF).
The setup used to measure both off-leakage currents is shown in Figure 8-2.
Is (OFF)
VDD
VDD
VDD
VDD
S0
S0
A
ID (OFF)
D
D
VS
S6
A
S6
S7
S7
VS
VD
VD
GND
GND
Figure 8-2. Off-Leakage Measurement Setup
16
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
8.1.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON).
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON).
Either the source pin or drain pin is left floating during the measurement. Figure 8-3 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON).
VDD
VDD
VDD
S0
N.C.
VDD
IS (ON)
S0
A
ID (ON)
S1
S1
D
D
A
N.C.
S7
S7
Vs
VS
VS
VD
GND
GND
Figure 8-3. On-Leakage Measurement Setup
8.1.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 50% after the address signal
has risen or fallen past the 50% threshold. Figure 8-4 shows the setup used to measure transition time, denoted
by the symbol tTRANSITION.
VDD
0.1…F
VDD
VSEL
tr < 5ns
50%
50%
tf < 5ns
VDD
S0
D
0V
OUTPUT
S1
tTRAN_HIGH
tTRAN_LOW
RL
CL
S7
Output
50%
50%
A0
0V
tTRAN = max ( tTRAN_HGH, tTRAN_LOW)
A1
EN
VSEL
A2
GND
Figure 8-4. Transition-Time Measurement Setup
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8.1.5 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. Figure 8-5 shows
the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM).
VDD
0.1…F
VDD
Input Select
(VSEL)
tr < 5ns
S0
VDD
tf < 5ns
D
OUTPUT
S1-S6
0V
RL
CL
S7
90%
Output
tBBM_1
tBBM_2
A0
0V
A1
tBBM = min ( tBBM_1, tBBM_2)
EN
VSEL
A2
GND
Figure 8-5. Break-Before-Make Delay Measurement Setup
8.1.6 tON(EN) and tOFF(EN)
Turn-on time is defined as the time taken by the output of the device to rise to 10% after the enable has risen
past the 50% threshold. The 10% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. Figure 8-6 shows
the setup used to measure transition time, denoted by the symbol tON(EN).
Turn-off time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen
past the 50% threshold. The 90% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. Figure 8-6 shows
the setup used to measure transition time, denoted by the symbol tOFF(EN).
VDD
0.1…F
VDD
VEN
tf < 5ns
50%
50%
tr < 5ns
VDD
S0
D
0V
OUTPUT
S1
RL
CL
S7
tON (EN)
tOFF (EN)
90%
A0
EN
OUTPUT
A1
VEN
A2
10%
GND
0V
Figure 8-6. Turn-On and Turn-Off Time Measurement Setup
18
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
8.1.7 Charge Injection
The TMUX1308-Q1 and TMUX1309-Q1 device have a transmission-gate topology. Any mismatch in capacitance
between the NMOS and PMOS transistors results in a charge injected into the drain or source during the falling
or rising edge of the gate signal. The amount of charge injected into the source or drain of the device is known
as charge injection, and is denoted by the symbol Q C. Figure 8-7 shows the setup used to measure charge
injection from source (Sx) to drain (D).
VDD
0.1…F
VDD
VDD
VS
S0
VEN
S5
OUTPUT
D
0V
S6
CL
S7
Output
VOUT
VOUT
VS
QC = C L ×
VOUT
EN
A0
A1
VEN
A2
GND
Figure 8-7. Charge-Injection Measurement Setup
8.1.8 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. Figure 8-8 shows the setup used to measure, and the equation to compute off
isolation.
0.1µF
NETWORK
VDD
VS
ANALYZER
50Q
S
VSIG
D
VOUT
RL
50Q
SX
GND
RL
50Q
Figure 8-8. Off Isolation Measurement Setup
Off Isolation
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
(1)
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
8.1.9 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. Figure 8-9 shows the setup used to measure, and the equation used to
compute crosstalk.
0.1µF
NETWORK
VDD
ANALYZER
S1
VOUT
RL
D
50Q
VS
RL
S2
50Q
50Q
VSIG
SX
RL
GND
50Q
Figure 8-9. Channel-to-Channel Crosstalk Measurement Setup
Channel-to-Channel Crosstalk
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
(2)
8.1.10 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure
8-10 shows the setup used to measure bandwidth.
0.1µF
NETWORK
VDD
VS
ANALYZER
50Q
S
VSIG
D
VOUT
RL
SX
50Q
GND
RL
50Q
Figure 8-10. Bandwidth Measurement Setup
Attenuation
20
§V ·
20 ˜ Log ¨ 2 ¸
© V1 ¹
(3)
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SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
8.1.11 Injection Current Control
Injection current is measured at the change in output of the enabled signal path when an current is injected into
a disabled signal path. Figure 8-11 shows the setup used to measure Injection current control.
VDD
Any OFF input
VINPUT_2 < GND or
VINPUT_2 > VDD
VINPUT_2
S0
S1
IINJ
S2
S3
D
VOUT = VINPUT_1 ± ûVOUT
S4
S5
VOUT
S6
VINPUT_1
S7
RS
VS
EN
A0 A1 A2
Figure 8-11. Injection current Measurement Setup
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8.2 Functional Block Diagram
The TMUX1308-Q1 is an 8:1, single-ended (1-channel), mux. The TMUX1309-Q1 is a 4:1, differential (2channel) mux. Each channel is turned on or turned off based on the state of the address lines and enable pin.
TMUX130 8-Q1
S0
S1
S2
S3
S4
S5
S6
S7
TMUX130 9-Q1
D
S0A
S1A
S2A
S3A
DA
S0B
S1B
S2B
S3B
DB
1-OF-8
DECODER
A0
A1
A2
1-OF-4
DECODER
EN
A0
A1
EN
Figure 8-12. TMUX1308-Q1 and TMUX1309-Q1 Functional Block Diagram
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX1308-Q1 and TMUX1309-Q1 devices conduct equally well from source (Sx) to drain (Dx) or from
drain (Dx) to source (Sx). Each signal path has very similar characteristics in both directions so they can be used
as both multiplexers and demultiplexer to supports both analog and digital signals.
8.3.2 Rail-to-Rail Operation
The valid signal path input and output voltage for the TMUX1308-Q1 and TMUX1309-Q1 ranges from GND to V
DD.
8.3.3 1.8 V Logic Compatible Inputs
The TMUX1308-Q1 and TMUX1309-Q1 support 1.8-V logic compatible control for all logic control inputs. The
logic input thresholds scale with supply but still provide 1.8-V logic control when operating at 5.5-V supply
voltage. 1.8-V logic level inputs allows the multiplexers to interface with processors that have lower logic I/O rails
and eliminates the need for an external voltage translator, which saves both space and BOM cost. The current
consumption of the TMUX1308-Q1 and TMUX1309-Q1 devices increase when using 1.8-V logic with higher
supply voltage. For more information on 1.8-V logic implementations refer to Simplifying Design with 1.8 V logic
Muxes and Switches.
8.3.4 Fail-Safe Logic
The TMUX1308-Q1 and TMUX1309-Q1 device have Fail-Safe Logic on the control input pins (EN, A0, A1, and
A2) allowing for operation up to 5.5-V, regardless of the state of the supply pin. This feature allows voltages on
the control pins to be applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic
minimizes system complexity by removing the need for power supply sequencing on the logic control pins. For
example, the Fail-Safe Logic feature allows the select pins of the TMUX1308-Q1 and TMUX1309-Q1 to be
ramped to 5.5-V while VDD = 0-V. Additionally, the feature enables operation of the multiplexers with VDD = 1.8-V
while allowing the select pins to interface with a logic level of another device up to 5.5-V, eliminating the potential
need for an external voltage translator.
8.3.5 Injection Current Control
Injection current is the current that is being forced into a pin by an input voltage (V IN) higher than the positive
supply (V DD + ∆V) or lower than ground (V SS). The current flows through the input protection diodes into
whichever supply of the device potentially compromising the accuracy and reliability of the system. Injected
currents can come from various sources depending on the application.
22
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•
•
SCDS414D – DECEMBER 2019 – REVISED NOVEMBER 2020
Harsh environments and applications with long cabling, such as in factory automation and automotive
systems, may be susceptible to injected currents from switching or transient events.
Other self-contained systems can also be subject to injected current if the input signal is coming from various
sensors or current sources.
Injected Current Impact: Typical CMOS switches have ESD protection diodes on the inputs and outputs. These
diodes not only serve as ESD protection but also provide a voltage clamp to prevent the inputs or outputs going
above V DD or below GND/VSS. When current is injected into the pin of a disabled signal path, a small amount of
current goes thorough the ESD diode but most of the current goes through conduction to the Drain. If forward
diode voltage of the ESD diode (VF) is greater than the PMOS threshold voltage (VT), the PMOS of all OFF
switches turns ON and there would be undesirable subthreshold leakage between the source and the drain that
can lift the OFF source pins up also. Figure 8-13 shows a simplified diagram of typical CMOS switch and
associated injected current path:
Log ic D ecode
Block
Injected curren t into
uns elected s witch input
n
S0
Som e c urre nt goe s
throug h ES D
S1
M ost c urre nt goe s throug h
a s conduc ti on
ESD
p
S2
S3
D
Drain voltage
VDD + VF (ESD)
S4
ESD
S5
S6
Log ic D ecode
Block
n
S7
Selected switch input
ESD
p
VDD (PMOS gate voltage)
Figure 8-13. Simplified Diagram of Typical CMOS Switch and Associated Injected Current Path
It is quite difficult to cut off these current paths. The drain pin can never be allowed to exceed the voltage above
V DD by more than a VT. Analog pins can be protected against current injection by adding external components
like Schottky diode from Drain pin to ground to clamp the drain voltage at < VDD + VT to cut off the current path.
Change in RON due to Current Injection: Because the ON resistance of the enabled FET switch is impacted by
the change in the supply rail, when the drain pin voltage exceeds the supply voltage by more than a VT, an error
in the output signal voltage can be expected. This undesired change in the output can cause issues related to
false trigger events and incorrect measurement readings, potentially compromising the accuracy and reliability of
the system. As shown in Figure 8-14, S2 is the enabled signal path that is conducting a signal from S2 pin to D
pin. Because there is an injected current at the disabled S1 pin, the voltage at that pin increases above the
supply voltage and the ESD protection diode is forward biased, shifting the power supply rail. This shift in supply
voltage alters the RON of the internal FET switches, causing a ∆V error on the output at the D pin.
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VDD
+ûV error
VD
VS2
II/O
S1
OFF
D
-ûV error
S2
ON
VS2
Figure 8-14. Injected Current Impact on RON
To avoid the complications of added external protection to your system, the TMUX1308-Q1 and TMUX1309-Q1
devices have an internal injection current control feature which eliminates the need for external diode/resistor
networks typically used to protect the switch and keep the input signals within the supply voltage. The internal
injection current control circuitry allows signals on disabled signal paths to exceed the supply voltage without
affecting the signal of the enabled signal path. The injection current control circuitry also protects the TMUX13xxQ1 from currents injected into disabled signal paths without impacting the enabled signal path, which typical
CMOS switches do not support. Additionally, the TMUX1308-Q1 and TMUX1309-Q1 do not have any internal
diode paths to the supply pin, which eliminates the risk of damaging components connected to the supply pin, or
providing unintended power to the system supply rail. Figure 8-12 shows a simplified diagram of one signal path
for the TMUX13xx-Q1 devices and the associated injection current circuit.
Log ic D ecode
Block
n
Control
Circuitry
ESD
Simplified injection curr ent circuitry
p
Control
Circuitry
ESD
Simplified injection curr ent circuitry
Figure 8-15. Simplified Diagram of Injection Current Control
The injection current control circuitry is independently controlled for each source or drain pin (Sx, D). The control
circuitry for a particular pin is enabled when that input is disabled by the logic pins and the injected current
causes the voltage at the pin to be above VDD or below GND. The injection current circuit includes a FET to
shunt undesired current to GND in the case of overvoltage or injected current events. Each injection current
circuit is rated to handle up to 50 mA, however the device can support a maximum current of 100 mA at any
given time. Depending on the system application, a series limiting resistor may be needed and must be sized
appropriately. Figure 8-15 shows the TMUX13xx-Q1 protection circuitry with an injected current at an input pin.
24
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Log ic D ecode
Block
Injected current into
unselected switch input
n
Control
Circuitry
ESD
IIN J
Control
Circuitry
p
Simplified injection curr ent circuitry
ESD
Simplified injection curr ent circuitry
Figure 8-16. Injected Current at Input Pin
Figure 8-17 shows an example of using a series limiting resistor in the case of an overvoltage event.
Log ic D ecode
Block
VIN PU T > VDD or
VIN PU T < GND
n
RLIM
VIN PU T
ESD
Control
Circuitry
Control
Circuitry
p
Simplified injection curr ent circuitry
ESD
Simplified injection curr ent circuitry
Figure 8-17. Over-voltage Event with Series Resistor
If the voltage at the source or drain pins is greater than VDD, or less than GND, the protection FET will be turned
on for any disabled signal path and shunt the pin the GND. In this event, a series resistor is needed to limit the
total current injected into the device to be less than 100 mA. Two example scenarios are:
8.3.5.1 TMUX13xx-Q1 is Powered and the Input Signal is Greater Than VDD (VDD = 5 V, VINPUT = 5.5 V)
A typical CMOS switch would have an internal ESD diode to the supply pin rated for about ≈30 mA that would be
turned on and a series limited resistor would be needed. However, any conducted current would be injected into
the supply rail potentially damaging the system, unexpectedly turning on other devices on the same supply rail,
or requiring additional components for protection. The TMUX13xx-Q1 implementation also handles this scenario
with a series limiting resistor, however, the current path is now to GND which doesn’t have the same issues as
the current injected into the supply rail.
8.3.5.2 TMUX13xx-Q1 is Unpowered and the Input Signal has a Voltage Present (VDD = 0 V, VINPUT = 3 V)
Many CMOS switches are unable to support a voltage at the input without a valid supply voltage present
otherwise the voltage will be coupled from input to output and could damage downstream devices or impact
power-sequencing. The TMUX13xx-Q1 circuitry can handle an input signal present without a supply voltage
while minimizing power transfer from the input to output of the switch. By limiting the output voltage coupling to
400 mV the TMUX1308-Q1 and TMUX1309-Q1 help reduce the chance of conduction through any downstream
ESD diodes.
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8.3.6 Device Functional Modes
When the EN pin of the TMUX1308-Q1 is pulled low, one of the switches is closed based on the state of the
address lines. Similarly, when the EN pin of the TMUX1309-Q1 is pulled low, two of the switches are closed
based on the state of the address lines. When the EN pin is pulled high, all the switches are in an open state
regardless of the state of the address lines.
Unused logic control pins must be tied to GND or VDD in order to ensure the device does not consume additional
current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx and Dx)
should be connected to GND.
8.3.7 Truth Tables
Table 8-1 and Table 8-2 show the truth tables for the TMUX1308-Q1 and TMUX1309-Q1 respectively.
Table 8-1. TMUX1308-Q1 Truth Table
EN
A2
A1
A0
Selected Signal Path Connected To Drain
(D) Pin
0
0
0
0
S0
0
0
0
1
S1
0
0
1
0
S2
0
0
1
1
S3
0
1
0
0
S4
0
1
0
1
S5
0
1
1
0
S6
0
1
1
1
S7
1
X(1)
X(1)
X(1)
All channels are off
(1)
X denotes don't care.
Table 8-2. TMUX1309-Q1 Truth Table
EN
A1
A0
Selected Signal Path Connected To Drain (DA
and DB) Pins
0
0
0
S0A to DA
S0B to DB
0
0
1
S1A to DA
S1B to DB
0
1
0
S2A to DA
S2B to DB
0
1
1
S3A to DA
S3B to DB
1
(1)
26
X(1) X(1)
All channels are off
X denotes don't care.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TMUX13xx-Q1 family offers protection against injection current invents across a wide operating supply
range (1.62 V to 5.5 V). These devices include 1.8 V logic compatible control input pins that enable operation in
systems with 1.8 V I/O rails. Additionally, the control input pins support Fail-Safe Logic which allows for operation
up to 5.5 V, regardless of the state of the supply pin. This feature stops the logic pins from back-powering the
supply rail while the injection current circuitry prevents the signal path from back-powering the supply. These
features make the TMUX13xx-Q1 a family of general purpose multiplexers and switches that can reduce system
complexity, board size, and overall system cost.
9.2 Typical Application
One useful application to take advantage of the TMUX13xx-Q1 features is multiplexing various physical switches
in a body control module (BCM) or electronic control unit (ECU). Automotive BCMs are complex systems
designed to manage numerous functions such as lighting, door locks, windows, wipers, turn signals and many
more inputs. The BCM monitors these physical switches and controls power to various loads within the vehicle.
A CMOS multiplexer can be used to multiplex the inputs and minimize the number of GPIO or ADC inputs
needed by an onboard MCU. Figure 9-1 shows a typical BCM system using the TMUX1308-Q1 to multiplex
system inputs.
D1
Electronic Control Unit (ECU)
VBAT V
CBUFF
CVBAT
Wetting Current
Control Circuity
FET
FET
RWETT
R1
CX
DX
R2
Rx
S8
CX
DX
Rx
TMUX1308-Q1
S1
…C
Logic x3
Figure 9-1. Multiplexing BCM Inputs
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9.3 Design Requirements
For this design example, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
PARAMETERS
VALUES
Supply (VDD)
5.0 V
I/O signal range
0 V to VDD (Rail to Rail)
Control logic thresholds
1.8 V compatible
Switch inputs
Eight
9.4 Detailed Design Procedure
The TMUX1308-Q1 has an internal injection current control feature which eliminates the need for external diode/
resistor networks typically used to protect the switch and keep the input signals within the supply voltage. The
internal injection current control circuitry allows signals on disabled signal paths to exceed the supply voltage
without affecting the signal of the enabled signal path. Injected currents can come from various sources such as
from long cabling in automotive systems that may be susceptible to induced currents from switching or transient
events. Another momentary source of injected currents in BCMs are wetting currents, which are small currents
used to prevent oxidation on metal switch contacts or wires. A switch without injection current control can have
the measured output of the enabled signal path impacted if a current is injected into a disabled signal path. This
undesired change in the output can cause issues related to false trigger events and incorrect measurement
readings which can compromise the accuracy and reliability of the BCM system. Figure 9-2 shows a detailed
BCM application.
DBATT
VBAT
12V
VBATT
12 kO
V
10 kO
CBUFF
CVBAT
2.7 nF
RWETT
1.2 kO
1.2 kO
20 kO
S0
10 nF
15 kO
20 kO
S8
10 nF
D8
15 kO
TMUX1308-Q1
S1
D1
…C
D
A2
S7
A1
A0
Figure 9-2. Detailed BCM Application
The BCM uses the 12 V battery voltage to provide a wetting current to each switch when the associated control
circuitry is enabled by the micro controller. The wetting current is sized by the RWETT and the required value may
vary depending on the type physical switch being monitoried. The 20 kΩ and 15 kΩ resistors are used in addition
to the wetting resistor to create a voltage divider before the input of the multiplexer incase of a short to battery
condition. The resistor values are selected to maintain the voltage at the switch signal path below VDD. The 20
kΩ series resistor also limits the amount of injected current into the switch if an overvotlage event occurs. Diodes
D1 through D8 are used to prevent back flow of current in case a secondary system is monitoring the same
physical switches for backup or redundancy reasons. The 10 nF capacitors are used for initial ESD protection in
the system and must be sized based on system level requirements.
28
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The logic address pins are controlled by the micro controller to cycle between the eight switch inputs in the
system. If the parts desired power-up state is disabled, the enable pin should have a weak pull-up resistor and
be controlled by the MCU through the GPIO.
10 Power Supply Recommendations
The TMUX1308-Q1 and TMUX1309-Q1 devices operate across a wide supply range of 1.62 V to 5.5 V. Note: do
not exceed the absolute maximum ratings because stresses beyond the listed ratings can cause permanent
damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the V DD supply
to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from V DD to
ground. Place the bypass capacitors as close to the power supply pins of the device as possible using lowimpedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low
equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes.
For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting
the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers
the overall inductance and is beneficial for connections to ground planes.
11 Layout
11.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight; therefore, some traces must turn
corners. Figure 11-1 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
BETTER
BEST
2W
WORST
1W min.
W
Figure 11-1. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance
changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via
introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference
from the other layers of the board. Be careful when designing test points, through-hole pins are not
recommended at high frequencies.
Figure 11-2 illustrates an example of a PCB layout with the TMUX1308-Q1 and TMUX1309-Q1. Some key
considerations are:
•
•
•
Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
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•
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
Via to G ND plane
Wide (low inductance)
trace for power
Wide (low inductance)
trace for power
C
C
S4
VDD
S0B
VDD
S6
S2
S2B
S2A
D
S1
DB
S1A
S0
S3B
S5
S3
S1B
S0A
EN
A0
EN
S3A
N.C.
A1
N.C.
A0
GND
A2
GND
A1
S7
TMUX130 8-Q1
TMUX130 9-Q1
DA
Figure 11-2. TMUX1308-Q1 and TMUX1309-Q1 Layout Example
30
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.
Texas Instruments, QFN/SON PCB Attachment.
Texas Instruments, Quad Flatpack No-Lead Logic Packages.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 12-1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TMUX1308-Q1
Click here
Click here
Click here
Click here
Click here
TMUX1309-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32
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PACKAGE OPTION ADDENDUM
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4-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMUX1308QBQBRQ1
ACTIVE
WQFN
BQB
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1308Q
TMUX1308QDYYRQ1
ACTIVE
SOT-23-THIN
DYY
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TMUX1308Q
TMUX1308QPWRQ1
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TM1308Q
TMUX1309QBQBRQ1
ACTIVE
WQFN
BQB
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1309Q
TMUX1309QDYYRQ1
ACTIVE
SOT-23-THIN
DYY
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TMUX1309Q
TMUX1309QPWRQ1
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TM1309Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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