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TMUX1574
SCDS391C – OCTOBER 2018 – REVISED DECEMBER 2019
TMUX1574 Low-Capacitance, 2:1 (SPDT) 4-Channel,
Powered-Off Protected Switch with 1.8 V Logic
1 Features
3 Description
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The TMUX1574 is a complementary metal-oxide
semiconductor (CMOS) switch. The TMUX1574
offers 2:1 SPDT switch configuration with 4-channels.
Wide operating supply of 1.5 V to 5.5 V allows for use
in a broad array of applications from servers and
communication equipment to industrial applications.
The device supports bidirectional analog and digital
signals on the source (SxA, SxB) and drain (Dx) pins
and can pass signals above supply up to VDD x 2,
with a maximum input/output voltage of 5.5 V.
1
Wide supply range: 1.5 V to 5.5 V
Low on-capacitance: 7.5 pF
Low on-resistance: 2 Ω
High bandwidth: 2 GHz
-40°C to +125°C operating temperature
1.8 V Logic Compatible
Supports Input Voltage Beyond Supply
Integrated Pull Down Resistor on Logic Pins
Bidirectional Signal Path
Fail-Safe Logic
Powered-off Protection up to 3.6 V Signals
– Pinout compatible to SN74CBTLV3257
2 Applications
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Powered-off Protection up to 3.6 V on the signal path
of the TMUX1574 provides isolation when the supply
voltage is removed (VDD = 0 V). Without this
protection feature, switches can back-power the
supply rail through an internal ESD diode and cause
potential damage to the system.
Fail-Safe Logic circuitry allows voltages on the logic
control pins to be applied before the supply pin,
protecting the device from potential damage. All
control inputs have 1.8 V logic compatible thresholds,
ensuring both TTL and CMOS logic compatibility
when operating in the valid supply voltage range.
Integrated pull down resistor on the logic pins
removes external components to reduce system size
and cost.
Flash memory sharing
JTAG multiplexing
SPI multiplexing
eMMC multiplexing
Servers
Data center switches & routers
Wireless infrastructure
PC & notebooks
Building automation
Grid infrastructure
ePOS
Appliances
Device Information(1)
PART NUMBER
TMUX1574
PACKAGE
BODY SIZE (NOM)
TSSOP (16)
5.00 mm × 4.40 mm
UQFN (16)
2.60 mm x 1.80 mm
SOT-23-THIN (16)
4.20 mm x 2.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Application Example
VDD
VI/O
0.1µF
TMUX1574
VDD
Processor
S1A
S2A
S3A
S4A
D1
RAM
JTAG
DEBUG,
SPI, GPIO
CPU
D2
S1B
S2B
S3B
S4B
D4
GND
SPI / JTAG / UART
Device #1
S1A
S1B
D1
MISO / TDI / GPIO
MOSI / TDO / GPIO
SCLK / TCK / GPIO
SS / TMS / GPIO
S2A
S2B
D2
S3A
S3B
D3
S4A
S4B
D4
SPI / JTAG / UART
Device #2
D3
Peripherals
1.8V Logic
I/O
Block Diagram
SEL
EN
GND
MISO / TDI / GPIO
MOSI / TDO / GPIO
SCLK / TCK / GPIO
SS / TMS / GPIO
LOGIC CONTROL*
SEL
EN
*Internal 6MO Pull-Down on Logic Pins
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX1574
SCDS391C – OCTOBER 2018 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5
5
5
5
6
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dynamic Characteristics ...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 14
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
On-Resistance ........................................................ 14
Off-Leakage Current ............................................... 14
On-Leakage Current ............................................... 15
IPOFF Leakage Current ............................................ 15
Transition Time ....................................................... 16
tON (EN) and tOFF (EN) Time....................................... 16
tON (VDD) and tOFF (VDD) Time................................... 17
Break-Before-Make Delay....................................... 17
Propagation Delay................................................... 18
Skew ..................................................................... 18
Charge Injection .................................................... 19
7.12
7.13
7.14
7.15
8
19
20
20
21
Detailed Description ............................................ 22
8.1
8.2
8.3
8.4
8.5
9
Capacitance ..........................................................
Off Isolation ...........................................................
Channel-to-Channel Crosstalk ..............................
Bandwidth .............................................................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Truth Tables ............................................................
22
22
22
24
24
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application ................................................. 25
10 Power Supply Recommendations ..................... 26
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 28
12 Device and Documentation Support ................. 29
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2019) to Revision C
Page
•
Added prop delay and skew specs for DYY package ........................................................................................................... 8
•
Changed Figure 20 to include prop. delay and skew for DYY package .............................................................................. 12
Changes from Revision A (December 2018) to Revision B
Page
•
Added the SOT-23-THIN (DYY) package to the data sheet .................................................................................................. 1
•
Added thermal information for DYY package. ........................................................................................................................ 5
Changes from Original (October 2018) to Revision A
•
2
Page
Changed the document status From: Advanced Information To: Production data ................................................................ 1
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SCDS391C – OCTOBER 2018 – REVISED DECEMBER 2019
5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
DYY Package
16-Pin SOT-23-THIN
Top View
SEL
1
16
VDD
SEL
1
16
VDD
S1A
2
15
EN
S1A
2
15
EN
S1B
3
14
S4A
S1B
3
14
S4A
D1
4
13
S4B
D1
4
13
S4B
S2A
5
12
D4
S2B
6
11
S3A
S3B
S2A
5
12
D4
S2B
6
11
S3A
D2
7
10
D2
7
10
S3B
GND
8
9
GND
8
9
D3
D3
Not to scale
S1B
EN
VDD
14
1
13
SEL
15
16
S1A
RSV Package
16-Pin UQFN
Top View
12
S4A
S4B
S2A
3
10
D4
S2B
4
9
8
S3A
S3B
D3
GND
D2
7
11
6
2
5
D1
Not to scale
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SCDS391C – OCTOBER 2018 – REVISED DECEMBER 2019
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Pin Functions
PIN
TYPE (1)
DESCRIPTION (2)
TSSOP /
SOT-23-THIN
UQFN
SEL
1
15
I
S1A
2
16
I/O
Source pin 1A. Can be an input or output.
S1B
3
1
I/O
Source pin 1B. Can be an input or output.
D1
4
2
I/O
Drain pin 1. Can be an input or output.
S2A
5
3
I/O
Source pin 2A. Can be an input or output.
S2B
6
4
I/O
Source pin 2B. Can be an input or output.
D2
7
5
I/O
Drain pin 2. Can be an input or output.
GND
8
6
P
D3
9
7
I/O
Drain pin 3. Can be an input or output.
S3B
10
8
I/O
Source pin 3B. Can be an input or output.
S3A
11
9
I/O
Source pin 3A. Can be an input or output.
D4
12
10
I/O
Drain pin 4. Can be an input or output.
S4B
13
11
I/O
Source pin 4B. Can be an input or output.
S4A
14
12
I/O
Source pin 4A. Can be an input or output.
EN
15
13
I
Active low enable: When this pin is high, all switches are turned off. When this pin is low,
SEL pin controls the signal path selection. Internal 6 MΩ pull-down to GND.
VDD
16
14
P
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and
GND.
NAME
(1)
(2)
4
Select pin: controls state of switches according to Table 1. Internal 6 MΩ pull-down to
GND.
Ground (0 V) reference
I = input, O = output, I/O = input and output, P = power
Refer to Device Functional Modes for what to do with unused pins.
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SCDS391C – OCTOBER 2018 – REVISED DECEMBER 2019
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). (1) (2) (3)
MIN
MAX
VDD
Supply voltage
–0.5
6
VSEL or VEN
Logic control input pin voltage (SEL or EN)
–0.5
6
V
ISEL or IEN
Logic control input pin current (SEL or EN)
–30
30
mA
VS or VD
Source or drain pin voltage
–0.5
6
V
IS or ID (CONT)
Source and drain pin continuous current: (SxA, SxB, Dx)
–25
25
mA
Tstg
Storage temperature
–65
150
°C
TJ
Junction temperature
150
°C
(1)
(2)
(3)
UNIT
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
±2000
Charged-device model (CDM), per JEDEC specification
JESD22-C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
UNIT
VDD
Supply voltage
1.5
5.5
V
VS or VD
Signal path input/output voltage (source or drain pin), VDD ≥ 1.5 V (1)
0
VDD x 2
V
VS_off or VD_off
Signal path input/output voltage (source or drain pin), VDD < 1.5 V (2)
0
3.6
V
VSEL or VEN
Logic control input voltage (EN, SEL)
0
5.5
V
TA
Ambient temperature
–40
125
ºC
(1)
(2)
Device input and output can operate up to VDD x 2, with a maximum input and output voltage of 5.5 V.
VS_off and VD_off refers to the voltage at the source or drain pins when supply is less than 1.5 V.
6.4 Thermal Information
THERMAL METRIC (1)
DEVICE
DEVICE
DEVICE
PW (TSSOP)
DYY (SOT-23)
RSV (UQFN)
UNIT
16 PINS
16 PINS
16 PINS
RθJA
Junction-to-ambient thermal resistance
117.4
123.0
129.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
47.9
70.5
69.7
°C/W
RθJB
Junction-to-board thermal resistance
63.7
50.4
58.7
°C/W
ΨJT
Junction-to-top characterization parameter
6.9
5.0
3.6
°C/W
ΨJB
Junction-to-board characterization parameter
63.1
50.3
56.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SCDS391C – OCTOBER 2018 – REVISED DECEMBER 2019
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6.5 Electrical Characteristics
VDD = 1.5 V to 5.5 V, GND = 0V, TA = –40°C to +125°C
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VDD
Power supply voltage
1.5
IDD
Active supply current
VSEL = 0 V, 1.4V or VDD
VS = 0 V to 5.5 V
IDD_STANDB
Supply current when disabled
VEN = 1.4 V or VDD
VS = 0 V to 5.5 V
Y
5.5
V
40
68
μA
7.5
15
µA
DC CHARACTERISTICS
RON
On-resistance
VS = 0 V to VDD*2
VS(max) = 5.5 V
ISD = 8 mA
Refer to ON-State Resistance Figure
2
4.5
Ω
ΔRON
On-resistance match between channels
VS = VDD
ISD = 8 mA
Refer to ON-State Resistance Figure
0.07
0.28
Ω
RON (FLAT)
On-resistance flatness
VS = 0 V to VDD
ISD = 8 mA
Refer to ON-State Resistance Figure
1
1.8
Ω
IPOFF
Powered-off I/O pin leakage current
VDD = 0 V
VS = 0 V to 3 V
VD = 0 V
TA = 25℃
Refer to Ipoff Leakage Figure
–10
0.01
10
nA
IPOFF
Powered-off I/O pin leakage current
VDD = 0 V
VS = 0 V to 3.6 V
VD = 0 V
Refer to Ipoff Leakage Figure
–2
0.01
2
µA
IS(OFF)
ID(OFF)
OFF leakage current
Switch Off
VD = 0.8*VDD / 0.2*VDD
VS = 0.2*VDD / 0.8*VDD
Refer to Off Leakage Figure
–100
0.03
100
nA
ON leakage current
Switch On
VD = 0.8*VDD / 0.2*VDD, S pins floating
or
VS = 0.8*VDD / 0.2*VDD, D pins floating
Refer to On Leakage Figure
–50
0.01
50
nA
1.2
5.5
V
0
0.45
V
1
±2
μA
0.2
±2
ID(ON)
IS(ON)
LOGIC INPUTS
VIH
Input logic high
VIL
Input logic low
IIH
Input high leakage current
VSEL = 1.8 V, VDD
IIL
Input low leakage current
VSEL = 0 V
RPD
Internal pull-down resistor on logic pins
CI
Logic input capacitance
6
VSEL = 0 V, 1.8 V or VDD
f = 1 MHz
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μA
6
MΩ
3
pF
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6.6 Dynamic Characteristics
VDD = 1.5 V to 5.5 V, GND = 0V, TA = –40°C to +125°C
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Switch
OFF
3.5
6
pF
12
pF
COFF
Source and drain off capacitance
VS = 2.5 V
VSEL= 0 V
f = 1 MHz
Refer to Capacitance Figure
CON
Source and drain on capacitance
VS = 2.5 V
VSEL= 0 V
f = 1 MHz
Refer to Capacitance Figure
Switch
ON
7.5
QC
Charge Injection
VS = VDD/2
RS = 0 Ω, CL =1 nF
Refer to Charge Injection Figure
Switch
ON
3.5
pC
RL = 50 Ω
f = 100 kHz
Refer to Off Isolation Figure
Switch
OFF
–90
dB
RL = 50 Ω
f = 1 MHz
Refer to Off Isolation Figure
Switch
OFF
–75
dB
dB
OISO
Off isolation
XTALK
Channel to Channel crosstalk
RL = 50 Ω
f = 100 kHz
Refer to Crosstalk Figure
Switch
ON
–90
BW
Bandwidth
RL = 50 Ω
Refer to Bandwidth Figure
Switch
ON
2
ILOSS
Insertion loss
RL = 50 Ω
f = 1 MHz
Refer to Bandwidth Figure
Switch
ON
–0.12
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dB
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SCDS391C – OCTOBER 2018 – REVISED DECEMBER 2019
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6.7 Timing Requirements
VDD = 1.5 V to 5.5 V, GND = 0V, TA = –40°C to +125°C
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
160
350
ns
180
580
ns
tTRAN
Transition time from control input
VDD = 2.5 V to 5.5 V
VS = VDD
RL = 200 Ω, CL = 15pF
Refer to Transition Timing Figure
tTRAN
Transition time from control input
VDD < 2.5 V
VS = VDD
RL = 200 Ω, CL = 15pF
Refer to Transition Timing Figure
tON(EN)
Device turn on time from enable pin
VS = VDD
RL = 200 Ω, CL = 15pF
Refer to Ton(EN) & Toff(EN) Figure
12
35
µs
tOFF(EN)
Device turn off time from enable pin
VS = VDD
RL = 200 Ω, CL = 15pF
Refer to Ton(EN) & Toff(EN) Figure
50
95
ns
tON(VDD)
Device turn on time (VDD to output)
VS = 3.6 V
VDD rise time = 1us
RL = 200 Ω, CL = 15pF
Refer to Ton(vdd) & Toff(vdd) Figure
20
60
µs
tOFF(VDD)
Device turn off time (VDD to output)
VS = 3.6 V
VDD fall time = 1us
RL = 200 Ω, CL = 15pF
Refer to Ton(vdd) & Toff(vdd) Figure
1.2
2.7
µs
tOPEN (BBM)
Break before make time
VS = 1 V
RL = 200 Ω, CL = 15pF
Refer to Topen(BBM) Figure
tSK(P)
Inter - channel skew - QFN (RSV)
Refer to Tsk Figure
5
ps
tSK(P)
Inter - channel skew - DYY (SOT-23)
Refer to Tsk Figure
9
ps
tSK(P)
Inter - channel skew - TSSOP (PW)
Refer to Tsk Figure
18
ps
tPD
Propagation delay - QFN (RSV)
Refer to Tpd Figure
50
ps
tPD
Propagation delay - DYY (SOT-23)
Refer to Tpd Figure
75
ps
tPD
Propagation delay - TSSOP (PW)
Refer to Tpd Figure
95
ps
8
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0.5
ns
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6.8 Typical Characteristics
5
5
4
4
On Resistance (:)
On Resistance (:)
At TA = 25°C, VDD = 5 V (unless otherwise noted).
3
VDD = 1.5 V
VDD = 5.5 V
2
1
3
TA = 85qC
2
1
VDD = 3.3 V
0
0
1
2
3
4
Source or Drain Voltage (V)
5
5.5
0
1
2
3
4
Source or Drain Voltage (V)
D001
TA = 25°C
5
5.5
D002
VDD = 5.5 V
Figure 1. On-Resistance vs Source or Drain Voltage
Figure 2. On-Resistance vs Source or Drain Voltage
4
4
3
3
On Resistance (:)
On Resistance (:)
TA = 25qC
TA = -40qC
0
TA = 125qC
TA = 85qC
2
1
TA = 85qC
TA = 125qC
TA = -40qC
TA = 25qC
2
1
TA = 25qC
TA = -40qC
0
0
0
0.5
1
1.5
2
2.5
Source or Drain Voltage (V)
3
3.5
0
0.5
1
Source or Drain Voltage (V)
D003
VDD = 3.3 V
1.5
D004
VDD = 1.5 V
Figure 3. On-Resistance vs Source or Drain Voltage
Figure 4. On-Resistance vs Source or Drain Voltage
65
60
TA = 125qC
60
55
55
Supply Current (PA)
Supply Current (PA)
TA = 125qC
VDD = 3.3 V
50
VDD = 5.5 V
45
40
35
45
TA = 25qC
40
35
VDD = 1.5 V
30
TA = 85qC
50
TA = -40qC
25
0
0.5
1
1.5
2 2.5 3 3.5
Logic Voltage (V)
4
4.5
5
5.5
30
1.5
2
D005
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
6
D006
TA = 25°C
Figure 5. Supply Current vs Logic Voltage
Figure 6. Supply Current vs Supply Voltage
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Typical Characteristics (continued)
2
30
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
25
1.5
On Leakage (nA)
On Leakage (pA)
20
15
10
5
1
0.5
0
0
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
-5
-0.5
-50
-10
0
0.5
1
1.5 2
2.5 3
3.5 4
Source or Drain Voltage (V)
4.5
5
5.5
-25
0
25
50
75
Temperature (qC)
D007
100
125
150
D008
TA = 25°C
Figure 7. On-Leakage vs Source or Drain Voltage
Figure 8. On-Leakage vs Temperature
3
0.1
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
2.7
2.4
0.05
Off Leakage (nA)
Off Leakage (nA)
2.1
0
-0.05
1.8
1.5
1.2
0.9
0.6
-0.1
0.3
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.5 V
0
-0.3
-40
-0.15
0
1
2
3
Source Voltage (V)
4
5
5.5
-20
0
20
D009
40
60
80
Temperature (qC)
100
120
140
D010
TA = 25°C
Figure 9. Off-Leakage vs Source or Drain Voltage
Figure 10. Off-Leakage vs Temperature
10
1
0.9
8
IPOFF Leakage (nA)
0.8
IPOFF (nA)
0.7
0.6
0.5
0.4
0.3
0.2
6
4
2
0
0.1
0
0
0.5
1
1.5
2
2.5
Source Voltage (V)
3
3.5
4
-2
-40
-30
D011
TA = 25°C
-10
0
10
20
30
Temperature (qC)
40
50
60
D012
VSource = 3 V
Figure 11. IPOFF Leakage vs Source or Drain Voltage
10
-20
Figure 12. IPOFF Leakage vs Temperature
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Typical Characteristics (continued)
700
IPOFF Leakage (nA)
600
500
400
300
200
100
0
-100
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
D013
TA = 25°C
RL= 200 Ω
VSource = 3.6 V
VDrain = 0 V
Figure 14. IPOFF Leakage vs Source or Drain Voltage
180
220
160
195
140
170
Transition Time (nS)
Transition Time (nS)
Figure 13. IPOFF Leakage vs Temperature
120
Transiton_Falling
Transiton_Rising
100
80
60
40
20
1.5
Transiton_Falling
Transiton_Rising
145
120
95
70
45
2
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
20
-40
6
-20
0
D015
TA = 25°C
40
60
80
Temperature (qC)
100
120
140
D016
VDD = 5.5 V
Figure 15. TTRANSITION vs Supply Voltage
Figure 16. TTRANSITION vs Temperature
25
25
20
20
15
Time (PS)
Time (PS)
20
TON(VDD)
TOFF(VDD)
10
5
15
10
5
0
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
0
1.5
D017
TA = 25°C
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
D018
TA = 25°C
Figure 17. TON (VDD) and TOFF (VDD) vs Supply Voltage
Figure 18. TON (EN) vs Supply Voltage
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Typical Characteristics (continued)
100
80
90
70
Propagation Delay - PW
80
70
50
Time (ps)
Time (nS)
60
40
30
60
Propagation Delay - DYY
Propagation Delay - RSV
50
40
Skew - PW
30
20
Skew - DYY
Skew - RSV
20
10
10
0
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
0
1.5
5.5
2
2.5
D019
TA = 25°C
3
3.5
4
Supply Voltage (V)
5
5.5
D020
TA = 25°C
Figure 19. TOFF (EN) vs Supply Voltage
Figure 20. Skew and Propagation Delay vs Supply Voltage
10
10
CSOFF
CSON
9
8
8
VDD = 5.5 V
7
Capacitance (pF)
Charge Injection (pC)
4.5
6
VDD = 3.3 V
5
4 V = 1.5 V
DD
3
2
6
4
2
1
0
0
1
2
3
4
Source Voltage (V)
5
0
1M
6
10M
D021
TA = 25°C
100M
Frequency (Hz)
1G
D022
TA = 25°C
VDD = 1.5 V to 5.5 V
Figure 21. Charge Injection vs Source Voltage
Figure 22. Capacitance vs Frequency
0
-10
-20
0
Off Isolation
Crosstalk
-1
-40
Attenuation (dB)
Attenuation (dB)
-30
-50
-60
-70
-80
-2
-3
-4
-90
-100
-5
-110
-120
100k
-6
1M
10M
100M
Frequency (Hz)
1G
1M
D023
TA = 25°C
VDD = 3.3 V
1G
D024
TA = 25°C
VDD = 1.5 V to 5.5 V
Figure 23. Off Isolation and Crosstalk vs Frequency
12
10M
100M
Frequency (Hz)
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6.8.1 Eye Diagrams
TA = 25°C
Bias = 1.5 V
50 Ω Termination
TA = 25°C
Bias = 1.5 V
50 Ω Termination
Figure 25. Eye Pattern: 2.4 Gbps
Figure 26. Eye Pattern: 2.4 Gbps Through Path
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7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (Dx) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.
The measurement setup used to measure RON is shown in Figure 27. Voltage (V) and current (ISD) are measured
using this setup, and RON is computed as shown below with RON = V / ISD:
V
ISD
Sx
Dx
VS
Figure 27. On-Resistance Measurement Setup
7.2 Off-Leakage Current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS (OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID (OFF).
The setup used to measure both off-leakage currents is shown in Figure 28.
VDD
VDD
VDD
IS (OFF)
ID (OFF)
S1A
D1
S1B
A
A
VS
ID (OFF)
S4A
D4
S4B
IS (OFF)
A
A
S1A
D1
S1B
VS
GND
VD
VD
VD
VS
D1
S1B
VD
VS
VDD
S1A
GND
VD
VD
Figure 28. Off-Leakage Measurement Setup
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7.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS (ON).
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID (ON).
Either the source pin or drain pin is left floating during the measurement. Figure 29 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON).
VDD
VDD
IS (ON)
VDD
N.C.
N.C.
ID (ON)
S1A
D1
D1
A
S1B
N.C.
VS
VDD
S1A
A
S1B
N.C.
VD
IS (ON)
N.C.
N.C.
ID (ON)
S4A
S4A
A
D4
D4
A
S4B
VS
N.C.
S4B
N.C.
VD
GND
GND
Figure 29. On-Leakage Measurement Setup
7.4 IPOFF Leakage Current
IPOFF leakage current is defined as the leakage current flowing into or out of the source pin when the device is
powered off. This current is denoted by the symbol IPOFF.
The setup used to measure both IPOFF leakage current is shown in Figure 30.
VDD
IPOFF
A
D1
N.C.
VS
VDD
S1A
S1B
VD
IPOFF
S4A
A
VS
D4
N.C.
S4B
VD
GND
Figure 30. IPOFF Leakage Measurement Setup
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7.5 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the select signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device. The time constant from the load resistance and load capacitance can be added to the transition time
to calculate system level timing. Figure 31 shows the setup used to measure transition time, denoted by the
symbol tTRANSITION.
VDD
0.1 F
VDD
VDD
ADDRESS
DRIVE
(VSEL)
tf < 5ns
tr < 5ns
VIH
S1A
VS
VIL
D1
0V
OUTPUT
S1B
CL
RL
tTRANSITION
tTRANSITION
S4A
VS
D4
OUTPUT
S4B
CL
RL
90%
OUTPUT
SEL
GND
VSEL
10%
0V
Figure 31. Transition-Time Measurement Setup
7.6 tON (EN) and tOFF (EN) Time
The tON (EN) time is defined as the time taken by the output of the device to rise to 90% after the enable has fallen
past the logic threshold. The 90% measurement is used to provide the timing of the device being enabled in the
system. Figure 32 shows the setup used to measure the enable time, denoted by the symbol tON (EN).
The tOFF (EN) time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen
past the logic threshold. The 90% measurement is used to provide the timing of the device being disabled in the
system. Figure 32 shows the setup used to measure enable time, denoted by the symbol tOFF (EN).
VDD
0.1 F
VDD
VDD
ENABLE
DRIVE
(VEN)
VIH
VIL
tr < 5ns
tf < 5ns
VS
S1A
D1
OUTPUT
S1B
RL
CL
0V
tOFF (EN)
tON (EN)
VS
S4A
D4
OUTPUT
S4B
90%
RL
90%
CL
OUTPUT
EN
0V
VEN
GND
Figure 32. tON (EN) and tOFF (EN) Time Measurement Setup
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7.7 tON (VDD) and tOFF (VDD) Time
The tON (VDD) time is defined as the time taken by the output of the device to rise to 90% after the supply has
risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in
the system. Figure 33 shows the setup used to measure turn on time, denoted by the symbol tON (VDD).
the tOFF (VDD) time is defined as the time taken by the output of the device to fall to 90% after the supply has fallen
past the supply threshold. The 90% measurement is used to provide the timing of the device turning off in the
system. Figure 33 shows the setup used to measure turn off time, denoted by the symbol tOFF (VDD).
VDD
0.1 F
VDD
VDD
VDD
Supply
Ramp
(VDD)
1.5 V
1.5 V
S1A
VS
OUTPUT
D1
S1B
0V
CL
RL
tOFF (VDD)
tON (VDD)
90%
90%
S4A
VS
OUTPUT
D4
OUTPUT
S4B
CL
RL
0V
EN
GND
Figure 33. tON (VDD) and tOFF (VDD)Time Measurement Setup
7.8 Break-Before-Make Delay
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. Figure 34 shows
the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM).
VDD
0.1 F
VDD
VDD
VSEL
tr < 5ns
VS
tf < 5ns
S1A
D1
OUTPUT
S1B
0V
RL
VS
90%
Output
CL
S4A
D4
OUTPUT
S4B
tBBM 1
tBBM 2
RL
CL
0V
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
SEL
VSEL
GND
Figure 34. Break-Before-Make Delay Measurement Setup
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7.9 Propagation Delay
Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal
has risen or fallen past the 50% threshold. Figure 35 shows the setup used to measure propagation delay,
denoted by the symbol tPD.
VDD
0.1 F
VDD
250 mV
Input
(VS)
50%
50%
0V
S1A
VS
D1
S1B
VS
tPD 1
RL
50
tPD 2
S4A
VS
Output
OUTPUT
50%
50%
D4
S4B
VS
OUTPUT
RL
50
0V
GND
tProp Delay = max ( tPD 1, tPD 2)
Figure 35. Propagation Delay Measurement Setup
7.10 Skew
Skew is defined as the difference between propagation delays of any two outputs of the same device. The skew
measurement is taken from the output of one channel rising or falling past 50% to a second channel rising or
falling past the 50% threshold when the input signals are switched at the same time. Figure 36 shows the setup
used to measure skew, denoted by the symbol tSK.
VDD
0.1 F
VDD
Output 1
50%
50%
0V
VS
VS
tSK 1
50%
D1
S1B
OUTPUT
RL
50
tSK 2
VS
Output 2
S1A
50%
VS
S4A
D4
S4B
OUTPUT
RL
50
0V
GND
tSKEW = max ( tSK 1, tSK 2)
Figure 36. Skew Measurement Setup
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7.11 Charge Injection
The amount of charge injected into the source or drain of the device during the falling or rising edge of the gate
signal is known as charge injection, and is denoted by the symbol QC. Figure 37 shows the setup used to
measure charge injection from source (Sx) to drain (Dx).
VDD
0.1 F
VDD
VDD
S1A
VS
D1
VEN
OUTPUT
S1B
VOUT
CL
0V
S4A
VS
Output
D4 OUTPUT
S4B
VOUT
VS
QC = CL ×
VOUT
CL
VOUT
EN
VEN
GND
Figure 37. Charge-Injection Measurement Setup
7.12 Capacitance
The parasitic capacitance of the device is captured at the source (Sx), drain (Dx), and select (SELx) pins. The
capacitance is measured in both the on and off state and is denoted by the symbol CON and COFF. Figure 38
shows the setup used to measure capacitance.
VDD
VDD
S1A
D1
S1B
1 MHz
Capacitance
Meter
Capacitance is measured at S X, DX,
and logic pins during ON and OFF
conditions
S4A
D4
S4B
LOGIC CONTROL
SEL
EN
GND
Figure 38. Capacitance Measurement Setup
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7.13 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the
source pin (Sx) of an off-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. Figure 39
shows the setup used to measure off isolation. Use off isolation equation to compute off isolation.
0.1µF
NETWORK
VDD
ANALYZER
VS
50Ÿ
S
VSIG
D
VOUT
RL
50Ÿ
SxA / SxB / Dx
RL
50Ÿ
GND
Figure 39. Off Isolation Measurement Setup
Off Isolation
§V
·
20 ˜ Log ¨ OUT ¸
V
© S ¹
(1)
7.14 Channel-to-Channel Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (Dx) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. The characteristic impedance, Z0, for the measurement is 50 Ω.
Figure 40 shows the setup used to measure, and the equation used to compute crosstalk.
VDD
0.1µF
NETWORK
VDD
ANALYZER
VOUT
S1A
D1
S4A
D4
RL
RL
50Ÿ
50Ÿ
VS
RL
50Ÿ
50Ÿ
SxA / SxB / Dx
VSIG = 200 mVpp
VBIAS = VDD / 2
RL
50Ÿ
GND
Figure 40. Channel-to-Channel Crosstalk Measurement Setup
Channel-to-Channel Crosstalk
20
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
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7.15 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. The
characteristic impedance, Z0, for the measurement is 50 Ω. Figure 41 shows the setup used to measure
bandwidth.
VDD
0.1µF
NETWORK
VDD
VS
ANALYZER
50Ÿ
S
VSIG
D
VOUT
RL
SxA / SxB / Dx
50Ÿ
RL
50Ÿ
GND
Figure 41. Bandwidth Measurement Setup
8176
)
85
#PPAJQ=PEKJ = 20 × .KC (
(3)
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8 Detailed Description
8.1 Overview
The TMUX1574 is a high speed 2:1 (SPDT) 4-ch. switch with powered-off protection up to 3.6 V. Wide
operating supply of 1.5 V to 5.5 V allows for use in a wide array of applications from servers and
communication equipment to industrial applications. The device supports bidirectional analog and digital
signals on the source (SxA, SxB) and drain (Dx) pins. The wide bandwidth of this switch allows little or no
attenuation of high-speed signals at the outputs to pass with minimum edge and phase distortion as well as
propagation delay.
The enable (EN) pin is an active-low logic pin that controls the connection between the source (SxA, SxB)
and drain (Dx) pins of the device. The select pin (SEL) controls the state of all four channels of the
TMUX1574 and determines which source pin is connected to the drain. Fail-Safe Logic circuitry allows
voltages on the logic control pins to be applied before the supply pin, protecting the device from potential
damage. All logic control inputs have 1.8V logic compatible thresholds, ensuring both TTL and CMOS logic
compatibility when operating in the valid supply voltage range.
Powered-off protection up to 3.6 V on the signal path of the TMUX1574 provides isolation when the supply
voltage is removed (VDD = 0 V). Without this protection feature, the system can back-power the supply rail
through an internal ESD diode and cause potential damage to the system.
8.2 Functional Block Diagram
TMUX1574
S1A
S1B
D1
S2A
S2B
D2
S3A
S3B
D3
S4A
S4B
D4
LOGIC CONTROL*
SEL
EN
*Internal 6MO Pull-Down on Logic Pins
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX1574 conducts equally well from source (SxA, SxB) to drain (Dx) or from drain (Dx) to source (SxA,
SxB). Each channel has very similar characteristics in both directions and supports both analog and digital
signals.
8.3.2 Beyond Supply Operation
When the TMUX1574 is powered from 1.5 V to 5.5 V, the valid signal path input/output voltage ranges from
GND to VDD x 2, with a maximum input/output voltage of 5.5 V.
Example 1: If the TMUX1574 is powered at 1.5V, the signal range is 0 V to 3 V.
Example 2: If the TMUX1574 is powered at 3V, the signal range is 0 V to 5.5 V.
Example 3: If the TMUX1574 is powered at 5.5V, the signal range is 0 V to 5.5 V.
Other voltage levels not mentioned in the examples support Beyond Supply Operation as long as the supply
voltage falls within the recommended operation conditions of 1.5 V to 5.5 V.
22
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Feature Description (continued)
8.3.3 1.8 V Logic Compatible Inputs
The TMUX1574 has 1.8-V logic compatible control inputs. Regardless of the VDD voltage, the control input
thresholds remain fixed, allowing a 1.8-V processor GPIO to control the TMUX1574 without the need for an
external translator. This saves both space and BOM cost. For more information on 1.8 V logic implementations,
refer to Simplifying Design with 1.8 V logic Muxes and Switches.
8.3.4 Powered-off Protection
Powered-off protection up to 3.6 V on the signal path of the TMUX1574 provides isolation when the supply
voltage is removed (VDD = 0 V). When the TMUX1574 is powered-off, the I/Os of the device remain in a high-Z
state. Powered-off protection minimizes system complexity by removing the need for power supply sequencing
on the signal path. The device performance remains within the leakage performance mentioned in the Electrical
Specifications. For more information on powered-off protection, refer to Eliminate Power Sequencing with
Powered-off Protection Signal Switches.
8.3.5 Fail-Safe Logic
The TMUX1574 has Fail-Safe Logic on the control input pins (SELx) which allows for operation up to 5.5 V,
regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied before the
supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by
removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic
feature allows the select pins of the TMUX1574 to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature
enables operation of the TMUX1574 with VDD = 1.5 V while allowing the select pins to interface with a logic level
of another device up to 5.5 V.
8.3.6 Low Capacitance
The TMUX1574 has very low capacitance in both the ON and OFF states on the source and drain pins. Low
capacitance helps to reduce large overshoots and ringing of an amplifier circuit when the switch is connected to
the feedback network. Additionally, low capacitance improves system settling time by reducing the switch time
constant formed by the On-resistance and On-capacitance. For more information on the benefits of low
capacitance refer to Improve Stability Issues with Low CON Multiplexers.
8.3.7 Integrated Pull-Down Resistors
The TMUX1574 has internal weak pull-down resistors (6 MΩ) to GND to ensure the logic pins are not left
floating. This feature integrates up to four external components and reduces system size and cost.
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8.4 Device Functional Modes
The enable (EN) pin is an active-low logic pin that controls the connection between the source (SxA, SxB) and
drain (Dx) pins of the device. When the enable pin is pulled high, all switches are turned off. When the enable is
pulled low, the select pin controls the signal path selection. The select pin (SEL) controls the state of all four
channels of the TMUX1574 and determines which source pin is connected to the drain pins. When the select pin
is pulled low, the SxA pin conducts to the corresponding Dx pins. When the select pin is pulled high, the SxB pin
conducts to the corresponding Dx pins. The TMUX1574 logic pins have internal weak pull-down resistors (6 MΩ)
to GND so that it powers-on in a known state.
The TMUX1574 can be operated without any external components except for the supply decoupling capacitors.
Unused logic control pins should be tied to GND or VDD in order to ensure the device does not consume
additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs
(SxA, SxB, or Dx) should be connected to GND.
8.5 Truth Tables
Table 1. TMUX1574 Truth Table
INPUTS
SEL
0
0
S1A connected to D1
S2A connected to D2
S3A connected to D3
S4A connected to D4
0
1
S1B connected to D1
S2B connected to D2
S3B connected to D3
S4B connected to D4
1
X (1)
Hi-Z (OFF)
(1)
24
Selected Source Pins Connected To Drain Pins (Dx)
EN
X denotes don't care.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TMUX15xx family offers high-speed system performance across a wide operating supply (1.5 V to 5.5 V)
and operating temperature (-40°C to +125°C). The TMUX1574 supports a number of features that improve
system performance such as 1.8 V logic compatibility, supports input voltages beyond supply, Fail-Safe Logic,
and Powered-off Protection up to 3.6 V. These features make the TMUX15xx a family of protection multiplexers
and switches that can reduce system complexity, board size, and overall system cost.
9.2 Typical Application
Common applications that require the features of the TMUX1574 include multiplexing various protocols from a
possessor or MCU such as SPI, JTAG, or standard GPIO signals. The TMUX1574 provides superior isolation
performance when the device is powered. The added benefit of powered-off protection allows a system to
minimize complexity by eliminating the need for power sequencing in hot-swap and live insertion applications.
The example shown in Figure 42 illustrates the use of the TMUX1574 to multiplex an SPI bus to multiple flash
memory devices.
1.8 V
3.3 V
VI/O
0.1µF 3.3 V
FLASH Device #1
VDD
VDD
Processor
D1
RAM
S1A
S2A
S3A
S4A
D2
MISO
MOSI
SCLK
SS
SPI PORT
CPU
D3
FLASH Device #2
S1B
S2B
S3B
S4B
D4
Peripherals
1.8V Logic
I/O
SEL
EN
GND
MISO
MOSI
SCLK
SS
GND
Figure 42. Multiplexing Flash Memory
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 2.
Table 2. Design Parameters
PARAMETERS
VALUES
Supply (VDD)
3.3 V
Input / Output signal range
0 V to 3.3 V
Control logic thresholds
1.8 V compatible
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9.2.2 Detailed Design Procedure
The TMUX1574 can be operated without any external components except for the supply decoupling capacitors.
The TMUX1574 has internal weak pull-down resistors (6 MΩ) to GND so that it powers-on with the switches in a
known state. All inputs signals passing through the switch must fall within the recommend operating conditions of
the TMUX1574 including signal range and continuous current. For this design example, with a supply of 3.3 V,
the signals can range from 0 V to 3.3 V when the device is powered. This example can also utilize the Poweredoff Protection feature and the inputs can range from 0 V to 3.6 V when VDD = 0 V. The max continuous current
can be 25 mA. Due to the voltage range and high speed capability, the TMUX1574 example is suitable for use in
SPI, JTAG, and I2S applications. Refer to Enabling SPI-based flash memory expansion by using multiplexers for
more information on using switches and multiplexers for SPI protocol expansion.
9.2.3 Application Curves
Two important specifications when using a switch or multiplexer to pass signals are the device propagation delay
and skew.
100
90
Propagation Delay - PW
80
Time (ps)
70
60
Propagation Delay - DYY
Propagation Delay - RSV
50
40
Skew - PW
30
Skew - DYY
Skew - RSV
20
10
0
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
D020
Figure 43. Propagation Delay and Skew Measurement
10 Power Supply Recommendations
The TMUX1574 operates across a wide supply range of 1.5 V to 5.5 V. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply to
other components. Good power-supply decoupling is important to achieve optimum performance. For improved
supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground.
Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance
connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series
resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive
systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to
the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall
inductance and is beneficial for connections to ground planes.
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11 Layout
11.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners.Figure 44 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
BETTER
BEST
2W
WORST
1W min.
W
Figure 44. Trace Example
Route the high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, throughhole pins are not recommended at high frequencies.
Do not route high speed signal traces under or near crystals, oscillators, clock signal generators, switching
regulators, mounting holes, magnetic devices or ICs that use or duplicate clock signals.
Avoid stubs on the high-speed signals traces because they cause signal reflections.
Route all high-speed signal traces over continuous GND planes, with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
When working with high frequencies, a printed circuit board with at least four layers is recommended; two
signal layers separated by a ground and power layer as shown in Figure 45.
Signal 1
GND Plane
Power Plane
Signal 2
Figure 45. Example Layout
The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer must
be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power
plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the
number of signal vias reduces EMI by reducing inductance at high frequencies.
Figure 46 illustrates an example of a PCB layout with the TMUX1574. Some key considerations are:
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Layout Guidelines (continued)
Decouple the VDD pin with a 0.1-μF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
High-speed switches require proper layout and design procedures for optimum performance.
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
Wide (low inductance)
trace for power
Via to GND plane
C
SEL
VDD
S1A
EN
S1B
S4A
D1
TMUX1574
S4B
S2A
D4
S2B
S3A
D2
S3B
GND
D3
Figure 46. Example Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
Texas Instruments, Improve Stability Issues with Low CON Multiplexers.
Texas Instruments, Enabling SPI-based flash memory expansion by using multiplexers.
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.
Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches.
Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers.
Texas Instruments, High-Speed Interface Layout Guidelines.
Texas Instruments, High-Speed Layout Guidelines.
Texas Instruments, QFN/SON PCB Attachment.
Texas Instruments, Quad Flatpack No-Lead Logic Packages.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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4-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMUX1574DYYR
ACTIVE
SOT-23-THIN
DYY
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TMUX1574
TMUX1574PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
MUX1574
TMUX1574RSVR
ACTIVE
UQFN
RSV
16
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1574
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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