TMUX4052PWR

TMUX4051, TMUX4052, TMUX4053 SCDS445B – MAY 2022 – REVISED MARCH 2023 TMUX405x 24-V, 8:1, 1-Channel, 4:1, 2-Channel and 2:1, 3-Channel Multiplexers with 1.8-V Logic 1 Features 3 Description • • • • • • • • • • The TMUX405x devices are general purpose complementary metal-oxide semiconductor (CMOS) multiplexers (MUX). The TMUX4051 is an 8:1, 1channel multiplexer, the TMUX4052 is a 4:1, 2channel multiplexer, and the TMUX4053 is 2:1, 3 channel switch. The devices work with a single supply (5 V to 24 V), dual supplies (up to ±12 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V). The wide supply voltage range allows the TMUX405x devices to be used in a broad array of applications from battery testers to appliances. Single supply range: 5 V to 24 V Dual supply range: up to ±12 V Low capacitance: 3 pF –55°C to +125°C operating temperature Bidirectional signal path Rail-to-rail operation 1.8 V logic compatible Break-before-make switching ESD protection HBM: 2000 V TMUX405x – pin compatible with: – Industry standard 4051, 4052, and 4053 muxes The TMUX405x devices support bidirectional analog signals on the source (Sx) and drain (Dx) pins ranging from VSS to VDD. All logic inputs have 1.8 V logic compatible thresholds, which is compatible for both TTL and CMOS logic when operating with a valid supply voltage. 2 Applications • • • • • • • • Analog multiplexing and demultiplexing Factory automation and control Appliances Battery test equipment Power delivery Medical Building automation Grid infrastructure Package Information(1)(2) PART NUMBER TMUX4051 TMUX4052 TMUX4053 (1) (2) TMUX4051 S0A S1A S2A S3A D 1-OF-8 DECODER A1 A0 5.00 mm × 4.40 mm DYY (SOT-23-THIN, 16) 4.20 mm × 2.00 mm BQB (WQFN, 16) 3.50 mm × 2.50 mm For all available packages, see the package option addendum at the end of the data sheet. See the Device Comparison Table DB 1-OF-4 DECODER EN TMUX4053 DA S0B S1B S2B S3B A1 A0 BODY SIZE (NOM) PW (TSSOP, 16) TMUX4052 S0 S1 S2 S3 S4 S5 S6 S7 A2 PACKAGE S1A S1B D1 S2A S2B D2 S3A S3B D3 LOGIC CONTROL EN SEL1 SEL2 SEL3 EN TMUX4051, TMUX4052, and TMUX4053 Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 7 7.1 Absolute Maximum Ratings........................................ 7 7.2 ESD Ratings............................................................... 7 7.3 Thermal Information: TMUX405x................................8 7.4 Recommended Operating Conditions.........................8 7.5 Electrical Characteristics.............................................9 7.6 AC Performance Characteristics...............................11 7.7 Timing Characteristics...............................................12 7.8 Typical Characteristics.............................................. 14 8 Parameter Measurement Information.......................... 16 8.1 On-Resistance.......................................................... 16 8.2 Off-Leakage Current................................................. 16 8.3 On-Leakage Current................................................. 17 8.4 Transition Time......................................................... 17 8.5 Break-Before-Make...................................................18 8.6 tON(EN) and tOFF(EN) .................................................. 18 8.7 Propagation Delay.................................................... 19 8.8 Charge Injection........................................................19 8.9 Off Isolation...............................................................20 8.10 Crosstalk................................................................. 20 8.11 Bandwidth............................................................... 21 9 Detailed Description......................................................22 9.1 Overview................................................................... 22 9.2 Functional Block Diagram......................................... 22 9.3 Feature Description...................................................22 10 Application and Implementation................................ 24 10.1 Application Information........................................... 24 10.2 Typical Application.................................................. 24 10.3 Design Requirements............................................. 25 10.4 Detailed Design Procedure..................................... 25 10.5 Application Curves.................................................. 25 10.6 Power Supply Recommendations...........................25 10.7 Layout..................................................................... 26 11 Device and Documentation Support..........................27 11.1 Documentation Support.......................................... 27 11.2 Receiving Notification of Documentation Updates.. 27 11.3 Support Resources................................................. 27 11.4 Trademarks............................................................. 27 11.5 Electrostatic Discharge Caution.............................. 27 11.6 Glossary.................................................................. 27 12 Mechanical, Packaging, and Orderable Information.................................................................... 27 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (September 2022) to Revision B (March 2023) Page • Changed the status DYY and BQB packages from: preview to: active ............................................................. 1 Changes from Revision * (May 2022) to Revision A (September 2022) Page • Changed the status from: Advanced Information to: Production Data ...............................................................1 2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 5 Device Comparison Table PRODUCT DESCRIPTION TMUX4051 8:1, 1-channel multiplexer TMUX4052 4:1, 2-channel multiplexer TMUX4053 2:1, 3-channel switch Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 Submit Document Feedback 3 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 6 Pin Configuration and Functions S4 1 16 VDD S6 2 15 S2 D 3 14 S1 S4 1 16 VDD S6 2 15 S2 D 3 14 S1 4 13 S0 5 12 S3 6 11 A0 S7 4 13 S0 S7 S5 5 12 S3 S5 6 11 A0 VSS 7 10 A1 VSS 7 10 A1 GND 8 9 A2 GND 8 9 A2 Not to scale Figure 6-2. TMUX4051 DYY Package, 16-Pin SOT-23-THIN (Top View) Not to scale S4 VDD 1 16 Figure 6-1. TMUX4051 PW Package, 16-Pin TSSOP (Top View) S6 2 15 S2 D 3 14 S1 S7 4 13 S0 S5 5 12 S3 6 11 A0 7 10 A1 Thermal A2 GND 8 VSS 9 Pad Not to scale Figure 6-3. TMUX4051 BQB Package, 16-Pin WQFN (Top View) Table 6-1. Pin Functions TMUX4051 PIN NAME NO. TYPE(1) S4 1 I/O Source pin 4. Signal path can be an input or output. S6 2 I/O Source pin 6. Signal path can be an input or output. D 3 I/O Drain pin (common). Signal path can be an input or output. S7 4 I/O Source pin 7. Signal path can be an input or output. S5 5 I/O Source pin 5. Signal path can be an input or output. EN 6 I Active low logic enable. When this pin is high, all switches are turned off. Table 9-1 lists how the A[2:0] address inputs determine which switch is turned on when this pin is low. VSS 7 P Negative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. GND 8 P Ground (0 V) reference A2 9 I Address line 2. Table 9-1 provides information about how A2 controls the switch configuration. A1 10 I Address line 1. Table 9-1 provides information about how A1 controls the switch configuration. A0 11 I Address line 0. Table 9-1 provides information about how A0 controls the switch configuration. S3 12 I/O Source pin 3. Signal path can be an input or output. S0 13 I/O Source pin 0. Signal path can be an input or output. S1 14 I/O Source pin 1. Signal path can be an input or output. S2 15 I/O Source pin 2. Signal path can be an input or output. VDD 16 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. — The thermal pad is not connected internally. It is recommended that the pad be left floating or tied to GND. Thermal pad (1) (2) 4 DESCRIPTION(2) I = input, O = output, I/O = input and output, P = power. For what to do with unused pins, refer to Section 9.3.4. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 S0B 1 16 VDD S2B 2 15 S2A DB 3 14 S1A S0B 1 16 VDD S2B 2 15 S2A DB 3 14 S1A 4 13 DA 5 12 S0A 6 11 S3A 7 10 A0 8 9 A1 S3B 4 13 DA S3B S1B 5 12 S0A S1B 6 11 S3A VSS 7 10 A0 VSS GND 8 9 A1 GND Not to scale Figure 6-5. TMUX4052 DYY Package, 16-Pin SOT-23-THIN (Top View) Not to scale S0B VDD 1 16 Figure 6-4. TMUX4052 PW Package, 16-Pin TSSOP (Top View) S2B 2 15 S2A DB 3 14 S1A S3B 4 13 DA S1B 5 12 S0A 6 11 S3A 7 10 A0 Thermal A1 GND 8 VSS 9 Pad Not to scale Figure 6-6. TMUX4052 BQB Package, 16-Pin WQFN (Top View) Table 6-2. Pin Functions TMUX4052 PIN NAME NO. TYPE(1) DESCRIPTION(2) S0B 1 I/O Source pin 0 of mux B. Can be an input or output. S2B 2 I/O Source pin 2 of mux B. Can be an input or output. DB 3 I/O Drain pin (common) of mux B. Can be an input or output. S3B 4 I/O Source pin 3 of mux B. Can be an input or output. S1B 5 I/O Source pin 1 of mux B. Can be an input or output. EN 6 I Active low logic enable. When this pin is high, all switches are turned off. When this pin is low, the A[1:0] address inputs determine which switch is turned on. VSS 7 P Negative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. GND 8 P Ground (0 V) reference A1 9 I Address line 1. Table 9-2 provides information about how A1 controls the switch configuration. A0 10 I Address line 0. Table 9-2 provides information about how A0 controls the switch configuration. S3A 11 I/O Source pin 3 of mux A. Can be an input or output. S0A 12 I/O Source pin 0 of mux A. Can be an input or output. DA 13 I/O Drain pin (common) of mux A. Can be an input or output. S1A 14 I/O Source pin 1 of mux A. Can be an input or output. S2A 15 I/O Source pin 2 of mux A. Can be an input or output. VDD 16 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. — The thermal pad is not connected internally. It is recommended that the pad be left floating or tied to GND. Thermal pad (1) (2) I = input, O = output, I/O = input and output, P = power. For what to do with unused pins, refer to Section 9.3.4 . Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 Submit Document Feedback 5 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 S2B 1 16 VDD S2A 2 15 D2 S3B 3 14 D1 S2B 1 16 VDD S2A 2 15 D2 S3B 3 14 D1 4 13 S1B 5 12 S1A 6 11 SEL1 7 10 SEL2 8 9 SEL3 D3 4 13 S1B D3 S3A 5 12 S1A S3A 6 11 SEL1 VSS 7 10 SEL2 VSS GND 8 9 SEL3 GND Not to scale Figure 6-8. TMUX4053 DYY Package, 16-Pin SOT-23-THIN (Top View) Not to scale S2B VDD 1 16 Figure 6-7. TMUX4053 PW Package, 16-Pin TSSOP (Top View) S2A 2 15 D2 S3B 3 14 D1 D3 4 13 S1B S3A 5 12 S1A 6 11 SEL1 7 10 SEL2 Thermal SEL3 GND 8 VSS 9 Pad Not to scale Figure 6-9. TMUX4053 BQB Package, 16-Pin WQFN (Top View) Table 6-3. Pin Functions TMUX4053 PIN NAME NO. TYPE(1) S2B 1 I/O Source pin B of switch 2. Can be an input or output. S2A 2 I/O Source pin A of switch 2. Can be an input or output. S3B 3 I/O Source pin B of switch 3. Can be an input or output. D3 4 I/O Drain pin (common) of switch 3. Can be an input or output. S3A 5 I/O Source pin A of switch 3. Can be an input or output. EN 6 I Active low logic enable. When this pin is high, all switches are turned off. When this pin is low, the SEL[x] logic control inputs determine which switch is turned on. VSS 7 P Negative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. GND 8 P Ground (0 V) reference SEL3 9 I Logic control select pin 3. Table 9-3 provides controls switch 3 configuration. SEL2 10 I Logic control select pin 2. Table 9-3 provides controls switch 2 configuration. SEL1 11 I Logic control select pin 1. Table 9-3 provides controls switch 1 configuration. S1A 12 I/O Source pin A of switch 1. Can be an input or output. S1B 13 I/O Source pin B of switch 1. Can be an input or output. D1 14 I/O Drain pin (common) of switch 1. Can be an input or output. D2 15 I/O Drain pin (common) of switch 2. Can be an input or output. VDD 16 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. — The thermal pad is not connected internally. It is recommended that the pad be left floating or tied to GND. Thermal pad (1) (2) 6 DESCRIPTION(2) I = input, O = output, I/O = input and output, P = power. For what to do with unused pins, refer to Section 9.3.4. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) (3) MIN MAX VDD – VSS UNIT 28 V Supply voltage –0.5 28 V –28 0.5 V VSEL or VEN Logic control input pin voltage (EN, Ax, SELx) –0.5 28 V ISEL or IEN Logic control input pin current (EN, Ax, SELx) mA VS or VD Source or drain voltage (Sx, D) VDD VSS Diode clamp IS or ID (CONT) Source or drain continuous current (Sx, D) TJ Junction temperature Tstg Storage temperature (2) (3) 28 VDD+0.5 –30 30 mA –10 10 mA 150 °C 150 °C current(2) IIK (1) –0.5 VSS–0.5 –65 V Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings. To avoid drawing excess current from VDD, or into VSS, the voltage drop across the bidirectional switch path (ΔVswitch) must not exceed 1.2 V (600 mV for high temperature). 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 Submit Document Feedback 7 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 7.3 Thermal Information: TMUX405x TMUX4051 / TMUX4052 / TMUX4053 THERMAL METRIC(1) PW (TSSOP) DYY (SOT) BQB (WQFN) 16 PINS 16 PINS 16 PINS UNIT RθJA Junction-to-ambient thermal resistance 116.5 138.9 70.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 47.2 70.3 67.8 °C/W RθJB Junction-to-board thermal resistance 63.0 69.1 40.2 °C/W ΨJT Junction-to-top characterization parameter 6.4 5.1 3.9 °C/W ΨJB Junction-to-board characterization parameter 62.1 69.0 40.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 18.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VDD – VSS (1) Power supply voltage differential MAX UNIT 24 V VDD Positive power supply voltage 5 24 V VSS Negative power supply voltage –15 0 V VS or VD Signal path input/output voltage (source or drain pin) (Sx, D) VSS VDD V VAx or VEN Address or enable pin voltage 0 VDD V IS or ID (CONT) Source or drain continuous current (Sx, D) –10 10 mA TA –55 125 °C (1) 8 NOM 5 Ambient temperature VDD and VSS can be any value as long as 5 V ≤ (VDD – VSS) ≤ 24 V, and the minimum VDD and VSS are met. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 7.5 Electrical Characteristics Over operating free-air temperature range, Typical at TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS VDD VSS TA MIN TYP MAX UNIT POWER SUPPLY –55°C Address inputs = 0 V, 5 V, or VDD EN = 0 V Address inputs = 0 V, 5 V, or VDD EN = 0 V Supply current IDD Address inputs = 0 V, 5 V, or VDD EN = 0 V Address inputs = 0 V, 5 V, or VDD EN = 0 V Address inputs = 0 V, 5 V, or VDD EN = 0 V Address inputs = 0 V, 5 V, or VDD EN = 0 V 5V 10 V 24 V 5V 12 V 5V 0V 0V 0V –5 V –12 V –5 V Negative supply current ISS Address inputs = 0 V, 5 V, or VDD EN = 0 V 12 V –12 V 25°C 60 17 85°C 80 125°C 80 –55°C 60 25°C 18 EN = 5 V or VDD All 60 85°C 80 125°C 80 –55°C 60 25°C 21 60 85°C 80 125°C 80 –55°C 60 25°C 18 80 125°C 80 –55°C 60 25°C 20 60 85°C 80 125°C 80 –55°C 20 25°C 6 20 85°C 25 125°C 25 –55°C 22 25°C 7 85°C 25°C –55°C to 125°C Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 µA 60 85°C µA 22 26 125°C IDD disable 60 26 8 20 µA Submit Document Feedback 9 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 7.5 Electrical Characteristics (continued) Over operating free-air temperature range, Typical at TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS VDD VSS TA MIN TYP MAX 75 1050 UNIT ANALOG SWITCH –55°C VS = VSS to VDD ID = –1 mA 5V VS = VSS to VDD ID = –1 mA 10 V RON VS = VSS to VDD Source to Drain ONID = –1 mA Resistance 24 V VS = VSS to VDD ID = –1 mA 5V VS = VSS to VDD ID = –1 mA 12 V ΔRON VS = VSS to VDD ID = –1 mA RON FLAT VS = VSS to VDD ID = –1 mA All Switch State is off VS = VSS / VDD VD = VDD / VSS 24 V IS(OFF) ID(OFF) 0V 0V 0V –5 V –12 V All 800 25°C 85°C 1200 125°C 1300 –55°C 310 25°C 60 520 125°C 550 –55°C 200 25°C 60 300 125°C 300 –55°C 310 25°C 60 520 125°C 550 –55°C 200 25°C 60 300 125°C 300 2 25°C 60 24 V 0V Ω –55°C to 85°C 150 –55°C to 125°C 150 ±0.3 –55°C to 85°C Ω ±100 ±800 nA ±1000 25°C ION 240 85°C 25°C Ω 400 85°C –55°C to 125°C Switch State is on VS = VD = VSS or VDD 240 85°C 25°C 0V 400 85°C ±0.3 ±100 –55°C to 85°C ±800 –55°C to 125°C ±1000 nA LOGIC INPUTS (ADDRESS / ENABLE pins) VIH Input High Voltage All –55°C to 125°C 1.35 VIL Input Low Voltage All –55°C to 125°C 0 IIH IIL Logic Input Current 25°C VLOGIC = 0 V, 5 V, or VDD CIN 10 All All –55°C to 125°C 25°C Submit Document Feedback VDD V 0.8 V ±0.6 –1 1 2 µA pF Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 7.6 AC Performance Characteristics Typical at TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS CONDITION TA = –55℃ to 125℃ VDD VSS GPN MIN TYP MAX UNIT CAPACITANCE CS(OFF) CD(OFF) CS(ON) CD(ON) VS = (VDD + VSS) / 2 V f = 1 MHz VS = (VDD + VSS) / 2 V f = 1 MHz VS = (VDD + VSS) / 2 V f = 1 MHz 5V –5 V 24 V 0V 5V –5 V 24 V 0V 5V –5 V 24 V 0V 5V –5 V 24 V 0V 5V –5 V 24 V 0V 5V –5 V 24 V 0V 5V –5 V 24 V 0V +5 V –5 V 24 V 0V +5 V –5 V 24 V 0V +5 V –5 V 24 V 0V +5 V –5 V All TMUX4051 TMUX4052 TMUX4053 TMUX4051 TMUX4052 TMUX4053 3 3 pF 11 9 6 5 pF 4 3 13 11 8 7 pF 10 5 DYNAMIC CHARACTERISTICS VBIAS = (VDD + VSS) / 2 (1) Bandwidth (BW) V = 200 mVpp (Sine Wave Input) S RL = 50 Ω, CL = 5 pF VBIAS = (VDD + VSS) / 2 Off Isolation VS = 200 mVpp Channel OFF RL = 50 Ω, CL = 5 pF (Sine Wave Input) f = 1 MHz (1) VBIAS = (VDD + VSS) / 2 (1) Crosstalk VS = 200 mVpp (Sine Wave Input) RL = 50 Ω, CL = 5 pF f = 1 MHz Charge Injection (1) VS = (VDD + VSS) / 2 RS = 0 Ω, CL = 100 pF 24 V 0V +5 V –5 V 24 V 0V +5 V –5 V 24 V 0V TMUX4051 TMUX4052 TMUX4053 280 430 600 700 MHz 750 850 –95 All –95 dB –90 All TMUX4051 –90 6 2 dB pC Peak-to-Peak voltage symmetrical about (VDD + VSS) / 2. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 Submit Document Feedback 11 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 7.7 Timing Characteristics Over operating free-air temperature range, Typical at TA = 25℃ (unless otherwise noted) TEST CONDITIONS PARAMETER Prop Delay tON (EN) tOFF 12 VS = VSS to VDD Address-to-Signal OUT tr , tf = 20 ns, Transition time between CL = 50 pF, inputs RL = 10 kΩ tTRAN (EN) Signal Input to Signal Output CONDITION Enable-to-Signal OUT Channel turning ON Enable-to-Signal OUT Channel turning OFF tr , tf = 20 ns, CL = 50 pF, RL = 10 kΩ tr , tf = 20 ns, CL = 50 pF, RL = 10 kΩ VDD VSS TA MIN TYP MAX 5V 0V 25°C 4 20 10 V 0V 25°C 4 20 24 V 0V 25°C 3 20 5V –5 V 25°C 4 20 12 V –12 V 25°C 3 20 5V 0V 25°C 105 10 V 0V 24 V 0V 5V –5 V 12 V –12 V 5V 0V 10 V 0V 24 V 0V 5V –5 V 12 V –12 V 5V 0V 10 V 0V 24 V 0V 5V –5 V 12 V –12 V –55°C to +125°C 25°C 100 190 110 –55°C to +125°C 25°C 230 190 100 –55°C to +125°C 25°C 190 100 –55°C to +125°C 25°C 190 95 –55°C to +125°C 25°C 190 110 –55°C to +125°C 25°C 230 190 100 –55°C to +125°C 25°C 190 90 –55°C to +125°C 25°C 140 90 –55°C to +125°C 25°C 140 85 –55°C to +125°C 25°C 140 –55°C to +125°C Submit Document Feedback ns 100 –55°C to +125°C 25°C ns 100 –55°C to +125°C 25°C ns 100 –55°C to +125°C 25°C ns 190 –55°C to +125°C 25°C UNIT 160 90 140 Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 7.7 Timing Characteristics (continued) Over operating free-air temperature range, Typical at TA = 25℃ (unless otherwise noted) PARAMETER tBBM TEST CONDITIONS CONDITION CL = 15 pF, RL = 10 kΩ VDD VSS 5V 0V 10 V 0V 5V –5 V 12 V –12 V 24 V 0V TA MIN 25°C –55°C to +125°C 45 1 45 1 25°C –55°C to +125°C Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 ns 55 1 25°C –55°C to +125°C UNIT 60 25°C –55°C to +125°C MAX 1 25°C –55°C to +125°C TYP 75 1 Submit Document Feedback 13 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 7.8 Typical Characteristics at TA = 25°C, VDD = 5 V (unless otherwise noted) 240 TA = 125C TA = 85C 220 TA = 25C TA = −55C On Resistance () 200 180 160 140 120 100 80 60 40 0 0.5 1 1.5 2 2.5 3 3.5 4 VS or VD - Source or Drain Voltage (V) VDD = 5 V, VSS = -5 V Figure 7-2. On-Resistance vs Temperature 230 27 TA = 125C TA = 85C 210 TA = 25C TA = −55C 25 Supply Current (A) On Resistance () VDD VDD VDD VDD 26 190 170 150 130 110 90 24 = = = = 24V 10V 15V 5V 23 22 21 20 19 18 70 17 50 16 15 30 0 2 4 6 8 10 12 14 16 18 20 VS or VD - Source or Drain Voltage (V) 22 0 24 2.5 5 7.5 250 Input 90% to Output 90% Input 80% to Output 80% Input 50% to Output 50% 200 Settling Time (ns) 175 150 125 100 75 50 25 0 -25 -50 0 0.2 0.4 0.6 0.8 1 1.2 tr, tf - Signal Rise, Fall Time (s) VDD = 5 V, Vsignal = 5 V RL = 200 kΩ, CL = 15 pF Figure 7-5. System Settling Time 20 22.5 25 Figure 7-4. Supply Current vs Logic Voltage Figure 7-3. On-Resistance vs Temperature 225 10 12.5 15 17.5 Logic Voltage (V) . VDD = 24 V Settling Time (ns) 5 VDD = 5 V Figure 7-1. On-Resistance vs Temperature 14 4.5 1.4 650 600 550 500 450 400 350 300 250 200 150 100 50 0 Input 90% to Output 90% Input 80% to Output 80% Input 50% to Output 50% 0 0.2 0.4 0.6 0.8 1 1.2 tr, tf - Signal Rise, Fall Time (s) 1.4 VDD = 5 V, Vsignal = 5 V RL = 10 kΩ, CL = 15 pF Figure 7-6. System Settling Time Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 7.8 Typical Characteristics (continued) at TA = 25°C, VDD = 5 V (unless otherwise noted) 0 0 TMUX4051 TMUX4052 TMUX4053 -10 -2 -20 -30 -40 -50 Gain (dB) Gain (dB) -4 -6 -8 -60 -70 -80 -10 -90 -100 TMUX4053 TMUX4052 TMUX4051 -12 -14 100k 1M -110 10M Frequency (Hz) 100M 1G -120 100k 1M 10M Frequency (Hz) 100M 1G VDD = 12 V, VSS = -12 V VDD = 12 V, VSS = -12 V Figure 7-8. Off-Isolation vs Frequency Figure 7-7. On Response vs Frequency 0 -10 -20 TMUX4051 TMUX4052 TMUX4053 -30 Gain (dB) -40 -50 -60 -70 -80 -90 -100 -110 -120 100k 1M 10M Frequency (Hz) 100M 1G VDD = 12 V, VSS = -12 V Figure 7-9. Xtalk vs Frequency Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 Submit Document Feedback 15 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 8 Parameter Measurement Information 8.1 On-Resistance The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance. The measurement setup used to measure RON is shown in the following figure. Figure 8-1 shows how the RON is computed with RON = V / ISD, and the voltage (V) and current (ISD) are measured using this setup. V ISD Sx D VS Figure 8-1. On-Resistance Measurement Setup 8.2 Off-Leakage Current There are two types of leakage currents associated with a switch during the off state: 1. Source off-leakage current. 2. Drain off-leakage current. Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is off. This current is denoted by the symbol IS(OFF). Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off. This current is denoted by the symbol ID(OFF). Figure 8-2 shows the setup used to measure both off-leakage currents. Is (OFF) VDD VDD VDD VDD S0 S0 A ID (OFF) D D VS S6 A S6 S7 S7 VS VD VD GND GND Figure 8-2. Off-Leakage Measurement Setup 16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 8.3 On-Leakage Current Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch is on. This current is denoted by the symbol IS(ON). Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is on. This current is denoted by the symbol ID(ON). Either the source pin or drain pin is left floating during the measurement. Figure 8-3 shows the circuit used for measuring the on-leakage current, denoted by IS(ON) or ID(ON). VDD VDD VDD S0 N.C. VDD IS (ON) S0 A ID (ON) S1 S1 D D A N.C. S7 S7 Vs VS VS VD GND GND Figure 8-3. On-Leakage Measurement Setup 8.4 Transition Time Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal has risen or fallen past the 50% threshold. Figure 8-4 shows the setup used to measure transition time, denoted by the symbol tTRANSITION. VSS VDD VSS 0.1 µF 0.1 µF 5V VADDRESS VDD tr < 20 ns 50% 50% tf < 20 ns VS S1 0V D tTRANSITION tTRANSITION Output S2 S8 90% RL CL Output 10% 0V A0 A1 VADDRESS A2 GND Figure 8-4. Transition-Time Measurement Setup Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 Submit Document Feedback 17 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 8.5 Break-Before-Make Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is switching. The output first breaks from the on-state switch before making the connection with the next on-state switch. The time delay between the break and the make is known as break-before-make delay. Figure 8-5 shows the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM). VDD 0.1…F VDD Input Select (VSEL) tr < 5ns S0 VDD tf < 5ns D OUTPUT S1-S6 0V RL CL S7 90% Output tBBM_1 tBBM_2 A0 0V A1 tBBM = min ( tBBM_1, tBBM_2) EN VSEL A2 GND Figure 8-5. Break-Before-Make Delay Measurement Setup 8.6 tON(EN) and tOFF(EN) Turn-on time is defined as the time taken by the output of the device to rise to 10% after the enable has risen past the 50% threshold. The 10% measurement is utilized to provide the timing of the device, system level timing can then account for the time constant added from the load resistance and load capacitance. Figure 8-6 shows the setup used to measure transition time, denoted by the symbol tON(EN). Turn-off time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen past the 50% threshold. The 90% measurement is utilized to provide the timing of the device, system level timing can then account for the time constant added from the load resistance and load capacitance. Figure 8-6 shows the setup used to measure transition time, denoted by the symbol tOFF(EN). VDD 0.1
F VSS 0.1 F Logic High VEN tf = 20ns 50% 50% tr = 20ns VS S0 D 0V OUTPUT S1 RL CL S7 tON (EN) tOFF (EN) 90% A0 EN OUTPUT A1 VEN A2 10% GND 0V Figure 8-6. Turn-On and Turn-Off Time Measurement Setup 18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 8.7 Propagation Delay Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal has risen or fallen past the 50% threshold. Figure 8-7 shows the setup used to measure propagation delay, denoted by the symbol tPD. VDD 0.1 µF 0.1 µF VDD Input (VS) VSS 50% VDD 50% 50
VS VSS tPD 1 VSS S1 D tPD 2 RL S8 Output 50% Output S2 CL 50% GND 0V tProp Delay = max ( tPD 1, tPD 2) Figure 8-7. Propagation Delay Measurement Setup 8.8 Charge Injection Any mismatch in capacitance between the NMOS and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted by the symbol QC. Figure 8-8 shows the setup used to measure charge injection from source (Sx) to drain (D). VDD 0.1
F VDD VDD VS S0 VEN S5 OUTPUT D 0V S6 CL S7 Output VOUT VOUT VS QC = CL × VOUT EN A0 A1 VEN A2 GND Figure 8-8. Charge-Injection Measurement Setup Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 Submit Document Feedback 19 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 8.9 Off Isolation Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the source pin (Sx) of an off-channel. Figure 8-9 shows the setup used to measure, and the equation to compute off isolation. 0.1 µF NETWORK VDD ANALYZER VS 50
S VSIG D VOUT RL 50 SX GND RL 50  Figure 8-9. Off Isolation Measurement Setup Off Isolation  =  20  ×  Log  8.10 Crosstalk VOUT VS (1) Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied at the source pin (Sx) of an on-channel. Figure 8-10 shows the setup used to measure, and the equation used to compute crosstalk. 0.1 µF NETWORK VDD ANALYZER S1 VOUT RL D 50
VS RL S2 50 50  VSIG SX RL 50  GND Figure 8-10. Channel-to-Channel Crosstalk Measurement Setup Cℎannel − to − Cℎannel Crosstalk  =  20  ×  Log  20 VOUT VS Submit Document Feedback (2) Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 8.11 Bandwidth Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure 8-11 shows the setup used to measure bandwidth. 0.1 µF NETWORK VDD VS ANALYZER 50
S VSIG D VOUT RL SX 50 GND RL 50  Figure 8-11. Bandwidth Measurement Setup V (3) Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Attenuation  =  20  ×  Log  V2 1 Product Folder Links: TMUX4051 TMUX4052 TMUX4053 21 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 9 Detailed Description 9.1 Overview The TMUX4051 is an 8:1, single-ended (1-channel) mux, the TMUX4052 is a 4:1, differential (2-channel) multiplexer, and the TMUX4053 is 2:1, 3 channel switch. Each channel is turned on or turned off based on the state of the address lines and enable pin. 9.2 Functional Block Diagram TMUX4051 TMUX4052 S0A S1A S2A S3A S0 S1 S2 S3 S4 S5 S6 S7 D 1-OF-8 DECODER A2 A1 A0 DA S0B S1B S2B S3B DB 1-OF-4 DECODER EN TMUX4053 A1 A0 S1A S1B D1 S2A S2B D2 S3A S3B D3 LOGIC CONTROL EN SEL1 SEL2 SEL3 EN 9.3 Feature Description 9.3.1 Bidirectional Operation The TMUX4051, TMUX4052, and TMUX4053 devices conduct equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each signal path has very similar characteristics in both directions so they can be used as both multiplexers and demultiplexer to support analog signals. 9.3.2 Rail-to-Rail Operation The valid signal path input and output voltage for the TMUX4051, TMUX4052, and TMUX4053 ranges from VSS to VDD. 9.3.3 1.8 V Logic Compatible Inputs The TMUX4051, TMUX4052, and TMUX4053 support 1.8-V logic compatible control for all logic control inputs. 1.8-V logic level inputs allows the multiplexers to interface with processors that have lower logic I/O rails and eliminates the need for an external voltage translator, which saves both space and BOM cost. For more information on 1.8-V logic implementation, refer to Simplifying Design with 1.8 V logic Muxes and Switches. 9.3.4 Device Functional Modes When the EN pin of the TMUX405x devices is pulled low, one of the switches is closed based on the state of the address or select pins. When the EN pin is pulled high, all the switches are in an open state regardless of the state of the address or select pins. Unused logic control pins must be tied to GND or VDD to be certain that the device does not consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx and Dx) should be connected to GND. 22 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 9.3.5 Truth Tables Table 9-1, Table 9-2, and Table 9-3 provides the truth tables for the TMUX4051 respectively. Table 9-1. TMUX4051 Truth Table EN A2 A1 A0 Selected Signal Path Connected To Drain (D) Pin 0 0 0 0 S0 0 0 0 1 S1 0 0 1 0 S2 0 0 1 1 S3 0 1 0 0 S4 0 1 0 1 S5 0 1 1 0 S6 0 1 1 1 S7 1 X(1) X(1) X(1) All inputs are unselected (HI-Z) (1) X denotes do not care. Table 9-2. TMUX4052 Truth Table EN A1 A0 Selected Signal Path Connected To Drain (DA and DB) Pins 0 0 0 S0A to DA S0B to DB 0 0 1 S1A to DA S1B to DB 0 1 0 S2A to DA S2B to DB 0 1 1 S3A to DA S3B to DB 1 X(1) X(1) All inputs are unselected (HI-Z) (1) X denotes do not care. Table 9-3. TMUX4053 Truth Table (1) EN SEL1 SEL2 SEL3 0 0 X X S1A to D1 0 1 X X S1B to D1 0 X 0 X S2A to D2 0 X 1 X S2B to D2 0 X X 0 S3A to D3 0 X X 1 S3B to D3 1 X(1) X(1) X(1) Selected Signal Path Connected To Drain Pins All inputs are unselected (HI-Z) X denotes do not care. The Enable pin, EN, of the TMUX405x devices have a weak internal pull-up resistor to put the devices into a disabled state upon power up. The SELx / Address pins (Ax) have weak internal pull-down resistors to put the switch into a defined logic state. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 Submit Document Feedback 23 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 10 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The TMUX405x devices offer good system performance across a wide operating supply (5 V to 24 V). These devices include 1.8 V logic compatible control input pins that enable operation in systems with 1.8 V I/O rails. These features make the TMUX405x a family of general purpose multiplexers and switches that can reduce system complexity, board size, and overall system cost. 10.2 Typical Application One useful application to take advantage of the TMUX405x features is multiplexing various signals into an ADC that is integrated into an MCU. Utilizing an integrated ADC in an MCU allows a system to minimize cost with a potential tradeoff of system performance when compared to an external ADC. The multiplexer allows for multiple inputs or sensors to be monitored with a single ADC pin of the device, which is critical in systems with limited I/O. The TMUX4052 is suitable for a similar design example using differential signals, or as two 4:1 multiplexers. VDD VSS VDD VI/O LDO #1 MCU S1 LDO #2 S2 LDO #3 RAM FLASH S3 S4 LM20 Analog Temp. Sensor LM20 Analog Temp. Sensor LM20 Analog Temp. Sensor D S5 Integrated 12-bit ADC S6 S7 Port I/O S8 TIMERS A2 A0 A1 GND EN 1.8 V Logic I/O System Inputs and Sensors Figure 10-1. Multiplexing Signals to an Integrated ADC with TMUX4051 24 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 10.3 Design Requirements Table 10-1 lists the parameters that must be used for this design example. Table 10-1. Design Parameters PARAMETERS VALUES Supply (VDD) 12 V I/O signal range 0 V to VDD (rail-to-rail) Control logic thresholds 1.8 V compatible 10.4 Detailed Design Procedure The TMUX4051, TMUX4052, and TMUX4053 can operate without any external components except for the supply decoupling capacitors. The MCU can control the enable and address pins through GPIOs to toggle between various inputs of the multiplexer. The enable pin should be connected to ground if the functionality is not required in the system. All inputs being muxed to the ADC of the MCU must fall within the Recommended Operating Conditions, including signal range and continuous current. For this design with a supply of 12 V, the signal range can be 0 V to 12 V. 10.5 Application Curves 0 -2 Gain (dB) -4 -6 -8 -10 -12 TMUX4053 TMUX4052 TMUX4051 -14 100k 1M 10M Frequency (Hz) 100M 1G TA = 25°C Figure 10-2. Bandwidth 10.6 Power Supply Recommendations The TMUX4051, TMUX4052, and TMUX4053 devices operate across a wide supply range of 5 V to 24 V. Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply pins to other components. Good power-supply decoupling is important to achieve optimum performance. For improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground and VSS to ground. Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems or systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground planes. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 Submit Document Feedback 25 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 10.7 Layout 10.7.1 Layout Guidelines Route high-speed signals using minimal vias and corners, which reduces signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points, through-hole pins are not recommended at high frequencies. Figure 10-3 shows an example of a PCB layout with the TMUX4051, TMUX4052, and TMUX4053. Some key considerations are as follows: • • • • Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the capacitor voltage rating is sufficient. Keep the input lines as short as possible. Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary. 10.7.2 Layout Example Via to GND plane Wide (low inductance) trace for power Wide (low inductance) trace for power C C VDD S0B VDD S2B VDD S6 S2 S2B S2A S2A D2 D S1 DB S1A S3B D1 S7 S0 S3B DA D3 S1B S5 S3 S1B S0A S3A S1A EN A0 EN S3A EN SEL1 TMUX4051 VSS A1 GND A2 To VSS TMUX4052 VSS A0 GND A1 To VSS C S4 C To VSS C C Wide (low inductance) trace for power TMUX4053 VSS SEL2 GND SEL3 Figure 10-3. TMUX4051, TMUX4052, and TMUX4053 Layout Example 26 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 TMUX4051, TMUX4052, TMUX4053 www.ti.com SCDS445B – MAY 2022 – REVISED MARCH 2023 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For releated documentation, see the following: • • • Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches application brief Texas Instruments, QFN/SON PCB Attachment application report Texas Instruments, Quad Flatpack No-Lead Logic Packages application report 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TMUX4051 TMUX4052 TMUX4053 Submit Document Feedback 27 PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TMUX4051BQBR ACTIVE WQFN BQB 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T4051 Samples TMUX4051DYYR ACTIVE SOT-23-THIN DYY 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T4051 Samples TMUX4051PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T4051 Samples TMUX4052BQBR ACTIVE WQFN BQB 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T4052 Samples TMUX4052DYYR ACTIVE SOT-23-THIN DYY 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T4052 Samples TMUX4052PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T4052 Samples TMUX4053BQBR ACTIVE WQFN BQB 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T4053 Samples TMUX4053DYYR ACTIVE SOT-23-THIN DYY 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T4053 Samples TMUX4053PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 T4053 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of