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TMUX6119
SCDS384A – SEPTEMBER 2018 – REVISED DECEMBER 2018
TMUX6119 ±16.5-V, Low Capacitance, Low-Leakage-Current, Precision, SPDT Switch
1 Features
3 Description
•
The TMUX6119 is a modern complementary metaloxide semiconductor (CMOS) single-pole, double
throw (SPDT) switch. The device works well with dual
supplies (±5 V to ±16.5 V), a single supply (10 V to
16.5 V), or asymmetric supplies. Both digital input
pins (EN and SEL) have transistor-transistor logic
(TTL) compatible thresholds, ensuring both TTL/
CMOS logic compatibility.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Wide Supply Range: ±5 V to ±16.5 V (Dual) or 10
V to 16.5 V (Single)
Latch-Up Performance Meets 100 mA per
JESD78 Class II Level A on all Pins
Low On-Capacitance: 6.4 pF
Low Input Leakage: 0.5 pA
Low Charge Injection: 0.19 pC
Rail-to-Rail Operation
Low On-Resistance: 120 Ω
Transition Time: 68 ns
Break-Before-Make Switching Action
EN Pin and SEL Pin Connectable to VDD with
Integrated Pull-down
Logic Levels: 2 V to VDD
Low Supply Current: 17 µA
Human Body Model (HBM) ESD Protection: ±2 kV
on All Pins
Industry-Standard SOT-23 Package
The TMUX6119 can be enabled or disabled by
controlling the EN pin. When disabled, both channel
switches are off. When enabled, the SEL pin can be
used to turn on channel A (SA to D) or channel B (SB
to D). Each channel conducts equally well in both
directions and has an input signal range that extends
to the supplies. The switches of TMUX6119 exhibit
break-before-make (BBM) switching action.
The TMUX6119 is part of Texas Instruments
Precision Switches and Multiplexers family. The
TMUX6119 has very low leakage currents and charge
injection, allowing the device to be used in high
precision measurement applications. The device also
provides excellent isolation capability by blocking
signal levels up to the supplies when the switches are
in the OFF position. A low supply current of 17 µA
enables usage in portable applications.
2 Applications
•
•
•
•
•
•
Factory Automation and Industrial Process
Controls
Programmable Logic Controllers (PLC)
Analog Input Modules
ATE Test Equipment
Digital Multimeters
Battery Monitoring Systems
Device Information(1)
PART NUMBER
TMUX6119
PACKAGE
SOT-23 (8)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACER
SPACER
Simplified Schematic
VDD
VSS
SA
D
SB
Decoder
EN
SEL
TMUX6119
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX6119
SCDS384A – SEPTEMBER 2018 – REVISED DECEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
6
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Thermal Information ..................................................
Recommended Operating Conditions.......................
Electrical Characteristics (Dual Supplies: ±15 V) .....
Switching Characteristics (Dual Supplies: ±15 V).....
Electrical Characteristics (Single Supply: 12 V)........
Switching Characteristics (Single Supply: 12 V).......
Typical Characteristics ..............................................
7
Parameter Measurement Information ................ 11
8
Detailed Description ............................................ 12
7.1 Truth Tables ............................................................ 11
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 19
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 21
9
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application ................................................. 22
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2018) to Revision A
•
2
Page
Changed the document status From: Advanced Information To: Production data ................................................................ 1
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SCDS384A – SEPTEMBER 2018 – REVISED DECEMBER 2018
5 Pin Configuration and Functions
DCN Package
8-Pin SOT-23
Top View
EN
1
8
SEL
VDD
2
7
SA
GND
3
6
D
VSS
4
5
SB
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
EN
1
I
Active high digital input. When this pin is low, both switches are turned off. When this pin is high,
the SEL logic input determine which switch is turned on.
VDD
2
P
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
GND
3
P
Ground (0 V) reference
VSS
4
P
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
SB
5
I/O
Source pin B. Can be an input or output.
D
6
I/O
Drain pin. Can be an input or output.
SA
7
I/O
Source pin A. Can be an input or output.
SEL
8
I
(1)
Logic control input.
I = input, O = output, I/O = input and output, P = power
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SCDS384A – SEPTEMBER 2018 – REVISED DECEMBER 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VDD to VSS
VDD to GND
Supply voltage
VSS to GND
UNIT
36
V
–0.3
18
V
–18
0.3
V
GND –0.3
VDD+0.3
V
VDIG
Digital input pin (SEL, EN) voltage
IDIG
Digital input pin (SEL, EN) current
–30
30
VANA_IN
Analog input pin (Sx) voltage
VSS–0.3
VDD+0.3
IANA_IN
Analog input pin (Sx) current
–30
30
VANA_OUT
Analog output pin (D) voltage
VSS–0.3
VDD+0.3
IANA_OUT
Analog output pin (D) current
–30
30
mA
TA
Ambient temperature
–55
140
°C
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
–65
mA
V
mA
V
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Thermal Information
TMUX6119
THERMAL METRIC (1)
DCN (SOT-23)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
180.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
138.8
°C/W
RθJB
Junction-to-board thermal resistance
90.4
°C/W
ΨJT
Junction-to-top characterization parameter
73.7
°C/W
ΨJB
Junction-to-board characterization parameter
90.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD to VSS
(1)
NOM
MAX
UNIT
Power supply voltage differential
10
33
V
VDD to GND
Positive power supply voltage (singlle supply, VSS = 0 V)
10
16.5
V
VDD to GND
Positive power supply voltage (dual supply)
5
16.5
V
VSS to GND
Negative power supply voltage (dual supply)
–16.5
–5
V
(1)
4
When VSS = 0 V, VDD can range from 10 V to 36 V.
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SCDS384A – SEPTEMBER 2018 – REVISED DECEMBER 2018
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
VS
(2)
NOM
MAX
UNIT
Source pins voltage
VSS
VDD
V
VD
Drain pin voltage
VSS
VDD
V
VDIG
Digital input pin (SEL, EN) voltage
0
VDD
V
ICH
Channel current (TA = 25°C )
–25
25
mA
TA
Ambient temperature
–40
125
℃
(2)
VDD and VSS can be any value as long as 10 V ≤ (VDD – VSS) ≤ 36 V.
6.5 Electrical Characteristics (Dual Supplies: ±15 V)
at TA = 25°C, VDD = 15 V, and VSS = -15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
V
120
135
Ω
140
165
Ω
TA = –40°C to +85°C
210
Ω
TA = –40°C to +125°C
245
Ω
ANALOG SWITCH
VA
Analog signal range
TA = –40°C to +125°C
VSS
VS = 0 V, IS = 1 mA
RON
On-resistance
VS = ±10 V, IS = 1 mA
2.4
ΔRON
On-resistance mismatch
between channels
VS = ±10 V, IS = 1 mA
6
Ω
TA = –40°C to +85°C
9
Ω
TA = –40°C to +125°C
11
Ω
45
Ω
47
Ω
49
Ω
22
RON_FLAT
RON_DRIFT
IS(OFF)
ID(OFF)
ID(ON)
On-resistance flatness
On-resistance drift
Source off leakage current (1)
Drain off leakage current (1)
Drain on leakage current
VS = –10 V, 0 V, +10 V, IS
TA = –40°C to +85°C
= 1 mA
TA = –40°C to +125°C
VS = 0 V
0.5
–0.02
nA
–0.12
0.05
nA
–1
0.2
nA
TA = –40°C to +85°C
Switch state is off, VS =
+10 V/ –10 V, VD = –10
V/ +10 V
TA = –40°C to +85°C
Switch state is on, VS =
+10 V/ –10 V, VD = –10
V/ +10 V
TA = –40°C to +85°C
–0.25
TA = –40°C to +125°C
–1.8
TA = –40°C to +125°C
–0.02
TA = –40°C to +125°C
%/°C
0.02
Switch state is off, VS =
+10 V/ –10 V, VD = –10
V/ + 10 V
0.005
0.02
nA
–0.12
0.05
nA
–1
0.2
nA
0.04
nA
0.1
nA
0.4
nA
–0.04
0.005
0.01
DIGITAL INPUT (EN, Ax pins)
VIH
Logic voltage high
VIL
Logic voltage low
RPD(EN)
Pull-down resistance on EN pin
2
V
0.8
6
V
MΩ
POWER SUPPLY
16
IDD
VDD supply current
VA = 0 V or 3.3 V, VS = 0
V
21
µA
22
µA
23
µA
10
µA
TA = –40°C to +85°C
11
µA
TA = –40°C to +125°C
12
µA
TA = –40°C to +85°C
TA = –40°C to +125°C
7
ISS
(1)
VSS supply current
VA = 0 V or 3.3 V, VS = 0
V
When VS is positive, VD is negative, and vice versa.
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6.6 Switching Characteristics (Dual Supplies: ±15 V)
at TA = 25°C, VDD = 15 V, and VSS = -15 V (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
VS = ±10 V, RL = 300 Ω , CL = 35 pF
tON
Enable turn-on time
Enable turn-off time
Transition time
ns
110
ns
VS = ±10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
121
ns
64
ns
VS = ±10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
57
78
ns
VS = ±10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
82
ns
88
ns
VS = 10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
99
ns
VS = 10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
106
ns
68
tBBM
Break-before-make time delay
VS = 10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
QJ
Charge injection
VS = 0 V, RS = 0 Ω , CL = 1 nF
OISO
Off-isolation
XTALK
Channel-to-channel crosstalk
IL
Insertion loss
ACPSRR
AC Power Supply Rejection
Ratio
68
UNIT
86
VS = 10 V, RL = 300 Ω , CL = 35 pF
tTRAN
MAX
VS = ±10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
VS = ±10 V, RL = 300 Ω , CL = 35 pF
tOFF
TYP
8
37
ns
–0.19
pC
RL = 50 Ω , CL = 5 pF, f = 1 MHz
–85
dB
RL = 50 Ω , CL = 5 pF, f = 1 MHz
–93
dB
RL = 50 Ω , CL = 5 pF, f = 1 MHz
-7.7
dB
RL = 10 kΩ , CL = 5 pF, VPP= 0.62 V on VDD, f= 1
MHz
–55
dB
RL = 10 kΩ , CL = 5 pF, VPP= 0.62 V on VSS, f= 1
MHz
–55
dB
BW
-3dB Bandwidth
RL = 50 Ω , CL = 5 pF
700
MHz
THD
Total harmonic distortion +
noise
RL = 10k Ω , CL = 5 pF, f= 20Hz to 20kHz
0.08
%
CIN
Digital input capacitance
VIN = 0 V or VDD
0.8
pF
CS(OFF)
Source off-capacitance
VS = 0 V, f = 1 MHz
1.9
2.8
pF
CD(OFF)
Drain off-capacitance
VS = 0 V, f = 1 MHz
4.3
4.7
pF
CS(ON),
CD(ON)
Source and drain oncapacitance
VS = 0 V, f = 1 MHz
6.4
8.1
pF
TYP
MAX
UNIT
VDD
V
(1)
Specified by design; not subject to production testing.
6.7 Electrical Characteristics (Single Supply: 12 V)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
ANALOG SWITCH
VA
Analog signal range
TA = –40°C to +125°C
TA = –40°C to +125°C
VSS
265
Ω
RON
On-resistance
VS = 10 V, IS = 1 mA
TA = –40°C to +85°C
355
Ω
TA = –40°C to +125°C
405
Ω
230
1
On-resistance mismatch
between channels
ΔRON
RON_DRIFT
6
On-resistance drift
VS = 10 V, IS = 1 mA
9
Ω
TA = –40°C to +85°C
12
Ω
TA = –40°C to +125°C
14
Ω
VS = 0 V
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0.48
%/°C
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SCDS384A – SEPTEMBER 2018 – REVISED DECEMBER 2018
Electrical Characteristics (Single Supply: 12 V) (continued)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
IS(OFF)
Source off leakage current (1)
TEST CONDITIONS
Switch state is off, VS =
T = –40°C to +85°C
10 V/ 1 V, VD = 1 V/ 10 V A
TA = –40°C to +125°C
MIN
TYP
MAX
UNIT
–0.02
0.005
0.02
nA
–0.08
0.04
nA
–0.75
0.13
nA
–0.02
ID(OFF)
Drain off leakage current (1)
Switch state is off, VS =
T = –40°C to +85°C
10 V/ 1 V, VD = 1 V/ 10 V A
TA = –40°C to +125°C
0.02
nA
–0.08
0.04
nA
–0.75
0.13
nA
0.04
nA
–0.04
ID(ON)
Drain on leakage current
Switch state is on, VS =
floating, VD = 1 V/ 10 V
0.005
0.01
TA = –40°C to +85°C
–0.16
0.08
nA
TA = –40°C to +125°C
–1.5
0.25
nA
DIGITAL INPUT (EN, Ax pins)
VIH
Logic voltage high
VIL
Logic voltage low
RPD(EN)
Pull-down resistance on EN pin
2
V
0.8
6
V
MΩ
POWER SUPPLY
11
IDD
(1)
VDD supply current
VA = 0 V or 3.3 V, VS = 0
V
14
µA
TA = –40°C to +85°C
16
µA
TA = –40°C to +125°C
17
µA
When VS is positive, VD is negative, and vice versa.
6.8 Switching Characteristics (Single Supply: 12 V)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
VS = 8 V, RL = 300 Ω , CL = 35 pF
tON
Enable turn-on time
Enable turn-off time
Transition time
73
UNIT
91
ns
119
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
130
ns
69
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
60
82
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
88
ns
93
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
104
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
112
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF
tTRAN
MAX
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
VS = 8 V, RL = 300 Ω , CL = 35 pF
tOFF
TYP
tBBM
Break-before-make time delay
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
QJ
Charge injection
VS = 6 V, RS = 0 Ω , CL = 1 nF
OISO
Off-isolation
XTALK
Channel-to-channel crosstalk
IL
Insertion loss
73
45
ns
0.1
pC
RL = 50 Ω , CL = 5 pF, f = 1 MHz
-85
dB
RL = 50 Ω , CL = 5 pF, f = 1 MHz
–100
dB
RL = 50 Ω , CL = 5 pF, f = 1 MHz
-15
dB
ACPSRR
AC Power Supply Rejection
Ratio
RL = 10 kΩ , CL = 5 pF, VPP= 0.62 V, f= 1 MHz
–55
dB
BW
-3dB Bandwidth
RL = 50 Ω , CL = 5 pF
440
MHz
CIN
Digital input capacitance
VIN = 0 V or VDD
(1)
10
1
pF
Specified by design; not subject to production testing.
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Switching Characteristics (Single Supply: 12 V) (continued)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CS(OFF)
Source off-capacitance
VS = 6 V, f = 1 MHz
2
2.9
pF
CD(OFF)
Drain off-capacitance
VS = 6 V, f = 1 MHz
4.9
5.3
pF
CS(ON),
CD(ON)
Source and drain oncapacitance
VS = 6 V, f = 1 MHz
7.4
8.9
pF
8
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6.9 Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
650
250
600
VDD= 12V
VSS = -12V
550
On Resistance (:)
On Resistance (:)
200
VDD= 13.5V
VSS = -13.5V
150
100
VDD= 16.5V
VSS = -16.5V
VDD= 15V
VSS = -15V
50
VDD= 10V
VSS = 0V
500
VDD= 12V
VSS = 0V
450
400
350
300
250
200
VDD= 14V
VSS = 0V
150
0
-20
100
-15
-10
-5
0
5
10
Source or Drain Voltage (V)
15
0
20
2
4
6
8
10
Source or Drain Voltage (V)
D001
Dual Supply Operation (TA = 25°C)
12
14
D002
Single Supply Operation (TA = 25°C)
Figure 1. On-Resistance vs Source or Drain Voltage
Figure 2. On-Resistance vs Source or Drain Voltage
250
700
TA = 125qC
TA = 85qC
TA = 125qC
600
On Resistance (:)
On Resistance (:)
200
150
100
50
TA = 25qC
0
-15
500
TA = 85qC
400
300
200
TA = -40qC
100
TA = -40qC
TA = 25qC
0
-10
-5
0
5
Source or Drain Voltage (V)
10
15
0
2
VDD = 15 V, VSS = –15 V
10
12
D004
VDD = 12 V, VSS = 0 V
Figure 3. On-Resistance vs Source or Drain Voltage
Figure 4. On-Resistance vs Source or Drain Voltage
400
400
ID(ON)+
200
IS(OFF)+
ID(ON)_10V
200
ID(OFF)+
Leakage Current (pA)
Leakage Current (pA)
4
6
8
Source or Drain Voltage (V)
D003
0
-200
IS(OFF)-400
ID(OFF)-
-600
ID(OFF)_10V
IS(OFF)_10V
0
-200
IS(OFF)_1V
-400
ID(OFF)_1V
-600
-800
-1000
-50
ID(ON)-25
0
25
50
75
100
Ambient Temperature (qC)
ID(ON)_1V
125
150
-800
-50
-25
D005
VDD = 15 V, VSS = –15 V
0
25
50
75
100
Ambient Temperature (qC)
125
150
D006
VDD = 12 V, VSS = 0 V
Figure 5. . Leakage Current vs Temperature
Figure 6. Leakage Current vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
8
6
VDD= 10V
VSS = -10V
1
Charge Injection (pC)
Charge Injection (pC)
2
0
VDD= 15V
VSS = -15V
-1
-2
-15
-10
VDD= 12V
VSS = 0V
-5
0
5
Source Voltage (V)
VDD= 10V
VSS = -10V
4
2
0
-2
-4
10
-8
-15
15
-10
-5
D007
TA = 25°C
0
5
Drain Voltage (V)
10
15
D008
TA = 25°C
Figure 7. Charge Injection vs Source Voltage
Figure 8. Charge Injection vs Drain Voltage
120
0
tON(VDD= 12V, VSS= 0V)
tON(VDD= 15V, VSS= -15V)
VDD = 12
VSS = 0V
-20
90
Off Isolation (dB)
Enable Turn On/Off Time (ns)
VDD= 12V
VSS = 0V
VDD= 15V
VSS = -15V
-6
60
30
-40
-60
VDD = 15
VSS = -15V
-80
tOFF(VDD= 15V, VSS= -15V)
-100
tOFF(VDD= 12V, VSS= 0V)
0
-50
-25
0
25
50
75
100
Ambient Temperature (qC)
125
-120
1E+5
150
1E+6
D009
1E+7
Frequency (Hz)
1E+8
5E+8
D010
TA = 25°C
Figure 9. Enable turn-on and turn-off time
Figure 10. Off Isolation vs Frequency
0
100
50
-20
THD + N (%)
Crosstalk (dB)
-40
VDD = 12
VSS = 0V
-60
-80
-140
1E+5
VDD = 15
VSS = -15V
1E+6
1E+7
Frequency (Hz)
2
1
0.5
1E+8
5E+8
0.02
0.01
1E+1
D011
TA = 25°C
VDD = 15
VSS = -15V
1E+2
1E+3
Frequency (Hz)
1E+4
1E+5
D012
TA = 25°C
Figure 11. Crosstalk vs Frequency
10
VDD = 5V
VSS = -5V
0.2
0.1
0.05
-100
-120
20
10
5
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Figure 12. THD+N vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
-5
10
9
CD(ON), CS(ON)
8
Capactiance (pF)
Insertion Loss (dB)
-10
-15
-20
CD(OFF)
7
6
5
4
3
-25
CS(OFF)
2
-30
1E+5
1E+6
1E+7
Frequency(Hz)
1E+8
1
-15
1E+9
-12
-9
VDD = 15 V, VSS = –15 V, TA = 25°C
-3
0
3
6
Source Voltage (V)
9
12
15
D014
VDD = 15 V, VSS = –15 V, TA = 25°C
Figure 13. On Response vs Frequency
Figure 14. Capacitance vs Source Voltage
10
0
CD(ON), CS(ON)
-20
8
VSS
CD(OFF)
-40
ACPSRR (dB)
Capactiance (pF)
-6
D013
6
4
CS(OFF)
-60
-80
VDD
-100
2
-120
0
0
2
4
6
8
Source Voltage (V)
10
12
-140
1E+5 2E+5
5E+5 1E+6 2E+6 5E+6 1E+7 2E+7
Frequency (Hz)
D015
VDD = 12 V, VSS = 0 V, TA = 25°C
5E+7 1E+8
D016
VDD = 15 V, VSS = –15 V, TA = 25°C
Figure 15. Capacitance vs Source Voltage
Figure 16. ACPSRR vs Frequency
7 Parameter Measurement Information
7.1 Truth Tables
Table 1 shows the truth tables for theTMUX6119.
Table 1. TMUX6119 Truth Table
STATE
(1)
EN
SEL
Switch A (SA
to D)
Switch B (SB
to D)
0
X (1)
OFF
OFF
1
0
ON
OFF
1
1
OFF
ON
X denotes don't care..
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8 Detailed Description
8.1 Overview
The TMUX6119 has a low on and off leakage currents and ultra-low charge injection, allowing the device to be
used in high precision measurement applications. The device also provides excellent isolation capability by
blocking signal levels up to the supplies when the switches are in the OFF position. A low supply current of 17
µA enables usage in portable applications.
8.1.1 On-Resistance
The on-resistance of the TMUX6119 is the ohmic resistance across the source (SA or SB) and drain (D) pins of
the device. The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote
on-resistance. The measurement setup used to measure RON is shown in Figure 17. Voltage (V) and current (ICH)
are measured using this setup, and RON is computed as shown in Equation 1:
V
D
S
ICH
VS
Figure 17. On-Resistance Measurement Setup
RON = V / ICH
(1)
8.1.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF).
The setup used to measure both off-leakage currents is shown in Figure 18.
ID (OFF)
Is (OFF)
A
S
D
VS
A
VD
Figure 18. Off-Leakage Measurement Setup
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Overview (continued)
8.1.3 On-Leakage Current
On-leakage current is defined as the leakage current that flows into or out of the drain pin when the switch is in
the on state. The source pin is left floating during the measurement. Figure 19 shows the circuit used for
measuring the on-leakage current, denoted by ID(ON).
ID (ON)
D
S
A
NC
NC = No Connection
VD
Figure 19. On-Leakage Measurement Setup
8.1.4 Transition Time
Transition time is defined as the time taken by the output of the TMUX6119 to rise or fall to 90% of the transition
after the digital address signal has fallen or risen to 50% of the transition. Figure 20 shows the setup used to
measure transition time, denoted by the symbol tt.
3V
VS
tr < 20 ns
VIN
50%
50%
VDD
VSS
VDD
VSS
SB
Output
D
tf < 20 ns
SA
0V
SEL
VS
Output
300 Ÿ
35 pF
0.9 VS
tTRAN 2
tTRAN 1
0.1 VS
VSEL
GND
tTRAN = max ( tTRAN 1, tTRAN 2)
Figure 20. Transition-Time Measurement Setup
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Overview (continued)
8.1.5 Break-Before-Make Delay
Break-before-make delay is a safety feature that prevents two inputs from connecting when the TMUX6119 is
switching. The TMUX6119 output first breaks from the on-state switch before making the connection with the
next on-state switch. The time delay between the break and the make is known as break-before-make delay.
Figure 21 shows the setup used to measure break-before-make delay, denoted by the symbol tBBM.
3V
VS
VDD
VSS
VDD
VSS
SB
Output
D
VIN
SA
0V
SEL
300 Ÿ
35 pF
VS
0.8 VS
Output
VSEL
GND
tBBM 2
tBBM 1
0V
tBBM = min ( tBBM 1, tBBM 2)
Figure 21. Break-Before-Make Delay Measurement Setup
8.1.6 Enable Turn-On and Enable Turn-Off Time
Enable turn-on time is defined as the time taken by the output of the TMUX6119 to rise to a 90% final value after
the EN signal has risen to a 50% final value. Figure 22 shows the setup used to measure turn-on time. Enable
turn-on time is denoted by the symbol tON.
Enable turn off time is defined as the time taken by the output of the TMUX6119 to fall to a 10% initial value after
the EN signal has fallen to a 50% initial value. Figure 22 shows the setup used to measure turn-off time. Enable
Turn-off time is denoted by the symbol tOFF.
3V
VS
50%
VIN
VDD
VSS
VDD
VSS
SA
Output
D
50%
SB
0V
EN
VS
Output
300 Ÿ
35 pF
0.9 VS
tOFF (EN)
tON (EN)
0.1 VS
VEN
GND
Figure 22. Turn-On and Turn-Off Time Measurement Setup
14
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Overview (continued)
8.1.7 Charge Injection
The TMUX6119 have a simple transmission-gate topology. Any mismatch in capacitance between the NMOS
and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the
gate signal. The amount of charge injected into the source or drain of the device is known as charge injection,
and is denoted by the symbol QINJ. Figure 23 and Figure 24 shows the setup used to measure charge injection
from source to drain and from drain to source. The charge injection is optimized for the TMUX6119 from the
direction of source to drain.
VS
3V
VDD
VSS
VDD
VSS
SB
VIN
D
RS
VS
Output
SA
NC
0V
EN
Output
VS
QINJ = CL ×
VOUT
1 nF
VOUT
VEN
GND
Figure 23. Source to Drain Charge-Injection Measurement Setup
3V
Output
VDD
VSS
VDD
VSS
VS
SB
D
VIN
NC
0V
VS
QINJ = CL ×
VOUT
RS
VS
1 nF
Output
SA
SEL
VOUT
VSEL
GND
Figure 24. Drain to Source Charge-Injection Measurement Setup
8.1.8 Off Isolation
Off isolation is defined as the voltage at the drain pin (D) of the TMUX6119 when a 1-VRMS signal is applied to
the source pin (SA or SB) of an off-channel. Figure 25 shows the setup used to measure off isolation. Use
Equation 2 to compute off isolation.
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Overview (continued)
Network Analyzer
VDD
VSS
VDD
VSS
SA
NC SB
50 Ÿ
VOUT
D
VS
50 Ÿ
SEL
GND
VSEL
Figure 25. Off Isolation Measurement Setup
Off Isolation
§V
·
20 ˜ Log ¨ OUT ¸
V
© S ¹
(2)
8.1.9 Channel-to-Channel Crosstalk
Channel-to-channel crosstalk is defined as the voltage at the source pin (SA or SB) of an off-channel, when a 1VRMS signal is applied at the source pin of an on-channel. Figure 26 shows the setup used to measure, and
Equation 3 is the equation used to compute, channel-to-channel crosstalk.
Network Analyzer
VDD
VSS
VDD
VSS
SxA
Dx
VOUT
SxB
50 Ÿ
50 Ÿ
SEL
VS
50 Ÿ
VSEL
GND
Figure 26. Channel-to-Channel Crosstalk Measurement Setup
Channel-to-Channel Crosstalk
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
(3)
8.1.10 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to the
source pin of an on-channel, and the output is measured at the drain pin of the TMUX6119. Figure 27 shows the
setup used to measure bandwidth of the mux. Use Equation 4 to compute the attenuation.
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Overview (continued)
Network Analyzer
VDD
VSS
VDD
VSS
SA
NC SB
VOUT
D
VS
50 Ÿ
SEL
GND
VSEL
Figure 27. Bandwidth Measurement Setup
Attenuation
§V ·
20 ˜ Log ¨ 2 ¸
© V1 ¹
(4)
8.1.11 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the
ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the mux
output. The on-resistance of the TMUX6119 varies with the amplitude of the input signal and results in distortion
when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as
THD+N. Figure 28 shows the setup used to measure THD+N of the TMUX6119.
Audio Precision
VDD
VSS
VDD
VSS
SA
NC SB
RS
VOUT
D
VS
10N Ÿ
SEL
GND
VSEL
Figure 28. THD+N Measurement Setup
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Overview (continued)
8.1.12 AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply
voltage pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine
wave of 620 mVPP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is
the AC PSRR. Figure 29 shows the setup used to measure ACPSRR of the TMUX6119.
VDD
Network Analyzer
DC Bias
Injector
VSS
VSS
VDD
620 mVPP
VBIAS
VIN
SA
SB
SW
SW
NC
VOUT
50 Ÿ
D
10N Ÿ
5 pF
VSEL
SEL
GND
VBIAS = 0 V
ACPSRR= 20 × Log (VOUT/ VIN)
Figure 29. AC PSRR Measurement Setup
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8.2 Functional Block Diagram
VDD
VSS
SA
D
SB
Decoder
EN
SEL
TMUX6119
8.3 Feature Description
8.3.1 Ultra-low Leakage Current
The TMUX6119 provide extremely low on- and off-leakage currents. The TMUX6119 is capable of switching
signals from high source-impedance inputs into a high input-impedance op amp with minimal offset error
because of the ultralow leakage currents. Figure 30 shows typical leakage currents of the TMUX6119 versus
temperature.
400
ID(ON)+
Leakage Current (pA)
200
IS(OFF)+
ID(OFF)+
0
-200
IS(OFF)-400
ID(OFF)-
-600
-800
-1000
-50
ID(ON)-25
0
25
50
75
100
Ambient Temperature (qC)
125
150
D005
Figure 30. Leakage Current vs Temperature
8.3.2 Ultra-low Charge Injection
The TMUX6119 is implemented with simple transmission gate topology, as shown in Figure 31. Any mismatch in
the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch
is opened or closed.
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Feature Description (continued)
OFF ON
CGSN
CGDN
S
D
CGSP
CGDP
OFF ON
Figure 31. Transmission Gate Topology
The TMUX6119 utilizes special charge-injection cancellation circuitry that reduces the source (SA or SB)-to-drain
(D) charge injection to as low as 0.19 pC at VS = 0 V, as shown in Figure 32.
Charge Injection (pC)
2
VDD= 10V
VSS = -10V
1
0
-1
-2
-15
VDD= 15V
VSS = -15V
-10
VDD= 12V
VSS = 0V
-5
0
5
Source Voltage (V)
10
15
D007
Figure 32. Charge Injection vs Source Voltage
The drain (D)-to-source (SA or SB) charge injection becomes important when the device is used as a
demultiplexer (demux), where D becomes the input and Sx becomes the output. Figure 33 shows the drain-tosource charge injection across the full signal range.
20
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Feature Description (continued)
8
Charge Injection (pC)
6
VDD= 10V
VSS = -10V
4
2
0
-2
-4
VDD= 15V
VSS = -15V
-6
-8
-15
-10
-5
VDD= 12V
VSS = 0V
0
5
Drain Voltage (V)
10
15
D008
Figure 33. Charge Injection vs Drain Voltage
8.3.3 Bidirectional and Rail-to-Rail Operation
The TMUX6119 conducts equally well from source (SA or SB) to drain (D) or from drain (D) to source (SA or
SB). Each TMUX6119 channel has very similar characteristics in both directions. The valid analog signal for
TMUX6119 ranges from VSS to VDD. The input signal to the TMUX6119 swings from VSS to VDD without any
significant degradation in performance.
8.4 Device Functional Modes
When the EN pin of the TMUX6119 is pulled high, one of the two switches is closed based on the state of the
SEL pin. When the EN pin is pulled low, both switches remain open irrespective of the state of the SEL pin. The
EN pin is weakly pull-down internally through a 6MΩ resistor, thereby setting each channel to the open state if
the EN pin is not actively driven. The SEL pin is also weakly pulled-down through an internal 6Mohm resistor,
allowing channel A (SA to D) to be selected by default when EN pin is driven high. Both the EN pin and the SEL
pin can be connected to VDD (as high as 16.5 V).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TMUX6119 offers outstanding input / output leakage current and ultra-low charge injection performance. The
on-capacitance of the TMUX6119 is also very low. These properties make the TMUX6119 ideal for implementing
high precision industrial systems requiring selection of one of two inputs or outputs.
9.2 Typical Application
One application to take advantage of TMUX6119’s precision performance is the implementation of the chopper
amplifier. The chopper amplifier was developed in the 1950s to achieve ultra-low offset voltage and low offset
voltage drift over time and temperature. It also drastically reduces low frequency 1/f (flicker) noise. These
attributes make the chopper amplifier ideal for small signal conditioning. Figure 34 illustrates a classic example of
a simple chopper amplifier implemented with two TMUX6119 SPDT switches.
SW
Control
S
VIN
Z
C1
C2
LFP
S
A1
±
Z
TMUX6119
R1
Wideband
Amplifier
A2
+
TMUX6119
VOUT
Integrator
R2
Figure 34. Example of classic chopper amplifier implemented with two TMUX6119
9.2.1 Design Requirements
The goal of a chopper-amplifier design is to produce extremely high DC precision by continuously self-cancelling
input offset voltage even during variations in temperature, time, common-mode voltage, and power supply
voltage, while reducing low-frequency 1/f (flicker) voltage.
22
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Typical Application (continued)
9.2.2 Detailed Design Procedure
The theory of operation for the chopper amplifier relies on the concept of converting a DC input signal to AC
before feeding it into an AC-coupled wideband amplifier. The conversion utilizes a SPDT switches to “chop” the
input DC signal into an AC voltage. The output of the amplifier is then modulated by another SPDT switch to
convert the signal back to DC. The output of the switch is then low-pass filtered (or integrated) to smooth and
produce the final DC output.
The operation of the chopper amplifier consists of 2 phases, the sampling (S) phase and the auto-zero (Z)
phase. During the auto-zero phase, the switches are toggled to the Z position, and capacitors C1 and C2 are
charged to the amplifier input and output offset voltage, respectively. During the sampling phase, the switches
are toggled to the S position, during which VIN is connected to VOUT through C1, the wideband amplifier, C2,
and the integrator. Input DC voltage is AC-coupled by capacitor C1 and amplified by the wideband amplifier A1.
C2 helps reduce any DC component caused by the amplifier’s input offset voltage, and the integrator helps
smooth out the output signals to produce desired DC voltage output.
Several mechanisms helps reduce overall noise of the chopper-amplifier design. The DC gain, being the product
of the AC stage and the DC gain of the integrator, can easily reach an open-loop gain of 160 dB or higher and
therefore reduce the gain error, VOUT/ (A1×A2) to almost zero. The offset and drift in the output integrator stage
are nulled by the DC gain of the preceding AC stage. DC drifts in the AC stage are also non-factors because the
amplification stage is AC-coupled. The 1/f noise of the wideband amplifier is modulated to higher frequencies by
the demodulator.
Note that the input signal frequency shall be much less than one-half of the chopping frequency to prevent
aliasing errors in this chopper amplifier implementation. The chopper frequency, in turn, is restricted by the
wideband amplifier’s gain-phase limitations as well as errors induced by switch transition time and charge
injection. The TMUX6119 ‘s switch transition time is only 68 ns (typ) and average charge injection is less than
0.19pC, making it ideal for the chopper amplifier implementation. However, the input signal frequency is still
limited by the amplifier’s performance. If higher sampling frequency is required, a chopper-stabilized amplifier, or
an integrated zero-drift amplifier (such as the OPA2188), can be used to satisfy the requirement.
9.2.3 Application Curve
Fast transition time and small charge injection are two critical parameters for the SPDT switches used in the
chopper amplifier design. Figure 35 shows the plot for the charge injection vs. source voltage for the TMUX6119.
Charge Injection (pC)
2
VDD= 10V
VSS = -10V
1
0
-1
-2
-15
VDD= 15V
VSS = -15V
-10
VDD= 12V
VSS = 0V
-5
0
5
Source Voltage (V)
10
15
D007
Figure 35. Charge Injection vs Source Voltage
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10 Power Supply Recommendations
The TMUX6119 operates across a wide supply range of ±5 V to ±16.5 V (10 V to 16.5 V in single-supply mode).
They also perform well with unsymmetric supplies such as VDD = 12 V and VSS= –5 V. For reliable operation, use
a supply decoupling capacitor ranging between 0.1 µF to 10 µF at both the VDD and VSS pins to ground.
The on-resistance of the TMUX6119 varies with supply voltage, as illustrated in Figure 36.
250
On Resistance (:)
200
VDD= 12V
VSS = -12V
VDD= 13.5V
VSS = -13.5V
150
100
VDD= 15V
VSS = -15V
50
0
-20
-15
VDD= 16.5V
VSS = -16.5V
-10
-5
0
5
10
Source or Drain Voltage (V)
15
20
D001
Figure 36. On-Resistance Variation With Supply and Input Voltage
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11 Layout
11.1 Layout Guidelines
Figure 37 shows an example of a PCB layout with the TMUX6119.
Some key considerations are:
1. Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure
that the capacitor voltage rating is sufficient for the VDD and VSS supplies.
2. Keep the input lines as short as possible. In case of the differential signal, make sure the A inputs and B
inputs are as symmetric as possible.
3. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
4. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
EN
C
Via to
ground plane
VDD
SEL
SA
TMUX6119
C
GND
D
VSS
SB
Figure 37. TMUX6119 Layout Example
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Product Folder Links: TMUX6119
25
TMUX6119
SCDS384A – SEPTEMBER 2018 – REVISED DECEMBER 2018
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
• OPA2188 0.03-μV/°C Drift, Low-Noise, Rail-to-Rail Output, 36-V, Zero-Drift Operational Amplifiers (SBOS525)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX6119
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMUX6119DCNR
ACTIVE
SOT-23
DCN
8
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1QAC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
