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TMUX6121, TMUX6122, TMUX6123
SCDS398 – DECEMBER 2018
TMUX612x ±16.5-V, Low-Capacitance, Low-Leakage-Current,
Precision, Dual SPST Switches
1 Features
3 Description
•
The TMUX6121, TMUX6122, and TMUX6123 are
modern complementary metal-oxide semiconductor
(CMOS) devices that have two independently
selectable single-pole, single-throw (SPST) switches.
The devices work well with dual supplies (±5 V to
±16.5 V), a single supply (10 V to 16.5 V), or
asymmetric supplies. All digital inputs have transistortransistor logic (TTL) compatible thresholds, ensuring
both TTL and CMOS logic compatibility.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Wide Supply Range: ±5 V to ±16.5 V (dual) or 10
V to 16.5 V (single)
Latch-Up Performance Meets 100 mA per
JESD78 Class II Level A on all Pins
Low On-Capacitance: 4.2 pF
Low Input Leakage: 0.5 pA
Low Charge Injection: 0.51 pC
Rail-to-Rail Operation
Low On-Resistance: 120 Ω
Fast Switch Turn-On Time: 68 ns
Break-Before-Make Switching (TMUX6123)
SELx Pin Connectable to VDD With Integrated
Pull-down
Logic Levels: 2 V to VDD
Low Supply Current: 16 µA
Human Body Model (HBM) ESD Protection: ± 2kV
on All Pins
Industry-Standard VSSOP Package
2 Applications
•
•
•
•
•
•
Factory Automation and Industrial Process
Controls
Programmable Logic Controllers (PLC)
Analog Input Modules
ATE Test Equipment
Digital Multimeters
Battery Monitoring Systems
The switches are turned on with Logic 1 on the digital
control inputs in the TMUX6121. Logic 0 is required
to turn on switches in the TMUX6122. The
TMUX6123 has one switch with similar digital control
logic to the TMUX6121 while the logic is inverted on
the other switch. The TMUX6123 exhibits breakbefore-make switching, allowing the device to be
used in the cross-point switching application.
The TMUX6121, TMUX6122, and TMUX6123 are
part of the precision switches and multiplexers family
of devices. The devices have very low leakage
current and low charge injection, allowing them to be
used in high-precision measurement applications.
Low supply current of 16 µA enables the device
usage in portable applications.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TMUX6121
TMUX6122
VSSOP (10)
3.00 mm × 3.00 mm
TMUX6123
(1) For all available packages, see the package option addendum
at the end of the data sheet.
SPACER
Simplified Schematic
VDD
VSS
VDD
SW
VSS
VDD
SW
S1
D1
D1
S1
SW
D2
S2
SW
S1
SW
S2
D2
S2
SEL1
SEL1
SEL2
SEL2
SEL2
TMUX6122
D1
SW
SEL1
TMUX6121
VSS
D2
TMUX6123
ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX6121, TMUX6122, TMUX6123
SCDS398 – DECEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
6
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Thermal Information ..................................................
Recommended Operating Conditions.......................
Electrical Characteristics (Dual Supplies: ±15 V) .....
Switching Characteristics (Dual Supplies: ±15 V).....
Electrical Characteristics (Single Supply: 12 V)........
Switching Characteristics (Single Supply: 12 V).......
Typical Characteristics ..............................................
7
Parameter Measurement Information ................ 11
8
Detailed Description ............................................ 12
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 19
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
12.7
7.1 Truth Tables ............................................................ 11
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
8.1 Overview ................................................................. 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
December 2018
*
Initial release.
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Product Folder Links: TMUX6121 TMUX6122 TMUX6123
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SCDS398 – DECEMBER 2018
5 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
SEL1
1
10
SEL2
S1
2
9
VDD
D1
3
8
GND
D2
4
7
NC
S2
5
6
VSS
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
SEL1
1
I
S1
2
I/O
Source pin 1. Can be an input or output.
D1
3
I/O
Drain pin 1. Can be an input or output.
D2
4
I/O
Drain pin 2. Can be an input or output.
S2
5
I/O
Source pin 2. Can be an input or output.
VSS
6
P
NC
7
No Connect
No internal connection.
GND
8
P
Ground (0 V) reference.
VDD
9
P
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and
GND.
SEL2
10
I
Logic control input 2.
Logic control input 1.
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
Copyright © 2018, Texas Instruments Incorporated
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3
TMUX6121, TMUX6122, TMUX6123
SCDS398 – DECEMBER 2018
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VDD to VSS
VDD to GND
UNIT
36
V
–0.3
18
V
–18
0.3
V
GND –0.3
VDD+0.3
V
Supply voltage
VSS to GND
VDIG
Digital input pin (SEL1, SEL2) voltage
IDIG
Digital input pin (SEL1, SEL2) current
–30
30
VANA_IN
Analog input pin (Sx) voltage
VSS–0.3
VDD+0.3
IANA_IN
Analog input pin (Sx) current
–30
30
VANA_OUT
Analog output pin (Dx) voltage
VSS–0.3
VDD+0.3
IANA_OUT
Analog output pin (Dx) current
–30
30
mA
TA
Ambient temperature
–55
140
°C
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
–65
mA
V
mA
V
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Thermal Information
THERMAL METRIC (1)
TMUX6121/ TMUX6122/
TMUX6123
UNIT
DGS (VSSOP)
10 PINS
RθJA
Junction-to-ambient thermal resistance
180.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
66.2
°C/W
RθJB
Junction-to-board thermal resistance
103.2
°C/W
ΨJT
Junction-to-top characterization parameter
11.2
°C/W
ΨJB
Junction-to-board characterization parameter
101.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD to VSS
(1)
NOM
MAX
UNIT
Power supply voltage differential
10
33
V
VDD to GND
Positive power supply voltage (singlle supply, VSS = 0 V)
10
16.5
V
VDD to GND
Positive power supply voltage (dual supply)
5
16.5
V
VSS to GND
Negative power supply voltage (dual supply)
–16.5
–5
V
(1)
4
VDD and VSS can be any value as long as 10 V ≤ (VDD – VSS) ≤ 33 V.
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SCDS398 – DECEMBER 2018
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
(2)
NOM
MAX
UNIT
VS
Source pins voltage
VSS
VDD
V
VD
Drain pin voltage
VSS
VDD
V
VSEL
Select pin (SEL1, SEL2) voltage
VSS
VDD
V
ICH
Channel current (TA = 25°C )
–25
25
mA
TA
Ambient temperature
–40
125
°C
(2)
VS is the voltage on both S pins.
6.5 Electrical Characteristics (Dual Supplies: ±15 V)
at TA = 25°C, VDD = 15 V, and VSS = -15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
V
120
135
Ω
140
165
Ω
TA = –40°C to +85°C
210
Ω
TA = –40°C to +125°C
245
Ω
ANALOG SWITCH
VA
Analog signal range
TA = –40°C to +125°C
TA = –40°C to +125°C
VSS
VS = 0 V, IS = 1 mA
RON
On-resistance
VS = ±10 V, IS = 1 mA
2.4
ΔRON
On-resistance mismatch
between channels
VS = ±10 V, IS = 1 mA
6
Ω
TA = –40°C to +85°C
9
Ω
TA = –40°C to +125°C
11
Ω
45
Ω
47
Ω
49
Ω
22
RON_FLAT
RON_DRIFT
IS(OFF)
ID(OFF)
ID(ON)
VS = –10 V, 0 V, +10 V, IS
TA = –40°C to +85°C
= 1 mA
TA = –40°C to +125°C
On-resistance flatness
On-resistance drift
VS = 0 V
Source off leakage current (1)
Drain off leakage current (1)
Drain on leakage current
0.5
–0.02
nA
–0.12
0.05
nA
–1
0.2
nA
TA = –40°C to +85°C
Switch state is off, VS =
+10 V/ –10 V, VD = –10
V/ +10 V
TA = –40°C to +85°C
Switch state is on, VS =
+10 V/ –10 V, VD = –10
V/ +10 V
TA = –40°C to +85°C
–0.25
TA = –40°C to +125°C
–1.8
TA = –40°C to +125°C
–0.02
TA = –40°C to +125°C
%/°C
0.02
Switch state is off, VS =
+10 V/ –10 V, VD = –10
V/ + 10 V
0.005
0.02
nA
–0.12
0.05
nA
–1
0.2
nA
0.04
nA
0.1
nA
0.4
nA
–0.04
0.005
0.01
DIGITAL INPUT (EN, Ax pins)
VIH
Logic voltage high
VIL
Logic voltage low
2
RPD(IN)
Pull-down resistance on INx
pins
V
0.8
6
V
MΩ
POWER SUPPLY
16
IDD
VA = 0 V or 3.3 V, VS = 0
V
VDD supply current
21
µA
TA = –40°C to +85°C
22
µA
TA = –40°C to +125°C
23
µA
10
µA
TA = –40°C to +85°C
11
µA
TA = –40°C to +125°C
12
µA
7
ISS
(1)
VA = 0 V or 3.3 V, VS = 0
V
VSS supply current
When VS is positive, VD is negative, and vice versa.
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6.6 Switching Characteristics (Dual Supplies: ±15 V)
at TA = 25°C, VDD = 15 V, and VSS = -15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VS = ±10 V, RL = 300 Ω , CL = 35 pF
tON
Switch turn-on time
Switch turn-off time
68
UNIT
86
ns
110
ns
VS = ±10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
121
ns
76
ns
VS = ±10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
57
82
ns
VS = ±10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
85
ns
tBBM
Break-before-make time delay
(TMUX6123 Only)
VS = 10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
QJ
Charge injection
OISO
Off-isolation
XTALK
IL
ACPSRR
MAX
VS = ±10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
VS = ±10 V, RL = 300 Ω , CL = 35 pF
tOFF
TYP
40
ns
VS = 0 V, RS = 0 Ω , CL = 1 nF
0.51
pC
RL = 50 Ω , CL = 5 pF, f = 1 MHz
–85
dB
Channel-to-channel crosstalk
RL = 50 Ω , CL = 5 pF, f = 1 MHz
–110
dB
Insertion loss
RL = 50 Ω , CL = 5 pF, f = 1 MHz
–7.7
dB
RL = 10 kΩ , CL = 5 pF, VPP= 0.62 V on VDD, f= 1
MHz
–61
dB
RL = 10 kΩ , CL = 5 pF, VPP= 0.62 V on VSS, f= 1
MHz
–61
dB
AC Power Supply Rejection
Ratio
20
BW
-3dB Bandwidth
RL = 50 Ω , CL = 5 pF
630
MHz
THD
Total harmonic distortion +
noise
RL = 10k Ω , CL = 5 pF, f= 20Hz to 20kHz
0.08
%
CIN
Digital input capacitance
VSELx = 0 V or VDD
1.2
CS(OFF)
Source off-capacitance
VS = 0 V, f = 1 MHz
1.9
2.5
pF
CD(OFF)
Drain off-capacitance
VS = 0 V, f = 1 MHz
2.2
2.6
pF
CS(ON),
CD(ON)
Source and drain oncapacitance
VS = 0 V, f = 1 MHz
4.2
5
pF
TYP
MAX
pF
6.7 Electrical Characteristics (Single Supply: 12 V)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
UNIT
ANALOG SWITCH
VA
Analog signal range
TA = –40°C to +125°C
VSS
230
RON
On-resistance
VS = 10 V, IS = 1 mA
TA = –40°C to +85°C
TA = –40°C to +125°C
1
ΔRON
On-resistance mismatch
between channels
VS = 10 V, IS = 1 mA
RON_DRIFT
On-resistance drift
VS = 0 V
TA = –40°C to +85°C
TA = –40°C to +125°C
IS(OFF)
Source off leakage current
Switch state is off, VS =
T = –40°C to +85°C
10 V/ 1 V, VD = 1 V/ 10 V A
TA = –40°C to +125°C
(1)
6
Switch state is off, VS =
T = –40°C to +85°C
10 V/ 1 V, VD = 1 V/ 10 V A
TA = –40°C to +125°C
Drain off leakage current (1)
Ω
355
Ω
405
Ω
9
Ω
12
Ω
14
0.005
Ω
%/°C
0.02
nA
–0.08
0.04
nA
–0.75
0.13
nA
0.02
nA
–0.08
0.04
nA
–0.75
0.13
nA
–0.02
ID(OFF)
V
265
0.48
–0.02
(1)
VDD
0.005
When VS is positive, VD is negative, and vice versa.
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Electrical Characteristics (Single Supply: 12 V) (continued)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
ID(ON)
TEST CONDITIONS
Switch state is on, VS =
floating, VD = 1 V/ 10 V
Drain on leakage current
MIN
TYP
MAX
UNIT
–0.04
0.01
0.04
nA
TA = –40°C to +85°C
–0.16
0.08
nA
TA = –40°C to +125°C
–1.5
0.25
nA
DIGITAL INPUT (EN, Ax pins)
VIH
Logic voltage high
VIL
Logic voltage low
2
RPD(IN)
Pull-down resistance on INx
pins
V
0.8
6
V
MΩ
POWER SUPPLY
VA = 0 V or 3.3 V, VS = 0
V
IDD
VA = 0 V or 3.3 V, VS = 0
V
VDD supply current
11
14
µA
VA = 0 V or 3.3 V, VS = 0
V
16
µA
VA = 0 V or 3.3 V, VS = 0
V
17
µA
6.8 Switching Characteristics (Single Supply: 12 V)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
74
82
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
89
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
93
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF
tON
Switch turn-on time
VS = 8 V, RL = 300 Ω , CL = 35 pF
tOFF
Switch turn-off time
75
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
83
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
85
ns
tBBM
Break-before-make time delay
(TMUX6123 only)
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
QJ
Charge injection
VS = 6 V, RS = 0 Ω , CL = 1 nF
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF, f = 1 MHz
XTALK
Channel-to-channel crosstalk
RL = 50 Ω , CL = 5 pF, f = 1 MHz
IL
Insertion loss
ACPSRR
AC Power Supply Rejection
Ratio
BW
CIN
56
UNIT
37
ns
0.14
pC
-85
dB
–115
dB
RL = 50 Ω , CL = 5 pF, f = 1 MHz
–15
dB
RL = 10 kΩ , CL = 5 pF, VPP= 0.62 V, f= 1 MHz
–61
dB
-3dB Bandwidth
RL = 50 Ω , CL = 5 pF
500
MHz
Digital input capacitance
VIN = 0 V or VDD
1.3
CS(OFF)
Source off-capacitance
VS = 6 V, f = 1 MHz
2.2
2.8
pF
CD(OFF)
Drain off-capacitance
VS = 6 V, f = 1 MHz
2.5
2.8
pF
CS(ON),
CD(ON)
Source and drain oncapacitance
VS = 6 V, f = 1 MHz
4.8
6.1
pF
Copyright © 2018, Texas Instruments Incorporated
20
pF
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6.9 Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
700
250
200
650
VDD= 13.6V
VSS = -13.5V
VDD= 12V
VSS = -12V
600
On Resistance (:)
On Resistance (:)
550
150
100
VDD= 15V
VSS = -15V
50
0
-20
VDD= 14V
VSS = 0V
500
450
VDD= 12V
VSS = 0V
400
350
300
250
VDD= 16.5V
VSS = -16.5V
200
VDD= 10V
VSS = 0V
150
100
-15
-10
-5
0
5
10
Source or Drain Voltage (V)
15
0
20
2
4
6
8
10
Source or Drain Voltage (V)
D001
12
14
D002
Dual Supply Operation (TA = 25°C)
Dual Supply Operation (TA = 25°C)
Figure 1. On-Resistance vs Source or Drain Voltage
Figure 2. On-Resistance vs Source or Drain Voltage
250
700
TA = 125qC
TA = 85qC
600
TA = 125qC
TA = 85qC
On Resistance (:)
On Resistance (:)
200
150
100
50
500
400
300
200
TA = 25qC
TA = -40qC
TA = -40qC
100
TA = 25qC
0
-15
0
-10
-5
0
5
Source or Drain Voltage (V)
10
15
0
2
4
6
8
Source or Drain Voltage (V)
D003
VDD = 15 V, VSS = –15 V
10
12
D004
VDD = 12 V, VSS = 0 V
Figure 3. On-Resistance vs Source or Drain Voltage
Figure 4. On-Resistance vs Source or Drain Voltage
400
400
ID(OFF)+
ID(ON)+
0
-200
ID(OFF)-
-400
IS(OFF)-
-600
IS(ON)_10V
200
IS(OFF)+
Leakage Current (pA)
Leakage Current (pA)
200
0
IS(OFF)_10V
-200
IS(OFF)_1V
-400
ID(ON)-
ID(OFF)_1V
ID(OFF)_10V
ID(ON)_1V
-800
-50
-25
0
25
50
75
100
Ambient Temperature (qC)
125
VDD = 15 V, VSS = –15 V
Figure 5. Leakage Current vs Temperature
8
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150
D005
-600
-50
-25
0
25
50
75
100
Ambient Temperature (qC)
125
150
D006
VDD = 12 V, VSS = 0 V
Figure 6. Leakage Current vs Temperature
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Typical Characteristics (continued)
7
VDD= 15V
VSS = -15V
1
5
VDD= 12V
VSS = 0V
Charge Injection (pC)
Charge Injection (pC)
2
0
VDD= 10V
VSS = -10V
-1
VDD= 15V
VSS = -15V
3
1
VDD= 10V
VSS = -10V
-1
-3
VDD= 12V
VSS = 0V
-5
-2
-15
-10
-5
0
5
Source Voltage (V)
10
-7
-15
15
-10
-5
D007
TA = 25°C
Figure 7. Charge Injection vs Source Voltage
D008
Figure 8. Charge Injection vs Drain Voltage
-20
tON(VDD= 12V, VSS= 0V)
tON(VDD= 15V, VSS= -15V)
Off Isolation (dB)
Switch Turn On/Off Time (ns)
15
0
VDD= 12V, VSS= 0V
120
90
60
-40
-60
-80
VDD= 15V, VSS= -15V
-100
tOFF(VDD= 15V, VSS= -15V)
-120
tOFF(VDD= 12V, VSS= 0V)
0
-50
10
TA = 25°C
150
30
0
5
Drain Voltage (V)
-25
0
25
50
75
100
Ambient Temperature (qC)
125
-140
1E+5
150
1E+6
1E+7
Frequency (Hz)
D009
1E+8
5E+8
D010
TA = 25°C
Figure 9. Turn-On and Turn-Off Times vs Temperature
Figure 10. Off Isolation vs Frequency
0
100
50
-20
VDD= 12V, VSS= 0V
THD + N (%)
Crosstalk (dB)
-40
-60
-80
2
1
0.5
VDD= 5V, VSS= -5V
VDD= 15V, VSS= -15V
0.2
0.1
0.05
-100
-120
-140
1E+5
20
10
5
VDD= 15V, VSS= -15V
1E+6
1E+7
Frequency (Hz)
1E+8
5E+8
0.02
0.01
1E+1
1E+2
1E+3
Frequency (Hz)
D011
VDD = 15 V, VSS = –15 V, TA = 25°C
Figure 11. Crosstalk vs Frequency
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1E+4
1E+5
D012
TA = 25°C
Figure 12. THD+N vs Frequency
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-5
0
-10
-20
ACPSRR (dB)
Insertion Loss (dB)
Typical Characteristics (continued)
-15
-20
-25
-40
VDD= 12V, VSS= 0V
-60
-80
VDD= 15V, VSS= -15V
-30
1E+5
1E+6
1E+7
Frequency(Hz)
1E+8
-100
1E+5
1E+9
D013
VDD = 15 V, VSS = –15 V, TA = 25°C
2E+53E+5 5E+5
1E+6
2E+63E+6 5E+6
Frequency (Hz)
Figure 13. On Response vs Frequency
7
7
5
4
CD(OFF)
3
2
5
4
CD(OFF)
3
2
1
1
CS(OFF)
CS(OFF)
0
-12
-9
-6
-3
0
3
6
Source Voltage (V)
9
12
VDD = 15 V, VSS = –15 V, TA = 25°C
Figure 15. Capacitance vs Source Voltage
10
CD(ON), CS(ON)
6
CS(ON), CD(ON)
Capactiance (pF)
Capactiance (pF)
Figure 14. ACPSRR vs Frequency
8
0
-15
D016
VDD = 15 V, VSS = –15 V, VPP= 0.62 V, TA = 25°C
8
6
1E+7
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15
D014
0
2
4
6
8
Source Voltage (V)
10
12
D015
VDD = 12 V, VSS = 0 V, TA = 25°C
Figure 16. Capacitance vs Source Voltage
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7 Parameter Measurement Information
7.1 Truth Tables
Table 1, Table 2, and Table 3 show the truth tables for the TMUX6121, TMUX6122, and TMUX6123, respectively
Table 1. TMUX6121 Truth Table
SELx
STATE
0
All Switch OFF
1
All Switch ON
Table 2. TMUX6122 Truth Table
SELx
STATE
0
All Switch ON
1
All Switch OFF
Table 3. TMUX6123 Truth Table
SELx
STATE
0
Switch 1 OFF
Switch 2 ON
1
Switch 1 ON
Switch 2 OFF
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8 Detailed Description
8.1 Overview
The TMUX6121, TMUX6122, and TMUX6123 are 2-channel single-pole/ single-throw (SPDT) switches that
support dual supplies (±5 V to ±16.5 V) or single supply (10 V to 16.5 V) operation. Each channel of the switch is
turned on or turned off based on the state of its corresponding SELx pin. The Functional Block Diagram section
provides a top-level block diagram of the switches.
8.1.1 On-Resistance
The on-resistance of the TMUX6121, TMUX6122, and TMUX6123 is the ohmic resistance across the source (Sx)
and drain (D) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol RON
is used to denote on-resistance. The measurement setup used to measure RON is shown in Figure 17. Voltage
(V) and current (ICH) are measured using this setup, and RON is computed as shown in Equation 1:
V
D
S
ICH
VS
Figure 17. On-Resistance Measurement Setup
RON = V / ICH
(1)
8.1.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF).
The setup used to measure both off-leakage currents is shown in Figure 18
ID (OFF)
Is (OFF)
A
VS
S
D
A
VD
Figure 18. Off-Leakage Measurement Setup
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Overview (continued)
8.1.3 On-Leakage Current
On-leakage current is defined as the leakage current that flows into or out of the drain pin when the switch is in
the on state. The source pin is left floating during the measurement. Figure 19 shows the circuit used for
measuring the on-leakage current, denoted by ID(ON).
ID (ON)
D
S
A
NC
NC = No Connection
VD
Figure 19. On-Leakage Measurement Setup
8.1.4 Turn-On and Turn-Off Time
Turn-on time is defined as the time taken by the output of the TMUX6121, TMUX6122, and TMUX6123 to rise to
a 90% final value after the SELx signal has risen (for NO switches) or fallen (for NC switches) to a 50% final
value. Figure 20 shows the setup used to measure turn-on time. Turn-on time is denoted by the symbol tON.
Turn off time is defined as the time taken by the output of the TMUX6121, TMUX6122, and TMUX6123 to fall to
a 10% initial value after the SELx signal has fallen (for NO switches) or risen (for NC switches) to a 50% initial
value. Figure 20 shows the setup used to measure turn-off time. Turn-off time is denoted by the symbol tOFF.
VDD
VSS
VDD
VSS
3V
TMUX6122
50%
VIN
50%
0V
VS
3V
TMUX6121
50%
VIN
50%
Sx
Output
Dx
SELx
300 Ÿ
35 pF
0V
VS
Output
0.9 VS
VIN
GND
tOFF
tON
0.1 VS
Figure 20. Transition-Time Measurement Setup
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Overview (continued)
8.1.5 Break-Before-Make Delay
The break-before-make delay is a safety feature of the TMUX6123 switch. The TMUX6123's ON switches first
break the connection before the OFF switches make connection. The time delay between the break and the
make is known as break-before-make delay. Figure 21 shows the setup used to measure break-before-make
delay, denoted by the symbol tBBM.
VDD
VSS
VDD
VSS
3V
TMUX6123
50%
VIN
50%
0V
VS
S1
D1
VS
VS
S2
D2
0.9 VS
0.9 VS
Output 1
Output 2
300 Ÿ
Output 2
VS
Output 1
300 Ÿ
SEL1,
SEL2
0V
0.9 VS
35 pF
35 pF
0.9 VS
tBBM2
GND
VIN
tBBM1
0V
tBBM= min (tBBM2, tBBM2)
Figure 21. Break-Before-Make Delay Measurement Setup
8.1.6 Charge Injection
The TMUX6121, TMUX6122, and TMUX6123 have a simple transmission-gate topology. Any mismatch in
capacitance between the NMOS and PMOS transistors results in a charge injected into the drain or source
during the falling or rising edge of the gate signal. The amount of charge injected into the source or drain of the
device is known as charge injection, and is denoted by the symbol QINJ. Figure 22 shows the setup used to
measure charge injection.
VDD
VSS
VDD
VSS
3V
TMUX6122
VIN
0V
Sx
3V
Output
Dx
RS
TMUX6121
VS
VIN
1 nF
SELx
0V
VS
Output
VIN
QINJ = CL ×
VOUT
GND
VOUT
Figure 22. Charge-Injection Measurement Setup
8.1.7 Off Isolation
Off isolation is defined as the voltage at the drain pin (Dx) of the TMUX6121, TMUX6122, and TMUX6123 when
a 1-VRMS signal is applied to the source pin (Sx) of an OFF switch. Figure 23 shows the setup used to measure
off isolation. Use Equation 2 to compute off isolation.
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Overview (continued)
Network Analyzer
VDD
VSS
VDD
VSS
Sx
VOUT
Dx
SELx
VS
50 Ÿ
50 Ÿ
VIN
GND
Figure 23. Off Isolation Measurement Setup
Off Isolation
§V
·
20 ˜ Log ¨ OUT ¸
V
© S ¹
(2)
8.1.8 Channel-to-Channel Crosstalk
Channel-to-channel crosstalk is defined as the voltage at the source pin (Sx) of an off-channel, when a 1-VRMS
signal is applied at the source pin (Sx) of an on-channel. Figure 24 shows the setup used to measure, and
Equation 3 is the equation used to compute, channel-to-channel crosstalk.
Network Analyzer
VOUT
VS
VDD
VSS
VDD
VSS
S1
D1
S2
D2
50 Ÿ
SELx
50 Ÿ
50 Ÿ
VIN
GND
Figure 24. Channel-to-Channel Crosstalk Measurement Setup
Channel-to-Channel Crosstalk
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
(3)
8.1.9 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to the
source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the TMUX6121, TMUX6122,
and TMUX6123. Figure 25 shows the setup used to measure bandwidth of the switch. Use Equation 4 to
compute the attenuation.
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Overview (continued)
Network Analyzer
VDD
VSS
VDD
VSS
Sx
VOUT
VS
Dx
SELx
50 Ÿ
VIN
GND
Figure 25. Bandwidth Measurement Setup
Attenuation
§V ·
20 ˜ Log ¨ 2 ¸
© V1 ¹
(4)
8.1.10 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the
ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the mux
output. The on-resistance of the TMUX6121, TMUX6122, and TMUX6123 varies with the amplitude of the input
signal and results in distortion when the drain pin is connected to a low-impedance load. Total harmonic
distortion plus noise is denoted as THD+N. Figure 26 shows the setup used to measure THD+N of the
TMUX6121, TMUX6122, and TMUX6123.
Audio Precision
VDD
VSS
VDD
VSS
Sx
RS
VS
VOUT
Dx
SELx
10N Ÿ
VIN
GND
Figure 26. THD+N Measurement Setup
8.1.11 AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply
voltage pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine
wave of 620 mVPP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is
the AC PSRR. Figure 27 shows the setup used to measure ACPSRR of the TMUX6121, TMUX6122, and
TMUX6123.
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Overview (continued)
VDD
Network Analyzer
DC Bias
Injector
VSS
VSS
VDD
620 mVPP
VBIAS
SW
Sx
VIN
VOUT
50 Ÿ
Dx
10N Ÿ
5 pF
VSEL
SELx
GND
VBIAS = 0 V
ACPSRR= 20 × Log (VOUT/ VIN)
Figure 27. AC PSRR Measurement Setup
The Functional Block Diagram section provides a top-level block diagram of the TMUX6121, TMUX6122, and
TMUX6123. The devices are 2-channel, single-ended, analog switches. Each channel is turned on or turned off
based on the state of the address lines and enable pin.
8.2 Functional Block Diagram
VDD
VSS
VDD
SW
VSS
VDD
SW
S1
D1
S2
SW
S1
SW
D1
S1
D1
SW
D2
S2
SEL2
S2
D2
SEL1
SEL2
TMUX6121
SW
D2
SEL1
SEL1
VSS
SEL2
TMUX6122
TMUX6123
ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT
8.3 Feature Description
8.3.1 Ultralow Leakage Current
The TMUX6121, TMUX6122, and TMUX6123 provide extremely low on- and off-leakage currents. The devices
are capable of switching signals from high source-impedance inputs into a high input-impedance op amp with
minimal offset error because of the ultralow leakage currents. Figure 28 shows typical leakage currents of the
devices versus temperature.
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Feature Description (continued)
400
ID(OFF)+
200
Leakage Current (pA)
ID(ON)+
IS(OFF)+
0
-200
ID(OFF)-
-400
IS(OFF)-
-600
-800
-50
ID(ON)-
-25
0
25
50
75
100
Ambient Temperature (qC)
125
150
D005
Figure 28. Leakage Current vs Temperature
8.3.2 Ultralow Charge Injection
The TMUX6121 is implemented with simple transmission gate topology, as shown in Figure 29. Any mismatch in
the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch
is opened or closed.
OFF ON
CGSN
CGDN
S
D
CGSP
CGDP
OFF ON
Figure 29. Transmission Gate Topology
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Feature Description (continued)
The devices utilize special charge-injection cancellation circuitry that reduces the source (Sx)-to-drain (Dx)
charge injection to as low as 0.51 pC at VS = 0 V, as shown in Figure 30.
Charge Injection (pC)
2
1
VDD= 15V
VSS = -15V
VDD= 12V
VSS = 0V
0
VDD= 10V
VSS = -10V
-1
-2
-15
-10
-5
0
5
Source Voltage (V)
10
15
D007
Figure 30. Source-to-Drain Charge Injection vs Source or Drain Voltage
8.3.3 Bidirectional and Rail-to-Rail Operation
The TMUX6121, TMUX6122, and TMUX6123 conduct equally well from source (Sx) to drain (Dx) or from drain
(Dx) to source (Sx). Each channel of the switches has very similar characteristics in both directions. The input
signal to the devices swings from VSS to VDD without any significant degradation in performance. The on
resistance of these devices varies with input signal.
8.4 Device Functional Modes
Each channel of the TMUX6121, TMUX6122, and TMUX6123 is turned on or turned off based on the state of its
corresponding SELx pin. The SELx pins are weakly pulled-down through an internal 6 MΩ resistor, allowing the
switches to stay in a determined state when power is applies to the devices. The SELx pins can be connected to
VDD.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TMUX6121, TMUX6122, and TMUX6123 offer outstanding input/output leakage currents and ultralow charge
injection. These devices operate up to 33 (dual supply) or 16.5V (single supply), and offer true rail-to-rail input
and output. The on-capacitance of the TMUX6121, TMUX6122, and TMUX6123 is low. These features makes
the TMUX6121, TMUX6122, and TMUX6123 a family of precision, robust, high-performance analog multiplexer
for high-voltage, industrial applications.
9.2 Typical Application
One useful application to take advantage of TMUX6121, TMUX6122, and TMUX6123's precision performance is
the sample and hold circuit. A sample and hold circuit can be useful for an analog to digital converter (ADC) to
sample a varying input voltage with improved reliability and stability. It can also be used to store the output
samples from a single digital-to-analog converter (DAC) in a multi-output application. A simple sample and hold
circuit can be realized using an analog switch like one of the TMUX6121, TMUX6122, and TMUX6123 analog
switches.
+15V
-15V
VDD
VSS
CH
+
VIN1
+
SW1
+15V
CC
+15V
OPA2192
VOUT
RC
OPA2192
±
-15V
±
SW2
SEL1/
SEL2
-15V
CH
GND
TMUX612x
Figure 31. A Sample and Hold Circuit Realized Using the TMUX611x Analog Switch
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Typical Application (continued)
9.2.1 Design Requirements
The purpose of this precision design is to implement an optimized 2-output sample and hold circuit using a 4channel SPST switch. The sample and hold circuit needs to be capable of supporting high voltage output swing
up to ± 15V with minimized pedestal error and fast settling time. The overall system block diagram is illustrated in
Figure 31.
9.2.2 Detailed Design Procedure
The TMUX6121, TMUX6122, or TMUX6123 switch is used in conjunction with the voltage holding capacitors
(CH) to implement the sample and hold circuit. The basic operation is:
1. When the switch SW2 is closed, it samples the input voltage and charges the holding capacitors (CH) to the
input voltages values.
2. When the switch SW2 is open, the holding capacitors (CH) holds its previous value, maintaining stable
voltage at the amplifier output (VOUT)
Ideally, the switch delivers only the input signals to the holding capacitors. However, when the switch gets
toggled, some amount of charge also gets transferred to the switch output in the form of charge injection,
resulting slight sampling error. The TMUX6121, TMUX6122, and TMUX6123 switches have excellent charge
injection performance of only 0.51 pC, making them ideal choices for this implementation to minimize sampling
error. Due to switch and capacitor leakage current, the voltage on the hold capacitors droops with time. The
TMUX6121, TMUX6122, and TMUX6123 minimize the droops due to its ultra-low leakage performance. At 25°C,
the TMUX6111, TMUX6112, and TMUX6113 have extremely tiny leakage current at 0.5pA typical and 20pA
max. The TMUX6121, TMUX6122, and TMUX6123 devices also support high voltage capability. The devices
support up to ± 16.5 V dual supply operation, making it an ideal solution in this high voltage sample and hold
application.
A second switch SW1 is also included to operate in parallel with SW2 to reduce pedestal error during switch
toggling. Because both switches are driven at the same potential, they act as common-mode signal to the opamp, thereby minimizing the charge injection effects caused by the switch toggling action. Compensation network
consisting of RC and CC is also added to further reduce the pedestal error, whiling reducing the hold-time glitch
and improving the settling time of the circuit.
9.2.3 Application Curve
TMUX6121, TMUX6122, and TMUX6123 have excellent charge injection performance of only 0.51 pC (typical),
making them ideal choices to minimize sampling error for the sample and hold application. Figure 32 shows the
plot for the charge injection vs. source input voltage for TMUX6121, TMUX6122, and TMUX6123.
Charge Injection (pC)
2
1
VDD= 15V
VSS = -15V
VDD= 12V
VSS = 0V
0
VDD= 10V
VSS = -10V
-1
-2
-15
-10
-5
0
5
Source Voltage (V)
10
15
D007
Figure 32. Charge injection vs. Source Voltage for TMUX6121, TMUX6122 and TMUX6123
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10 Power Supply Recommendations
The TMUX6121, TMUX6122, and TMUX6123 operate across a wide supply range of ±5 V to ±16.5 V (10 V to
16.5 V in single-supply mode). They also perform well with asymmetrical supplies such as VDD = 12 V and VSS=
–5 V. For improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 µF to 10 µF at
both the VDD and VSS pins to ground. Always ensure the ground (GND) connection is established before supplies
are ramped. As a best practice, it is recommended to ramp VSS first before VDD in dual or asymmetrical supply
applications.
The on-resistance of the TMUX6121, TMUX6122, and TMUX6123 varies with supply voltage, as illustrated in
Figure 33
250
On Resistance (:)
200
VDD= 12V
VSS = -12V
VDD= 13.6V
VSS = -13.5V
150
100
VDD= 15V
VSS = -15V
50
0
-20
-15
VDD= 16.5V
VSS = -16.5V
-10
-5
0
5
10
Source or Drain Voltage (V)
15
20
D001
Figure 33. On-Resistance Variation With Supply and Input Voltage
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11 Layout
11.1 Layout Guidelines
Figure 34 illustrates an example of a PCB layout with the TMUX6121, TMUX6122, and TMUX6123.
Some key considerations are:
1. Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure
that the capacitor voltage rating is sufficient for the VDD and VSS supplies.
2. Keep the input lines as short as possible.
3. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
4. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
SEL1
SEL2
S1
VDD
D1
D2
S2
TMUX6121
TMUX6122
TMUX6123
C
Via to
ground plane
GND
NC
VSS
C
Figure 34. TMUX6121 Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
• OPAx192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias Current Op Amp with
e-trim™ (SBOS620E)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 4. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TMUX6121
Click here
Click here
Click here
Click here
Click here
TMUX6122
Click here
Click here
Click here
Click here
Click here
TMUX6123
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX6121 TMUX6122 TMUX6123
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMUX6121DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1Q16
TMUX6122DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1Q26
TMUX6123DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1Q36
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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