TMUX7211, TMUX7212, TMUX7213
ZHCSMW8C – OCTOBER 2020 – REVISED AUGUST 2021
TMUX721x 44 V 具有闩锁效应抑制和 1.8V 逻辑电平的低 RON、1:1 (SPST) 4 通
道精密开关
1 特性
3 说明
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TMUX7211、TMUX7212 和 TMUX7213 是互补金属氧
化物半导体 (CMOS) 开关，具有四个独立可选的 1:1
单极单掷 (SPST) 开关通道。该器件支持单电源（4.5V
至 44 V）、双电源（±4.5V 至 ±22 V）或非对称电源
（例如，VDD = 12V，VSS = –5V）。TMUX721x 可支
持源极 (Sx) 和漏极 (Dx) 引脚上 VSS 到 VDD 范围的双
向模拟和数字信号。
闩锁效应抑制
双电源电压范围：±4.5V 至 ±22 V
单电源电压范围：4.5V 至 44 V
低导通电阻：2Ω
高电流支持：330mA（最大值）(WQFN)
高电流支持：220mA（最大值）(TSSOP)
–40°C 至 +125°C 工作温度
逻辑引脚上的集成下拉电阻器
兼容 1.8V 逻辑电平
失效防护逻辑
轨至轨运行
双向运行
TMUX721x 的开关通过 SELx 引脚上适当的逻辑控制
输入控制。TMUX721x 是精密开关和多路复用器系列
器件，具有非常低的导通和关断泄漏电流，因此可用于
高精度测量应用。
TMUX721x 系列具有闩锁效应抑制，可防止器件内寄
生结构之间通常由过压事件引起的大电流不良事件。闩
锁状态通常会一直持续到电源轨关闭为止，并可能导致
器件故障。闩锁效应抑制使得 TMUX721x 系列开关和
多路复用器能够在恶劣的环境中使用。
2 应用
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采样保持电路
反馈增益开关
信号隔离
现场发送器
可编程逻辑控制器 (PLC)
工厂自动化和控制
超声波扫描仪
患者监护和诊断
心电图 (ECG)
数据采集系统 (DAQ)
半导体测试设备
LCD 测试
仪表：实验室、分析、便携
超声波智能仪表：水表和燃气表
光纤网络
光学测试设备
VDD
器件信息(1)
器件型号
TMUX7211
TMUX7212
TMUX7213
(1)
VSS
VDD
SW
D1
S1
D2
S2
D3
S3
D4
S4
SW
VSS
SW
D1
S1
D2
S2
D3
S3
VSS
D4
S4
D1
D2
SW
D3
SW
SW
SEL1
SEL1
SEL1
SEL2
SEL2
SEL2
SEL3
SEL3
SEL3
SEL4
SEL4
SEL4
TMUX7211
(SELx = Logic 1)
4.00mm × 4.00mm
SW
SW
S4
WQFN (16) (RUM)
SW
SW
S3
5.00mm × 4.40mm
VDD
SW
S2
TSSOP (16) (PW)
如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
SW
S1
封装尺寸（标称值）
封装
TMUX7212
(SELx = Logic 1)
D4
TMUX7213
(SELx = Logic 1)
TMUX721x 方框图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS416
TMUX7211, TMUX7212, TMUX7213
www.ti.com.cn
ZHCSMW8C – OCTOBER 2020 – REVISED AUGUST 2021
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................7
7.5 Source or Drain Continuous Current ..........................7
7.6 ±15 V Dual Supply: Electrical Characteristics ...........8
7.7 ±15 V Dual Supply: Switching Characteristics .......... 9
7.8 ±20 V Dual Supply: Electrical Characteristics ..........10
7.9 ±20 V Dual Supply: Switching Characteristics ......... 11
7.10 44 V Single Supply: Electrical Characteristics ...... 12
7.11 44 V Single Supply: Switching Characteristics ......13
7.12 12 V Single Supply: Electrical Characteristics ...... 14
7.13 12 V Single Supply: Switching Characteristics ..... 15
7.14 Typical Characteristics............................................ 16
8 Parameter Measurement Information.......................... 21
8.1 On-Resistance.......................................................... 21
8.2 Off-Leakage Current................................................. 21
8.3 On-Leakage Current................................................. 22
8.4 tON and tOFF Time......................................................22
8.5 tON (VDD) Time............................................................23
8.6 Propagation Delay.................................................... 23
8.7 Charge Injection........................................................24
8.8 Off Isolation...............................................................24
8.9 Channel-to-Channel Crosstalk..................................25
8.10 Bandwidth............................................................... 25
8.11 THD + Noise............................................................26
8.12 Power Supply Rejection Ratio (PSRR)................... 26
9 Detailed Description......................................................27
9.1 Overview................................................................... 27
9.2 Functional Block Diagram......................................... 27
9.3 Feature Description...................................................27
9.4 Device Functional Modes..........................................29
9.5 Truth Tables.............................................................. 29
10 Application and Implementation................................ 30
10.1 Application Information........................................... 30
10.2 Typical Application ................................................. 30
11 Power Supply Recommendations..............................32
12 Layout...........................................................................32
12.1 Layout Guidelines................................................... 32
12.2 Layout Example...................................................... 33
13 Device and Documentation Support..........................34
13.1 Documentation Support.......................................... 34
13.2 接收文档更新通知................................................... 34
13.3 支持资源..................................................................34
13.4 Trademarks............................................................. 34
13.5 Electrostatic Discharge Caution..............................34
13.6 术语表..................................................................... 34
14 Mechanical, Packaging, and Orderable
Information.................................................................... 34
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (April 2021) to Revision C (August 2021)
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为 TMUX7211、TMUX7212 和 TMUX7213 添加了 QFN 封装........................................................................... 1
Added ESD detail for RUM package.................................................................................................................. 5
Changed THD+N typical for 12V supply........................................................................................................... 15
Added the Integrated Pull-Down Resistor on Logic Pins section......................................................................27
Updated the Ultra-Low Charge Injection section.............................................................................................. 28
Updated the TMUX721x Layout Example figure in the Layout Example section............................................. 33
Changes from Revision A (March 2021) to Revision B (April 2021)
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• Included Break-before-make time delay for TMUX7213 ...................................................................................9
• Updated the Charge Injection Compensation figure.........................................................................................28
Changes from Revision * (December 2020) to Revision A (March 2021)
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向“特性”部分添加了对 WQFN 的高电流支持..................................................................................................1
Added thermal information for QFN package..................................................................................................... 7
Updated IDC specs for TSSOP package in Source or Drain Continuous Current table ..................................... 7
Added IDC specs for QFN package in Source or Drain Continuous Current table .............................................7
Updated VDD rise time value from 100ns to 1µs in TON(VDD) test condition........................................................ 9
Updated CL value from 1nF to 100pF in Charge Injection test condition............................................................9
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• Updated Figure 7-10 Leakage Current vs. Temperature ................................................................................. 16
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5 Device Comparison Table
PRODUCT
DESCRIPTION
TMUX7211
Low-Leakage-Current, Precision, 4-Channel, 1:1 (SPST) Switches (Logic Low)
TMUX7212
Low-Leakage-Current, Precision, 4-Channel, 1:1 (SPST) Switches (Logic High)
TMUX7213
Low-Leakage-Current, Precision, 4-Channel, 1:1 (SPST) Switches (Logic Low + Logic High)
6 Pin Configuration and Functions
图 6-1. PW Package
16-Pin TSSOP
Top View
图 6-2. RUM Package
16-Pin WQFN
Top View
表 6-1. Pin Functions
PIN
NAME
TYPE(1)
WQFN
D1
2
16
I/O
Drain pin 1. Can be an input or output.
D2
15
13
I/O
Drain pin 2. Can be an input or output.
D3
10
8
I/O
Drain pin 3. Can be an input or output.
D4
7
5
I/O
Drain pin 4. Can be an input or output.
GND
5
3
P
Ground (0 V) reference
N.C.
12
10
—
No internal connection. Can be shorted to GND or left floating.
S1
3
1
I/O
Source pin 1. Can be an input or output.
S2
14
12
I/O
Source pin 2. Can be an input or output.
S3
11
9
I/O
Source pin 3. Can be an input or output.
S4
6
4
I/O
Source pin 4. Can be an input or output.
SEL1
1
15
I
Logic control input 1, has internal 4 MΩ pull-down resistor. Controls channel 1 state as shown in 节 9.5.
SEL2
16
14
I
Logic control input 2, has internal 4 MΩ pull-down resistor. Controls channel 2 state as shown in 节 9.5.
SEL3
9
7
I
Logic control input 3, has internal 4 MΩ pull-down resistor. Controls channel 3 state as shown in 节 9.5.
SEL4
8
6
I
Logic control input 4, has internal 4 MΩ pull-down resistor. Controls channel 4 state as shown in 节 9.5.
VDD
13
11
P
Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VSS
4
2
P
Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this
pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 μF to
10 μF between VSS and GND.
Thermal Pad
(1)
(2)
4
DESCRIPTION(2)
TSSOP
—
The thermal pad is not connected internally. No requirement to solder this pad, if connected it is recommended
that the pad be left floating or tied to GND
I = input, O = output, I/O = input and output, P = power.
Refer to 节 9.4 for what to do with unused pins.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
48
V
–0.5
48
V
–48
0.5
V
–0.5
48
V
mA
VDD – VSS
Supply voltage
VDD
VSS
VSEL or VEN
Logic control input pin voltage (SELx)
ISEL or IEN
Logic control input pin current (SELx)
VS or VD
Source or drain voltage (Sx, Dx)
IIK
Diode clamp
UNIT
–30
30
VSS–0.5
VDD+0.5
–30
30
mA
%(4)
mA
current(3)
IS or ID (CONT)
Source or drain continuous current (Sx, Dx)
TA
Ambient temperature
–55
150
°C
Tstg
Storage temperature
–65
150
°C
TJ
Junction temperature
150
°C
1650
mW
700
mW
Total power dissipation
Ptot
(1)
(2)
(3)
(4)
(5)
IDC + 10
V
(QFN)(5)
Total power dissipation (TSSOP)(5)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltages are with respect to ground, unless otherwise specified.
Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.
Refer to Source or Drain Continuous Current table for IDC specifications.
For QFN package: Ptot derates linearly above TA = 70°C by 24.2mW/°C.
For TSSOP package: Ptot = 700 mW (max) and derates linearly above TA = 70°C by 10.7mW/°C.
7.2 ESD Ratings
VALUE
UNIT
TMUX721x in PW package
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±1500
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±1000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
V
TMUX721x in RUM package
V(ESD)
(1)
(2)
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
(1)
NOM
MAX
UNIT
Power supply voltage differential
4.5
44
V
VDD
Positive power supply voltage
4.5
44
V
VS or VD
Signal path input/output voltage (source or drain pin) (Sx, D)
VSS
VDD
V
VSEL or VEN
Address or enable pin voltage
0
44
V
(2)
mA
VDD – VSS
IS or ID (CONT) Source or drain continuous current (Sx, D)
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IDC
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over operating free-air temperature range (unless otherwise noted)
MIN
TA
(1)
(2)
6
Ambient temperature
–40
NOM
MAX
UNIT
125
°C
VDD and VSS can be any value as long as 4.5 V ≤ (VDD – VSS) ≤ 44 V, and the minimum VDD is met.
Refer to Source or Drain Continuous Current table for IDC specifications.
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7.4 Thermal Information
TMUX721x
THERMAL
METRIC(1)
PW (TSSOP)
RUM (WQFN)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
94.5
41.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
25.5
25.1
°C/W
RθJB
Junction-to-board thermal resistance
41.1
16.5
°C/W
ΨJT
Junction-to-top characterization parameter
1.1
0.3
°C/W
ΨJB
Junction-to-board characterization parameter
40.4
16.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
2.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Source or Drain Continuous Current
at supply voltage of VDD ± 10%, VSS ± 10 % (unless otherwise noted)
CONTINUOUS CURRENT PER CHANNEL (IDC) (2)
PACKAGE
PW (TSSOP)
RUM (WQFN)
(1)
(2)
TEST CONDITIONS
TA = 25°C
TA = 85°C
TA = 125°C
UNIT
+44 V Dual Supply(1)
220
160
100
mA
±15 V Dual Supply
220
160
100
mA
+12 V Single Supply
190
130
90
mA
±5 V Dual Supply
170
120
80
mA
+5 V Single Supply
130
90
60
mA
+44 V Single Supply(1)
330
220
120
mA
±15 V Dual Supply
330
220
120
mA
+12 V Single Supply
260
180
110
mA
±5 V Dual Supply
240
160
100
mA
+5 V Single Supply
180
120
80
mA
Specified for nominal supply voltage only.
Refer to Total power dissipation (Ptot) limits in Absolute Maximum Ratings table that must be followed with max continuous current
specification.
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7.6 ±15 V Dual Supply: Electrical Characteristics
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
2
2.7
Ω
3.4
Ω
4
Ω
ANALOG SWITCH
RON
VS = –10 V to +10 V
ID = –10 mA
Refer to On-Resistance
On-resistance
ΔRON
RON FLAT
V = –10 V to +10 V
On-resistance mismatch between S
ID = –10 mA
channels
Refer to On-Resistance
On-resistance flatness
VS = 0 V, IS = –10 mA
Refer to On-Resistance
RON DRIFT On-resistance drift
IS(OFF)
ID(OFF)
IS(ON)
ID(ON)
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage
VS = –10 V to +10 V
IS = –10 mA
Refer to On-Resistance
current(2)
25°C
–40°C to +85°C
–40°C to +125°C
25°C
0.18
Ω
–40°C to +85°C
0.1
0.19
Ω
–40°C to +125°C
0.21
Ω
25°C
0.46
Ω
–40°C to +85°C
0.2
0.65
Ω
–40°C to +125°C
0.7
Ω
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / + 10 V
Refer to Off-Leakage Current
25°C
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / + 10 V
Refer to Off-Leakage Current
25°C
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
Refer to On-Leakage Current
Ω/°C
0.008
–40°C to +125°C
–0.25
0.05
0.25
nA
nA
–40°C to +85°C
–3
3
–40°C to +125°C
–20
20
nA
0.25
nA
–0.25
0.05
–40°C to +85°C
–3
3
nA
–40°C to +125°C
–20
20
nA
25°C
–0.4
0.4
nA
–1
1
nA
–40°C to +125°C
–3
3
nA
–40°C to +85°C
0.1
LOGIC INPUTS (SEL / EN pins)
VIH
Logic voltage high
–40°C to +125°C
1.3
44
V
VIL
Logic voltage low
–40°C to +125°C
0
0.8
V
IIH
Input leakage current
–40°C to +125°C
0.4
1.2
µA
IIL
Input leakage current
–40°C to +125°C
–0.1 –0.005
µA
CIN
Logic input capacitance
–40°C to +125°C
3.5
pF
25°C
35
POWER SUPPLY
IDD
VDD supply current
VDD = 16.5 V, VSS = –16.5 V
Logic inputs = 0 V, 5 V, or VDD
56
µA
65
µA
80
µA
20
µA
–40°C to +85°C
24
µA
–40°C to +125°C
35
µA
–40°C to +85°C
–40°C to +125°C
25°C
ISS
(1)
(2)
8
VSS supply current
VDD = 16.5 V, VSS = –16.5 V
Logic inputs = 0 V, 5 V, or VDD
5
When VS is positive, VD is negative, or when VS is negative, VD is positive.
When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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7.7 ±15 V Dual Supply: Switching Characteristics
VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
tON
tOFF
TEST CONDITIONS
TA
25°C
Turn-on time from control input
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
25°C
Turn-off time from control input
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
MIN
tBBM
VS = 10 V,
RL = 300 Ω, CL = 35 pF
MAX
UNIT
100
175
ns
205
ns
225
ns
205
ns
225
ns
240
ns
–40°C to +85°C
–40°C to +125°C
80
–40°C to +85°C
–40°C to +125°C
25°C
Break-before-make time delay
(TMUX7213 Only)
TYP
27
ns
–40°C to +85°C
5
ns
–40°C to +125°C
5
ns
25°C
0.17
ms
–40°C to +85°C
0.18
ms
–40°C to +125°C
0.18
ms
RL = 50 Ω , CL = 5 pF
Refer to Propagation Delay
25°C
260
ps
Charge injection
VS = 0 V, CL = 100 pF
Refer to Charge Injection
25°C
60
pC
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Off Isolation
25°C
–70
dB
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1 MHz
Refer to Off Isolation
25°C
–50
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Crosstalk
25°C
–114
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1MHz
Refer to Crosstalk
25°C
–93
dB
BW
–3dB Bandwidth
RL = 50 Ω , CL = 5 pF
VS = 0 V
Refer to Bandwidth
25°C
56
IL
Insertion loss
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1 MHz
25°C
–0.15
dB
25°C
–68
dB
THD+N
VPP = 15 V, VBIAS = 0 V
R = 10 kΩ , CL = 5 pF,
Total Harmonic Distortion + Noise L
f = 20 Hz to 20 kHz
Refer to THD + Noise
25°C
0.0004
%
CS(OFF)
Source off capacitance
VS = 0 V, f = 1 MHz
25°C
28
pF
CD(OFF)
Drain off capacitance
VS = 0 V, f = 1 MHz
25°C
45
pF
CS(ON),
CD(ON)
On capacitance
VS = 0 V, f = 1 MHz
25°C
145
pF
Device turn on time
(VDD to output)
VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
tPD
Propagation delay
QINJ
tON (VDD)
VPP = 0.62 V on VDD and VSS
R = 50 Ω , CL = 5 pF,
ACPSRR AC Power Supply Rejection Ratio L
f = 1 MHz
Refer to ACPSRR
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ZHCSMW8C – OCTOBER 2020 – REVISED AUGUST 2021
7.8 ±20 V Dual Supply: Electrical Characteristics
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
1.7
2.5
Ω
ANALOG SWITCH
RON
VS = –15 V to +15 V
ID = –10 mA
Refer to On-Resistance
On-resistance
ΔRON
RON FLAT
V = –15 V to +15 V
On-resistance mismatch between S
ID = –10 mA
channels
Refer to On-Resistance
On-resistance flatness
VS = 0 V, IS = –10 mA
Refer to On-Resistance
RON DRIFT On-resistance drift
IS(OFF)
ID(OFF)
IS(ON)
ID(ON)
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage
VS = –15 V to +15 V
IS = –10 mA
Refer to On-Resistance
current(2)
25°C
–40°C to +85°C
–40°C to +125°C
25°C
0.1
3
Ω
3.6
Ω
0.18
Ω
–40°C to +85°C
0.19
Ω
–40°C to +125°C
0.21
Ω
25°C
0.6
Ω
–40°C to +85°C
0.3
0.8
Ω
–40°C to +125°C
0.95
Ω
VDD = 22 V, VSS = –22 V
Switch state is off
VS = +15 V / –15 V
VD = –15 V / + 15 V
Refer to Off-Leakage Current
25°C
VDD = 22 V, VSS = –22 V
Switch state is off
VS = +15 V / –15 V
VD = –15 V / + 15 V
Refer to Off-Leakage Current
25°C
VDD = 22 V, VSS = –22 V
Switch state is on
VS = VD = ±15 V
Refer to On-Leakage Current
25°C
Ω/°C
0.008
–40°C to +125°C
–1
0.05
1
nA
nA
–40°C to +85°C
–4.5
4.5
–40°C to +125°C
–33
33
nA
1
nA
–1
0.1
–40°C to +85°C
–4.5
4.5
nA
–40°C to +125°C
–33
33
nA
1
nA
–1.5
1.5
nA
–40°C to +125°C
–8
8
nA
–1
–40°C to +85°C
0.1
LOGIC INPUTS (SEL / EN pins)
VIH
Logic voltage high
–40°C to +125°C
1.3
44
V
VIL
Logic voltage low
–40°C to +125°C
0
0.8
V
IIH
Input leakage current
–40°C to +125°C
0.4
1.2
µA
IIL
Input leakage current
–40°C to +125°C
–0.1 –0.005
µA
CIN
Logic input capacitance
–40°C to +125°C
3.5
pF
25°C
33
POWER SUPPLY
IDD
VDD supply current
VDD = 22 V, VSS = –22 V
Logic inputs = 0 V, 5 V, or VDD
65
µA
74
µA
90
µA
26
µA
–40°C to +85°C
30
µA
–40°C to +125°C
45
µA
–40°C to +85°C
–40°C to +125°C
25°C
ISS
(1)
(2)
10
VSS supply current
VDD = 22 V, VSS = –22 V
Logic inputs = 0 V, 5 V, or VDD
7
When VS is positive, VD is negative, or when VS is negative, VD is positive.
When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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ZHCSMW8C – OCTOBER 2020 – REVISED AUGUST 2021
7.9 ±20 V Dual Supply: Switching Characteristics
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
tON
tOFF
TEST CONDITIONS
TA
25°C
Turn-on time from control input
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
25°C
Turn-off time from control input
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
MIN
tBBM
VS = 10 V,
RL = 300 Ω, CL = 35 pF
MAX
UNIT
100
185
ns
210
ns
230
ns
210
ns
225
ns
235
ns
–40°C to +85°C
–40°C to +125°C
90
–40°C to +85°C
–40°C to +125°C
25°C
Break-before-make time delay
(TMUX7213 Only)
TYP
28
ns
–40°C to +85°C
10
ns
–40°C to +125°C
10
ns
25°C
0.17
ms
–40°C to +85°C
0.18
ms
–40°C to +125°C
0.18
ms
RL = 50 Ω , CL = 5 pF
Refer to Propagation Delay
25°C
260
ps
Charge injection
VS = 0 V, CL = 100 pF
Refer to Charge Injection
25°C
92
pC
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Off Isolation
25°C
–70
dB
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1 MHz
Refer to Off Isolation
25°C
–50
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Crosstalk
25°C
–112
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1MHz
Refer to Crosstalk
25°C
–93
dB
BW
–3dB Bandwidth
RL = 50 Ω , CL = 5 pF
VS = 0 V
Refer to Bandwidth
25°C
48
IL
Insertion loss
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1 MHz
25°C
–0.14
dB
25°C
–68
dB
THD+N
VPP = 20 V, VBIAS = 0 V
R = 10 kΩ , CL = 5 pF,
Total Harmonic Distortion + Noise L
f = 20 Hz to 20 kHz
Refer to THD + Noise
25°C
0.0003
%
CS(OFF)
Source off capacitance
VS = 0 V, f = 1 MHz
25°C
28
pF
CD(OFF)
Drain off capacitance
VS = 0 V, f = 1 MHz
25°C
45
pF
CS(ON),
CD(ON)
On capacitance
VS = 0 V, f = 1 MHz
25°C
145
pF
Device turn on time
(VDD to output)
VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
tPD
Propagation delay
QINJ
tON (VDD)
VPP = 0.62 V on VDD and VSS
R = 50 Ω , CL = 5 pF,
ACPSRR AC Power Supply Rejection Ratio L
f = 1 MHz
Refer to ACPSRR
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ZHCSMW8C – OCTOBER 2020 – REVISED AUGUST 2021
7.10 44 V Single Supply: Electrical Characteristics
VDD = +44 V, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +44 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
2
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
RON FLAT
V = 0 V to 40 V
On-resistance mismatch between S
ID = –10 mA
channels
Refer to On-Resistance
On-resistance flatness
RON DRIFT On-resistance drift
IS(OFF)
ID(OFF)
IS(ON)
ID(ON)
VS = 0 V to 40 V
ID = –10 mA
Refer to On-Resistance
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
VS = 0 V to 40 V
ID = –10 mA
Refer to On-Resistance
VS = 22 V, IS = –10 mA
Refer to On-Resistance
25°C
2.4
Ω
–40°C to +85°C
3.2
Ω
–40°C to +125°C
3.8
Ω
0.18
Ω
0.19
Ω
0.21
Ω
0.8
Ω
–40°C to +85°C
1.1
Ω
–40°C to +125°C
1.2
Ω
25°C
0.1
–40°C to +85°C
–40°C to +125°C
25°C
0.65
Ω/°C
0.007
–40°C to +125°C
VDD = 44 V, VSS = 0 V
Switch state is off
VS = 40 V / 1 V
VD = 1 V / 40 V
Refer to Off-Leakage Current
25°C
–1
–40°C to +85°C
–40°C to +125°C
VDD = 44 V, VSS = 0 V
Switch state is off
VS = 40 V / 1 V
VD = 1 V / 40 V
Refer to Off-Leakage Current
25°C
–1
–40°C to +85°C
–7
–40°C to +125°C
–50
VDD = 44 V, VSS = 0 V
Switch state is on
VS = VD = 40 V or 1 V
Refer to On-Leakage Current
25°C
0.05
1
nA
–7
7
nA
–50
50
nA
1
nA
7
nA
50
nA
0.05
1
nA
–3.5
3.5
nA
–40°C to +125°C
–5
5
nA
–1
–40°C to +85°C
0.05
LOGIC INPUTS (SEL / EN pins)
VIH
Logic voltage high
–40°C to +125°C
1.3
44
V
VIL
Logic voltage low
–40°C to +125°C
0
0.8
V
IIH
Input leakage current
–40°C to +125°C
0.6
1.2
µA
IIL
Input leakage current
–40°C to +125°C
–0.1 –0.005
µA
CIN
Logic input capacitance
–40°C to +125°C
3.5
pF
25°C
44
POWER SUPPLY
IDD
(1)
(2)
12
VDD supply current
VDD = 44 V, VSS = 0 V
Logic inputs = 0 V, 5 V, or VDD
79
µA
–40°C to +85°C
88
µA
–40°C to +125°C
105
µA
When VS is positive, VD is negative, or when VS is negative, VD is positive.
When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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ZHCSMW8C – OCTOBER 2020 – REVISED AUGUST 2021
7.11 44 V Single Supply: Switching Characteristics
VDD = +44 V, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +44 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
tON
tOFF
TEST CONDITIONS
TA
TYP
MAX
UNIT
80
185
ns
205
ns
225
ns
205
ns
–40°C to +85°C
220
ns
–40°C to +125°C
228
ns
25°C
Turn-on time from control input
VS = 18 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
25°C
Turn-off time from control input
VS = 18 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
MIN
–40°C to +85°C
–40°C to +125°C
90
25°C
tBBM
Break-before-make time delay
(TMUX7213 Only)
VS = 18 V,
RL = 300 Ω, CL = 35 pF
27
ns
–40°C to +85°C
10
ns
–40°C to +125°C
10
ns
25°C
0.14
ms
–40°C to +85°C
0.15
ms
–40°C to +125°C
0.15
ms
RL = 50 Ω , CL = 5 pF
Refer to Propagation Delay
25°C
270
ps
Charge injection
VS = 22 V, CL = 100 pF
Refer to Charge Injection
25°C
104
pC
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Off Isolation
25°C
–70
dB
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1 MHz
Refer to Off Isolation
25°C
–50
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Crosstalk
25°C
–112
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1MHz
Refer to Crosstalk
25°C
–93
dB
BW
–3dB Bandwidth
RL = 50 Ω , CL = 5 pF
VS = 6 V
Refer to Bandwidth
25°C
46
IL
Insertion loss
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1 MHz
25°C
–0.15
dB
25°C
–66
dB
THD+N
VPP = 22 V, VBIAS = 22 V
R = 10 kΩ , CL = 5 pF,
Total Harmonic Distortion + Noise L
f = 20 Hz to 20 kHz
Refer to THD + Noise
25°C
0.0003
%
CS(OFF)
Source off capacitance
VS = 22 V, f = 1 MHz
25°C
28
pF
CD(OFF)
Drain off capacitance
VS = 22 V, f = 1 MHz
25°C
45
pF
CS(ON),
CD(ON)
On capacitance
VS = 22 V, f = 1 MHz
25°C
145
pF
Device turn on time
(VDD to output)
VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
tPD
Propagation delay
QINJ
tON (VDD)
VPP = 0.62 V on VDD and VSS
R = 50 Ω , CL = 5 pF,
ACPSRR AC Power Supply Rejection Ratio L
f = 1 MHz
Refer to ACPSRR
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ZHCSMW8C – OCTOBER 2020 – REVISED AUGUST 2021
7.12 12 V Single Supply: Electrical Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
2.8
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
RON FLAT
V = 0 V to 10 V
On-resistance mismatch between S
ID = –10 mA
channels
Refer to On-Resistance
On-resistance flatness
RON DRIFT On-resistance drift
IS(OFF)
ID(OFF)
IS(ON)
ID(ON)
VS = 0 V to 10 V
ID = –10 mA
Refer to On-Resistance
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
VS = 0 V to 10 V
IS = –10 mA
Refer to On-Resistance
VS = 6 V, IS = –10 mA
Refer to On-Resistance
25°C
5.4
Ω
–40°C to +85°C
6.8
Ω
–40°C to +125°C
7.4
Ω
0.21
Ω
0.23
Ω
0.25
Ω
1.7
Ω
1.9
Ω
2
Ω
25°C
0.13
–40°C to +85°C
–40°C to +125°C
25°C
1
–40°C to +85°C
–40°C to +125°C
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
VD = 1 V / 10 V
Refer to Off-Leakage Current
25°C
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
VD = 1 V / 10 V
Refer to Off-Leakage Current
25°C
VDD = 13.2 V, VSS = 0 V
Switch state is on
VS = VD = 10 V or 1 V
Refer to On-Leakage Current
Ω/°C
0.015
–40°C to +125°C
–0.25
0.01
0.25
nA
–40°C to +85°C
–2
2
nA
–40°C to +125°C
–16
16
nA
0.25
nA
–40°C to +85°C
–2
2
nA
–40°C to +125°C
–16
16
nA
25°C
–0.5
–0.25
0.05
0.5
nA
–40°C to +85°C
–1
0.05
1
nA
–40°C to +125°C
–3
3
nA
LOGIC INPUTS (SEL / EN pins)
VIH
Logic voltage high
–40°C to +125°C
1.3
44
V
VIL
Logic voltage low
–40°C to +125°C
0
0.8
V
IIH
Input leakage current
–40°C to +125°C
0.4
1.2
µA
IIL
Input leakage current
–40°C to +125°C
–0.1 –0.005
µA
CIN
Logic input capacitance
–40°C to +125°C
3.5
pF
25°C
30
POWER SUPPLY
IDD
(1)
(2)
14
VDD supply current
VDD = 13.2 V, VSS = 0 V
Logic inputs = 0 V, 5 V, or VDD
44
µA
–40°C to +85°C
52
µA
–40°C to +125°C
62
µA
When VS is positive, VD is negative, or when VS is negative, VD is positive.
When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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ZHCSMW8C – OCTOBER 2020 – REVISED AUGUST 2021
7.13 12 V Single Supply: Switching Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
tON
tOFF
TEST CONDITIONS
TA
TYP
MAX
UNIT
170
225
ns
276
ns
315
ns
248
ns
–40°C to +85°C
285
ns
–40°C to +125°C
310
ns
25°C
Turn-on time from control input
VS = 8 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
25°C
Turn-off time from control input
VS = 8 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
MIN
–40°C to +85°C
–40°C to +125°C
75
25°C
tBBM
Break-before-make time delay
(TMUX7213 Only)
VS = 8 V,
RL = 300 Ω, CL = 35 pF
30
ns
–40°C to +85°C
13
ns
–40°C to +125°C
13
ns
25°C
0.17
ms
–40°C to +85°C
0.18
ms
–40°C to +125°C
0.18
ms
RL = 50 Ω , CL = 5 pF
Refer to Propagation Delay
25°C
270
ps
Charge injection
VS = 6 V, CL = 100 pF
Refer to Charge Injection
25°C
12
pC
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Off Isolation
25°C
–70
dB
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1 MHz
Refer to Off Isolation
25°C
–50
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Crosstalk
25°C
–112
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1MHz
Refer to Crosstalk
25°C
–93
dB
BW
–3dB Bandwidth
RL = 50 Ω , CL = 5 pF
VS = 6 V
Refer to Bandwidth
25°C
125
MHz
IL
Insertion loss
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1 MHz
25°C
–0.25
dB
25°C
–70
dB
THD+N
VPP = 6 V, VBIAS = 6 V
RL = 10 kΩ , CL = 5 pF,
Total Harmonic Distortion + Noise
f = 20 Hz to 20 kHz
Refer to THD + Noise
25°C
0.001
%
CS(OFF)
Source off capacitance
VS = 6 V, f = 1 MHz
25°C
35
pF
CD(OFF)
Drain off capacitance
VS = 6 V, f = 1 MHz
25°C
50
pF
CS(ON),
CD(ON)
On capacitance
VS = 6 V, f = 1 MHz
25°C
145
pF
Device turn on time
(VDD to output)
VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
tPD
Propagation delay
QINJ
tON (VDD)
VPP = 0.62 V on VDD and VSS
R = 50 Ω , CL = 5 pF,
ACPSRR AC Power Supply Rejection Ratio L
f = 1 MHz
Refer to ACPSRR
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ZHCSMW8C – OCTOBER 2020 – REVISED AUGUST 2021
7.14 Typical Characteristics
at TA = 25°C (unless otherwise noted)
.
.
图 7-1. On-Resistance vs. Source or Drain Voltage - Dual Supply 图 7-2. On-Resistance vs. Source or Drain Voltage - Dual Supply
.
.
图 7-3. On-Resistance vs. Source or Drain Voltage - Single
Supply
VDD = 15 V, VSS = -15 V
图 7-5. On-Resistance vs Temperature
16
图 7-4. On-Resistance vs. Source or Drain Voltage - Single
Supply
VDD = 20 V, VSS = -20V
图 7-6. On-Resistance vs Temperature
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7.14 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
VDD = 12 V, VSS = 0 V
VDD = 36 V, VSS = 0 V
图 7-7. On-Resistance vs Temperature
图 7-8. On-Resistance vs Temperature
15
Leakage Current (nA)
10
5
ID(OFF) VS/VD= –10V/10V
ID(OFF) VS/VD = 10V/–10V
I(ON) Vs/Vd = –10V/–10V
I(ON) Vs/Vd = 10V/10V
IS(OFF) Vs/Vd = –10V/10V
IS(OFF) Vs/Vd = 10V/–10V
0
-5
-10
-15
-40
VDD = 20 V, VSS = -20V
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
VDD = 15 V, VSS = -15 V
图 7-9. Leakage Current vs Temperature
图 7-10. Leakage Current vs Temperature
30
25
Leakage Current (nA)
20
15
10
ID(OFF) Vs/Vd = 1V/30V
ID(OFF) Vs/Vd = 30V/1V
I(ON) Vs/Vd = 1V/1V
I(ON) Vs/Vd = 30V/30V
IS(OFF) Vs/Vd = 1V/30V
IS(OFF) Vs/Vd = 30V/1V
5
0
-5
-10
-15
-20
-25
-30
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
VDD = 36 V, VSS = 0 V
图 7-11. Leakage Current vs Temperature
VDD = 12 V, VSS = 0 V
图 7-12. Leakage Current vs Temperature
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7.14 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
.
.
图 7-13. Supply Current vs. Logic Voltage
.
.
图 7-15. Charge Injection vs. Drain Voltage - Dual Supply
.
图 7-16. Charge Injection vs. Source Voltage - Single Supply
VDD = 15 V, VSS = -15 V
图 7-17. Charge Injection vs. Drain Voltage - Single Supply
18
图 7-14. Charge Injection vs. Source Voltage - Dual Supply
图 7-18. TON and TOFF vs. Temperature
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7.14 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
VDD = 36 V, VSS = 0 V
图 7-19. TON and TOFF vs. Temperature
.
图 7-20. Off-Isolation vs Frequency
.
VDD = +15 V, VSS = -15 V
图 7-21. Off-Isolation vs Frequency
.
图 7-22. Crosstalk vs Frequency
.
图 7-23. THD+N vs. Frequency (Dual Supplies)
图 7-24. THD+N vs. Frequency (Single Supplies)
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7.14 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
VDD = +15 V, VSS = -15 V
图 7-25. On Response vs Frequency
VDD = +15 V, VSS = -15 V
图 7-27. Capacitance vs. Source Voltage or Drain Voltage
20
VDD = +15 V, VSS = -15 V
图 7-26. ACPSRR vs. Frequency
VDD = 12 V, VSS = 0 V
图 7-28. Capacitance vs. Source Voltage or Drain Voltage
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8 Parameter Measurement Information
8.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (Dx) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote onresistance. 图 8-1 shows the measurement setup used to measure RON. Voltage (V) and current (ISD) are
measured using this setup, and RON is computed with RON = V / ISD:
V
ISD
Sx
Dx
VS
RON
图 8-1. On-Resistance Measurement Setup
8.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current.
2. Drain off-leakage current.
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF).
图 8-2 shows the setup used to measure both off-leakage currents.
VDD
VSS
VDD
VSS
Is (OFF)
A
ID (OFF)
S1
D1
S1
D1
A
VD
VS
VD
VS
Is (OFF)
A
ID (OFF)
S4
D4
S4
D4
GND
A
GND
VS
VD
VS
IS(OFF)
VD
ID(OFF)
图 8-2. Off-Leakage Measurement Setup
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8.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON).
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON).
Either the source pin or drain pin is left floating during the measurement. 图 8-3 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON).
VDD
VSS
VDD
VSS
Is (ON)
A
ID (ON)
S1
D1
S1
D1
N.C.
N.C.
A
VD
VS
Is (ON)
A
ID (ON)
S4
D4
N.C.
D4
S4
N.C.
GND
A
GND
VS
VD
IS(ON)
ID(ON)
图 8-3. On-Leakage Measurement Setup
8.4 tON and tOFF Time
Turn-on time is defined as the time taken by the output of the device to rise to 90% after the enable has risen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. 图 8-4
shows the setup used to measure turn-on time, denoted by the symbol tON.
Turn-off time is defined as the time taken by the output of the device to fall to 10% after the enable has fallen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. 图 8-4
shows the setup used to measure turn-off time, denoted by the symbol tOFF.
VDD
0.1 µF
0.1 µF
3V
VEN
VSS
tr < 20 ns
50%
50%
VDD
tf < 20 ns
0V
VSS
Sx
tON
Dx
Output
tOFF
90%
RL
CL
Output
10%
VSELx
GND
CL
0V
图 8-4. Turn-On and Turn-Off Time Measurement Setup
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8.5 tON (VDD) Time
The tON (VDD) time is defined as the time taken by the output of the device to rise to 90% after the supply has
risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in
the system. 图 8-5 shows the setup used to measure turn on time, denoted by the symbol tON (VDD).
VSS
0.1 µF
VDD
Supply
Ramp
VDD
tr = 10 µs
VDD
4.5 V
VS
0V
VSS
S1
D1
S4
D4
Output
tON
VS
90%
Output
RL
CL
Output
CL
0V
3V
SELx
GND
图 8-5. tON (VDD) Time Measurement Setup
8.6 Propagation Delay
Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal
has risen or fallen past the 50% threshold. 图 8-6 shows the setup used to measure propagation delay, denoted
by the symbol tPD.
VDD
tr < 40ps
50%
50%
VDD
tf < 40ps
VS
0V
tPD 1
50%
50
VSS
S1
D1
S4
D4
Output
tPD 2
VS
Output
0.1 µF
0.1 µF
250 mV
Input
(VS)
VSS
50
Output
RL
CL
50%
RL
CL
0V
tProp Delay = max ( tPD 1, tPD 2)
GND
图 8-6. Propagation Delay Measurement Setup
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8.7 Charge Injection
The TMUX721x devices have a transmission-gate topology. Any mismatch in capacitance between the NMOS
and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the
gate signal. The amount of charge injected into the source or drain of the device is known as charge injection,
and is denoted by the symbol QC. 图 8-7 shows the setup used to measure charge injection from source (Sx) to
drain (Dx).
VDD
VSS
0.1 µF
0.1 µF
3V
VDD
tr < 20 ns
VSEL
tf < 20 ns
VSS
S1
D1
S4
D4
Output
0V
Output
QINJ = CL ×
VS
CL
SELx
VOUT
VOUT
Output
CL
VSEL
GND
图 8-7. Charge-Injection Measurement Setup
8.8 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the
source pin (Sx) of an off-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. 图 8-8 shows
the setup used to measure off isolation. Use off isolation equation to compute off isolation.
VDD
VSS
VDD
VSS
0.1 µF
Network Analyzer
0.1 µF
VS
S1
50Ÿ
VSIG
VOUT
D1
50Ÿ
Sx/Dx
50Ÿ
GND
1BB +OKH=PEKJ = 20 × .KC
8176
85
图 8-8. Off Isolation Measurement Setup
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8.9 Channel-to-Channel Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (Dx) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. 图 8-9
shows the setup used to measure, and the equation used to compute crosstalk.
VDD
VSS
0.1 µF
0.1 µF
VDD
Network Analyzer
VOUT
VSS
S1
D1
S2
D2
50Ÿ
50Ÿ
Vs
50Ÿ
50Ÿ
Sx/Dx
VSIG
GND
50Ÿ
%NKOOP=HG = 20 × .KC
8176
85
图 8-9. Channel-to-Channel Crosstalk Measurement Setup
8.10 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. The
characteristic impedance, Z0, for the measurement is 50 Ω. 图 8-10 shows the setup used to measure
bandwidth.
VDD
VSS
VDD
VSS
0.1 µF
Network Analyzer
0.1 µF
VS
Sx
VOUT
50Ÿ
VSIG
Dx
50Ÿ
GND
$=J@SE@PD = 20 × .KC
8176
85
图 8-10. Bandwidth Measurement Setup
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8.11 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the
mux output. The on-resistance of the device varies with the amplitude of the input signal and results in distortion
when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as
THD + N.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Audio Precision
SX
40 Ÿ
Dx
VOUT
VS
RL
GND
图 8-11. THD + N Measurement Setup
8.12 Power Supply Rejection Ratio (PSRR)
PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply voltage
pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine wave
of 100 mVPP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is the
AC PSRR.
VDD
Network Analyzer
VSS
DC Bias
Injector
With & Without
Capacitor
50 Ÿ
0.1 µF
0.1 µF
VSS
VDD
620 mVPP
S1
VBIAS
VIN
Other Sx/
Dx pins
50 Ÿ
50 Ÿ
VOUT
D1
GND
RL
CL
2544 = 20 × .KC
8176
8+0
图 8-12. AC PSRR Measurement Setup
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9 Detailed Description
9.1 Overview
The TMUX7211, TMUX7212, and TMUX7213 are 1:1 (SPST), 4-Channel switches. The devices have four
independently selectable single-pole, single-throw switches that are turned-on or turned-off based on the state of
the corresponding select pin.
9.2 Functional Block Diagram
VDD
VSS
VDD
SW
VSS
VDD
SW
S1
D1
S1
D2
S2
SW
SW
D1
S1
D2
S2
SW
D3
S3
D3
SW
D2
SW
SW
S3
D1
SW
SW
S2
VSS
S3
D3
SW
S4
D4
S4
SW
D4
S4
SEL1
SEL1
SEL1
SEL2
SEL2
SEL2
SEL3
SEL3
SEL3
SEL4
SEL4
SEL4
TMUX7211
(SELx = Logic 1)
TMUX7212
(SELx = Logic 1)
D4
TMUX7213
(SELx = Logic 1)
9.3 Feature Description
9.3.1 Bidirectional Operation
The TMUX721x conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each
channel has similar characteristics in both directions and supports both analog and digital signals.
9.3.2 Rail-to-Rail Operation
The valid signal path input and output voltage for TMUX721x ranges from VSS to VDD.
9.3.3 1.8 V Logic Compatible Inputs
The TMUX721x devices have 1.8-V logic compatible control for all logic control inputs. 1.8-V logic level inputs
allows the TMUX721x to interface with processors that have lower logic I/O rails and eliminates the need for an
external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations
refer to Simplifying Design with 1.8 V logic Muxes and Switches.
9.3.4 Integrated Pull-Down Resistor on Logic Pins
The TMUX721x has internal weak pull-down resistors to GND to ensure the logic pins are not left floating. The
value of this pull-down resistor is approximately 4 MΩ, but is clamped to about 1uA at higher voltages. This
feature integrates up to four external components and reduces system size and cost.
9.3.5 Fail-Safe Logic
The TMUX721x supports Fail-Safe Logic on the control input pins (SEL1, SEL2, SEL3, and SEL4) allowing for
operation up to 44 V, regardless of the state of the supply pin. This feature allows voltages on the control pins to
be applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system
complexity by removing the need for power supply sequencing on the logic control pins. For example, the FailSafe Logic feature allows the select pins of the TMUX721x to be ramped to 44 V while VDD and VSS = 0 V. The
logic control inputs are protected against positive faults of up to 44 V in powered-off condition, but do not offer
protection against negative overvoltage conditions.
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9.3.6 Latch-Up Immune
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the
low impedance path.
The TMUX721x family of devices are constructed on silicon on insulator (SOI) based process where an oxide
layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures
from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events
due to overvoltage or current injections. The latch-up immunity feature allows the TMUX721x family of switches
and multiplexers to be used in harsh environments. For more information on latch-up immunity refer to Using
Latch Up Immune Multiplexers to Help Improve System Reliability.
9.3.7 Ultra-Low Charge Injection
图 9-1 shows how the TMUX721x devices have a transmission gate topology. Any mismatch in the stray
capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is
opened or closed.
OFF ON
CGSN
CGDN
S
D
CGSP
CGDP
OFF ON
图 9-1. Transmission Gate Topology
The TMUX721x contains specialized architecture to reduce charge injection on the Drain (Dx). To further reduce
charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the Source (Sx). This
will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on the
Source (Sx) instead of the Drain (Dx). As a general rule, Cp should be 20x larger than the equivalent load
capacitance on the Drain (Dx). 图 9-2 shows charge injection variation with different compensation capacitors on
the Source side. This plot was captured on the TMUX7219 as part of the TMUX72xx family with a 100 pF load
capacitance.
图 9-2. Charge Injection Compensation
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9.4 Device Functional Modes
The TMUX721x devices have four independently selectable single-pole, single-throw switches that are turned-on
or turned-off based on the state of the corresponding select pin. The control pins can be as high as 44 V.
The TMUX721x devices can be operated without any external components except for the supply decoupling
capacitors. The SELx pins have internal pull-down resistors of 4 MΩ. If unused, SELx pin must be tied to GND
in order to ensure the device does not consume additional current as highlighted in Implications of Slow or
Floating CMOS Inputs. Unused signal path inputs (Sx or Dx) should be connected to GND.
9.5 Truth Tables
表 9-1, 表 9-2, and 表 9-3 show the truth tables for the TMUX7211, TMUX7212, and TMUX7213, respectively.
表 9-1. TMUX7211 Truth Table
SEL x (1)
CHANNEL x
0
Channel x ON
1
Channel x OFF
表 9-2. TMUX7212 Truth Table
SEL x (1)
CHANNEL x
0
Channel x OFF
1
Channel x ON
表 9-3. TMUX7213 Truth Table
(1)
(2)
SEL1
SEL2
SEL3
SEL4
ON / OFF CHANNELS(2)
0
X
X
X
CHANNEL 1 OFF
1
X
X
X
CHANNEL 1 ON
X
0
X
X
CHANNEL 2 ON
X
1
X
X
CHANNEL 2 OFF
X
X
0
X
CHANNEL 3 ON
X
X
1
X
CHANNEL 3 OFF
X
X
X
0
CHANNEL 4 OFF
X
X
X
1
CHANNEL 4 ON
x denotes 1, 2, 3, or 4 for the corresponding channel.
X = do not care.
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10 Application and Implementation
Note
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The TMUX721x is part of the precision switches and multiplexers family of devices. These devices operate with
dual supplies (±4.5 V to ±22 V), a single supply (4.5 V to 44 V), or asymmetric supplies (such as VDD = 12 V, VSS
= –5 V), and offer true rail-to-rail input and output. The TMUX721x offers low RON, low on and off leakage
currents and ultra-low charge injection performance. These features makes the TMUX721x a family of precision,
robust, high-performance analog multiplexer for high-voltage, industrial applications.
10.2 Typical Application
One example to take advantage of TMUX721x precision performance is the implementation of parametric
measurement unit (PMU) in the semiconductor automatic test equipment (ATE) application.
In Automated Test Equipment (ATE) systems, the Parametric Measurement Unit (PMU) is tasked to measure
device (DUT) parametric information in terms of voltage and current. When measuring voltage, current is applied
at the DUT pin, and current range adjustment can be done through changing the value of the internal sense
resistor. There is sometimes a need, depending on the DUT, to use even higher testing current than natively
supported by the system. A 4 channel SPST switch, together with external higher current amplifier and resistor,
can be used to achieve the flexibility. The PMU operating voltage is typically in mid voltage (up to 20 V). An
appropriate switch like the TMUX721x with low leakage current (0.05 nA typical) works well in these applications
to ensure measurement accuracy and low RON and flat RON_FLATNESS allows the current range to be controlled
more precisely. 图 10-1 shows simplified diagram of such implementations in memory and semiconductor test
equipment.
图 10-1. High Current Range Selection Using External Resistor
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10.2.1 Design Requirements
For this design example, use the parameters listed in 表 10-1.
表 10-1. Design Parameters
PARAMETERS
VALUES
Supply (VDD)
20 V
Supply (VSS)
–10 V
Input / Output signal range
–10 V to 20 V (Rail-to-Rail)
Control logic thresholds
1.8 V compatible
10.2.2 Detailed Design Procedure
Figure 10-1 demonstrates how the TMUX721x can be used in semiconductor test equipment for high-precision,
high-voltage, multi-channel measurement applications. The TMUX721x can support 1.8 V logic signals on the
control input, allowing the device to interface with low logic controls of an FPGA or MCU. The TMUX721x can be
operated without any external components except for the supply decoupling capacitors. The select pins have an
internal pull-down resistor to prevent floating input logic. All inputs to the switch must fall within the recommend
operating conditions of the TMUX721x including signal range and continuous current. For this design with a
positive supply of 20 V on VDD, and negative supply of -10 V on VSS, the signal range can be 20 V to -10 V. The
max continuous current (IDC) can be up to 330 mA as shown in the Recommended Operating Conditions table
for wide-range current measurement.
10.2.3 Application Curve
The TMUX721x have excellent charge injection performance and ultra-low leakage current, making them ideal
choices to minimize sampling error for the sample and hold application.
15
Leakage Current (nA)
10
5
ID(OFF) VS/VD= –10V/10V
ID(OFF) VS/VD = 10V/–10V
I(ON) Vs/Vd = –10V/–10V
I(ON) Vs/Vd = 10V/10V
IS(OFF) Vs/Vd = –10V/10V
IS(OFF) Vs/Vd = 10V/–10V
0
-5
-10
-15
-40
TA = 25°C
图 10-2. Charge Injection vs. Drain Voltage
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
VDD = 15 V, VDD = -15 V
图 10-3. On-Leakage vs. Source or Drain Voltage
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11 Power Supply Recommendations
The TMUX721x device operates across a wide supply range of ±4.5 V to ±22 V (4.5 V to 44 V in single-supply
mode). The device also perform well with asymmetrical supplies such as VDD = 12 V and VSS = –5 V.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply rails
to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the
VDD and VSS pins to ground. Place the bypass capacitors as close to the power supply pins of the device as
possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs)
that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply
decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use
of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple
vias in parallel lowers the overall inductance and is beneficial for connections to ground and power planes.
Always ensure the ground (GND) connection is established before supplies are ramped.
12 Layout
12.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. 图 12-1 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
BETTER
BEST
2W
WORST
1W min.
W
图 12-1. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance
changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via
introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference
from the other layers of the board. Be careful when designing test points, through-hole pins are not
recommended at high frequencies.
Some key considerations are:
• For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD/VSS and
GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to the pin as
possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
• Keep the input lines as short as possible.
• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
• Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground
planes.
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TMUX7211, TMUX7212, TMUX7213
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ZHCSMW8C – OCTOBER 2020 – REVISED AUGUST 2021
12.2 Layout Example
Wide (low inductance)
trace for power
D2
S1
S2
VSS
C
SEL2
D1
C
SEL1
Wide (low inductance)
trace for power
VDD
TMUX721x
C
C
GND
N.C.
S4
S3
D4
D3
SEL4
SEL3
D2
Wide (low inductance)
trace for power
D3
S3
SEL4
NC
S4
SEL3
VSS
GND
C
S2
VDD
C
SEL1
D1
Via to ground plane
S1
D4
C
C
Wide (low inductance)
trace for power
SEL2
Via to ground plane
图 12-2. TMUX721x Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
Texas Instruments, Using Latch Up Immune Multiplexers to Help Improve System Reliability application note
Texas Instruments, Improve Stability Issues with Low CON Multiplexers application brief
Texas Instruments, Improving Signal Measurement Accuracy in Automated Test Equipment application brief
Texas Instruments, Sample & Hold Glitch Reduction for Precision Outputs Reference Design reference guide
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches application brief
Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers application note
Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit
application note
• Texas Instruments, QFN/SON PCB Attachment application note
• Texas Instruments, Quad Flatpack No-Lead Logic Packages application note
•
•
•
•
•
•
•
13.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
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有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
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TI 提供的产品受 TI 的销售条款 (https:www.ti.com/legal/termsofsale.html) 或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器 (TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMUX7211PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
X211
TMUX7211RUMR
ACTIVE
WQFN
RUM
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TMUX
X211
TMUX7212PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
X212
TMUX7212RUMR
ACTIVE
WQFN
RUM
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TMUX
X212
TMUX7213PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
X213
TMUX7213RUMR
ACTIVE
WQFN
RUM
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TMUX
X213
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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