TMUX8108, TMUX8109
SCDS435B – SEPTEMBER 2021 – REVISED AUGUST 2023
TMUX810x 100-V, Flat RON, Single 8:1 and Dual 4:1 Multiplexers
with Latch-Up Immunity and 1.8-V Logic
1 Features
3 Description
•
The TMUX8108 and TMUX8109 are modern high
voltage capable analog multiplexers in 8:1 (single
ended) and 4:1 (differential) configurations. The
devices work well with dual supplies, a single supply,
or asymmetric supplies up to a maximum supply
voltage of 100 V. The TMUX810x devices provide
consistent analog parametric performance across the
entire supply voltage range. The TMUX8108 and
TMUX8109 support bidirectional analog and digital
signals on the source (Sx) and drain (Dx) pins.
•
•
•
•
•
•
•
•
•
•
•
•
•
High supply voltage capable:
– Dual supply: ±10 V to ±50 V
– Single supply: 10 V to 100 V
– Asymmetric dual supply operation
Consistent parametrics across supply voltages
Latch-up immune
Low crosstalk: –110 dB
Low input leakage: 40 pA
Low on resistance flatness: 0.5 Ω
Removes need for additional logic rail (VL)
1.8 V Logic capable
Fail-safe logic: up to 48 V independent of supply
Integrated pull-down resistor on logic pins
Bidirectional signal path
Break-before-make switching
Wide operating temperature TA: –40°C to 125°C
Industry-standard TSSOP and
smaller WQFN packages
All logic inputs support logic levels of 1.8 V, 3.3 V, 5V
and can be connected as high as 48 V, allowing for
system flexibility with control signal voltage. Fail-safe
logic circuitry allows voltages on the logic pins to be
applied before the supply pin, protecting the device
from potential damage.
The device family provides latch-up immunity,
preventing undesirable high current events between
parasitic structures within the device. A latch-up
condition typically continues until the power supply
rails are turned off and can lead to device failure.
The latch-up immunity feature allows this family of
multiplexers to be used in harsh environments.
2 Applications
•
•
•
•
•
•
•
•
•
•
High voltage bidirectional switching
Analog and digital multiplexing and demultiplexing
Semiconductor test equipment
LCD test equipment
Battery test equipment
Data acquisition systems (DAQ)
Digital multi-meter (DMM)
Factory automation and control
Programmable logic controllers (PLC)
Analog input modules
Package Information
PART
TMUX8108
TMUX8109
(1)
(2)
(3)
VDD
NUMBER(1)
VSS
PACKAGE SIZE(3)
PW (TSSOP, 16)
5 mm × 6.4 mm
RUM (WQFN, 16)
4 mm × 4 mm
See Device Comparison
For all available packages, see the orderable addendum at
the end of the data sheet.
The package size (length × width) is a nominal value and
includes pins, where applicable.
VDD
SW
PACKAGE(2)
VSS
SW
S1
S1A
...
SW
S2
S4A
...
D
DA
SW
SW
S1B
...
SW
DB
SW
S4B
S8
A0
A1
Log ic Decoder
EN
A0
Log ic Decoder
EN
A1
A2
TMUX8108
TMUX8109
TMUX8108 and TMUX8109 Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX8108, TMUX8109
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SCDS435B – SEPTEMBER 2021 – REVISED AUGUST 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings: TMUX810x Devices...... 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions:
TMUX810x Devices.......................................................6
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics (Global): TMUX810x
Devices..........................................................................7
7.6 Electrical Characteristics (±15-V Dual Supply)........... 7
7.7 Electrical Characteristics (±36-V Dual Supply)........... 8
7.8 Electrical Characteristics (±50-V Dual Supply)........... 9
7.9 Electrical Characteristics (72-V Single Supply).........10
7.10 Electrical Characteristics (100-V Single Supply).....11
7.11 Switching Characteristics: TMUX810x Devices...... 12
7.12 Typical Characteristics............................................ 13
8 Parameter Measurement Information.......................... 18
8.1 On-Resistance.......................................................... 18
8.2 Off-Leakage Current................................................. 18
8.3 On-Leakage Current................................................. 19
8.4 Break-Before-Make Delay.........................................19
8.5 Enable Turn-on and Turn-off Time............................ 20
8.6 Transition Time......................................................... 20
8.7 Charge Injection........................................................21
8.8 Off Isolation...............................................................21
8.9 Crosstalk................................................................... 22
8.10 Bandwidth............................................................... 23
8.11 THD + Noise............................................................23
9 Detailed Description......................................................24
9.1 Overview................................................................... 24
9.2 Functional Block Diagram......................................... 24
9.3 Feature Description...................................................24
9.4 Device Functional Modes..........................................26
10 Application and Implementation................................ 27
10.1 Application Information........................................... 27
10.2 Typical Application.................................................. 27
10.3 Power Supply Recommendations...........................29
10.4 Layout..................................................................... 29
11 Device and Documentation Support..........................31
11.1 Documentation Support.......................................... 31
11.2 Receiving Notification of Documentation Updates.. 31
11.3 Support Resources................................................. 31
11.4 Trademarks............................................................. 31
11.5 Electrostatic Discharge Caution.............................. 31
11.6 Glossary.................................................................. 31
12 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2021) to Revision B (August 2023)
Page
• Changed the status of the RUM package from: preview to: active ................................................................... 1
Changes from Revision * (September 2021) to Revision A (December 2021)
Page
• Changed the status of the data sheet from: Advanced Information to: Production Data .................................. 1
2
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SCDS435B – SEPTEMBER 2021 – REVISED AUGUST 2023
5 Device Comparison Table
PRODUCT
DESCRIPTION
TMUX8108
Single channel 8:1 multiplexer
TMUX8109
Dual channel 4:1 multiplexer
A2
VSS
3
14
GND
S1
4
13
VDD
VSS
1
S1
2
A2
15
13
2
A1
EN
14
A1
A0
16
15
1
EN
A0
16
6 Pin Configuration and Functions
12
GND
11
VDD
10
S5
9
S6
Thermal
S4
7
10
S7
D
8
9
S8
S2
3
S3
4
Pad
8
S6
S7
11
7
6
S8
S3
6
S5
D
12
5
5
S4
S2
Not to scale
Not to scale
Figure 6-1. PW Package, 16-Pin TSSOP (Top View)
Figure 6-2. RUM Package 16-Pin WQFN (Top View)
Table 6-1. Pin Functions: TMUX8108
PIN
NAME
TYPE(1)
DESCRIPTION
TSSOP
WQFN
A0
1
15
I
Logic control input address 0 (A0).
EN
2
16
I
Active high digital enable (EN) pin. The device is disabled and all switches become high impedance when
the pin is low. When the pin is high, the Ax logic inputs determine individual switch states.
VSS
3
1
P
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor
ranging from 0.1 µF to 10 µF between VSS and GND.
S1
4
2
I/O
Source pin 1. Can be an input or output.
S2
5
3
I/O
Source pin 2. Can be an input or output.
S3
6
4
I/O
Source pin 3. Can be an input or output.
S4
7
5
I/O
Source pin 4. Can be an input or output.
D
8
6
I/O
Drain pin. Can be an input or output.
S8
9
7
I/O
Source pin 8. Can be an input or output.
S7
10
8
I/O
Source pin 7. Can be an input or output.
S6
11
9
I/O
Source pin 6. Can be an input or output.
S5
12
10
I/O
Source pin 5. Can be an input or output.
VDD
13
11
P
Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect
a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
GND
14
12
P
Ground (0 V) reference
A2
15
13
I
Logic control input address 2 (A2).
A1
16
14
I
Logic control input address 1 (A1).
Thermal Pad
(1)
—
The thermal pad is not connected internally. It is recommended to tie the pad to GND or VSS for the best
performance.
I = input, O = output, I/O = input and output, P = power
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GND
VSS
3
14
VDD
S1A
4
13
S1B
S2A
5
12
S2B
S3A
6
11
S3B
S4A
7
10
S4B
DA
8
9
DB
VSS
1
S1A
2
GND
15
13
2
A1
EN
14
A1
A0
16
15
1
EN
A0
16
SCDS435B – SEPTEMBER 2021 – REVISED AUGUST 2023
12
VDD
11
S1B
10
S2B
9
S3B
Thermal
Not to scale
Figure 6-3. PW Package, 16-Pin TSSOP (Top View)
6
7
8
DB
S4B
4
DA
S3A
Pad
5
3
S4A
S2A
Not to scale
Figure 6-4. RUM Package, 16-Pin WQFN (Top View)
Table 6-2. Pin Functions: TMUX8109
PIN
NAME
DESCRIPTION
WQFN
A0
1
15
I
Logic control input address 0 (A0).
EN
2
16
I
Active high digital enable (EN) pin. The device is disabled and all switches become high impedance when
the pin is low. When the pin is high, the Ax logic inputs determine individual switch states.
VSS
3
1
P
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor
ranging from 0.1 µF to 10 µF between VSS and GND.
S1A
4
2
I/O
Source pin 1A. Can be an input or output.
S2A
5
3
I/O
Source pin 2A. Can be an input or output.
S3A
6
4
I/O
Source pin 3A. Can be an input or output.
S4A
7
5
I/O
Source pin 4A. Can be an input or output.
DA
8
6
I/O
Drain terminal A. Can be an input or output.
DB
9
7
I/O
Drain terminal B. Can be an input or output
S4B
10
8
I/O
Source pin 4B. Can be an input or output.
S3B
11
9
I/O
Source pin 3B. Can be an input or output.
S2B
12
10
I/O
Source pin 2B. Can be an input or output.
S1B
13
11
I/O
Source pin 1B. Can be an input or output.
VDD
14
12
P
Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect
a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
GND
15
13
P
Ground (0 V) reference
A1
16
14
I
Logic control input address 1 (A1).
Thermal Pad
(1)
4
TYPE(1)
TSSOP
—
The thermal pad is not connected internally. It is recommended to tie the pad to GND or VSS for the best
performance.
I = input, O = output, I/O = input and output, P = power
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SCDS435B – SEPTEMBER 2021 – REVISED AUGUST 2023
7 Specifications
7.1 Absolute Maximum Ratings: TMUX810x Devices
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
VDD–VSS
VDD
Supply voltage
VSS
VAx or VEN
Logic control input pin voltage (Ax, EN)
IAx or IEN
Logic control input pin current (Ax, EN)
VS or VD
Source or drain voltage (Sx, D)
IDC (CONT)
IIK (2)
UNIT
110
V
–0.5
110
V
–110
0.5
V
–0.5
50
V
mA
–30
30
VSS–2
VDD+2
Source or drain continuous current (Sx, D)
–100
100
mA
Diode clamp current at 85°C
–100
100
mA
V
Diode clamp current at 125°C
–15
15
mA
Tstg
Storage temperature
–65
150
°C
TA
Ambient temperature
–55
150
°C
TJ
Junction temperature
150
°C
Total power dissipation (TSSOP)
720
mW
Ptot
(1)
(2)
(3)
(3)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.
For TSSOP package: Ptot derates linearly above TA = 70°C by 10.5 mW/°C
7.2 ESD Ratings
VALUE
V(ESD) Electrostatic discharge
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins(1)
±2000
Charged device model (CDM), per ANSI/ESDA/JEDEC
JS-002, all pins(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions: TMUX810x Devices
over operating free-air temperature range (unless otherwise noted)
MIN
VDD – VSS (1) Power supply voltage differential
VDD
Positive power supply voltage
VS or VD (2)
Signal path input/output voltage (source or drain pin)
VA or VEN
Address or enable pin voltage
TA
Ambient temperature
VS or VD (2)
TA
IDC 1ch.(3)
Continuous current through switch for TSSOP or QFN on 1 channel
IDC All
(1)
(2)
(3)
(4)
ch.(4)
NOM
MAX
UNIT
100
V
10
100
V
VSS
VDD
V
10
0
48
V
–40
125
°C
Signal path input/output voltage (source or drain pin)
VSS
VDD
V
Ambient temperature
–40
125
°C
Continuous current through switch on all channels at the
same time, TSSOP package
100
mA
TA = 25°C
75
mA
TA = 85°C
50
mA
TA = 125°C
25
mA
VDD and VSS can be any value as long as 10 V ≤ (VDD – VSS) ≤ 100 V, and the minimum VDD is met.
VS or VD is the voltage on any Source or Drain pins.
Max continuous current shown for a single channel at a time.
Max continuous current shown for all channels at a time. Refer to the maximum power dissipation (Ptot) so that the package limitations
are not violated.
7.4 Thermal Information
THERMAL METRIC(1)
TMUX8109
TMUX8108
TMUX8109
PW (TSSOP)
PW (TSSOP)
RUM (QFN)
UNIT
16 PINS
16 PINS
16 PINS
RθJA
Junction-to-ambient thermal resistance
97.0
96.4
41.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
26.7
26.5
25.8
°C/W
RθJB
Junction-to-board thermal resistance
43.8
43.1
17.0
°C/W
ΨJT
Junction-to-top characterization parameter
1.1
1.1
0.3
°C/W
ΨJB
Junction-to-board characterization parameter
43.1
42.5
17.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
3.2
°C/W
(1)
6
TMUX8108
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics (Global): TMUX810x Devices
over operating free-air temperature range (unless otherwise noted)
typical at VDD = +36 V, VSS = –36 V, GND = 0 V and TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
LOGIC INPUTS
VIH
Logic voltage high
–40°C to +125°C
1.3
48
V
VIL
Logic voltage low
–40°C to +125°C
0
0.8
V
IIH
Input leakage current
Logic inputs = 0 V, 5 V, or 48 V
–40°C to +125°C
3.8
µA
IIL
Input leakage current
Logic inputs = 0 V, 5 V, or 48 V
–40°C to +125°C
CIN
Logic input capacitance
0.4
–0.2
–40°C to +125°C
–0.005
µA
3
pF
POWER SUPPLY
25°C
IDD
VDD supply current
Logic inputs = 0 V, 5 V, or 48 V
250
500
µA
–40°C to +85°C
500
µA
–40°C to +125°C
500
µA
25°C
ISS
VSS supply current
Logic inputs = 0 V, 5 V, or 48 V
420
µA
–40°C to +85°C
250
420
µA
–40°C to +125°C
420
µA
TYP
MAX
UNIT
38
55
7.6 Electrical Characteristics (±15-V Dual Supply)
VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
ANALOG SWITCH
25°C
RON
On-resistance
VS = –10 V to +10 V
ID = –5 mA
–40°C to +85°C
75
–40°C to +125°C
90
25°C
ΔRON
RON FLAT
On-resistance mismatch between VS = –10 V to +10 V
channels
ID = –5 mA
ID(OFF)
2.1
–40°C to +125°C
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / +10 V
25°C
Source off leakage current(1)
25°C
Drain off leakage current(1)
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / +10 V
IS(ON)
ID(ON)
Channel on leakage current(2)
ΔIS(ON)
ΔID(ON)
Leakage current mismatch
between channels(2)
(1)
(2)
–40°C to +125°C
VS = 0 V, IS = –5 mA
RON DRIFT On-resistance drift
IS(OFF)
1.5
25°C
On-resistance flatness
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
0.65
–40°C to +85°C
VS = –10 V to +10 V
ID = –5 mA
Ω
Ω
0.5
Ω
0.25
Ω/°C
0.01
–40°C to +85°C
–3
–40°C to +125°C
–15
3
nA
15
0.04
–40°C to +85°C
–8
–40°C to +125°C
–40
25°C
8
nA
40
0.04
–40°C to +85°C
–8
8
–40°C to +125°C
–40
40
25°C
5
85°C
50
125°C
900
nA
pA
When VS is positive,VD is negative. And when VS is negative, VD is positive.
When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.7 Electrical Characteristics (±36-V Dual Supply)
VDD = +36 V ± 10%, VSS = –36 V ± 10%, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
38
48
UNIT
ANALOG SWITCH
25°C
RON
On-resistance
VS = -25 V to +25 V
ID = –5 mA
–40°C to +85°C
65
–40°C to +125°C
80
25°C
On-resistance mismatch between VS = -25 V to +25 V
channels
ID = –5 mA
ΔRON
RON FLAT
On-resistance flatness
RON DRIFT On-resistance drift
IS(OFF)
ID(OFF)
Drain off leakage current(1)
IS(ON)
ID(ON)
Channel on leakage current(2)
ΔIS(ON)
ΔID(ON)
Leakage current mismatch
between channels(2)
(1)
(2)
8
Source off leakage current(1)
0.65
–40°C to +85°C
1.5
–40°C to +125°C
2.1
VS = -25 V to +25 V
ID = –5 mA
25°C
VS = 0 V, IS = –5 mA
–40°C to +125°C
VDD = 39.6 V, VSS = –39.6 V
Switch state is off
VS = +25 V / –25 V
VD = –25 V / +25 V
25°C
VDD = 39.6 V, VSS = –39.6 V
Switch state is off
VS = +25 V / –25 V
VD = –25 V / +25 V
25°C
VDD = 39.6 V, VSS = –39.6 V
Switch state is on
VS = VD = ±25 V
VDD = 39.6 V, VSS = –39.6 V
Switch state is on
VS = VD = ±25 V
Ω
Ω
0.9
Ω
0.25
Ω/°C
0.01
–40°C to +85°C
–3
3
–40°C to +125°C
–15
15
nA
0.06
–40°C to +85°C
–8
–40°C to +125°C
–40
25°C
8
nA
40
0.06
–40°C to +85°C
–8
8
–40°C to +125°C
–40
40
25°C
5
85°C
30
125°C
100
nA
pA
When VS is positive,VD is negative. And when VS is negative, VD is positive.
When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.8 Electrical Characteristics (±50-V Dual Supply)
VDD = +50 V, VSS = –50 V, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
38
48
UNIT
ANALOG SWITCH
25°C
RON
On-resistance
VS = –45 V to +45 V
ID = –5 mA
–40°C to +85°C
65
–40°C to +125°C
80
25°C
ΔRON
RON FLAT
On-resistance mismatch between VS = –45 V to +45 V
channels
ID = –5 mA
On-resistance flatness
RON DRIFT On-resistance drift
IS(OFF)
ID(OFF)
Source off leakage current(1)
Drain off leakage current(1)
IS(ON)
ID(ON)
Channel on leakage current(2)
ΔIS(ON)
ΔID(ON)
Leakage current mismatch
between channels(2)
(1)
(2)
1.5
–40°C to +125°C
2.1
25°C
VS = 0 V, IS = –5 mA
–40°C to +125°C
VDD = 50 V, VSS = –50 V
Switch state is off
VS = +45 V / –45 V
VD = –45 V / +45 V
25°C
VDD = 50 V, VSS = –50 V
Switch state is off
VS = +45 V / –45 V
VD = –45 V / +45 V
25°C
VDD = 50 V, VSS = –50 V
Switch state is on
VS = VD = ±45 V
VDD = 50 V, VSS = –50 V
Switch state is on
VS = VD = ±45 V
0.65
–40°C to +85°C
VS = –45 V to +45 V
ID = –5 mA
Ω
Ω
1
Ω
0.25
Ω/°C
0.02
–40°C to +85°C
–3
3
–40°C to +125°C
–15
15
nA
0.09
–40°C to +85°C
–8
–40°C to +125°C
–40
25°C
8
nA
40
0.09
–40°C to +85°C
–8
8
–40°C to +125°C
–40
40
25°C
10
85°C
40
125°C
170
nA
pA
When VS is positive,VD is negative. And when VS is negative, VD is positive.
When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.9 Electrical Characteristics (72-V Single Supply)
VDD = +72 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
38
48
UNIT
ANALOG SWITCH
25°C
RON
On-resistance
VS = 0 V to +60 V
ID = –5 mA
–40°C to +85°C
65
–40°C to +125°C
80
25°C
On-resistance mismatch between VS = 0 V to +60 V
channels
ID = –5 mA
ΔRON
RON FLAT
On-resistance flatness
RON DRIFT On-resistance drift
IS(OFF)
ID(OFF)
Source off leakage current(1)
Drain off leakage current(1)
0.65
–40°C to +85°C
1.5
–40°C to +125°C
2.1
VS = 0 V to +60 V
ID = –5 mA
25°C
VS = 0 V, IS = –5 mA
–40°C to +125°C
Switch state is off
VS = +60 V / 1 V
VD = 1 V / +60 V
Switch state is off
VS = +60 V / 1 V
VD = 1 V / +60 V
25°C
Channel on leakage current(2)
Switch state is on
VS = VD = 1 V / +60 V
–3
–40°C to +125°C
–15
25°C
(1)
(2)
10
Leakage current mismatch
between channels(2)
Switch state is on
VS = VD = 1 V / +60 V
0.6
Ω
0.25
Ω/°C
3
nA
15
0.06
–40°C to +85°C
–8
8
–40°C to +125°C
–40
40
nA
0.07
–40°C to +85°C
–8
–40°C to +125°C
–40
25°C
ΔIS(ON)
ΔID(ON)
Ω
0.02
–40°C to +85°C
25°C
IS(ON)
ID(ON)
Ω
8
nA
40
20
85°C
50
125°C
120
pA
When VS is 60 V, VD is 1 V. Or when VS is 1 V, VD is 60 V.
When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.
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7.10 Electrical Characteristics (100-V Single Supply)
VDD = +100 V, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
38
48
UNIT
ANALOG SWITCH
25°C
RON
On-resistance
VS = 0 V to +95 V
ID = –5 mA
–40°C to +85°C
65
–40°C to +125°C
80
25°C
ΔRON
RON FLAT
On-resistance mismatch between VS = 0 V to +95 V
channels
ID = –5 mA
On-resistance flatness
RON DRIFT On-resistance drift
IS(OFF)
ID(OFF)
Source off leakage current(1)
Drain off leakage current(1)
1.5
–40°C to +125°C
2.1
25°C
VS = 0 V, IS = –5 mA
–40°C to +125°C
Switch state is off
VS = +95 V / 1 V
VD = 1 V / +95 V
Switch state is off
VS = +95 V / 1 V
VD = 1 V / +95 V
0.65
–40°C to +85°C
VS = 0 V to +95 V
ID = –5 mA
25°C
ΔIS(ON)
ΔID(ON)
(1)
(2)
Channel on leakage current(2)
Leakage current mismatch
between channels(2)
Switch state is on
VS = VD = 1 V / +95 V
Switch state is on
VS = VD = 1 V / +95 V
Ω
0.6
Ω
0.25
Ω/°C
0.02
–40°C to +85°C
–3
–40°C to +125°C
–15
25°C
3
nA
15
0.09
–40°C to +85°C
–8
8
–40°C to +125°C
–40
40
25°C
IS(ON)
ID(ON)
Ω
nA
0.1
–40°C to +85°C
–8
–40°C to +125°C
–40
8
nA
40
25°C
50
85°C
120
125°C
350
pA
When VS is 95 V, VD is 1 V. Or when VS is 1 V, VD is 95 V.
When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.
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7.11 Switching Characteristics: TMUX810x Devices
over operating free-air temperature range (unless otherwise noted)
typical at VDD = +36 V, VSS = –36 V, GND = 0 V and TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
25°C
tTRAN
Transition time from control input
VS = 10 V
RL = 10 kΩ, CL = 15 pF
(EN)
Turn-on time from enable
VS = 10 V
RL = 10 kΩ, CL = 15 pF
–40°C to +85°C
10
–40°C to +125°C
12
(EN)
Turn-off time from enable
VS = 10 V
RL = 10 kΩ, CL = 15 pF
14
–40°C to +125°C
15
Break-before-make time delay
µs
µs
0.65
–40°C to +85°C
3
–40°C to +125°C
µs
3
25°C
tBBM
UNIT
3
–40°C to +85°C
25°C
tOFF
MAX
3
25°C
tON
TYP
3
VS = 10 V,
RL = 10 kΩ, CL = 15 pF
–40°C to +85°C
0.1
–40°C to +125°C
0.1
µs
TON (VDD)
Device turn on time
(VDD to output)
VDD ramp rate = 1 V/µs,
VS = 10 V,
RL = 10 kΩ, CL = 15 pF
25°C
75
µs
tPD
Propagation delay
RL = 50 Ω , CL = 5 pF
25°C
550
ps
QINJ
Charge injection
VS = (VDD + VSS) / 2, CL = 1 nF
25°C
–150
pC
OISO
Off isolation
RL = 50 Ω , CL = 5 pF
VS = (VDD + VSS) / 2, f = 1 MHz
25°C
–110
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = (VDD + VSS) / 2, f = 1MHz
25°C
–110
dB
BW
–3dB bandwidth (TMUX8108)
BW
–3dB bandwidth (TMUX8109)
RL = 50 Ω , CL = 5 pF
VS = (VDD + VSS) / 2
25°C
IL
Insertion loss
RL = 50 Ω , CL = 5 pF
VS = (VDD + VSS) / 2, f = 1 MHz
25°C
–2.8
dB
THD+N
Total harmonic distortion + Noise
Dual supply voltage
VPP = 5 V, VBIAS = (VDD + VSS) / 2
25°C
RL = 1 kΩ , CL = 5 pF,
f = 20 Hz to 20 kHz
0.003
%
CS(OFF)
Source off capacitance
VS = (VDD + VSS) / 2, f = 1 MHz
25°C
3
pF
CD(OFF)
Drain off capacitance
(TMUX8108)
VS = (VDD + VSS) / 2, f = 1 MHz
25°C
20
pF
CD(OFF)
Drain off
capacitance (TMUX8109)
VS = (VDD + VSS) / 2, f = 1 MHz
25°C
10
pF
CS(ON),
CD(ON)
On capacitance (TMUX8108)
VS = (VDD + VSS) / 2, f = 1 MHz
25°C
21
pF
CS(ON),
CD(ON)
On capacitance (TMUX8109)
VS = (VDD + VSS) / 2, f = 1 MHz
25°C
12
pF
12
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7.12 Typical Characteristics
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
VDD = 36 V, VSS = –36 V
Flatest Ron Region
VDD = 36 V, VSS = –36 V
Figure 7-2. On-Resistance vs Source or Drain Voltage
Figure 7-1. On-Resistance vs Source or Drain Voltage
VDD = 36 V, VSS = –36 V
Figure 7-3. On-Resistance vs Source or Drain Voltage
Dual Supply Voltages
Figure 7-4. On-Resistance vs Source or Drain Voltage
VDD = 15 V, VSS = –15 V
Figure 7-5. On-Resistance vs Source or Drain Voltage
VDD = 15 V, VSS = –15 V
Figure 7-6. On-Resistance vs Source or Drain Voltage
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7.12 Typical Characteristics (continued)
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
VDD = 72 V, VSS = 0 V
Figure 7-7. On-Resistance vs Source or Drain Voltage
VDD = 72 V, VSS = 0 V
Figure 7-8. On-Resistance vs Source or Drain Voltage
VDD = 100 V, VSS = 0 V
Figure 7-9. On-Resistance vs Source or Drain Voltage
VDD = 100 V, VSS = 0 V
Figure 7-10. On-Resistance vs Source or Drain Voltage
VDD = 36 V, VSS = –36 V
TMUX8108
Figure 7-11. Leakage Current vs Temperature
14
VDD = 36 V, VSS = –36 V
TMUX8109
Figure 7-12. Leakage Current vs Temperature
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7.12 Typical Characteristics (continued)
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
VDD = 36 V, VSS = –36 V
TMUX8108
Figure 7-13. Leakage Current vs Temperature
VDD = 36 V, VSS = –36 V
TMUX8109
Figure 7-14. Leakage Current vs Temperature
VDD = 72 V, VSS = 0 V
TMUX8108
Figure 7-15. Leakage Current vs Temperature
VDD = 72 V, VSS = 0 V
TMUX8109
Figure 7-16. Leakage Current vs Temperature
VDD = 100 V, VSS = 0 V
TMUX8108
Figure 7-17. Leakage Current vs Temperature
VDD = 100 V, VSS = 0 V
TMUX8109
Figure 7-18. Leakage Current vs Temperature
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7.12 Typical Characteristics (continued)
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
VDD = 36 V, VSS = –36 V
TMUX8109 and TMUX8109
Figure 7-19. IS(OFF) Leakage Current vs Source or Drain Voltage
VDD = 36 V, VSS = –36 V
TMUX8108
Figure 7-20. Leakage Current vs Source or Drain Voltage
VDD = 36 V, VSS = –36 V
TMUX8109
Figure 7-21. Leakage Current vs Source or Drain Voltage
VDD = 100 V, VSS = 0 V
TMUX8108 and TMUX8109
Figure 7-22. IS(OFF) Leakage Current vs Source or Drain Voltage
VDD = 100 V, VSS = 0 V
TMUX8108
Figure 7-23. Leakage Current vs Source or Drain Voltage
16
VDD = 100 V, VSS = 0 V
TMUX8109
Figure 7-24. Leakage Current vs Source or Drain Voltage
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7.12 Typical Characteristics (continued)
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
VDD = 36 V, VSS = –36 V
Figure 7-25. Charge Injection vs Source Voltage
.
Figure 7-26. Supply Current vs Temperature
VDD = 36 V, VSS = –36 V
Figure 7-27. Turn-On and Turn-Off Times vs Source Voltage
TA = 25°C
Figure 7-28. Off Isolation vs Frequency
TA = 25°C
Bandwidth
Figure 7-29. Crosstalk vs Frequency
Figure 7-30. Insertion Loss vs Frequency
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8 Parameter Measurement Information
8.1 On-Resistance
The on-resistance of the TMUX8108 and TMUX8109 is the ohmic resistance across the source (Sx) and drain
(Dx) pins of the device. The on-resistance varies with input voltage and supply voltage. Figure 8-1 shows how
the symbol RON is used to denote on-resistance. The measurement setup used to measure RON is also shown
in the following figure. ΔRON represents the difference between the RON of any two channels, while RON_FLAT
denotes the flatness that is defined as the difference between the maximum and minimum value of on-resistance
measured over the specified analog signal range.
V
VDD
VSS
410 =
VDD
Sx
VS
8
+5
VSS
IS
SW
Dx
GND
Figure 8-1. On-Resistance Measurement Setup
8.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current IS(OFF): the leakage current flowing into or out of the source pin when the switch
is off.
2. Drain off-leakage current ID(OFF): the leakage current flowing into or out of the drain pin when the switch is
off.
Figure 8-2 shows the setup used to measure both off-leakage currents.
VDD
Is (OFF)
S1
VSS
VDD
SW
VSS
SW
S1
A
S2
SW
SW
S2
ID (OFF)
VS
SW
D
...
...
...
S8
...
...
...
GND
D
VD
SW
S8
A
VD
GND
VS
GND
GND
GND
GND
IS(OFF)
ID(OFF)
Figure 8-2. Off-Leakage Measurement Setup
18
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8.3 On-Leakage Current
Source on-leakage current (IS(ON)) and drain on-leakage current (ID(ON)) denote the channel leakage currents
when the switch is in the on state. IS(ON) is measured with the drain floating, while ID(ON) is measured with the
source floating. Figure 8-3 shows the circuit used for measuring the on-leakage currents.
VDD
IS(ON)
VSS
VDD
SW
S1
VSS
SW
S1
N.C.
A
SW
S2
SW
S2
ID(ON)
N.C.
...
SW
S8
A
SW
S8
VS
D
...
...
D
...
...
GND
...
VS
VD
GND
VS
GND
GND
GND
GND
IS(ON)
ID(ON)
Figure 8-3. On-Leakage Measurement Setup
8.4 Break-Before-Make Delay
The break-before-make delay is a safety feature of the TMUX8108 and TMUX8109. The ON switches first break
the connection before the OFF switches make connection. The time delay between the break and the make
is known as break-before-make delay. Figure 8-4 shows the setup used to measure break-before-make delay,
denoted by the symbol tBBM.
VDD
VSS
VDD
VSS
0.1 µF
0.1 µF
GND
D
...
tf < 20 ns
...
tr < 20 ns
VA
SW
S2
3V
GND
SW
S1
S7
SW
RL
S8
SW
GND
0V
GND
VS
CL
GND
0.8 VS
Output
tBBM 2
tBBM 1
0V
A0
VS
A1
tBBM = min ( tBBM 1, tBBM 2)
EN
Decoder
A2
GND
VEN
VA
GND
GND
GND
Figure 8-4. Break-Before-Make Delay Measurement Setup
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8.5 Enable Turn-on and Turn-off Time
tON(EN) time is defined as the time taken by the output of the TMUX8108 and TMUX8109 to rise to a 90% final
value after the EN signal has risen to a 50% final value. tOFF(EN) is defined as the time taken by the output of
the TMUX8108 and TMUX8109 to fall to a 10% final value after the EN signal has fallen to a 50% initial value.
Figure 8-5 shows the setup used to measure the enable delay time.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
GND
SW
S2
3V
VS
50%
tf < 20 ns
GND
0V
D
...
50%
...
tr < 20 ns
VEN
GND
SW
S1
RL
SW
S8
0.9
Output
CL
GND
tOFF(EN)
tON(EN)
GND
GND
A0
0.1
EN
A1
Decoder
A2
VEN
GND
GND
GND
Figure 8-5. Enable Delay Measurement Setup
8.6 Transition Time
Transition time is defined as the time taken by the output of the device to rise (to 90% of the transition) or fall (to
10% of the transition) after the address signal (Ax) has fallen or risen to 50% of the transition. Figure 8-6 shows
the setup used to measure transition time, denoted by the symbol tTRAN.
VDD
VSS
VDD
VSS
0.1 µF
0.1 µF
GND
3V
50%
50%
tf < 20 ns
...
0.9
tTRAN 1
D
...
VS
0V
Output
SW
S2
tr < 20 ns
VA
GND
SW
S1
GND
RL
SW
S8
tTRAN 2
GND
0.1
CL
GND
GND
A0
tTRAN = max ( tTRAN 1, tTRAN 2)
EN
A1
Decoder
A2
VEN
VA
GND
GND
GND
Figure 8-6. Transition Time Measurement Setup
20
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8.7 Charge Injection
Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during
switching, and is denoted by the symbol QINJ. Figure 8-7 shows the setup used to measure charge injection from
the source to drain.
VDD
VSS
VDD
VSS
0.1 µF
0.1 µF
GND
SW
S2
...
3V
GND
VEN
tr < 20 ns
D
...
VS
Output
CL
SW
S8
tf < 20 ns
GND
SW
S1
GND
0V
GND
A0
Output
VS
QINJ = CL ×
VOUT
VOUT
EN
A1
Decoder
A2
VEN
GND
GND
GND
Figure 8-7. Charge-Injection Measurement Setup
8.8 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the
source pin (Sx) of an off-channel. The characteristic impedance for the measurement (ZO) is 50 Ω. Figure 8-8
shows the setup used to measure off isolation.
VDD
VSS
VDD
VSS
0.1 µF
Network Analyzer
0.1 µF
GND
SW
SX
GND
SW
N.C.
Other
Sx/ Dx
Pins
RS
SW
N.C.
VOUT
D/ DX
VS
Ax, EN
50Ÿ
VAX
VEN
1BB +OKH=PEKJ = 20 × .KC
GND
8176
85
Figure 8-8. Off Isolation Measurement Setup
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8.9 Crosstalk
There are two types of crosstalk that can be defined for the devices:
1. Intra-channel crosstalk (XTALK(INTRA)): the voltage at the source pin (Sx) of an off-switch input when a signal
is applied at the source pin of an on-switch input in the same channel, as shown in Figure 8-9 .
2. Inter-channel crosstalk (XTALK(INTER)): the voltage at the source pin (Sx) of an on-switch input when a
signal is applied at the source pin of an on-switch input in a different channel, as shown in Figure 8-10.
Inter-channel crosstalk applies only to the TMUX8109 device.
VDD
VSS
VDD
VSS
0.1 µF
Network Analyzer
0.1 µF
GND
S1/S1X
GND
SW
D/ DX
VOUT
S2/S2X
SW
RS
RL
Other
Sx/ Dx
SW
Pins
50Ÿ
VS
N.C.
Ax, EN
GND
VAX
VEN
+JPN= F ?D=JJAH %NKOOP=HG = 20 × .KC
8176
85
Figure 8-9. Intra-channel Crosstalk Measurement Setup
VDD
VSS
0.1 µF
Network Analyzer
0.1 µF
VDD
GND
SxA
VSS
GND
SW
DA
RS
VOUT
N.C.
Other
SW
SxA Pins
SxB
RL
SW
DB
50Ÿ
N.C.
Other
SxB Pins SW
RL
VS
Ax, EN
VAX
VEN
GND
+JPAN F ?D=JJAH %NKOOP=HG = 20 × .KC
8176
85
Figure 8-10. Inter-channel Crosstalk Measurement Setup
22
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8.10 Bandwidth
Bandwidth (BW) is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D or Dx) of the TMUX810x.
Figure 8-11 shows the setup used to measure bandwidth of the switch.
VDD
VSS
VDD
VSS
0.1 µF
Network Analyzer
0.1 µF
GND
GND
SW
SX
SW
N.C.
Other
Sx/ Dx
Pins
RS
SW
N.C.
VOUT
D/ DX
VS
Ax, EN
50Ÿ
VAX
VEN
GND
$=J@SE@PD = 20 × .KC
8176
85
Figure 8-11. Bandwidth Measurement Setup
8.11 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at
the multiplexer output. The on-resistance of the TMUX8108 and TMUX8109 varies with the amplitude of the
input signal and results in distortion when the drain pin is connected to a low-impedance load. Total harmonic
distortion plus noise is denoted as THD+N. Figure 8-12 shows the setup used to measure THD+N of the
devices.
VDD
VSS
VDD
VSS
0.1 µF
0.1 µF
GND
Audio Precision
SX
SW
GND
SW
N.C.
Other
Sx/ Dx
Pins
RS
SW
N.C.
VOUT
D/ DX
VS
RL
Ax, EN
VAX
VEN
GND
Figure 8-12. THD+N Measurement Setup
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9 Detailed Description
9.1 Overview
The TMUX8108 and TMUX8109 are modern complementary metal-oxide semiconductor (CMOS) analog
multiplexers in 8:1 (single ended) and 4:1 (differential) configurations. The devices work well with dual supplies,
a single supply, or asymmetric supplies up to 100 V.
9.2 Functional Block Diagram
VDD
VSS
VDD
SW
VSS
SW
S1
S1A
...
SW
S2
S4A
...
D
DA
SW
SW
S1B
...
SW
DB
SW
S4B
S8
A0
A1
Log ic Decoder
EN
A0
Log ic Decoder
EN
A1
A2
TMUX8108
TMUX8109
9.3 Feature Description
9.3.1 Bidirectional Operation
The TMUX8108 and TMUX8109 conduct equally well from source (Sx) to drain (D or Dx) or from drain (D or Dx)
to source (Sx). Each signal path has very similar characteristics in both directions.
9.3.2 Flat On – Resistance
The TMUX8108 and TMUX8109 are designed with a special switch architecture to produce ultra-flat onresistance (RON) across most of the switch input operating region. The flat RON response allows the device
to be used in precision sensor applications since the RON is controlled regardless of the signals sampled. The
architecture is implemented without a charge pump so no unwanted noise is produced from the device to affect
sampling accuracy.
The flatest on-resistance region extends from VSS to roughly 5 V below VDD. Once the signal is within 5 V of VDD
the on-resistance will exponentially increase and may impact desired signal transmission.
24
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9.3.3 Protection Features
The TMUX8108 and TMUX8109 offer a number of protection features to enable robust system implementations.
9.3.3.1 Fail-Safe Logic
Fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pins, protecting
the device from potential damage. Additionally the fail safe logic feature allows the logic inputs of the mux to be
interfaced with high voltages, allowing for simplified interfacing if only high voltage control signals are present.
The logic inputs are protected against positive faults of up to +48 V in powered-off condition, but do not offer
protection against negative overvoltage condition.
Fail-safe logic also allows the devices to interface with a voltage greater than VDD on the control pins during
normal operation to add maximum flexibility in system design. For example, with a VDD = 15 V, the logic control
pins could be connected to +24 V for a logic high signal which allows different types of signals, such as analog
feedback voltages, to be used when controlling the logic inputs. Regardless of the supply voltage, the logic
inputs can be interfaced as high as 48 V.
9.3.3.2 ESD Protection
All pins on the TMUX8108 and TMUX8109 support HBM ESD protection level up to ±2 kV, which helps protect
the devices from ESD events during the manufacturing process.
9.3.3.3 Latch-Up Immunity
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the
low impedance path.
In the TMUX8108 and TMUX8109 devices, an insulating oxide layer is placed on top of the silicon substrate
to prevent any parasitic junctions from forming. As a result, the devices are latch-up immune under all
circumstances by device construction.
The TMUX8108 and TMUX8109 devices are constructed on silicon on insulator (SOI) based process where
an oxide layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic
structures from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch
up events due to overvoltage or current injections. The latch-up immunity feature allows the TMUX8108 and
TMUX8109 to be used in harsh environments. For more information on latch-up immunity refer to Using Latch
Up Immune Multiplexers to Help Improve System Reliability.
9.3.4 1.8 V Logic Compatible Inputs
The TMUX8108 and TMUX8109 devices have 1.8 V logic compatible control for all logic control inputs. 1.8
V logic level inputs allows the TMUX8108 and TMUX8109 to interface with processors that have lower logic
I/O rails and eliminates the need for an external translator, which saves both space and bill of materials cost.
For more information on 1.8 V logic implementations, refer to Simplifying Design with 1.8 V logic Muxes and
Switches.
9.3.5 Integrated Pull-Down Resistor on Logic Pins
The TMUX8108 and TMUX8109 have internal weak pull-down resistors to GND so that the logic pins are not
left floating. The value of this pull-down resistor is approximately 4 MΩ, but is clamped to about 1 µA at higher
voltages. This feature integrates up to four external components and reduces system size and cost.
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9.4 Device Functional Modes
9.4.1 Normal Mode
In Normal Mode operation, signals of up to VDD and VSS can be passed through the switch from source (Sx) to
drain (D or Dx) or from drain (D or Dx) to source (Sx). Table 9-1 and Table 9-2 provides the address (Ax) pins
and the enable (EN) pin determines which switch path to turn on. The following conditions must be satisfied for
the switch to stay in the ON condition:
• The difference between the primary supplies (VDD – VSS) must be greater than or equal to 10 V. With a
minimum VDD of 10 V.
• The input signals on the source (Sx) or the drain (Dx) must be between VDD and VSS.
• The logic control address pins (Ax) must have selected the switch path.
9.4.2 Truth Tables
Table 9-1 provides the truth tables for the TMUX8108.
Table 9-1. TMUX8108 Truth Table
(1)
EN
A2
A1
A0
Normal Condition
0
X(1)
X(1)
X(1)
None
1
0
0
0
S1
1
0
0
1
S2
1
0
1
0
S3
1
0
1
1
S4
1
1
0
0
S5
1
1
0
1
S6
1
1
1
0
S7
1
1
1
1
S8
"X" means "do not care."
Table 9-2 provides the truth tables for the TMUX8109.
Table 9-2. TMUX8109 Truth Table
(1)
EN
A1
A0
Normal Condition
0
X(1)
X(1)
None
1
0
0
S1x
1
0
1
S2x
1
1
0
S3x
1
1
1
S4x
"X" means "do not care."
If unused, then address (Ax) pins must be tied to GND or Logic High in so that the device does not consume
additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx
or Dx) should be connected to GND for best performance.
26
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The TMUX8108 and TMUX8109 are high voltage multiplexers capable of supporting analog and digital signals.
The high voltage capability of these multiplexers allow them to be used in systems with high voltage signal
swings or in systems with high common mode voltages.
Additionally, the TMUX810x devices provide consistent analog parametric performance across the entire supply
voltage range allowing the devices to be powered by the most convenient supply rails in the system while still
providing excellent performance.
10.2 Typical Application
Many analog front end data acquisition systems are designed to support differential input signals with a wide
range of output voltages. In systems where the output sensor is separated from the rest of the signal chain
by long cables, a high common mode voltage shift can superimpose on the signal lines. One solution to this
problem is to use a high voltage multiplexer in combination with a high voltage op amp level translation stage to
properly scale the input signals to the correct input requirements of the ADC. The TMUX8109 allows the system
to be designed for a differential, four channel, multiplexed data acquisition system.
+50V
+
REF
Differential
Input Signals
Up to ±50V CM
RC Filter
OPA
RC Filter
+50V
OPA454
+
+
Gain Network
Gain Network
-50V
+50V
TMUX8109
+
+50V
+
OPA454
OPA454
Differential
Input Signals
Up to ±50V CM
+
Gain Network
-50V
High-Voltage Level Translation
Gain Network
-50V
-50V
High-Voltage Multiplexed Input
Reference Driver
REF
VINP
Charge
Kickback
Filter
TI ADC
VINM
VCM
ADC Stage
Figure 10-1. Typical Application
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10.2.1 Design Requirements
Table 10-1. Design Parameters
PARAMETER
VALUE
Positive supply (VDD) mux and Op Amps
+50 V
Negative supply (VSS) mux and Op Amps
-50 V
Maximum input / output signals with common mode shift
-50 V to 50 V
Mux control logic thresholds
1.8 V compatible, up to 48 V
Mux temperature range
-40°C to +125°C
10.2.2 Detailed Design Procedure
The multiplexed data acquisition circuit allows the system designer to have flexibility over both size and cost
of the end product. Utilizing a multiplexer can reduce board size and cost by reducing the number of op amp
circuits required for a multi-channel design. Additionally, the high voltage multiplexer can be paired with many
implementations of high voltage level translation circuits such as difference amplifiers, instrumentation amplifiers,
or fully differential amplifiers depending on the gain, noise requirements, and cost targets of the system.
In the example application, the TMUX8109 is paired with a difference amplifier and buffer stage op amps on both
the positive and negative differential signals. Many data acquisition systems will place a buffer op amp following
the mux for two reasons. The first reason is to eliminate the impact of the multiplexer on-resistance change
across the signal range, preventing gain errors in the system. Secondly, depending on the output impedance
of the sensors being interfaced, a high input impedance stage may be required to achieve system specification
targets. The TMUX810x multiplexers have exceptionally flat on-resistance and low leakage currents across the
signal voltage range and can potentially eliminate the need for buffer stage op amps depending on system
requirements. Additionally, excellent crosstalk and off-isolation performance, paired with low capacitance ratings
makes the TMUX810x multiplexers very flexible for system design of data acquisition systems.
A difference amplifier stage follows the multiplexer to eliminate the common mode voltage shift and can be used
to scale the input signals to match the dynamic range of the selected ADC. In this example, both the op amp and
multiplexer are rated for performance up to ±50 V. To find the maximum common mode voltage shift allowed, the
system designer should take the maximum supply voltage and subtract the maximum voltage of the differential
signal; the resulting voltage is the maximum common mode shift that can be accommodated without exceeding
the input voltage requirements of the multiplexer. The difference amplifier circuit relies on the matched resistor
for good CMRR performance and typically has lower voltage gains and lower input impedances. If higher gains
are required, or for better CMRR performance, an instrumentation amplifier can be swapped into the circuit. Both
op amp solutions can be utilized to remove the common mode voltage offset and extract the true differential
signal. The high voltage multiplexer at the front end of the design requires the system to have high voltage
power supply rails to pass signals within V SS and VDD, this should be considered in the overall architecture of the
system design. This multiplexed application becomes increasingly valuable with larger number of input channels
by greatly reducing the total component count.
28
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10.2.3 Application Curves
The example application utilizes the excellent leakage and crosstalk performance of the TMUX810x devices to
reduce any impact introduced from a multiplexed system architecture. Figure 10-2 shows the leakage current
for both ON and OFF cases with a varying temperature. Figure 10-3 shows the excellent crosstalk performance
of the TMUX810x devices. These features make the TMUX8108 and TMUX8109 an excellent solution for
multiplexed data acquisition applications that require excellent linearity and low distortion.
.
.
Figure 10-2. Leakage Current
Figure 10-3. Crosstalk
10.3 Power Supply Recommendations
The TMUX8108 and TMUX8109 operate across a wide supply range of ±10 V to ±50 V (10 V to 100 V in
single-supply mode). They also perform well with asymmetric supplies such as VDD = 50 V and VSS= –10 V.
For improved supply noise immunity, use a supply decoupling capacitor ranging from 1 µF to 10 µF at both the
VDD and VSS pins to ground. An additional 0.1 µF capacitor placed closest to the supply pins will provide the
best supply decoupling solution. Always ensure the ground (GND) connection is established before supplies are
ramped.
10.4 Layout
10.4.1 Layout Guidelines
The following images illustrate an example of a PCB layout with the TMUX8108 and TMUX8109. Some key
considerations are:
•
•
•
•
For reliable operation, connect at least one decoupling capacitor ranging from 0.1 µF to 10 µF between VDD
and VSS to GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to
the pin as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
Keep the input lines as short as possible.
Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
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10.4.2 Layout Example
Via to
ground plane
Wide (low inductance)
trace for power
Via to
ground plane
C
A0
C
A1
EN
A2
VSS
S1
C
C
GND
Via to
ground plane
Wide (low inductance)
trace for power
VDD
S2
S5
TMUX8108
S3
S6
S4
S7
D
S8
A2
A0
Wide (low inductance)
trace for power
S7
S6
S8
S5
S3
D
VDD
S2
S4
GND
S1
C
VSS
C
Wide (low inductance)
trace for power
A1
C
C
EN
Figure 10-4. TMUX8108 TSSOP Layout Example
Via to ground plane
Figure 10-5. TMUX8108 QFN Layout Example
Via to
ground plane
Via to
ground plane
Wide (low inductance)
trace for power
C
C
A0
A1
EN
GND
VSS
VDD
S1A
C
C
Wide (low inductance)
trace for power
S1B
TMUX8109
S2A
S2B
S3A
S3B
S4A
S4B
DA
DB
GND
A1
A0
C
Wide (low inductance)
trace for power
VDD
VSS
S3A
S3B
S4B
S2B
DB
S1B
S2A
DA
S1A
S4A
Wide (low inductance)
trace for power
C
C
C
EN
Figure 10-6. TMUX8109 TSSOP Layout Example
Via to ground plane
Figure 10-7. TMUX8109 QFN Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
•
•
•
Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
Texas Instruments, Multiplexers and Signal Switches Glossary application report
Texas Instruments, Using Latch-Up Immune Multiplexers to Help Improve System Reliability application
report
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Oct-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TMUX8108PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TM8108
Samples
TMUX8108RUMR
ACTIVE
WQFN
RUM
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TMUX
8108
Samples
TMUX8109PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TM8109
Samples
TMUX8109RUMR
ACTIVE
WQFN
RUM
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TMUX
8109
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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