TP3054-X, TP3057-X
www.ti.com
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
Extended Temperature Serial Interface CODEC/Filter COMBO Family
Check for Samples: TP3054-X, TP3057-X
FEATURES
1
•
•
2
•
•
•
•
•
•
•
•
•
•
•
−40°C to +85°C Operation
Complete CODEC and Filtering System
(COMBO) Including:
– Transmit High-Pass and Low-Pass Filtering
– Receive Low-Pass Filter with Sin x/x
Correction
– Active RC Noise Filters
– μ-Law or A-Law Compatible COder and
DECoder
– Internal Precision Voltage Reference
– Serial I/O Interface
– Internal Auto-Zero Circuitry
μ-Law, 16-Pin - TP3054
A-Law, 16-Pin - TP3057
Designed for D3/D4 and CCITT Spplications
±5V Operation
Low Operating Power - Typically 50 mW
Power-Down Standby Mode - Typically 3 mW
Automatic Power-Down
TTL or CMOS Compatible Digital Interfaces
Maximizes Line Interface Card Circuit Density
Dual-In-Line or PCC Surface Mount Packages
See also AN-370, “Techniques for Designing
with CODEC/Filter COMBO Circuits”
(SNLA136)
DESCRIPTION
The TP3054, TP3057 family consists of μ-law and Alaw monolithic PCM CODEC/filters utilizing the A/D
and D/A conversion architecture shown in Figure 3,
and a serial PCM interface. The devices are
fabricated using TI's advanced double-poly CMOS
process (microCMOS).
The encode portion of each device consists of an
input gain adjust amplifier, an active RC pre-filter
which eliminates very high frequency noise prior to
entering a switched-capacitor band-pass filter that
rejects signals below 200 Hz and above 3400 Hz.
Also included are auto-zero circuitry and a
companding coder which samples the filtered signal
and encodes it in the companded μ-law or A-law
PCM format. The decode portion of each device
consists of an expanding decoder, which reconstructs
the analog signal from the companded μ-law or A-law
code, a low-pass filter which corrects for the sin x/x
response of the decoder output and rejects signals
above 3400 Hz followed by a single-ended power
amplifier capable of driving low impedance loads. The
devices require two 1.536 MHz, 1.544 MHz or
2.048 MHz transmit and receive master clocks, which
may be asynchronous; transmit and receive bit
clocks, which may vary from 64 kHz to 2.048 MHz;
and transmit and receive frame sync pulses. The
timing of the frame sync pulses and PCM data is
compatible with both industry standard formats.
Connection Diagram
Figure 1. Plastic Chip Carriers (Top View)
Package Number FN0020A
Figure 2. Dual-In-Line Package (Top View)
Package Number NFG001E & DW0016B
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
TP3054-X, TP3057-X
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
www.ti.com
Block Diagram
Figure 3.
PIN DESCRIPTIONS
Symbol
VBB
Function
Negative power supply pin.
VBB = −5V ±5%.
GNDA
Analog ground. All signals are referenced to this pin.
VFRO
Analog output of the receive power amplifier.
VCC
Positive power supply pin.
VCC = +5V ±5%.
FSR
Receive frame sync pulse which enables BCLKR to shift PCM data into DR. FSR is an 8 kHz
pulse train. See Figure 4 and Figure 5 for timing details.
DR
Receive data input. PCM data is shifted into DR following the FSR leading edge.
BCLKR/CLKSEL
The bit clock which shifts data into DR after the FSR leading edge. May vary from 64 kHz to
2.048 MHz. Alternatively, may be a logic input which selects either 1.536 MHz/1.544 MHz or
2.048 MHz for master clock in synchronous mode and BCLKX is used for both transmit and
receive directions (see Table 1).
MCLKR/PDN
Receive master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with
MCLKX, but should be synchronous with MCLKX for best performance. When MCLKR is
connected continuously low, MCLKX is selected for all internal timing. When MCLKR is connected
continuously high, the device is powered down.
MCLKX
Transmit master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous
with MCLKR. Best performance is realized from synchronous operation.
FSX
Transmit frame sync pulse input which enables BCLKX to shift out the PCM data on DX. FSX is
an 8 kHz pulse train, see Figure 4 and Figure 5 for timing details.
BCLKX
The bit clock which shifts out the PCM data on DX. May vary from 64 kHz to 2.048 MHz, but must
be synchronous with MCLKX.
2
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: TP3054-X TP3057-X
TP3054-X, TP3057-X
www.ti.com
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
PIN DESCRIPTIONS (continued)
Symbol
Function
DX
The TRI-STATE PCM data output which is enabled by FSX.
TSX
Open drain output which pulses low during the encoder time slot.
GSX
Analog output of the transmit input amplifier. Used to externally set gain.
VFXI−
Inverting input of the transmit input amplifier.
+
VFXI
Non-inverting input of the transmit input amplifier.
Functional Description
POWER-UP
When power is first applied, power-on reset circuitry initializes the COMBO and places it into a power-down
state. All non-essential circuits are deactivated and the DX and VFRO outputs are put in high impedance states.
To power-up the device, a logical low level or clock must be applied to the MCLKR/PDN pin and FSX and/or FSR
pulses must be present. Thus, 2 power-down control modes are available. The first is to pull the MCLKR/PDN pin
high; the alternative is to hold both FSX and FSR inputs continuously low—the device will power-down
approximately 1 ms after the last FSX or FSR pulse. Power-up will occur on the first FSX or FSR pulse. The TRISTATE PCM data output, DX, will remain in the high impedance state until the second FSX pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive
directions. In this mode, a clock must be applied to MCLKX and the MCLKR/PDN pin can be used as a powerdown control. A low level on MCLKR/PDN powers up the device and a high level powers down the device. In
either case, MCLKX will be selected as the master clock for both the transmit and receive circuits. A bit clock
must also be applied to BCLKX and the BCLKR/CLKSEL can be used to select the proper internal divider for a
master clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically
compensates for the 193rd clock pulse each frame.
With a fixed level on the BCLKR/CLKSEL pin, BCLKX will be selected as the bit clock for both the transmit and
receive directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state
of BCLKR/CLKSEL. In this synchronous mode, the bit clock, BCLKX, may be from 64 kHz to 2.048 MHz, but must
be synchronous with MCLKX.
Each FSX pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the
enabled DX output on the positive edge of BCLKX. After 8 bit clock periods, the TRI-STATE DX output is returned
to a high impedance state. With an FSR pulse, PCM data is latched via the DR input on the negative edge of
BCLKX (or BCLKR if running). FSX and FSR must be synchronous with MCLKX/R.
Table 1. Selection of Master Clock Frequencies
Master Clock
BCLKR/CLKSEL
Frequency Selected
Clocked
TP3057
TP3054
2.048 MHz
1.536 MHz or 1.544 MHz
0
1.536 MHz or 1.544 MHz
2.048 MHz
1
2.048 MHz
1.536 MHz or 1.544 MHz
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: TP3054-X TP3057-X
Submit Documentation Feedback
3
TP3054-X, TP3057-X
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
www.ti.com
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and receive clocks may be applied. MCLKX and MCLKR must be
2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the TP3054, and need not be synchronous. For best
transmission performance, however, MCLKR should be synchronous with MCLKX, which is easily achieved by
applying only static logic levels to the MCLKR/PDN pin. This will automatically connect MCLKX to all internal
MCLKR functions (see Pin Description above). For 1.544 MHz operation, the device automatically compensates
for the 193rd clock pulse each frame. FSX starts each encoding cycle and must be synchronous with MCLKX and
BCLKX. FSR starts each decoding cycle and must be synchronous with BCLKR. BCLKR must be a clock, the logic
levels shown in Table 1 are not valid in asynchronous mode. BCLKX and BCLKR may operate from 64 kHz to
2.048 MHz.
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse or a long frame sync pulse. Upon power initialization, the
device assumes a short frame mode. In this mode, both frame sync pulses, FSX and FSR, must be one bit clock
period long, with timing relationships specified in Figure 4. With FSX high during a falling edge of BCLKX, the next
rising edge of BCLKX enables the DX TRI-STATE output buffer, which will output the sign bit. The following seven
rising edges clock out the remaining seven bits, and the next falling edge disables the DX output. With FSR high
during a falling edge of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign
bit. The following seven falling edges latch in the seven remaining bits. All four devices may utilize the short
frame sync pulse in synchronous or asynchronous operating mode.
LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync pulses, FSX and FSR, must be three or more bit clock periods
long, with timing relationships specified in Figure 5. Based on the transmit frame sync, FSX, the COMBO will
sense whether short or long frame sync pulses are being used. For 64 kHz operation, the frame sync pulse must
be kept low for a minimum of 160 ns. The DX TRI-STATE output buffer is enabled with the rising edge of FSX or
the rising edge of BCLKX, whichever comes later, and the first bit clocked out is the sign bit. The following seven
BCLKX rising edges clock out the remaining seven bits. The DX output is disabled by the falling BCLKX edge
following the eighth rising edge, or by FSX going low, whichever comes later. A rising edge on the receive frame
sync pulse, FSR, will cause the PCM data at DR to be latched in on the next eight falling edges of BCLKR (BCLKX
in synchronous mode). All four devices may utilize the long frame sync pulse in synchronous or asynchronous
mode.
In applications where the LSB bit is used for signalling, with FSR two bit clock periods long, the decoder will
interpret the lost LSB as “½” to minimize noise and distortion.
TRANSMIT SECTION
The transmit section input is an operational amplifier with provision for gain adjustment using two external
resistors, see Figure 8. The low noise and wide bandwidth allow gains in excess of 20 dB across the audio
passband to be realized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an
eighth order switched-capacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the
encoder sample-and-hold circuit. The A/D is of companding type according to μ-law (TP3054) or A-law (TP3057)
coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (tMAX)
of nominally 2.5V peak (see Transmission Characteristics). The FSX frame sync pulse controls the sampling of
the filter output, and then the successive-approximation encoding cycle begins. The 8-bit code is then loaded into
a buffer and shifted out through DX at the next FSX pulse. The total encoding delay will be approximately 165 μs
(due to the transmit filter) plus 125 μs (due to encoding delay), which totals 290 μs. Any offset voltage due to the
filters or comparator is cancelled by sign bit integration.
4
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: TP3054-X TP3057-X
TP3054-X, TP3057-X
www.ti.com
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
RECEIVE SECTION
The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz. The decoder is A-law (TP3057) or μ-law (TP3054) and the 5th order low pass filter corrects
for the sin x/x attenuation due to the 8 kHz sample/hold. The filter is then followed by a 2nd order RC active postfilter/power amplifier capable of driving a 600Ω load to a level of 7.2 dBm. The receive section is unity-gain. Upon
the occurrence of FSR, the data at the DR input is clocked in on the falling edge of the next eight BCLKR (BCLKX)
periods. At the end of the decoder time slot, the decoding cycle begins, and 10 μs later the decoder DAC output
is updated. The total decoder delay is ∼10 μs (decoder update) plus 110 μs (filter delay) plus 62.5 μs (½ frame),
which gives approximately 180 μs.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
VCC to GNDA
7V
VBB to GNDA
−7V
VCC+0.3V to VBB−0.3V
Voltage at any Analog Input or Output
Voltage at any Digital Input or Output
VCC+0.3V to GNDA−0.3V
−55°C to + 125°C
Operating Temperature Range
−65°C to +150°C
Storage Temperature Range
Lead Temperature
(1)
(2)
(Soldering, 10 sec.)
300°C
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Electrical Characteristics
Unless otherwise noted, limits printed in BOLD characters are ensured for VCC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40°C
to +85°C by correlation with 100% electrical testing at TA = 25°C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC =
+5.0V, VBB = −5.0V, TA = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.6
V
DIGITAL INTERFACE
VIL
Input Low Voltage
VIH
Input High Voltage
2.2
VOL
Output Low Voltage
V
DX, IL=3.2 mA
0.4
V
SIGR, IL=1.0 mA
0.4
V
0.4
V
TSX, IL=3.2 mA, Open Drain
VOH
Output High Voltage
DX, IH=−3.2 mA
2.4
SIGR, IH=−1.0 mA
2.4
V
V
IIL
Input Low Current
GNDA≤VIN≤VIL, All Digital Inputs
−10
10
μA
IIH
Input High Current
VIH≤VIN≤VCC
−10
10
μA
IOZ
Output Current in High Impedance State
(TRI-STATE)
DX, GNDA≤VO≤VCC
−10
10
μA
200
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)
IIXA
Input Leakage Current
−2.5V≤V≤+2.5V, VFXI+ or VFXI−
−200
RIXA
Input Resistance
−2.5V≤V≤+2.5V, VFXI+ or VFXI−
10
ROXA
Output Resistance
Closed Loop, Unity Gain
RLXA
Load Resistance
GSX
CLXA
Load Capacitance
GSX
VOXA
Output Dynamic Range
GSX, RL ≥ 10 kΩ
AVXA
3
10
+
Voltage Gain
1
VFXI to GSX
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: TP3054-X TP3057-X
−2.8
nA
MΩ
Ω
kΩ
50
pF
2.8
V
5000
Submit Documentation Feedback
V/V
5
TP3054-X, TP3057-X
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
www.ti.com
Electrical Characteristics (continued)
Unless otherwise noted, limits printed in BOLD characters are ensured for VCC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40°C
to +85°C by correlation with 100% electrical testing at TA = 25°C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC =
+5.0V, VBB = −5.0V, TA = 25°C.
Symbol
Parameter
Conditions
Min
Typ
1
2
Max
Units
FUXA
Unity Gain Bandwidth
VOSXA
Offset Voltage
MHz
VCMXA
Common-Mode Voltage
CMRRXA > 60 dB
CMRRXA
Common-Mode Rejection Ratio
DC Test
60
dB
PSRRXA
Power Supply Rejection Ratio
DC Test
60
dB
−20
20
mV
−2.5
2.5
V
ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)
RORF
Output Resistance
Pin VFRO
RLRF
Load Resistance
VFRO=±2.5V
CLRF
Load Capacitance
VOSRO
Output DC Offset Voltage
1
3
Ω
500
pF
200
mV
Ω
600
−200
POWER DISSIPATION (ALL DEVICES)
ICC0
Power-Down Current
No Load (1)
0.65
2.0
mA
IBB0
Power-Down Current
No Load (1)
0.01
0.33
mA
ICC1
Power-Up (Active) Current
No Load
5.0
11.0
mA
IBB1
Power-Up (Active) Current
No Load
5.0
11.0
mA
(1)
6
ICC0 and IBB0 are measured after first achieving a power-up state.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: TP3054-X TP3057-X
TP3054-X, TP3057-X
www.ti.com
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
Timing Specifications
Unless otherwise noted, limits printed in BOLD characters are ensured for VCC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40°C
to +85°C by correlation with 100% electrical testing at TA = 25°C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC =
+5.0V, VBB = –5.0V, TA = 25°C. All timing parameters are assured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing
Conventions section for test methods information.
Symbol
Parameter
1/tPM
Frequency of Master Clocks
Conditions
Min
Typ
Max
Units
Depends on the Device Used and the
1.536
MHz
BCLKR/CLKSEL Pin.
1.544
MHz
MCLKX and MCLKR
2.048
MHz
tRM
Rise Time of Master Clock
MCLKX and MCLKR
tFM
Fall Time of Master Clock
MCLKX and MCLKR
tPB
Period of Bit Clock
tRB
Rise Time of Bit Clock
BCLKX and BCLKR
tFB
Fall Time of Bit Clock
BCLKX and BCLKR
tWMH
Width of Master Clock High
MCLKX and MCLKR
160
ns
tWML
Width of Master Clock Low
MCLKX and MCLKR
160
ns
tSBFM
Set-Up Time from BCLKX High
to MCLKX Falling Edge
First Bit Clock after the Leading Edge of
FSX
Short Frame
100
ns
Long Frame
125
tSFFM
Setup Time from FSX High to
MCLKX Falling Edge
Long Frame Only
tWBH
Width of Bit Clock High
tWBL
Width of Bit Clock Low
tHBFL
Holding Time from Bit Clock
Low to Frame Sync
tHBFS
485
488
50
ns
50
ns
15725
ns
50
ns
50
ns
100
ns
VIH=2.2V
160
ns
VIL=0.6V
160
ns
Long Frame Only
0
ns
Holding Time from Bit Clock
High to Frame Sync
Short Frame Only
0
ns
tSFB
Set-Up Time from Frame Sync
to Bit Clock Low
Long Frame Only
115
ns
tDBD
Delay Time from BCLKX High
to Data Valid
Load=150 pF plus 2 LSTTL Loads
tDBTS
Delay Time to TSX Low
Load=150 pF plus 2 LSTTL Loads
tDZC
Delay Time from BCLKX Low to
Data Output Disabled
CL=0 pF to 150 pF
tDZF
Delay Time to Valid Data from
FSX or BCLKX, Whichever
Comes Later
CL=0 pF to 150 pF
tSDB
Set-Up Time from DR Valid to
BCLKR/X Low
tHBD
Hold Time from BCLKR/X Low to
DR Invalid
tSF
Set-Up Time from FSX/R to
BCLKX/R Low
tHF
tHBFl
tWFL
0
140
ns
140
ns
50
165
ns
20
165
ns
50
ns
50
ns
Short Frame Sync Pulse (1 Bit Clock Period Long)
50
ns
Hold Time from BCLKX/R Low
to FSX/R Low
Short Frame Sync Pulse (1 Bit Clock Period Long)
100
ns
Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
(FSX or FSR)
Long Frame Sync Pulse (from 3 to 8 Bit Clock Periods
Long)
100
ns
Minimum Width of the Frame
Sync Pulse (Low Level)
64k Bit/s Operating Mode
160
ns
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: TP3054-X TP3057-X
Submit Documentation Feedback
7
TP3054-X, TP3057-X
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
www.ti.com
Timing Diagrams
Figure 4. Short Frame Sync Timing
8
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: TP3054-X TP3057-X
TP3054-X, TP3057-X
www.ti.com
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
Figure 5. Long Frame Sync Timing
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: TP3054-X TP3057-X
9
TP3054-X, TP3057-X
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
www.ti.com
Transmission Characteristics
Unless otherwise noted, limits printed in BOLD characters are ensured for VCC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40°C
to +85°C by correlation with 100% electrical testing at TA = 25°C. All other limits are assured by correlation with other
production tests and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, VIN = 0 dBm0, transmit input amplifier
connected for unity gain non inverting. Typicals are specified at VCC = +5.0V, VBB = −5.0V, TA = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AMPLITUDE RESPONSE
Absolute Levels
(Definition of nominal gain)
Nominal 0 dBm0 Level is 4 dBm
(600Ω) 0 dBm0
tMAX
GXA
1.2276
Vrms
TP3054 (3.17 dBm0)
2.501
VPK
TP3057 (3.14 dBm0)
2.492
VPK
Max Overload Level
TA=25°C, VCC=5V, VBB=−5V
Input at GSx=0 dBm0 at 1020 Hz
Transmit Gain, Absolute
GXR
−0.15
0.15
dB
f=16 Hz
−40
dB
f=50 Hz
−30
dB
−26
dB
f=200 Hz
−1.8
−0.1
dB
f=300 Hz–3000 Hz
−0.15
0.15
dB
f=3152 Hz
−0.15
0.20
dB
f=3300 Hz
−0.35
0.1
dB
f=3400 Hz
−0.7
0
dB
f=4000 Hz
−14
dB
f=4600 Hz and Up, Measure
−32
dB
f=60 Hz
Transmit Gain, Relative to GXA
Response from 0 Hz to 4000 Hz
GXAT
Absolute Transmit Gain Variation with
Temperature
Relative to GXA
−0.15
0.15
dB
GXAV
Absolute Transmit Gain Variation with
Supply Voltage
Relative to GXA
−0.05
0.05
dB
VFXI+=−40 dBm0 to +3 dBm0
−0.2
0.2
dB
VFXI+=−50 dBm0 to −40 dBm0
−0.4
0.4
dB
−1.2
1.2
dB
−0.20
0.20
dB
f=0 Hz to 3000 Hz
−0.15
0.15
dB
f=3300 Hz
−0.35
0.1
dB
f=3400 Hz
−0.7
0
dB
−14
dB
GXRL
Sinusoidal Test Method
Reference Level=−10 dBm0
Transmit Gain Variations with Level
+
VFXI =−55 dBm0 to −50 dBm0
GRA
TA=25°C, VCC=5V, VBB=−5V
Receive Gain, Absolute
Input=Digital Code Sequence
for 0 dBm0 Signal at 1020 Hz
GRR
Receive Gain, Relative to GRA
f=4000 Hz
GRAT
Absolute Receive Gain Variation with
Temperature
Relative to GRA
−0.15
0.15
dB
GRAV
Absolute Receive Gain Variation with
Supply Voltage
Relative to GRA
−0.05
0.05
dB
PCM Level =−40 dBm0 to +3 dBm0
−0.2
0.2
dB
PCM Level =−50 dBm0 to −40 dBm0
−0.4
0.4
dB
PCM Level =−55 dBm0 to −50 dBm0
−1.2
1.2
dB
−2.5
2.5
V
GRRL
Sinusoidal Test Method; Reference
Input PCM Code Corresponds to an
Receive Gain Variations with Level
VRO
10
Receive Output Drive Level
Submit Documentation Feedback
Ideally Encoded
RL=600Ω
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: TP3054-X TP3057-X
TP3054-X, TP3057-X
www.ti.com
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
Transmission Characteristics (continued)
Unless otherwise noted, limits printed in BOLD characters are ensured for VCC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40°C
to +85°C by correlation with 100% electrical testing at TA = 25°C. All other limits are assured by correlation with other
production tests and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, VIN = 0 dBm0, transmit input amplifier
connected for unity gain non inverting. Typicals are specified at VCC = +5.0V, VBB = −5.0V, TA = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
f=1600 Hz
290
315
μs
f=500 Hz−600 Hz
195
220
μs
f=600 Hz−800 Hz
120
145
μs
f=800 Hz−1000 Hz
50
75
μs
f=1000 Hz−1600 Hz
20
40
μs
f=1600 Hz−2600 Hz
55
75
μs
f=2600 Hz−2800 Hz
80
105
μs
f=2800 Hz−3000 Hz
130
155
μs
f=1600 Hz
180
200
μs
ENVELOPE DELAY DISTORTION WITH FREQUENCY
DXA
Transmit Delay, Absolute
DXR
Transmit Delay, Relative to DXA
DRA
Receive Delay, Absolute
DRR
Receive Delay, Relative to DRA
f=500 Hz−1000 Hz
−40
−25
f=1000 Hz−1600 Hz
−30
−20
μs
μs
f=1600 Hz−2600 Hz
70
90
μs
f=2600 Hz−2800 Hz
100
125
μs
f=2800 Hz−3000 Hz
145
175
μs
NOISE
NXC
Transmit Noise, C Message Weighted
TP3054 (1)
12
16
dBrnC0
NXP
Transmit Noise, P Message Weighted
TP3057 (1)
−74
−67
dBm0p
NRC
Receive Noise, C Message Weighted
PCM Code is Alternating Positive and
Negative Zero - TP3054
8
11
dBrnC0
NRP
Receive Noise, P Message Weighted
TP3057 PCM Code Equals Positive Zero
−82
−79
dBm0p
Noise, Single Frequency
f=0 kHz to 100 kHz, Loop Around
Measurement, VFXI+=0 Vrms
−53
dBm0
NRS
PPSRX
NPSRX
Positive Power Supply Rejection,
Transmit
VCC=5.0 VDC+100 mVrms
Negative Power Supply Rejection,
Transmit
VBB=−5.0 VDC+ 100 mVrms
40
dBC
40
dBC
f=0 Hz−4000 Hz
38
dBC
f=4 kHz−25 kHz
38
dB
f=25 kHz−50 kHz
35
dB
f=0 Hz−4000 Hz
38
dBC
f=4 kHz−25 kHz
38
dB
f=25 kHz−50 kHz
35
dB
f=0 kHz−50 kHz (2)
f=0 kHz−50 kHz (2)
PPSRR
PCM Code Equals Positive Zero
VCC=5.0 VDC+100 mVrms
Measure VFR0
Positive Power Supply Rejection,
Receive
NPSRR
PCM Code Equals Positive Zero
VBB=−5.0 VDC+100 mVrms
Measure VFR0
Negative Power Supply Rejection,
Receive
(1)
(2)
Measured by extrapolation from the distortion test result at −50 dBm0.
PPSRX, NPSRX, and CTR–X are measured with a −50 dBm0 activation signal applied to VFXI+.
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: TP3054-X TP3057-X
Submit Documentation Feedback
11
TP3054-X, TP3057-X
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
www.ti.com
Transmission Characteristics (continued)
Unless otherwise noted, limits printed in BOLD characters are ensured for VCC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40°C
to +85°C by correlation with 100% electrical testing at TA = 25°C. All other limits are assured by correlation with other
production tests and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, VIN = 0 dBm0, transmit input amplifier
connected for unity gain non inverting. Typicals are specified at VCC = +5.0V, VBB = −5.0V, TA = 25°C.
Symbol
Parameter
Conditions
SOS
Min
Typ
Max
Units
−30
dB
4600 Hz–7600 Hz
−30
dB
7600 Hz–8400 Hz
−40
dB
8400 Hz–100,000 Hz
−30
dB
Loop Around Measurement, 0 dBm0,
300 Hz to 3400 Hz Input PCM Code
Applied at DR.
Spurious Out-of-Band Signals at the
Channel Output
DISTORTION
Sinusoidal Test Method (3)
STDX,
STDR
Signal to Total Distortion Transmit or
Receive Half-Channel
Level=3.0 dBm0
33
dBC
=0 dBm0 to −30 dBm0
36
dBC
XMT
28
dBC
RCV
29
dBC
XMT
13
dBC
RCV
14
=−40 dBm0
=−55 dBm0
dBC
SFDX
Single Frequency Distortion, Transmit
−43
dB
SFDR
Single Frequency Distortion, Receive
−43
dB
−41
dB
IMD
Loop Around Measurement,
Intermodulation Distortion
VFXI+=−4 dBm0 to −21 dBm0, Two
Frequencies in the Range
300 Hz−3400 Hz
CROSSTALK
CTX-R
Transmit to Receive Crosstalk, 0 dBm0 f=300 Hz−3400 Hz
Transmit Level
DR=Quiet PCM Code (4)
−90
−70
dB
CTR-X
Receive to Transmit Crosstalk, 0 dBm0
f=300 Hz−3400 Hz, VFXI=Multitone (5)
Receive Level
−90
−70
dB
(3)
(4)
(5)
12
TP3054/57 are measured using C message weighted filter for μ-law and psophometric weighted filter for A-law.
CTX–R @ 1.544 MHz MCLKX freq. is −70 dB max. 50% ±5% BCLKX duty cycle.
PPSRX, NPSRX, and CTR–X are measured with a −50 dBm0 activation signal applied to VFXI+.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: TP3054-X TP3057-X
TP3054-X, TP3057-X
www.ti.com
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
Encoding Format at DX Output
TP3054 μ-Law
VIN (at GSX)=+Full-Scale
VIN (at GSX)=0V
VIN (at GSX)=−Full-Scale
TP3057 A-Law (Includes Even Bit Inversion)
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
APPLICATIONS INFORMATION
POWER SUPPLIES
While the pins of the TP3050 family are well protected against electrical misuse, it is recommended that the
standard CMOS practice be followed, ensuring that ground is connected to the device before any other
connections are made. In applications where the printed circuit board may be plugged into a “hot” socket with
power and clocks already present, an extra long ground pin in the connector should be used.
All ground connections to each device should meet at a common point as close as possible to the GNDA pin.
This minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1 μF
supply decoupling capacitors should be connected from this common ground point to VCC and VBB, as close to
device pins as possible.
For best performance, the ground point of each CODEC/FILTER on a card should be connected to a common
card ground in star formation, rather than via a ground bus.
This common ground point should be decoupled to VCC and VBB with 10 μF capacitors.
RECEIVE GAIN ADJUSTMENT
For applications where a TP3050 family CODEC/filter receive output must drive a 600Ω load, but a peak swing
lower than ±2.5V is required, the receive gain can be easily adjusted by inserting a matched T-pad or π-pad at
the output. Table 2 lists the required resistor values for 600Ω terminations. As these are generally non-standard
values, the equations can be used to compute the attenuation of the closest practical set of resistors. It may be
necessary to use unequal values for the R1 or R4 arms of the attenuators to achieve a precise attenuation.
Generally it is tolerable to allow a small deviation of the input impedance from nominal while still maintaining a
good return loss. For example a 30 dB return loss against 600Ω is obtained if the output impedance of the
attenuator is in the range 282Ω to 319Ω (assuming a perfect transformer).
Figure 6. T-Pad Attenuator
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: TP3054-X TP3057-X
Submit Documentation Feedback
13
TP3054-X, TP3057-X
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
www.ti.com
Note: See Application Note 370 for further details.
Figure 7. π-Pad Attenuator
Table 2. Attentuator Tables for Z1=Z2=300Ω (All Values in Ω)
14
dB
R1
R2
R3
R4
0.1
1.7
26k
3.5
52k
0.2
3.5
13k
6.9
26k
0.3
5.2
8.7k
10.4
17.4k
0.4
6.9
6.5k
13.8
13k
0.5
8.5
5.2k
17.3
10.5k
0.6
10.4
4.4k
21.3
8.7k
0.7
12.1
3.7k
24.2
7.5k
0.8
13.8
3.3k
27.7
6.5k
0.9
15.5
2.9k
31.1
5.8k
1.0
17.3
2.6l
34.6
5.2k
2
34.4
1.3k
70
2.6k
3
51.3
850
107
1.8k
4
68
650
144
1.3k
5
84
494
183
1.1k
6
100
402
224
900
7
115
380
269
785
8
379
284
317
698
9
143
244
370
630
10
156
211
427
527
11
168
184
490
535
12
180
161
550
500
13
190
142
635
473
14
200
125
720
450
15
210
110
816
430
16
218
98
924
413
18
233
77
1.17k
386
20
246
61
1.5k
366
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: TP3054-X TP3057-X
TP3054-X, TP3057-X
www.ti.com
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
Typical Synchronous Application
Figure 8.
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: TP3054-X TP3057-X
Submit Documentation Feedback
15
TP3054-X, TP3057-X
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
•
16
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: TP3054-X TP3057-X
PACKAGE OPTION ADDENDUM
www.ti.com
6-Nov-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
TP3054WM-X/63
NRND
Package Type Package Pins Package
Drawing
Qty
SOIC
DW
16
1000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TBD
Call TI
Call TI
Op Temp (°C)
Device Marking
(4/5)
TP3054WM-X
COMBO$R
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of