TP3054. TP3057
Enhanced Serial Interface CODEC/Filter COMBO Family
Literature Number: SNAS569
TP3054, TP3057
‘‘Enhanced’’ Serial Interface
CODEC/Filter COMBOÉ Family
General Description
Features
The TP3054, TP3057 family consists of m-law and A-law
monolithic PCM CODEC/filters utilizing the A/D and D/A
conversion architecture shown in Figure 1 , and a serial PCM
interface. The devices are fabricated using National’s advanced double-poly CMOS process (microCMOS).
The encode portion of each device consists of an input gain
adjust amplifier, an active RC pre-filter which eliminates very
high frequency noise prior to entering a switched-capacitor
band-pass filter that rejects signals below 200 Hz and above
3400 Hz. Also included are auto-zero circuitry and a companding coder which samples the filtered signal and encodes it in the companded m-law or A-law PCM format. The
decode portion of each device consists of an expanding
decoder, which reconstructs the analog signal from the
companded m-law or A-law code, a low-pass filter which
corrects for the sin x/x response of the decoder output and
rejects signals above 3400 Hz followed by a single-ended
power amplifier capable of driving low impedance loads.
The devices require two 1.536 MHz, 1.544 MHz or 2.048
MHz transmit and receive master clocks, which may be
asynchronous; transmit and receive bit clocks, which may
vary from 64 kHz to 2.048 MHz; and transmit and receive
frame sync pulses. The timing of the frame sync pulses and
PCM data is compatible with both industry standard formats.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Complete CODEC and filtering system (COMBO)
including:
Ð Transmit high-pass and low-pass filtering
Ð Receive low-pass filter with sin x/x correction
Ð Active RC noise filters
Ð m-law or A-law compatible COder and DECoder
Ð Internal precision voltage reference
Ð Serial I/O interface
Ð Internal auto-zero circuitry
m-law, 16-pinÐTP3054
A-law, 16-pinÐTP3057
Designed for D3/D4 and CCITT applications
g 5V operation
Low operating powerÐtypically 50 mW
Power-down standby modeÐtypically 3 mW
Automatic power-down
TTL or CMOS compatible digital interfaces
Maximizes line interface card circuit density
Dual-In-Line or surface mount packages
See also AN-370, ‘‘Techniques for Designing with
CODEC/Filter COMBO Circuits’’
Connection Diagrams
Plastic Chip Carriers
Dual-In-Line Package
TL/H/5510 – 1
Top View
TL/H/5510 – 10
Order Number TP3054J or TP3057J
See NS Package Number J16A
Top View
Order Number TP3054N or TP3057N
See NS Package Number N16A
Order Number TP3057V
See NS Package Number V20A
Order Number TP3054WM or TP3057WM
See NS Package Number M16B
COMBOÉ and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/H/5510
RRD-B30M125/Printed in U. S. A.
TP3054, TP3057 ‘‘Enhanced’’ Serial Interface CODEC/Filter COMBO Family
August 1994
Block Diagram
FIGURE 1
TL/H/5510 – 2
Pin Description
Symbol
VBB
Symbol
Function
Negative power supply pin.
VBB e b5V g 5%.
GNDA
Analog ground. All signals are referenced
to this pin.
VFRO
Analog output of the receive power amplifier.
VCC
Positive power supply pin.
VCC e a 5V g 5%.
FSR
Receive frame sync pulse which enables
BCLKR to shift PCM data into DR. FSR is
an 8 kHz pulse train. See Figures 2 and 3
for timing details.
DR
Receive data input. PCM data is shifted
into DR following the FSR leading edge.
BCLKR/CLKSEL The bit clock which shifts data into DR after the FSR leading edge. May vary from
64 kHz to 2.048 MHz. Alternatively, may
be a logic input which selects either
1.536 MHz/1.544 MHz or 2.048 MHz for
master clock in synchronous mode and
BCLKX is used for both transmit and receive directions (see Table I).
MCLKR/PDN
Receive master clock. Must be
1.536 MHz, 1.544 MHz or 2.048 MHz.
May be asynchronous with MCLKX, but
MCLKX
Transmit master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be asynchronous
with MCLKR. Best performance is realized from
synchronous operation.
FSX
Transmit frame sync pulse input which enables
BCLKX to shift out the PCM data on DX. FSX is
an 8 kHz pulse train, see Figures 2 and 3 for
timing details.
BCLKX
The bit clock which shifts out the PCM data on
DX. May vary from 64 kHz to 2.048 MHz, but
must be synchronous with MCLKX.
DX
The TRI-STATEÉ PCM data output which is enabled by FSX.
Open drain output which pulses low during the
encoder time slot.
TSX
GSX
Analog output of the transmit input amplifier.
Used to externally set gain.
VFXIb
Inverting input of the transmit input amplifier.
Non-inverting input of the transmit input amplifier.
VFXI a
2
Function
should be synchronous with MCLKX for best performance. When MCLKR is connected continuously low, MCLKX is selected for all internal timing. When MCLKR is connected continuously
high, the device is powered down.
Functional Description
POWER-UP
ASYNCHRONOUS OPERATION
When power is first applied, power-on reset circuitry initializes the COMBO and places it into a power-down state. All
non-essential circuits are deactivated and the DX and VFRO
outputs are put in high impedance states. To power-up the
device, a logical low level or clock must be applied to the
MCLKR/PDN pin and FSX and/or FSR pulses must be present. Thus, 2 power-down control modes are available. The
first is to pull the MCLKR/PDN pin high; the alternative is to
hold both FSX and FSR inputs continuously lowÐthe device
will power-down approximately 1 ms after the last FSX or
FSR pulse. Power-up will occur on the first FSX or FSR
pulse. The TRI-STATE PCM data output, DX, will remain in
the high impedance state until the second FSX pulse.
For asynchronous operation, separate transmit and receive
clocks may be applied. MCLKX and MCLKR must be
2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the
TP3054, and need not be synchronous. For best transmission performance, however, MCLKR should be synchronous
with MCLKX, which is easily achieved by applying only static
logic levels to the MCLKR/PDN pin. This will automatically
connect MCLKX to all internal MCLKR functions (see Pin
Description). For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame.
FSX starts each encoding cycle and must be synchronous
with MCLKX and BCLKX. FSR starts each decoding cycle
and must be synchronous with BCLKR. BCLKR must be a
clock, the logic levels shown in Table 1 are not valid in
asynchronous mode. BCLKX and BCLKR may operate from
64 kHz to 2.048 MHz.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive directions. In this mode, a clock must be applied to MCLKX
and the MCLKR/PDN pin can be used as a power-down
control. A low level on MCLKR/PDN powers up the device
and a high level powers down the device. In either case,
MCLKX will be selected as the master clock for both the
transmit and receive circuits. A bit clock must also be applied to BCLKX and the BCLKR/CLKSEL can be used to
select the proper internal divider for a master clock of 1.536
MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation,
the device automatically compensates for the 193rd clock
pulse each frame.
With a fixed level on the BCLKR/CLKSEL pin, BCLKX will be
selected as the bit clock for both the transmit and receive
directions. Table 1 indicates the frequencies of operation
which can be selected, depending on the state of BCLKR/
CLKSEL. In this synchronous mode, the bit clock, BCLKX,
may be from 64 kHz to 2.048 MHz, but must be synchronous with MCLKX.
Each FSX pulse begins the encoding cycle and the PCM
data from the previous encode cycle is shifted out of the
enabled DX output on the positive edge of BCLKX. After 8
bit clock periods, the TRI-STATE DX output is returned to a
high impedance state. With an FSR pulse, PCM data is
latched via the DR input on the negative edge of BCLKX (or
BCLKR if running). FSX and FSR must be synchronous with
MCLKX/R.
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse or a
long frame sync pulse. Upon power initialization, the device
assumes a short frame mode. In this mode, both frame sync
pulses, FSX and FSR, must be one bit clock period long,
with timing relationships specified in Figure 2 . With FSX high
during a falling edge of BCLKX, the next rising edge of
BCLKX enables the DX TRI-STATE output buffer, which will
output the sign bit. The following seven rising edges clock
out the remaining seven bits, and the next falling edge disables the DX output. With FSR high during a falling edge of
BCLKR (BCLKX in synchronous mode), the next falling edge
of BCLKR latches in the sign bit. The following seven falling
edges latch in the seven remaining bits. All four devices
may utilize the short frame sync pulse in synchronous or
asynchronous operating mode.
LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync pulses,
FSX and FSR, must be three or more bit clock periods long,
with timing relationships specified in Figure 3 . Based on the
transmit frame sync, FSX, the COMBO will sense whether
short or long frame sync pulses are being used. For 64 kHz
operation, the frame sync pulse must be kept low for a minimum of 160 ns. The DX TRI-STATE output buffer is enabled
with the rising edge of FSX or the rising edge of BCLKX,
whichever comes later, and the first bit clocked out is the
sign bit. The following seven BCLKX rising edges clock out
the remaining seven bits. The DX output is disabled by the
falling BCLKX edge following the eighth rising edge, or by
FSX going low, whichever comes later. A rising edge on the
receive frame sync pulse, FSR, will cause the PCM data at
DR to be latched in on the next eight falling edges of BCLKR
(BCLKX in synchronous mode). All four devices may utilize
the long frame sync pulse in synchronous or asynchronous
mode.
In applications where the LSB bit is used for signalling with
FSR two bit clock periods long, the decoder will interpret the
lost LSB as ‘‘(/2’’ to minimize noise and distortion.
TABLE I. Selection of Master Clock Frequencies
BCLKR/CLKSEL
Clocked
0
1
Master Clock
Frequency Selected
TP3057
TP3054
2.048 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
1.536 MHz or
1.544 MHz
3
Functional Description
(Continued)
(due to encoding delay), which totals 290 ms. Any offset
voltage due to the filters or comparator is cancelled by sign
bit integration.
TRANSMIT SECTION
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
see Figure 4 . The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be realized. The op amp drives a unity-gain filter consisting of RC
active pre-filter, followed by an eighth order switched-capacitor bandpass filter clocked at 256 kHz. The output of
this filter directly drives the encoder sample-and-hold circuit.
The A/D is of companding type according to m-law
(TP3054) or A-law (TP3057) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (tMAX) of nominally 2.5V peak (see
table of Transmission Characteristics). The FSX frame sync
pulse controls the sampling of the filter output, and then the
successive-approximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out through DX
at the next FSX pulse. The total encoding delay will be approximately 165 ms (due to the transmit filter) plus 125 ms
RECEIVE SECTION
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz. The decoder is A-law (TP3057) or
m-law (TP3054) and the 5th order low pass filter corrects for
the sin x/x attenuation due to the 8 kHz sample/hold. The
filter is then followed by a 2nd order RC active post-filter/
power amplifer capable of driving a 600X load to a level of
7.2 dBm. The receive section is unity-gain. Upon the occurrence of FSR, the data at the DR input is clocked in on the
falling edge of the next eight BCLKR (BCLKX) periods. At
the end of the decoder time slot, the decoding cycle begins,
and 10 ms later the decoder DAC output is updated. The
total decoder delay is E 10 ms (decoder update) plus
110 ms (filter delay) plus 62.5 ms ((/2 frame), which gives
approximately 180 ms.
4
Absolute Maximum Ratings
Voltage at any Digital Input or
Output
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
VCC to GNDA
VCC a 0.3V to GNDAb0.3V
b 25§ C to a 125§ C
Operating Temperature Range
b 65§ C to a 150§ C
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
300§ C
ESD (Human Body Model)
2000V
Latch-Up Immunity e 100 mA on any Pin
7V
VBB to GNDA
Voltage at any Analog Input
or Output
b 7V
VCC a 0.3V to VBBb0.3V
Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC
e 5.0V g 5%, VBB e b 5.0V g 5%; TA e 0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits
are assured by correlation with other production tests and/or product design and characterization. All signals referenced to
GNDA. Typicals specified at VCC e 5.0V, VBB e b5.0V, TA e 25§ C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.6
V
0.4
0.4
0.4
V
V
V
DIGITAL INTERFACE
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
DX, IL e 3.2 mA
SIGR, IL e 1.0 mA
TSX, IL e 3.2 mA, Open Drain
VOH
Output High Voltage
DX, IH eb3.2 mA
SIGR, IH eb1.0 mA
IIL
Input Low Current
GNDAsVINsVIL, All Digital Inputs
b 10
10
mA
IIH
Input High Current
VIHsVINsVCC
b 10
10
mA
IOZ
Output Current in High Impedance
State (TRI-STATE)
DX, GNDAsVOsVCC
b 10
10
mA
200
2.2
V
2.4
2.4
V
V
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)
IIXA
Input Leakage Current
b 2.5V s V s a 2.5V, VFXI a or VFXI b
b 200
RIXA
Input Resistance
b 2.5V s V s a 2.5V, VFXI a or VFXI b
10
ROXA
Output Resistance
Closed Loop, Unity Gain
RLXA
Load Resistance
GSX
CLXA
Load Capacitance
GSX
VOXA
Output Dynamic Range
GSX, RLt10 kX
b 2.8
AVXA
Voltage Gain
VFXI a to GSX
5000
1
3
10
X
kX
50
1
nA
MX
2.8
pF
V
V/V
FUXA
Unity Gain Bandwidth
VOSXA
Offset Voltage
2
MHz
VCMXA
Common-Mode Voltage
CMRRXA l 60 dB
CMRRXA
Common-Mode Rejection Ratio
DC Test
60
dB
PSRRXA
Power Supply Rejection Ratio
DC Test
60
dB
b 20
20
b 2.5
2.5
mV
V
ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)
RORF
Output Resistance
Pin VFRO
RLRF
Load Resistance
VFRO e g 2.5V
1
CLRF
Load Capacitance
VOSRO
Output DC Offset Voltage
3
X
500
pF
200
mV
600
X
b 200
POWER DISSIPATION (ALL DEVICES)
ICC0
Power-Down Current
No Load (Note)
0.5
1.5
mA
IBB0
Power-Down Current
No Load (Note)
0.05
0.3
mA
ICC1
Power-Up Active Current
No Load
5.0
9.0
mA
IBB1
Power-Up Active Current
No Load
5.0
9.0
mA
Note: ICC0 and IBB0 are measured after first achieving a power-up state.
5
Timing Specifications Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e
5.0V g 5%, VBB e b5.0V g 5%; TA e 0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are
assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA.
Typicals specified at VCC e 5.0V, VBB e b5.0V, TA e 25§ C. All timing parameters are measured at VOH e 2.0V and VOL e
0.7V. See Definitions and Timing Conventions section for test methods information.
Symbol
Parameter
Conditions
Min
Typ
Max
1.536
1.544
2.048
Units
1/tPM
Frequency of Master Clocks
Depends on the Device Used and the
BCLKR/CLKSEL Pin.
MCLKX and MCLKR
tRM
Rise Time of Master Clock
MCLKX and MCLKR
50
ns
tFM
Fall Time of Master Clock
MCLKX and MCLKR
50
ns
tPB
Period of Bit Clock
tRB
Rise Time of Bit Clock
tFB
Fall Time of Bit Clock
BCLKX and BCLKR
tWMH
Width of Master Clock High
MCLKX and MCLKR
160
ns
tWML
Width of Master Clock Low
MCLKX and MCLKR
160
ns
tSBFM
Set-Up Time from BCLKX High
to MCLKX Falling Edge
First Bit Clock after the Leading
Edge of FSX
100
ns
tSFFM
Set-Up Time from FSX High
to MCLKX Falling Edge
Long Frame Only
100
ns
tWBH
Width of Bit Clock High
VIH e 2.2V
160
ns
tWBL
Width of Bit Clock Low
VIL e 0.6V
160
ns
tHBFL
Holding Time from Bit Clock
Low to Frame Sync
Long Frame Only
0
ns
tHBFS
Holding Time from Bit Clock
High to Frame Sync
Short Frame Only
0
ns
tSFB
Set-Up Time from Frame Sync
to Bit Clock Low
Long Frame Only
80
ns
tDBD
Delay Time from BCLKX High
to Data Valid
Load e 150 pF plus 2 LSTTL Loads
tDBTS
Delay Time to TSX Low
Load e 150 pF plus 2 LSTTL Loads
tDZC
Delay Time from BCLKX Low to
Data Output Disabled
tDZF
Delay Time to Valid Data from
FSX or BCLKX, Whichever
Comes Later
tSDB
Set-Up Time from DR Valid to
BCLKR/X Low
50
ns
tHBD
Hold Time from BCLKR/X Low to
DR Invalid
50
ns
tSF
Set-Up Time from FSX/R to
BCLKX/RLow
Short Frame Sync Pulse (1 Bit Clock
Period Long)
50
ns
tHF
Hold Time from BCLKX/R Low
to FSX/R Low
Short Frame Sync Pulse (1 Bit Clock
Period Long)
100
ns
tHBFl
Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
(FSX or FSR)
Long Frame Sync Pulse (from 3 to 8 Bit
Clock Periods Long)
100
ns
tWFL
Minimum Width of the Frame
Sync Pulse (Low Level)
64k Bit/s Operating Mode
160
ns
485
BCLKX and BCLKR
488
MHz
MHz
MHz
15725
ns
50
ns
50
ns
0
140
140
ns
CL e 0 pF to 150 pF
50
165
ns
CL e 0 pF to 150 pF
20
165
ns
6
ns
FIGURE 2. Short Frame Sync Timing
TL/H/5510 – 3
Timing Diagrams
7
FIGURE 3. Long Frame Sync Timing
TL/H/5510 – 4
Timing Diagrams (Continued)
8
Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for
VCC e 5.0V g 5%, VBB e b5.0V g 5%; TA e 0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other
limits are assured by correlation with other production tests and/or product design and characterization. GNDA e 0V, f e
1.02 kHz, VIN e 0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at VCC e 5.0V, VBB
e b 5.0V, TA e 25§ C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AMPLITUDE RESPONSE
Absolute Levels
(Definition of Nominal Gain)
Nominal 0 dBm0 Level is 4 dBm
(600X)
0 dBm0
1.2276
Vrms
Virtual Decision Valve Defined
Per CCITT Rec. G711
Max Overload Level
TP3054 (3.17 dBm0)
TP3057 (3.14 dBm0)
2.501
2.492
VPK
VPK
GXA
Transmit Gain, Absolute
TA e 25§ C, VCC e 5V, VBB eb5V
Input at GSX e 0 dBm0 at 1020 Hz
TP3054/57
GXR
Transmit Gain, Relative to GXA
f e 16 Hz
f e 50 Hz
f e 60 Hz
f e 200 Hz
f e 300 Hzb3000 Hz
f e 3300 Hz
f e 3400 Hz
f e 4000 Hz
f e 4600 Hz and Up, Measure
Response from 0 Hz to 4000 Hz
tMAX
b 0.15
b 1.8
b 0.15
b 0.35
b 0.7
0.15
dB
b 40
b 30
b 26
b 0.1
0.15
0.05
0
b 14
b 32
dB
dB
dB
dB
dB
dB
dB
dB
dB
GXAT
Absolute Transmit Gain Variation
with Temperature
Relative to GXA
b 0.1
0.1
dB
GXAV
Absolute Transmit Gain Variation
with Supply Voltage
Relative to GXA
b 0.05
0.05
dB
GXRL
Transmit Gain Variations with
Level
Sinusoidal Test Method
Reference Level eb10 dBm0
VFXI a eb40 dBm0 to a 3 dBm0
VFXI a eb50 dBm0 to b40 dBm0
VFXI a eb55 dBm0 to b50 dBm0
b 0.2
b 0.4
b 1.2
0.2
0.4
1.2
dB
dB
dB
TA e 25§ C, VCC e 5V, VBB eb5V
Input e Digital Code Sequence for
0 dBm0 Signal at 1020 Hz
TP3054/57
b 0.15
0.15
dB
b 0.15
b 0.35
b 0.7
0.15
0.05
0
b 14
dB
dB
dB
dB
GRA
Receive Gain, Absolute
GRR
Receive Gain, Relative to GRA
f e 0 Hz to 3000 Hz
f e 3300 Hz
f e 3400 Hz
f e 4000 Hz
GRAT
Absolute Receive Gain Variation
with Temperature
Relative to GRA
b 0.1
0.1
dB
GRAV
Absolute Receive Gain Variation
with Supply Voltage
Relative to GRA
b 0.05
0.05
dB
GRRL
Receive Gain Variations with
Level
Sinusoidal Test Method; Reference
Input PCM Code Corresponds to an
Ideally Encoded PCM Level
eb 40 dBm0 to a 3 dBm0
eb 50 dBm0 to b 40 dBm0
eb 55 dBm0 to b 50 dBm0
b 0.2
b 0.4
b 1.2
0.2
0.4
1.2
dB
dB
dB
RL e 600X
b 2.5
2.5
V
VRO
Receive Output Drive Level
9
Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are
guaranteed for VCC e 5.0V g 5%, VBB e b5.0V g 5%; TA e 0§ C to 70§ C by correlation with 100% electrical testing at TA e
25§ C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA
e 0V, f e 1.02 kHz, VIN e 0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at VCC e
5.0V, VBB e b5.0V, TA e 25§ C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ENVELOPE DELAY DISTORTION WITH FREQUENCY
DXA
Transmit Delay, Absolute
f e 1600 Hz
290
315
ms
DXR
Transmit Delay, Relative to DXA
f e 500 Hz – 600 Hz
f e 600 Hz – 800 Hz
f e 800 Hz – 1000 Hz
f e 1000 Hz – 1600 Hz
f e 1600 Hz – 2600 Hz
f e 2600 Hz – 2800 Hz
f e 2800 Hz – 3000 Hz
195
120
50
20
55
80
130
220
145
75
40
75
105
155
ms
ms
ms
ms
ms
ms
ms
DRA
Receive Delay, Absolute
f e 1600 Hz
180
200
ms
DRR
Receive Delay, Relative to DRA
f e 500 Hz – 1000 Hz
f e 1000 Hz – 1600 Hz
f e 1600 Hz – 2600 Hz
f e 2600 Hz – 2800 Hz
f e 2800 Hz – 3000 Hz
70
100
145
90
125
175
ms
ms
ms
ms
ms
b 40
b 30
b 25
b 20
NOISE
NXC
Transmit Noise, C Message
Weighted
TP3054
12
15
dBrnC0
NXP
Transmit Noise, P Message
Weighted
TP3057
b 74
b 67
dBm0p
NRC
Receive Noise, C Message
Weighted
PCM Code is Alternating Positive
and Negative Zero Ð TP3054
8
11
dBrnC0
NRP
Receive Noise, P Message
Weighted
PCM Code Equals Positive
Zero Ð TP3057
b 82
b 79
dBm0p
NRS
Noise, Single Frequency
f e 0 kHz to 100 kHz, Loop Around
Measurement, VFXI a e 0 Vrms
b 53
dBm0
PPSRX
Positive Power Supply Rejection,
Transmit
VFXI a e b50 dBm0
VCC e 5.0 VDC a 100 mVrms
f e 0 kHz – 50 kHz (Note 2)
40
dBC
NPSRX
Negative Power Supply Rejection,
Transmit
VFXI a e b50 dBm0
VBB eb5.0 VDC a 100 mVrms
f e 0 kHz – 50 kHz (Note 2)
40
dBC
PPSRR
Positive Power Supply Rejection,
Receive
PCM Code Equals Positive Zero
VCC e 5.0 VDC a 100 mVrms
Measure VFR0
f e 0 Hz – 4000 Hz
f e 4 kHz – 25 kHz
f e 25 kHz – 50 kHz
40
40
36
dBC
dB
dB
PCM Code Equals Positive Zero
VBB eb5.0 VDC a 100 mVrms
Measure VFR0
f e 0 Hz – 4000 Hz
f e 4 kHz – 25 kHz
f e 25 kHz – 50 kHz
40
40
36
dBC
dB
dB
NPSRR
Negative Power Supply Rejection,
Receive
10
Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are
guaranteed for VCC e 5.0V g 5%, VBB e b5.0V g 5%; TA e 0§ C to 70§ C by correlation with 100% electrical testing at TA e
25§ C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA
e 0V, f e 1.02 kHz, VIN e 0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at VCC e
5.0V, VBB e b5.0V, TA e 25§ C.
Symbol
SOS
Parameter
Conditions
Spurious Out-of-Band Signals
at the Channel Output
Loop Around Measurement, 0 dBm0,
300 Hz to 3400 Hz Input PCM Code Applied
at DR.
4600 Hz – 7600 Hz
7600 Hz – 8400 Hz
8400 Hz – 100,000 Hz
Min
Typ
Max
Units
b 30
dB
b 30
b 40
b 30
dB
dB
dB
DISTORTION
STDX
STDR
Signal to Total Distortion
Transmit or Receive
Half-Channel
Sinusoidal Test Method (Note 3)
Level e 3.0 dBm0
e 0 dBm0 to b 30 dBm0
eb 40 dBm0
XMT
RCV
eb 55 dBm0
XMT
RCV
SFDX
Single Frequency Distortion,
Transmit
b 46
dB
SFDR
Single Frequency Distortion,
Receive
b 46
dB
IMD
Intermodulation Distortion
b 41
dB
b 90
b 75
dB
b 90
b 70
dB
33
36
29
30
14
15
dBC
dBC
dBC
dBC
dBC
dBC
Loop Around Measurement,
VFX a eb4 dBm0 to b21 dBm0, Two
Frequencies in the Range
300 Hz – 3400 Hz
CROSSTALK
CTX-R
Transmit to Receive Crosstalk,
0 dBm0 Transmit Level
f e 300 Hz – 3400 Hz
DR e Quiet PCM Code
CTR-X
Receive to Transmit Crosstalk,
0 dBm0 Receive Level
f e 300 Hz – 3400 Hz, VFXI e Multitone
(Note 2)
ENCODING FORMAT AT DX OUTPUT
TP3057
A-Law
(Includes Even Bit Inversion)
TP3054
m-Law
VIN (at GSX) e a Full-Scale
VIN (at GSX) e 0V
VIN (at GSX) ebFull-Scale
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
Ð
Note 1: Measured by extrapolation from the distortion test result at b 50 dBm0.
Note 2: PPSRX, NPSRX, and CTR-X are measured with a b 50 dBm0 activation signal applied to VFXI a .
Note 3: Devices are measured using C message weighted filter for m-Law and psophometric weighted filter for A-Law.
11
Applications Information
POWER SUPPLIES
This common ground point should be decoupled to VCC and
VBB with 10 mF capacitors.
While the pins of the TP305X family are well protected
against electrical misuse, it is recommended that the standard CMOS practice be followed, ensuring that ground is
connected to the device before any other connections are
made. In applications where the printed circuit board may be
plugged into a ‘‘hot’’ socket with power and clocks already
present, an extra long ground pin in the connector should
be used.
All ground connections to each device should meet at a
common point as close as possible to the GNDA pin. This
minimizes the interaction of ground return currents flowing
through a common bus impedance. 0.1 mF supply decoupling capacitors should be connected from this common
ground point to VCC and VBB, as close to the device as
possible.
For best performance, the ground point of each CODEC/
FILTER on a card should be connected to a common card
ground in star formation, rather than via a ground bus.
RECEIVE GAIN ADJUSTMENT
For applications where a TP305X family CODEC/filter receive output must drive a 600X load, but a peak swing lower
than g 2.5V is required, the receive gain can be easily adjusted by inserting a matched T-pad or q-pad at the output.
Table II lists the required resistor values for 600X terminations. As these are generally non-standard values, the equations can be used to compute the attenuation of the closest
practical set of resistors. It may be necessary to use unequal values for the R1 or R4 arms of the attenuators to
achieve a precise attenuation. Generally it is tolerable to
allow a small deviation of the input impedance from nominal
while still maintaining a good return loss. For example a 30
dB return loss against 600X is obtained if the output impedance of the attenuator is in the range 282X to 319X (assuming a perfect transformer).
T-Pad Attenuator
R1 e Z1
N2 a 1
2b1
#N
#N
R2 e 20Z1.Z2
Where: N e
0
J
b 20Z1.Z2
N
2b1
#N
N
2b1
J
J
POWER IN
POWER OUT
and
Se
0Z2
Z1
Also: Z e 0ZSC # ZOC
Where ZSC e impedance with short circuit termination
and ZOC e impedance with open circuit termination
q-Pad Attenuator
TL/H/5510 – 5
R3 e
0
Z1.Z2
2
#
N2 b 1
N
J
N2 b 1
R3 e Z1
N2 b 2NS a 1
Note: See Application Note 370 for further details.
#
12
J
Applications Information (Continued)
TABLE II. Attentuator Tables for Z1 e Z2 e 300X
(All Values in X)
dB
R1
R2
R3
R4
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
20
1.7
3.5
5.2
6.9
8.5
10.4
12.1
13.8
15.5
17.3
34.4
51.3
68
84
100
115
379
143
156
168
180
190
200
210
218
233
246
26k
13k
8.7k
6.5k
5.2k
4.4k
3.7k
3.3k
2.9k
2.6l
1.3k
850
650
494
402
380
284
244
211
184
161
142
125
110
98
77
61
3.5
6.9
10.4
13.8
17.3
21.3
24.2
27.7
31.1
34.6
70
107
144
183
224
269
317
370
427
490
550
635
720
816
924
1.17k
1.5k
52k
26k
17.4k
13k
10.5k
8.7k
7.5k
6.5k
5.8k
5.2k
2.6k
1.8k
1.3k
1.1k
900
785
698
630
527
535
500
473
450
430
413
386
366
Typical Synchronous Application
TL/H/5510 – 6
Note 1: XMIT gain e 20 c log
#
R1 a R2
R2
J
FIGURE 4
13
where (R1 a R2) l 10 KX.
Connection Diagrams (Continued)
Plastic Chip Carrier
TL/H/5510 – 7
Top View
Order Number TP3057V
See NS Package Number V20A
14
Physical Dimensions inches (millimeters)
Cavity Dual-In-Line Package (J)
Order Number TP3054J or TP3057J
NS Package Number J16A
Molded Small Outline Package (WM)
Order Number TP3054WM or TP3057WM
NS Package Number M16B
15
TP3054, TP3057 ‘‘Enhanced’’ Serial Interface CODEC/Filter COMBO Family
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number TP3054N or TP3057N
NS Package Number N16A
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