TP3064, TP3067
Enhanced Serial Interface CMOS CODEC/Filter COMBO
Literature Number: SNAS570
TP3064, TP3067
‘‘Enhanced’’ Serial Interface
CMOS CODEC/Filter COMBOÉ
General Description
Features
The TP3064 (m-law) and TP3067 (A-law) are monolithic
PCM CODEC/Filters utilizing the A/D and D/A conversion
architecture shown in Figure 1 , and a serial PCM interface.
The devices are fabricated using National’s advanced double-poly CMOS process (microCMOS).
Similar to the TP305X family, these devices feature an additional Receive Power Amplifier to provide push-pull balanced output drive capability. The receive gain can be adjusted by means of two external resistors for an output level
of up to g 6.6V across a balanced 600X load.
Also included is an Analog Loopback switch and a TSX output.
See also AN-370, ‘‘Techniques for Designing with CODEC/
Filter COMBO Circuits.’’
Y
Y
Y
Y
Y
Y
Y
Y
Y
COMBOÉ and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.
Y
Complete CODEC and filtering system including:
Ð Transmit high-pass and low-pass filtering
Ð Receive low-pass filter with sin x/x correction
Ð Active RC noise filters
Ð m-law or A-law compatible COder and DECoder
Ð Internal precision voltage reference
Ð Serial I/O interface
Ð Internal auto-zero circuitry
Ð Receive push-pull power amplifiers
m-lawÐTP3064
A-lawÐTP3067
Designed for D3/D4 and CCITT applications
g 5V operation
Low operating powerÐtypically 70 mW
Power-down standby modeÐtypically 3 mW
Automatic power-down
TTL or CMOS compatible digital interfaces
Maximizes line interface card circuit density
Block Diagram
TL/H/5070 – 1
FIGURE 1
C1995 National Semiconductor Corporation
TL/H/5070
RRD-B30M115/Printed in U. S. A.
TP3064, TP3067 ‘‘Enhanced’’ Serial Interface CMOS CODEC/Filter COMBO
October 1991
Connection Diagrams
Plastic Chip Carrier
Dual-In-Line Package
TL/H/5070 – 6
Top View
Order Number TP3064J or TP3067J
See NS Package J20A
Order Number TP3064WM or TP3067WM
See NS Package M20B
Order Number TP3064N or TP3067N
See NS Package N20A
TL/H/5070–2
Top View
Order Number TP3064V or TP3067V
See NS Package V20A
Pin Description
Symbol
VPO a
GNDA
VPOb
VPI
VFRO
VCC
FSR
DR
BCLKR/
CLKSEL
MCLKR/
PDN
Symbol
MCLKX
Function
The non-inverted output of the receive power
amplifier.
Analog ground. All signals are referenced to
this pin.
The inverted output of the receive power
amplifier.
Inverting input to the receive power amplifier.
Analog output of the receive filter.
Positive power supply pin. VCC e a 5V g 5%.
Receive frame sync pulse which enables
BCLKR to shift PCM data into DR. FSR is an
8 kHz pulse train. See Figures 2 and 3 for
timing details.
Receive data input. PCM data is shifted into
DR following the FSR leading edge.
The bit clock which shifts data into DR after
the FSR leading edge. May vary from 64 kHz
to 2.048 MHz. Alternatively, may be a logic
input which selects either
1.536 MHz/1.544 MHz or 2.048 MHz for
master clock in synchronous mode and
BCLKX is used for both transmit and receive
directions (see Table I).
Receive master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be
asynchronous with MCLKX, but should be
synchronous with MCLKX for best
performance. When MCLKR is connected
continuously low, MCLKX is selected for all
internal timing. When MCLKR is connected
continuously high, the device is powered
down.
BCLKX
DX
FSX
TSX
ANLB
GSX
VFXIb
VFXI a
VBB
2
Function
Transmit master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be
asynchronous with MCLKR. Best
performance is realized from synchronous
operation.
The bit clock which shifts out the PCM data
on DX. May vary from 64 kHz to 2.048 MHz,
but must be synchronous with MCLKX.
The TRI-STATEÉ PCM data output which is
enabled by FSX.
Transmit frame sync pulse input which
enables BCLKX to shift out the PCM data on
DX. FSX is an 8 kHz pulse train, see Figures 2
and 3 for timing details.
Open drain output which pulses low during
the encoder time slot.
Analog Loopback control input. Must be set
to logic ‘0’ for normal operation. When pulled
to logic ‘1’, the transmit filter input is
disconnected from the output of the transmit
preamplifier and connected to the VPO a
output of the receive power amplifier.
Analog output of the transmit input amplifier.
Used to externally set gain.
Inverting input of the transmit input amplifier.
Non-inverting input of the transmit input
amplifier.
Negative power supply pin. VBB eb5V g 5%.
Functional Description
sion performance, however, MCLKR should be synchronous
with MCLKX, which is easily achieved by applying only static
logic levels to the MCLKR/PDN pin. This will automatically
connect MCLKX to all internal MCLKR functions (see Pin
Description). For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame.
FSX starts each encoding cycle and must be synchronous
with MCLKX and BCLKX. FSR starts each decoding cycle
and must be synchronous with BCLKR. BCLKR must be a
clock, the logic levels shown in Table I are not valid in asynchronous mode. BCLKX and BCLKR may operate from 64
kHz to 2.048 MHz.
POWER-UP
When power is first applied, power-on reset circuitry initializes the COMBOTM and places it into a power-down state. All
non-essential circuits are deactivated and the DX, VFRO,
VPOb and VPO a outputs are put in high impedance states.
To power-up the device, a logical low level or clock must be
applied to the MCLKR/PDN pin and FSX and/or FSR pulses
must be present. Thus, 2 power-down control modes are
available. The first is to pull the MCLKR/PDN pin high; the
alternative is to hold both FSX and FSR inputs continuously
lowÐthe device will power-down approximately 2 ms after
the last FSX or FSR pulse. Power-up will occur on the first
FSX or FSR pulse. The TRI-STATE PCM data output, DX,
will remain in the high impedance state until the second FSX
pulse.
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse (the
same as the TP3020/21 CODECs) or a long frame sync
pulse. Upon power initialization, the device assumes a short
frame mode. In this mode, both frame sync pulses, FSX and
FSR, must be one bit clock period long, with timing relationships specified in Figure 2 . With FSX high during a falling
edge of BCLKX, the next rising edge of BCLKX enables the
DX TRI-STATE output buffer, which will output the sign bit.
The following seven rising edges clock out the remaining
seven bits, and the next falling edge disables the DX output.
With FSR high during a falling edge of BCLKR (BCLKX in
synchronous mode), the next falling edge of BCLKR latches
in the sign bit. The following seven falling edges latch in the
seven remaining bits. All devices may utilize the short frame
sync pulse in synchronous or asynchronous operating
mode.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive directions. In this mode, a clock must be applied to MCLKX
and the MCLKR/PDN pin can be used as a power-down
control. A low level on MCLKR/PDN powers up the device
and a high level powers down the device. In either case,
MCLKX will be selected as the master clock for both the
transmit and receive circuits. A bit clock must also be applied to BCLKX and the BCLKR/CLKSEL can be used to
select the proper internal divider for a master clock of 1.536
MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation,
the device automatically compensates for the 193rd clock
pulse each frame.
With a fixed level on the BCLKR/CLKSEL pin, BLCKX will be
selected as the bit clock for both the transmit and receive
directions. Table I indicates the frequencies of operation
which can be selected, depending on the state of BCLKR/
CLKSEL. In this synchronous mode, the bit clock, BCLKX,
may be from 64 kHz to 2.048 MHz, but must be synchronous with MCLKX.
Each FSX pulse begins the encoding cycle and the PCM
data from the previous encode cycle is shifted out of the
enabled DX output on the positive edge of BCLKX. After 8
bit clock periods, the TRI-STATE DX output is returned to a
high impedance state. With an FSR pulse, PCM data is
latched via the DR input on the negative edge of BCLKX (or
BCLKR if running). FSX and FSR must be synchronous with
MCLKX/R.
LONG FRAME SYNC OPERATION
To use the long (TP5116A/56 CODECs) frame mode, both
the frame sync pulses, FSX and FSR, must be three or more
bit clock periods long, with timing relationships specified in
Figure 3 . Based on the transmit frame sync, FSX, the COMBO will sense whether short or long frame sync pulses are
being used. For 64 kHz operation, the frame sync pulse
must be kept low for a minimum of 160 ns. The DX TRISTATE output buffer is enabled with the rising edge of FSX
or the rising edge of BCLKX, whichever comes later, and the
first bit clocked out is the sign bit. The following seven
BCLKX rising edges clock out the remaining seven bits. The
DX output is disabled by the falling BCLKX edge following
the eighth rising edge, or by FSX going low, whichever
comes later. A rising edge on the receive frame sync pulse,
FSR, will cause the PCM data at DR to be latched in on the
next eight falling edges of BCLKR(BCLKX in synchronous
mode). All devices may utilize the long frame sync pulse in
synchronous or asynchronous mode.
TABLE I. Selection of Master Clock Frequencies
BCLKR/CLKSEL
Clocked
0
1
Master Clock
Frequency Selected
TP3067
TP3064
2.048 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
TRANSMIT SECTION
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
see Figure 4 . The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be realized. The op amp drives a unity-gain filter consisting of RC
active pre-filter, followed by an eighth order switched-capacitor bandpass filter clocked at 256 kHz. The output of
this filter directly drives the encoder sample-and-hold circuit.
The A/D is of companding type according to m-law
(TP3064) or A-law (TP3067) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (tMAX) of nominally 2.5V peak (see
1.536 MHz or
1.544 MHz
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and receive
clocks may be applied. MCLKX and MCLKR must be 2.048
MHz for the TP3067, or 1.536 MHZ, 1.544 MHz for the
TP3064, and need not be synchronous. For best transmis3
Functional Description (Continued)
table of Transmission Characteristics). The FSX frame sync
pulse controls the sampling of the filter output, and then the
successive-approximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out through DX
at the next FSX pulse. The total encoding delay will be approximately 165 ms (due to the transmit filter) plus 125 ms
(due to encoding delay), which totals 290 ms. Any offset
voltage due to the filters or comparator is cancelled by sign
bit integration.
ods. At the end of the decoder time slot, the decoding cycle
begins, and 10 ms later the decoder DAC output is updated.
The total decoder delay is E 10 ms (decoder update) plus
110 ms (filter delay) plus 62.5 ms ((/2 frame), which gives
approximately 180 ms.
RECEIVE POWER AMPLIFIERS
Two inverting mode power amplifiers are provided for directly driving a matched line interface transformer. The gain of
the first power amplifier can be adjusted to boost the g 2.5V
peak output signal from the receive filter up to g 3.3V peak
into an unbalanced 300X load, or g 4.0V into an unbalanced 15 kX load. The second power amplifier is internally
connected in unity-gain inverting mode to give 6 dB of signal
gain for balanced loads.
Maximum power transfer to a 600X subscriber line termination is obtained by differentially driving a balanced transformer with a S2:1 turns ratio, as shown in Figure 4 . A total
peak power of 15.6 dBm can be delivered to the load plus
termination.
RECEIVE SECTION
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz. The decoder is A-law (TP3067) or
m-law (TP3064) and the 5th order low pass filter corrects for
the sin x/x attenuation due to the 8 kHz sample/hold. The
filter is then followed by a 2nd order RC active post-filter
with its output at VFRO. The receive section is unity-gain,
but gain can be added by using the power amplifiers. Upon
the occurrence of FSR, the data at the DR input is clocked in
on the falling edge of the next eight BCLKR (BCLKX) peri-
ENCODING FORMAT AT DX OUTPUT
TP3067
A-Law
(Includes Even Bit Inversion)
TP3064
m-Law
VIN e a Full-Scale
VIN e 0V
VIN e bFull-Scale
1
1
0
0
Ð
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
4
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
Absolute Maximum Ratings
Voltage at any Digital Input
or Output
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
VCC to GNDA
VBB to GNDA
Voltage at any Analog Input
or Output
VCC a 0.3V to GNDAb0.3V
Operating Temperature Range
Storage Temperature Range
Lead Temp. (Soldering, 10 sec.)
ESD (Human Body Model) J
ESD (Human Body Model) N
Latch-Up Immunity
7V
b 7V
VCC a 0.3V to VBBb0.3V
b 25§ C to a 125§ C
b 65§ C to a 150§ C
300§ C
1000V
1500V
100 mA on Any Pin
Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e
a 5.0V g 5%, VBB e b 5.0V g 5%; TA e 0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits
are assured by correlation with other production tests and/or product design and characterization. All signals referenced to
GNDA. Typicals specified at VCC e a 5.0V, VBB e b5.0V, TA e 25§ C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note)
0.5
1.5
mA
POWER DISSIPATION (ALL DEVICES)
ICC0
Power-Down Current
IBB0
Power-Down Current
(Note)
0.05
0.3
mA
ICC1
Active Current
VPI e 0V; VFRO, VPO a and VPOb unloaded
7.0
10.0
mA
IBB1
Active Current
VPI e 0V; VFRO, VPO a and VPOb unloaded
7.0
10.0
mA
0.6
V
0.4
0.4
V
V
DIGITAL INTERFACE
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
DX, IL e 3.2 mA
TSX, IL e 3.2 mA, Open Drain
VOH
Output High Voltage
DX, IH eb3.2 mA
IIL
Input Low Current
GNDAsVINsVIL, All Digital Inputs
b 10
10
mA
IIH
Input High Current
VIHsVINsVCC
b 10
10
mA
IOZ
Output Current in High Impedance
State (TRI-STATE)
DX, GNDAsVOsVCC
b 10
10
mA
2.2
Note: ICC0 and IBB0 are measured after first achieving a power-up state.
5
V
2.4
V
Electrical Characteristics (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e a 5.0V g 5%, VBB e b5.0V g 5%; TA e
0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC e
a 5.0V, VBB e b 5.0V, TA e 25§ C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)
IIXA
Input Leakage Current
b 2.5V s V s a 2.5V, VFXI a or VFXI b
b 200
RIXA
Input Resistance
b 2.5V s V s a 2.5V, VFXI a or VFXI b
10
ROXA
Output Resistance
Closed Loop, Unity Gain
RLXA
Load Resistance
GSX
CLXA
Load Capacitance
GSX
VOXA
Output Dynamic Range
GSX, RLt10 kX
b 2.8
AVXA
Voltage Gain
VFXI a to GSX
5000
200
1
3
10
X
kX
50
1
nA
MX
a 2.8
pF
V
V/V
FUXA
Unity-Gain Bandwidth
VOSXA
Offset Voltage
2
MHz
VCMXA
Common-Mode Voltage
CMRRXA l 60 dB
CMRRXA
Common-Mode Rejection Ratio
DC Test
60
dB
PSRRXA
Power Supply Rejection Ratio
DC Test
60
dB
b 20
20
b 2.5
2.5
mV
V
ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)
RORF
Output Resistance
Pin VFRO
RLRF
Load Resistance
VFRO e g 2.5V
1
CLRF
Load Capacitance
Connect from VFRO to GNDA
VOSRO
Output DC Offset Voltage
Measure from VFRO to GNDA
3
10
X
kX
25
pF
b 200
200
mV
100
ANALOG INTERFACE WITH POWER AMPLIFIERS (ALL DEVICES)
IPI
Input Leakage Current
b 1.0V s VPI s 1.0V
b 100
RIPI
Input Resistance
b 1.0V s VPI s 1.0V
10
VIOS
Input Offset Voltage
ROP
Output Resistance
Inverting Unity-Gain at
VPO a or VPOb
FC
Unity-Gain Bandwidth
Open Loop (VPOb)
CLP
Load Capacitance
GAP a
Gain from VPOb to VPO a
RL e 600X VPO a to VPOb
Level at VPOb e 1.77 Vrms
PSRRP
Power Supply Rejection of
VCC or VBB
VPOb Connected to VPI
0 kHzb4 kHz
4 kHzb50 kHz
60
36
dB
dB
Load Resistance
Connect from VPO a to VPOb
600
X
RLP
b 25
25
1
400
b1
mV
X
kHz
100
6
nA
MX
pF
V/V
Timing Specifications
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e a 5.0V g 5%, VBB e b5.0V g 5%, TA e
0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals are referenced to GNDA. Typicals specified at VCC e
a 5.0V, VBB e b 5.0V, TA e 25§ C. All timing parameters are measured at VOH e 2.0V and VOL e 0.7V.
See Definitions and Timing Conventions section for test methods information.
Symbol
1/tPM
Parameter
Conditions
Min
Frequency of Master Clock
Typ
Max
1.536
1.544
2.048
MCLKX and MCLKR
Units
MHz
MHz
MHz
tRM
Rise Time of Master Clock
MCLKX and MCLKR
50
ns
tFM
Fall Time of Master Clock
MCLKX and MCLKR
50
ns
tPB
Period Bit of Clock
tRB
Rise Time of Bit Clock
tFB
Fall Time of Bit Clock
BCLKX and BCLKR
tWMH
Width of Master Clock High
MCLKX and MCLKR
160
ns
tWML
Width of Master Clock Low
MCLKX and MCLKR
160
ns
tSBFM
Set-Up Time from BCLKX High
to MCLKX Falling Edge
100
ns
tSFFM
Set-Up Time from FSX High
to MCLKX Falling Edge
100
ns
tWBH
Width of Bit Clock High
160
ns
tWBL
Width of Bit Clock Low
160
ns
tHBFL
Holding Time from Bit Clock
Low to Frame Sync
Long Frame Only
0
ns
tHBFS
Holding Time from Bit Clock
High to Frame Sync
Short Frame Only
0
ns
tSFB
Set-Up Time for Frame Sync
to Bit Clock Low
Long Frame Only
80
ns
tDBD
Delay Time from BCLKX High
to Data Valid
Load e 150 pF plus 2 LSTTL Loads
tDBTS
Delay Time to TSX Low
Load e 150 pF plus 2 LSTTL Loads
tDZC
Delay Time from BCLKX Low to
Data Output Disabled
tDZF
Delay Time to Valid Data from
FSX or BCLKX, Whichever
Comes Later
tSDB
Set-Up Time from DR Valid to
BCLKR/X Low
50
ns
tHBD
Hold Time from BCLKR/X Low to
DR Invalid
50
ns
tSF
Set-Up Time from FSX/R to
BCLKX/R Low
Short Frame Sync Pulse (1 Bit Clock
Period Long)
50
ns
tHF
Hold Time from BCLKX/R Low
to FSX/R Low
Short Frame Sync Pulse (1 Bit Clock
Period Long)
100
ns
tHBFI
Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
(FSX or FSR)
Long Frame Sync Pulse (from 3 to 8 Bit
Clock Periods Long)
100
ns
tWFL
Minimum Width of the Frame
Sync Pulse (Low Level)
64k Bit/s Operating Mode
160
ns
485
BCLKX and BCLKR
Long Frame Only
CL e 0 pF to 150 pF
7
488
15725
ns
50
ns
50
0
ns
180
ns
140
ns
50
165
ns
20
165
ns
FIGURE 2. Short Frame Sync Timing
TL/H/5070 – 3
Timing Diagrams
8
FIGURE 3. Long Frame Sync Timing
TL/H/5070 – 4
Timing Diagrams (Continued)
9
Transmission Characteristics
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e a 5.0V g 5%, VBB e b5.0V g 5%; TA e
0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other
production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, VIN e 0 dbm0, transmit input amplifier
connected for unity gain non-inverting. Typicals specified at VCC e a 5.0V, VBB e b5.0V, TA e 25§ C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AMPLITUDE RESPONSE
tMAX
Absolute Levels
(Definition of
nominal gain)
Nominal 0 dBm0 Level is 4 dBm
(600X)
0 dBm0
1.2276
Vrms
Virtual Decision Value Defined
per CCITT Rec. G711
Max Transmit Overload Level
TP3064 (3.17 dBm0)
TP3067 (3.14 dBm0)
2.501
2.492
VPK
VPK
GXA
Transmit Gain, Absolute
TA e 25§ C, VCC e 5V, VBB eb5V
GXR
Transmit Gain, Relative to GXA
f e 16 Hz
f e 50 Hz
f e 60 Hz
f e 200 Hz
f e 300 Hz-3000 Hz
f e 3300 Hz
f e 3400 Hz
f e 4000 Hz
f e 4600 Hz and Up, Measure
Response from 0 Hz to 4000 Hz
b 0.15
b 1.8
b 0.15
b 0.35
b 0.7
0.15
dB
b 40
b 30
b 26
b 0.1
0.15
0.05
0
b 14
b 32
dB
dB
dB
dB
dB
dB
dB
dB
dB
GXAT
Absolute Transmit Gain Variation
with Temperature
Relative to GXA
b 0.1
0.1
dB
GXAV
Absolute Transmit Gain Variation
with Supply Voltage
Relative to GXA
b 0.05
0.05
dB
GXRL
Transmit Gain Variations with
Level
Sinusoidal Test Method
Reference Level eb10 dBm0
VFXI a eb40 dBm0 to a 3 dBm0
VFXI a eb50 dBm0 to b40 dBm0
VFXI a eb55 dBm0 to b50 dBm0
b 0.2
b 0.4
b 1.2
0.2
0.4
1.2
dB
dB
dB
GRA
Receive Gain, Absolute
TA e 25§ C, VCC e 5V, VBB eb5V
Input e Digital Code Sequence
for 0 dBm0 Signal
b 0.15
0.15
dB
GRR
Receive Gain, Relative to GRA
f e 0 Hz to 3000 Hz
f e 3300 Hz
f e 3400 Hz
f e 4000 Hz
b 0.15
b 0.35
b 0.7
0.15
0.05
0
b 14
dB
dB
dB
dB
GRAT
Absolute Receive Gain Variation
with Temperature
Relative to GRA
b 0.1
0.1
dB
GRAV
Absolute Receive Gain Variation
with Supply Voltage
Relative to GRA
b 0.05
0.05
dB
GRRL
Receive Gain Variations with
Level
Sinusoidal Test Method; Reference
Input PCM Code Corresponds to an
Ideally Encoded b 10 dBm0 Signal
PCM Level eb40 dBm0 to a 3 dBm0
PCM Level eb50 dBm0 to b40 dBm0
PCM Level eb55 dBm0 to b50 dBm0
b 0.2
b 0.4
b 1.2
0.2
0.4
1.2
dB
dB
dB
RL e 10 kX
b 2.5
2.5
V
VRO
Receive Filter Output at VFRO
10
Transmission Characteristics (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e a 5.0V g 5%, VBB e b5.0V g 5%; TA e
0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other
production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, VIN e 0 dbm0, transmit input amplifier
connected for unity gain non-inverting. Typicals specified at VCC e a 5.0V, VBB e b5.0V, TA e 25§ C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ENVELOPE DELAY DISTORTION WITH FREQUENCY
DXA
Transmit Delay, Absolute
f e 1600 Hz
290
315
ms
DXR
Transmit Delay, Relative to DXA
f e 500 Hzb600 Hz
f e 600 Hzb800 Hz
f e 800 Hzb1000 Hz
f e 1000 Hzb1600 Hz
f e 1600 Hzb2600 Hz
f e 2600 Hzb2800 Hz
f e 2800 Hzb3000 Hz
195
120
50
20
55
80
130
220
145
75
40
75
105
155
ms
ms
ms
ms
ms
ms
ms
DRA
Receive Delay, Absolute
f e 1600 Hz
180
200
ms
DRR
Receive Delay, Relative to DRA
f e 500 Hzb1000 Hz
f e 1000 Hzb1600 Hz
f e 1600 Hzb2600 Hz
f e 2600 Hzb2800 Hz
f e 2800 Hzb3000 Hz
70
100
145
90
125
175
ms
ms
ms
ms
ms
b 40
b 30
b 25
b 20
NOISE
NXC
Transmit Noise, C Message
Weighted
TP3064 (Note 1)
12
15
dBrnC0
NXP
Transmit Noise, Psophometric
Weighted
TP3067 (Note 1)
b 74
b 67
dBm0p
NRC
Receive Noise, C Message
Weighted
PCM Code Equals Alternating
Positive and Negative Zero
TP3064
8
11
dBrnCO
NRP
Receive Noise, Psophometric
Weighted
PCM Code Equals Positive
Zero
TP3067
b 82
b 79
dBm0p
NRS
Noise, Single Frequency
f e 0 kHz to 100 kHz, Loop Around
Measurement, VFXI a e 0 Vrms
b 53
dBm0
PPSRX
Positive Power Supply Rejection,
Transmit
VCC e 5.0 VDC a 100 mVrms
f e 0 kHzb50 kHz (Note 2)
40
dBC
NPSRX
Negative Power Supply Rejection,
Transmit
VBB eb5.0 VDC a 100 mVrms
f e 0 kHzb50 kHz (Note 2)
40
dBC
Positive Power Supply Rejection,
Receive
PCM Code Equals Positive Zero
VCC e 5.0 VDC a 100 mVrms
Measure VFRO
f e 0 Hzb4000 Hz
f e 4 kHzb50 kHz
38
25
dBC
dB
PCM Code Equals Positive Zero
VBB eb5.0 VDC a 100 mVrms
Measure VFRO
f e 0 Hzb4000 Hz
f e 4 kHzb25 kHz
f e 25 kHzb50 kHz
40
40
36
dBC
dB
dB
PPSRR
NPSRR
SOS
Negative Power Supply Rejection,
Receive
Spurious Out-of-Band Signals
at the Channel Output
0 dBm0, 300 Hzb3400 Hz Input
PCM Code Applied at DR
Measure Individual Image Signals at
VFRO
4600 Hz – 7600 Hz
7600 Hz – 8400 Hz
8400 Hz – 100,000 Hz
11
b 32
b 40
b 32
dB
dB
dB
Transmission Characteristics (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e a 5.0V g 5%, VBB e b5.0V g 5%; TA e
0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other
production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, VIN e 0 dbm0, transmit input amplifier
connected for unity gain non-inverting. Typicals specified at VCC e a 5.0V, VBB e b5.0V, TA e 25§ C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DISTORTION
STDX,
STDR
Signal to Total Distortion
Transmit or Receive
Half-Channel
Sinusoidal Test Method (Note 3)
Level e 3.0 dBm0
e 0 dBm0 to b 30 dBm0
eb 40 dBm0
XMT
RCV
eb 55 dBm0
XMT
RCV
SFDX
Single Frequency Distortion,
Transmit
b 46
dB
SFDR
Single Frequency Distortion,
Receive
b 46
dB
IMD
Intermodulation Distortion
b 41
dB
b 90
b 75
dB
b 90
b 70
dB
33
36
29
30
14
15
dBC
dBC
dBC
dBC
dBC
dBC
Loop Around Measurement,
VFXI a eb4 dBm0 to b21 dBm0, Two
Frequencies in the Range
300 Hzb3400 Hz
CROSSTALK
CTX-R
CTR-X
Transmit to Receive Crosstalk
Receive to Transmit Crosstalk
f e 300 Hzb3000 Hz
DR e Quiet PCM Code
f e 300 Hzb3000 Hz, VFXI e 0V
(Note 2)
POWER AMPLIFIERS
VOPA
S/DP
Maximum 0 dBm0 Level
(Better than g 0.1 dB Linearity over
the Range b10 dBm0 to a 3 dBm0)
Signal/Distortion
Balanced Load, RL Connected Between
VPO a and VPOb.
RL e 600X
RL e 1200X
RL e 600X
Note 1: Measured by extrapolation from the distortion test result at b 50 dBm0.
Note 2: PPSRX, NPSRX, and CTRbX are measured with a b 50 dBm0 activation signal applied to VFXI a .
Note 3: TP3064 is measured using C message weighted filter. TP3067 is measured using psophometric weighted filter.
12
3.3
3.5
Vrms
Vrms
50
dB
Applications Information
POWER SUPPLIES
While the pins of the TP3060 family are well protected
against electrical misuse, it is recommended that the standard CMOS practice be followed, ensuring that ground is
connected to the device before any other connections are
made. In applications where the printed circuit board may be
plugged into a ‘‘hot’’ socket with power and clocks already
present, an extra long ground pin in the connector should
be used.
All ground connections to each device should meet at a
common point as close as possible to the GNDA pin. This
minimizes the interaction of ground return currents flowing
through a common bus impedance. 0.1 mF supply decoupling capacitors should be connected from this common
ground point to VCC and VBB, as close to the device as
possible.
For best performance, the ground point of each CODEC/
FILTER on a card should be connected to a common card
ground in ‘‘STAR’’ formation, rather than via a ground bus.
This common ground point should be decoupled to VCC and
VBB with 10 mF capacitors.
Note: See Application Note 370 for further details
Typical Asynchronous Application
TL/H/5070 – 5
Note 1: Transmit gain e 20 c log
#
J
2 R3
,R4
# R4 J
R1 a R2
R2
,(R1 a R2) t 10 kX
c
Note 2: Receive gain e 20 c log
FIGURE 4
13
t 10 kX
Definitions and Timing Conventions
TIMING CONVENTIONS
DEFINITIONS
VIH
VIH is the d.c. input level above which
an input level is guaranteed to appear
as a logical one. This parameter is to
be measured by performing a
functional test at reduced clock
speeds and nominal timing, (i.e. not
minimum setup and hold times or
output strobes), with the high level of
all driving signals set to VIH and
maximum supply voltages applied to
the device
VIL
VIL is the d.c. input level below which
an input level is guaranteed to appear
as a logical zero to the device. This
parameter is measured in the same
manner as VIH but with all driving
signal low levels set to VIL and
minimum supply voltages applied to
the device.
VOH
VOH is the minimum d.c. output level
to which an output placed in a logical
one state will converge when loaded
at the maximum specified load current.
VOL
VOL is the maximum d.c. output level
to which an output placed in a logical
zero state will converge when loaded
at the maximum specified load current.
Threshold Region The threshold region is the range of
input voltages between VIL and VIH.
Valid Signal
A signal is Valid if it is in one of the
valid logic states, (i.e. above VIH or
below VIL). In timing specifiations, a
signal is deemed valid at the instant it
enters a valid state.
Invalid Signal
A signal is Invalid if it is not in a valid
logic state, i.e. when it is in in the
threshold region between VIL and VIH.
In timing specifications, a signal is
deemed Invalid at the instant it enters
the threshold region.
For the purposes of this timing specification, the following
conventions apply:
Input Signals
All input signals may be characterized
as: VL e 0.4V, VH e 2.4V, tR k 10 ns,
tF k 10 ns.
Period
The period of clock signal is
designated as tPxx where xx
represents the mnemonic of the clock
signal being specified.
Rise Time
Rise times are designated as tRyy,
where yy represents a mnemonic of
the signal whose rise time is being
specified. tRyy is measured from VIL to
VIH.
Fall Time
Fall times are designated as tFyy,
where yy represents a mnemonic of
the signal whose fall time is being
specified. tFyy is measured from VIH to
VIL.
Pulse Width High The high pulse width is designated as
tWzzH, where zz represents the
mnemonic of the input or output signal
whose pulse width is being specified.
High pulse widths are measured from
VIH to VIH.
Pulse Width Low The low pulse width is designated as
tWzzL, where zz represents the
mnemonic of the input or output signal
whose pulse width is being specified.
Low pulse widths are measured from
VIL to VIL.
Setup Time
Setup times are designated as tSwwxx,
where ww represents the mnemonic of
the input signal whose setup time is
being specified relative to a clock or
strobe input represented by mnemonic
xx. Setup times are measured from the
ww Valid to xx Invalid.
Hold Time
Hold times are designated as tHxxww,
where ww represents the mnemonic of
the input signal whose hold time is
being specified relative to a clock or
strobe input represented by mnemonic
xx. Hold times are measured from xx
Valid to ww Invalid.
Delay Time
Delay times are designated as tDxxyy
Hi to Low, where xx represents the
mnemonic of the input reference
signal and yy represents the
mnemonic of the output signal whose
timing is being specified relative to xx.
The mnemonic may optionally be
terminated by an H or L to specify the
high going or low going transition of
the output signal. Maximum delay
times are measured from xx Valid to yy
Valid. Minimum delay times are
measured from xx Valid to yy Invalid.
This parameter is tested under the
load conditions specified in the
Conditions column of the Timing
Specifications section of this data
sheet.
14
15
Physical Dimensions inches (millimeters)
Cavity Dual-In-Line Package (J)
Order Number TP3064J or TP3067J
NS Package Number J20A
Molded Small Outline Package (WM)
Order Number TP3064WM or TP3067WM
NS Package Number M20B
16
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number TP3064N or TP3067N
NS Package Number N20A
17
TP3064, TP3067 ‘‘Enhanced’’ Serial Interface CMOS CODEC/Filter COMBO
Physical Dimensions inches (millimeters) (Continued)
Lit. Ý 113975
Plastic Chip Carrier (V)
Order Number TP3064V or TP3067V
NS Package Number V20A
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