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TP3404 Quad Digital Adapter for Subscriber Loops (QDASL)
Check for Samples: TP3404
FEATURES
DESCRIPTION
•
The TP3404 is a combination 4-line transceiver for
voice and data transmission on twisted pair
subscriber loops, typically in PBX line card
applications. It is a companion device to the
TP3401/2/3 DASL single-channel transceivers. In
addition to 4 independent transceivers, a time-slot
assignment circuit is included to support interfacing to
the system backplane.
1
23
•
•
•
•
•
•
•
•
•
•
•
•
•
4 COMPLETE ISDN PBX 2-WIRE DATA
TRANSCEIVERS INCLUDING:
Quad 2 B Plus D Channel Interface for PBX
“U” Interface
144 kb/s Full-Duplex on 1 Twisted Pair Using
Burst Mode Transmission Technique
Loop Range up to 6 kft (#24AWG)
Alternate Mark Inversion Coding with Transmit
Pulse Shaping DAC, Smoothing Filter, and
Scrambler for Low Emi Radiation
Adaptive Line Equalizer
On-Chip Timing Recovery, No External
Components
Programmable Time-Slot Assignment TDM
Interface for B Channels
Separate Interface for D Channel with
Programmable Sub-Slot Assignment
4.096 MHz Master Clock
4 Loop-Back Test Modes
MICROWIRE™ Compatible Serial Control
Interface
5V Operation
28-Pin PLCC Package
Each QDASL line operates as an ISDN “U” Interface
for short loop applications, typically in a PBX
environment, providing transmission for 2 B channels
and 1 D channel.
Full-duplex transmission at 144 kb/s is achieved on
single twisted wire pairs using a burst-mode
technique (Time Compression Multiplexed). All timing
sequences necessary for loop activation and deactivation are generated on-chip.
Alternate Mark Inversion (AMI) line coding is used to
ensure low error rates in the presence of noise with
lower emi radiation than other codes such as Biphase
(Manchester). On #24 AWG cable the range is at
least 1.8 km (6k ft.).
BLOCK DIAGRAM
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MICROWIRE is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1) (2)
VDDA/VDDD to GNDA/GNDD
7V
VCC + 1V to GND − 1V
Voltage at Any Li, Lo Pin
Current at Any Lo
±100 mA
VCC + 1V to GND − 1V
Voltage at Any Digital Input
Current at Any Digital Output
±50 mA
Storage Temperature Range
−65°C to +150°C
Lead Temperature (Soldering, 10 sec.)
(1)
(2)
300°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, limits printed in BOLD characters are specified for VCCA = VCCD = 5V ±5%, TA = 0°C to +70°C.
Typical characteristics are specified at VDDA = VDDD = 5.0V, TA = 25°C. All signals are referenced to GND, which is the
common of GNDA and GNDD
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIGITAL INTERFACES
VIH
Input High Voltage
All Digital Inputs (DC)
VIL
Input Low Voltage
All Digital Inputs (DC)
VOH
Output High Voltage
IL = +1 mA
VOL
Output Low Voltage
IL = −1 mA
IIL
Input Low Current
All Digital Input, GND < VIN < VIL
IIH
Input High Current
All Digital Input, VIH < VIN < VCC
IOZ
Output Current in High Impedance (TRl-STATE) BO, CO, and DO
2
V
0.8
2.4
V
V
0.4
V
−10
10
μA
−10
10
μA
−10
10
μA
LINE INTERFACES
RLi
Input Resistance
0V < VLi < VCC
CLLo
Load Capacitance
From Lo to GND
20
ROLS
Output Resistance
Load = 60Ω in Series with 2 μF to GND
VDC
Mean DC Voltage at Lo
Voltage at LS+, LS−
Load = 200Ω in Series with 2 μF to GND
kΩ
1.75
200
pF
3
Ω
2.25
V
POWER DISSIPATION
ICC0
Power Down Current
BCLK = 0 Hz; MCLK = 0 Hz, CCLK = 0 Hz
10
mA
ICC1
Power Up Current
All 4 Channels Activated
75
mA
1.5
Vpk
TRANSMISSION PERFORMANCE
Transmit Pulse Amplitude at Lo
RL = 200Ω in Series with 2 μF to GND
Input Pulse Amplitude at Li
1.1
1.3
±60
mVpk
TIMING SPECIFICATIONS
Symbol
Parameter
Conditions
Min
Typ
Max
Units
MASTER CLOCK INPUT SPECIFICATIONS
fMCLK
Frequency of MCLK
4.096
−100
MHz
Master Clock Tolerance
Relative 2X MCLK in Slave
tWMH
Period of MCLK High
Measured from VIH to VIH
70
tWML
Period of MCLK Low
Measured from VIL to VIL
70
tRM
Rise Time of MCLK
Measured from VIL to VIH
15
ns
tFM
Fall Time of MCLK
Measured from VIH to VIL
15
ns
2
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+100
ppm
ns
ns
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ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified, limits printed in BOLD characters are specified for VCCA = VCCD = 5V ±5%, TA = 0°C to +70°C.
Typical characteristics are specified at VDDA = VDDD = 5.0V, TA = 25°C. All signals are referenced to GND, which is the
common of GNDA and GNDD
Symbol
Parameter
Conditions
Min
Typ
Max
Units
4.096
4.1
MHz
DIGITAL INTERFACE TIMING
fBCLK
BCLK Frequency
tWBH,
Clock Pulse Width High
Measured from VIH to VIH
70
tWBL
and Low for BCLK
Measured from VIL to VIL
70
tRB,
Rise Time and Fall Time
Measured from VIL to VIH
tFB
of BCLK
Measured from VIH to VIL
tHBM
BCLK Transition to MCLK High or Low
−30
tSFC
Set up Time, FS Valid to BCLK Invalid
20
4
ns
tHCF
Hold Time, BCLK Low to FS Invalid
40
30
ns
tSBC
Setup Time, BI Valid to BCLK Invalid
30
11
ns
tHCB
Hold Time, BCLK Valid to BI Invalid
40
7
ns
tSDC
Setup Time, DI Valid to BCLK Low
30
tHCD
Hold Time, BCLK Low to DI Invalid
tDCB
Delay Time, BCLK High to BO Valid
tDCBZ
Delay Time, BCLK Low to BO High-Z
tDCD
Delay Time, BCLK High to DO valid
tDCZ
Delay Time, BCLK Low to DO High Impedance
tDCT
tZBT
ns
15
ns
15
30
ns
40
Load = 2 LSTTL + 100 pF
ns
ns
80
ns
80
120
ns
80
ns
40
120
ns
Delay Time, BCLK High to TSB Low
120
ns
Disable Time, BCLK Low to TSB High-Z
120
ns
2.1
MHz
Load = 2 LSTTL + 100 pF
MICROWIRE CONTROL INTERFACE TIMING
fCCLK
Frequency of CCLK
tCH
Period of CCLK High
Measured from VIH to VIH
150
ns
tCL
Period of CCLK Low
Measured from VIL to VIL
150
ns
tSSC
Setup Time, CS Low to CCLK High
50
ns
tHCS
Hold Time, CCLK High to CS Transition
40
ns
tSIC
Setup Time, CI Valid to CCLK High
50
ns
tHCI
Hold Time, CCLK High to CI Invalid
20
tDCO
Delay Time, CCLK Low to CO Valid
80
ns
tDSOZ
Delay Time, CS High to CO High-Z
80
ns
tDCIZ
Delay Time, CCLK to INT High-Z
100
ns
ns
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PIN DESCRIPTIONS
Pin
Pin
No.
Name
4
Description
1
GNDA
Analog Ground or 0V. All analog signals are referenced to this pin.
15
GNDD
Digital Ground 0V. It must connect to GNDA with a shortest possible trace. This can be done directly underneath the part.
28
VDDA
Positive power supply input to QDASL analog section. It must be 5V ±5%.
16
VDDD
Positive power supply input to QDASL digital section. It must be 5V ±5%, and connect to VDDA with the shortest possible
trace. This can be done directly underneath the part.
11
FS
9
MCLK
This pin is the 4.096 MHz Master Clock input, which requires a CMOS logic level clock from a stable source. MCLK must
be synchronous with BCLK.
10
BCLK
Bit Clock logic input, which determines the data shift rate for B and D channel data at the BI, BO, DI and DO pins. BCLK
may be any multiple of 8 kHz from 256 kHz to 4.096 MHz, but must be synchronous with MCLK.
12
BI
Time-division multiplexed input for B1 and B2 channel data to be transmitted to the 4 lines. Data on this pin is shifted in on
the failing edge of BCLK into the B1 and B2 channels during the selected transmit time-slots.
13
BO
Time-division multiplexed receive data output bus. B1 and B2 channel data from all 4 lines is shifted out on the rising edge
of BCLK on this pin during the assigned receive time-slots. At all other times this output is TRI-STATE (high impedance).
14
TSB
This pin is an open-drain output which is normally high impedance but pulls low during any active B channel receive time
slots at the BO pin.
7
DI
Time-division multiplexed input for D channel data to be transmitted to the 4 lines. Data on this pin is shifted in on the
failing edge of BCLK into the D channel during the selected transmit sub-time-slots.
8
DO
Time-division multiplexed output for D channel data received from the 4 lines. Data on this pin is shifted out on the rising
edge of BCLK during the selected receive sub-time-slot.
19
CCLK
Microwire Control Clock input. This clock shifts serial control information into CI and out from CO when the CS input is low,
depending on the current instruction. CCLK may be asynchronous with the other system clocks.
21
CI
Control data Input. Serial control information is shifted into the QDASL on this pin on the rising edges of CCLK when CS is
low.
17
INT
Interrupt request output, a latched output signal which is normally high impedance and goes low to indicate a change of
status of any of the 4 loop transmission systems. This latch is cleared when the Status Register is read by the
microprocessor. Bipolar Violation does not effect this output.
20
CO
Control data Output. Serial control/status information is shifted out from the QDASL on this pin on the falling edges of
CCLK when CS is low.
18
CS
Chip Select input. When this pin is pulled low, the Microwire interface is enabled to allow control information to be written
in to and out from the device via the CI and CO ins. When high, this pin inhibits the Microwire interface.
4
3
26
25
Lo0
Lo1
Lo2
Lo3
Line driver transmit outputs for the 4 transmission channels. Each output is an amplifier intended to drive a transformer.
5
2
27
24
Li0
Li1
Li2
Li3
Line receive amplifier inputs for the 4 transmission channels. Each Li pin is a self-biased high impedance input which
should be connected to the transformer via the recommended line interface circuit.
Frame Sync input: this signal is the 8 kHz clock which defines the start of the transmit and receive frames at the digital
interfaces.
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Li1
GNDA
VDDA
3
2
1
28 27 26
Lo2
Lo1
4
Li2
Lo0
CONNECTION DIAGRAM
Li0
5
25
Lo3
NC
6
24
Li3
DI
7
23
NC
DO
8
22
NC*
MCLK
9
21
CI
BCLK
10
20
CO
FS
11
19
CCLK
CS
INT
VDDD
GNDD
TSB
BI
BO
12 13 14 15 16 17 18
* Do not connect to this pin.
Figure 1. Top View
See Package Number FN0028A
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FUNCTIONAL DESCRIPTION
The QDASL contains 4 transceivers, each of which can interoperate with any of the TP340X family of singlechannel DASL transceivers. Each QDASL transceiver has its own independent line transmit and receive section,
timing recovery circuit, scrambler/descrambler and loop activation controller. Functions which are shared by the 4
transceivers include the Microwire control port and the digital interface with time-slot assignment.
BURST MODE OPERATION
For full-duplex operation over a single twisted-pair, burst mode timing is used, with the QDASL end of each line
acting as the loop timing master, and the DASL at the terminal being the timing slave (the QDASL transceivers
cannot operate in loop timing slave mode).
Each burst within a DASL line is initiated by the QDASL Master transmitting a start bit, for burst framing, followed
by the B1, B2 and D channel data from 2 consecutive 8 kHz frames, combined in the format shown in Figure 2.
During transmit bursts the receiver input for that channel is inhibited to avoid disturbing the adaptive circuits. The
slave's receiver is enabled at this time and it synchronizes to the start bit of the burst, which is always an
unscrambled “1” (of the opposite polarity to the last “1” sent in the previous burst). When the slave detects that
36 bits following the start bit have been received, it disables the received input, waits 6 line symbol periods to
match the other end settling guard time, and then begins to transmit its burst back towards the master, which by
this time has enabled its receiver input. The burst repetition rate is thus 4 kHz.
LINE TRANSMIT SECTIONS
Alternate Mark Inversion (AMI) line coding, in which binary “1”s are alternately transmitted as a positive pulse
then a negative pulse, is used on each DASL line because of its spectral efficiency and null DC energy content.
All transmitted bits, excluding the start bit, are scrambled by a 9-bit scrambler to provide good spectral spreading
with a strong timing content. The scrambler feedback polynomial is: X9 + X5 + 1.
Figure 2. Burst Mode Timing on the Line
Pulse shaping is obtained by means of a Digital to Analog Converter followed by a Continuous Smoothing Filter,
in order to limit RF energy and crosstalk while minimizing Inter-Symbol Interference (ISI). Figure 3 shows the
pulse shape at the Lo output, while a template for the typical power spectrum transmitted to the line with random
data is shown in Figure 4.
Each line-driver output, Lo0–Lo3, is designed to drive a transformer through a capacitor and termination resistor.
A 1:1 transformer, terminated in 100Ω, results in signal amplitude of typically 1.3 Vpk on the line. Over-voltage
protection must be included in each interface circuit.
6
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LINE RECEIVE SECTIONS
The input of each receive section, Li0–Li3, consists of a continuous anti-alias filter followed by a switchedcapacitor low-pass filter designed to limit the noise bandwidth with minimum intersymbol interference. To correct
pulse attenuation and distortion caused by the transmission line an AGC circuit and first-order equalizer adapt to
the received pulse shape, thus restoring a “flat” channel response with maximum received eye opening over a
wide spread of cable attenuation characteristics.
From the equalized output a DPLL (Digital Phase-Locked Loop) recovers a low-jitter clock for optimum sampling
of the received symbols. The MCLK input provides the reference clock for the DPLL at 4.096 MHz.
Following detection of the recovered symbols, the received data is de-scrambled by the same X9 + X5 + 1
polynomial and presented to the digital system interface circuit.
When a transmission line is de-activated, a Line-Signal Detect Circuit is enabled to detect the presence of
incoming bursts if the far-end starts to activate the loop.
Figure 3. Typical AMI Waveform at Lo
Figure 4. Typical AMI Transmit Spectrum Measured at LO Output (With RGB = 100 Hz)
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ACTIVATION AND LOOP SYNCHRONIZATION
Activation (i.e. power-up and loop synchronization) may be initiated from either end of the loop. If the master
(QDASL) end is activating the loop, it sends normal bursts of scrambled “1”s which are detected by the slave's
line-signal-detect circuitry. The slave then replies with bursts of scrambled “1”s synchronized to the received
bursts, and the Framing Detection circuit at each end searches for 4 consecutive correctly formatted receive
bursts to acquire full loop synchronization. The QDASL receiver indicates when it is correctly in sync with
received bursts by setting an indication in the Status Register and pulling the INT pin low.
For the slave end to initiate activation, it begins transmission of alternate bursts i.e., the burst repetition rate is 2
kHz, not 4 kHz. At this point the slave is running from its local oscillator and is not receiving any sync information
from the master. When the master's Line-Signal Detect Circuit recognizes this “wake-up” signal, the appropriate
QDASL line must be activated by writing to the Control Register. The master begins to transmit bursts
synchronized, as normal, to the FS input with a 4 kHz repetition rate. This enables the slave's receiver to
correctly identify burst timing from the master and to re-synchronize its own burst transmissions to those it
receives. The Framing Detection Circuits then acquire full loop sync as described earlier.
Loop synchronization is considered to be lost if the Framing Detection Circuit does not find four framing marks of
the four consecutive 4 kHz line frames. At this point an indication is set in the Status Register, the INT output is
pulled low, and the receiver searches to re-acquire loop sync.
MICROWIRE CONTROL INTERFACE
A serial interface, which can be clocked independently from the B and D channel system interfaces, is provided
for microcontroller access to the time-slot assignment, Control and Status Registers in the QDASL. The
microcontroller is normally the timing master of this interface, and it supplies the CCLK and CS signals.
All data transfers consist of simultaneous read and write cycles, in which 2 continuous bytes are sampled on the
CI pin, at the same time as 2 bytes are shifted out from the CO pin, see Figure 7. The first byte is a register
address and the second is the data. To initiate a Microwire read/write cycle, CS must be pulled low for 16 cycles
of CCLK. Data on CI is sampled on rising edges of CCLK, and shifted out from CO on failing edges. When CS is
high, the CO pin is in the high-impedance TRI-STATE, enabling the CO pins of many devices to be multiplexed
together.
Whenever a change (except Bipolar Violation) in any of the QDASL status conditions occurs, the Interrupt output
INT is pulled low to alert the microprocessor to initiate a read cycle of the Status Register. This latched output is
cleared when the read cycle is initiated.
Table 1 lists the address map of control functions and status indicators. Table 2 lists the addresses for the
Control Registers for each QDASL line. Even-numbered addresses are read-write cycles, in which the data
returned by the CO pin is previous contents of the addressed register. Odd-numbered addresses are readback
commands only.
Table 1. Global Register Address Map
Address
Registers
(Hex)
00–0F
LINE 0 Control (TSX,TSR,CTRL)
10–1F
LINE 1 Control (TSX,TSR,CTRL)
20–2F
LINE 2 Control (TSX,TSR,CTRL)
30–3F
LINE 3 Control (TSX,TSR,CTRL)
40–CF
Not used
FF
Common Status Register for all lines (0–3).
See Table 6
8
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Table 2. Per Line Control Register Address Map
Byte 1
Function
MSB Nibble
7
5
LSB Nibble
4
Byte 2
3
2
1
0
Write TSXD Register
N
0
0
0
0
See Table 5
Read TSXD Register
N
0
0
0
1
See Table 5
Write TSXB1 Register
N
0
0
1
0
See Table 4
Read TSXB1 Register
N
0
0
1
1
See Table 4
Write TSXB2 Register
N
0
1
0
0
See Table 4
Read TSXB2 Register
N
0
1
0
1
See Table 4
Write TSRD Register
N
0
1
1
0
See Table 5
Read TSRD Register
N
0
1
1
1
See Table 5
Write TSRB1 Register
N
1
0
0
0
See Table 4
Read TSRB1 Register
N
1
0
0
1
See Table 4
Write TSRB2 Register
N
1
0
1
0
See Table 4
Read TSRB2 Register
N
1
0
1
1
See Table 4
Write Line Control Register (CTR L)
N
1
1
1
0
See Table 3
Read Line Control Register (CTRL)
N
1
1
1
1
See Table 3
(1)
(2)
6
(2)
(1)
Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI and CO pins.
N = 0, 1, 2, or 3 in straight Binary notation for Line 0, 1, 2, or 3 respectively.
LINE CONTROL REGISTERS CTRLN
Each of the 4 transceivers has a Line Control Register, CTRL0–CTRL3, which provides for control of loop
activation, Ioopbacks, Interrupt enabling and D channel interface enabling. Table 3 lists the functions.
POWER ON INITIALIZATION
Following the initial application of power, the QDASL enters the power-down (de-activated) state, in which all the
internal circuits are inactive and in a low power state except for a Line-Signal Detect Circuit for each of the 4
lines, and the necessary bias circuits. The 4 line outputs, Lo0–Lo3, are in a high impedance state and all digital
outputs are inactive. All bits in the Line Control Registers power-up initially set to “0”. While powered-down, each
Line-Signal Detect Circuit continually monitors its line, to detect if the far-end initiates loop transmission.
POWER-UP/DOWN CONTROL
To power-up the device and initiate activation, bit C7 in any of the 4 Line Control Registers must be set high, see
Table 3. Setting C7 low de-activates the loop, or puts the channel in power-down state. During power-down
state, internal register data is retained, and still can be accessed.
LOOPBACKS
Four different loopbacks can be set for each line. They are enabled and disabled by setting the corresponding
bits in the Control Register, see Table 3. In addition, a line must be activated to see the effect of loopback
commands.
1. 2B+D Line Loopback
– When bit 5 is set to 1, this loop will transfer all three channels, B1, B2 and D, that are received at the Li
pin back to the Lo pin. Data out on BO/DO is still the same as received at the Li input.
2. B1 Line Loopback
– When bit 4 is set high, the loop path is the same as (1) but only data on the B1 channel is looped back to
the line. Transmit data in the B2 and D channels is from the Bi/DI pins.
3. B2 Line Loopback
– As (2) but for the B2 channel.
4. 2B+D Digital Loopback
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– This loop will transfer all data (2B+D) received at BI/DI back to BO/DO. The data is also transmitted to the
line.
TIME-SLOT ASSIGNMENT
The digital interface of the QDASL uses time-division multiplexing, with data framed in up to 64 possible 8-bit
time-slots per 125 μs frame. Channels B1 and B2 for all 4 lines are clocked in (towards the line) at the BI pin and
clocked out (from the line) at the BO pin. A separate port is provided for the D channel data for all 4 lines, which
is clocked in on DI and out on DO. In addition to time-slot assignment, D channel data may be assigned into 2-bit
sub-slots within each time slot, with up to 256 sub-slots per frame (with BCLK = 4.096 MHz). Each frame starts
with the first positive edge of BCLK after the FS signal goes high, and counting of timeslots starts from zero at
the beginning of the frame. Figure 5 shows the timing, with some example time-slot assignments.
For each of the 4 QDASL lines there are 6 Time-Slot Assignment control registers, one each for transmit and
receive B1, B2 and D channels. Selection of time-slots for transmit data into the BI or DI pin is made by writing
the timeslot number (in Hex notation) into the appropriate TSX register. TSXB1 is the time-slot assignment for
the transmit B1, TSXB2 is the time-slot assignment register for the transmit B2 channel and TSXD is the sub-slot
assignment register for the transmit D channel.
Table 3. Byte 2 of Control Register (CTRLN)
Bit Number
7
6
5
4
Function
3
2
1
0
0
Deactivate Line
1
Activate Line
0
Disable Digital Loopback
1
Enable 2B+D Digital Loopback
0
Disable Line Loopback
1
Enable 2B+D Line Loopback
0
Disable B1 Line Loopback
1
Enable B1 Line Loopback
0
Disable B2 Line Loopback
1
Enable B2 Line Loopback
0
Disable Interrupt from this Line
1
Enable Interrupt from this Line
0
D Channel enabled from DO to Line
1
D Channel disabled from DO to Line
0
D Channel enabled from Line to DI
1
D Channel disabled from Line to DI
In the same manner the time-slot number should be written into the appropriate TSR registers for receive data at
the BO and DO pins. TSRB1 is the time-slot assignment for the receive B1 channel, TSRB2 is the time-slot
assignment register for the receive B2 channel and TSRD is the sub-slot assignment register for the receive D
channel.
Whenever any receive time-slot is active at BO, the TSB output is also pulled low.
REGISTERS TSXB1, TSXB2, TSRB1, TSRB2
The data format for all B channel time-slot assignment registers is shown in Table 4.
BIT 7 TRANSPARENCY CONTROL: EB
This bit enables or disables data transparency between the digital interface and the line interface for the selected
channel.
EB = 0 disables the channel.
EB = 1 enables the channel.
10
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When the transmit direction (towards the line) is disabled there will be all “ONE's” (scrambled) as data for this
channel at the Lo pin. If the receive direction (from the line) is disabled, BO will stay high impedance for the
programmed time slot while, if it is enabled, data out on BO in the assigned time slot is the data from Li.
BITS 5–0: TS5–TS0
These bits define the binary number of the time-slot selected. Time-slots are numbered from 0–63. The frame
sync signal is used as marker pulses for the beginning of time slot 0.
Table 4. Byte 2 of Register TSXB1, TSXB2, TSRB1 or TSRB2 for B Channel Time-Slot Assignment
Bit Number and Name
Function
7
6
5
4
3
2
1
0
EB
X
TS5
TS4
TS3
TS2
TS1
TS0
0
X
X
X
X
X
X
X
1
X
Disable B1 and/or B2
Assign One Binary Coded Time-Slot from 0–63
Enable B1 and/or B2
REGISTERS TXD, TRD
The data format for all D channel time-slot assignment registers is as follows:
Data transparency between the digital interface and the line interface for the D channels can be controlled via the
Channel Control Register, see Table 3.
BITS 7–0: TS7–TS0
These bits define the binary number of the sub-slot selected. Sub-slots are numbered from 0–255. The frame
sync signal is used as marker pulses for the beginning of Sub-slot 0.
Table 5. Byte 2 of Register TSXD or TSRD for D Channel Time-Slot Assignment
Bit Number and Name
7
6
5
4
3
2
1
0
SS
SS
SS
SS
SS
SS
SS
SS
7
6
5
4
3
2
1
0
Assign One Binary Coded Sub-Slot from 0–255 for D Channel
Figure 5. QDASL Digital Interface Timing
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Table 6. Status Register Functions
Byte 2
(1)
5
4
Indication
7
6
3
2
1
0
0
0
Line 3: deactivated
0
1
Line 3: line signal present but not in sync
1
0
Line 3: activated, bipolar violation
1
1
Line 3: activated, no bipolar violation
(1)
0
0
Line 2: deactivated
0
1
Line 2: line signal present but not in sync
1
0
Line 2: activated, bipolar violation
1
1
(1)
Line 2: activated, no bipolar violation
0
0
Line 1: deactivated
0
1
Line 1: line signal present but not in sync
1
0
Line 1: activated, bipolar violation
1
1
(1)
Line 1: activated, no bipolar violation
0
0
Line 0: deactivated
0
1
Line 0: line signal present but not in sync
1
0
Line 0: activated, bipolar violation
1
1
Line 0: activated, no bipolar violation
(1)
Bipolar Violation does not cause an Interrupt.
STATUS REGISTER
Status information for all 4 channels may be read from the common Status Register by addressing location X′FF.
2 bits per line are coded as shown in Table 6. A change in the status of 1 or more lines is indicated by the INT
pin being pulled low, provided bit 2 of the corresponding control register is set to “ONE” to enable the interrupt for
that line.
BIPOLAR VIOLATION DETECTOR
On an activated line, whenever a line error is received there will be a violation of the AMI coding rule. This is
reported by setting the code 10 for that line. The violation indication is cleared to 11 after a read of the Status
Register.
As an example of the interpretation of the Status Register contents, if the byte 2 read back from the Status
Register =00111001 (=X′39), this indicates the following status of the 4 lines: line 3 is deactivated; line 2 is in
sync with no error since the last read cycle; line 1 is in sync but there has been 1 or more errors since the last
read cycle of the Status Register; line 0 is receiving a line signal but the line transmission is not synchronized.
12
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SNOS703 – DECEMBER 2004
APPLICATIONS INFORMATION
POWER SUPPLIES
While the pins of the TP3404 QDASL device are well protected against electrical misuse, it is recommended that
the standard CMOS practice of applying GND to the device before any other connections are made should
always be followed. In applications where the printed circuit card may be plugged into a hot socket with power
and clocks already present, an extra long ground pin on the connector should be used.
To minimize noise sources, the VDDA and VDDD pins should be connected together via the shortest possible
trace; likewise the GNDA and GNDD pins must be connected together. These two connections can be done
directly underneath the part. All other ground connections to each device should meet at a common point as
close as possible to the GNDD pin in order to prevent the interaction of ground return currents flowing through a
common bus impedance. A power supply decoupling capacitor of 0.1 μF should be connected from this common
point to VDDD as close as possible to the device pins.
Figure 6 shows a typical 4 line application of the QDASL. The current list of suitable commercial transformers is:
Schott Corporation (Nashville);
Phone 615-889-8800.
Part numbers: 67110850 (dry);
Part numbers: 67110860 (50 mA DC).
Pulse Engineering (San Diego);
Phone 619-674-8100.
Part number:TBD.
Note that the Zener diode protection shown in Figure 9 is only intended as secondary protection for inside wiring
applications; primary protection is also necessary. Further information can be found in the datasheet for the
TP3401/2/3 DASL devices (SNOSC12) and in Application Note AN-509 “Using the TP3401/2/3 ISDN PBX
Transceivers”.
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Figure 6. Typical Application
14
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Figure 7. Microwire Control Interface Timing Details
Figure 8. B Channel Digital Interface Details
Figure 9. D-Channel Digital Interface Timing Details
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PACKAGE OPTION ADDENDUM
www.ti.com
30-May-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TP3404V/63SN
LIFEBUY
PLCC
FN
28
750
Green (RoHS
& no Sb/Br)
CU SN
Level-2A-245C-4
WEEK
TP3404V
TP3404V/NOPB
LIFEBUY
PLCC
FN
28
35
Green (RoHS
& no Sb/Br)
CU SN
Level-3-245C-168 HR
TP3404V
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
