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TPA2013D1
SLOS520A – AUGUST 2007 – REVISED MARCH 2016
TPA2013D1 2.7-W Constant Output Power Class-D Audio Amplifier With Integrated Boost
Converter
1 Features
3 Description
•
The TPA2013D1 device is a high efficiency Class-D
audio power amplifier with an integrated boost
converter. It drives up to 2.7 W (10% THD+N) into a
4-Ω speaker. With 85% typical efficiency, the
TPA2013D1 helps extend battery life when playing
audio.
1
•
•
•
•
•
•
•
•
•
•
•
High Efficiency Integrated Boost Converter (Over
90% Efficiency)
2.2-W into an 8-Ω Load from a 3.6-V Supply
2.7-W into an 4-Ω Load from a 3.6-V Supply
Operates from 1.8 V to 5.5 V
Efficient Class-D Prolongs Battery Life
Independent Shutdown for Boost Converter and
Class-D Amplifier
Differential Inputs Reduce RF Common Noise
Built-In INPUT Low-Pass Filter Decreases RF and
Out-of-Band Noise Sensitivity
Synchronized Boost and Class-D Eliminates Beat
Frequencies
Thermal and Short-Circuit Protection
Available in 2.275-mm × 2.275-mm 16-ball WCSP
and 4-mm × 4-mm 20-Lead QFN Packages
3 Selectable Gain Settings of 2 V/V, 6 V/V, and
10 V/V
The built-in boost converter generates the voltage rail
for the Class-D amplifier. This provides a louder
audio output than a stand-alone amplifier connected
directly to the battery. It also maintains a consistent
loudness, regardless of battery voltage. Additionally,
the boost converter can be used to supply external
devices.
The TPA2013D1 has an integrated low pass filter to
improve RF rejection and reduce out-of-band noise,
increasing the signal-to-noise ratio (SNR). A built-in
PLL synchronizes the boost converter and Class-D
switching frequencies, thus eliminating beat
frequencies and improving audio quality. All outputs
are fully protected against shorts to ground, power
supply, and output-to-output shorts.
Device Information(1)
2 Applications
•
•
•
•
PART NUMBER
Cell Phones
PDA
GPS
Portable Electronics
TPA2013D1
PACKAGE
BODY SIZE (NOM)
VQFN (20)
4.00 mm × 4.00 mm
DSBGA (16)
2.275 mm × 2.275 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Schematic
R1
50 kΩ
R2
500 kΩ
22 mF
1 mF
2.2 to 6.2 mH
To Battery
10 mF
VDD
SW VCCFB
VCCOUT
VCCIN
CIN
IN–
Differential
Input
1 mF
VOUT+
IN+
CIN
Gain (VCC/Float/GND)
GPIO
TPA2013D1
VOUT–
GAIN
ShutDown Boost
SDb
ShutDown ClassD
SDd
AGND
PGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA2013D1
SLOS520A – AUGUST 2007 – REVISED MARCH 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
4
4
4
4
5
5
6
6
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
DC Characteristics ....................................................
Boost Converter DC Characteristics .........................
Class D Amplifier DC Characteristics .......................
AC Characteristics ....................................................
Class D Amplifier AC Characteristics........................
Dissipation Ratings .................................................
Typical Characteristics ............................................
Parameter Measurement Information ................ 13
Detailed Description ............................................ 14
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
14
16
10 Application and Implementation........................ 18
10.1 Application Information.......................................... 18
10.2 Typical Applications .............................................. 18
11 Power Supply Recommendations ..................... 25
11.1 Power Supply Decoupling Capacitors................... 25
12 Layout................................................................... 25
12.1 Layout Guidelines ................................................. 25
12.2 Layout Examples................................................... 27
12.3 Efficiency and Thermal Considerations ................ 28
13 Device and Documentation Support ................. 30
13.1
13.2
13.3
13.4
13.5
Device Support ....................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
14 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2007) to Revision A
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
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5 Device Comparison Table
DEVICE NUMBER
SPEAKER AMP TYPE
SPECIAL FEATURE
OUTPUT POWER (W)
PSRR (Db)
TPA2013D1
Class D
Boost Converter
2.7
95
TPA2015D1
Class D
Adaptive Boost Converter
2
85
TPA2025D1
Class D
Class G Boost Converter
2
65
TPA2080D1
Class D
Class G Boost Converter
2.2
62.5
6 Pin Configuration and Functions
RGP Package
20-Pin VQFN
Top View
PGND
SW
SW
VCCOUT
VCCIN
YZH Package
16-Pin DSBGA
Top View
VCCIN
20
19
18
17
16
VOUT+
2
14
VOUT+
GAIN
3
13
VOUT+
AGND
4
12
VOUT–
SDd
5
11
VOUT–
6
7
8
9
10
PGND
VCCFB
PGND
VOUT+
IN+
15
IN–
1
SDb
VDD
VCCOUT
SW
PGND
A1
A2
A3
A4
GAIN
VCCFB
VDD
B1
B2
B3
B4
VOUT–
PGND
SDd
AGND
C1
C2
C3
C4
PGND
IN+
IN–
SDb
D1
D2
D3
D4
Pin Functions
PIN
I/O
DESCRIPTION
NAME
VQFN
DSBGA
AGND
4
C4
–
Analog ground – connect all GND pins together
GAIN
3
B2
I
Gain selection pin
IN+
8
D2
I
Positive audio input
IN–
7
D3
I
Negative audio input
9, 10, 20
D1, C2, A4
–
Power ground – connect all GND pins together
SDb
6
D4
I
Shutdown terminal for the Boost Converter
SDd
5
C3
I
Shutdown terminal for the Class D Amplifier
SW
18, 19
A3
–
Boost and rectifying switch input
Die Pad
N/A
P
Solder the thermal pad on the bottom of the QFN package to the GND plane of the PCB. It is
required for mechanical stability and enhances thermal performance.
VCCFB
2
B3
I
Voltage feedback
VC CIN
16
A1
–
Class-D audio power amplifier voltage supply – connect to VCCOUT
VCCOUT
17
A2
–
Boost converter output – connect to VCCIN
VDD
1
B4
–
Supply voltage
VOUT+
13, 14, 15
B1
O
Positive audio output
VOUT–
11, 12
C1
O
Negative audio output
PGND
Thermal Pad
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VDD
Supply voltage
–0.3
6
V
VI
Input voltage, Vi: SDb, SDd, IN+, IN–, VCCFB
–0.3
VDD + 0.3
V
Continuous total power dissipation
See Dissipation Ratings
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
VDD
Supply voltage
VIH
High-level input voltage
SDb, SDd
VIL
Low-level input voltage
SDb, SDd
| IIH |
High-level input current
SDb = SDd = 5.8 V, VDD = 5.5 V, VCC = 5.5 V
| IIL|
Low-level input current
SDb = SDd = -0.3 V, VDD = 5.5 V, VCC = 5.5 V
TA
Operating free-air temperature
MIN
MAX
1.8
5.5
1.3
UNIT
V
V
0.35
V
1
μA
20
μA
85
°C
–40
7.4 Thermal Information
TPA2013D1
THERMAL METRIC
(1)
RGP (VQFN)
YZH (DSBGA)
20 PINS
16 PINS
UNIT
34
70.6
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
33.4
0.3
°C/W
RθJB
Junction-to-board thermal resistance
10.5
15
°C/W
ψJT
Junction-to-top characterization parameter
0.4
1.8
°C/W
ψJB
Junction-to-board characterization parameter
10.5
14.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.1
—
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 DC Characteristics
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Class-D audio power amplifier
voltage supply range, VCCIN
VCC
ISD
Shutdown quiescent current
TYP
3
MAX
5.5
SDd = SDb = 0 V, VDD = 1.8 V, RL = 8 Ω
0.04
1.5
SDd = SDb = 0 V, VDD = 3.6 V, RL = 8 Ω
0.04
1.5
SDd = SDb = 0 V, VDD = 4.5 V, RL = 8 Ω
0.02
1.5
SDd = SDb = 0.35 V, VDD = 1.8 V, RL = 8 Ω
0.03
1.5
SDd = SDb = 0.35 V, VDD = 3.6 V, RL = 8 Ω
0.03
1.5
SDd = SDb = 0.35 V, VDD = 4.5 V, RL = 8 Ω
0.02
1.5
IDD
Boost converter quiescent
current
SDd = 0 V, SDb = 1.3 V, VDD = 3.6 V, VCC = 5.5 V, No
Load, No Filter
1.3
ICC
Class D amplifier quiescent
current
VDD = 3.6, Vcc = 5.5 V, No Load, No Filter
4.3
6
VDD = 4.5, Vcc = 5.5 V, No Load, No Filter
3.6
6
SDd = SDb = 1.3 V, VDD = 3.6 V, Vcc = 5.5 V, No Load,
No Filter
16.5
23
IDD
Boost converter and audio
power amplifier quiescent
current, Class D (1)
SDd = SDb = 1.3V, VDD = 4.5 V, Vcc = 5.5 V, No Load,
No Filter
11
18.5
f
UVLO
GAIN
PORD
(1)
UNIT
V
μA
mA
mA
mA
Boost converter switching
frequency
500
600
700
kHz
Class D switching frequency
250
300
350
kHz
1.7
V
0
0.35
V
0.8
1
V
Under voltage lockout
Gain input low level
Gain = 2 V/V (6 dB)
Gain input mid level
Gain = 6 V/V (15.5 dB) (floating input)
Gain input high level
Gain = 10 V/V (20 dB)
0.7
1.35
Class D Power on reset ON
threshold
V
2.8
V
IDD is calculated using IDD = (ICC× VCC)/(VDD×η), where ICC is the class D amplifier quiescent current; η = 40%, which is the boost
converter efficiency when class D amplifier has no load. To achieve the minimal 40% η, it is recommended to use the suggested
inductors in table 4 and to follow the layout guidelines.
7.6 Boost Converter DC Characteristics
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
Output voltage range
VFB
Feedback voltage
IOL
Output current limit, Boost_max
RON_PB
PMOS switch resistance
220
mΩ
RON_NB
NMOS resistance
170
mΩ
IL
3
MAX
VCC
Line regulation
No Load, 1.8 V < VDD < 5.2
V, VCC = 5.5 V
Load regulation
VDD = 3.6 V, 0 < IL < 500 mA,
VCC = 5.5 V
Start-up current limit, Boost
5.5
V
mV
490
500
510
1300
1500
1700
mA
3
mV/V
30
mV/A
0.4×IBoost
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7.7 Class D Amplifier DC Characteristics
TA = 25°C (unless otherwise noted)
PARAMETER
CMR
CMRR
VOO
TEST CONDITIONS
Input common mode range
MIN
Output offset voltage
Class-D
0.5
2.2
Vin = ±100 mV, VDD = 2.5 V, VCC = 3.6 V, RL = 8 Ω
0.5
2.8
Vin = ±100 mV, VDD = 3.6 V, VCC = 5.5 V, RL = 8 Ω
0.5
4.7
–75
1
6
VCC= 3.6 V, Av = 6 V/V, IN+ = IN– = Vref, RL = 8 Ω
1
6
VCC= 3.6 V, Av = 10 V/V, IN+ = IN– = Vref, RL = 8 Ω
1
6
1
6
RDS(on)
RDS(on)
AV
Input Impedance
Gain = 2 V/V (6 dB)
32
Gain = 6 V/V (15.5 dB)
15
Gain = 10 V/V (20 dB)
9.5
OUTP High-side FET On-state
series resistance
OUTP Low-side FET On-state
series resistance
OUTN High-side FET On-state
series resistance
UNIT
V
dB
VCC = 3.6 V, Av = 2 V/V, IN+ = IN– = Vref, RL = 8 Ω
VCC = 5.5 V, Av = 2 V/V, IN+ = IN– = Vref, RL = 8 Ω
Rin
MAX
Vin = ±100 mV, VDD = 1.8 V, VCC = 3 V, RL = 8 Ω
RL = 8 Ω, Vicm = 0.5 and Vicm = VCC – 0.8, differential
inputs shorted
Input common mode rejection
TYP
mV
kΩ
0.36
0.36
Ω
IOUTx = –300 mA; VCC = 3.6 V
0.36
OUTN Low-side FET On-state
series resistance
0.36
Low Gain
GAIN ≤ 0.35 V
1.8
Mid Gain
GAIN = 0.8 V
5.7
High Gain
GAIN ≥ 1.35 V
9.5
2
2.2
V/V
6
6.3
V/V
10
10.5
V/V
7.8 AC Characteristics
TA = 25°C, VDD = 3.6 V, RL = 8 Ω, L = 4.7 μH (unless otherwise noted)
PARAMETER
tSTART
η
Start up time
Efficiency
Thermal Shutdown
6
TEST CONDITIONS
1.8 V ≤ VDD ≤ 5.5 V, CIN ≤ 1 μF
MIN
TYP
7.5
THD+N = 1%, VCC = 5.5 V, VDD = 3.6 V,
RL= 8 Ω, Pout = 1.7 W, Cboost= 47μF
85%
THD+N = 1%, VCC = 5.5 V, VDD = 4.2 V,
RL = 8 Ω, Pout = 1.7 W
87.5%
Threshold
150
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MAX
UNIT
ms
°C
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SLOS520A – AUGUST 2007 – REVISED MARCH 2016
7.9 Class D Amplifier AC Characteristics
TA = 25°C, VDD = 3.6V, RL = 8 Ω, L = 4.7μH (unless otherwise noted)
PARAMETER
KSVR
Class-D
THD+N
Class-D
Vn
Class-D
PO
TEST CONDITIONS
Output referred power supply
rejection ratio
Total harmonic distortion + noise
MIN
TYP
VDD = 3.6 V, VCC = 5.5V, 200 mVPP ripple,
f = 217 Hz
–95
f = 1 kHz, Po = 1.7 W, VCC = 5.5 V
1%
UNIT
dB
f = 1 kHz, Po = 1.2 W, VCC = 4.5 V
1%
f = 1 kHz, Po = 2.2 W, VCC = 5.5 V
10%
f = 1 kHz, Po = 1 W, VCC = 5.5 V
0.1%
Output integrated noise floor
Av = 6 dB (2V/V)
31
Output integrated noise floor Aweighted
Av = 6 dB (2V/V)
23
THD+N = 10%, VCC = 5.5 V, VDD = 3.6 V , RL = 8
Ω
2.2
THD+N = 1%, VCC = 5.5 V, VDD = 3.6 V , RL = 8 Ω
1.7
THD+N = 1%, VCC = 4.5 V, VDD = 3.6 V , RL = 8 Ω
1.2
THD+N = 10%, VCC = 5.5 V, VDD = 3.6 V , RL = 4
Ω
2.7
THD+N = 1%, VCC = 5.5 V, VDD = 3.6 V , RL = 4 Ω
2.2
THD+N = 1%, VCC = 4.5 V, VDD = 3.6 V , RL = 4 Ω
1.9
Maximum output power
MAX
μVrms
W
7.10 Dissipation Ratings
(1)
PACKAGE
TA ≤ 25°C
DERATING FACTOR (1)
16 ball WCSP
1.5 W
20 pin QFN
2.5 W
TA = 70°C
TA = 85°C
12.4 mW/°C
1W
0.8 W
20.1 mW/°C
1.6 W
1.3 W
Derating factor measured with JEDEC High K board.
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100
100
80
80
Efficiency − %
Efficiency − %
7.11 Typical Characteristics
60
40
VDD = 3.6 V
VDD = 2.5 V
VDD = 4.2 V
VDD = 1.8 V
Gain = 2 V/V
RL = 8 Ω + 33 µH
VCC = 4.5 V
20
0
0.0
0.5
1.0
60
VDD = 3.6 V
VDD = 4.2 V
40
Gain = 2 V/V
RL = 8 Ω + 33 µH
VCC = 5.5 V
20
0
0.0
1.5
PO − Output Power − W
0.5
1.5
2.0
G002
Figure 2. Efficiency vs Output Power
0.6
Gain = 2 V/V
RL = 8 Ω + 33 µH
VCC = 4.5 V
PD − Power Dissipation − W
0.6
PD − Power Dissipation − W
1.0
PO − Output Power − W
G001
Figure 1. Efficiency vs Output Power
0.5
VDD = 2.5 V
VDD = 1.8 V
VDD = 3.6 V
0.4
VDD = 2.5 V
0.3
VDD = 1.8 V
0.2
0.1
0.5
Gain = 2 V/V
RL = 8 Ω + 33 µH
VCC = 5.5 V
VDD = 2.5 V
0.4
0.3
VDD = 3.6 V
VDD = 1.8 V
0.2
0.1
VDD = 4.2 V
VDD = 4.2 V
0.0
0.0
0.5
1.0
0.0
0.0
1.5
PO − Output Power − W
VDD = 3.6 V
IDD − Supply Current − A
IDD − Supply Current − A
2.0
G004
1.2
Gain = 2 V/V
RL = 8 Ω + 33 µH
VCC = 4.5 V
VDD = 2.5 V
0.6
VDD = 1.8 V
0.4
0.2
0.5
1.0
1.5
PO − Output Power − W
1.0
0.8
0.6
Gain = 2 V/V
VDD = 3.6 V
RL = 8 Ω + 33 µH
VCC = 5.5 V
VDD = 2.5 V
VDD = 1.8 V
0.4
0.2
VDD = 4.2 V
VDD = 4.2 V
0.0
0.0
0.5
1.0
1.5
PO − Output Power − W
G005
Figure 5. Supply Current vs Output Power
8
1.5
Figure 4. Power Dissipation vs Output Power
1.0
0.0
0.0
1.0
PO − Output Power − W
G003
Figure 3. Power Dissipation vs Output Power
0.8
0.5
2.0
G006
Figure 6. Supply Current vs Output Power
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Typical Characteristics (continued)
2.5
2.0
L = 6.2 µH
L = 3.3 µH
Gain = 2 V/V
RL = 8 Ω + 33 µH
THD = 1%
VCC = 4.5 V
PO − Output Power − W
PO − Output Power − W
2.5
1.5
1.0
L = 4.7 µH
L = 2.2 µH
0.5
0.0
1.8
2.2
2.6
3.0
3.4
3.8
4.2
VDD − Supply Voltage − V
L = 6.2 µH
2.0
1.5
L = 3.3 µH
1.0
L = 4.7 µH
Gain = 2 V/V
RL = 8 Ω + 33 µH
THD = 1%
VCC = 5.5 V
0.5
0.0
1.8
4.6
2.2
2.6
3.0
3.4
3.8
4.2
4.6
5.0
5.4
VDD − Supply Voltage − V
G007
Figure 7. Output Power vs Supply Voltage
G008
Figure 8. Output Power vs Supply Voltage
2.5
2.5
2.0
L = 3.3 µH
L = 6.2 µH
PO − Output Power − W
PO − Output Power − W
L = 6.2 µH
1.5
1.0
L = 2.2 µH
L = 4.7 µH
Gain = 2 V/V
RL = 8 Ω + 33 µH
THD = 10%
VCC = 4.5 V
0.5
0.0
1.8
2.2
2.6
3.0
3.4
3.8
4.2
VDD − Supply Voltage − V
2.0
L = 3.3 µH
1.5
L = 4.7 µH
1.0
Gain = 2 V/V
RL = 8 Ω + 33 µH
THD = 10%
VCC = 5.5 V
0.5
0.0
1.8
4.6
2.6
3.0
3.4
3.8
4.2
4.6
5.0
5.4
VDD − Supply Voltage − V
G009
Figure 9. Output Power vs Supply Voltage
G010
Figure 10. Output Power vs Supply Voltage
3.0
3.0
f = 1 kHz
Gain = 2 V/V
VCC = 4.5 V
2.0
1.5
THD = 10%
1.0
0.5
f = 1 kHz
Gain = 2 V/V
VCC = 5.5 V
2.5
PO − Output Power − W
2.5
PO − Output Power − W
2.2
2.0
1.5
THD = 10%
1.0
0.5
THD = 1%
0.0
THD = 1%
0.0
4
8
12
16
20
24
28
RL − Load Resistance − Ω
32
4
G011
Figure 11. Output Power vs Load
8
12
16
20
24
28
32
RL − Load Resistance − Ω
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Figure 12. Output Power vs Load
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Typical Characteristics (continued)
100
100
Gain = 2 V/V
RL = 8 Ω + 33 µH
VCC = 4.5 V
10
Gain = 2 V/V
RL = 8 Ω + 33 µH
VCC = 5.5 V
10
VDD = 1.8 V
THD+N − %
THD+N − %
VDD = 1.8 V
VDD = 2.5 V
1
VDD = 3.6 V
0.1
VDD = 2.5 V
VDD = 3.6 V
VDD = 4.2 V
1
0.1
VDD = 4.2 V
0.01
0.01
0.1
1
0.01
0.01
3
PO − Output Power − W
G013
Figure 13. Total Harmonic distortion + Noise vs Output
Power
1
3
G014
Figure 14. Total Harmonic Distortion + Noise vs Output
Power
100
10
Gain = 2 V/V
RL = 4 Ω + 33 µH
VCC = 5.5 V
10
VDD = 2.5 V
VDD = 3.6 V
1
Gain = 2 V/V
RL = 8 Ω + 33 µH
VCC = 4.5 V
VDD = 1.8 V
1
VDD = 1.8 V
THD+N − %
THD+N − %
0.1
PO − Output Power − W
VDD = 4.2 V
0.1
PO = 0.2 W
0.1
0.01
PO = 0.075 W
PO = 0.025 W
0.01
0.01
0.001
0.1
1
5
PO − Output Power − W
20
10k
20k
G016
Figure 16. Total Harmonic Distortion + Noise vs Frequency
10
10
Gain = 2 V/V
RL = 8 Ω + 33 µH
VCC = 4.5 V
VDD = 3.6 V
PO = 1 W
0.1
0.01
Gain = 2 V/V
RL = 8 Ω + 33 µH
VCC = 5.5 V
VDD = 1.8 V
1
THD+N − %
1
PO = 0.025 W
0.1
0.01
PO = 0.05 W
PO = 0.075 W
PO = 0.2 W
PO = 0.25 W
0.001
0.001
20
100
1k
f − Frequency − Hz
10k
20k
20
100
1k
f − Frequency − Hz
G017
Figure 17. Total Harmonic Distortion + Noise vs Frequency
10
1k
f − Frequency − Hz
G015
Figure 15. Total Harmonic Distortion + Noise vs Output
Power
THD+N − %
100
10k
20k
G018
Figure 18. Total Harmonic Distortion + Noise vs Frequency
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Typical Characteristics (continued)
10
10
Gain = 2 V/V
RL = 8 Ω + 33 µH
VCC = 5.5 V
VDD = 3.6 V
PO = 1 W
1
THD+N − %
THD+N − %
1
0.1
0.01
Gain = 2 V/V
PO = 250 mW
RL = 4 Ω + 33 µH
VCC = 4.5 V
VDD = 3.6 V
0.1
VDD = 2.5 V
0.01
PO = 0.05 W
PO = 0.25 W
0.001
100
1k
10k
f − Frequency − Hz
20k
20
100
1k
10k
20k
f − Frequency − Hz
G019
Figure 19. Total Harmonic Distortion + Noise vs Frequency
G020
Figure 20. Total Harmonic Distortion + Noise vs Frequency
10
0
Gain = 2 V/V
PO = 250 mW
RL = 4 Ω + 33 µH
VCC = 5.5 V
1
−20
VDD = 3.6 V
PSRR − dB
THD+N − %
VDD = 4.2 V
0.001
20
VDD = 1.8 V
VDD = 4.2 V
0.1
Gain = 2 V/V
RL = 8 Ω + 33 µH
VCC = 4.5 V
−40
−60
VDD = 1.8 V
VDD = 4.2 V
VDD = 3.6 V
−80
VDD = 2.5 V
0.01
−100
VDD = 1.8 V
VDD = 2.5 V
0.001
20
100
1k
10k
f − Frequency − Hz
−120
20
20k
G021
20k
G022
0
Gain = 2 V/V
RL = 8 Ω + 33 µH
VCC = 5.5 V
−20
CMRR − dB
−40
VDD = 1.8 V
−60
VDD = 3.6 V
VDD = 2.5 V
−80
−100
Gain = 2 V/V
RL = 8 Ω
VCC = 4.5 V
−40
VDD = 1.8 V
VDD = 2.5 V
−60
−80
VDD = 4.2 V
−100
VDD = 3.6 V
VDD = 4.2 V
−120
20
10k
Figure 22. Power Supply Rejection Ratio vs Frequency
0
PSRR − dB
1k
f − Frequency − Hz
Figure 21. Total Harmonic Distortion + Noise vs Frequency
−20
100
100
1k
f − Frequency − Hz
10k
20k
−120
20
1k
10k
20k
f − Frequency − Hz
G023
Figure 23. Power Supply Rejection Ratio vs Frequency
100
G024
Figure 24. Common-Mode Rejection Ratio vs Frequency
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Typical Characteristics (continued)
100
0
Gain = 2 V/V
RL = 8 Ω
VCC = 5.5 V
CMRR − dB
−20
95
90
Boost Efficiency − %
−10
−30
−40
VDD = 3.6 V
−50
VDD = 1.8 V
VDD = 2.5 V
VDD = 4.2 V
−60
85
VDD = 3.6 V
80
75
70
VDD = 1.8 V
65
−70
60
−80
55
−90
20
50
0.01
100
1k
10k
20k
f − Frequency − Hz
VCC = 4.5 V
G025
VCC = 4.5 V
90
Boost Efficiency − %
Boost Efficiency − %
90
85
80
VDD = 3.6 V
75
VDD = 4.2 V
VDD = 2.5 V
70
VDD = 1.8 V
65
60
VCC = 5.5 V
80
70
60
55
VCC = 5.5 V
50
0.01
0.1
50
1.8
1
IO − Output Current − A
ICC = 250 mA
L = 4.7 µH
2.2
2.6
3.0
3.4
3.8
4.2
VDD − Supply Voltage − V
G027
Figure 27. Boost Efficiency vs Output Current
G028
Figure 28. Boost Efficiency vs Supply Voltage
6
1.4
L = 4.7 µH
5
VCC
4
1.0
0.8
V − Voltage − V
IOM − Max. Continuous Output Current − A
G026
100
95
VCC = 4.5 V
0.6
VCC = 5.5 V
0.4
3
SDb, SDd
2
1
OUT
0
0.2
Start Time 7.5 ms
−1
−2
2.2
2.6
3.0
3.4
VDD − Supply Voltage (Boost) − V
3.8
4.2
0
2
G029
Figure 29. Maximum Continuous Output Current vs Supply
Voltage (Boost)
12
1
Figure 26. Boost Efficiency vs Output Current
100
0.0
1.8
0.1
IO − Output Current − A
Figure 25. Common-Mode Rejection Ratio vs Frequency
1.2
VDD = 4.2 V
VDD = 2.5 V
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4
6
8
10
12
14
t − Time − ms
16
18
20
G030
Figure 30. Start-Up Time
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8 Parameter Measurement Information
All parameters are measured according to the conditions described in Specifications. Figure 31 shows the setup
used for the typical characteristics of the test device.
TPA2013D1
CI
+
Measurement
Output
–
IN+
OUT+
Load
CI
IN
VDD
+
OUT–
30 kHz
Low-Pass
Filter
+
Measurement
Input
–
GND
1 mF
VDD
–
(1)
CI was shorted for any common-mode input voltage measurement. All other measurements were taken with a 1-μF CI
(unless otherwise noted).
(2)
A 33-μH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.
(3)
The 30-kHz low-pass filter is required, even if the analyzer has an internal low-pass filter. An RC low-pass filter (100Ω, 47-nF) is used on each output for the data sheet graphs.
(4)
L = 4.7 μH is used for the boost converter unless otherwise noted.
Figure 31. Test Set-Up for Graphs
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9 Detailed Description
9.1 Overview
The TPA2013D1 is a high efficiency Class D audio power amplifier with an integrated boost converter. It drives
up to 2.7 W (10% THD+N) into a 4-Ω speaker. The built-in boost converter generates the voltage rail for the
Class-D amplifier. The TPA2013D1 has an integrated low-pass filter to improve RF rejection and reduce out-ofband noise, increasing the signal-to-noise ratio (SNR).
9.2 Functional Block Diagram
SW
BG Control
VCCOUT
AntiRinging
VDD
VCCOUT
Vmax
Control
Gate
Control
PGND
VCCFB
Regulator
SDb
Biases, Control,
and
References
SDd
Vref
Internal
Oscillator
AGND
VCCIN
GAIN
IN–
IN+
Res.
Array
PWM
and
Level
Shifter
VOUT+
H-Bridge
VOUT–
PGND
AGND
AGND
PGND
9.3 Feature Description
9.3.1 Fully Differential Amplifier
The TPA2013D1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier
consists of a differential amplifier with common-mode feedback. The differential amplifier ensures that the
amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The
common-mode feedback ensures that the common-mode voltage at the output is biased around VCC/2 regardless
of the common-mode voltage at the input. The fully differential TPA2013D1 can still be used with a single-ended
input; however, the TPA2013D1 must be used with differential inputs when in a noisy environment, like a
wireless handset, to ensure maximum noise rejection.
14
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Feature Description (continued)
9.3.1.1 Advantages of Fully Differential Amplifiers
• Input-coupling capacitors not required:
– The fully differential amplifier allows the inputs to be biased at voltage other than mid-supply. The inputs of
the TPA2013D1 can be biased anywhere within the common mode input voltage range listed in the
Recommended Operating Conditions. If the inputs are biased outside of that range, input-coupling
capacitors are required.
• Midsupply bypass capacitor, C(BYPASS), not required:
– The fully differential amplifier does not require a bypass capacitor. Any shift in the midsupply affects both
positive and negative channels equally and cancels at the differential output.
• Better RF-immunity:
– GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The
transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signal
better than the typical audio amplifier.
9.3.2 Class-D Amplifier
The TPA2013D1 is a high efficiency Class-D audio power amplifier with an integrated boost converter able to
drive up to 2.7 W (10% THD+N) into a 4-Ω speaker with 85% typical efficiency, the device helps extend battery
life when playing audio. It is available in 2.275-mm × 2.275-mm 16-ball WCSP and 4-mm × 4-mm 20-lead QFN
packages. The device has three selectable gain settings of 2 V/V, 6 V/V and 10 V/V.
9.3.3 Boost Converter
The TPA2013D1 consists of a boost converter and a Class-D amplifier. The boost converter takes a low supply
voltage, VDD, and increases it to a higher output voltage, VCC.
The two main passive components necessary for the boost converter are the boost inductor and the boost
capacitor. The boost inductor stores current, and the boost capacitor stores charge. As the Class-D amplifier
depletes the charge in the boost capacitor, the boost inductor charges it back up with the stored current. The
cycle of charge and discharge occurs at a frequency of fboost.
The TPA2013D1 allows a range of VCC voltages, including setting VCC lower than VDD.
9.3.4 Operation With DACs and CODECs
When using switching amplifiers with CODECs and DACs, sometimes there is an increase in the output noise
floor from the audio amplifier. This occurs when mixing of the output frequencies of the CODEC and DAC with
the switching frequencies of the audio amplifier input stage. The noise increase can be solved by placing a lowpass filter between the CODEC and DAC and audio amplifier. This filters off the high frequencies that cause the
problem and allow proper performance.
The TPA2013D1 has a two pole low-pass filter at the inputs. The cutoff frequency of the filter is set to
approximately 100 kHz. The integrated low-pass filter of the TPA2013D1 eliminates the need for additional
external filtering components. A properly designed additional low-pass filter may be added without altering the
performance of the device.
If driving the TPA2013D1 input with 4th-order or higher ΔΣ DACs or CODECs, add an R-C low-pass filter at each
of the audio inputs (IN+ and IN–) of the TPA2013D1 to ensure best performance. The recommended resistor
value is 100 Ω and the capacitor value of 47 nF.
9.3.5 Filter-Free Operation and Ferrite Bead Filters
A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter and the
frequency sensitive circuit is greater than 1 MHz. This filter functions well for circuits that just have to pass FCC
and CE because FCC and CE only test radiated emissions greater than 30 MHz. When choosing a ferrite bead,
choose one with high impedance at high frequencies, and very low impedance at low frequencies. In addition,
select a ferrite bead with adequate current rating to prevent distortion of the output signal.
Use an LC output filter if there are low-frequency, (< 1 MHz) EMI-sensitive circuits and/or there are long leads
from amplifier to speaker.
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Feature Description (continued)
Figure 32 shows a typical ferrite bead output filters.
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 32. Typical Ferrite Chip Bead Filter
Table 1. Suggested Chip Ferrite Bead
LOAD
VENDOR
PART NUMBER
SIZE
8Ω
Murata
BLM18EG121SN1
0603
4Ω
TDK
MPZ2012S101A
0805
9.3.6 Fixed Gain Settings
The TPA2013D1 has 3 selectable fixed-gains: 6 dB, 15.5 dB, and 20 dB. Connect the GAIN pin as shown in
Table 2.
Table 2. Amplifier Fixed-Gain
CONNECT GAIN PIN TO
AMPLIFIER GAIN
GND
6 dB
No connection (Floating)
15.5 dB
VBAT
20 dB
9.4 Device Functional Modes
9.4.1 Boost Converter Mode
The TPA2013D1 has 4 boost converter operation modes as shown in Table 3.
Table 3. Boost Converter Mode Condition
CASE
OUTPUT CURRENT
MODE OF OPERATION
VDD < VCC
Low
Continuous (fixed frequency)
VDD < VCC
High
Continuous (fixed frequency)
VDD ≥ VCC
Low
Discontinuous (variable frequency)
VDD ≥ VCC
High
Discontinuous (variable frequency)
9.4.2 Shutdown Mode
The TPA2013D1 amplifier can be put in shutdown mode when asserting SDd pin to a logic LOW. While in
shutdown mode, the device output stage is turned off and the current consumption is very low. The boost
converter can be put in shutdown mode when asserting SDb pin to a logic LOW. While in shutdown Mode, the
boost converter is turned off.
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Table 4. Device Configuration
SDb
SDd
BOOST
CONVERTE
R
CLASS D
AMPLIFIER
low
low
OFF
OFF
Device is in shutdown mode Iq ≤ 1 μA
low
high
OFF
ON
Boost converter is off. Class-D Audio Power Amplifier (APA) can be driven by an
external pass transistor connected to the battery.
high
low
ON
OFF
Class-D APA is off. Boost Converter is on and can be used to drive an external device.
high
high
ON
ON
Boost converter and Class-D APA are on. Normal operation. Boost converter can be
used to drive an external device in parallel to the Class-D APA within the limits of the
boost converter output current.
COMMENTS
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
These typical connection diagrams highlight the required external components and system level connections for
proper operation of the device. Each of these configurations can be realized using the Evaluation Modules
(EVMs) for the device. These flexible modules allow full evaluation of the device in the most common modes of
operation. Any design variation can be supported by TI through schematic and layout reviews. Visit e2e.ti.com for
design assistance, and join the audio amplifier discussion forum for additional information.
10.2 Typical Applications
10.2.1 TPA2013D1 With Differential Input Signal
R1
50 kΩ
R2
500 kΩ
22 mF
1 mF
2.2 to 6.2 mH
To Battery
10 mF
VDD
SW VCCFB
VCCIN
VCCOUT
CIN
IN–
Differential
Input
1 mF
VOUT+
IN+
CIN
Gain (VCC/Float/GND)
GPIO
TPA2013D1
VOUT–
GAIN
ShutDown Boost
SDb
ShutDown ClassD
SDd
AGND
PGND
Figure 33. Typical Application Schematic With Differential Input Signals
10.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 5.
Table 5. Design Parameters
DESIGN PARAMETERS
Power Supply
Enable Inputs
Speaker
18
EXAMPLE VALUE
3.6 V
High > 1.3 V
Low < 0.6 V
8Ω
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10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Setting the Boost Voltage
Use Equation 1 to determine the value of R1 for a given VCC. The maximum recommended value for VCC is
5.5 V. The typical value of the VCCFB pin is 500 mV. The current through the resistor divider should be about 100
times greater than the current into the VCCFB pin, typically 0.01 μA. Based on those two values, the
recommended value of R2 is 500 kΩ. VCC must be greater than 3 V and less than or equal to 5.5 V.
æ 0.5 ´ (R1 + R2) ö
VCC = ç
÷
R1
è
ø
(1)
10.2.1.2.2 Inductor Selection
10.2.1.2.2.1 Surface Mount Inductors
Working inductance decreases as inductor current increases. If the drop in working inductance is severe enough,
it may cause the boost converter to become unstable, or cause the TPA2013D1 to reach its current limit at a
lower output power than expected. Inductor vendors specify currents at which inductor values decrease by a
specific percentage. This can vary by 10% to 35%. Inductance is also affected by DC current and temperature.
10.2.1.2.2.2 TPA2013D1 Inductor Equations
Inductor current rating is determined by the requirements of the load. The inductance is determined by two
factors: the minimum value required for stability and the maximum ripple current permitted in the application.
Use Equation 2 to determine the required current rating. Equation 2 shows the approximate relationship between
the average inductor current, IL, to the load current, load voltage, and input voltage (ICC, VCC, and VDD,
respectively). Insert ICC, VCC, and VDD into Equation 2 to solve for IL. The inductor must maintain at least 90% of
its initial inductance value at this current.
æ
ö
VCC
IL = ICC ´ ç
÷
è VDD ´ 0.8 ø
(2)
The minimum working inductance is 2.2 μH. A lower value may cause instability.
Ripple current, ΔIL, is peak-to-peak variation in inductor current. Smaller ripple current reduces core losses in the
inductor as well as the potential for EMI. Use Equation 3 to determine the value of the inductor, L. Equation 3
shows the relationship between inductance L, VDD, VCC, the switching frequency, fboost, and ΔIL. Insert the
maximum acceptable ripple current into Equation 3 to solve for L.
V
´ (VCC - VDD )
L = DD
DIL ´ fboost ´ VCC
(3)
ΔIL is inversely proportional to L. Minimize ΔIL as much as is necessary for a specific application. Increase the
inductance to reduce the ripple current.
NOTE
Making the inductance too large prevents the boost converter from responding to fast load
changes properly. Typical inductor values for the TPA2013D1 are 4.7 μH to 6.8 μH.
Select an inductor with a small DC resistance, DCR. DCR reduces the output power due to the voltage drop
across the inductor.
10.2.1.2.3 Capacitor Selection
10.2.1.2.3.1 Surface Mount Capacitors
Temperature and applied DC voltage influence the actual capacitance of high-K materials.
Table 6 shows the relationship between the different types of high-K materials and their associated tolerances,
temperature coefficients, and temperature ranges. Notice that a capacitor made with X5R material can lose up to
15% of its capacitance within its working temperature range.
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High-K material is very sensitive to applied DC voltage. X5R capacitors can have losses ranging from 15 to 45%
of their initial capacitance with only half of their DC-rated voltage applied. For example, if 5 Vdc is applied to a
10-V, 1-μF X5R capacitor, the measured capacitance at that point may show 0.85 μF, 0.55 μF, or somewhere in
between. Y5V capacitors have losses that can reach or exceed 50% to 75% of their rated value.
In an application, the working capacitance of components made with high-K materials is generally much lower
than nominal capacitance. A worst-case result with a typical X5R material might be –10% tolerance, –15%
temperature effect, and –45% DC-voltage effect at 50% of the rated voltage. This particular case would result in
a working capacitance of 42% (0.9 × 0.85 × 0.55) of the nominal value.
Select high-K ceramic capacitors according to the following rules:
1. Use capacitors made of materials with temperature coefficients of X5R, X7R, or better.
2. Use capacitors with DC-voltage ratings of at least twice the application voltage. Use minimum 10-V
capacitors for the TPA2013D1.
3. Choose a capacitance value at least twice the nominal value calculated for the application. Multiply the
nominal value by a factor of 2 for safety. If a 10-μF capacitor is required, use 20 μF.
The preceding rules and recommendations apply to capacitors used in connection with the TPA2013D1. The
TPA2013D1 cannot meet its performance specifications if the rules and recommendations are not followed.
Table 6. Typical Tolerance and Temperature Coefficient of Capacitance by Material
MATERIAL
COG/NPO
X7R
X5R
Typical Tolerance
±5%
±10%
80/–20%
Temperature Coefficient
±30ppm
±15%
22/–82%
Temperature Range, °C
–55/125°C
–55/125°C
–30/85°C
10.2.1.2.3.2 TPA2013D1 Capacitor Equations
The value of the boost capacitor is determined by the minimum value of working capacitance required for stability
and the maximum voltage ripple allowed on VCC in the application. The minimum value of working capacitance is
10 μF. Do not use any component with a working capacitance less than 10 μF.
For X5R or X7R ceramic capacitors, Equation 4 shows the relationship between the boost capacitance, C, to
load current, load voltage, ripple voltage, input voltage, and switching frequency (ICC, VCC, ΔV, VDD, fboost
respectively). Insert the maximum allowed ripple voltage into Equation 4 to solve for C. A factor of 2 is included
to implement the rules and specifications listed earlier.
C=2 ´
ICC ´
(VCC
- VDD )
DV ´ fboost ´ VCC
(4)
For aluminum or tantalum capacitors, Equation 5 shows the relationship between the boost capacitance, C, to
load current, load voltage, ripple voltage, input voltage, and switching frequency (ICC, VCC, ΔV, VDD, fboost
respectively). Insert the maximum allowed ripple voltage into Equation 5 to solve for C. Solve this equation
assuming ESR is zero.
C=
ICC ´
(VCC
- VDD )
DV ´ fboost ´ VCC
(5)
Capacitance of aluminum and tantalum capacitors is normally not sensitive to applied voltage, so there is no
factor of 2 included in Equation 5. However, the ESR in aluminum and tantalum capacitors can be significant.
Choose an aluminum or tantalum capacitor with ESR around 30 mΩ. For best perfornamce using of tantalum
capacitor, use at least a 10-V rating.
NOTE
Tantalum capacitors must generally be used at voltages of half their ratings or less.
10.2.1.2.4 Recommended Inductor and Capacitor Values by Application
Use Table 7 as a guide for determining the proper inductor and capacitor values.
20
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Table 7. Recommended Values
CLASS-D
OUTPUT POWER
(W) (1)
CLASS-D
LOAD
(Ω)
MINIMUM
VDD
(V)
REQUIRED
VCC
(V)
MAX IL
(A)
L
(μH)
INDUCTOR
VENDOR
PART NUMBERS
MAX ΔV
(mVpp)
3.3
1
8
3
4.3
0.70
Toko DE2812C
Coilcraft DO3314
Murata LQH3NPN3R3NG0
1.6
8
3
5.5
1.13
2
4
3
4.6
1.53
Murata LQH55PN3R3NR0
Toko DE4514C
2.3
4
1.8
5.5
2
30
30
Murata GRM32ER71A226KE20L
Taiyo Yuden LMK316BJ226ML-T
33
30
6.2
(1)
(2)
Kemet C1206C106K8PACTU
Murata GRM32ER61A106KA01B
Taiyo Yuden LMK316BJ106ML-T
22
3.3
Sumida
CDRH5D28NP-6R2NC
CAPACITOR VENDOR
PART NUMBERS
10
4.7
Murata LQH32PN4R7NN0
Toko DE4514C
Coilcraft LPS4018-472
C (2)
(μF)
TDK C4532X5R1A336M
47
30
Murata GRM32ER61A476KE20L
Taiyo Yuden LMK325BJ476MM-T
All power levels are calculated at 1% THD unless otherwise noted
All values listed are for ceramic capacitors. The correction factor of 2 is included in the values.
10.2.1.2.5 Components Location and Selection
10.2.1.2.5.1 Decoupling Capacitors
The TPA2013D1 is a high-performance Class-D audio amplifier that requires adequate power-supply decoupling
to ensure the efficiency is high and total harmonic distortion (THD) is low. Place a low equivalent-seriesresistance (ESR) ceramic capacitor, typically 1 μF, as close as possible to the device VDD lead. This choice of
capacitor and placement helps with higher frequency transients, spikes, or digital hash on the line. Additionally,
placing this decoupling capacitor close to the TPA2013D1 is important for the efficiency of the Class-D amplifier,
because any resistance or inductance in the trace between the device and the capacitor can cause a loss in
efficiency. Place a capacitor of 10 μF or greater between the power supply and the boost inductor. The capacitor
filters out high-frequency noise. More importantly, it acts as a charge reservoir, providing energy more quickly
than the board supply, thus helping to prevent any droop.
10.2.1.2.5.2 Input Capacitors
The TPA2013D1 does not require input coupling capacitors if the design uses a differential source that is biased
within the common mode input range. Use input coupling capacitors if the input signal is not biased within the
recommended common-mode input range, if high-pass filtering is needed, or if using a single-ended source.
The input capacitors and input resistors form a high-pass filter with the corner frequency, fc, determined in
Equation 6.
1
fc =
(2 ´ p ´ RICI )
(6)
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)
performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the
corner frequency can be set to block low frequencies in this application. Not using input capacitors can increase
output offset.
Use Equation 7 to find the required the input coupling capacitance.
1
CI =
(2 ´ p ´ fc ´ RI )
(7)
Any mismatch in capacitance between the two inputs causes a mismatch in the corner frequencies. Choose
capacitors with a tolerance of ±10% or better.
10.2.1.3 Application Curves
For application curves, see the figures listed in table Table 8.
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Table 8. Table of Graphs
DESCRIPTION
FIGURE NUMBER
Efficiency vs Output Power
Figure 1
Supply Current vs Output Power
Figure 5
Output Power vs Supply Voltage
Figure 7
Output Power vs Load
Figure 11
10.2.2 Bypassing the Boost Converter
Bypass the boost converter to drive the Class-D amplifier directly from the battery. Place a Shottky diode
between the SW pin and the VCCIN pin. Select a diode that has an average forward current rating of at least 1 A,
reverse breakdown voltage of 10 V or greater, and a forward voltage as small as possible. See Figure 34 for an
example of a circuit designed to bypass the boost converter.
Do not configure the circuit to bypass the boost converter if VDD is higher than VCC when the boost converter is
enabled (SDb ≥ 1.3 V); VDD must be lower than VCC for proper operation. VDD may be set to any voltage within
the recommended operating range when the boost converter is disabled (SDb ≤ 0.3 V).
Place a logic high on SDb to place the TPA2013D1 in boost mode. Place a logic low on SDb to place the
TPA2013D1 in bypass mode.
Toshiba CRS 06
Schottky Diode
R1
50 kΩ
R2
500 kΩ
Toko
1098AS-4R7M
To Battery
22 mF
1 mF
4.7 mH
22 mF
VDD
SW VCCFB
VCCOUT
VCCIN
CIN
IN–
Left
Channel
Input
1 mF
VOUT+
IN+
TPA2013D1
CIN
VOUT–
GAIN
GND = Bypass
VDD = Boost Mode
SDb
GPIO
SDd
AGND
PGND
Figure 34. Bypass Circuit
10.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 5.
10.2.2.2 Detailed Design Procedure
For the design procedure, see Detailed Design Procedure.
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10.2.2.3 Application Curves
For application curves, see the figures listed in Table 8.
10.2.3 Stereo Operation Application
Use the boost converter of the TPA2013D1 to supply the power for another audio amplifier when stereo
operation is required. Ensure the gains of the amplifiers match each other. This prevents one channel from
sounding louder than the other. Use Equation 1 through Equation 5 to determine R1, R2, boost inductor, and the
boost capacitor values. Figure 35 is an example schematic. The TPA2032D1 is a good choice for this
application; the gain is internally set to 2 V/V, the power supply is compatible with VCCOUT of the TPA2013D1,
and the output power of the TPA2032D1 is on par with the TPA2013D1.
R1
62.5 kΩ
R2
500 kΩ
1 mF
47 mF
4.7 mH
To Battery
22 mF
VDD
SW VCCFB
VCCOUT
VCCIN
CIN
Left
Channel
Input
IN–
1 mF
VOUT+
IN+
CIN
TPA2013D1
VOUT–
GAIN
GPIO
ShutDown Boost
CI
SDb
ShutDown ClassD
SDd
VDD
IN–
AGND
PGND
Right
Channel
Input
1 mF
VO+
TPA2032D1
IN+
VO–
CI
SHUTDOWN
GND
Figure 35. TPA2013D1 in Stereo With the TPA2032D1
10.2.3.1 Design Requirements
For this design example, use the parameters listed in Table 5.
10.2.3.2 Detailed Design Procedure
For the design procedure, see Detailed Design Procedure.
10.2.3.3 Application Curves
For application curves, see the figures listed in Table 8.
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10.2.4 LED Driver for Digital Still Cameras
Use the boost converter of the TPA2013D1 as a power supply for the flash LED of a digital still camera. Use a
microprocessor or other device or synchronize the flash to shutter sound that typically comes from the speaker of
a digital still camera. Figure 36 shows a typical circuit for this application. LEDs, switches, and other components
varies by application.
R1
50 kΩ
R2
500 kΩ
1 mF
100 mF
6.2 mH
LXCL-PWF3
To Battery
CKG57NX5R1C107M
22 mF
VDD
SW VCCFB
VCCOUT
VCCIN
1W
CIN
IN–
Differential
Input
1 mF
VOUT+
IN+
CIN
Gain
GPIO
TPA2013D1
VOUT–
GAIN
ShutDown Boost
SDb
ShutDown ClassD
SDd
NDS355N
GPIO
AGND
PGND
Figure 36. LED Driver
10.2.5 Design Requirements
For this design example, use the parameters listed in Table 5.
10.2.6 Detailed Design Procedure
For the design procedure, see Detailed Design Procedure.
10.2.7 Application Curves
For application curves, see the figures listed in Table 8.
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11 Power Supply Recommendations
The TPA2013D1 is designed to operate from an input voltage supply range from 1.8 V to 5.5 V. Therefore, the
output voltage range of the power supply should be within this range. The current capability of upper power must
not exceed the maximum current limit of the power switch.
11.1 Power Supply Decoupling Capacitors
The TPA2013D1 requires adequate power-supply decoupling to ensure a high-efficiency operation with low total
harmonic distortion (THD). Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF,
within 2 mm of the VDD/VCCOUT pin. This choice of capacitor and placement helps with higher-frequency
transients, spikes, or digital hash on the line. In addition to the 0.1-μF ceramic capacitor, TI recommends placing
a 2.2-µF to 10-µF capacitor on the VDD supply trace. This larger capacitor acts as a charge reservoir, providing
energy faster than the board supply, thus helping to prevent any droop in the supply voltage.
12 Layout
12.1 Layout Guidelines
12.1.1 Component Placement
Place all the external components close to the TPA2013D1 device. Placing the decoupling capacitors as close to
the device as possible is important for the efficiency of the class-D amplifier. Any resistance or inductance in the
trace between the device and the capacitor can cause a loss in efficiency
12.1.1.1 Trace Width
Recommended trace width at the solder balls is 75 μm to 100 μm to prevent solder wicking onto wider PCB
traces.
For high current pins (SW, PGND, VOUT+, VOUT–, VCCIN, and VCCOUT) of the TPA2013D1, use 100-μm trace
widths at the solder balls and at least 500-μm PCB traces to ensure proper performance and output power for
the device.
For low current pins (IN–, IN+, SDd, SDb, GAIN, VCCFB, VDD) of the TPA2013D1, use 75-μm to 100-μm trace
widths at the solder balls. Run IN– and IN+ traces side-by-side to maximize common-mode noise cancellation.
12.1.2 Pad Side
In making the pad size for the WCSP balls, use nonsolder mask defined (NSMD) land. With this method, the
solder mask opening is made larger than the desired land area, and the opening size is defined by the copper
pad width. Figure 37 and Table 9 show the appropriate diameters for a WCSP layout.
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Layout Guidelines (continued)
Copper Trace Width
Solder Pad Width
Solder Mask Opening
Solder Mask Thickness
Copper Trace Thickness
Figure 37. Land Pattern Dimensions
Table 9. Land Pattern Dimensions
SOLDER PAD
DEFINITIONS
COPPER PAD
SOLDER MASK
OPENING
COPPER
THICKNESS
STENCIL
OPENING
STENCIL
THICKNESS
Nonsolder mask
defined (NSMD)
275 μm
(+0.0, –25 μm)
375 μm
(+0.0, –25 μm)
1 oz max (32 μm)
275 μm x 275 μm Sq.
(rounded corners)
125 μm thick
NOTES:
1. Circuit traces from NSMD defined PWB lands should be 75 μm to 100 μm wide in the exposed area inside
the solder mask opening. Wider trace widths reduce device stand off and impact reliability.
2. Recommend solder paste is Type 3 or Type 4.
3. Best reliability results are achieved when the PWB laminate glass transition temperature is above the
operating the range of the intended application.
4. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in
thermal fatigue performance.
5. Solder mask thickness should be less than 20 μm on top of the copper circuit pattern.
6. Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically
etched stencils results in inferior solder paste volume control.
7. Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional
component movement due to solder wetting forces.
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12.2 Layout Examples
IN
Input capacitors
placed as close as
possible to the device
-
IN +
Differential Routing of
input and output
signals is
recommended
SDb
OUT GAIN
D4
D3
D2
D1
C4
C3
C2
C1
B4
B3
B2
B1
A4
A3
A2
A1
OUT +
SDd
Decoupling capacitor
placed as close as
possible to the device
0.1µF
TPA2013D1
500KΩ
50KΩ
10µF
Decoupling capacitor
placed as close as
possible to the device
2.2µH
Resistors placed as close
as possible to the device
10µF
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Bottom Layer Traces
Via to Ground Plane
Via to Bottom Layer
Via to Power Supply Plane
Figure 38. TPA2015BGA Layout
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Layout Examples (continued)
Decoupling capacitor
placed as close as
possible to the device
Decoupling capacitor
placed as close as
possible to the device
1µF
500KΩ
10µF
2.2uH
20
1µF
19
18
17
16
1
15
OUT +
2
14
3
13
OUT +
OUT +
SDd
4
12
OUT -
SDb
5
11
OUT -
GAIN
50KΩ
6
7
8
9
10
TPA2013D1
Input capacitors
placed as close as
possible to the device
1µF
Differential Routing of
input and output
signals is
recommended
1µF
IN -
IN +
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Bottom Layer Traces
Via to Bottom Ground Plane
Via to Bottom Layer
Via to Power Supply Plane
Thermal Pad
Figure 39. TPA2015QFN Layout
12.3 Efficiency and Thermal Considerations
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factors
for the YZH and RGP packages are shown in Dissipation Ratings. Apply the same principles to both packages.
Using the YZH package, and converting this to θJA:
1
1
qJA =
=
= 80.64°C/W
Derating Factor
0.0124
(8)
Given θJA of 80.64°C/W, the maximum allowable junction temperature of 150°C, and the maximum internal
dissipation of 0.317 W (VDD = 3.6 V, PO = 1.7 W), the maximum ambient temperature is calculated with
Equation 9:
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Efficiency and Thermal Considerations (continued)
TA Max = TJMax - qJA PDmax = 150 - 80.64 (0.317) = 124°C
(9)
Equation 9 shows that the calculated maximum ambient temperature is 124°C at maximum power dissipation
under the above conditions. The TPA2013D1 is designed with thermal protection that turns the device off when
the junction temperature surpasses 150°C to prevent damage to the IC. Also, using speakers more resistive than
4-Ω dramatically increases the thermal performance by reducing the output current and increasing the efficiency
of the amplifier.
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.1.2 Device Nomenclature
13.1.2.1 Boost Terms
The following is a list of terms and definitions used in the boost equations found in this document.
C
Minimum boost capacitance required for a given ripple voltage on VCC.
L
Boost inductor
fboost
Switching frequency of the boost converter.
ICC
Current pulled by the Class-D amplifier from the boost converter.
IL
Average current through the boost inductor.
R1 and R2
Resistors used to set the boost voltage.
VCC
Boost voltage. Generated by the boost converter. Voltage supply for the Class-D
amplifier.
VDD
Supply voltage to the IC.
ΔIL
Ripple current through the inductor.
ΔV
Ripple voltage on VCC due to capacitance.
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPA2013D1RGPR
ACTIVE
QFN
RGP
20
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
BTI
TPA2013D1YZHR
ACTIVE
DSBGA
YZH
16
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BTH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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