TPA3004D2
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SLOS407E – FEBRUARY 2003 – REVISED JANUARY 2011
12-W STEREO CLASS-D AUDIO POWER AMPLIFIER
WITH DC VOLUME CONTROL
Check for Samples: TPA3004D2
FEATURES
1
•
•
2
•
•
•
•
•
DESCRIPTION
12-W/Ch Into an 8-Ω Load From 15-V Supply
Efficient, Class-D Operation Eliminates
Heatsinks and Reduces Power Supply
Requirements
32-Step DC Volume Control From -40 dB to
36 dB
Line Outputs For External Headphone
Amplifier With Volume Control
Regulated 5-V Supply Output for Powering
TPA6110A2
Space-Saving, Thermally-Enhanced
PowerPAD™ Packaging
Thermal and Short-Circuit Protection
The TPA3004D2 is a 12-W (per channel) efficient,
Class-D audio amplifier for driving bridged-tied stereo
speakers. The TPA3004D2 can drive stereo speakers
as low as 4 Ω. The high efficiency of the TPA3004D2
eliminates the need for external heatsinks when
playing music.
Stereo speaker volume is controlled with a dc voltage
applied to the volume control terminal offering a
range of gain from -40 dB to 36 dB. Line outputs, for
driving external headphone amplifier inputs, are also
dc voltage controlled with a range of gain from -56 dB
to 20 dB.
An integrated 5-V regulated supply is provided for
powering an external headphone amplifier.
APPLICATIONS
LCD Monitors and TVs
Powered Speakers
10 µF
Cs
0.1 µF
Cs
0.1 µF
Crinp 1 µF
1 µF
Clinp
1 µF
BSRP
PVCCR
PVCCR
PGNDR
ROUTN
PGNDR
PVCCR
MODE
V2P5
AVCC
LINP
1 µF
MODE_OUT
SYSTEM CONTROL
VAROUTR
LINN
RLINE_OUT
VAROUTL
TPA3004D2
AVDDREF
FADE
VOLUME
AGND
REFGND
VCLAMPL
Cs
Cbs
10 nF
PVCC
0.1 µF
BSLP
ROSC
PVCCL
COSC
VARMAX
PVCCL
VARDIFF
VARMAX
LOUTP
VARDIFF
PGNDL
AVDD
PGNDL
VREF
BSLN
VOL
Ccpr
VCLAMPR
RINP
LOUTN
LINN
1 µF
1 µF Clinn
Cbs
Cs
RINN
LOUTN
LINP
C2p5
10 nF
MODE_OUT
PVCCL
RINP
SD
PVCCL
RINN
Crinn
ROUTN
BSRN
SYSTEM CONTROL
PVCCR
Cs
PVCC
ROUTP
Cbs
10 µF
ROUTP
PVCC
10 nF
LOUTP
•
•
AVCC
Cs
0.1 µF
Cvcc
10 µF
LLINE_OUT
AVDD
Cvdd
Cosc
100 nF
220 pF
SYSTEM CONTROL
Rosc
120 kΩ
Ccpl
1 µF
10
kΩ
10
kΩ
Cs
0.1 µF
Cs
Cs
10 µF
10 µF
Cbs
10 nF
PVCC
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2011, Texas Instruments Incorporated
TPA3004D2
SLOS407E – FEBRUARY 2003 – REVISED JANUARY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
PACKAGED DEVICE
TA
48-PIN HTQFP (PHP)
40°C to 85°C
(1)
(1)
TPA3004D2PHP
The PHP package is available taped and reeled. To order a taped and reeled part, add the suffix R to
the part number (e.g., TPA3004D2PHPR).
PHP PACKAGE
BSRP
PVCCR
ROUTP
ROUTP
PGNDR
ROUTN
ROUTN
PGNDR
43 42
41 40 39 38
37
SD
1
36
VCLAMPR
RINN
2
35
MODE_OUT
RINP
3
34
MODE
V2P5
4
33
AVCC
LINP
5
32
VAROUTR
LINN
6
31
VAROUTL
AVDDREF
7
30
FADE
VREF
8
29
AVDD
VARDIFF
9
28
COSC
VARMAX
10
27
ROSC
VOLUME
11
26
AGND
REFGND
12
25
VCLAMPL
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24
BSLP
PVCCL
PVCCL
LOUTP
LOUTP
PGNDL
PGNDL
20 21 22 23
LOUTN
18 19
LOUTN
PVCCL
BSLN
15 16 17
PVCCL
TPA3004D2
13 14
2
46 45 44
PVCCR
48 47
PVCCR
PVCCR
BSRN
(TOP VIEW)
Copyright © 2003–2011, Texas Instruments Incorporated
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SLOS407E – FEBRUARY 2003 – REVISED JANUARY 2011
FUNCTIONAL BLOCK DIAGRAM
V2P5
PVCC
V2P5
VAROUTR
VClamp
Gen
V2P5
VCLAMPR
BSRN
Gain
Adj.
PVCCR(2)
Gate
Drive
Cint2
RINN
Gain
Adj.
Rfdbk2
RINP
ROUTN(2)
Deglitch &
PGNDR
Modulation
Logic
BSRP
PVCCR(2)
Rfdbk2
V2P5
VREF
Gate
Drive
Cint2
ROUTP(2)
VOLUME
VARDIFF
VARMAX
FADE
Gain
Control
PGNDR
To Gain Adj.
Blocks
REFGND
OC
Detect
V2P5
ROSC
Ramp
Generator
Biases
References
AVDDREF
Thermal
Startup
Protection
Logic
&
COSC
VDD
VDDok
AVCC
AVDD
VCCok
AVDD
5V LDO
PVCC
TTL Input
Buffer
SD
MODE
MODE_OUT
AGND
VClamp
Gen
VCLAMPL
BSLN
Mode
PVCCL(2)
Control
Gate
Drive
Cint2
V2P5
LINN
AVCC
PGNDL
Deglitch &
Gain
Adj.
Rfdbk2
BSLP
Modulation
Logic
LINP
LOUTN(2)
PVCCL(2)
Rfdbk2
V2P5
Cint2
Gain
Adj.
Gate
Drive
LOUTP(2)
PGNDL
VAROUTL
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Pin Functions
Pin
NO.
NAME
I/O
DESCRIPTION
AGND
26
-
Analog ground for digital/analog cells in core
AVCC
33
-
High-voltage analog power supply (8.5 V to 18 V)
AVDD
29
O
5-V Regulated output capable of 100-mA output
AVDDREF
7
O
5-V Reference output—provided for connection to adjacent VREF terminal.
BSLN
13
I/O
Bootstrap I/O for left channel, negative high-side FET
BSLP
24
I/O
Bootstrap I/O for left channel, positive high-side FET
BSRN
48
I/O
Bootstrap I/O for right channel, negative high-side FET
BSRP
37
I/O
Bootstrap I/O for right channel, positive high-side FET
COSC
28
I/O
I/O for charge/discharging currents onto capacitor for ramp generator triangle wave biased at
V2P5
FADE
30
I
Input for controlling volume ramp rate. A logic low on this pin places the amplifier in fade mode.
A logic high on this pin allows a quick transition to the desired volume setting when cycling SD
or during power-up.
LINN
6
I
Negative differential audio input for left channel
LINP
5
I
Positive differential audio input for left channel
LOUTN
16, 17
O
Class-D ½-H-bridge negative output for left channel
LOUTP
20, 21
O
Class-D ½-H-bridge positive output for left channel
MODE
34
I
Input for MODE control. A logic high on this pin places the amplifier in the variable output mode
and the Class-D outputs are disabled. A logic low on this pin places the amplifier in the Class-D
mode and Class-D stereo outputs are enabled. Variable outputs (VAROUTL and VAROUTR)
are still enabled in Class-D mode to be used as line-level outputs for external amplifiers.
MODE_OUT
35
O
Output for control of the variable output amplifiers. When the MODE pin (34) is a logic high, the
MODE_OUT pin is driven low. When the MODE pin (34) is a logic low, the MODE_OUT pin is
driven high. This pin is intended for MUTE control of an external headphone amplifier. Leave
unconnected when not used for headphone amplifier control.
PGNDL
18, 19
-
Power ground for left channel H-bridge
PGNDR
42, 43
-
Power ground for right channel H-bridge
PVCCL
14, 15
Power supply for left channel H-bridge (tied to pins 22 and 23 internally), not connected to
PVCCR or AVCC.
PVCCL
22, 23
Power supply for left channel H-bridge (tied to pins 14 and 15 internally), not connected to
PVCCR or AVCC.
PVCCR
38,39
Power supply for right channel H-bridge (tied to pins 46 and 47 internally), not connected to
PVCCL or AVCC.
PVCCR
46, 47
Power supply for right channel H-bridge (tied to pins 38 and 39 internally), not connected to
PVCCL or AVCC.
REFGND
12
-
Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume,
connect the DAC ground to this terminal.
RINP
3
I
Positive differential audio input for right channel
Negative differential audio input for right channel
RINN
2
I
ROSC
27
I/O
Current setting resistor for ramp generator. Nominally equal to 1/8*VCC
ROUTN
44, 45
O
Class-D ½-H-bridge negative output for right channel
ROUTP
40, 41
O
Class-D ½-H-bridge positive output for right channel
SD
1
I
Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance
to VCC.
VARDIFF
9
I
DC voltage to set the difference in gain between the Class-D and VAROUT outputs. Connect to
GND or AVDDREF if VAROUT outputs are unconnected.
VARMAX
10
I
DC voltage that sets the maximum gain for the VAROUT outputs. Connect to GND or AVDDREF
if VAROUT outputs are unconnected.
VAROUTL
31
O
Variable output for left channel audio. Line level output for driving external HP amplifier.
VAROUTR
32
O
Variable output for right channel audio. Line level output for driving external HP amplifier.
VCLAMPL
25
-
Internally generated voltage supply for left channel bootstrap capacitors.
VCLAMPR
36
-
Internally generated voltage supply for right channel bootstrap capacitors.
4
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SLOS407E – FEBRUARY 2003 – REVISED JANUARY 2011
Pin Functions (continued)
Pin
NO.
I/O
NAME
DESCRIPTION
VOLUME
11
I
DC voltage that sets the gain of the Class-D and VAROUT outputs.
VREF
8
I
Analog reference for gain control section.
V2P5
4
O
2.5-V Reference for analog cells, as well as reference for unused audio input when using
single-ended inputs.
Thermal
Pad
—
Connect to AGND and PGND—should be center point for both grounds.
—
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Supply voltage range: AVCC, PVCC
-0.3 V to 20 V
≥ 3.6 Ω
Load impedance, RL
MODE, VREF, VARDIFF, VARMAX, VOLUME, FADE
Input voltage range, VI
SD
-0.3 V to VCC + 0.3 V
RINN, RINP, LINN, LINP
Supply current
Output current
120 mA
AVDDREF
10 mA
VAROUTL, VAROUTR
20 mA
See the Thermal Information Table
Operating free-air temperature range, TA
Operating junction temperature range, TJ
-40°C to 85°C
-40°C to 150°C
(2)
Storage temperature range, Tstg
(2)
-0.3 V to 7 V
AVDD
Continuous total power dissipation
(1)
0 V to 5.5 V
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The (TPA3004D2) incorporates an exposed PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to
a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
that could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPAD
thermally enhanced package.
THERMAL INFORMATION
THERMAL METRIC (1) (2)
TPS3004D2
PHP (48) PIN
qJA
Junction-to-ambient thermal resistance
26.6
qJCtop
Junction-to-case (top) thermal resistance
12.6
qJB
Junction-to-board thermal resistance
7.9
yJT
Junction-to-top characterization parameter
0.1
yJB
Junction-to-board characterization parameter
4.2
qJCbot
Junction-to-case (bottom) thermal resistance
0.2
(1)
(2)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
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SLOS407E – FEBRUARY 2003 – REVISED JANUARY 2011
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RECOMMENDED OPERATING CONDITIONS
MIN
MAX
UNIT
Supply voltage, VCC
PVCC, AVCC; RL ≥ 3.6 Ω
8.5
18
V
Volume reference voltage
VREF
3.0
5.5
V
Volume control pins, input voltage
VARDIFF, VARMAX, VOLUME
5.5
V
SD
High-level input voltage, VIH
Low-level input voltage, VIL
2
MODE
3.5
FADE
4
SD
0.8
MODE, FADE
MODE_OUT, IOH = 1 mA
Low-level output voltage, VOL
MODE_OUT, IOL = -1 mA
Low-level input current, IIL
AVDD–100mV
AGND+100mV
V
1
FADE, VI= 18 V, VCC = 18 V
150
SD, VI= 18 V, VCC = 18 V
50
MODE, FADE , VI= 0 V, VCC = 18 V
1
SD, VI= 0 V, VCC = 18 V
1
µA
275
kHz
85
°C
125
°C
225
Operating free-air temperature, TA
(1)
V
MODE, VI = 5 V, VCC = 18 V
Oscillator frequency, fOSC
Operating junction temperature, TJ
V
2
High-level output voltage, VOH
High-level input current, IIH
V
–40
(1)
µA
µA
Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device. The
junction temperature is controlled by the thermal design of the application and should be carefully considered in high power dissipation
applications. See the thermal considerations section on pages 33-35 for recommendations on improving the thermal performance of
your application.
DC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
Class-D Output offset voltage
(measured differentially)
| VOS |
TEST CONDITIONS
MIN
MAX
10
65
0.45 x
AVDD
0.5 x
AVDD
0.55 x
AVDD
V
4.5
5
5.5
V
INN and INP connected together, Gain = 36 dB
V2P5 (terminal 4) 2.5-V Bias voltage
No load
AVDD
5-V Regulated output
IO = 0 to 100 mA, SD = 2 V, VCC = 8.5 V to 18
V
PSRR
Class-D power supply rejection
ratio
VCC = 11.5 V to 12.5 V
ICC(class-D)
Class-D mode quiescent current
MODE = 2 V, SD = 2 V, VCC = 18 V
ICC(varout)
Variable output mode quiescent
current
ICC(class-D)max
Class-D mode RMS current at
max power
ICC(SD)
Supply current in shutdown
mode
rDS(on)
Drain-source on-state resistance
6
TYP
–80
UNIT
mV
dB
16
28.5
mA
MODE = 3.5 V, SD = 2 V, VCC = 18 V
7
9
mA
RL = 8 Ω, PO = 12 W, VCC = 15 V to 18 V
2
SD = 0.8 V, VCC = 12 V
1
SD = 0.8 V, VCC = 18 V
VCC = 12 V, IO = 1 A,
TJ = 25°C
A
10
160
High side
300
Low side
250
Total
550
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µA
mΩ
650
Copyright © 2003–2011, Texas Instruments Incorporated
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SLOS407E – FEBRUARY 2003 – REVISED JANUARY 2011
AC CHARACTERISTICS FOR CLASS-D OUTPUTS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
kSVR
Supply ripple rejection ratio
VCC = 11.5 V to 12.5 V from 10 Hz to 1 kHz,
Gain = 36 dB
–67
dB
PO(max)
Maximum continuous output
power(thermally limited)
RL = 4 Ω
7.5
W
RL = 8 Ω, VCC = 15 V
12
W
Output integrated noise floor
20 Hz to 22 kHz, No weighting filter,
Gain = 0.5 dB
–82
dBV
Crosstalk,
Class-D-Left → Class-D-Right
Gain = 13.2 dB, PO = 1 W, RL = 8 Ω
–77
dB
Crosstalk,
Class-D → VAROUT
Maximum output at THD < 0.5%, Gain = 36 dB
–63
dB
Signal-to-noise ratio
Maximum output at THD+N < 0.5%, f = 1 kHz,
Gain = 0.5 dB
102
dB
150
°C
20
°C
Vn
SNR
MIN
Thermal trip point
Thermal hysteresis
TYP
MAX
UNITS
CHARACTERISTICS FOR VAROUT OUTPUTS
PARAMETER
|VOS|
THD+N
Output offset voltage
Total harmonic distortion + noise
TEST CONDITIONS
Measured between V2P5 and VAROUT,
Gain = 20 dB, RL = 10 kΩ
MIN
TYP
MAX
10
65
AV = 7.3 dB, f = 1 kHz,
PO = 6 mW, RL = 32 Ω
0.025%
AV = 7.3 dB, f = 1 kHz,
RL = 2 kΩ, VO = 1 Vrms
0.002%
UNITS
mV
PSRR
DC power supply rejection ratio
Gain = 20 dB
–74
dB
kSVR
Supply ripple rejection ratio
Gain = 20 dB, f = 1 kHz
–95
dB
Crosstalk, VAROUTL → VAROUTR
Maximum output at THD < 0.5%, Gain = 20 dB
–60
dB
Crosstalk, VAROUT → Class-D
Maximum output at THD < 0.5%, Gain = 20 dB
–74
dB
Vn
Output integrated noise floor
20 Hz to 22 kHz, Gain = 20 dB
75
20 Hz to 22 kHz, Gain = –0.3 dB
15
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Table 1. DC Volume Control for Class-D Outputs
(1)
8
VOLTAGE ON THE
VOLUME PIN AS A
PERCENTAGE OF VREF
(INCREASING VOLUME
OR FIXED GAIN)
VOLTAGE ON THE
VOLUME PIN AS A
PERCENTAGE OF VREF
(DECREASING VOLUME)
GAIN OF CLASS-D
AMPLIFIER
%
%
dB
0 – 4.5
0 – 2.9
–75 (1)
4.5 – 6.7
2.9 – 5.1
–40.0
6.7– 8.91
5.1 – 7.2
–37.5
8.9 – 11.1
7.2 – 9.4
–35.0
11.1 – 13.3
9.4 – 11.6
–32.4
13.3 – 15.5
11.6 – 13.8
–29.9
15.5 – 17.7
13.8 – 16.0
–27.4
17.7 – 19.9
16.0 – 18.2
–24.8
19.9 – 22.1
18.2 – 20.4
–22.3
22.1 – 24.3
20.4 – 22.6
–19.8
24.3 – 26.5
22.6 – 24.8
–17.2
26.5 – 28.7
24.8 – 27.0
–14.7
28.7– 30.9
27.0 – 29.1
–12.2
30.9 – 33.1
29.1 – 31.3
–9.6
33.1 – 35.3
31.3 – 33.5
–7.1
35.3 – 37.5
33.5 – 35.7
–4.6
37.5 – 39.7
35.7 – 37.9
–2.0
39.7 – 41.9
37.9 – 40.1
0.5 (1)
41.9 – 44.1
40.1 – 42.3
3.1
44.1 – 46.4
42.3 – 44.5
5.6
46.4 – 48.6
44.5 – 46.7
8.1
48.6 – 50.8
46.7 – 48.9
10.7
50.8 – 53.0
48.9 – 51.0
13.2
53.0 – 55.2
51.0 – 53.2
15.7
55.2 – 57.4
53.2 – 55.4
18.3
57.4 – 59.6
55.4 – 57.6
20.8
59.6 – 61.8
57.6 – 59.8
23.3
61.8 – 64.0
59.8 – 62.0
25.9
64.0 – 66.2
62.0 – 64.2
28.4
66.2 – 68.4
64.2 – 66.4
30.9
68.4 – 70.6
66.4 – 68.6
33.5
>70.6
>68.6
36.0 (1)
Tested in production. Remaining steps are specified by design.
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Table 2. DC Volume Control for VAROUT Outputs
(1)
(2)
VAROUT_VOLUME (V) (1) –
FROM FIGURE 24 – AS A
PERCENTAGE OF VREF
(INCREASING VOLUME
OR FIXED GAIN)
VAROUT_VOLUME (V) –
FROM FIGURE 24 – AS A
PERCENTAGE OF VREF
(DECREASING VOLUME)
GAIN OF VAROUT
AMPLIFIER
%
%
dB
0 – 4.5
0 – 2.9
–66 (1)
4.5 – 6.7
2.9 – 5.1
–56.0
6.7– 8.91
5.1 – 7.2
–53.5
8.9 – 11.1
7.2 – 9.4
–50.9
11.1 – 13.3
9.4 – 11.6
–48.4
13.3 – 15.5
11.6 – 13.8
–45.9
15.5 – 17.7
13.8 – 16.0
–43.3
17.7 – 19.9
16.0 – 18.2
–40.8
19.9 – 22.1
18.2 – 20.4
–38.3
22.1 – 24.3
20.4 – 22.6
–35.7
24.3 – 26.5
22.6 – 24.8
–33.2
26.5 – 28.7
24.8 – 27.0
–30.7
28.7– 30.9
27.0 – 29.1
–28.1
30.9 – 33.1
29.1 – 31.3
–25.6
33.1 – 35.3
31.3 – 33.5
–23.1
35.3 – 37.5
33.5 – 35.7
–20.5
37.5 – 39.7
35.7 – 37.9
–18.0
39.7 – 41.9
37.9 – 40.1
–15.5
41.9 – 44.1
40.1 – 42.3
–13.0 (2)
44.1 – 46.4
42.3 – 44.5
–10.4
46.4 – 48.6
44.5 – 46.7
–7.9
48.6 – 50.8
46.7 – 48.9
–5.3
50.8 – 53.0
48.9 – 51.0
–2.8
53.0 – 55.2
51.0 – 53.2
–0.3
55.2 – 57.4
53.2 – 55.4
2.3
57.4 – 59.6
55.4 – 57.6
4.8
59.6 – 61.8
57.6 – 59.8
7.3
61.8 – 64.0
59.8 – 62.0
9.9
64.0 – 66.2
62.0 – 64.2
12.4
66.2 – 68.4
64.2 – 66.4
14.9
68.4 – 70.6
66.4 – 68.6
17.5
>70.6
>68.6
20.0 (1)
VAROUT_VOLUME (V) = VOLUME (V) - VARDIFF (V), see section VOLUME CONTROL
OPERATION through MODE_OUT OPERATION section.
Tested in production. Remaining steps are specified by design.
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TYPICAL CHARACTERISTICS
Table 3. Table of Graphs
FIGURE
Class-D Efficiency
vs Output power
Figure 1
PO
Class-D Output power
vs Load resistance
Figure 2
vs Supply voltage
Figure 3
ICC
Class-D Supply current
vs Supply voltage
Figure 4
vs Output Power
Figure 5
Shutdown supply current
vs Supply voltage
Figure 6
Class-D Input impedance
vs Gain
IO(sd)
THD+N
Class-D Total harmonic distortion + noise
kSVR
Class-D Supply ripple rejection ratio
Figure 8 – Figure 12
vs Output power
Figure 13 – Figure 17
vs Frequency
Figure 19
Class-D Intermodulation performance
Figure 20
Class-D Input offset voltage
vs Common-mode input voltage
Figure 21
Class-D Crosstalk
vs Frequency
Figure 22
vs Frequency
Class-D Shutdown attenuation
10
Figure 23
Figure 24
Class-D Common-mode rejection ratio
vs Frequency
Figure 25
VAROUT Input resistance
vs Gain
Figure 26
VAROUT Noise
vs Frequency
Figure 27
VAROUT Closed Loop Response
kSVR
Figure 18
Class-D Closed loop response
Class-D Mute attenuation
THD+N
Figure 7
vs Frequency
Figure 28
VAROUT Common-mode rejection ratio
vs Frequency
Figure 29
VAROUT Crosstalk
vs Frequency
Figure 30
vs Output power
Figure 31
vs Output voltage
Figure 32
vs Frequency
Figure 33
vs Frequency
Figure 34
VAROUT Total harmonic distortion + noise
VAROUT Supply ripple rejection ratio
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EFFICIENCY
vs
OUTPUT POWER
OUTPUT POWER
vs
LOAD RESISTANCE
12
100
VCC = 12 V,
THD = 10%
RL = 8 Ω, VCC = 18 V
90
10
80
Efficiency – %
PO – Output Power – W
RL = 4 Ω, VCC = 12 V
70
60
50
40
30
Class-D,
LC Filter,
Resistive Load
20
10
VCC = 12 V,
THD = 1%
8
VCC = 8 V,
THD = 10%
6
4
VCC = 8 V,
THD = 1%
2
Dashed line may require external heat sinking
0
0
0
2
4
6
8
PO – Output Power – W
10
4
12
6
8
10
12
RL – Load Resistance – Ω
Figure 1.
16
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
20
12
8 Ω Speaker
10% THD+N
19
18
I CC– Supply Current – mA
10
8
8 Ω Speaker
1% THD+N
6
4
SD = 2 V,
MODE = 2 V,
Class-D,
No Load
17
16
15
14
13
12
TA = 25°C
2
8.5 9
14
Figure 2.
OUTPUT POWER
vs
SUPPLY VOLTAGE
PO – Output Power – W
f = 1 kHz,
LC Filter,
Class-D,
Resistive Load,
TA = 25°C
10
11
11 12 13 14 15 16
VCC – Supply Voltage – V
17
18
10
8.5 9
Figure 3.
10
11 12 13 14 15 16
VCC – Supply Voltage – V
17
18
Figure 4.
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SHUTDOWN SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
OUTPUT POWER
2500
4.5
I CC– Supply Current – mA
2000
I CC(sd)– Shutdown Supply Current – µ A
VCC = 12 V,
MODE = 2 V,
Class-D,
Left/Right Channel
Total Output Power
8Ω
1500
4Ω
1000
16 Ω
500
0
0
5
10
15
PO – Output Power – W
20
SD = 0 V,
No Load
4
3.5
3
2.5
2
1.5
1
0.5
0
25
8
6
10
12
14
VCC – Supply Voltage – V
Figure 5.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
120
THD+N – Total Harmonic Distortion + Noise – %
1
Class-D
Z i – Input Impedance – k Ω
100
80
60
40
20
–30
–10
10
Gain – dB
30
50
VCC = 8 V
RL = 8 Ω
Gain = +36 dB
Class-D
PO = 3 W
0.1
PO = 0.25 W
PO = 1.5 W
0.01
20
100
1k
10k
f – Frequency – Hz
Figure 7.
12
18
Figure 6.
INPUT IMPEDANCE
vs
GAIN
0
–50
16
Figure 8.
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TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
VCC = 12 V
RL = 8 Ω
Gain = +36 dB
Class-D
THD+N –Total Harmonic Distortion + Noise – dB
THD+N – Total Harmonic Distortion + Noise – %
1
PO = 0.5 W
PO = 5 W
0.1
PO = 2.5 W
0.01
10
100
1k
10k
VCC = 18 V,
Gain = 36 dB,
RL = 8 Ω
5
2
1
0.5
PO = 1 W
PO = 4 W
0.2
0.1
0.05
PO = 12 W
0.02
0.01
20
50
f – Frequency – Hz
100 200
Figure 9.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N – Total Harmonic Distortion + Noise – %
1
THD+N – Total Harmonic Distortion + Noise – %
5 k 10 k 20 k
Figure 10.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
VCC = 8 V
RL = 4 Ω
Gain = +36 dB
PO = 4 W
500 1 k 2 k
f – Frequency – Hz
PO = 0.5 W
0.1
PO = 2 W
0.01
1
VCC = 12 V
RL = 4 Ω
Gain = +36 dB
PO = 0.5 W
0.1
PO = 7 W
PO = 3.5 W
0.01
20
100
1k
10k
20
f – Frequency – Hz
100
1k
10k
f – Frequency – Hz
Figure 11.
Figure 12.
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TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
VCC = 8 V
RL = 8 Ω
Gain = +13.2 dB
Class-D
THD+N – Total Harmonic Distortion + Noise – %
THD+N – Total Harmonic Distortion + Noise – %
10
1
f = 1 kHz
f = 20 Hz
0.1
0.01
10 m
100 m
1
10
VCC = 12 V
RL = 8 Ω
Gain = +13.2 dB
Class-D
1
f = 20 Hz
f = 1 kHz
0.1
0.01
10 m
PO – Output Power – W
100 m
Figure 13.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
VCC = 18 V,
RL = 8 Ω
THD+N – Total Harmonic Distortion + Noise – %
THD+N –Total Harmonic Distortion + Noise – dB
10
2
1
0.5
f = 1 kHz
0.2
0.1
f = 20 kHz
0.05
0.02
0.01
100 m 200 m
f = 20 Hz
5
500 m
1
2
PO – Output Power – W
10
20
VCC = 8 V
RL = 4 Ω
Gain = 13.2 dB
1
f = 1 kHz
f = 20 Hz
0.1
0.01
20 m
100 m
1
10
PO – Output Power – W
Figure 15.
14
10
Figure 14.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
5
1
PO – Output Power – W
Figure 16.
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TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
–40
VCC = 12 V
RL = 4 Ω
Gain = 13.2 dB
k SVR – Supply Ripple Rejection Ratio – dB
THD+N – Total Harmonic Distortion + Noise – %
10
1
f = 20 Hz
f = 1 kHz
0.1
0.01
20 m
100 m
1
–45
RL = 8 Ω,
C2p5 = 1 µF,
Class-D
–50
–55
VCC = 8 V
–60
–65
VCC = 12 V
–70
–75
–80
20
10
100
PO – Output Power – W
Figure 17.
CLOSED LOOP RESPONSE
INTERMODULATION PERFORMANCE
–20
0
–40
FFT – dBr
50
Phase – Deg
Gain
Phase
Gain – dB
0
100
0
–50
–100
–100
–150
–150
–100
–200
–120
–250
10
VCC = 12 V,
Gain= +36 dB,
RL = 8 Ω
Class-D
100
1k
10 k
f – Frequency – Hz
100 k
–250
1M
VCC = 12 V, 19 kHz, 20 kHz,
1:1, PO = 1 W, RL = 8 Ω
Gain= +13.2 dB,
BW =20 Hz to 22 kHz,
Class-D
No Filter
–60
–50
–200
10 k 20 k
Figure 18.
100
50
1k
f – Frequency – Hz
–80
–140
50
Figure 19.
100
1k
f – Frequency – Hz
10 k
Figure 20.
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CROSSTALK
vs
FREQUENCY
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
6
0
VCC = 12 V
Class-D
–20
4
Crosstalk – dB
VIO – Input Offset Voltage – mV
5
VCC = 12 V,
C2p5 = 1 µF,
PO = 1 W,
Gain = +13.2 dB,
Class-D,
RL = 8 Ω
–10
3
2
–30
–40
–50
–60
1
–70
0
–80
–1
0
4
1
2
3
VICM – Common-Mode Input Voltage – V
–90
20
5
100
Figure 21.
Figure 22.
SHUTDOWN ATTENUATION
vs
FREQUENCY
MUTE ATTENUATION
vs
FREQUENCY
–80
–40
VCC = 12 V,
RL = 8 Ω,
VI = 1 Vrms
–85
–50
Class-D,
–90
Shutdown Attenuation – dB
Mute Attenuation – dB
–30
VOLUME = 0 V
–60
–70
–80
–90
–100
VCC = 12 V,
RL = 8 Ω,
VI = 1 Vrms
Gain = +13.2 dB,
Class-D
–95
–100
–105
–110
–115
–110
–120
–120
–125
–130
–130
10
100
1k
10 k
10
f – Frequency – Hz
100
1k
10 k
f – Frequency – Hz
Figure 23.
16
10 k 20 k
1k
f – Frequency – Hz
Figure 24.
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COMMON-MODE REJECTION RATIO
vs
FREQUENCY
INPUT RESISTANCE
vs
GAIN
160
VCC = 12 V,
RL = 8 Ω,
C2p5 = 1 µF,
Class-D
–50
VAROUT
140
RL – Input Resistance – k Ω
–60
–70
–80
120
100
80
60
40
–90
20
–100
10
100
1k
10 k
f – Frequency – Hz
0
–50
100 k
–30
Figure 25.
10
BCLOSED LOOP RESPONSE
0
12.853
VCC = 12 V,
Gain = +20 dB,
RL = 8 Ω,
Inputs AC Coupled to GND,
VAROUT,
No Filter
−20
−40
−60
Gain − dB
−120
−140
5.784
100
2.249
75
−1.285
50
25
Phase
−4.82
−25
−50
−11.889
−75
−15.424
−180
−18.958
−200
10 k
0
−8.354
−160
1k
f − Frequency − Hz
150
125
−100
100
175
Gain
9.318
−80
20
30
Figure 26.
NOISE
vs
FREQUENCY
Noise FFT − dBV
–10
Gain – dB
Phase − Deg
CMRR – Common-Mode Rejection Ratio – dB
–40
−100
VCC = 12 V,
Gain = +7.9 dB,
RL = 8 Ω,
VAROUT
−22.493
10
100
−125
−150
−175
1k
10 k
f − Frequency − Hz
Figure 27.
Figure 28.
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COMMON-MODE REJECTION RATIO
vs
FREQUENCY
CROSSTALK (VAROUTL-TO-VAROUTR)
vs
FREQUENCY
0
VCC = 12 V,
RL = 8 Ω ,
C2P5 = 1 µF,
VAROUT
–42
–44
VO = 1 Vrms,
RL = 10 kΩ,
VAROUT
–10
–20
–46
G = 20 dB
G = 10 dB
G = 0 dB
–30
Crosstalk – dB
CMRR – Common-Mode Rejection Ratio – dBv
–40
–48
–50
–52
–40
G = –10 dB
–50
–60
–54
–70
–56
–80
–58
–90
–60
20
–100
100
1k
f– Frequency – Hz
20
10 k
100
1k
Figure 29.
Figure 30.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT VOLTAGE
2
20
VCC = 12 V
RL = 32 Ω,
Gain = +6 dB,
VAROUT
THD+N –Total Harmonic Distortion + Noise – %
THD+N –Total Harmonic Distortion + Noise – %
20
10
1
0.2
f = 1 kHz
0.1
f = 20 kHz
0.02
0.01
f = 20 Hz
0.001
20 µ
100 µ 200 µ
1m
2m
10 m 20 m
10
2
1
VCC = 12 V
RL = 10 kΩ,
Gain = +6 dB
VAROUT
0.2
0.1
0.02
f = 1 kHz
0.01
0.001
20 m
PO – Output Power – W
Figure 31.
18
10 k
f – Frequency – Hz
100 m
200 m
VO – Output Voltage – VRMS
1
2
Figure 32.
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SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
2
1
–40
VCC = 12 V
RL = 32 Ω,
PO = 5 mW,
Gain = +7.9 dB,
VAROUT
k SVR – Supply Ripple Rejection Ratio – dB
THD+N –Total Harmonic Distortion + Noise – %
10
0.2
0.1
0.02
0.01
0.005
20
100
1k
f – Frequency – Hz
10 k
–50
VCC = 12 V
VAROUT
–60
–70
–80
–90
–100
–110
20
100
1k
10 k
f – frequency – Hz
Figure 33.
Figure 34.
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C22
1 nF
VCC
ROUT+
GND
VCC
ROUT–
APPLICATION INFORMATION
C23
1 nF
L1
(Bead)
L2
(Bead)
10 µF
PGND
10 nF
C15
0.1uF
0.1uF
C9
C10
10 nF
SHUTDOWN
C2
1 µF
C3
1 µF
1 µF C4
LIN–
1 µF
MODEB
BSRP
PVCCR
PVCCR
ROUTP
ROUTP
PGNDR
PGNDR
ROUTN
ROUTN
V2P5
AVCC
LINP
VAROUTR
VAROUTR
LINN
VAROUTL
VAROUTL
TPA3004D2
AVDDREF
FADE
VREF
AVDD
VARDIFF
COSC
VARMAX
ROSC
T5
VOLUME
AGND
REFGND
VCLAMPL
MODE
C13
0.1 µF
C16
10 µF
220pF
C11
100 nF
R1
120 kΩ
AGND
BSLP
PVCCL
PVCCL
LOUTP
10 nF
PGND
L3
(Bead)
L4
(Bead)
C25
1nF
GND
C24
1nF
VCC
C21
0.1 µF
10 µF
LOUT–
PGND
VCC
10 nF
GND
1 µF
C12
0.1 µF
C17
LOUT+
C20
LOUTP
PGNDL
PGNDL
LOUTN
LOUTN
PVCCL
PVCCL
AGND
VCC
AVDD
C14
C6
C8
GND
GND
MODE
T6
P1
50 kΩ
PGND
RINP
T7
P2
50 kΩ
1 µF
MODE_OUT
BSLN
P3
50k
C7
VCLAMPR
RINN
1 µF C5
AGND
PVCCR
SD
C1
RIN–
C19
PVCCR
BSRN
C18
†
Schottky diodes only needed for short circuit protection when VCC > 15 V. See SHORT CIRCUIT PROTECTION
section in Application Information.
Figure 35. Stereo Class-D With Single-Ended Inputs
20
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AGND
REFGND
VOLUME
VARMAX
VARDIFF
VREF
AVDDREF
LINN
BSRN
T5
1 µF
LINP
V2P5
PGNDL
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C24
1 nF
L3
(Bead)
C25
1 nF
L4
(Bead)
PGND
PGNDL
10 µ F
0.1 µ F
VCLAMPR
VCLAMPL
AGND
ROSC
COSC
AVDD
FADE
VAROUTL
VAROUTR
AVCC
MODE
MODE_OUT
10 nF
C21
PVCCL
LOUTN
LOUT–
VCC
PVCCR
PVCCL
VCC
PVCCR
PVCCL
10 nF
LOUTN
C12
LOUTP
C11
PVCCR
0.1 µ F
C17
C19
1 µF
C8
220 pF
C6
120 kΩ
R1
100 nF
C14
C16
10 µ F
PGND
C13
0.1µ F
1 µF
AVDD
AVCC
C7
Cin2
(T2)
1 µF
Rin2
10 kΩ
(T1)
1 µF
Rin1
10 kΩ
Cin1
10 kΩ (T3)
Rhps2
0.47µ F
Cvcc
10 kΩ
Rhps1
Rout1 1 kΩ
Rout2 1 kΩ
R3
120 kΩ
AVDD
Cout2
BYP IN1
10 kΩ
Rhpf2
IN2 Vo2
SD VDD
GND Vo1
AVDD
(T4)
220 µ F
Rhpf1
10 kΩ
220 µ F
TPA6110A2
Cout1
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C20
C10
10 nF
VCC
PVCCR
PVCCL
VCC
ROUT+
ROUTP
LOUTP
LOUT+
TPA3004D2
ROUTN
P1
50 kΩ
C4
1 µF
RINP
RINN
PGNDR
GND
T6
C5
1 µF
1 µF
PGNDR
P2
50 kΩ
T7
C3
C1
1 µF
C9
0.1 µ F
PGND
ROUTP
P3
50 kΩ
LIN–
AGND
C2
SD
ROUTN
C18
C15
0.1 µ F
10 µ F
L2
(Bead)
C23
1 nF
BSRP
RIN–
SHUTDOWN
ROUT–
10 nF
GND
L1
(Bead)
C22
1 nF
TPA3004D2
SLOS407E – FEBRUARY 2003 – REVISED JANUARY 2011
BSLP
GND
BSLN
†
Schottky diodes only needed for short circuit protection when VCC > 15 V. See SHORT CIRCUIT PROTECTION
section in Application Information.
Figure 36. Stereo Class-D With Single-Ended Inputs and Stereo Headphone Amplifier Interface
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Class-D Operation
This section focuses on the class-D operation of the TPA3004D2.
Traditional Class-D Modulation Scheme
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore,
the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields 0
V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 37. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,
causing high loss, thus causing a high supply current.
OUTP
OUTN
+12 V
Differential Voltage
Across Load
0V
–12 V
Current
Figure 37. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an
Inductive Load With No Input
TPA3004D2 Modulation Scheme
The TPA3004D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater
than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and
OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most
of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.
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OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
+12 V
0V
–12 V
Current
OUTP
OUTN
Differential
Voltage
Output > 0 V
+12 V
0V
Across
Load
–12 V
Current
Figure 38. The TPA3004D2 Output Voltage and Current Waveforms Into an Inductive Load
Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3004D2 modulation scheme has very little loss in the load without a filter because the pulses are very
short and the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen,
making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for
most applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance than the speaker, which results in less power
dissipation, therefore increasing efficiency.
Effects of Applying a Square Wave into a Speaker
Audio specialists have advised for years not to apply a square wave to speakers. If the amplitude of the
waveform is high enough and the frequency of the square wave is within the bandwidth of the speaker, the
square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A 250-kHz switching
frequency, however, does not significantly move the voice coil, as the cone movement is proportional to 1/f2 for
frequencies beyond the audio band.
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Damage may occur if the voice coil cannot handle the additional heat generated from the high-frequency
switching current. The amount of power dissipated in the speaker may be estimated by first considering the
overall efficiency of the system. If the on-resistance (rds(on)) of the output transistors is considered to cause the
dominant loss in the system, then the maximum theoretical efficiency for the TPA3004D2 with an 8-Ω load is as
follows:
ǒ
Efficiency (theoretical, %) + R ń R ) r
L
L
ds(on)
Ǔ
100% + 8ń(8 ) 0.58)
100% + 93.24%
(1)
The maximum measured output power is approximately 7.5 W with an 12-V power supply. The total theoretical
power supplied (P(total)) for this worst-case condition would therefore be as follows:
P
+ P ńEfficiency + 7.5 W ń 0.9324 + 8.04 W
(total)
O
(2)
The efficiency measured in the lab using an 8-Ω speaker was 89%. The power not accounted for as dissipated
across the rds(on) may be calculated by simply subtracting the theoretical power from the measured power:
Other losses + P
(measured) * P
(theoretical) + 8.43 * 8.04 + 0.387 W
(total)
(total)
(3)
The quiescent supply current at 14 V is measured to be 14.3 mA. It can be assumed that the quiescent current
encapsulates all remaining losses in the device, i.e., biasing and switching losses. It may be assumed that any
remaining power is dissipated in the speaker and is calculated as follows:
P
+ 0.387 W * (14 V 14.3 mA) + 0.19 W
(dis)
(4)
Note that these calculations are for the worst-case condition of 7.5 W delivered to the speaker. Since the 0.19 W
is only 2.5% of the power delivered to the speaker, it may be concluded that the amount of power actually
dissipated in the speaker is relatively insignificant. Furthermore, this power dissipated is well within the
specifications of most loudspeaker drivers in a system, as the power rating is typically selected to handle the
power generated from a clipping waveform.
When to Use an Output Filter
Design the TPA3004D2 without the filter if the traces from amplifier to speaker are short (< 1 inch). Powered
speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without
a filter.
Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and
CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high
impedance at high frequencies, but very low impedance at low frequencies.
Use a LC output filter if there are low frequency (
YES
(VOLUME–VARDIFF)
VAROUT_VOLUME (V) = VOLUME (V) – VARDIFF (V)
?
NO
VAROUT_VOLUME (V) = VARMAX (V)
Figure 42. Block Diagram of VAROUT Volume Control
26
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Decreasing Voltage on
VOLUME Terminal
Class-D Gain – dB
5.6
3.1
Increasing Voltage on
VOLUME Terminal
0.5
2.00
(40.1%*VREF)
2.21
2.10 2.11
(44.1%*VREF)
(41.9%*VREF) (42.3%*VREF)
Voltage on VOLUME Pin – V
Figure 43. DC Volume Control Operation, VREF = 5 V
MODE OPERATION
The MODE pin is an input for controlling the output mode of the TPA3004D2. A logic HIGH on this pin disables
the Class-D outputs. A logic LOW on this pin enables the class-D outputs. The VAROUT outputs are active in
both modes and can be used as line level inputs to an external powered subwoofer while driving internal stereo
speakers with the class-D outputs. The trip levels are defined in the specifications table.
For interfacing with an external headphone amplifier like the TPA6110A2, the MODE pin can be connected to the
switch on a headphone jack. When configured like Figure 36, the class-D outputs will be disabled when a
headphone plug is inserted into the headphone jack.
MODE_OUT OPERATION
The MODE_OUT pin is an output for controlling the SHUTDOWN pin on an external headphone amplifier like the
TPA6110A2 or for interfacing with other logic. The output voltages for a given load condition are given in the
specifications table.
This output is controlled by the MODE pin logic. When the MODE input is driven to a logic low, the MODE_OUT
output drives to a logic high. Conversely, when the MODE pin is driven to a logic high, the MODE_OUT output
drives LOW. The MODE_OUT output is simply the inverted state of the MODE input.
It is designed in this manner because the TPA6110A2 SHUTDOWN input is active high. This allows the
TPA3004D2 to place the TPA6110A2 into the shutdown state when driving internal speakers in the Class-D
mode. Conversely, the MODE_OUT pin drives low to enable the TPA6110A2 headphone amplifier when
headphones are plugged into the headphone jack and the MODE input is driven high.
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FADE OPERATION
The FADE terminal is a logic input that controls the operation of the volume control circuitry during transitions to
and from the shutdown state and during power-up.
A logic low on this terminal, places the amplifier in the fade mode. During power-up or recovering from the
shutdown state (a logic high is applied to the SD terminal), the volume is smoothly ramped up from the mute
state, –75 dB, to the desired volume setting determined by the voltage on the volume control terminals.
Conversely, the volume is smoothly ramped down from the current state to the mute state when a logic low is
applied to the SD terminal. The timing of the volume control circuitry is controlled by an internal 60-Hz clock. This
clock determines the rate at which the gain changes when adjusting the voltage on the external volume control
pins. The gain updates every 4 clock cycles (nominally 67 ms based on a 60 Hz clock) to the next step until the
final desired gain is reached. For example, if the TPA3004D2 is currently in the +0.53 db class-D gain step and
the VOLUME pin is adjusted for maximum gain at +36 dB, the time required for the gain to reach 36dB is 14
steps x 67 ms/step = 0.938 seconds. Referencing Table 1, there are 14 steps between the +0.53 dB gain step
and the maximum gain step of +36 dB.
Figure 44 shows a scope capture of the differential output (measured across OUT+ and OUT–) with the amplifier
in the fade mode. A 1 Vpp dc voltage was applied across the differential inputs and a logic low was applied to the
SD terminal at the time defined in the figure. The figure depicts the outputs transitioning from one gain step to
the next lower step at approximately 67 ms/step.
A logic high on this pin disables the volume fade effect during transitions to and from the shutdown state and
during power-up. During power-up or recovering from the shutdown state (a logic high is applied to the SD
terminal), the transition from the mute state, –75 dB, to the desired volume setting is less than 1 ms. Conversely,
the volume ramps down from current state to the mute state within 1 ms when a logic low is applied to the SD
terminal. For the best pop performance, the fade mode should be enabled (a logic low is applied to the FADE
terminal).
SD = 0V
GND
Figure 44. Differential Output With FADE (Terminal 30) Held Low
Figure 45 shows a scope capture of the differential output with the fade effect disabled. The outputs transition to
the lowest gain state within 1ms of applying a logic low to the SD terminal.
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SD = 0 V
GND
Figure 45. Differential Output With FADE Terminal Held High
The switching frequency is determined using the values of the components connected to ROSC (pin 27) and
COSC (pin 28) and may be calculated with the following equation:
fOSC = 6.6 / (ROSC × COSC) .
INTERNAL 2.5-V BIAS GENERATOR CAPACITOR SELECTION
The internal 2.5-V bias generator (V2P5) provides the internal bias for the preamplifier stages on both the
class-D amplifiers and the variable amplifiers. The external input capacitors and this internal reference allow the
inputs to be biased within the optimal common-mode range of the input preamplifiers.
The selection of the capacitor value on the V2P5 terminal is critical for achieving the best device performance.
During startup or recovery from the shutdown state, the V2P5 capacitor determines the rate at which the
amplifier starts up. When the voltage on the V2P5 capacitor equals 0.75xV2P5, or 75% of its final value, the
device turns on and the class-D outputs start switching. The startup time is not critical for the best depop
performance since any pop sound that is heard is the result of the class-D outputs switching on and not the
startup time. However, at least a 0.47-µF capacitor is recommended for the V2P5 capacitor.
A secondary function of the V2P5 capacitor is to filter high frequency noise on the internal 2.5-V bias generator.
INPUT RESISTANCE
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest
value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the –3 dB
or cutoff frequency also changes by over six times.
Zf
Ci
Input
Signal
IN
Zi
The –3-dB frequency can be calculated using Equation 5. Input impedance (ZI) vs Gain can be found in Figure 7.
1
f *3dB +
2p Z iC i
(5)
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INPUT CAPACITOR, CI
In the typical application an input capacitor (CI) is required to allow the amplifier to bias the input signal to the
proper dc level (V2P5) for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form
a high-pass filter with the corner frequency determined in equation 6.
–3 dB
fc =
1
2pZiCi
fc
(6)
The value of CI is important, as it directly affects the bass (low frequency) performance of the circuit. Consider
the example where ZI is 20 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 6 is
reconfigured as Equation 7.
1
Ci +
2pZ i f c
(7)
In this example, CI is 0.4 µF, so one would likely choose a value in the range of 0.47 µF to 1 µF. If the gain is
known and will be constant, use ZI from Figure 7 (Input Impedance vs Gain) to calculate CI. Calculations for CI
should be based off the impedance at the lowest gain step intended for use in the system. A further
consideration for this capacitor is the leakage path from the input source through the input network (CI) and the
feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that
reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic
capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face
the amplifier input in most applications as the dc level there is held at 2.5 V, which is likely higher than the source
dc level. Note that it is important to confirm the capacitor polarity in the application.
Power Supply Decoupling, CS
The TPA3004D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 µF placed as close as possible to the device VCC lead works best. For filtering
lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the audio
power amplifier is recommended. The 10-µF capacitor also serves as local storage capacitor for supplying
current during large signal transients on the amplifier outputs.
BSN and BSP Capacitors
The full H-bridge output stages use only NMOS transistors. They therefore require bootstrap capacitors for the
high side of each output to turn on correctly. A 10-nF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 10-nF capacitor must be
connected from xOUTP to xBSP, and one 10-nF capacitor must be connected from xOUTN to xBSN. (See the
application circuit diagram in Figure 35.)
The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating
power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching
cycle, the bootstrap capacitors attempt to hold the gate-to-source voltage high enough to keep the high-side
MOSFETs turned on. However, there is a leakage path and the voltage on the bootstrap capacitors slowly
decrease while the high-side is conducting.
30
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By driving the outputs into heavy clipping with a sine wave of less than 50 Hz, the bootstrap voltage can
decrease below the minimum Vgs required to keep the high-side output MOSFET turned on. When this occurs,
the output transistor becomes a source-follower and the output drops from VCC to approximately Vclamp (voltage
on pins 25 and 36).
For the majority of applications, driving a square wave at low frequencies is not a design consideration and the
recommended bootstrap capacitor value of 10-nF is acceptable. However, if this is a concern, increasing the
bootstrap capacitors holds the gate voltage for a longer period of time and the drop in the output voltage does
not occur. A value of 220-nF is recommended with a 51 Ω resistor placed in series between the outputs and
bootstrap pins. The 51 Ω series resistor is necessary to limit the current charging and discharging the bootstrap
capacitors.
VCLAMP Capacitors
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two
internal regulators clamp the gate voltage. Two 1-µF capacitors must be connected from VCLAMPL (pin 25) and
VCLAMPR (pin 36) to ground and must be rated for at least 25 V. The voltages at the VCLAMP terminals vary
with VCC and may not be used for powering any other circuitry.
Internal Regulated 5-V Supply (AVDD)
The AVDD terminal (pin 29) is the output of an internally-generated 5-V supply, used for the oscillator,
preamplifier, and volume control circuitry. It requires a 0.1-µF to 1-µF capacitor, placed very close to the pin, to
ground to keep the regulator stable. The regulator may be used to power an external headphone amplifier or
other circuitry, up to a current limit specified in the specification table. When powering external circuitry, like the
TPA6110A2 headphone amplifier, an additional 10 µF or larger capacitor should be added to the AVDD terminal.
AVDD – POWER-UP RESPONSE
Power–Up
Ch1
(AVDD)
AVDD
(pin 29)
AVCC
(pin 33)
Ch2
(AVCC)
Ch1 5.00 V/div
Ch2 2.00 V/div
M 10.0 µs
Figure 46. Power-Up Response
Differential Input
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3004D2 EVM with a differential source, connect the positive lead of the audio source to the INP
input and the negative lead from the audio source to the INN input. To use the TPA3004D2 with a single-ended
source, ac ground the INP input through a capacitor equal in value to the input capacitor on INN and apply the
audio source to the INN input. In a single-ended input application, the INP input should be ac-grounded at the
audio source instead of at the device input for best noise performance.
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SD OPERATION
The TPA3004D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for power conservation. The SD input terminal should be held high (see
specification table for trip point) during normal operation when the amplifier is in use. Pulling SD low causes the
outputs to mute and the amplifier to enter a low-current state, ICC(SD) = 10 µA. SD should never be left
unconnected, because amplifier operation would be unpredictable.
POWER-OFF POP REDUCTION
For the best power-off pop performance, the amplifier should be placed in the shutdown mode prior to removing
the power supply voltage.
Another method to reduce power-off pop is implemented in the hardware. A 100 µF – 150 µF capacitor can be
added to the AVDD terminal in parallel with the 100-nF capacitor shown in Figure 35. The additional capacitance
holds up the regulator voltage for a longer period of time and results in smaller power-off pop.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance
the more the real capacitor behaves like an ideal capacitor.
SHORT-CIRCUIT PROTECTION
The TPA3004D2 has short circuit protection circuitry on the outputs that prevents damage to the device during
output-to-output shorts, output-to-GND shorts, and output-to-VCC shorts. When a short-circuit is detected on the
outputs, the part immediately disables the output drive. This is a latched fault and must be reset by cycling the
voltage on the SD pin to a logic low and back to the logic high state for normal operation. This will clear the
short-circuit flag and allow for normal operation if the short was removed. If the short was not removed, the
protection circuitry will again activate. The trip-point for the short-circuit protection is nominally set at 8 A.
For VCC > 15 V, two Schottky diodes are required to provide short-circuit protection. The diodes should be placed
as close to the TPS3004D2 as possible, with the anodes connected to PGND and the cathodes connected to
OUTP and OUTN as shown in the application circuit schematic. The diodes should have a forward voltage rating
of 0.5 V at a minimum of 1 A output current and a dc blocking voltage rating of at least 30 V. The diodes must
also be rated to operate at a junction temperature of 150°C. If VCC < 15 V, the Schottky diodes are not required
for short circuit protection.
If short-circuit protection is not required, the Schottky diodes may be omitted.
THERMAL PROTECTION
Thermal protection on the TPA3004D2 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15 degree tolerance on this trip point from device to device. Once the die
temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are
disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by
20°C. The device begins normal operation at this point with no external system interaction.
THERMAL CONSIDERATIONS: OUTPUT POWER AND MAXIMUM AMBIENT TEMPERATURE
To calculate the maximum ambient temperature, the following equation may be used:
TAmax = TJ - qJAPDissipated
where: TJ = 125°C
qJA = 19°C/W spacer 2-Layer PCB, 5 sq. in. copper, see Figure 47.
(8)
To estimate the power dissipation, the following equation may be used:
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PDissipated = PO(average) x ((1 / Efficiency) – 1)
Efficiency = ~85% for an 8-Ω load
= ~75% for a 4-Ω load
(9)
Example. What is the maximum ambient temperature for an application that requires the TPA3004D2 to drive 10
W into an 8-Ω speaker (stereo)?
PDissipated = 20 W x ((1 / 0.85) – 1) = 3.5 W space (PO = 10 W * 2)
TAmax = 125°C – (19°C/W x 3.5 W) = 58.5°C
This calculation shows that the TPA3004D2 can drive 10 W of continuous RMS power per channel into an 8-Ω
speaker up an ambient temperature of 58.5°C.
Figure 47 and Figure 48 show the results of several thermal experiments conducted with the TPA3004D2. Both
figures show that the best thermal performance can be achieved with more copper area for heat dissipation and
an adequate number of thermal vias.
Figure 47 shows two curves for a 2-layer and 4-layer PCB. The 2-layer PCB layout was tightly controlled with a
fixed amount of 2 oz. copper on the bottom layer of the PCB. The amount of copper is shown on the x-axis. Nine
thermal vias of 13 mil (0.33mm) diameter were drilled under the PowerPad and connected to the bottom layer.
The top layer only consisted of traces for signal routing.
The 4-layer PCB layout was also tightly controlled with a fixed amount of 2 oz. copper in middle GND layer. The
top layer only consisted of traces for signal routing. The bottom and other middle layer were left blank. Nine
thermal vias of 0.33mm diameter were drilled under the PowerPad and connected to the middle layer.
Figure 48 shows the effect of the number of thermal vias drilled under the PowerPad on the thermal performance
of the PCB. The experiment was conducted with a 2-layer PCB and 3 square inches of copper on the bottom
layer. For the best thermal performance, at least 16 vias in a 4x4 pattern should be used under the PowerPad.
Refer to the TPA3004D2 EVM User's Manual, SLOU115, for an example layout with a 4x4 via pattern. PCB
gerber files are available at request.
PRINTED CIRCUIT BOARD (PCB) LAYOUT
Because the TPA3004D2 is a class-D amplifier that switches at a high frequency, the layout of the printed circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
• Decoupling capacitors — The high-frequency 0.1-µF decoupling capacitors should be placed as close to the
PVCC (pin 14, 15, 22, 23, 38, 39, 46, 47) and AVCC (pin 33) terminals as possible. The V2P5 (pin 4)
capacitor, AVDD (pin 29) capacitor, and VCLAMP (pins 25, 36) capacitor should also be placed as close to the
device as possible. Large (10 µF or greater) bulk power supply decoupling capacitors should be placed near
the TPA3004D2 on the PVCCL, PVCCR, and AVCC terminals.
• Grounding — The AVCC (pin 33) decoupling capacitor, AVDD (pin 29) capacitor, V2P5 (pin 4) capacitor, COSC
(pin 28) capacitor, and ROSC (pin 27) resistor should each be grounded to analog ground (AGND, pin 26 and
pin 30). The PVCC (pin 9 and pin 16) decoupling capacitors should each be grounded to power ground
(PGND, pins 18, 19, 42, 43). Analog ground and power ground may be connected at the PowerPAD, which
should be used as a central ground connection or star ground for the TPA3004D2. Basically, an island should
be created with a single connection to PGND at the PowerPAD.
• Output filter — The ferrite EMI filter (Figure 41) should be placed as close to the output terminals as possible
for the best EMI performance. The LC filter (Figure 40 should be placed close to the outputs. The capacitors
used in both the ferrite and LC filters should be grounded to power ground.
• PowerPAD — The PowerPAD must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the PowerPAD thermal land should be 5 mm by 5 mm (197 mils by 197 mils).
The PowerPAD size measures 4.55 x 4.55 mm. Four rows of solid vias (four vias per row, 0.3302 mm or 13
mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a solid
copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not
thermal relief or webbed vias. For additional information, refer to the PowerPAD Thermally Enhanced
Package application note, TI literature number SLMA002.
For an example layout, see the TPA3004D2 Evaluation Module (TPA3004D2EVM) User Manual, TI (SLOU158).
Both the EVM user manual and the PowerPAD application note are available on the TI web site at
http://www.ti.com.
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THERMAL RESISTANCE
vs
COPPER AREA 2-LAYER PCB
THERMAL RESISTANCE
vs
COPPER AREA 4-LAYER PCB
35
θ JA – Thermal Resistance – °C/W
θ JA – Thermal Resistance – °C/W
35
30
25
20
15
1
1.5
2
2.5
3
3.5
4
Copper Area – sq. Inches
4.5
5
30
25
20
15
1
2
3
4
Copper Area – sq. Inches
5
Figure 47. Thermal Resistance
THERMAL RESISTANCE
vs
THERMAL VIA QUANTITY 2-LAYER PCB
θ JA – Thermal Resistance – °C/W
25
24
23
22
21
20
4
6
8
10
12
14
Thermal Via Quantity (13 Mil Diameter)
16
Figure 48. Thermal Resistance
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BASIC MEASUREMENT SYSTEM
This application note focuses on methods that use the basic equipment listed below:
• Audio analyzer or spectrum analyzer
• Digital multimeter (DMM)
• Oscilloscope
• Twisted pair wires
• Signal generator
• Power resistor(s)
• Linear regulated power supply
• Filter components
• EVM or other complete audio circuit
Figure 49 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine
wave is normally used as the input signal since it consists of the fundamental frequency only (no other harmonics
are present). An analyzer is then connected to the APA output to measure the voltage output. The analyzer must
be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to reduce the noise
and distortion injected into the APA through the power pins. A System Two audio measurement system (AP-II)
(Reference 1) by Audio Precision includes the signal generator and analyzer in one package.
The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling
capacitors, (CIN), so no additional coupling is required. The generator output impedance should be low to avoid
attenuating the test signal, and is important since the input resistance of APAs is not very high (about 10 kΩ).
Conversely the analyzer-input impedance should be high. The output impedance, ROUT, of the APA is normally in
the hundreds of milliohms and can be ignored for all but the power-related calculations.
Figure 49(a) shows a class-AB amplifier system. They take an analog signal input and produce an analog signal
output. These amplifier circuits can be directly connected to the AP-II or other analyzer input.
This is not true of the class-D amplifier system shown in Figure 49(b), which requires low pass filters in most
cases in order to measure the audio output waveforms. This is because it takes an analog input signal and
converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some
analyzers.
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TPA3004D2
SLOS407E – FEBRUARY 2003 – REVISED JANUARY 2011
www.ti.com
Power Supply
Signal
Generator
APA
RL
Analyzer
20 Hz – 20 kHz
(a) Basic Class–AB
Power Supply
Low–Pass RC
Filter
Signal
Generator
Class–D APA
RL
Low–Pass RC
Filter
Analyzer
20 Hz – 20 kHz
(b) Filter–Free and Traditional Class–D
(1)
For efficiency measurements with filter-free class-D, RL should be an inductive load like a speaker.
Figure 49. Audio Measurement Systems
The TPA3004D2 uses a modulation scheme that does not require an output filter for operation, but they do
sometimes require an RC low-pass filter when making measurements. This is because some analyzer inputs
cannot accurately process the rapidly changing square-wave output and therefore record an extremely high level
of distortion. The RC low-pass measurement filter is used to remove the modulated waveforms so the analyzer
can measure the output sine wave.
DIFFERENTIAL INPUT AND BTL OUTPUT
All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs.
Differential inputs have two input pins per channel and amplify the difference in voltage between the pins.
Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly
used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180
degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling the
output power to the load and eliminating a dc blocking capacitor.
A block diagram of the measurement circuit is shown in Figure 50. The differential input is a balanced input,
meaning the positive (+) and negative (–) pins will have the same impedance to ground. Similarly, the BTL output
equates to a balanced output.
36
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SLOS407E – FEBRUARY 2003 – REVISED JANUARY 2011
Evaluation Module
Audio Power
Amplifier
Generator
Analyzer
Low–Pass
RC Filter
CIN
VGEN
RGEN
RIN
ROUT
RIN
ROUT
CIN
RGEN
RL
Low–Pass
RC Filter
Twisted–Pair Wire
RANA
CANA
RANA
CANA
Twisted–Pair Wire
Figure 50. Differential Input—BTL output Measurement Circuit
The generator should have balanced outputs and the signal should be balanced for best results. An unbalanced
output can be used, but it may create a ground loop that will affect the measurement accuracy. The analyzer
must also have balanced inputs for the system to be fully balanced, thereby cancelling out any common mode
noise in the circuit and providing the most accurate measurement.
The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:
• Use a balanced source to supply the input signal.
• Use an analyzer with balanced inputs.
• Use twisted-pair wire for all connections.
• Use shielding when the system environment is noisy.
• Ensure the cables from the power supply to the APA, and from the APA to the load, can handle the large
currents (see Table 4).
Table 4 shows the recommended wire size for the power supply and load cables of the APA system. The real
concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations
are based on 12-inch long wire with a 20-kHz sine-wave signal at 25°C.
Table 4. Recommended Minimum Wire Size for Power Cables
POUT
(W)
RL
(Ω)
10
4
18
22
16
40
18
42
2
4
18
22
3.2
8.0
3.7
8.5
1
8
22
28
2.0
8.0
2.1
8.1
< 0.75
8
22
28
1.5
6.1
1.6
6.2
AWG Size
DC Power Loss
(mW)
AC Power Loss
(mW)
CLASS-D RC LOW-PASS FILTER
An RC filter is used to reduce the square-wave output when the analyzer inputs cannot process the pulse-width
modulated class-D output waveform. This filter has little effect on the measurement accuracy because the cutoff
frequency is set above the audio band. The high frequency of the square wave has negligible impact on
measurement accuracy because it is well above the audible frequency range and the speaker cone cannot
respond at such a fast rate. The RC filter is not required when an LC low-pass filter is used, such as with the
class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx).
The component values of the RC filter are selected using the equivalent output circuit as shown in Figure 51. RL
is the load impedance that the APA is driving for the test. The analyzer input impedance specifications should be
available and substituted for RANA and CANA. The filter components, RFILT and CFILT, can then be derived for the
system. The filter should be grounded to the APA near the output ground pins or at the power supply ground pin
to minimize ground loops.
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TPA3004D2
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Load
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RC Low–Pass Filters
RFILT
AP Analyzer Input
CFILT
VL= VIN
RL
CANA
RANA
CANA
RANA
VOUT
RFILT
CFILT
To APA
GND
Figure 51. Measurement Low-Pass Filter Derivation Circuit—Class-D APAs
The transfer function for this circuit is shown in Equation 10 where wO = REQCEQ, REQ = RFILT||RANA and CEQ =
(CFILT + CANA). The filter frequency should be set above fMAX, the highest frequency of the measurement
bandwidth, to avoid attenuating the audio signal. Equation 11 provides this cutoff frequency, fC. The value of
RFILT must be chosen large enough to minimize current that is shunted from the load, yet small enough to
minimize the attenuation of the analyzer-input voltage through the voltage divider formed by RFILT and RANA. A
rule of thumb is that RFILT should be small (~100 Ω) for most measurements. This reduces the measurement
error to less than 1% for RANA≥ 10 kΩ.
ǒ Ǔ
R
V
OUT
V
IN
f
C
+ Ǹ2
ǒ
+
R
ANA
)R
ANA
FILT
Ǔ
ǒ Ǔ
1 ) j ww
O
f
(10)
MAX
(11)
An exception occurs with the efficiency measurements, where RFILT must be increased by a factor of ten to
reduce the current shunted through the filter. CFILT must be decreased by a factor of ten to maintain the same
cutoff frequency. See Table 2 for the recommended filter component values.
Once fC is determined and RFILT is selected, the filter capacitance is calculated using Equation 11. When the
calculated value is not available, it is better to choose a smaller capacitance value to keep fC above the minimum
desired value calculated in Equation 12.
1
C
+
FILT
2p
f
R
C
FILT
(12)
Table 5 shows recommended values of RFILT and CFILT based on common component values. The value of fC
was originally calculated to be 28 kHz for an fMAX of 20 kHz. CFILT, however, was calculated to be 57000 pF, but
the nearest values of 56000 pF and 51000 pF were not available. A 47000 pF capacitor was used instead, and fC
is 34 kHz, which is above the desired value of 28 kHz.
Table 5. Typical RC Measurement Filter Values
MEASUREMENT
38
RFILT
CFILT
Efficiency
1000 Ω
5600 pF
All other measurements
100 Ω
56000 pF
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SLOS407E – FEBRUARY 2003 – REVISED JANUARY 2011
REVISION HISTORY
Changes from Original (February 2003) to Revision A
•
Page
Changed the data sheet From: Product Preview To Production Data ................................................................................. 1
Changes from Revision A (March 2003) to Revision B
Page
•
Updated the FUNCTIONAL BLOCK DIAGRAM ................................................................................................................... 3
•
Updated Figure 35 .............................................................................................................................................................. 20
•
Updated Figure 36 .............................................................................................................................................................. 21
•
Changed Figure 39 title From: Cutoff Frequency of 41 kHz, To: Cutoff Frequency of 27 kHz, ......................................... 24
•
Changed Figure 39 title From: Cutoff Frequency of 41 kHz, To: Cutoff Frequency of 27 kHz, ......................................... 25
•
Changed text in section SELECTION OF COSC AND ROSC From: ROSC (pin 20) and COSC (pin 21) To: ROSC
(pin 27) and COSC (pin 28) ................................................................................................................................................ 29
•
Added three paragraphs to the section BSN and BSP CAPACITORS .............................................................................. 30
•
Added two paragraphs to the section SHORT-CIRCUIT PROTECTION ........................................................................... 32
•
Added Note 1 to Figure 49 ................................................................................................................................................. 36
Changes from Revision B (August 2003) to Revision C
Page
•
Added 10µF between AVDD and AGND in Figure 35 ........................................................................................................ 20
•
Updated Figure 36 .............................................................................................................................................................. 21
•
Added section POWER-OFF POP REDUCTION ............................................................................................................... 32
Changes from Revision C (January 2004) to Revision D
•
Page
Changed the PO(max) Test Condition From: RL = 8 Ω To: RL = 8 Ω, VCC = 15 V ................................................................... 7
Changes from Revision D (September 2010) to Revision E
•
Page
Replaced the Dissipations Ratings table with the Thermal Information table. ..................................................................... 5
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39
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPA3004D2PHP
ACTIVE
HTQFP
PHP
48
250
RoHS & Green
NIPDAU
Level-4-260C-72 HR
-40 to 85
TPA3004D2
Samples
TPA3004D2PHPG4
ACTIVE
HTQFP
PHP
48
250
RoHS & Green
NIPDAU
Level-4-260C-72 HR
-40 to 85
TPA3004D2
Samples
TPA3004D2PHPR
ACTIVE
HTQFP
PHP
48
1000
RoHS & Green
NIPDAU
Level-4-260C-72 HR
-40 to 85
TPA3004D2
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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