TPA3005D2PHPR

TPA3005D2 www.ti.com SLOS427A – MAY 2004 – REVISED AUGUST 2010 6-W STEREO CLASS-D AUDIO POWER AMPLIFIER Check for Samples: TPA3005D2 FEATURES 1 • • 2 • • • • • • DESCRIPTION 6-W/Ch Into an 8-Ω Load From a 12-V Supply Up to 92% Efficient, Class-D Operation Eliminates Need For Heatsinks 8.5-V to 18-V Single-Supply Operation Four Selectable, Fixed Gain Settings Differential Inputs Minimizes Common-Mode Noise Space-Saving, Thermally Enhanced PowerPAD™ Packaging Thermal Protection and Short Circuit Pinout Similar to TPA3002D2, TPA3003D2, and TPA3004D2 The TPA3005D2 is a 6-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo speakers. The TPA3005D2 can drive stereo speakers as low as 8 Ω. The high efficiency of the TPA3005D2 eliminates the need for external heatsinks when playing music. The gain of the amplifier is controlled by two gain select pins. The gain selections are 15.3, 21.2, 27.2, and 31.8 dB. The outputs are fully protected against shorts to GND, VCC, and output-to-output shorts. Thermal protection ensures the maximum junction temperature is not exceeded. APPLICATIONS LCD Monitors and TVs All-In-One PCs PVCC 10 µF 10 µF PVCC 220 nF 220 nF BSRP PVCCR PVCCR ROUTP ROUTP PGNDR ROUTN PGNDR ROUTN NC NC LINN NC TPA3005D2 AVDDREF AVDD GAIN0 COSC GAIN1 ROSC 220 nF PVCC 0.1 µF 10 µF 10 µF BSLP PVCCL LOUTP LOUTP VCLAMPL PGNDL AGND NC PGNDL NC 0.1 µF 0.1 µF 10 µF AGND NC BSLN Gain Control LINP LOUTN 0.47 µF AVCC AVCC V2P5 LOUTN 0.47 µF NC RINP PVCCL 0.47 µF 1 µF VCLAMPR RINN 0.47 µF 0.47 µF Left Differential Inputs 0.1 µF SHUTDOWN PVCCL Right Differential Inputs PVCCR Shutdown/Mute Control PVCCR BSRN 0.1 µF PVCCL • • 1 µF 220 pF 120 kΩ 1 µF 220 nF PVCC † †Optimal output filter for EMI suppression 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2010, Texas Instruments Incorporated TPA3005D2 SLOS427A – MAY 2004 – REVISED AUGUST 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS (1) (2) TA PACKAGED DEVICE 48-PIN HTQFP (PHP) (1) (2) -40°C to 85°C TPA3005D2PHP The PHP package is available taped and reeled. To order a taped and reeled part, add the suffix R to the part number (e.g., TPA3005D2PHPR). For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) TPA3005D2 Supply voltage range AVCC, PVCC -0.3 V to 20 V SHUTDOWN -0.3 V to VCC + 0.3 V ≥6Ω Load Impedance, RL Input voltage range, VI GAIN0, GAIN1, RINN, RINP, LINN, LINP Continuous total power dissipation -0.3 V to 6 V See Thermal Information Table Operating free–air temperature range, TA - 40°C to 85°C Operating junction temperature range, TJ - 40°C to 150°C Storage temperature range, Tstg - 65°C to 150°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. THERMAL INFORMATION THERMAL METRIC (1) (2) TPA3005D2 qJA Junction-to-ambient thermal resistance 27.7 qJCtop Junction-to-case (top) thermal resistance 14.8 qJB Junction-to-board thermal resistance 9.4 yJT Junction-to-top characterization parameter 0.6 yJB Junction-to-board characterization parameter 5.6 qJCbot Junction-to-case (bottom) thermal resistance 0.3 (1) (2) UNITS PHP (48 PINS) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. RECOMMENDED OPERATING CONDITIONS MIN MAX 8.5 18 UNIT Supply voltage, VCC PVCC, AVCC High-level input voltage, VIH SHUTDOWN, GAIN0, GAIN1 Low-level input voltage, VIL SHUTDOWN, GAIN0, GAIN1 0.8 V SHUTDOWN, VI = VCC = 18 V 10 µA GAIN0, GAIN1, VI = 5.5 V, VCC = 18 V 1 µA SHUTDOWN, VI = 0 V, VCC = 18 V 1 µA GAIN0, GAIN1, VI = 5.5 V, VCC = 18 V 1 µA High-level input current, IIH Low-level input current, IIL Oscillator frequency, fOSC Frequency is set by selection of ROSC and COSC (see the Application Information Section). Operating free–air temperature, TA 2 Submit Documentation Feedback 2 V V 200 300 -40 85 kHz °C Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): TPA3005D2 TPA3005D2 www.ti.com SLOS427A – MAY 2004 – REVISED AUGUST 2010 DC ELECTRICAL CHARACTERISTICS TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS |VOO| Class-D output offset voltage (measured differentially) INN and INP connected together, Gain = 36 dB V2P5 2.5-V Bias voltage No load AVDD +5-V internal supply voltage IL = 10 mA, SHUTDOWN = 2 V, VCC = 8.5 V to 18 V PSRR Power supply rejection ratio VCC = 11.5 V to 12.5 V ICC Quiescent supply current SHUTDOWN = 2 V, no load ICC(SD) Quiescent supply current in shutdown mode SHUTDOWN = 0 V rDS(on) Drain-source on-state resistance VCC = 12 V, IO = 1 A, TJ = 25°C MIN TYP MAX 5 55 2.5 GAIN1 = 0.8 V 4.5 5 mV V 5.5 V 11 22 mA 1.6 25 µA -80 High side UNIT dB 600 Low side 500 Total mΩ 1100 1300 GAIN0 = 0.8 V 14.6 15.3 16.2 GAIN0 = 2 V 20.5 21.2 21.8 GAIN0 = 0.8 V 26.4 27.2 27.8 GAIN0 = 2 V 31.1 31.8 32.5 G Gain ton Turn-on time C(V2P5) = 1 µF, SHUTDOWN = 2 V 16 ms toff Turn-off time C(V2P5) = 1 µF, SHUTDOWN = 0.8 V 60 µs GAIN1 = 2 V dB AC ELECTRICAL CHARACTERISTICS TA = 25°C, VCC = 12 V, RL = 8 Ω, (unless otherwise noted) PARAMETER kSVR PO TEST CONDITIONS Supply voltage rejection ratio Continuous output power 200 mVPP ripple from 20 Hz to 1 kHz, Gain = 15.6 dB, Inputs ac-coupled to GND TYP 3 THD+N = 0.23%, f = 1 kHz, RL = 8 Ω 6 Total harmonic distortion plus noise PO = 1 W, f = 1 kHz, RL = 8 Ω Vn Output integrated noise floor 20 Hz to 22 kHz, A-weighted filter, Gain = 15.6 dB MAX -70 THD+N = 0.13%, f = 1 kHz, RL = 8 Ω THD+N UNIT dB W 0.1% -80 dB -93 dB 97 dB Thermal trip point 150 °C Thermal hystersis 20 °C Crosstalk SNR MIN Signal-to-noise ratio PO = 1 W, RL = 8 Ω, Gain = 15.6 dB, f = 1 kHz Maximum output at THD+N < 0.5%, f = 1 kHz, Gain = 15.6 dB Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): TPA3005D2 3 TPA3005D2 SLOS427A – MAY 2004 – REVISED AUGUST 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM V2P5 PVCC V2P5 VClamp Gen VCLAMPR BSRN PVCCR(2) Gate Drive RINN RINP ROUTN(2) Deglitch and PWM Mode Logic Gain Adj. V2P5 PGNDR BSRP PVCCR(2) Gate Drive GAIN0 GAIN1 Gain Control To Gain Adj. Blocks & Startup Logic 4 PGNDR V2P5 ROSC Ramp Generator COSC AVDDREF ROUTP(2) SC Detect Biases and References Startup and Protection Logic Thermal VDDok AVDD VCCok 5V LDO AVDD PVCC TTL Input Buffer (VCC Compl) SHUTDOWN VDD AVCC AVCC AGND(2) VClamp Gen VCLAMPL BSLN PVCCL(2) Gate Drive V2P5 LINN LINP Gain Adj. Deglitch and PWM Mode Logic LOUTN(2) PGNDL BSLP PVCCL(2) Gate Drive LOUTP(2) PGNDL 4 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): TPA3005D2 TPA3005D2 www.ti.com SLOS427A – MAY 2004 – REVISED AUGUST 2010 48 47 46 45 44 43 42 41 40 39 38 BSRP PVCCR PVCCR ROUTP ROUTP PGNDR PGNDR ROUTN ROUTN PVCCR PVCCR BSRN PHP PACKAGE (TOP VIEW) 37 SHUTDOWN 1 36 VCLAMPR RINN 2 35 NC RINP 3 34 NC V2P5 4 33 AVCC LINP 5 32 NC LINN 6 31 NC AVDDREF 7 30 AGND NC 8 29 AVDD GAIN0 9 28 COSC GAIN1 10 27 ROSC NC 11 26 AGND NC 12 25 VCLAMPL LOUTP BSLP PVCCL PGNDL PVCCL 24 LOUTP 20 21 22 23 PGNDL 18 19 LOUTN 15 16 17 LOUTN PVCCL BSLN 13 14 PVCCL TPA3005D2 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): TPA3005D2 5 TPA3005D2 SLOS427A – MAY 2004 – REVISED AUGUST 2010 www.ti.com TERMINAL FUNCTIONS PIN NAME PIN NUMBER I/O AGND 26, 30 - Analog ground for digital/analog cells in core AVCC 33 - High-voltage analog power supply, not connected internally to PVCCR or PVCCL AVDD 29 O 5-V Regulated output for use by internal cells and GAIN0, GAIN1 pins only. Not specified for driving other external circuitry. AVDDREF 7 O 5-V Reference output—connect to gain setting resistor or directly to GAIN0, GAIN1. BSLN 13 - Bootstrap I/O for left channel, negative high-side FET BSLP 24 - Bootstrap I/O for left channel, positive high-side FET BSRN 48 - Bootstrap I/O for right channel, negative high-side FET BSRP 37 - Bootstrap I/O for right channel, positive high-side FET COSC 28 I/O GAIN0 9 I Gain select least significant bit. TTL logic levels with compliance to AVDD. GAIN1 10 I Gain select most significant bit. TTL logic levels with compliance to AVDD. LINN 6 I Negative audio input for left channel LINP 5 I Positive audio input for left channel LOUTN 16, 17 O Class-D 1/2-H-bridge negative output for left channel LOUTP 20, 21 O Class-D 1/2-H-bridge positive output for left channel 8, 11, 12, 31, 32, 34, 35 - No internal connection PGNDL 18, 19 - Power ground for left channel H-bridge PGNDR 42, 43 - Power ground for right channel H-bridge PVCCL 14, 15 - Power supply for left channel H-bridge (internally connected to pins 22 and 23), not connected to PVCCR or AVCC. PVCCL 22, 23 - Power supply for left channel H-bridge (internally connected to pins 14 and 15), not connected to PVCCR or AVCC. PVCCR 38, 39 - Power supply for right channel H-bridge (internally connected to pins 46 and 47), not connected to PVCCL or AVCC. PVCCR 46, 47 - Power supply for right channel H-bridge (internally connected to pins 38 and 39), not connected to PVCCL or AVCC. RINP 3 I Positive audio input for right channel RINN 2 I Negative audio input for right channel ROSC 27 I/O I/O current setting resistor for ramp generator. ROUTN 44, 45 O Class-D 1/2-H-bridge negative output for right channel ROUTP 40, 41 O Class-D 1/2-H-bridge positive output for right channel SHUTDOWN 1 I Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to VCC. VCLAMPL 25 - Internally generated voltage supply for left channel bootstrap capacitors. VCLAMPR 36 - Internally generated voltage supply for right channel bootstrap capacitors. V2P5 4 O 2.5-V Reference for analog cells. Thermal Pad - - Connect to AGND and PGND—should be the center point for both grounds. Internal resistive connection to AGND. NC DESCRIPTION I/O for charge/discharging currents onto capacitor for ramp generator. TYPICAL CHARACTERISTICS Table 1. TABLE OF GRAPHS FIGURE THD+N Total harmonic distortion + noise vs Output power vs Frequency Closed loop response ICC 6 1, 2 3, 4, 5, 6 7 Supply current vs Output power 8 Efficiency vs Output power 9 Output power vs Supply voltage 10, 11 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): TPA3005D2 TPA3005D2 www.ti.com SLOS427A – MAY 2004 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) Table 1. TABLE OF GRAPHS (continued) Crosstalk vs Frequency 12 kSVR Supply ripple rejection ratio vs Frequency 13 CMRR Commom-mode rejection ratio vs Frequency 14 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 VCC = 12 V, RL = 8 W, Gain = 21.6 dB THD+N −Total Harmonic Distortion + Noise − % THD+N −Total Harmonic Distortion + Noise − % 10 1 1 kHz 0.1 20 Hz 0.01 20 m 20 kHz 100 m 1 VCC = 12 V, RL = 16 W, Gain = 21.6 dB 1 1 kHz 0.1 20 Hz 0.02 0.01 20 kHz 0.005 20 m 7 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY VCC = 12 V, RL = 16 W, Gain = 21.6 dB 1 0.1 PO = 2.5 W PO = 1 W PO = 0.5 W 0.005 20 10 Figure 2. 10 0.01 100 m 1 PO − Output Power − W Figure 1. THD+N −Total Harmonic Distortion + Noise − % THD+N −Total Harmonic Distortion + Noise − % PO − Output Power − W 100 1k f − Frequency − Hz 10 VCC = 18 V, RL = 16 W, Gain = 21.6 dB 1 PO = 0.5 W 0.1 PO = 1 W PO = 2.5 W 0.01 10 k 20 k 20 Figure 3. 100 1k f − Frequency − Hz 10 k 20 k Figure 4. Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): TPA3005D2 7 TPA3005D2 SLOS427A – MAY 2004 – REVISED AUGUST 2010 www.ti.com TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N −Total Harmonic Distortion + Noise − % THD+N −Total Harmonic Distortion + Noise − % 10 VCC = 12 V, RL = 8 W Gain = 21.6 dB 1 PO = 0.5 W PO = 1 W 0.1 PO = 2.5 W VCC = 18 V, RL = 8 W, Gain = 21.6 dB 1 PO = 2.5 W 0.1 PO = 1 W 0.01 PO = 5 W 0.005 0.01 20 100 1k f − Frequency − Hz 20 10 k 20 k 100 Figure 6. CLOSED LOOP RESPONSE SUPPLY CURRENT vs TOTAL OUTPUT POWER 10 k 20 k 1.4 150 32 100 Gain 50 24 Phase 20 0 16 Phase − 5 28 −50 12 VCC = 12 V, RL = 8 Ω, Gain = 32 dB 33 kHz, RC LPF 8 4 1 0.8 8W 0.6 16 W 0.4 −100 0.2 −150 0 0 10 100 VCC = 12 V, LC Filter, Resistive Load, Stereo Operation 1.2 ICC − Supply Current − A 36 1k 10k 80k 0 f − Frequency − Hz Figure 7. 8 1k f − Frequency − Hz Figure 5. 40 Gain − dB 10 2 4 6 8 PO − Total Output Power − W 10 12 Figure 8. Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): TPA3005D2 TPA3005D2 www.ti.com SLOS427A – MAY 2004 – REVISED AUGUST 2010 EFFICIENCY vs TOTAL OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 100 12 16 W 11 90 10 80 PO − Output Power − W 8W Efficiency − % 70 60 50 40 30 10 0 1 2 3 4 5 6 7 8 9 10 11 9 THD+N = 10% 8 7 6 5 THD+N = 1% 4 3 VCC = 12 V, LC Filter, Resistive Load, Stereo Operation 20 0 RL = 16 W 2 1 0 12 8 9 PO − Total Output Power − W 11 12 13 14 15 16 VCC − Supply Voltage − V Figure 9. Figure 10. OUTPUT POWER vs SUPPLY VOLTAGE CROSSTALK vs FREQUENCY 7 0 RL = 8 W −10 THD+N = 10% 6 −20 17 18 VCC = 12 V, PO = 2.5 W, Gain = 21.6 dB RL = 8 W −30 Crosstalk − dB PO − Output Power − W 10 5 4 THD+N = 1% −40 −50 −60 −70 3 −80 −90 −100 2 8 9 10 11 12 VCC − Supply Voltage − V 13 14 20 100 1k 10 k 20 k f − Frequency − Hz Figure 11. Figure 12. Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): TPA3005D2 9 TPA3005D2 SLOS427A – MAY 2004 – REVISED AUGUST 2010 www.ti.com SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY COMMON-MODE REJECTION RATIO vs FREQUENCY 0 −10 −20 CMRR − Common-Mode Rejection Ratio − dB k SVR − Supply Ripple Rejection Ratio − dB 0 VCC = 12 V, V(RIPPLE) = 200 mVPP, RL = 8 W, Gain = 15.6 dB −30 −40 −50 −60 −70 −80 −90 −100 20 VCC = 12 V, Gain = 15.6 dB, RL = 8 W, Output Referred −10 −20 −30 −40 −50 −60 −70 100 1k 10 k 20 k 20 f − Frequency − Hz Figure 13. 10 100 1k f − Frequency − Hz 10 k 20 k Figure 14. Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): TPA3005D2 TPA3005D2 www.ti.com SLOS427A – MAY 2004 – REVISED AUGUST 2010 APPLICATION INFORMATION * * PVCC 1 nF 1 nF PVCC 220 nF 220 nF 10 mF 10 mF 0.47 mF 0.47 mF 0.47 mF 0.47 mF BSRP PVCCR PVCCR ROUTP PGNDR PGNDR ROUTN ROUTN RINN NC RINP NC V2P5 AVCC LINP NC LINN 10 mF 10 mF 1 mF 220 pF 120 kW 1 mF 0.1 mF 10 mF 220 nF 220 nF PVCC 1 nF Chip ferrite bead (example: Fair-Rite 251206700743) BSLP VCLAMPL PVCCL NC PVCCL AGND LOUTP NC LOUTP ROSC PGNDL GAIN1 PGNDL COSC LOUTN AVDD GAIN0 0.1 mF 0.1 mF AGND NC BSLN Gain Control AVCC NC TPA3005D2 AVDDREF LOUTN 0.47 mF * 1 mF VCLAMPR PVCCL Left Differential Inputs PVCCR BSRN SHUTDOWN PVCCL Right Differential Inputs PVCCR Shutdown/Mute Control ROUTP 0.1 mF 0.1 mF 1 nF * PVCC * Figure 15. Stereo Class-D With Differential Inputs Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): TPA3005D2 11 TPA3005D2 SLOS427A – MAY 2004 – REVISED AUGUST 2010 www.ti.com CLASS-D OPERATION This section focuses on the class-D operation of the TPA3005D2. Traditional Class-D Modulation Scheme The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore, the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields 0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in Figure 16. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high, causing high loss and thus causing a high supply current. OUTP OUTN +12 V Differential Voltage Across Load 0V −12 V Current Figure 16. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an Inductive Load With No Input TPA3005D2 Modulation Scheme The TPA3005D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage. However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load. 12 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): TPA3005D2 TPA3005D2 www.ti.com SLOS427A – MAY 2004 – REVISED AUGUST 2010 OUTP OUTN Differential Voltage Across Load Output = 0 V +12 V 0V −12 V Current OUTP OUTN Differential Voltage Output > 0 V +12 V 0V Across Load −12 V Current Figure 17. The TPA3005D2 Output Voltage and Current Waveforms Into an Inductive Load Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 x VCC, and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive. The TPA3005D2 modulation scheme has little loss in the load without a filter because the pulses are short and the change in voltage is VCC instead of 2 x VCC. As the output power increases, the pulses widen, making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed. An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance than the speaker, which results in less power dissipation, therefore increasing efficiency. Effects of Applying a Square Wave Into a Speaker Audio specialists have advised for years not to apply a square wave to speakers. If the amplitude of the waveform is high enough and the frequency of the square wave is within the bandwidth of the speaker, the square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A 250-kHz switching frequency, however, does not significantly move the voice coil, as the cone movement is proportional to 1/f2 for frequencies beyond the audio band. Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): TPA3005D2 13 TPA3005D2 SLOS427A – MAY 2004 – REVISED AUGUST 2010 www.ti.com Damage may occur if the voice coil cannot handle the additional heat generated from the high-frequency switching current. The amount of power dissipated in the speaker may be estimated by first considering the overall efficiency of the system. If the on-resistance (rds(on)) of the output transistors is considered to cause the dominant loss in the system, then the maximum theoretical efficiency for the TPA3005D2 with an 8-Ω load is as follows: R 8 L Efficiency (theoretical, %) + 100% + 100% + 86% (8 ) 1.3) R )r L ds(on) (1) ǒ Ǔ The maximum measured output power is approximately 6 W with an 12-V power supply. The total theoretical power supplied (P(total)) for this worst-case condition would therefore be as follows: P O P + + 6 W + 6.98 W (total) 0.86 Efficiency (2) The efficiency measured in the lab using an 8-W speaker was 81%. The power not accounted for as dissipated across the rDS(on) may be calculated by simply subtracting the theoretical power from the measured power: Other losses + P (total) (measured) * P (total) (theoretical) + 7.41 * 6.98 + 0.43 W (3) The quiescent supply current at 12 V is measured to be 22 mA. It can be assumed that the quiescent current encapsulates all remaining losses in the device, i.e., biasing and switching losses. It may be assumed that any remaining power is dissipated in the speaker and is calculated as follows: P (dis) + 0.43 W * (12 V 22 mA) + 0.17 W (4) Note that these calculations are for the worst-case condition of 6 W delivered to the speaker. Because the 0.17 W is only 3% of the power delivered to the speaker, it may be concluded that the amount of power actually dissipated in the speaker is relatively insignificant. Furthermore, this power dissipated is well within the specifications of most loudspeaker drivers in a system, as the power rating is typically selected to handle the power generated from a clipping waveform. When to use an Output Filter Design the TPA3005D2 without the filter if the traces from amplifier to speaker are short (< 50 cm). Powered speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without a filter. Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high impedance at high frequencies, but low impedance at low frequencies. Use a LC output filter if there are low frequency (