TPA3100D2
HTQFP
QFN
www.ti.com
SLOS469F – OCTOBER 2005 – REVISED AUGUST 2010
20-W STEREO CLASS-D AUDIO POWER AMPLIFIER
Check for Samples: TPA3100D2
FEATURES
APPLICATIONS
•
•
•
•
•
•
1
•
•
•
•
•
•
20-W/ch into an 8-Ω Load From a 18-V Supply
10-W/ch into an 8-Ω Load From a 12-V Supply
15-W/ch into an 4-Ω Load From a 12-V Supply
Operates from 10 V to 26 V
92% Efficient Class-D Operation Eliminates
Need for Heat Sinks
Four Selectable, Fixed Gain Settings
Differential Inputs
Thermal and Short-Circuit Protection With
Auto Recovery Feature
Clock Output for Synchronization With
Multiple Class-D Devices
Surface Mount 7 mm × 7 mm, 48-pin QFN
Package
Surface Mount 9 mm × 9 mm, 48-pin HTQFP
Package
Televisions
DESCRIPTION
The TPA3100D2 is a 20-W (per channel) efficient,
Class-D audio power amplifier for driving bridged-tied
stereo speakers. The TPA3100D2 can drive stereo
speakers as low as 4 Ω. The high efficiency of the
TPA3100D2, 92%, eliminates the need for an
external heat sink when playing music.
The gain of the amplifier is controlled by two gain
select pins. The gain selections are 20, 26, 32,
36 dB.
The outputs are fully protected against shorts to
GND, VCC, and output-to-output shorts with an auto
recovery feature and monitor output.
Simplified Application Circuit
1 mF
RINP
1 mF
RINN
TV Audio
Processor
0.22 mF
TPA3100D2
1 mF
LINN
1 mF
BSRN
ROUTN
ROUTP
BSRP
LINP
Shutdown
Control
Mute Control
Gain Select
PGNDR
10 nF
VREG
MUTE
GAIN0
MSTR/SLV
Sync Control
SYNC
10 V to 26 V
1 mF
SHUTDOWN
FAULT
PVCCR
PVCCL
AVCC
AGND
1 mF
VBYP
ROSC
100 kW
GAIN1
Fault Flag
0.22 mF
VCLAMPR
BSLN
LOUTN
0.22 mF
LOUTP
BSLP
VCLAMPL
PGNDL
0.22 mF
1 mF
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2010, Texas Instruments Incorporated
TPA3100D2
SLOS469F – OCTOBER 2005 – REVISED AUGUST 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VCC
Supply voltage
VI
Input voltage
AVCC, PVCC
–0.3 V to 30 V
SHUTDOWN, MUTE
–0.3 V to VCC + 0.3 V
GAIN0, GAIN1, RINN, RINP, LINN, LINP, MSTR/SLV,
SYNC
–0.3 V to VREG + 0.5 V
Continuous total power dissipation
See Thermal Information Table
TA
Operating free-air temperature range
–40°C to 85°C
TJ
Operating junction temperature range (2)
–40°C to 150°C
Tstg
Storage temperature range
–65°C to 150°C
RLoad
Load Resistance
3.2 Ω Minimum
Human body model
Electrostatic discharge
Machine model
(4)
(3)
(2)
(3)
(4)
(5)
±2 kV
(all pins)
Charged-device model
(1)
(all pins)
(5)
±200 V
(all pins)
±500 V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The TPA3100D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical
Briefs SLMA002 for more information about using the HTQFP thermal pad.
In accordance with JEDEC Standard 22, Test Method A114-B.
In accordance with JEDEC Standard 22, Test Method A115-A
In accordance with JEDEC Standard 22, Test Method C101-A
THERMAL INFORMATION
THERMAL METRIC (1)
TPA3100D2
(2)
RGZ (48 PINS)
PHP (48 PINS)
25
28.7
qJA
Junction-to-ambient thermal resistance
qJCtop
Junction-to-case (top) thermal resistance
16.5
19.2
qJB
Junction-to-board thermal resistance
12.8
12.4
yJT
Junction-to-top characterization parameter
0.2
0.2
yJB
Junction-to-board characterization parameter
4.9
6.6
qJCbot
Junction-to-case (bottom) thermal resistance
1.0
0.7
(1)
(2)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
Supply voltage
PVCC, AVCC
VIH
High-level input voltage
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV,
SYNC
VIL
Low-level input voltage
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV,
SYNC
2
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MIN
MAX
10
26
2
UNIT
V
V
0.8
V
Copyright © 2005–2010, Texas Instruments Incorporated
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SLOS469F – OCTOBER 2005 – REVISED AUGUST 2010
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
SHUTDOWN, VI = VCC, VCC = 24 V
IIH
High-level input current
UNIT
125
MUTE, VI = VCC, VCC = 24 V
75
GAIN0, GAIN1, MSTR/SLV, SYNC, VI = VREG,
VCC = 24 V
2
SHUTDOWN, VI = 0, VCC = 24 V
2
IIL
Low-level input current
SYNC, MUTE, GAIN0, GAIN1, MSTR/SLV, VI = 0
V, VCC = 24 V
1
VOH
High-level output voltage
FAULT, IOH = 1 mA
VOL
Low-level output voltage
FAULT, IOL = -1 mA
fOSC
Oscillator frequency
Rosc Resistor = 100 kΩ, MSTR/SLV = 2 V
TA
Operating free-air temperature
µA
µA
VREG - 0.6
V
AGND + 0.4
V
200
300
kHz
–40
85
°C
DC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Class-D output offset voltage (measured
differentially)
VI = 0 V, Gain = 36 dB
Bypass reference for input amplifier
VBYP, no load
4-V internal supply voltage
VREG, no load, VCC = 10 V to 26 V
PSRR
DC Power supply rejection ratio
VCC = 12 V to 24 V, inputs ac coupled to AGND,
Gain = 36 dB
ICC
Quiescent supply current
SHUTDOWN = 2 V, MUTE = 0 V, no load, filter,
or snubber
22
26.5
ICC(SD)
Quiescent supply current in shutdown mode
SHUTDOWN = 0.8 V, no load, filter, or snubber
180
250
µA
ICC(MUTE)
Quiescent supply current in mute mode
MUTE = 2 V, no load, filter, or snubber
8
10
mA
rDS(on)
Drain-source on-state resistance
VCC = 12 V, IO = 500 mA,
TJ = 25°C
| VOS |
GAIN1 = 0.8 V
G
Gain
GAIN1 = 2 V
5
50
1.1
1.25
1.45
V
3.75
4
4.25
V
-70
mV
dB
High Side
200
Low side
200
Total
400
500
mA
mΩ
GAIN0 = 0.8 V
19
20
21
GAIN0 = 2 V
25
26
27
GAIN0 = 0.8 V
31
32
33
GAIN0 = 2 V
35
36
37
dB
dB
Gain matching
Between channels
tON
Turn-on time
C(VBYP) = 1 µF, SHUTDOWN = 2 V
2%
25
ms
tOFF
Turn-off time
C(VBYP) = 1 µF, SHUTDOWN = 0.8 V
0.1
ms
DC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Class-D output offset voltage (measured
differentially)
VI = 0 V, Gain = 36 dB
Bypass reference for input amplifier
VBYP, no load
4-V internal supply voltage
VREG, no load
PSRR
DC Power supply rejection ratio
VCC = 12 V to 24 V, Inputs ac coupled to AGND,
Gain = 36 dB
ICC
Quiescent supply current
SHUTDOWN = 2 V, MUTE = 0 V, no load, filter,
or snubber
18
22.5
ICC(SD)
Quiescent supply current in shutdown mode
SHUTDOWN = 0.8 V, no load, filter, or snubber
80
200
µA
ICC(MUTE)
Quiescent supply current in mute mode
MUTE = 2 V, no load, filter, or snubber
7
9
mA
| VOS |
5
50
1.1
1.25
1.45
V
3.75
4
4.25
V
-70
dB
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SLOS469F – OCTOBER 2005 – REVISED AUGUST 2010
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DC CHARACTERISTICS (continued)
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
rDS(on)
Drain-source on-state resistance
TEST CONDITIONS
VCC = 12 V, IO = 500 mA,
TJ = 25°C
GAIN1 = 0.8 V
G
Gain
GAIN1 = 2 V
MIN
TYP MAX
High Side
200
Low side
200
Total
400
500
UNIT
mΩ
GAIN0 = 0.8 V
19
20
21
GAIN0 = 2 V
25
26
27
GAIN0 = 0.8 V
31
32
33
GAIN0 = 2 V
35
36
37
dB
dB
tON
Turn-on time
C(VBYP) = 1 µF, SHUTDOWN = 2 V
25
ms
tOFF
Turn-off time
C(VBYP) = 1 µF, SHUTDOWN = 0.8 V
0.1
ms
AC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
–70
dB
THD+N = 7%, f = 1 kHz, VCC = 18 V
20.6
W
THD+N = 10%, f = 1 kHz, VCC = 18 V
21.8
W
KSVR
Supply ripple rejection
PO
Continuous output power
THD+N
Total harmonic distortion + noise
VCC = 18 V, f = 1 kHz, PO = 10 W (half-power)
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
Crosstalk
Signal-to-noise ratio
SNR
TYP
200 mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND
0.11%
100
µV
–80
dBV
VO = 1 Vrms, Gain = 20 dB, f = 1 kHz
–92
dB
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
102
dB
150
°C
30
°C
Thermal trip point
Thermal hysteresis
AC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
KSVR
PO
THD+N
Vn
SNR
Supply ripple rejection
Continuous output power
Total harmonic distortion + noise
TEST CONDITIONS
TYP
–70
THD+N = 7%, f = 1 kHz
9.4
THD+N = 10%, f = 1 kHz
10
THD+N = 7%, f = 1 kHz, RL = 4 Ω
15.6
THD+N = 10%, f = 1 kHz, RL = 4 Ω
16.4
RL = 8 Ω, f = 1 kHz, PO = 5 W (half-power)
0.11%
RL = 4 Ω, f = 1 kHz, PO = 8 W (half-power)
0.15%
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
Crosstalk
Po = 1 W, Gain = 20 dB, f = 1 kHz
Signal-to-noise ratio
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
Thermal trip point
Thermal hysteresis
4
MIN
200 mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND
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MAX
UNIT
dB
W
100
µV
–80
dBV
–94
dB
98
dB
150
°C
30
°C
Copyright © 2005–2010, Texas Instruments Incorporated
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SLOS469F – OCTOBER 2005 – REVISED AUGUST 2010
48 PIN, HTQFP PACKAGE
(TOP VIEW)
AVCC
AVCC
FAULT
MUTE
SHUTDOWN
BSRP
ROUTP
ROUTP
ROUTN
ROUTN
BSRN
GND
AVCC
NC
FAULT
MUTE
SHUTDOWN
BSRP
ROUTP
ROUTP
ROUTN
ROUTN
BSRN
NC
48 PIN, QFN PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
NC
RINN
RINP
AGND
LINP
LINN
NC
GAIN0
GAIN1
MSTR/SLV
SYNC
NC
48 47
1
36
2
35
3
34
4
33
5
6
7
32
Exposed
Thermal Pad
31
30
8
29
9
28
10
27
11
26
12
25
NC
PVCCR
PVCCR
PGNDR
PGNDR
VCLAMPR
VCLAMPL
PGNDL
PGNDL
PVCCL
PVCCL
NC
GND
RINN
RINP
AGND
LINP
LINN
GAIN0
GAIN0
GAIN1
MSTR/SLV
SYNC
GND
13 14 15 16 17 18 19 20 21 22 23 24
46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
32
5
Exposed
Thermal Pad
6
7
31
30
8
29
9
28
10
27
11
26
12
25
GND
PVCCR
PVCCR
PGNDR
PGNDR
VCLAMPR
VCLAMPL
PGNDL
PGNDL
PVCCL
PVCCL
GND
GND
ROSC
VREG
VBYP
AGND
BSLP
LOUTP
LOUTP
LOUTN
LOUTN
BSLN
GND
NC
ROSC
VREG
VBYP
AGND
BSLP
LOUTP
LOUTP
LOUTN
LOUTN
BSLN
NC
13 14 15 16 17 18 19 20 21 22 23 24
TERMINAL FUNCTIONS
TERMINAL
QFN
NO.
HTQFP
NO.
I/O
SHUTDOWN
44
44
I
Shutdown signal for IC (LOW = disabled, HIGH = operational). TTL logic
levels with compliance to AVCC.
RINN
2
2
I
Negative audio input for right channel. Biased at VREG/2.
RINP
3
3
I
Positive audio input for right channel. Biased at VREG/2.
LINN
6
6
I
Negative audio input for left channel. Biased at VREG/2.
LINP
5
5
I
Positive audio input for left channel. Biased at VREG/2.
GAIN0
8
7, 8
I
Gain select least significant bit. TTL logic levels with compliance to VREG.
GAIN1
9
9
I
Gain select most significant bit. TTL logic levels with compliance to VREG.
NAME
1, 12, 13,
24, 25, 36,
37
GND
DESCRIPTION
Connect to the thermal pad.
MUTE
45
45
I
Mute signal for quick disable/enable of outputs (HIGH = outputs high-Z,
LOW = outputs enabled). TTL logic levels with compliance to AVCC.
FAULT
46
46
O
TTL compatible output. HIGH = short-circuit fault. LOW = no fault. Only
reports short-circuit faults. Thermal faults are not reported on this terminal.
BSLP
18
18
I/O
Bootstrap I/O for left channel, positive high-side FET.
PVCCL
26, 27
26, 27
LOUTP
19, 20
19, 20
PGNDL
28, 29
28, 29
LOUTN
21, 22
21, 22
O
Class-D 1/2-H-bridge negative output for left channel.
BSLN
23
23
I/O
Bootstrap I/O for left channel, negative high-side FET.
VCLAMPL
30
30
VCLAMPR
31
31
BSRN
38
38
I/O
Bootstrap I/O for right channel, negative high-side FET.
ROUTN
39, 40
39, 40
O
Class-D 1/2-H-bridge negative output for right channel.
PGNDR
32, 33
32, 33
Power supply for left channel H-bridge, not internally connected to PVCCR
or AVCC.
O
Class-D 1/2-H-bridge positive output for left channel.
Power ground for left channel H-bridge.
Internally generated voltage supply for left channel bootstrap capacitor.
Internally generated voltage supply for right channel bootstrap capacitor.
Power ground for right channel H-bridge.
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
QFN
NO.
HTQFP
NO.
I/O
ROUTP
41, 42
41, 42
O
PVCCR
34, 35
34, 35
DESCRIPTION
Class-D 1/2-H-bridge positive output for right channel.
Power supply for right channel H-bridge, not connected to PVCCL or AVCC.
BSRP
43
43
AGND
4, 17
4, 17
ROSC
14
14
I/O
MSTR/SLV
10
10
I
SYNC
11
11
I/O
Clock input/output for synchronizing multiple class-D devices. Direction
determined by MSTR/SLV terminal. Input signal not to exceed VREG.
VBYP
16
16
O
Reference for preamplifier. Nominally equal to 1.25 V. Also controls start-up
time via external capacitor sizing.
VREG
15
15
O
4-V regulated output for use by internal cells, GAINx, MUTE, and
MSTR/SLV pins only. Not specified for driving other external circuitry.
AVCC
48
47, 48
Thermal Pad
-
Bootstrap I/O for right channel, positive high-side FET.
Analog ground for digital/analog cells in core.
I/O for current setting resistor of ramp generator.
Master/Slave select for determining direction of SYNC terminal.
HIGH=Master mode, SYNC terminal is an output; LOW = slave mode,
SYNC terminal accepts a clock input. TTL logic levels with compliance to
VREG.
High-voltage analog power supply. Not internally connected to PVCCR or
PVCCL.
1, 7, 12,
13, 24, 25,
36, 37, 47
NC
6
I/O
Not internally connected.
-
-
Connect to AGND and PGND – should be star point for both grounds.
Internal resistive connection to AGND and PGND. Thermal vias on the PCB
should connect this pad to a large copper area on an internal or bottom
layer for the best thermal performance. The Thermal Pad must be soldered
to the PCB for mechanical reliability.
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FUNCTIONAL BLOCK DIAGRAM
PVCCR
PVCCR
VCLAMPR
PVCCR
VBYP
BSRN
VBYP
AVCC
AVCC
Gain
RINN
Gate
Drive
Gain
Control
RINP
ROUTN
VClamp
Gen
PWM
Logic
PVCCR
VBYP
GAIN0
GAIN1
BSRP
Gain
Control
Gate
Drive
To Gain Adj.
Blocks and
Startup Logic
8
ROUTP
Gain
FAULT
PGNDR
SC
Detect
VBYP AVCC
Thermal
ROSC
VREG
Ramp
Generator
SYNC
Startup
Protection
Logic
Biases
and
References
MSTR/SLV
VREGok
PVCCL
AVCC
PVCCL
VCCok
VREG
VREG
4V Reg
PVCCL
SHUTDOWN
TLL Input
Buffer
(VCC Compliant)
MUTE
TLL Input
Buffer
(VCC Compliant)
BSLN
Gate
Drive
Gain
LINP
LOUTN
VClamp
Gen
VBYP
LINN
VCLAMPL
Gain
Control
PVCCL
BSLP
PWM
Logic
Gate
Drive
Gain
LOUTP
PGNDL
AGND
TYPICAL CHARACTERISTICS
Table 1. TABLE OF GRAPHS (1)
FIGURE
THD+N
Total harmonic distortion + noise
vs Frequency
1, 2, 3, 4
THD+N
Total harmonic distortion + noise
vs Output power
5, 6, 7, 8
Closed-loop response
vs Frequency
9, 10
Output power
vs Supply voltage
11. 12
Efficiency
vs Output power
13, 14
Supply current
vs Total output power
15, 16
Crosstalk
vs Frequency
17, 18
Supply ripple rejection ratio
vs Frequency
19, 20
VCC
kSVR
(1)
All graphs were measured using the TPA3100D2 EVM.
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TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N - Total Harmonic Distortion + Noise - %
RL = 8 W,
Gain = 20 dB
1
PO = 5 W
0.1
PO = 2.5 W
PO = 0.5 W
0.01
0.005
0.003
20
10
THD+N - Total Harmonic Distortion + Noise - %
10
VCC = 12 V,
100
10k 20k
1k
f - Frequency - Hz
RL = 8 W,
Gain = 20 dB
1
PO = 10 W
0.1
PO = 5 W
0.01
PO = 1 W
0.005
0.003
20
100
10k 20k
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
VCC = 24 V,
1
PO = 10 W
0.1
PO = 5 W
PO = 1 W
0.01
100
1k
f - Frequency - Hz
10k 20k
VCC = 12 V,
RL = 4 W,
Gain = 20 dB
PO = 5 W
1
PO = 10 W
0.1
PO = 1 W
0.01
0.005
0.003
20
Figure 3.
8
1k
f - Frequency - Hz
Figure 2.
RL = 8 W,
Gain = 20 dB
0.005
0.003
20
VCC = 18 V,
Figure 1.
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
100
1k
f - Frequency - Hz
10k 20k
Figure 4.
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THD+N - Total Harmonic Distortion + Noise - %
10
VCC = 12 V,
RL = 8 W,
Gain = 32 dB
1
10 kHz
0.1
0.05
1 kHz
0.02
20 Hz
0.01
10m
100m 200m
1
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
THD+N - Total Harmonic Distortion + Noise - %
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10 V = 18 V,
CC
RL = 8 W,
Gain = 32 dB
1
10 kHz
0.1
0.05
1 kHz
20 Hz
0.02
0.01
10m
10 20 40
100m 200m
PO - Output Power - W
Figure 5.
Figure 6.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
VCC = 24 V,
RL = 8 W,
Gain = 32 dB
1
10 kHz
0.1
0.05
1 kHz
20 Hz
0.02
0.01
10m
10 20 40
PO - Output Power - W
100m 200m
1
10 20 40
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
1
VCC = 12 V,
RL = 4 W,
Gain = 32 dB
1
10 kHz
0.1
1 kHz
0.05
20 kHz
0.02
0.01
10m
100m 200m
1
10 20 40
PO - Output Power - W
PO - Output Power - W
Figure 7.
Figure 8.
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CLOSED LOOP RESPONSE
vs
FREQUENCY
CLOSED LOOP RESPONSE
vs
FREQUENCY
Gain − dB
25
150
35
100
30
50
25
Phase
20
0
15
VCC = 12 V
RL = 8 W
VI = 0.1 Vrms
10
CI = 10 mF
Gain = 32 dB
RC Filter = 100 W, 10 nF
5
0
10
100
1k
10k
200
Gain
100
50
Phase
20
−50
15
−100
10
−150
5
−200
100k
0
0
−50
VCC = 24 V
RL = 8 W
VI = 0.1 Vrms
−100
CI = 10 mF
Gain = 32 dB
RC Filter = 100 W, 10 nF
−150
10
100
f − Frequency − Hz
1k
−200
100k
10k
f − Frequency − Hz
Figure 9.
Figure 10.
OUTPUT POWER
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
SUPPLY VOLTAGE
35
50
45
150
Phase − °
30
40
Phase − °
Gain
35
200
Gain − dB
40
RL = 8 W
Gain = 20 dB
RL = 4 W
Gain = 20 dB
30
PO − Output Power − W
PO − Output Power − W
40
35
30
25
THD+N = 10%
20
THD+N = 1%
15
25
THD+N = 10%
20
15
THD+N = 1%
10
10
Power Represented by
Dash Lines May Require
More Heatsinking.
5
0
10
12
14
16
18
20
22
24
26
Power Represented by
Dash Lines May Require
More Heatsinking.
5
28
0
10
VCC - Supply Voltage - V
12
13
14
15
16
VCC − Supply Voltage − V
Figure 11.
10
11
Figure 12.
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EFFICIENCY
vs
OUTPUT POWER
100
100
VCC = 12 V
90
90
80
80
VCC = 18 V
60
VCC = 24 V
50
VCC = 12 V
70
Efficiency − %
70
Efficiency − %
EFFICIENCY
vs
OUTPUT POWER
40
60
50
40
30
30
20
20
RL = 8 W
Gain = 32 dB
10
RL = 4 Ω
Gain = 32 dB
10
0
0
0
2
4
6
8
10
12
14
16
18
0
20
2
4
6
8
10
12
14 15
PO − Output Power (Per Channel) − W
PO − Output Power (Per Channel) − W
Figure 13.
Figure 14.
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER
2.5
3.5
RL = 8 Ω
Gain = 20 dB
VCC = 18 V
RL = 4 Ω
Gain = 20 dB
3
ICC − Supply Current − A
ICC − Supply Current − A
2
VCC = 12 V
1.5
VCC = 24 V
1
2.5
VCC = 12 V
2
1.5
1
0.5
Power Represented by
Dash Lines May Require
More Heatsinking.
0
0
10
20
30
Power Represented by
Dash Lines May Require
More Heatsinking.
0.5
40
0
0
PO − Total Output Power − W
Figure 15.
10
20
30
40
PO − Total Output Power − W
Figure 16.
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CROSSTALK
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
-40
-40
−60
VCC = 12 V
RL = 8 Ω
Gain = 20 dB
VO = 1 Vrms
−60
VCC = 24 V
RL = 8 Ω
Gain = 20 dB
VO = 1 Vrms
L to R
−80
R to L
−100
Crosstalk − dB
Crosstalk − dB
L to R
R to L
−100
−120
−120
−140
20
−80
100
1k
−140
20
10k 20k
100
Figure 17.
Figure 18.
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
−20
−30
−40
−50
−60
−70
−80
−90
−100
20
100
1k
10k 20k
−10
−20
VCC = 18 V
RL = 8 Ω
Gain = 20 dB
V(RIPPLE) = 200 mVPP
−30
−40
−50
−60
−70
−80
−90
−100
20
f − Frequency − Hz
100
1k
10k 20k
f − Frequency − Hz
Figure 19.
12
10k 20k
0
VCC = 12 V
RL = 8 Ω
Gain = 20 dB
V(RIPPLE) = 200 mVPP
kSVR − Supply Ripple Rejection Ratio − dB
kSVR − Supply Ripple Rejection Ratio − dB
0
−10
1k
f − Frequency − Hz
f − Frequency − Hz
Figure 20.
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Fault Output
Shutdown
and Mute
Control
APPLICATION INFORMATION
33 mH
1 nF
1 mF
20 W
8W
1 mF
1 nF
33 mH
20 W
10 V - 26 V
220nF
220nF
10 mF
Differential
Analog
Inputs
NC
BSRN
ROUTN
ROUTN
ROUTP
BSRP
ROUTP
MUTE
RINN
SHUTDOWN
1 mF
NC
NC
FAULT
AVCC
1 mF
NC
10 V - 26 V
1 mF
PVCCR
RINP
PVCCR
AGND
PGNDR
LINP
PGNDR
220 mF
1 mF
1 mF
1 mF
LINN
VCLAMPR
TPA3100D2
100 kW
BSLN
LOUTN
BSLP
LOUTN
PVCCL
NC
LOUTP
SYNC
LOUTP
PVCCL
AGND
PGNDL
MSTR/SLV
VBYP
GAIN1
VREG
PGNDL
NC
Synchronize Multiple
Class-D Devices
GAIN0
ROSC
4-Step
Gain Control
1 mF
VCLAMPL
NC
NC
1 mF
NC
220 mF
1 mF
10 V - 26 V
220nF
220nF
1 nF
10 nF
20 W
1 mF
1 nF
33 mH
1 mF
8W
20 W
33 mH
1 mF
Figure 21. Stereo Class-D With Differential Inputs (QFN)
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1 nF
33 mH
1 mF
20 W
8W
1 mF
1 nF
33 mH
20 W
10 V - 26 V
220nF
220nF
10 mF
Single-Ended
Analog
Inputs
NC
BSRN
ROUTN
ROUTN
ROUTP
BSRP
ROUTP
MUTE
RINN
SHUTDOWN
1 mF
NC
NC
FAULT
AVCC
1 mF
NC
10 V - 26 V
1 mF
PVCCR
RINP
PVCCR
AGND
PGNDR
LINP
PGNDR
220 mF
1 mF
1 mF
1 mF
VCLAMPR
TPA3100D2
100 kW
BSLN
BSLP
LOUTN
PVCCL
NC
LOUTN
SYNC
LOUTP
PVCCL
LOUTP
MSTR/SLV
VBYP
PGNDL
AGND
GAIN1
VREG
PGNDL
NC
Synchronize Multiple
Class-D Devices
GAIN0
ROSC
4-Step
Gain Control
1 mF
VCLAMPL
NC
NC
1 mF
LINN
NC
220 mF
1 mF
10 V - 26 V
220nF
220nF
1 nF
10 nF
20 W
1 mF
1 nF
33 mH
1 mF
8W
20 W
33 mH
1 mF
Figure 22. Stereo Class-D With Single-Ended Inputs (QFN)
14
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Control
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33 mH
1 nF
1 mF
20 W
8W
1 mF
1 nF
33 mH
20 W
10 V - 26 V
220nF
220nF
10 mF
Differential
Analog
Inputs
BSRN
GND
ROUTN
ROUTN
ROUTP
ROUTP
BSRP
MUTE
FAULT
RINN
SHUTDOWN
1 mF
AVCC
GND
AVCC
1 mF
10 V - 26 V
GND
1 mF
PVCCR
RINP
PVCCR
AGND
PGNDR
220 mF
1 mF
1 mF
LINP
PGNDR
1 mF
TPA3100D2
LINN
VCLAMPR
1 mF
BSLN
BSLP
GND
PVCCL
GND
LOUTN
SYNC
LOUTP
PVCCL
LOUTN
MSTR/SLV
LOUTP
PGNDL
AGND
GAIN1
VBYP
PGNDL
VREG
GAIN0
GND
Synchronize Multiple
Class-D Devices
VCLAMPL
ROSC
4-Step
Gain Control
GAIN0
1 mF
220 mF
1 mF
GND
10 V - 26 V
100 kW
220nF
220nF
10 nF
1 nF
1 mF
20 W
1 nF
33 mH
1 mF
8W
20 W
33 mH
1 mF
Figure 23. Stereo Class-D With Differential Inputs (HTQFP)
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SLOS469F – OCTOBER 2005 – REVISED AUGUST 2010
33 mH
1 nF
1 mF
20 W
8W
1 mF
1 nF
33 mH
20 W
10 V - 26 V
220nF
220nF
10 mF
Single-Ended
Analog
Inputs
RINN
BSRN
GND
ROUTN
ROUTN
ROUTP
BSRP
ROUTP
MUTE
FAULT
SHUTDOWN
1 mF
AVCC
GND
AVCC
1 mF
10 V - 26 V
GND
1 mF
PVCCR
RINP
PVCCR
AGND
PGNDR
220 mF
1 mF
1 mF
LINP
PGNDR
1 mF
TPA3100D2
LINN
VCLAMPR
1 mF
BSLN
BSLP
GND
PVCCL
GND
LOUTN
SYNC
LOUTN
PVCCL
LOUTP
MSTR/SLV
LOUTP
PGNDL
AGND
GAIN1
VBYP
PGNDL
VREG
GAIN0
ROSC
Synchronize Multiple
Class-D Devices
VCLAMPL
GND
4-Step
Gain Control
GAIN0
1 mF
220 mF
1 mF
GND
10 V - 26 V
100 kW
220nF
10 nF
220nF
1 nF
1 mF
20 W
1 nF
33 mH
1 mF
8W
20 W
33 mH
1 mF
Figure 24. Stereo Class-D With Single-Ended Inputs (HTQFP)
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SLOS469F – OCTOBER 2005 – REVISED AUGUST 2010
CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3100D2.
Traditional Class-D Modulation Scheme
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore,
the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields
0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 25. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,
causing high loss and thus causing a high supply current.
OUTP
OUTN
+12 V
Differential Voltage
Across Load
0V
-12 V
Current
Figure 25. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms into an
Inductive Load With No Input
TPA3100D2 Modulation Scheme
The TPA3100D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater
than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and
OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most
of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.
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OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
+12 V
0V
-12 V
Current
OUTP
OUTN
Differential
Voltage
Across
Load
Output > 0 V
+12 V
0V
-12 V
Current
Figure 26. The TPA3100D2 Output Voltage and Current Waveforms Into an Inductive Load
Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 x VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3100D2 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 x VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
When to Use an Output Filter for EMI Suppression
Design the TPA3100D2 without the filter if the traces from amplifier to speaker are short (< 10 cm). Powered
speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without
a filter.
18
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Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and
CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high
impedance at high frequencies, but low impedance at low frequencies.
Use an LC output filter if there are low frequency (