TPA3107D2
HTQFP
www.ti.com
SLOS509B – OCTOBER 2006 – REVISED JULY 2007
15-W STEREO CLASS-D AUDIO POWER AMPLIFIER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
15-W/ch into an 8-Ω Load From a 16-V Supply
Operates from 10 V to 26 V
Efficient Class-D Operation Eliminates the
Need for Heat Sinks
Four Selectable, Fixed Gain Settings
Differential Inputs
Thermal and Short-Circuit Protection With
Auto Recovery Feature
Clock Output for Synchronization With
Multiple Class-D Devices
Surface Mount 10 mm × 10 mm, 64-pin HTQFP
Package
Televisions
DESCRIPTION
The TPA3107D2 is a 15-W (per channel) efficient,
Class-D audio power amplifier for driving bridged-tied
stereo speakers. The TPA3107D2 can drive stereo
speakers as low as 6 Ω. The high efficiency of the
TPA3107D2, 87%, eliminates the need for an
external heat sink when playing music.
The gain of the amplifier is controlled by two gain
select pins. The gain selections are 20, 26, 32,
36 dB.
The outputs are fully protected against shorts to
GND, VCC, and output-to-output shorts with an auto
recovery feature and monitor output.
Simplified Application Circuit
1 mF
RINP
1 mF
RINN
TV Audio
Processor
0.22 mF
TPA3107D2
1 mF
LINN
1 mF
BSRN
ROUTN
ROUTP
BSRP
LINP
Shutdown
Control
Mute Control
PGNDR
10 nF
VREG
MUTE
Gain Select
MSTR/SLV
Sync Control
SYNC
FAULT
PVCCR
PVCCL
AVCC
AGND
1 mF
VBYP
ROSC
100 kW
GAIN1
10 V to 26 V
1 mF
SHUTDOWN
GAIN0
Fault Flag
0.22 mF
VCLAMPR
BSLN
LOUTN
0.22 mF
LOUTP
BSLP
VCLAMPL
PGNDL
0.22 mF
1 mF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
TPA3107D2
www.ti.com
SLOS509B – OCTOBER 2006 – REVISED JULY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VCC
Supply voltage
VI
Input voltage
AVCC, PVCC
–0.3 V to 30 V
SHUTDOWN, MUTE
–0.3 V to VCC + 0.3 V
GAIN0, GAIN1, RINN, RINP, LINN, LINP, MSTR/SLV, SYNC
–0.3 V to VREG + 0.5 V
Continuous total power dissipation
See Dissipation Rating
Table
TA
Operating free-air temperature range
–40°C to 85°C
TJ
Operating junction temperature range (2)
–40°C to 150°C
Tstg
Storage temperature range
–65°C to 150°C
Human body model
Electrostatic
discharge
(1)
(3)
Charged-device model
±2 kV
(all pins)
(4)
All pins except BS pins
±500 V
BS Pins – BSLP, BSLN, BSRP, and BSRN
±250 V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The TPA3107D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical
Briefs SLMA002 for more information about using the HTQFP thermal pad.
In accordance with JEDEC Standard 22, Test Method A114-B.
In accordance with JEDEC Standard 22, Test Method C101-A
(2)
(3)
(4)
TYPICAL DISSIPATION RATINGS
PACKAGE (1)
TA ≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
64-pin PAP (HTQFP)
5.43 W
43.5 mW/°C (2)
3.47 W
2.82 W
(1)
(2)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
This data was taken using a 2 oz trace and copper pad that is soldered directly to a 2-layer high-k PCB (EVM). These are typical values.
See TI Technical Briefs SLMA002 for more information about using the HTQFP thermal pad.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX
10
26
Supply voltage
PVCC, AVCC
VIH
High-level input voltage
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV, SYNC
VIL
Low-level input voltage
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV, SYNC
0.8
SHUTDOWN, VI = VCC, VCC = 24 V
125
IIH
2
TEST CONDITIONS
VCC
High-level input current
2
MUTE, VI = VCC, VCC = 24 V
75
2
SHUTDOWN, VI = 0, VCC = 24 V
2
IIL
Low-level input current
SYNC, MUTE, GAIN0, GAIN1, MSTR/SLV, VI = 0 V,
VCC = 24 V
1
VOH
High-level output voltage
FAULT, IOH = 1 mA
VOL
Low-level output voltage
FAULT, IOL = -1 mA
fOSC
Oscillator frequency
ROSC Resistor = 100 kΩ
RL
Load Resistance
TA
Operating free-air temperature
VREG - 0.6
µA
µA
V
300
kHz
85
°C
Ω
6
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V
V
AGND + 0.4
–40
V
V
GAIN0, GAIN1, MSTR/SLV, SYNC, VI = VREG,
VCC = 24 V
200
UNIT
TPA3107D2
www.ti.com
SLOS509B – OCTOBER 2006 – REVISED JULY 2007
DC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
| VOS |
PSRR
ICC
rDS(on)
TEST CONDITIONS
Class-D output offset voltage (measured
differentially)
VI = 0 V, Gain = 36 dB
Bypass reference for input amplifier
VBYP, no load
4-V internal supply voltage
VREG, no load, VCC = 10 V to 26 V
DC Power supply rejection ratio
VCC = 12 V to 24 V, inputs ac coupled to AGND,
Gain = 36 dB
Quiescent supply current
SHUTDOWN = 2 V, MUTE = 0 V, no load
Quiescent supply current in mute mode
MUTE = 2 V, no load
Drain-source on-state resistance
VCC = 12 V, IO = 500 mA,
TJ = 25°C
Gain
GAIN1 = 2 V
TYP MAX
UNIT
5
50
1.1
1.25
1.45
V
3.75
4
4.25
V
-70
Quiescent supply current in shutdown mode SHUTDOWN = 0.8 V, no load
GAIN1 = 0.8 V
G
MIN
mV
dB
22
26.5
300
400
µA
8
10
mA
High Side
370
Low side
370
Total
780
950
mA
mΩ
GAIN0 = 0.8 V
19
20
21
GAIN0 = 2 V
25
26
27
GAIN0 = 0.8 V
31
32
33
GAIN0 = 2 V
35
36
37
dB
dB
Gain matching
Between channels
tON
Turn-on time
C(VBYP) = 1 µF, SHUTDOWN = 2 V
2%
25
ms
tOFF
Turn-off time
C(VBYP) = 1 µF, SHUTDOWN = 0.8 V
0.1
ms
DC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
| VOS |
PSRR
ICC
rDS(on)
TEST CONDITIONS
Class-D output offset voltage (measured
differentially)
VI = 0 V, Gain = 36 dB
Bypass reference for input amplifier
VBYP, no load
4-V internal supply voltage
VREG, no load
DC Power supply rejection ratio
VCC = 12 V to 24 V, Inputs ac coupled to AGND,
Gain = 36 dB
Quiescent supply current
SHUTDOWN = 2 V, MUTE = 0 V, no load
Quiescent supply current in mute mode
MUTE = 2 V, no load
Drain-source on-state resistance
VCC = 12 V, IO = 500 mA,
TJ = 25°C
Gain
GAIN1 = 2 V
TYP MAX
UNIT
5
50
1.1
1.25
1.45
V
3.75
4
4.25
V
-70
Quiescent supply current in shutdown mode SHUTDOWN = 0.8 V, no load
GAIN1 = 0.8 V
G
MIN
mV
dB
18
22.5
180
300
µA
7
9
mA
High Side
350
Low side
350
Total
780
950
mA
mΩ
GAIN0 = 0.8 V
19
20
21
GAIN0 = 2 V
25
26
27
GAIN0 = 0.8 V
31
32
33
GAIN0 = 2 V
35
36
37
dB
dB
tON
Turn-on time
C(VBYP) = 1 µF, SHUTDOWN = 2 V
25
ms
tOFF
Turn-off time
C(VBYP) = 1 µF, SHUTDOWN = 0.8 V
0.1
ms
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TPA3107D2
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SLOS509B – OCTOBER 2006 – REVISED JULY 2007
AC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
KSVR
Supply ripple rejection
200 mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND
PO
Continuous output power
THD+N = 0.1%, f = 1 kHz (thermally limited)
THD+N
Total harmonic distortion + noise
f = 1 kHz, PO = 7.5 W (half-power)
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
Crosstalk
VO = 1 Vrms, Gain = 20 dB, f = 1 kHz
Signal-to-noise ratio
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
SNR
MIN
TYP
MAX
UNIT
–70
dB
15
W
0.08%
Thermal trip point
Thermal hysteresis
125
µV
–78
dBV
–92
dB
102
dB
150
°C
20
°C
AC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
KSVR
Supply ripple rejection
PO
Continuous output power
TEST CONDITIONS
THD+N = 7%, f = 1 kHz
8.7
THD+N = 10%, f = 1 kHz
9.2
THD+N = 10%, f = 1 kHz, VCC = 16 V
15
Total harmonic distortion + noise
RL = 8 Ω, f = 1 kHz, PO = 5 W
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
Crosstalk
Po = 1 W, Gain = 20 dB, f = 1 kHz
Signal-to-noise ratio
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
Thermal trip point
Thermal hysteresis
4
TYP
–70
THD+N
SNR
MIN
200 mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND
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MAX
UNIT
dB
W
0.11%
125
µV
–78
dBV
–94
dB
96
dB
150
°C
30
°C
TPA3107D2
www.ti.com
SLOS509B – OCTOBER 2006 – REVISED JULY 2007
AVCC
FAULT
MUTE
SHUTDOWN
NC
NC
NC
NC
NC
BSRP
ROUTP
ROUTP
ROUTN
ROUTN
BSRN
NC
64 PIN, HTQFP PACKAGE
(TOP VIEW)
64 63
NC
NC
NC
NC
RINN
RINP
AGND
LINP
LINN
GAIN0
GAIN1
MSTR/SLV
NC
NC
NC
NC
62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
2
47
3
46
4
45
5
44
43
6
7
Exposed
Thermal Pad
8
42
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
NC
NC
PVCCR
PVCCR
PGNDR
PGNDR
NC
VCLAMPR
VCLAMPL
NC
PGNDL
PGNDL
PVCCL
PVCCL
NC
NC
SYNC
ROSC
VREG
VBYP
AGND
NC
NC
NC
NC
BSLP
LOUTP
LOUTP
LOUTN
LOUTN
BSLN
NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
SHUTDOWN
61
I
Shutdown signal for IC (LOW = disabled, HIGH = operational). TTL logic levels
with compliance to AVCC. (Active low)
RINN
5
I
Negative audio input for right channel. Biased at VREG/2.
RINP
6
I
Positive audio input for right channel. Biased at VREG/2.
LINN
9
I
Negative audio input for left channel. Biased at VREG/2.
LINP
8
I
Positive audio input for left channel. Biased at VREG/2.
GAIN0
10
I
Gain select least significant bit. TTL logic levels with compliance to VREG.
GAIN1
11
I
Gain select most significant bit. TTL logic levels with compliance to VREG.
MUTE
62
I
Mute signal for quick disable/enable of outputs (HIGH = outputs high-Z, LOW =
outputs enabled). TTL logic levels with compliance to AVCC. (Active high)
FAULT
63
O
TTL compatible output. HIGH = short-circuit fault. LOW = no fault. Only reports
short-circuit faults. Thermal faults are not reported on this terminal.
BSLP
26
I/O
Bootstrap I/O for left channel, positive high-side FET.
Power supply for left channel H-bridge, not internally connected to PVCCR or
AVCC.
PVCCL
35, 36
LOUTP
27, 28
PGNDL
37, 38
LOUTN
29, 30
O
Class-D 1/2-H-bridge negative output for left channel.
BSLN
31
I/O
Bootstrap I/O for left channel, negative high-side FET.
VCLAMPL
40
VCLAMPR
41
BSRN
50
I/O
Bootstrap I/O for right channel, negative high-side FET.
ROUTN
51, 52
O
Class-D 1/2-H-bridge negative output for right channel.
PGNDR
43, 44
O
Class-D 1/2-H-bridge positive output for left channel.
Power ground for left channel H-bridge.
Internally generated voltage supply for left channel bootstrap capacitor.
Internally generated voltage supply for right channel bootstrap capacitor.
Power ground for right channel H-bridge.
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SLOS509B – OCTOBER 2006 – REVISED JULY 2007
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
ROUTP
53, 54
PVCCR
45, 46
O
DESCRIPTION
Class-D 1/2-H-bridge positive output for right channel.
Power supply for right channel H-bridge, not connected to PVCCL or AVCC.
BSRP
55
AGND
7, 21
ROSC
18
I/O
MSTR/SLV
12
I
Master/Slave select for determining direction of SYNC terminal. HIGH=Master
mode, SYNC terminal is an output; LOW = slave mode, SYNC terminal accepts a
clock input. TTL logic levels with compliance to VREG.
SYNC
17
I/O
Clock input/output for synchronizing multiple class-D devices. Direction determined
by MSTR/SLV terminal. Input signal not to exceed VREG.
VBYP
20
O
Reference for preamplifier. Nominally equal to 1.25 V. Also controls start-up time
via external capacitor sizing.
VREG
19
O
4-V regulated output for use by internal cells, GAINx, MUTE, and MSTR/SLV pins
only. Not specified for driving other external circuitry.
AVCC
NC
Thermal Pad
6
I/O
I/O
Analog ground for digital/analog cells in core.
64
I/O for current setting resistor of ramp generator.
High-voltage analog power supply. Not internally connected to PVCCR or PVCCL.
1-4, 13-16,
22-25,
32-34, 39,
42, 47-49,
56-60
-
Bootstrap I/O for right channel, positive high-side FET.
Not internally connected.
-
Connect to AGND and PGND – should be star point for both grounds. Internal
resistive connection to AGND and PGND. Thermal vias on the PCB should
connect this pad to a large copper area on an internal or bottom layer for the best
thermal performance. The Thermal Pad must be soldered to the PCB for
mechanical reliability.
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SLOS509B – OCTOBER 2006 – REVISED JULY 2007
FUNCTIONAL BLOCK DIAGRAM
PVCCR
PVCCR
VCLAMPR
PVCCR
VBYP
BSRN
VBYP
AVCC
AVCC
Gain
Control
RINN
RINP
Gate
Drive
Gain
Control
VClamp
Gen
PWM
Logic
BSRP
Gain
Control
8
Gate
Drive
To Gain Adj.
Blocks and
Startup Logic
ROUTP
Gain
FAULT
SC
Detect
VBYP AVCC
ROSC
Ramp
Generator
SYNC
Thermal
Biases
and
Reference
s
MSTR/SLV
VREG
Startup
Protection
Logic
VREGok
PGNDR
VREG
PVCCL
AVCC
PVCCL
VCCok
4V Reg
VREG
PVCCL
SHUTDOWN
TLL Input
Buffer
(VCC Compliant)
MUTE
TLL Input
Buffer
(VCC Compliant)
VCLAMPL
BSLN
Gate
Drive
Gain
Control
LOUTN
VClamp
Gen
VBYP
LINP
PVCCR
VBYP
GAIN0
GAIN1
LINN
ROUTN
Gate
Drive
Gain
PVCCL
BSLP
PWM
Logic
Gain
Control
LOUTP
PGNDL
AGND
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TPA3107D2
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SLOS509B – OCTOBER 2006 – REVISED JULY 2007
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS (1) (2)
FIGURE
THD+N
Total harmonic distortion + noise
vs Frequency
1, 2, 3, 4, 5
THD+N
Total harmonic distortion + noise
vs Output power
6, 7, 8, 9, 10
Closed-loop response
vs Frequency
Output power
vs Supply voltage
13
Supply current
vs Total output power
14
System efficiency
vs Output power
Crosstalk
vs Frequency
16, 17
Supply ripple rejection ratio
vs Frequency
18
VCC
kSVR
(1)
(2)
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
THD+N - Total Harmonic Distortion + Noise - %
10
THD+N - Total Harmonic Distortion + Noise - %
15
All graphs were measured using the TPA3107D2 EVM.
Power generated beyond normal and recommended operating conditions may require additional heatsinking.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
VCC = 12 V
RL = 8 W
Gain = 20 dB
1
PO = 5 W
0.1
PO = 2.5 W
0.01
PO = 1 W
0.001
20
8
11, 12
100
1k
10k 20k
VCC = 18 V
RL = 8 W
Gain = 20 dB
1
PO = 5 W
0.1
PO = 2.5 W
0.01
PO = 1 W
0.001
20
100
1k
f − Frequency − Hz
f − Frequency − Hz
Figure 1.
Figure 2.
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SLOS509B – OCTOBER 2006 – REVISED JULY 2007
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
VCC = 24 V
RL = 8 W
Gain = 20 dB
1
0.1
PO = 1 W
PO = 10 W
0.01
PO = 5 W
0.001
20
100
1k
PO = 10 W
0.1
PO = 1 W
0.01
PO = 5 W
100
1k
10k 20k
f − Frequency − Hz
Figure 3.
Figure 4.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
1
f − Frequency − Hz
VCC = 24 V
RL = 6 W
Gain = 20 dB
1
PO = 1 W
PO = 10 W
0.01
PO = 5 W
0.001
20
RL = 6 W
Gain = 20 dB
0.001
20
10k 20k
10
0.1
VCC = 18 V
100
1k
10k 20k
VCC = 12 V
RL = 8 W
Gain = 20 dB
1
10 kHz
1 kHz
0.1
20 Hz
0.01
10 m
100 m
1
f − Frequency − Hz
PO − Output Power − W
Figure 5.
Figure 6.
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40
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SLOS509B – OCTOBER 2006 – REVISED JULY 2007
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
20
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
20
VCC = 18 V
RL = 8 W
Gain = 20 dB
1
10 kHz
1 kHz
0.1
20 Hz
0.01
10 m
100 m
10 20
1
40
1
10 kHz
1 kHz
0.1
20 Hz
0.01
10 m
100 m
10 20 40
1
PO − Output Power − W
Figure 7.
Figure 8.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
VCC = 18 V
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
RL = 8 W
Gain = 20 dB
PO − Output Power − W
70
20
VCC = 24 V
10
RL = 8 W
Gain = 32 dB
10
1
10 kHz
1 kHz
0.1
20 Hz
0.01
10 m
100 m
1
10 20 30
VCC = 24 V
RL = 8 W
Gain = 32 dB
1
10 kHz
1 kHz
0.1
20 Hz
0.01
10 m
100 m
1
PO − Output Power − W
PO − Output Power − W
Figure 9.
Figure 10.
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SLOS509B – OCTOBER 2006 – REVISED JULY 2007
Gain
Phase
VCC = 12 V
RL = 8 W
VI = 0.1 Vrms
CI = 10 mF
Gain = 32 dB
RC filter = 100 W, 10 nF
10
100
1k
10 k
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
Gain
Phase
VCC = 24 V
RL = 8 W
VI = 0.1 Vrms
CI = 10 mF
Gain = 32 dB
RC filter = 100 W, 10 nF
10
100
f - Frequency - Hz
32.5
1k
10 k
f - Frequency - Hz
Figure 11.
Figure 12.
OUTPUT POWER
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER
37.5
35
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
100 k
Phase − o
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
100 k
Gain − dB
CLOSED LOOP RESPONSE
vs
FREQUENCY
Phase − o
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
2.5
RL = 8 Ω
Gain = 32 dB
RL = 8 W
Gain = 20 dB
2
ICC − Supply Current − A
30
PO − Output Power − W
Gain − dB
CLOSED LOOP RESPONSE
vs
FREQUENCY
27.5
25
22.5
THD+N = 10%
20
17.5
THD+N = 1%
15
12.5
VCC = 18 V
VCC = 12 V
1.5
VCC = 24 V
1
0.5
10
7.5
5
10
12
14
16
18
20
22
24
26
0
0
VCC - Supply Voltage - V
10
20
30
40
PO − Total Output Power − W
Figure 13.
Figure 14.
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SYSTEM EFFICIENCY
vs
OUTPUT POWER
CROSSTALK
vs
FREQUENCY
-40
100
VCC = 12 V
90
−60
80
VCC = 12 V
RL = 8 Ω
Gain = 20 dB
VO = 1 Vrms
VCC = 18 V
60
Crosstalk − dB
Efficiency − %
70
VCC = 24 V
50
40
−80
R to L
−100
30
L to R
RL = 8 W
Gain = 20 dB
20
−120
10
−140
20
0
0
5
10
15
20
25
100
Figure 15.
Figure 16.
CROSSTALK
vs
FREQUENCY
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
-40
L to R
−80
−100
R to L
−120
−140
20
100
1k
10k 20k
−10
−20
RL = 8 W
Gain = 20 dB
V(RIPPLE) = 200 mVPP
−30
−40
−50
−60
VCC = 12 V
VCC = 18 V
−70
−80
VCC = 24 V
−90
−100
20
f − Frequency − Hz
100
1k
f − Frequency − Hz
Figure 17.
12
10k 20k
0
VCC = 24 V
RL = 8 Ω
Gain = 20 dB
VO = 1 Vrms
kSVR − Supply Ripple Rejection Ratio − dB
Crosstalk − dB
−60
1k
f − Frequency − Hz
PO − Output Power (Per Channel) − W
Figure 18.
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20k
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Shutdown
and Mute
Control
Fault Output
APPLICATION INFORMATION
33 mH
0.1 mF
8W
0.47 mF
0.1 mF
10 V - 26 V
33 mH
220nF
220nF
10 mF
NC
NC
BSRN
ROUTN
ROUTP
ROUTN
BSRP
NC
NC
NC
RINP
PGNDR
AGND
LINN
1 mF
VCLAMPL
NC
GAIN1
PGNDL
220 mF
1 mF
10 V - 26 V
NC
LOUTN
BSLN
LOUTP
LOUTN
NC
1 mF
10 nF
NC
BSLP
NC
LOUTP
PVCCL
NC
NC
NC
NC
PVCCL
AGND
PGNDL
VBYP
MSTR/SLV
NC
100 kW
220 mF
VCLAMPR
GAIN0
NC
1 mF
NC
TPA3107D2
LINP
1 mF
NC
PGNDR
VREG
220nF
1 mF
Synchronize Multiple
Class-D Devices
1 mF
PVCCR
RINN
SYNC
4-Step
Gain Control
1 mF
10 V - 26 V
PVCCR
NC
ROSC
Single-Ended
Analog
Inputs
NC
NC
NC
1 mF
ROUTP
NC
NC
SHUTDOWN
MUTE
AVCC
NC
FAULT
1 mF
220nF
33 mH
0.1 mF
8W
0.47 mF
33 mH
0.1 mF
Figure 19. TPA3107D2 Application Circuit With Single-Ended Inputs
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APPLICATION INFORMATION (continued)
CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3107D2.
Traditional Class-D Modulation Scheme
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out-of-phase and changes from ground to the supply voltage, VCC. Therefore,
the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields
0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 20. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,
causing high loss and thus causing a high supply current.
OUTP
OUTN
+12 V
Differential Voltage
Across Load
0V
-12 V
Current
Figure 20. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms into an
Inductive Load With No Input
TPA3107D2 Modulation Scheme
The TPA3107D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater
than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50%
and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout
most of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.
14
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APPLICATION INFORMATION (continued)
OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
+12 V
0V
-12 V
Current
OUTP
OUTN
Differential
Voltage
Across
Load
Output > 0 V
+12 V
0V
-12 V
Current
Figure 21. The TPA3107D2 Output Voltage and Current Waveforms Into an Inductive Load
Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform
results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple
current is large for the traditional modulation scheme, because the ripple current is proportional to voltage
multiplied by the time at that voltage. The differential voltage swing is 2 x VCC, and the time at each voltage is
half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from
each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both
resistive and reactive, whereas an LC filter is almost purely reactive.
The TPA3107D2 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 x VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
When to Use an Output Filter for EMI Suppression
Design the TPA3107D2 without the filter if the traces from amplifier to speaker are short (< 10 cm). Powered
speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without
a filter.
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APPLICATION INFORMATION (continued)
Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and
CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high
impedance at high frequencies, but low impedance at low frequencies.
Use an LC output filter if there are low frequency (
