TPA3112D1PWP

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPA3112D1 SLOS654D – AUGUST 2009 – REVISED DECEMBER 2016 TPA3112D1 25-W Filter-Free Mono Class-D Audio Power Amplifier With SpeakerGuard™ 1 Features 3 Description • The TPA3112D1 is a 25-W efficient, Class-D audio power amplifier for driving a bridge tied speaker. Advanced EMI Suppression Technology enables the use of inexpensive ferrite bead filters at the outputs while meeting EMC requirements. SpeakerGuard speaker protection system includes an adjustable power limiter and a DC detection circuit. The adjustable power limiter allows the user to set a virtual voltage rail lower than the chip supply to limit the amount of current through the speaker. The DC detect circuit measures the frequency and amplitude of the PWM signal and shuts off the output stage if the input capacitors are damaged or shorts exist on the inputs. 1 • • • • • • • • • • 25-W into an 8-Ω Load at < 0.1% THD+N From a 24-V Supply 20-W into an 4-Ω Load at 10% THD+N From a 12-V Supply 94% Efficient Class-D Operation into 8-Ω Load Eliminates Need for Heat Sinks Wide Supply Voltage Range Allows Operation from 8 to 26 V Filter-Free Operation SpeakerGuard™ Speaker Protection Includes Adjustable Power Limiter plus DC Protection Flow Through Pin Out Facilitates Easy Board Layout Robust Pin-to-Pin Short Circuit Protection and Thermal Protection with Auto-Recovery Option Excellent THD+N/ Pop Free Performance Four Selectable, Fixed Gain Settings Differential Inputs 2 Applications • • The TPA3112D1 can drive a mono speaker as low as 4Ω. The high efficiency of the TPA3112D1, > 90%, eliminates the need for an external heat sink when playing music. The outputs are fully protected against shorts to GND, VCC, and output-to-output. The short-circuit protection and thermal protection includes an autorecovery feature. Device Information(1) Televisions Consumer Audio Equipment PART NUMBER TPA3112D1 PACKAGE HTSSOP (28) BODY SIZE (NOM) 4.40 mm × 9.70 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application Diagram 1uF Audio Source OUT+ INP OUT - INN TPA3112D1 OUTP OUTN FERRITE BEAD FILTER 25W 8Ω GAIN0 GAIN1 PLIMIT Fault SD PVCC 8 to 26V Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPA3112D1 SLOS654D – AUGUST 2009 – REVISED DECEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 Absolute Maximum Ratings ..................................... 6.2 ESD Ratings ............................................................ 6.3 Recommended Operating Conditions...................... 6.4 Thermal Information ................................................. 6.5 DC Characteristics, VCC = 24 V ............................... 6.6 DC Characteristics, VCC = 12 V ............................... 6.7 AC Characteristics, VCC = 24 V ............................... 6.8 AC Characteristics, VCC = 12 V ............................... 6.9 Typical Characteristics .............................................. 4 4 4 5 5 5 6 6 7 Detailed Description ............................................ 10 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 11 7.3 Feature Description................................................. 11 7.4 Device Functional Modes........................................ 14 8 Application and Implementation ........................ 16 8.1 Application Information............................................ 16 8.2 Typical Application ................................................. 16 9 Power Supply Recommendations...................... 21 10 Layout................................................................... 22 10.1 Layout Guidelines ................................................. 22 10.2 Layout Example .................................................... 23 11 Device and Documentation Support ................. 24 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Device Support .................................................... Documentation Support ....................................... Recieving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 24 24 24 24 24 24 24 12 Mechanical, Packaging, and Orderable Information ........................................................... 25 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (July 2012) to Revision D • 2 Page Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPA3112D1 TPA3112D1 www.ti.com SLOS654D – AUGUST 2009 – REVISED DECEMBER 2016 5 Pin Configuration and Functions PHP PowerPAD™ Package 28-Pin HTSSOP Top View SD FAULT 1 28 2 27 GND GND GAIN0 GAIN1 3 26 4 25 5 24 6 23 AVCC AGND GVDD PLIMIT 7 22 8 21 INN INP NC AVCC 9 20 10 19 11 18 12 17 13 16 14 15 PVCC PVCC BSN OUTN PGND OUTN BSN BSP OUTP PGND OUTP BSP PVCC PVCC Pin Functions PIN TYPE DESCRIPTION NAME NO. AGND 8 G Analog supply ground. Connect to the thermal pad. AVCC 7 P Analog supply. AVCC 14 P Connect AVCC supply to this pin BSN 22 I Bootstrap I/O for negative high-side FET. BSN 26 I Bootstrap I/O for negative high-side FET. BSP 21 I Bootstrap I/O for positive high-side FET. BSP 17 I Bootstrap I/O for positive high-side FET. FAULT 2 O Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both the short circuit faults and dc detect faults must be reset by cycling PVCC. GAIN0 5 I Gain select least significant bit. TTL logic levels with compliance to AVCC. GAIN1 6 I Gain select most significant bit. TTL logic levels with compliance to AVCC. GND 3 G Connect to local ground GND 4 G Connect to local ground GVDD 9 O High-side FET gate drive supply. Nominal voltage is 7 V. May also be used as supply for PLILMIT divider. Add a 1-μF capacitor to ground at this pin. INP 12 I Positive audio input. Biased at 3 V. INN 11 I Negative audio input. Biased at 3 V. NC 13 — Not connected OUTN 23 O Class-D H-bridge negative output. OUTN 25 O Class-D H-bridge negative output. OUTP 20 O Class-D H-bridge positive output. OUTP 18 O Class-D H-bridge positive output. PLIMIT 10 I Power limit level adjust. Connect directly to GVDD pin for no power limiting. Add a 1-μF capacitor to ground at this pin. PGND 19 G Power ground for the H-bridges. PGND 24 G Power ground for the H-bridges. PVCC 15 P Power supply for H-bridge. PVCC pins are also connected internally. Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPA3112D1 3 TPA3112D1 SLOS654D – AUGUST 2009 – REVISED DECEMBER 2016 www.ti.com Pin Functions (continued) PIN TYPE DESCRIPTION NAME NO. PVCC 16 P Power supply for H-bridge. PVCC pins are also connected internally. PVCC 27 P Power supply for H-bridge. PVCC pins are also connected internally. PVCC 28 P Power supply for H-bridge. PVCC pins are also connected internally. SD 1 I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN VCC Supply voltage VI Interface pin voltage TA Operating free-air temperature RL Minimum Load Resistance UNIT V AVCC, PVCC –0.3 30 SD, FAULT,GAIN0, GAIN1, AVCC (Pin 14) –0.3 VCC + 0.3 < 10 PLIMIT –0.3 GVDD + 0.3 INN, INP –0.3 6.3 V –40 85 °C 150 °C BTL V V/ms 3.2 Tstg DMD storage temperature (1) MAX V Ω –65 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) 6.3 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT 26 V VCC Supply voltage PVCC, AVCC 8 VIH High-level input voltage SD, GAIN0, GAIN1 2 VIL Low-level input voltage SD, GAIN0, GAIN1 0.8 VOL Low-level output voltage FAULT, RPULLUP = 100 kΩ, VCC = 26 V 0.8 V IIH High-level input current SD, GAIN0, GAIN1, VI = 2 V, VCC = 18 V 50 µA IIL Low-level input current SD, GAIN0, GAIN1, VI = 0.8 V, VCC = 18 V 5 µA 4 Submit Documentation Feedback V V Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: TPA3112D1 TPA3112D1 www.ti.com SLOS654D – AUGUST 2009 – REVISED DECEMBER 2016 6.4 Thermal Information TPA3112D1 THERMAL METRIC (1) PWP (HTSSOP) UNIT 28 PINS RθJA Junction-to-ambient thermal resistance 30.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 33.5 °C/W RθJB Junction-to-board thermal resistance 17.5 °C/W ψJT Junction-to-top characterization parameter 0.9 °C/W ψJB Junction-to-board characterization parameter 7.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 DC Characteristics, VCC = 24 V TA = 25°C, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS | VOS | Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB ICC Quiescent supply current SD = 2 V, no load, PVcc=21 V ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVcc=21 V rDS(on) IO = 500 mA, TJ = 25°C Drain-source on-state resistance GAIN1 = 0.8 V G Gain GAIN1 = 2 V tON Turn-on time SD = 2 V tOFF Turn-off time SD = 0.8 V GVDD Gate Drive Supply IGVDD = 2 mA 6.6 MIN TYP MAX 1.5 15 mV 40 mA 400 µA High side 240 Low side 240 mΩ GAIN0 = 0.8 V 19 20 21 GAIN0 = 2 V 25 26 27 GAIN0 = 0.8 V 31 32 33 GAIN0 = 2 V 35 36 37 10 6.9 dB dB ms 2 6.5 UNIT μs 7.3 V DC Characteristics, VCC = 12 V TA = 25°C, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT | VOS | Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB 1.5 ICC Quiescent supply current SD = 2 V, no load, PVcc=12 V 20 mA ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVcc=12 V 200 µA Drain-source on-state resistance IO = 500 mA, TJ = 25°C rDS(on) GAIN1 = 0.8 V G Gain GAIN1 = 2 V High side 240 Low side 240 15 mΩ GAIN0 = 0.8 V 19 20 21 GAIN0 = 2 V 25 26 27 GAIN0 = 0.8 V 31 32 33 GAIN0 = 2 V 35 36 37 tON Turn-on time SD = 2 V tOFF Turn-off time SD = 0.8 V GVDD Gate Drive Supply IGVDD = 2 mA PLIMIT Output Voltage maximum under PLIMIT control VPLIMIT= 2.0 V; VI= 6.0-V differential 10 Product Folder Links: TPA3112D1 dB dB ms 2 μs 6.5 6.9 7.3 V 6.75 7.90 8.75 V Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated mV 5 TPA3112D1 SLOS654D – AUGUST 2009 – REVISED DECEMBER 2016 6.7 www.ti.com AC Characteristics, VCC = 24 V TA = 25°C, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN KSVR Power Supply ripple rejection 200-mVPP ripple from 20 Hz–1 kHz, Gain = 20 dB, Inputs AC-coupled to AGND PO Continuous output power THD+N ≤ 0.1%, f = 1 kHz, VCC = 24 V THD+N Total harmonic distortion + noise VCC = 24 V, f = 1 kHz, PO = 12 W (half-power) Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB Crosstalk SNR Signal-to-noise ratio fOSC Oscillator frequency MAX UNIT –70 dB 25 W