TPA3140D2PWPEVM

User's Guide SLOU405 – April 2015 TPA3140D2EVM User's Guide This user’s guide describes the operation of the evaluation module for the TPA3140D2. The user’s guide also provides design information such as the schematic, BOM, and PCB layout. 1 2 3 Contents Overview ...................................................................................................................... Operation ..................................................................................................................... 2.1 Electrostatic Discharge Warning .................................................................................. 2.2 Unpacking the EVM ................................................................................................ 2.3 Power Supply Setup ................................................................................................ 2.4 Evaluation Module Preparations .................................................................................. 2.5 Inputs and Outputs ................................................................................................. 2.6 Power Up ............................................................................................................ 2.7 Automatic Gain Control (AGC) .................................................................................... 2.8 Thermal Foldback ................................................................................................... Design Documentation ...................................................................................................... 3.1 TPA3140D2 EVM Schematic...................................................................................... 3.2 TPA3140D2 EVM PCB Layers .................................................................................... 3.3 TPA3140D2EVM Bill of Materials................................................................................. 2 3 3 3 3 3 3 4 4 4 5 5 6 9 List of Figures 1 TAS3140D2 PCB ............................................................................................................ 2 2 TPA3140D2 EVM Schematic............................................................................................... 5 3 TPA3140D2 Assembly Drawing 4 5 ........................................................................................... TPA3140D2 EVM Top Side Layout ....................................................................................... TPA3140D2 EVM Bottom Side Layout ................................................................................... 6 7 8 List of Tables 1 Power Requirements ........................................................................................................ 3 2 TPA3140D2EVM Parts List ................................................................................................ SLOU405 – April 2015 Submit Documentation Feedback TPA3140D2EVM User's Guide Copyright © 2015, Texas Instruments Incorporated 9 1 Overview 1 www.ti.com Overview The TPA3140D2 EVM customer evaluation module demonstrates the integrated circuits TPA3140D2 from Texas Instruments (TI). The TPA3140D2 is a 10-W (per channel) efficient stereo digital amplifier power stage for driving 2 bridgetied speakers. This document covers EVM specifications and design documentation that includes schematics, parts list and layout design. Figure 1. TAS3140D2 PCB Table 1. TPA3140D2EVM Specification 2 KEY PARAMETERS VALUE Power Supply Voltage 4.5 V to 14.4 Number of Channels 2 Bridge Tied Load (BTL) Stereo Load Impedance 4 Ω (12 V) to 6 Ω (> 12 V) Output Power BTL 10 W per channel into a 8 Ω load TPA3140D2EVM User's Guide SLOU405 – April 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Operation www.ti.com 2 Operation This chapter describes the TPA3140D2EVM board in regards to power supply and system interfaces. The chapter provides information regarding handling and unpacking, absolute operating conditions, and a description of the factory default switch and jumper configuration. The following is a step–by–step guide to configuring the TPA3140D2EVM for device evaluation. 2.1 Electrostatic Discharge Warning Many of the components on the TPA3140D2EVM are susceptible to damage by electrostatic discharge (ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handling the EVM, including the use of a grounded wrist strap at an approved ESD workstation. CAUTION Failure to observe ESD handling procedures may result in damage to EVM components. 2.2 Unpacking the EVM On opening the TPA3140D2EVM package, ensure that the following items are included: • 1 piece TPA3140D2EVM board using one TPA3140D2. If either of these items is missing, contact the Texas Instruments Product Information Center nearest you to inquire about a replacement. 2.3 Power Supply Setup A single power supply is required to power up the EVM. Since most of the pins are PVCC compliant, the PVCC supply can also be used to power the analog supply (AVCC) and can be used to pull up the logic pins for shutdown (SD) control, and fault detection (FAULT). Table 1. Power Requirements DESCRIPTION VOLTAGE RANGE CURRENT REQUIREMENT MINIMUM WIRE SIZE PVCC 4.5 to 14.4 V 4A 24 AWG CAUTION Applying voltages above the limitations given in table above may cause permanent damage to your hardware. 2.4 Evaluation Module Preparations 1. Ensure that the external power source is set to OFF. 2. Connect the external regulated power supply adjusted from 4.5 V to 14.4 V to the module PVCC and GND banana jacks taking care to observe marked polarity. 2.5 Inputs and Outputs 1. For a BTL Configuration, connect a Load(s) across the outputs (OUTL+ and OUTL–) and (OUTR+ and OUTR–). 2. For PBTL configuration, connect a single load from one of the left speaker jacks to one of the right speaker jacks depending on how the filters are loaded. Apply a single input, differential or singleended, to the RIN RCA phono plug and tie LINP and LINN directly to Ground (without capacitors) via J3 and J4. SLOU405 – April 2015 Submit Documentation Feedback TPA3140D2EVM User's Guide Copyright © 2015, Texas Instruments Incorporated 3 Operation 2.6 www.ti.com Power Up 1. Select the desired gain and mode of operation via J5, J8, and J9 headers. Verify correct voltage and input polarity and turn the external power supplies ON. The EVM should begin operation. 2. Adjust the audio source for the correct volume. 2.7 Automatic Gain Control (AGC) The AGC allows the adjustment of the maximum output voltage without signal clipping for enhancement speaker protection and audio quality. Gain limit threshold (LIMTHRES) adjust the input gain control with a fast attack such that the audio output is largely attenuated to highest unclipped possible amplitude such that excessive input signals will not result in hard distortion, and equally important it reduces the maximum output power as well as reduces the amount of high frequency audio energy fed to a tweeter in a 2-way speaker; thus, protecting the speaker and increase overall system reliability. Resistor pot R7 is used to adjust the gain limit threshold level. The user can adjust the R7 pot such that LIMTHRES voltage equals to GVDD to defeat the limit threshold. The AGC release speed is set by an external voltage divider (J9) to select from fixed modes including disabling AGC (J9 = OFF, hard clip action operation as TPA3110D2 PLIMIT) as well as a selection between fast, nominal or slow rates. 2.8 Thermal Foldback A thermal foldback circuit is implemented to enhance system reliability by reducing risk of thermal runaway and/or shutdown by reducing the amplifier’s gain such that the output power is reduced. The thermal foldback is activated when a thermal trip point at a lower level than the OTE (Over Temperature Error) trip point is tripped. Thermal foldback acts as the AGC function, but with an attack speed chosen to match thermal time constants in a system with a TPA3140D2 mounted with a realistic PCB layout. Thermal foldback can be disabled with J9 set to OFF. 4 TPA3140D2EVM User's Guide SLOU405 – April 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Design Documentation www.ti.com 3 Design Documentation 3.1 TPA3140D2 EVM Schematic Figure 2 shows the TPA3140D2 EVM schematic. PVCC PVCC 1 PVCC PVCC 1 C1 LINP 3 4 1 LIN 2 SHUTDOWN J10 100k C3 1000pF LIMTHRES = GVDD 1µF GND 1 L1 PVCCL R1 C4 0.1µF C2 100 µF GND GND 1 2 RCA Jack White SDz J1 FAULTz GND C5 LINN 1 2 3 J2 1µF LINP LINN GND LIMRATE GAIN SSCTRL J3 LIMTHRES J4 1 2 PBTL 1 2 R6 GND 1 2 SD FAULT 3 4 LINP LINN 5 LIMRATE 6 GAIN 7 SSCTRL 8 LIMTHRES 9 R7 10.0k GND GND GND U1 2 1 100k 10 29 GVDD C6 BSPL 26 OUTPL 25 PGND 24 2 4 6 8 11 RINN