TPA3200D1
www.ti.com
SLOS442A – MAY 2005 – REVISED JULY 2005
20-W MONO DIGITAL INPUT AUDIO AMPLIFIER
FEATURES
•
•
DESCRIPTION
Digital Interface
– 24-bit Resolution
– Supports I2S and 16-Bit Word
Right-Justified Digital Input Formats
– Multiple Sampling Frequencies:
5 kHz – 200 kHz
– 8x Oversampling Digital Filter
– Soft Mute
Power Amplifier
– 20-W into an 8-Ω Load from an 18-V Supply
– Efficient Operation Eliminates Need for Heat
Sinks
– Three Selectable, Fixed Gain Settings
– Thermal and Short-Circuit Protection
The TPA3200D1 is a 20-W (per channel) efficient,
digital audio power amplifier for driving a bridged-tied
speaker. The TPA3200D1 can drive a speaker with
an impedance as low as 4 Ω. The high efficiency of
the TPA3200D1 (85%) eliminates the need for an
external heat sink.
The digital input accepts 16-24 bit data in I2S format
or 16-bit word right-justified. A digital filter performs
an 8x interpolation function. Other features include
soft mute, a zero input detect output flag for power
conscious designs, and power saving shutdown
mode.
Simplified Application Circuit
TAS3103
I2S or 16-bit RJ
22 nF
DATA
FLT1
SCLK
FLT2
Digital Audio
Processor
10 mF
VCOM
BCK
1 mF
VREF
1 mF
LRCK
BYPASS
Control
Inputs
{
Gain Select
{
FORMAT
220 pF
COSC
MUTE
ROSC
DEMP
GAIN0
120 kW
TPA3200D1
AGND
0.22 mF
GAIN1
BSN
51 W
Shutdown Control
Channel Select
SHUTDOWN
LR_SEL
OUTN
OUTP
51 W
BSP
Zero Input Flag
ZERO
0.22 mF
VCLAMP
+5V
VDD
+18V
PVCC
1.0 mF
PGND
AVCC
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
TPA3200D1
www.ti.com
SLOS442A – MAY 2005 – REVISED JULY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
(1)
TA
PACKAGED DEVICE
44-PIN (DCP) (1)
–40°C to 85°C
TPA3200D1DCP
The DCP package is available taped and reeled. To order a taped
and reeled part, add the suffix R to the part number (e.g.,
TPA3200D1DCPR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VSS
RL
TPA3200D1
UNIT
Supply voltage, VCC, PVCC
–0.3 to 21
V
Supply voltage, VDD
–0.3 to 6.5
V
SHUTDOWN
Vi
≥3.6
Ω
– 0.3 to VCC + 0.3
V
–0.3 to VDD + 0.3
V
Load Impedance
GAIN0, GAIN1, BCK, SCLK, DATA, LRCK, LR_SEL
FORMAT, MUTE, DEMP
Continuous total power dissipation
See Dissipation Rating Table
TA
Operating free-air temperature range
–25 to 85
°C
TJ
Operating junction temperature range
–25 to 150
°C
Tstg
Storage temperature range
–65 to 150
°C
260
°C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
(1)
2
PACKAGE
TA ≤ 25°C
DERATING FACTOR
(1/θJA)
TA = 70°C
TA = 85°C
44-pin DCP
4.89 W
39.1 mW/°C (1)
3.13 W
2.54 W
Based on a JEDEC high-K PCB with the PowerPAD™ soldered to a thermal land on the printed-circuit board. See the PowerPAD
Thermally Enhanced Package technical brief, literature number SLMA0002. The PowerPAD must be soldered to the PCB.
TPA3200D1
www.ti.com
SLOS442A – MAY 2005 – REVISED JULY 2005
RECOMMENDED OPERATING CONDITIONS
PARAMETER
PIN NAME
MIN
PVCC, VCC
VSS
Supply voltage
VIH
High-level input voltage
SHUTDOWN, GAIN0, GAIN1, BCK, SCLK, DATA,
LRCK, FORMAT, MUTE, DEMP
VIL
Low-level input voltage
SHUTDOWN, GAIN0, GAIN1, BCK, SCLK, DATA,
LRCK, FORMAT, MUTE, DEMP
VIH
High-level input voltage
LR_SEL
VIL
Low-level input voltage
LR_SEL
IIH
High-level input current
IIL
Low-level input current
VDD
MAX
8
18
4.5
5.5
2
V
0.8
VDD x 0.7
VDD x 0.3
SHUTDOWN: VI = VCC, VCC = 12 V
1
GAIN0, GAIN1, LR_SEL: VI = VDD, VDD = 5 V
1
SCLK, BCK, DATA, LRCK: VI = VDD, VDD = 5 V
10
FORMAT, MUTE, DEMP: VI = VDD, VDD = 5 V
100
SHUTDOWN: VI = 0 V, VCC = 12 V
1
GAIN0, GAIN1, LR_SEL: VI = 0 V, VDD = 5 V
1
BCK, SCLK, DATA, LRCK, FORMAT, MUTE, DEMP:
VI = 0 V, VDD = 5 V
10
VOH
High-level output voltage
IOH = –1 mA, ZERO
VOL
Low-level output voltage
IOL = 1 mA, ZERO
fOSC
Oscillator frequency
UNIT
µA
2.4
V
0.4
200
300
kHz
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VDD = 5 V, fS = 44.1 kHz, system clock = 384 fS and 24-bit data, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
fS = 44.1 kHz
26
31
fS = 96 kHz
25
fS = 192 kHz
30
UNIT
POWER SUPPLY REQUIREMENTS (1)
IDD
Supply current
mA
DIGITAL FILTER PERFORMANCE
FILTER CHARACTERISTICS
Pass band
±0.04 dB
Stop band
0.454 fs
0.546 fs
±0.04
Pass-band ripple
Stop-band attenuation
Stop band = 0.546 fS
–50
dB
dB
ANALOG FILTER PERFORMANCE
Frequency response
At 20 kHz
–0.03
At 44 kHz
–0.20
dB
SAMPLING FREQUENCY
fs
Sampling frequency
5
200
KHz
DYNAMIC PERFORMANCE
Channel separation
(1)
fS = 44.1 KHz, 96 KHz, 192 KHz
100
dB
Conditions in 192-kHz operation are system clock = 128 fS and oversampling rate = 64 fS of register 18.
3
TPA3200D1
www.ti.com
SLOS442A – MAY 2005 – REVISED JULY 2005
FORMAT CHARACTERISTICS
All specifications at TA = 25°C, VDD = 5 V, fS = 44.1 kHz, system clock = 384 fS and 24-bit data, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
Resolution
MAX
UNIT
24
Bits
Data
Audio-data interface format Audio
I2S, standard
Audio-data bit length Audio
16–24-bit (I2S), 16-bit (Right-justified)
Audio data format
MSB first, 2s complement
System clock frequency
128 fS, 192 fS, 256 fS, 384 fS,
512 fS, 768 fS, 1152 fS
ELECTRICAL CHARACTERISTICS
at TA = 25°C, PVCC = VCC = 12 V (unless otherwise noted)
PARAMETER
|VOS|
TEST CONDITIONS
Output offset voltage (measured differentially)
MUTE = 2 V
TYP
AV = 12 dB
PSRR Power supply rejection ratio
PVCC = 11.5 V to 12.5 V
VREF
IL = 10 mA, VCC = 8 V – 18 V
5 V regulator voltage
MIN
Supply current
4.55
SHUTDOWN = VCC, VCC = 18 V, PO = 20 W,
RL = 8 Ω
ICC(SD) Supply current shutdown mode
Output transistor on resistance (high side and
low side)
G
Gain
100
mV
dB
4.9
5.45
8
15
1.3
SHUTDOWN = 0.8 V
rDS(on)
UNIT
–73
SHUTDOWN = 2.0 V, No load
ICC
MAX
V
mA
A
1
2
µA
0.5
0.6
0.7
Ω
GAIN1 = 0.8 V, GAIN0 = 0.8 V
10.9
12
13.1
GAIN1 = 0.8 V, GAIN0 = 2 V
17.1
18
18.6
GAIN1 = 2 V, GAIN0 = 0.8 V
22.9
23.6
24.4
IO = 0.5 A, TJ = 25°C
dB
OPERATING CHARACTERISTICS
PVCC = VCC = 12 V, TA = 25° C unless otherwise noted
PARAMETER
Continuous output power at 10% THD+N
PO
Continuous output power at 1% THD+N
TEST CONDITIONS
TYP
RL = 4 Ω
12.8
f = 1 kHz,
RL = 8 Ω
9
f = 1 kHz,
RL = 4 Ω
10.3
f = 1 kHz,
RL = 8 Ω
THD+N
Total harmonic distortion plus noise
PO = 10 W, RL = 4 Ω
f = 20 Hz to 20 kHz
BOM
Maximum output power bandwidth
THD = 1%
kSVR
Supply ripple rejection ratio
f = 1 kHz,
SNR
Signal-to-noise ratio
PO = 10 W, RL = 4 Ω
Vn
Noise output voltage
C(BYPASS) = 1 µF,
A-weighted filter
4
MIN
f = 1 kHz,
W
7.5
–60
95
f = 20 Hz to 22 kHz,
Gain = 12 dB
UNIT
0.2%
20
C(BYPASS) = 1 µF
MAX
150
–76.5
kHz
dB
µV(rms)
dBV
TPA3200D1
www.ti.com
SLOS442A – MAY 2005 – REVISED JULY 2005
Functional Block Diagram
BCK
LRCK
DATA
Audio
Serial
Port
FORMAT
MUTE
Serial
Control
Port
4x/8x
Oversampling
Digital
Filter
and
Function
Control
Zero Detect
ZERO
Multi-Level
Delta-Sigma
Modulator
DEMP
System Clock
SCLK
VDD
Audio
Serial
Port
Power Supply
DGND
LR_SEL
VCOM
Clamp
Reference
DAC and
2:1 Mux
Gain
Adjust
FLT2
_
+
_
VCLAMP
BSN
PVCC
Deglitch
Logic
Gate
Drive
OUTN
+
PGND
BSP
PVCC
−
+
+ −
Gain
Adjust
FLT1
+
_
_
+
Deglitch
Logic
Gate
Drive
OUTP
PGND
SD
Start-Up
Protection
Logic
SHUTDOWN
GAIN0
GAIN1
2
Gain
COSC
ROSC
BYPASS
Biases
and
References
Short-Circuit
Detect
Ramp
Generator
Thermal
VCC OK
VREF AGND AVCC
VREF
AVCC
5
TPA3200D1
www.ti.com
SLOS442A – MAY 2005 – REVISED JULY 2005
DCP
(TOP VIEW)
BCK
NC
DATA
LRCK
DGND
VDD
LR_SEL
VDD
DGND
VCOM
GAIN0
GAIN1
SHUTDOWN
PGND
VCLAMP
NC
BSN
PVCC
OUTN
OUTN
PGND
PGND
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
SCLK
FORMAT
MUTE
DEMP
DGND
ZERO
DGND
FLT1
FLT2
VCC
VREF
BYPASS
COSC
ROSC
AGND
AGND
BSP
PVCC
OUTP
OUTP
PGND
PGND
TPA3200D1
www.ti.com
SLOS442A – MAY 2005 – REVISED JULY 2005
Terminal Functions
TERMINAL
NO.
NAME
I/O
DESCRIPTION
1
BCK
I
Bit clock input for audio data
3
DATA
I
Audio data input
4
LRCK
I
Left and right channel audio data latch enable input
7
LR_SEL
I
Select left-channel or right-channel data
HIGH: Left channel active
LOW: Right channel active
11
GAIN0
I
Gain select least significant bit. TTL logic levels with compliance to 5 V.
12
GAIN1
I
Gain select most significant bit. TTL logic levels with compliance to 5 V.
13
SHUTDOWN
I
Shutdown signal for IC (low = shutdown, high = operational).
TTL logic levels with compliance to 18 V.
5, 9, 38, 40
DGND
-
Digital ground
6, 8
VDD
-
Digital power supply (4.5 V – 5.5 V)
15
VCLAMP
-
Internally generated voltage supply for bootstrap capacitor
17
BSN
I/O
Bootstrap I/O, negative high-side FET
28
BSP
I/O
Bootstrap I/O, positive high-side FET
2, 16
NC
-
31
ROSC
I/O
I/O for current setting resistor for ramp generator
32
COSC
I/O
I/O for charge/discharging currents onto capacitor for ramp generator creation
33
BYPASS
O
Midrail analog reference voltage
34
VREF
O
Analog 5-V regulated output. Not to be used for powering external circuitry.
No internal connection
35
VCC
-
High-voltage analog power supply (8 V to 18 V).
19, 20
OUTN
O
Class-D 1/2-H-bridge negative output
39
ZERO
O
Zero flag output
HIGH: No input present
LOW: Data present at input
This can be used to shutdown the device when no data is present at input.
41
DEMP
I
De-emphasis control.
HIGH: 44.1 kHz De-emphasis ON
LOW: 44.1 kHz De-emphasis OFF
42
MUTE
I
Soft mute control
HIGH: Mute ON
LOW: Mute OFF
43
FORMAT
I
Audio data format select
HIGH: 16-bit right justified
LOW: 16- to 24-bit, I2S format
44
SCLK
I
System clock input
18, 27
PVCC
-
Power supply for H-bridge (8 V to 18 V)
25, 26
OUTP
O
Class-D 1/2-H-bridge positive output
29, 30
AGND
-
Analog ground
14, 21, 22, 23, 24
PGND
-
Power ground for H-bridge
10
VCOM
-
Midrail digital reference voltage
36
FLT2
I/O
37
FLT1
I/O
Thermal Pad
Noise-filter terminals. Connect capacitor across pins 36 and 37
Connect to AGND and PGND - should be the center point for both grounds.
Internal esistive connection to AGND.
7
TPA3200D1
www.ti.com
SLOS442A – MAY 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS
Total Harmonic Distortion Plus Noise
vs
Output Power
Total Harmonic Distortion Plus Noise
vs
Output Power
10
VCC = 12 V
RL = 8
Gain = 18 dB
fS = 48 kHz
24−bit, I2S format
5
2
Total Hormonic Distortion Plus Noise − %
Total Hormonic Distortion Plus Noise − %
10
1
0.5
10 kHz
0.2
0.1
1 kHz
0.05
0.02
20 Hz
0.01
10m
100m 200m
1
2
VCC = 12 V
RL = 8
Gain = 23.6 dB
fS = 48 kHz
24−bit, I2S format
5
2
1
0.5
10 kHz
0.2
1 kHz
0.1
0.05
20 Hz
0.02
0.01
10
10m
PO − Output Power − W
10
Harmonic Distortion Plus Noise
vs
Output Power
Total Harmonic Distortion
vs
Power
10
VCC = 18 V
RL = 8
Gain = 23.6 dB
fS = 48 kHz
24−bit, I2S format
1
0.5
10 kHz
0.2
0.1
1 kHz
0.05
0.02
0.01
10m
20 Hz
100m 200m
1
2
PO − Output Power − W
Figure 3.
8
2
Figure 2.
THD+N - Total Harmonic Distortion + Noise - %
Total Hormonic Distortion Plus Noise − %
2
1
Figure 1.
10
5
100m 200m
PO − Output Power − W
10 20
5 VCC = 12 V
RL= 4 Ù,
2 Gain = 18 dB,
fs= 48 kHz,
2
1 24-bit, I S format
10 kHz
0.5
1 kHz
0.2
0.1
0.05
0.02
0.01
10m
20 Hz
100m 200m
1
PO - Output Power - W
Figure 4.
10 20
TPA3200D1
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SLOS442A – MAY 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
Total Harmonic Distortion Plus Noise
vs
Frequency
Total Harmonic Distortion Plus Noise
vs
Frequency
20
VCC = 12 V
RL = 8
Gain = 18 dB
fS = 48 kHz
24−bit, I2S format
10
5
2
1
PO = 5 W
0.5
0.2
0.1
PO = 500 mW
0.05
PO = 1 W
0.02
0.01
20
100 200
1k
2k
Total Hormonic Distortion Plus Noise − %
Total Hormonic Distortion Plus Noise − %
20
10
VCC = 12 V
RL = 8
Gain = 23.6 dB
fS = 48 kHz
24−bit, I2S format
5
2
1
0.5
0.2
0.1
PO = 500 mW
0.05
PO = 1 W
0.02
PO = 5 W
0.01
10k 20k
20
100 200
f − Frequency − Hz
Figure 6.
Total Harmonic Distortion Plus Noise
vs
Frequency
Total Harmonic Distortion Plus Noise
vs
Frequency
10k 20k
20
VCC = 18 V
RL = 8
Gain = 18 dB
fS = 48 kHz
24−bit, I2S format
10
5
2
Total Hormonic Distortion Plus Noise − %
Total Hormonic Distortion Plus Noise − %
2k
Figure 5.
20
1
0.5
0.2
0.1
PO = 500 mW
0.05
PO = 1 W
0.02
0.01
1k
f − Frequency − Hz
100 200
VCC = 18 V
RL = 8
Gain = 23.6 dB
fS = 48 kHz
24−bit, I2S format
5
2
1
0.5
0.2
0.1
PO = 500 mW
0.05
PO = 1 W
0.02
PO = 5 W
PO = 5 W
20
10
1k
2k
f − Frequency − Hz
Figure 7.
10k 20k
0.01
20
100
200
1k
2k
10k 20k
f − Frequency − Hz
Figure 8.
9
TPA3200D1
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SLOS442A – MAY 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
Total Harmonic Distortion
vs
Frequency
Power Supply Voltage Rejection Ratio
vs
Frequency
0
VCC = 12 V
RL = 4 Ù
Gain = 18 dB
fS = 48 kHz
2
24-Bit, I S format
5
2
PSRR − Power Supply Rejecyion Ratio − dB
THD + N - Total Harmonic Distortion + Noise - %
10
1
Po = 2 W
0.5
Po = 200 mW
0.2
0.1
0.05
Po = 7.5 W
0.02
−10
−20
−30
−40
−50
−60
0.01
20
50 100 200
500 1k
2k
VCC = 12 V
V(RIPPLE) = 200 mVPP
RL = 8
Gain = 18 dB
−70
20
5k 10k 20k
100
f - Frequency - Hz
Figure 9.
Figure 10.
Efficiency
vs
Output Power
Output Power
vs
Load Impedance
10 k 20 k
21
90
8Ω
80
VCC = 18 V
19
4Ω
70
17
PO − Output Power − W
Efficiency − %
1k
f − Frequency − Hz
60
50
40
30
20
15
VCC = 15 V
13
11
VCC = 12 V
9
VCC = 12 V
7
10
0
0
2
4
6
8
10
PO − Output Power − W
Figure 11.
10
12
14
TA = 25°C,
10% THD Maximum
5
3.6 4
5
6
7
8
ZL − Load Impedance − Ω
Figure 12.
9
10
TPA3200D1
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SLOS442A – MAY 2005 – REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
Maximum Output Power
vs
Load Impedance
Maximum Output Power
vs
Load Impedance
21
21
TA = 60°C
TA = 45°C
19
VCC = 18 V
PO − Maximum Output Power − W
PO − Maximum Output Power − W
19
17
15
VCC = 15 V
13
11
9
VCC = 12 V
7
VCC = 18 V
15
VCC = 15 V
13
11
9
VCC = 12 V
7
5
3.6
4
5
6
7
8
ZL − Load Impedance − Ω
9
5
3.6
10
4
5
6
7
8
ZL − Load Impedance − Ω
Figure 13.
Figure 14.
De-emphasis Level
vs
Frequency
De-emphasis Error
vs
Frequency
0
9
10
0.5
fS = 44.1 kHz
−1
fS = 44.1 kHz
0.4
0.3
De-emphasis Error – dB
−2
De-emphasis Level – dB
17
−3
−4
−5
−6
−7
0.2
0.1
0.0
−0.1
−0.2
−8
−0.3
−9
−0.4
−10
−0.5
0
2
4
6
8
10
12
14
f – Frequency – kHz
Figure 15.
16
18
20
0
2
4
6
8
10
12
14
16
18
20
f – Frequency – kHz
Figure 16.
11
TPA3200D1
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SLOS442A – MAY 2005 – REVISED JULY 2005
APPLICATION INFORMATION
2
{
I S/RJ Clocks
& Data
BCK
SCLK
FORMAT
NC
VDD
10 mF
DATA
MUTE
LRCK
DEMP
DGND
DGND
VDD
ZERO
LR_SEL
DGND
VDD
Control
Inputs
Zero Flag Output
FLT1
DGND
0.1 mF
}
22 nF
FLT2
VCOM
VCC
GAIN0
VREF
GAIN1
BYPASS
10 mF
Gain Control
{
Shutdown Control
1 mF
1 mF
SHUTDOWN
COSC
PGND
ROSC
VCLAMP
AGND
NC
AGND
220 pF
120 kW
1 mF
51 W
0.22 mF
BSN
BSP
0.22 mF
VCC
22 mF
PVCC
PVCC
OUTN
OUTP
OUTN
OUTP
PGND
PGND
PGND
PGND
1 mF
51 W
VCC
1 mF
PGND and DGND
connected at
power supply
1 nF
Ferrite
Bead
1 nF
Ferrite
Bead
Ferrite
Bead
OUTN OUTP
Figure 17. Typical Application Circuit
12
PGND
DGND
TPA3200D1
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SLOS442A – MAY 2005 – REVISED JULY 2005
APPLICATION INFORMATION (continued)
SYSTEM CLOCK INPUT
The TPA3200D1 requires a system clock for operating the digital interpolation filters and multilevel delta-sigma
modulators. The system clock is applied at the SCLK input (pin 44). Table 1 shows examples of system clock
frequencies for common audio sampling rates.
Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase-jitter and noise. TI’s PLL170x family of multiclock generators is an excellent
choice for providing the TPA3200D1 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLE
FREQUENCY
(1)
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
1152fS
8 kHz
1.0240
1.5360
2.0480
3.0720
4.0960
6.1440
9.2160
16 kHz
2.0480
3.0720
4.0960
6.1440
8.1920
12.2880
18.4320
32 kHz
4.0960
6.1440
8.1920
12.2880
16.3840
24.5760
36.8640
44.1 kHz
5.6448
8.4672
11.2896
16.9344
22.5792
33.8688
(1)
48 kHz
6.1440
9.2160
12.2880
18.4320
24.5760
36.8640
(1)
88.2 kHz
11.2896
16.9344
22.5792
33.8688
45.1584
(1)
(1)
96 kHz
12.2880
18.4320
24.5760
36.8640
49.1520
(1)
(1)
192 kHz
24.5760
36.8640
49.1520
See
(1)
(1)
(1)
(1)
This system clock rate is not supported for the given sampling frequency.
t(SCKH)
H
2.0 V
System Clock (SCK)
0.8 V
L
t(SCKL)
t(SCY)
Figure 18. System Clock Input Timing
PARAMETERS
SYMBOL
System clock pulse duration, high
t(SCKH)
System clock pulse duration, low
t(SCKL)
System clock pulse cycle time
t(SCY)
(1)
MIN
TYP
MAX
UNITS
7
ns
7
See
(1)
1/128 fS, 1/256 fS, 1/384 fS, 1/512 fS, 1/768 fS, or 1/1152 fS
AUDIO SERIAL INTERFACE
The audio serial interface for the TPA3200D1 consists of a 3-wire synchronous serial port. It includes LRCK (pin
4), BCK (pin 1), and DATA (pin 3). BCK is the serial audio bit clock, and it is used to clock the serial data present
on DATA into the serial shift register of the audio interface. Serial data is clocked into the TPA3200D1 on the
rising edge of BCK. LRCK is the serial audio left/right word clock. It is used to latch serial data into the internal
registers of the serial audio interface.
Both LRCK and BCK should be synchronous to the system clock. Ideally, it is recommended that LRCK and BCK
be derived from the system clock input, SCK. LRCK is operated at the sampling frequency, fS. BCK can be
operated at 32, 48, or 64 times the sampling frequency for standard and left-justified formats. BCK can be
operated at 48 or 64 times the sampling frequency for the I2S format.
Internal operation of the TPA3200D1 is synchronized with LRCK. Accordingly, internal operation is held when the
sampling rate clock of LRCK is changed or when SCK and/or BCK is interrupted for a 3-bit clock cycle or longer.
If SCK, BCK, and LRCK are provided continuously after this held condition, the internal operation is
re-synchronized automatically in a period of less than 3/fS. External resetting is not required.
13
TPA3200D1
www.ti.com
SLOS442A – MAY 2005 – REVISED JULY 2005
AUDIO DATA FORMATS AND TIMING
The TPA3200D1 supports I2S and 16-bit-word right-justified. The data formats are shown in Figure 20. Data
formats are selected using the FORMAT pin on the TPA3200D1. All formats require binary 2s-complement,
MSB-first audio data. Figure 19 shows a detailed timing diagram for the serial audio interface.
1.4 V
LRCK
t(BCH)
t(BCL)
t(LB)
1.4 V
BCK
t(BCY)
t(BL)
1.4 V
DATA
t(DS)
t(DH)
Figure 19. Audio Interface Timing
PARAMETERS
SYMBOL
MIN
BCK pulse cycle time
t(BCY)
1/(32 fS), 1/(48 fS), 1/(64 fS) (1)
BCK high-level time
t(BCH)
35
BCK low-level time
t(BCL)
35
BCK rising edge to LRCK edge
t(BL)
10
LRCK falling edge to BCK rising edge
t(LB)
10
DATA setup time
t(DS)
10
DATA hold time
t(DH)
10
(1)
14
fS is the sampling frequency (e.g., 44.1 kHz, 48 kHz, 96 kHz, etc.).
TYP
MAX
UNITS
ns
TPA3200D1
www.ti.com
SLOS442A – MAY 2005 – REVISED JULY 2005
(1) 16-Bit-Word Right Justified
1/fS
LRCK
L-Channel
R-Channel
BCK
(= 32 fS, 48 fS, or 64 fS)
16-Bit Right-Justified, BCK = 48 fS or 64 fS
DATA
1
14 15 16
2
3
14 15 16
MSB
1
LSB
2
3
14 15 16
MSB
LSB
16-Bit Right-Justified, BCK = 32 fS
DATA
14 15 16
1
2
3
14 15 16
MSB
1
LSB
2
3
14 15 16
MSB
LSB
(2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
1/fS
LRCK
L-Channel
R-Channel
BCK
(= 48 fS or 64 fS)
DATA
1
2
3
MSB
N–2 N–1
LSB
N
1
2
3
N–2 N–1
MSB
LSB
N
1
2
Figure 20. Audio Data Input Formats
ZERO FLAG
ZERO (pin 39) is the L-channel and R-channel common zero flag pin. If the data for L-channel and R-channel
remains at a 0 level for 1024 sampling periods (or LRCK clock periods), the ZERO flag output is set to a logic 1
state.
The ZERO-pin output can be inverted using a standard logic gate or transistor, and connected to the
SHUTDOWN terminal (pin 13). This places the TPA3200D1 into a low-current state, conserving power, and
disables the switching outputs.
15
TPA3200D1
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SLOS442A – MAY 2005 – REVISED JULY 2005
REGISTER CONTROL
The digital functions of the TPA3200D1 are controlled by 4 terminals. Table 2 shows selectable data formats,
Table 3 shows de-emphasis control, Table 4 shows mute control, and Table 5 shows channel-output select.
Table 2. Data Format Select
FMT (PIN 43)
DATA FORMAT
LOW
16- to 24-bit, I2S format
HIGH
16-bit right-justified
Table 3. De-Emphasis Control
DEMP (PIN 41 )
DE-EMPHASIS FUNCTION
LOW
44.1 kHz de-emphasis OFF
HIGH
44.1 kHz de-emphasis ON
Table 4. Mute Control
MUTE (PIN 42 )
MUTE
LOW
Mute OFF
HIGH
Mute ON
Table 5. Channel Output Select
ACTIVE CHANNEL (1)
LR_SEL (PIN 7 )
(1)
LOW
Right
HIGH
Left
A digital data stream consists of two channels of data. In an I2S or
right-justified data stream, the left-channel data precedes the
right-channel data (See Figure 20). The LR_SEL input selects the
channel to send to the mono output.
OVERSAMPLING RATE CONTROL
The TPA3200D1 automatically controls the oversampling rate of the delta-sigma D/A converters with the system
clock rate. The oversampling rate is set to 64× oversampling with every system clock and sampling frequency.
VCOM OUTPUT
One unbuffered common-mode voltage output pin, VCOM (pin 10) is brought out for decoupling purposes. This
pin is nominally biased to a dc voltage level equal to 0.5 × VDD. This pin cannot be used to bias external circuits.
16
TPA3200D1
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SLOS442A – MAY 2005 – REVISED JULY 2005
CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3200D1.
Traditional Class-D Modulation Scheme
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore,
the differential pre-filtered output varies between positive and negative VCC, where filtered 50% duty cycle yields
0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 31. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,
causing high loss, thus causing a high supply current.
OUTP
OUTN
+12 V
Differential Voltage
Across Load
0V
−12 V
Current
Figure 21. Traditional Class-D Modulation Scheme’s Output Voltage and Current Waveforms Into an
Inductive Load With No Input
17
TPA3200D1
www.ti.com
SLOS442A – MAY 2005 – REVISED JULY 2005
TPA3200D1 Modulation Scheme
The TPA3200D1 uses a modulation scheme that still has each output switching from ground to VCC. However,
OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50%
and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is
greater than 50% for negative output voltages. The voltage across the load is 0 V throughout most of the
switching period, greatly reducing the switching current, which reduces any I2R losses in the load. (See
Figure 22.)
OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
+12 V
0V
−12 V
Current
OUTP
OUTN
Differential
Voltage
Output > 0 V
+12 V
0V
Across
Load
−12 V
Current
Figure 22. The TPA3200D1 Output Voltage and Current Waveforms Into an Inductive Load
18
TPA3200D1
www.ti.com
SLOS442A – MAY 2005 – REVISED JULY 2005
Maximum Allowable Output Power (Safe Operating Area)
The TPA3200D1 can drive load impedances as low as 3.6 Ω from power supply voltages ranging from 8 V to 18
V. To prevent device failure, however, the output power of the TPA3200D1 must be limited. Figure 23 shows the
maximum allowable output power versus load impedance for three power supply voltages at an ambient
temperature of 25°C.
MAXIMUM OUTPUT POWER
vs
LOAD IMPEDANCE
21
PO − Output Power − W
19
VCC = 18 V
17
15
VCC = 15 V
13
11
VCC = 12 V
9
7
TA = 25°C,
10% THD Maximum
5
3.6 4
5
6
7
8
9
ZL − Load Impedance − Ω
10
Figure 23. Output Power
Driving The Output Into Clipping
The output of the TPA3200D1 may be driven into clipping to attain a higher output power than is possible with no
distortion. Clipping is typically quantified by a THD measurement of 10%. The amount of additional power into
the load may be calculated with Equation 1.
P O(10% THD) P O(1% THD) 1.25
(1)
For example, consider an application in which the TPA3200D1 drives an 8-Ω speaker from an 18-V power
supply. The maximum output power with no distortion (less than 1% THD) is 16 W, which corresponds to a
maximum peak output voltage of 16 V. For the same output voltage level driven into clipping (10% THD), the
output power is increased to 20 W.
Output Filter Considerations
A ferrite bead filter (shown in Figure 24) should be used in order to pass FCC and/or CE radiated emissions
specifications and if a frequency sensitive circuit operating higher than 1 MHz is nearby. The ferrite filter reduces
EMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selecting
a ferrite bead, choose one with high impedance at high frequencies, but very low impedance at low frequencies.
Use an additional LC output filter if there are low frequency (
