TPA321
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SLOS312C – JUNE 2000 – REVISED JUNE 2004
350-mW MONO AUDIO POWER AMPLIFIER WITH DIFFERENTIAL INPUTS
•
•
•
•
•
•
Fully Specified for 3.3-V and 5-V Operation
Wide Power Supply Compatibility
2.5 V – 5.5 V
Output Power for RL = 8 Ω
– 350 mW at VDD = 5 V
– 250 mW at VDD = 3.3 V
Ultralow Supply Current in Shutdown
Mode . . . 0.15 µA
Thermal and Short-Circuit Protection
Surface-Mount Packaging
– SOIC
– PowerPAD™ MSOP
D OR DGN PACKAGE
(TOP VIEW)
SHUTDOWN
BYPASS
IN+
IN-
1
8
2
7
3
6
4
5
VOGND
VDD
VO+
DESCRIPTION
The TPA321 is a bridge-tied load (BTL) audio power amplifier developed especially for low-voltage applications
where internal speakers are required. Operating with a 3.3-V supply, the TPA321 can deliver 250 mW of
continuous power into a BTL 8-Ω load at less than 1% THD+N throughout voice band frequencies. Although this
device is characterized out to 20 kHz, its operation was optimized for narrower band applications such as cellular
communications. The BTL configuration eliminates the need for external coupling capacitors on the output in
most applications, which is particularly important for small battery-powered equipment. This device features a
shutdown mode for power-sensitive applications with a quiescent current of 0.15 µA during shutdown. The
TPA321 is available in an 8-pin SOIC surface-mount package and the surface-mount PowerPAD™ MSOP, which
reduces board space by 50% and height by 40%.
VDD 6
VDD
RF
CS
VDD/2
Audio
Input
RI
CI
4
IN -
3
IN+
2
BYPASS
1 µF
-
VO+ 5
+
CB
0.1 µF
-
VO-
+
8
350 mW
7
GND
From System Control
1
SHUTDOWN
Bias
Control
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2004, Texas Instruments Incorporated
TPA321
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SLOS312C – JUNE 2000 – REVISED JUNE 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE (1) (D)
MSOP (1) (DGN)
MSOP
SYMBOLIZATION
TPA321D
TPA321DGN
AJB
–40°C to 85°C
(1)
The D and DGN packages are available taped and reeled. To order a taped and reeled part, add the
suffix R to the part number (e.g., TPA321DR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VDD
Supply voltage
VI
Input voltage
6V
–0.3 V to VDD +0.3 V
Continuous total power dissipation
Internally limited (see Dissipation Rating Table)
TA
Operating free-air temperature range
–40°C to 85°C
TJ
Operating junction temperature range
–40°C to 150°C
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
(1)
PACKAGE
TA ≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
D
725 mW
5.8 mW/°C
464 mW
377 mW
DGN
2.14 W (1)
17.1 mW/°C
1.37 W
1.11 W
See the Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report
(literature number SLMA002), for more information on the PowerPAD™ package. The thermal data
was measured on a PCB layout based on the information in the section entitled Texas Instruments
Recommended Board for PowerPAD on page 33 of the before mentioned document.
RECOMMENDED OPERATING CONDITIONS
VDD
Supply voltage
VIH
High-level voltage
SHUTDOWN
VIL
Low-level voltage
SHUTDOWN
TA
Operating free-air temperature
2
MIN
MAX
2.5
5.5
0.9 VDD
–40
UNIT
V
V
0.1 VDD
V
85
°C
TPA321
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SLOS312C – JUNE 2000 – REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 3.3 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
|VOO|
Output offset voltage (measured differentially)
SHUTDOWN = 0 V, RL = 8 Ω, RF = 10 kΩ
PSRR
Power supply rejection ratio
VDD = 3.2 V to 3.4 V
85
IDD
Supply current (see Figure 3)
SHUTDOWN = 0 V, RF = 10 kΩ
IDD(SD)
Supply current, shutdown mode (see Figure 4)
SHUTDOWN = VDD, RF = 10 kΩ
|IIH|
High-level input current
SHUTDOWN, VDD = 3.3 V, VI = 3.3 V
|IIL|
Low-level input current
SHUTDOWN, VDD = 3.3 V, VI = 0 V
5
UNIT
20
mV
0.7
1.5
mA
0.15
5
µA
1
µA
1
µA
dB
OPERATING CHARACTERISTICS
VDD = 3.3 V, TA = 25°C, RL = 8 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
250
mW
PO
Output power (1)
THD = 0.5%,
See Figure 9
THD + N
Total harmonic distortion plus noise
PO = 250 mW,
AV = -2 V/V,
f = 20 Hz to 4 kHz,
See Figure 7
Maximum output power bandwidth
AV = -2 V/V, THD = 3%, See Figure 7
10
kHz
Unity-gain bandwidth
Open loop,
1.4
MHz
Supply ripple rejection ratio
f = 1 kHz, CB = 1 µF, See Figure 2
71
dB
Noise output voltage
AV = –1 V/V,
RL = 32 Ω ,
15
µV(rms)
B1
Vn
(1)
1.3%
See Figure 15
CB = 0.1 µF,
See Figure 19
Output power is measured at the output terminals of the device at f = 1 kHz.
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
|VOO|
Output offset voltage (measured differentially)
SHUTDOWN = 0 V, RL = 8 Ω, RF = 10 kΩ
PSRR
Power supply rejection ratio
VDD = 4.9 V to 5.1 V
78
IDD
Supply current (see Figure 3)
SHUTDOWN = 0 V, RF = 10 kΩ
IDD(SD)
Supply current, shutdown mode (see Figure 4)
SHUTDOWN = VDD, RF = 10 kΩ
|IIH|
High-level input current
|IIL|
Low-level input current
5
UNIT
20
mV
0.7
1.5
mA
0.15
5
µA
SHUTDOWN, VDD = 5.5 V, VI = VDD
1
µA
SHUTDOWN, VDD = 5.5 V, VI = 0 V
1
µA
dB
OPERATING CHARACTERISTICS
VDD = 5 V, TA = 25°C, RL = 8 Ω
TYP MAX
UNIT
PO
Output power
PARAMETER
THD = 0.5%,
See Figure 13
700
mW
THD + N
Total harmonic distortion plus noise
PO = 350 mW,
AV = –2 V/V,
f = 20 Hz to 4 kHz, See
Figure 11
1%
Maximum output power bandwidth
AV = –2 V/V, THD = 2%, See Figure 11
10
kHz
Unity-gain bandwidth
Open loop,
1.4
MHz
Supply ripple rejection ratio
f = 1 kHz, CB = 1 µF, See Figure 2
65
dB
Noise output voltage
AV = -1 V/V,
RL = 32 Ω ,
15
µV(rms)
B1
Vn
TEST CONDITIONS
See Figure 16
CB = 0.1 µF,
See Figure 20
MIN
3
TPA321
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SLOS312C – JUNE 2000 – REVISED JUNE 2004
Terminal Functions
TERMINAL
NAME
I/O
NO.
I
DESCRIPTION
BYPASS is the tap to the voltage divider for internal mid-supply bias. This terminal should be connected
to a 0.1-µF to 1-µF capacitor when used as an audio amplifier.
BYPASS
2
GND
7
IN-
4
I
IN- is the inverting input. IN- is typically used as the audio input terminal.
IN+
3
I
IN+ is the noninverting input. IN+ is typically tied to the BYPASS terminal for SE operations.
SHUTDOWN
1
I
SHUTDOWN places the entire device in shutdown mode when held high (IDD ~ 0.15 µA).
VDD
6
VO+
5
O
VO+ is the positive BTL output.
VO-
8
O
VO- is the negative BTL output.
GND is the ground connection.
VDD is the supply voltage terminal.
PARAMETER MEASUREMENT INFORMATION
VDD 6
RF
Audio
Input
RI
CI
4
IN -
3
IN+
2
BYPASS
1 µF
-
VO+ 5
+
RL = 8 Ω
CB
0.1 µF
-
VO-
+
SHUTDOWN
Bias
Control
Figure 1. Test Circuit
4
8
7
GND
1
VDD
CS
VDD/2
TPA321
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SLOS312C – JUNE 2000 – REVISED JUNE 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
kSVR
Supply voltage rejection ratio
vs Frequency
IDD
Supply current
vs Supply voltage
3, 4
PO
Output power
vs Supply voltage
5
THD+N
2
vs Load resistance
Total harmonic distortion plus noise
6
vs Frequency
7, 8, 11, 12
vs Output power
9, 10, 13, 14
Open-loop gain and phase
vs Frequency
15, 16
Closed-loop gain and phase
vs Frequency
17, 18
Vn
Output noise voltage
vs Frequency
19, 20
PD
Power dissipation
vs Output power
21, 22
SUPPLY VOLTAGE REJECTION RATIO
vs
FREQUENCY
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
−10
1.1
RL = 8 Ω
CB = 1 µF
SHUTDOWN = 0 V
RF = 10 kΩ
0.9
−20
I DD − Supply Current − mA
kSVR − Supply Voltage Rejection Ratio − dB
0
−30
−40
−50
VDD = 5 V
−60
−70
VDD = 3.3 V
−80
0.7
0.5
0.3
0.1
−90
−100
20
100
1k
f − Frequency − Hz
Figure 2.
10 k 20 k
−0.1
2
3
4
5
6
VDD − Supply Voltage − V
Figure 3.
5
TPA321
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SLOS312C – JUNE 2000 – REVISED JUNE 2004
SUPPLY CURRENT (SHUTDOWN)
vs
SUPPLY VOLTAGE
0.5
SHUTDOWN = VDD
RF = 10 kΩ
I DD(SD)− Supply Current − µ A
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
2
2.5
3
3.5
4
4.5
5
5.5
5
5.5
VDD − Supply Voltage − V
Figure 4.
OUTPUT POWER
vs
SUPPLY VOLTAGE
1000
THD+N 1%
PO − Output Power − mW
800
600
RL = 8 Ω
400
RL = 32 Ω
200
0
2
2.5
3
3.5
4
4.5
VDD − Supply Voltage − V
Figure 5.
6
TPA321
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SLOS312C – JUNE 2000 – REVISED JUNE 2004
OUTPUT POWER
vs
LOAD RESISTANCE
800
THD+N = 1%
700
PO − Output Power − mW
600
VDD = 5 V
500
400
300
VDD = 3.3 V
200
100
0
8
16
24
32
40
48
56
64
RL − Load Resistance − Ω
Figure 6.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
VDD = 3.3 V
PO = 250 mW
RL = 8 Ω
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
10
AV = −20 V/V
1
AV =− 10 V/V
AV = −2 V/V
0.1
0.01
20
100
1k
10k
20k
VDD = 3.3 V
RL = 8 Ω
AV = −2 V/V
PO = 50 mW
1
PO = 125 mW
0.1
PO = 250 mW
0.01
20
100
1k
f − Frequency − Hz
f − Frequency − Hz
Figure 7.
Figure 8.
10k
20k
7
TPA321
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SLOS312C – JUNE 2000 – REVISED JUNE 2004
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
10
VDD = 3.3 V
f = 1 kHz
AV = −2 V/V
1
RL = 8 Ω
0.1
0.01
0.04
0.1
0.16
0.22
0.28
0.34
f = 20 kHz
f = 10 kHz
1
f = 1 kHz
0.1
f = 20 Hz
0.01
0.01
0.4
0.1
Figure 9.
Figure 10.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
VDD = 5 V
PO = 350 mW
RL = 8 Ω
THD+N −Total Harmonic Distortion + Noise − %
THD+N −Total Harmonic Distortion + Noise − %
10
8
1
PO − Output Power − W
PO − Output Power − W
AV = −20 V/V
1
AV =− 10 V/V
AV = −2 V/V
0.1
0.01
20
VDD = 3.3 V
RL = 8 Ω
AV = −2 V/V
100
1k
10k
20k
VDD = 5 V
RL = 8 Ω
AV = −2 V/V
PO = 50 mW
1
PO = 175 mW
0.1
PO = 350 mW
0.01
20
100
1k
f − Frequency − Hz
f − Frequency − Hz
Figure 11.
Figure 12.
10k
20k
TPA321
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SLOS312C – JUNE 2000 – REVISED JUNE 2004
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
THD+N −Total Harmonic Distortion + Noise − %
VDD = 5 V
f = 1 kHz
AV = −2 V/V
1
RL = 8 Ω
0.1
0.25
0.40
0.55
0.70
0.85
f = 20 kHz
f = 10 kHz
1
f = 1 kHz
0.1
f = 20 Hz
VDD = 5 V
RL = 8 Ω
AV = −2 V/V
0.01
0.01
1
0.1
1
PO − Output Power − W
PO − Output Power − W
Figure 13.
Figure 14.
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
40
180
Phase
30
VDD = 3.3 V
RL = Open
120
Gain
20
60
10
0
0
Phase − °
0.01
0.1
Open-Loop Gain − dB
THD+N −Total Harmonic Distortion + Noise − %
10
−60
−10
−120
−20
−30
−180
1
101
102
103
104
f − Frequency − kHz
Figure 15.
9
TPA321
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SLOS312C – JUNE 2000 – REVISED JUNE 2004
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
40
180
VDD = 5 V
RL = Open
Phase
30
120
20
60
10
0
0
Phase − °
Open-Loop Gain − dB
Gain
−60
−10
−120
−20
−30
−180
1
101
102
103
104
f − Frequency − kHz
Figure 16.
CLOSED-LOOP GAIN AND PHASE
vs
FREQUENCY
1
180
Phase
0.75
170
0.25
0
160
Gain
−0.25
150
−0.5
−0.75
140
−1
−1.25
−1.5
−1.75
−2
101
VDD = 3.3 V
RL = 8 Ω
PO = 0.25 W
CI =1 µF
130
120
102
103
104
f − Frequency − Hz
Figure 17.
10
105
106
Phase − °
Closed-Loop Gain − dB
0.5
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SLOS312C – JUNE 2000 – REVISED JUNE 2004
CLOSED-LOOP GAIN AND PHASE
vs
FREQUENCY
1
180
Phase
0.75
170
0.25
0
160
Gain
−0.25
150
−0.5
−0.75
Phase − °
Closed-Loop Gain − dB
0.5
140
−1
VDD = 5 V
RL = 8 Ω
PO = 0.35 W
CI =1 µF
−1.25
−1.5
−1.75
−2
101
102
130
103
104
105
120
106
f − Frequency − Hz
Figure 18.
OUTPUT NOISE VOLTAGE
vs
FREQUENCY
100
VDD = 3.3 V
BW = 22 Hz to 22 kHz
RL = 32 Ω
CB =0.1 µF
AV = −1 V/V
Vn − Output Noise Voltage − µ V(rms)
Vn − Output Noise Voltage − µ V(rms)
100
OUTPUT NOISE VOLTAGE
vs
FREQUENCY
VO BTL
10
VO+
1
20
100
1k
f − Frequency − Hz
Figure 19.
10 k
20 k
VDD = 5 V
BW = 22 Hz to 22 kHz
RL = 32 Ω
CB =0.1 µF
AV = −1 V/V
VO BTL
10
VO+
1
20
100
1k
10 k
20 k
f − Frequency − Hz
Figure 20.
11
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SLOS312C – JUNE 2000 – REVISED JUNE 2004
POWER DISSIPATION
vs
OUTPUT POWER
300
720
270
640
PD − Power Dissipation − mW
PD − Power Dissipation − mW
POWER DISSIPATION
vs
OUTPUT POWER
240
210
180
150
VDD = 3.3 V
RL = 8 Ω
120
480
400
320
VDD = 5 V
RL = 8 Ω
240
90
160
0
100
200
300
PO − Output Power − mW
Figure 21.
12
560
400
0
200
400
600
800
PO − Output Power − mW
Figure 22.
1000
1200
TPA321
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SLOS312C – JUNE 2000 – REVISED JUNE 2004
APPLICATION INFORMATION
BRIDGE-TIED LOAD
Figure 23 shows a linear audio power amplifier (APA) in a BTL configuration. The TPA321 BTL amplifier consists
of two linear amplifiers driving both ends of the load. There are several potential benefits to this differential drive
configuration but power to the load should be initially considered. The differential drive to the speaker means that
as one side is slewing up, the other side is slewing down, and vice versa. This, in effect, doubles the voltage
swing on the load as compared to a ground-referenced load. Plugging 2 × VO(PP) into the power equation, where
voltage is squared, yields 4× the output power from the same supply rail and load impedance (see Equation 1).
VO(PP)
V (RMS)
2 2
Power
V (RMS)
2
RL
(1)
VDD
VO(PP)
RL
2x VO(PP)
VDD
-VO(PP)
Figure 23. Bridge-Tied Load Configuration
In a typical portable handheld equipment sound channel operating at 3.3 V, bridging raises the power into an 8-Ω
speaker from a single-ended (SE, ground reference) limit of 62.5 mW to 250 mW. In sound power that is a 6-dB
improvement, which is loudness that can be heard. In addition to increased power, there are frequency response
concerns. Consider the single-supply SE configuration shown in Figure 24. A coupling capacitor is required to
block the dc offset voltage from reaching the load. These capacitors can be quite large (approximately 33 µF to
1000 µF) so they tend to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of
limiting low-frequency performance of the system. This frequency limiting effect is due to the high pass filter
network created with the speaker impedance and the coupling capacitance and is calculated with Equation 2.
1
fc
2 R L CC
(2)
For example, a 68-µF capacitor with an 8-Ω speaker would attenuate low frequencies below 293 Hz. The BTL
configuration cancels the dc offsets, eliminating the need for the blocking capacitors. Low-frequency performance
is then limited only by the input network and speaker response. Cost and PCB space are also minimized by
eliminating the bulky coupling capacitor.
13
TPA321
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SLOS312C – JUNE 2000 – REVISED JUNE 2004
APPLICATION INFORMATION (continued)
VDD
-3 dB
VO(PP)
CC
RL
VO(PP)
fc
Figure 24. Single-Ended Configuration and Frequency Response
Increasing power to the load does carry a penalty of increased internal power dissipation. The increased
dissipation is understandable considering that the BTL configuration produces 4× the output power of a SE
configuration. Internal dissipation versus output power is discussed further in the thermal considerations section.
BTL AMPLIFIER EFFICIENCY
Linear amplifiers are inefficient. The primary cause of these inefficiencies is voltage drop across the output stage
transistors. There are two components of the internal voltage drop. One is the headroom or dc voltage drop that
varies inversely to output power. The second component is due to the sine-wave nature of the output. The total
voltage drop can be calculated by subtracting the RMS value of the output voltage from VDD. The internal voltage
drop multiplied by the RMS value of the supply current, IDD(RMS), determines the internal power dissipation of the
amplifier.
An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power
supply to the power delivered to the load. To accurately calculate the RMS values of power in the load and in the
amplifier, the current and voltage waveform shapes must first be understood (see Figure 25).
VO
IDD
IDD(RMS)
VL(RMS)
Figure 25. Voltage and Current Waveforms for BTL Amplifiers
Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are
different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified
shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different.
Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which
supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform.
The following equations are the basis for calculating amplifier efficiency.
14
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APPLICATION INFORMATION (continued)
P
Efficiency
where
PL
P
V
L RMS
R
L
L
SUP
2
Vp
2
2R
L
V
V
P
L RMS
2
P SUP VDD I
DD RMS
I
DDRMS
V DD 2VP
RL
2V P
RL
(3)
Efficiency of a BTL configuration
VP
2V DD
P LR L
2
12
2V DD
(4)
Table 1 employs Equation 4 to calculate efficiencies for three different output power levels. The efficiency of the
amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a
nearly flat internal power dissipation over the normal operating range. The internal dissipation at full output power
is less than in the half-power range. Calculating the efficiency for a specific system is the key to proper power
supply design.
Table 1. Efficiency vs Output Power in 3.3-V 8-Ω BTL Systems
(1)
OUTPUT POWER
(W)
EFFICIENCY
(%)
PEAK-to-PEAK
VOLTAGE
(V)
INTERNAL
DISSIPATION
(W)
0.125
33.6
1.41
0.26
0.25
47.6
2.00
0.29
0.375
58.3
2.45 (1)
0.28
High-peak voltage values cause the THD to increase.
A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the
efficiency equation to utmost advantage when possible. Note that in Equation 4, VDD is in the denominator. This
indicates that as VDD goes down, efficiency goes up.
15
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APPLICATION SCHEMATICS
Figure 26 is a schematic diagram of a typical handheld audio application circuit, configured for a gain of –10 V/V.
VDD 6
RF
50 kΩ
CF
5 pF
Audio
Input
CI
RI
0.47 µF 10 kΩ
4
IN -
3
IN+
2
BYPASS
VDD
CS
VDD/2
1 µF
-
VO+ 5
+
CB
2.2 µF
-
VO-
+
8
350 mW
7
GND
1
From System Control
SHUTDOWN
Bias
Control
Figure 26. TPA321 Application Circuit
Figure 27 is a schematic diagram of a typical handheld audio application circuit, configured for a gain of –10 V/V
with a differential input.
VDD 6
RF
50 kΩ
Audio
Input-
RI
10 kΩ
CI
RI
10 kΩ
Audio
Input+
VDD/2
4
IN -
3
IN+
1 µF
-
VO+ 5
+
RF
50 kΩ
2
CI
VDD
CS
BYPASS
CB
-
2.2 µF
VO-
+
8
700 mW
7
GND
From System Control
1
SHUTDOWN
Bias
Control
Figure 27. TPA321 Application Circuit With Differential Input
It is important to note that using the additional RF resistor connected between IN+ and BYPASS causes VDD/2 to
shift slightly, which could influence the THD+N performance of the amplifier. Although an additional external
operational amplifier could be used to buffer BYPASS from RF, tests in the lab have shown that the THD+N
performance is only minimally affected by operating in the fully differential mode as shown in Figure 27. The
following sections discuss the selection of the components used in Figure 26 and Figure 27.
16
TPA321
www.ti.com
SLOS312C – JUNE 2000 – REVISED JUNE 2004
COMPONENT SELECTION
Gain Setting Resistors, RF and RI
The gain for each audio input of the TPA321 is set by resistors RF and RI according to Equation 5 for BTL mode.
R
F
BTL Gain A V 2
R
I
(5)
BTL mode operation brings about the factor 2 in the gain equation due to the inverting amplifier mirroring the
voltage swing across the load. Given that the TPA321 is a MOS amplifier, the input impedance is high;
consequently, input leakage currents are not generally a concern, although noise in the circuit increases as the
value of RF increases. In addition, a certain range of RF values is required for proper start-up operation of the
amplifier. Taken together, it is recommended that the effective impedance seen by the inverting node of the
amplifier be set between 5 kΩ and 20 kΩ. The effective impedance is calculated in Equation 6.
R R
F I
Effective Impedance
R R
F
I
(6)
As an example, consider an input resistance of 10 kΩ and a feedback resistor of 50 kΩ. The BTL gain of the
amplifier would be –10 V/V, and the effective impedance at the inverting terminal would be 8.3 kΩ, which is well
within the recommended range.
For high-performance applications metal film resistors are recommended because they tend to have lower noise
levels than carbon resistors. For values of RF above 50 kΩ, the amplifier tends to become unstable due to a pole
formed from RF and the inherent input capacitance of the MOS input structure. For this reason, place a small
compensation capacitor (CF) of approximately 5 pF in parallel with RF when RF is greater than 50 kΩ. In effect,
this creates a low-pass filter network with the cutoff frequency defined in Equation 7.
−3 dB
fc
1
2 R C
F F
fc
(7)
For example, if RF is 100 kΩ and CF is 5 pF then fc is 318 kHz, which is well outside of audio range.
Input Capacitor, CI
In the typical application, input capacitor CI is required to allow the amplifier to bias the input signal to the proper
dc level for optimum operation. In this case, CI and RI form a high-pass filter with the corner frequency
determined in Equation 8.
17
TPA321
www.ti.com
SLOS312C – JUNE 2000 – REVISED JUNE 2004
−3 dB
fc
1
2 R C
I I
fc
(8)
The value of CI is important to consider as it directly affects the bass (low-frequency) performance of the circuit.
Consider the example where RI is 10 kΩ and the specification calls for a flat bass response down to 40 Hz.
Equation 8 is reconfigured as Equation 9.
1
C
I
2 R f c
I
(9)
In this example, CI is 0.40 µF, so one would likely choose a value in the range of 0.47 µF to 1 µF. A further
consideration for this capacitor is the leakage path from the input source through the input network (RI, CI) and
the feedback resistor (RF) to the load. This leakage current creates a dc offset voltage at the input to the amplifier
that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or
ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor
should face the amplifier input in most applications, as the dc level there is held at VDD/2, which is likely higher
than the source dc level. It is important to confirm the capacitor polarity in the application.
Power Supply Decoupling, CS
The TPA321 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents
oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by
using two capacitors of different types that target different types of noise on the power supply leads. For higher
frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic
capacitor, typically 0.1 µF, placed as close as possible to the device VDD lead, works best. For filtering
lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the audio
power amplifier is recommended.
Midrail Bypass Capacitor, CB
The midrail bypass capacitor, CB, is the most critical capacitor and serves several important functions. During
start-up or recovery from shutdown mode, CB determines the rate at which the amplifier starts up. The second
function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This
noise is from the midrail generation circuit internal to the amplifier, which appears as degraded PSRR and THD +
N. The capacitor is fed from a 250-kΩ source inside the amplifier. To keep the start-up pop as low as possible,
the relationship shown in Equation 10 should be maintained, which insures the input capacitor is fully charged
before the bypass capacitor is fully charged and the amplifier starts up.
10
1
CB 250 kΩ RF RI CI
(10)
As an example, consider a circuit where CB is 2.2 µF, CI is 0.47 µF, RF is 50 kΩ, and RI is 10 kΩ. Inserting these
values into the Equation 10 we get:
18.2 ≤ 35.5
which satisfies the rule. Bypass capacitor, CB, values of 2.2-µF to 1-µF ceramic or tantalum low-ESR capacitors
are recommended for the best THD and noise performance.
18
TPA321
www.ti.com
SLOS312C – JUNE 2000 – REVISED JUNE 2004
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application. A real (as opposed to ideal) capacitor can be
modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the
beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the
real capacitor behaves like an ideal capacitor.
5-V VERSUS 3.3-V OPERATION
The TPA321 operates over a supply range of 2.5 V to 5.5 V. This data sheet provides full specifications for 5-V
and 3.3-V operation, as these are considered to be the two most common standard voltages. There are no
special considerations for 3.3-V versus 5-V operation with respect to supply bypassing, gain setting, or stability.
The most important consideration is that of output power. Each amplifier in TPA321 can produce a maximum
voltage swing of VDD –1 V. This means, for 3.3-V operation, clipping starts to occur when VO(PP) = 2.3 V as
opposed to VO(PP) = 4 V at 5 V. The reduced voltage swing subsequently reduces maximum output power into an
8-Ω load before distortion becomes significant.
Operation from 3.3-V supplies, as can be shown from the efficiency formula in Equation 4, consumes
approximately two-thirds the supply power for a given output-power level than operation from 5-V supplies.
HEADROOM AND THERMAL CONSIDERATIONS
Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions.
A typical music CD requires 12 dB to 15 dB of dynamic headroom to pass the loudest portions without distortion
as compared with the average power output. The TPA321 data sheet shows that when the TPA321 is operating
from a 5-V supply into a 8-Ω speaker, 350 mW peaks are available. Converting watts to dB:
P
P
10Log W 10Log 350 mW –4.6 dB
dB
P
1W
ref
Subtracting the headroom restriction to obtain the average listening level without distortion yields:
4.6 dB – 15 dB = –19.6 dB (15-dB headroom)
4.6 dB – 12 dB = –16.6 dB (12-dB headroom)
4.6 dB – 9 dB = –13.6 dB (9-dB headroom)
4.6 dB – 6 dB = –10.6 dB (6-dB headroom)
4.6 dB – 3 dB = –7.6 dB (3-dB headroom)
Converting dB back into watts:
PW = 10PdB/10× Pref
= 11 mW (15 dB headroom)
= 22 mW (12-dB headroom)
= 44 mW (9-dB headroom)
= 88 mW (6-dB headroom)
= 175 mW (3-dB headroom)
This is valuable information to consider when attempting to estimate the heat dissipation requirements for the
amplifier system. Comparing the absolute worst case, which is 350 mW of continuous power output with 0 dB of
headroom, against 12-dB and 15-dB applications drastically affects maximum ambient temperature ratings for
the system. Using the power dissipation curves for a 5-V, 8-Ω system, the internal dissipation in the TPA321 and
maximum ambient temperatures is shown in Table 2.
19
TPA321
www.ti.com
SLOS312C – JUNE 2000 – REVISED JUNE 2004
Table 2. TPA321 Power Rating, 5-V, 8-Ω BTL
MAXIMUM AMBIENT
TEMPERATURE
PEAK OUTPUT
POWER
(mW)
AVERAGE OUTPUT
POWER
POWER DISSIPATION
(mW)
350
350 mW
600
46°C
350
175 mW (3 dB)
500
64°C
350
88 mW (6 dB)
380
85°C
350
44 mW (9 dB)
300
98°C
350
22 mW (12 dB)
200
115°C
350
11 mW (15 dB)
180
119°C
0 CFM
Table 2 shows that the TPA321 can be used to its full 350-mW rating without any heat sinking in still air up to
46°C.
20
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPA321D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPA321
TPA321DGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AJB
TPA321DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AJB
TPA321DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPA321
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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